1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
4 *
5 */
6
7 #include <asm/io.h>
8 #include <asm/u-boot.h>
9 #include <asm/utils.h>
10 #include <common.h>
11 #include <debug_uart.h>
12 #include <image.h>
13 #include <spl.h>
14 #include <asm/arch/clock_manager.h>
15 #include <asm/arch/firewall_s10.h>
16 #include <asm/arch/mailbox_s10.h>
17 #include <asm/arch/reset_manager.h>
18 #include <asm/arch/sdram_s10.h>
19 #include <asm/arch/system_manager.h>
20 #include <watchdog.h>
21
22 DECLARE_GLOBAL_DATA_PTR;
23
24 static struct socfpga_system_manager *sysmgr_regs =
25 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
26
spl_boot_device(void)27 u32 spl_boot_device(void)
28 {
29 /* TODO: Get from SDM or handoff */
30 return BOOT_DEVICE_MMC1;
31 }
32
33 #ifdef CONFIG_SPL_MMC_SUPPORT
spl_boot_mode(const u32 boot_device)34 u32 spl_boot_mode(const u32 boot_device)
35 {
36 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
37 return MMCSD_MODE_FS;
38 #else
39 return MMCSD_MODE_RAW;
40 #endif
41 }
42 #endif
43
spl_disable_firewall_l4_per(void)44 void spl_disable_firewall_l4_per(void)
45 {
46 const struct socfpga_firwall_l4_per *firwall_l4_per_base =
47 (struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;
48 u32 i;
49 const u32 *addr[] = {
50 &firwall_l4_per_base->nand,
51 &firwall_l4_per_base->nand_data,
52 &firwall_l4_per_base->usb0,
53 &firwall_l4_per_base->usb1,
54 &firwall_l4_per_base->spim0,
55 &firwall_l4_per_base->spim1,
56 &firwall_l4_per_base->emac0,
57 &firwall_l4_per_base->emac1,
58 &firwall_l4_per_base->emac2,
59 &firwall_l4_per_base->sdmmc,
60 &firwall_l4_per_base->gpio0,
61 &firwall_l4_per_base->gpio1,
62 &firwall_l4_per_base->i2c0,
63 &firwall_l4_per_base->i2c1,
64 &firwall_l4_per_base->i2c2,
65 &firwall_l4_per_base->i2c3,
66 &firwall_l4_per_base->i2c4,
67 &firwall_l4_per_base->timer0,
68 &firwall_l4_per_base->timer1,
69 &firwall_l4_per_base->uart0,
70 &firwall_l4_per_base->uart1
71 };
72
73 /*
74 * The following lines of code will enable non-secure access
75 * to nand, usb, spi, emac, sdmmc, gpio, i2c, timers and uart. This
76 * is needed as most OS run in non-secure mode. Thus we need to
77 * enable non-secure access to these peripherals in order for the
78 * OS to use these peripherals.
79 */
80 for (i = 0; i < ARRAY_SIZE(addr); i++)
81 writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
82 }
83
spl_disable_firewall_l4_sys(void)84 void spl_disable_firewall_l4_sys(void)
85 {
86 const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =
87 (struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;
88 u32 i;
89 const u32 *addr[] = {
90 &firwall_l4_sys_base->dma_ecc,
91 &firwall_l4_sys_base->emac0rx_ecc,
92 &firwall_l4_sys_base->emac0tx_ecc,
93 &firwall_l4_sys_base->emac1rx_ecc,
94 &firwall_l4_sys_base->emac1tx_ecc,
95 &firwall_l4_sys_base->emac2rx_ecc,
96 &firwall_l4_sys_base->emac2tx_ecc,
97 &firwall_l4_sys_base->nand_ecc,
98 &firwall_l4_sys_base->nand_read_ecc,
99 &firwall_l4_sys_base->nand_write_ecc,
100 &firwall_l4_sys_base->ocram_ecc,
101 &firwall_l4_sys_base->sdmmc_ecc,
102 &firwall_l4_sys_base->usb0_ecc,
103 &firwall_l4_sys_base->usb1_ecc,
104 &firwall_l4_sys_base->clock_manager,
105 &firwall_l4_sys_base->io_manager,
106 &firwall_l4_sys_base->reset_manager,
107 &firwall_l4_sys_base->system_manager,
108 &firwall_l4_sys_base->watchdog0,
109 &firwall_l4_sys_base->watchdog1,
110 &firwall_l4_sys_base->watchdog2,
111 &firwall_l4_sys_base->watchdog3
112 };
113
114 for (i = 0; i < ARRAY_SIZE(addr); i++)
115 writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
116 }
117
board_init_f(ulong dummy)118 void board_init_f(ulong dummy)
119 {
120 const struct cm_config *cm_default_cfg = cm_get_default_config();
121 int ret;
122
123 #ifdef CONFIG_HW_WATCHDOG
124 /* Ensure watchdog is paused when debugging is happening */
125 writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg);
126
127 /* Enable watchdog before initializing the HW */
128 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
129 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
130 hw_watchdog_init();
131 #endif
132
133 /* ensure all processors are not released prior Linux boot */
134 writeq(0, CPU_RELEASE_ADDR);
135
136 socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
137 timer_init();
138
139 sysmgr_pinmux_init();
140
141 /* configuring the HPS clocks */
142 cm_basic_init(cm_default_cfg);
143
144 #ifdef CONFIG_DEBUG_UART
145 socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
146 debug_uart_init();
147 #endif
148 ret = spl_early_init();
149 if (ret) {
150 debug("spl_early_init() failed: %d\n", ret);
151 hang();
152 }
153
154 preloader_console_init();
155 cm_print_clock_quick_summary();
156
157 /* enable non-secure interface to DMA330 DMA and peripherals */
158 writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, &sysmgr_regs->dma);
159 writel(SYSMGR_DMAPERIPH_ALL_NS, &sysmgr_regs->dma_periph);
160
161 spl_disable_firewall_l4_per();
162
163 spl_disable_firewall_l4_sys();
164
165 /* disable lwsocf2fpga and soc2fpga bridge security */
166 writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA);
167 writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA);
168
169 /* disable SMMU security */
170 writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU);
171
172 /* disable ocram security at CCU for non secure access */
173 clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),
174 CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
175 clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
176 CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
177
178 debug("DDR: Initializing Hard Memory Controller\n");
179 if (sdram_mmr_init_full(0)) {
180 puts("DDR: Initialization failed.\n");
181 hang();
182 }
183
184 gd->ram_size = sdram_calculate_size();
185 printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));
186
187 /* Sanity check ensure correct SDRAM size specified */
188 debug("DDR: Running SDRAM size sanity check\n");
189 if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
190 puts("DDR: SDRAM size check failed!\n");
191 hang();
192 }
193 debug("DDR: SDRAM size check passed!\n");
194
195 mbox_init();
196
197 #ifdef CONFIG_CADENCE_QSPI
198 mbox_qspi_open();
199 #endif
200 }
201