1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #define SWSMU_CODE_LAYER_L1
24
25 #include <linux/firmware.h>
26 #include <linux/pci.h>
27 #include <linux/power_supply.h>
28 #include <linux/reboot.h>
29
30 #include "amdgpu.h"
31 #include "amdgpu_smu.h"
32 #include "smu_internal.h"
33 #include "atom.h"
34 #include "arcturus_ppt.h"
35 #include "navi10_ppt.h"
36 #include "sienna_cichlid_ppt.h"
37 #include "renoir_ppt.h"
38 #include "vangogh_ppt.h"
39 #include "aldebaran_ppt.h"
40 #include "yellow_carp_ppt.h"
41 #include "cyan_skillfish_ppt.h"
42 #include "smu_v13_0_0_ppt.h"
43 #include "smu_v13_0_4_ppt.h"
44 #include "smu_v13_0_5_ppt.h"
45 #include "smu_v13_0_6_ppt.h"
46 #include "smu_v13_0_7_ppt.h"
47 #include "amd_pcie.h"
48
49 /*
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
53 */
54 #undef pr_err
55 #undef pr_warn
56 #undef pr_info
57 #undef pr_debug
58
59 static const struct amd_pm_funcs swsmu_pm_funcs;
60 static int smu_force_smuclk_levels(struct smu_context *smu,
61 enum smu_clk_type clk_type,
62 uint32_t mask);
63 static int smu_handle_task(struct smu_context *smu,
64 enum amd_dpm_forced_level level,
65 enum amd_pp_task task_id);
66 static int smu_reset(struct smu_context *smu);
67 static int smu_set_fan_speed_pwm(void *handle, u32 speed);
68 static int smu_set_fan_control_mode(void *handle, u32 value);
69 static int smu_set_power_limit(void *handle, uint32_t limit);
70 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed);
71 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
72 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state);
73
smu_sys_get_pp_feature_mask(void * handle,char * buf)74 static int smu_sys_get_pp_feature_mask(void *handle,
75 char *buf)
76 {
77 struct smu_context *smu = handle;
78
79 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
80 return -EOPNOTSUPP;
81
82 return smu_get_pp_feature_mask(smu, buf);
83 }
84
smu_sys_set_pp_feature_mask(void * handle,uint64_t new_mask)85 static int smu_sys_set_pp_feature_mask(void *handle,
86 uint64_t new_mask)
87 {
88 struct smu_context *smu = handle;
89
90 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
91 return -EOPNOTSUPP;
92
93 return smu_set_pp_feature_mask(smu, new_mask);
94 }
95
smu_set_residency_gfxoff(struct smu_context * smu,bool value)96 int smu_set_residency_gfxoff(struct smu_context *smu, bool value)
97 {
98 if (!smu->ppt_funcs->set_gfx_off_residency)
99 return -EINVAL;
100
101 return smu_set_gfx_off_residency(smu, value);
102 }
103
smu_get_residency_gfxoff(struct smu_context * smu,u32 * value)104 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value)
105 {
106 if (!smu->ppt_funcs->get_gfx_off_residency)
107 return -EINVAL;
108
109 return smu_get_gfx_off_residency(smu, value);
110 }
111
smu_get_entrycount_gfxoff(struct smu_context * smu,u64 * value)112 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value)
113 {
114 if (!smu->ppt_funcs->get_gfx_off_entrycount)
115 return -EINVAL;
116
117 return smu_get_gfx_off_entrycount(smu, value);
118 }
119
smu_get_status_gfxoff(struct smu_context * smu,uint32_t * value)120 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value)
121 {
122 if (!smu->ppt_funcs->get_gfx_off_status)
123 return -EINVAL;
124
125 *value = smu_get_gfx_off_status(smu);
126
127 return 0;
128 }
129
smu_set_soft_freq_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)130 int smu_set_soft_freq_range(struct smu_context *smu,
131 enum smu_clk_type clk_type,
132 uint32_t min,
133 uint32_t max)
134 {
135 int ret = 0;
136
137 if (smu->ppt_funcs->set_soft_freq_limited_range)
138 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
139 clk_type,
140 min,
141 max);
142
143 return ret;
144 }
145
smu_get_dpm_freq_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)146 int smu_get_dpm_freq_range(struct smu_context *smu,
147 enum smu_clk_type clk_type,
148 uint32_t *min,
149 uint32_t *max)
150 {
151 int ret = -ENOTSUPP;
152
153 if (!min && !max)
154 return -EINVAL;
155
156 if (smu->ppt_funcs->get_dpm_ultimate_freq)
157 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
158 clk_type,
159 min,
160 max);
161
162 return ret;
163 }
164
smu_set_gfx_power_up_by_imu(struct smu_context * smu)165 int smu_set_gfx_power_up_by_imu(struct smu_context *smu)
166 {
167 int ret = 0;
168 struct amdgpu_device *adev = smu->adev;
169
170 if (smu->ppt_funcs->set_gfx_power_up_by_imu) {
171 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
172 if (ret)
173 dev_err(adev->dev, "Failed to enable gfx imu!\n");
174 }
175 return ret;
176 }
177
smu_get_mclk(void * handle,bool low)178 static u32 smu_get_mclk(void *handle, bool low)
179 {
180 struct smu_context *smu = handle;
181 uint32_t clk_freq;
182 int ret = 0;
183
184 ret = smu_get_dpm_freq_range(smu, SMU_UCLK,
185 low ? &clk_freq : NULL,
186 !low ? &clk_freq : NULL);
187 if (ret)
188 return 0;
189 return clk_freq * 100;
190 }
191
smu_get_sclk(void * handle,bool low)192 static u32 smu_get_sclk(void *handle, bool low)
193 {
194 struct smu_context *smu = handle;
195 uint32_t clk_freq;
196 int ret = 0;
197
198 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK,
199 low ? &clk_freq : NULL,
200 !low ? &clk_freq : NULL);
201 if (ret)
202 return 0;
203 return clk_freq * 100;
204 }
205
smu_set_gfx_imu_enable(struct smu_context * smu)206 static int smu_set_gfx_imu_enable(struct smu_context *smu)
207 {
208 struct amdgpu_device *adev = smu->adev;
209
210 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
211 return 0;
212
213 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix)
214 return 0;
215
216 return smu_set_gfx_power_up_by_imu(smu);
217 }
218
smu_dpm_set_vcn_enable(struct smu_context * smu,bool enable)219 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
220 bool enable)
221 {
222 struct smu_power_context *smu_power = &smu->smu_power;
223 struct smu_power_gate *power_gate = &smu_power->power_gate;
224 int ret = 0;
225
226 if (!smu->ppt_funcs->dpm_set_vcn_enable)
227 return 0;
228
229 if (atomic_read(&power_gate->vcn_gated) ^ enable)
230 return 0;
231
232 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
233 if (!ret)
234 atomic_set(&power_gate->vcn_gated, !enable);
235
236 return ret;
237 }
238
smu_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)239 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
240 bool enable)
241 {
242 struct smu_power_context *smu_power = &smu->smu_power;
243 struct smu_power_gate *power_gate = &smu_power->power_gate;
244 int ret = 0;
245
246 if (!smu->ppt_funcs->dpm_set_jpeg_enable)
247 return 0;
248
249 if (atomic_read(&power_gate->jpeg_gated) ^ enable)
250 return 0;
251
252 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
253 if (!ret)
254 atomic_set(&power_gate->jpeg_gated, !enable);
255
256 return ret;
257 }
258
259 /**
260 * smu_dpm_set_power_gate - power gate/ungate the specific IP block
261 *
262 * @handle: smu_context pointer
263 * @block_type: the IP block to power gate/ungate
264 * @gate: to power gate if true, ungate otherwise
265 *
266 * This API uses no smu->mutex lock protection due to:
267 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
268 * This is guarded to be race condition free by the caller.
269 * 2. Or get called on user setting request of power_dpm_force_performance_level.
270 * Under this case, the smu->mutex lock protection is already enforced on
271 * the parent API smu_force_performance_level of the call path.
272 */
smu_dpm_set_power_gate(void * handle,uint32_t block_type,bool gate)273 static int smu_dpm_set_power_gate(void *handle,
274 uint32_t block_type,
275 bool gate)
276 {
277 struct smu_context *smu = handle;
278 int ret = 0;
279
280 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) {
281 dev_WARN(smu->adev->dev,
282 "SMU uninitialized but power %s requested for %u!\n",
283 gate ? "gate" : "ungate", block_type);
284 return -EOPNOTSUPP;
285 }
286
287 switch (block_type) {
288 /*
289 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
290 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
291 */
292 case AMD_IP_BLOCK_TYPE_UVD:
293 case AMD_IP_BLOCK_TYPE_VCN:
294 ret = smu_dpm_set_vcn_enable(smu, !gate);
295 if (ret)
296 dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
297 gate ? "gate" : "ungate");
298 break;
299 case AMD_IP_BLOCK_TYPE_GFX:
300 ret = smu_gfx_off_control(smu, gate);
301 if (ret)
302 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
303 gate ? "enable" : "disable");
304 break;
305 case AMD_IP_BLOCK_TYPE_SDMA:
306 ret = smu_powergate_sdma(smu, gate);
307 if (ret)
308 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
309 gate ? "gate" : "ungate");
310 break;
311 case AMD_IP_BLOCK_TYPE_JPEG:
312 ret = smu_dpm_set_jpeg_enable(smu, !gate);
313 if (ret)
314 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
315 gate ? "gate" : "ungate");
316 break;
317 default:
318 dev_err(smu->adev->dev, "Unsupported block type!\n");
319 return -EINVAL;
320 }
321
322 return ret;
323 }
324
325 /**
326 * smu_set_user_clk_dependencies - set user profile clock dependencies
327 *
328 * @smu: smu_context pointer
329 * @clk: enum smu_clk_type type
330 *
331 * Enable/Disable the clock dependency for the @clk type.
332 */
smu_set_user_clk_dependencies(struct smu_context * smu,enum smu_clk_type clk)333 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk)
334 {
335 if (smu->adev->in_suspend)
336 return;
337
338 if (clk == SMU_MCLK) {
339 smu->user_dpm_profile.clk_dependency = 0;
340 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK);
341 } else if (clk == SMU_FCLK) {
342 /* MCLK takes precedence over FCLK */
343 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
344 return;
345
346 smu->user_dpm_profile.clk_dependency = 0;
347 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK);
348 } else if (clk == SMU_SOCCLK) {
349 /* MCLK takes precedence over SOCCLK */
350 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
351 return;
352
353 smu->user_dpm_profile.clk_dependency = 0;
354 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK);
355 } else
356 /* Add clk dependencies here, if any */
357 return;
358 }
359
360 /**
361 * smu_restore_dpm_user_profile - reinstate user dpm profile
362 *
363 * @smu: smu_context pointer
364 *
365 * Restore the saved user power configurations include power limit,
366 * clock frequencies, fan control mode and fan speed.
367 */
smu_restore_dpm_user_profile(struct smu_context * smu)368 static void smu_restore_dpm_user_profile(struct smu_context *smu)
369 {
370 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
371 int ret = 0;
372
373 if (!smu->adev->in_suspend)
374 return;
375
376 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
377 return;
378
379 /* Enable restore flag */
380 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE;
381
382 /* set the user dpm power limit */
383 if (smu->user_dpm_profile.power_limit) {
384 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit);
385 if (ret)
386 dev_err(smu->adev->dev, "Failed to set power limit value\n");
387 }
388
389 /* set the user dpm clock configurations */
390 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
391 enum smu_clk_type clk_type;
392
393 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) {
394 /*
395 * Iterate over smu clk type and force the saved user clk
396 * configs, skip if clock dependency is enabled
397 */
398 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) &&
399 smu->user_dpm_profile.clk_mask[clk_type]) {
400 ret = smu_force_smuclk_levels(smu, clk_type,
401 smu->user_dpm_profile.clk_mask[clk_type]);
402 if (ret)
403 dev_err(smu->adev->dev,
404 "Failed to set clock type = %d\n", clk_type);
405 }
406 }
407 }
408
409 /* set the user dpm fan configurations */
410 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL ||
411 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) {
412 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode);
413 if (ret != -EOPNOTSUPP) {
414 smu->user_dpm_profile.fan_speed_pwm = 0;
415 smu->user_dpm_profile.fan_speed_rpm = 0;
416 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO;
417 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n");
418 }
419
420 if (smu->user_dpm_profile.fan_speed_pwm) {
421 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm);
422 if (ret != -EOPNOTSUPP)
423 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n");
424 }
425
426 if (smu->user_dpm_profile.fan_speed_rpm) {
427 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm);
428 if (ret != -EOPNOTSUPP)
429 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n");
430 }
431 }
432
433 /* Restore user customized OD settings */
434 if (smu->user_dpm_profile.user_od) {
435 if (smu->ppt_funcs->restore_user_od_settings) {
436 ret = smu->ppt_funcs->restore_user_od_settings(smu);
437 if (ret)
438 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n");
439 }
440 }
441
442 /* Disable restore flag */
443 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE;
444 }
445
smu_get_power_num_states(void * handle,struct pp_states_info * state_info)446 static int smu_get_power_num_states(void *handle,
447 struct pp_states_info *state_info)
448 {
449 if (!state_info)
450 return -EINVAL;
451
452 /* not support power state */
453 memset(state_info, 0, sizeof(struct pp_states_info));
454 state_info->nums = 1;
455 state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
456
457 return 0;
458 }
459
is_support_sw_smu(struct amdgpu_device * adev)460 bool is_support_sw_smu(struct amdgpu_device *adev)
461 {
462 /* vega20 is 11.0.2, but it's supported via the powerplay code */
463 if (adev->asic_type == CHIP_VEGA20)
464 return false;
465
466 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0))
467 return true;
468
469 return false;
470 }
471
is_support_cclk_dpm(struct amdgpu_device * adev)472 bool is_support_cclk_dpm(struct amdgpu_device *adev)
473 {
474 struct smu_context *smu = adev->powerplay.pp_handle;
475
476 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT))
477 return false;
478
479 return true;
480 }
481
482
smu_sys_get_pp_table(void * handle,char ** table)483 static int smu_sys_get_pp_table(void *handle,
484 char **table)
485 {
486 struct smu_context *smu = handle;
487 struct smu_table_context *smu_table = &smu->smu_table;
488
489 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
490 return -EOPNOTSUPP;
491
492 if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
493 return -EINVAL;
494
495 if (smu_table->hardcode_pptable)
496 *table = smu_table->hardcode_pptable;
497 else
498 *table = smu_table->power_play_table;
499
500 return smu_table->power_play_table_size;
501 }
502
smu_sys_set_pp_table(void * handle,const char * buf,size_t size)503 static int smu_sys_set_pp_table(void *handle,
504 const char *buf,
505 size_t size)
506 {
507 struct smu_context *smu = handle;
508 struct smu_table_context *smu_table = &smu->smu_table;
509 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
510 int ret = 0;
511
512 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
513 return -EOPNOTSUPP;
514
515 if (header->usStructureSize != size) {
516 dev_err(smu->adev->dev, "pp table size not matched !\n");
517 return -EIO;
518 }
519
520 if (!smu_table->hardcode_pptable || smu_table->power_play_table_size < size) {
521 kfree(smu_table->hardcode_pptable);
522 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
523 if (!smu_table->hardcode_pptable)
524 return -ENOMEM;
525 }
526
527 memcpy(smu_table->hardcode_pptable, buf, size);
528 smu_table->power_play_table = smu_table->hardcode_pptable;
529 smu_table->power_play_table_size = size;
530
531 /*
532 * Special hw_fini action(for Navi1x, the DPMs disablement will be
533 * skipped) may be needed for custom pptable uploading.
534 */
535 smu->uploading_custom_pp_table = true;
536
537 ret = smu_reset(smu);
538 if (ret)
539 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
540
541 smu->uploading_custom_pp_table = false;
542
543 return ret;
544 }
545
smu_get_driver_allowed_feature_mask(struct smu_context * smu)546 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
547 {
548 struct smu_feature *feature = &smu->smu_feature;
549 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
550 int ret = 0;
551
552 /*
553 * With SCPM enabled, the allowed featuremasks setting(via
554 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted.
555 * That means there is no way to let PMFW knows the settings below.
556 * Thus, we just assume all the features are allowed under
557 * such scenario.
558 */
559 if (smu->adev->scpm_enabled) {
560 bitmap_fill(feature->allowed, SMU_FEATURE_MAX);
561 return 0;
562 }
563
564 bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
565
566 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
567 SMU_FEATURE_MAX/32);
568 if (ret)
569 return ret;
570
571 bitmap_or(feature->allowed, feature->allowed,
572 (unsigned long *)allowed_feature_mask,
573 feature->feature_num);
574
575 return ret;
576 }
577
smu_set_funcs(struct amdgpu_device * adev)578 static int smu_set_funcs(struct amdgpu_device *adev)
579 {
580 struct smu_context *smu = adev->powerplay.pp_handle;
581
582 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
583 smu->od_enabled = true;
584
585 switch (adev->ip_versions[MP1_HWIP][0]) {
586 case IP_VERSION(11, 0, 0):
587 case IP_VERSION(11, 0, 5):
588 case IP_VERSION(11, 0, 9):
589 navi10_set_ppt_funcs(smu);
590 break;
591 case IP_VERSION(11, 0, 7):
592 case IP_VERSION(11, 0, 11):
593 case IP_VERSION(11, 0, 12):
594 case IP_VERSION(11, 0, 13):
595 sienna_cichlid_set_ppt_funcs(smu);
596 break;
597 case IP_VERSION(12, 0, 0):
598 case IP_VERSION(12, 0, 1):
599 renoir_set_ppt_funcs(smu);
600 break;
601 case IP_VERSION(11, 5, 0):
602 vangogh_set_ppt_funcs(smu);
603 break;
604 case IP_VERSION(13, 0, 1):
605 case IP_VERSION(13, 0, 3):
606 case IP_VERSION(13, 0, 8):
607 yellow_carp_set_ppt_funcs(smu);
608 break;
609 case IP_VERSION(13, 0, 4):
610 case IP_VERSION(13, 0, 11):
611 smu_v13_0_4_set_ppt_funcs(smu);
612 break;
613 case IP_VERSION(13, 0, 5):
614 smu_v13_0_5_set_ppt_funcs(smu);
615 break;
616 case IP_VERSION(11, 0, 8):
617 cyan_skillfish_set_ppt_funcs(smu);
618 break;
619 case IP_VERSION(11, 0, 2):
620 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
621 arcturus_set_ppt_funcs(smu);
622 /* OD is not supported on Arcturus */
623 smu->od_enabled = false;
624 break;
625 case IP_VERSION(13, 0, 2):
626 aldebaran_set_ppt_funcs(smu);
627 /* Enable pp_od_clk_voltage node */
628 smu->od_enabled = true;
629 break;
630 case IP_VERSION(13, 0, 0):
631 case IP_VERSION(13, 0, 10):
632 smu_v13_0_0_set_ppt_funcs(smu);
633 break;
634 case IP_VERSION(13, 0, 6):
635 smu_v13_0_6_set_ppt_funcs(smu);
636 /* Enable pp_od_clk_voltage node */
637 smu->od_enabled = true;
638 break;
639 case IP_VERSION(13, 0, 7):
640 smu_v13_0_7_set_ppt_funcs(smu);
641 break;
642 default:
643 return -EINVAL;
644 }
645
646 return 0;
647 }
648
smu_early_init(void * handle)649 static int smu_early_init(void *handle)
650 {
651 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
652 struct smu_context *smu;
653 int r;
654
655 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL);
656 if (!smu)
657 return -ENOMEM;
658
659 smu->adev = adev;
660 smu->pm_enabled = !!amdgpu_dpm;
661 smu->is_apu = false;
662 smu->smu_baco.state = SMU_BACO_STATE_EXIT;
663 smu->smu_baco.platform_support = false;
664 smu->user_dpm_profile.fan_mode = -1;
665
666 mutex_init(&smu->message_lock);
667
668 adev->powerplay.pp_handle = smu;
669 adev->powerplay.pp_funcs = &swsmu_pm_funcs;
670
671 r = smu_set_funcs(adev);
672 if (r)
673 return r;
674 return smu_init_microcode(smu);
675 }
676
smu_set_default_dpm_table(struct smu_context * smu)677 static int smu_set_default_dpm_table(struct smu_context *smu)
678 {
679 struct smu_power_context *smu_power = &smu->smu_power;
680 struct smu_power_gate *power_gate = &smu_power->power_gate;
681 int vcn_gate, jpeg_gate;
682 int ret = 0;
683
684 if (!smu->ppt_funcs->set_default_dpm_table)
685 return 0;
686
687 vcn_gate = atomic_read(&power_gate->vcn_gated);
688 jpeg_gate = atomic_read(&power_gate->jpeg_gated);
689
690 ret = smu_dpm_set_vcn_enable(smu, true);
691 if (ret)
692 return ret;
693
694 ret = smu_dpm_set_jpeg_enable(smu, true);
695 if (ret)
696 goto err_out;
697
698 ret = smu->ppt_funcs->set_default_dpm_table(smu);
699 if (ret)
700 dev_err(smu->adev->dev,
701 "Failed to setup default dpm clock tables!\n");
702
703 smu_dpm_set_jpeg_enable(smu, !jpeg_gate);
704 err_out:
705 smu_dpm_set_vcn_enable(smu, !vcn_gate);
706 return ret;
707 }
708
smu_apply_default_config_table_settings(struct smu_context * smu)709 static int smu_apply_default_config_table_settings(struct smu_context *smu)
710 {
711 struct amdgpu_device *adev = smu->adev;
712 int ret = 0;
713
714 ret = smu_get_default_config_table_settings(smu,
715 &adev->pm.config_table);
716 if (ret)
717 return ret;
718
719 return smu_set_config_table(smu, &adev->pm.config_table);
720 }
721
smu_late_init(void * handle)722 static int smu_late_init(void *handle)
723 {
724 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
725 struct smu_context *smu = adev->powerplay.pp_handle;
726 int ret = 0;
727
728 smu_set_fine_grain_gfx_freq_parameters(smu);
729
730 if (!smu->pm_enabled)
731 return 0;
732
733 ret = smu_post_init(smu);
734 if (ret) {
735 dev_err(adev->dev, "Failed to post smu init!\n");
736 return ret;
737 }
738
739 /*
740 * Explicitly notify PMFW the power mode the system in. Since
741 * the PMFW may boot the ASIC with a different mode.
742 * For those supporting ACDC switch via gpio, PMFW will
743 * handle the switch automatically. Driver involvement
744 * is unnecessary.
745 */
746 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
747 smu_set_ac_dc(smu);
748
749 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) ||
750 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3)))
751 return 0;
752
753 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
754 ret = smu_set_default_od_settings(smu);
755 if (ret) {
756 dev_err(adev->dev, "Failed to setup default OD settings!\n");
757 return ret;
758 }
759 }
760
761 ret = smu_populate_umd_state_clk(smu);
762 if (ret) {
763 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
764 return ret;
765 }
766
767 ret = smu_get_asic_power_limits(smu,
768 &smu->current_power_limit,
769 &smu->default_power_limit,
770 &smu->max_power_limit);
771 if (ret) {
772 dev_err(adev->dev, "Failed to get asic power limits!\n");
773 return ret;
774 }
775
776 if (!amdgpu_sriov_vf(adev))
777 smu_get_unique_id(smu);
778
779 smu_get_fan_parameters(smu);
780
781 smu_handle_task(smu,
782 smu->smu_dpm.dpm_level,
783 AMD_PP_TASK_COMPLETE_INIT);
784
785 ret = smu_apply_default_config_table_settings(smu);
786 if (ret && (ret != -EOPNOTSUPP)) {
787 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n");
788 return ret;
789 }
790
791 smu_restore_dpm_user_profile(smu);
792
793 return 0;
794 }
795
smu_init_fb_allocations(struct smu_context * smu)796 static int smu_init_fb_allocations(struct smu_context *smu)
797 {
798 struct amdgpu_device *adev = smu->adev;
799 struct smu_table_context *smu_table = &smu->smu_table;
800 struct smu_table *tables = smu_table->tables;
801 struct smu_table *driver_table = &(smu_table->driver_table);
802 uint32_t max_table_size = 0;
803 int ret, i;
804
805 /* VRAM allocation for tool table */
806 if (tables[SMU_TABLE_PMSTATUSLOG].size) {
807 ret = amdgpu_bo_create_kernel(adev,
808 tables[SMU_TABLE_PMSTATUSLOG].size,
809 tables[SMU_TABLE_PMSTATUSLOG].align,
810 tables[SMU_TABLE_PMSTATUSLOG].domain,
811 &tables[SMU_TABLE_PMSTATUSLOG].bo,
812 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
813 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
814 if (ret) {
815 dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
816 return ret;
817 }
818 }
819
820 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT;
821 /* VRAM allocation for driver table */
822 for (i = 0; i < SMU_TABLE_COUNT; i++) {
823 if (tables[i].size == 0)
824 continue;
825
826 /* If one of the tables has VRAM domain restriction, keep it in
827 * VRAM
828 */
829 if ((tables[i].domain &
830 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) ==
831 AMDGPU_GEM_DOMAIN_VRAM)
832 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
833
834 if (i == SMU_TABLE_PMSTATUSLOG)
835 continue;
836
837 if (max_table_size < tables[i].size)
838 max_table_size = tables[i].size;
839 }
840
841 driver_table->size = max_table_size;
842 driver_table->align = PAGE_SIZE;
843
844 ret = amdgpu_bo_create_kernel(adev,
845 driver_table->size,
846 driver_table->align,
847 driver_table->domain,
848 &driver_table->bo,
849 &driver_table->mc_address,
850 &driver_table->cpu_addr);
851 if (ret) {
852 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
853 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
854 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
855 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
856 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
857 }
858
859 return ret;
860 }
861
smu_fini_fb_allocations(struct smu_context * smu)862 static int smu_fini_fb_allocations(struct smu_context *smu)
863 {
864 struct smu_table_context *smu_table = &smu->smu_table;
865 struct smu_table *tables = smu_table->tables;
866 struct smu_table *driver_table = &(smu_table->driver_table);
867
868 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
869 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
870 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
871 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
872
873 amdgpu_bo_free_kernel(&driver_table->bo,
874 &driver_table->mc_address,
875 &driver_table->cpu_addr);
876
877 return 0;
878 }
879
880 /**
881 * smu_alloc_memory_pool - allocate memory pool in the system memory
882 *
883 * @smu: amdgpu_device pointer
884 *
885 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
886 * and DramLogSetDramAddr can notify it changed.
887 *
888 * Returns 0 on success, error on failure.
889 */
smu_alloc_memory_pool(struct smu_context * smu)890 static int smu_alloc_memory_pool(struct smu_context *smu)
891 {
892 struct amdgpu_device *adev = smu->adev;
893 struct smu_table_context *smu_table = &smu->smu_table;
894 struct smu_table *memory_pool = &smu_table->memory_pool;
895 uint64_t pool_size = smu->pool_size;
896 int ret = 0;
897
898 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
899 return ret;
900
901 memory_pool->size = pool_size;
902 memory_pool->align = PAGE_SIZE;
903 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
904
905 switch (pool_size) {
906 case SMU_MEMORY_POOL_SIZE_256_MB:
907 case SMU_MEMORY_POOL_SIZE_512_MB:
908 case SMU_MEMORY_POOL_SIZE_1_GB:
909 case SMU_MEMORY_POOL_SIZE_2_GB:
910 ret = amdgpu_bo_create_kernel(adev,
911 memory_pool->size,
912 memory_pool->align,
913 memory_pool->domain,
914 &memory_pool->bo,
915 &memory_pool->mc_address,
916 &memory_pool->cpu_addr);
917 if (ret)
918 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
919 break;
920 default:
921 break;
922 }
923
924 return ret;
925 }
926
smu_free_memory_pool(struct smu_context * smu)927 static int smu_free_memory_pool(struct smu_context *smu)
928 {
929 struct smu_table_context *smu_table = &smu->smu_table;
930 struct smu_table *memory_pool = &smu_table->memory_pool;
931
932 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
933 return 0;
934
935 amdgpu_bo_free_kernel(&memory_pool->bo,
936 &memory_pool->mc_address,
937 &memory_pool->cpu_addr);
938
939 memset(memory_pool, 0, sizeof(struct smu_table));
940
941 return 0;
942 }
943
smu_alloc_dummy_read_table(struct smu_context * smu)944 static int smu_alloc_dummy_read_table(struct smu_context *smu)
945 {
946 struct smu_table_context *smu_table = &smu->smu_table;
947 struct smu_table *dummy_read_1_table =
948 &smu_table->dummy_read_1_table;
949 struct amdgpu_device *adev = smu->adev;
950 int ret = 0;
951
952 if (!dummy_read_1_table->size)
953 return 0;
954
955 ret = amdgpu_bo_create_kernel(adev,
956 dummy_read_1_table->size,
957 dummy_read_1_table->align,
958 dummy_read_1_table->domain,
959 &dummy_read_1_table->bo,
960 &dummy_read_1_table->mc_address,
961 &dummy_read_1_table->cpu_addr);
962 if (ret)
963 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n");
964
965 return ret;
966 }
967
smu_free_dummy_read_table(struct smu_context * smu)968 static void smu_free_dummy_read_table(struct smu_context *smu)
969 {
970 struct smu_table_context *smu_table = &smu->smu_table;
971 struct smu_table *dummy_read_1_table =
972 &smu_table->dummy_read_1_table;
973
974
975 amdgpu_bo_free_kernel(&dummy_read_1_table->bo,
976 &dummy_read_1_table->mc_address,
977 &dummy_read_1_table->cpu_addr);
978
979 memset(dummy_read_1_table, 0, sizeof(struct smu_table));
980 }
981
smu_smc_table_sw_init(struct smu_context * smu)982 static int smu_smc_table_sw_init(struct smu_context *smu)
983 {
984 int ret;
985
986 /**
987 * Create smu_table structure, and init smc tables such as
988 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
989 */
990 ret = smu_init_smc_tables(smu);
991 if (ret) {
992 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
993 return ret;
994 }
995
996 /**
997 * Create smu_power_context structure, and allocate smu_dpm_context and
998 * context size to fill the smu_power_context data.
999 */
1000 ret = smu_init_power(smu);
1001 if (ret) {
1002 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
1003 return ret;
1004 }
1005
1006 /*
1007 * allocate vram bos to store smc table contents.
1008 */
1009 ret = smu_init_fb_allocations(smu);
1010 if (ret)
1011 return ret;
1012
1013 ret = smu_alloc_memory_pool(smu);
1014 if (ret)
1015 return ret;
1016
1017 ret = smu_alloc_dummy_read_table(smu);
1018 if (ret)
1019 return ret;
1020
1021 ret = smu_i2c_init(smu);
1022 if (ret)
1023 return ret;
1024
1025 return 0;
1026 }
1027
smu_smc_table_sw_fini(struct smu_context * smu)1028 static int smu_smc_table_sw_fini(struct smu_context *smu)
1029 {
1030 int ret;
1031
1032 smu_i2c_fini(smu);
1033
1034 smu_free_dummy_read_table(smu);
1035
1036 ret = smu_free_memory_pool(smu);
1037 if (ret)
1038 return ret;
1039
1040 ret = smu_fini_fb_allocations(smu);
1041 if (ret)
1042 return ret;
1043
1044 ret = smu_fini_power(smu);
1045 if (ret) {
1046 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
1047 return ret;
1048 }
1049
1050 ret = smu_fini_smc_tables(smu);
1051 if (ret) {
1052 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
1053 return ret;
1054 }
1055
1056 return 0;
1057 }
1058
smu_throttling_logging_work_fn(struct work_struct * work)1059 static void smu_throttling_logging_work_fn(struct work_struct *work)
1060 {
1061 struct smu_context *smu = container_of(work, struct smu_context,
1062 throttling_logging_work);
1063
1064 smu_log_thermal_throttling(smu);
1065 }
1066
smu_interrupt_work_fn(struct work_struct * work)1067 static void smu_interrupt_work_fn(struct work_struct *work)
1068 {
1069 struct smu_context *smu = container_of(work, struct smu_context,
1070 interrupt_work);
1071
1072 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work)
1073 smu->ppt_funcs->interrupt_work(smu);
1074 }
1075
smu_swctf_delayed_work_handler(struct work_struct * work)1076 static void smu_swctf_delayed_work_handler(struct work_struct *work)
1077 {
1078 struct smu_context *smu =
1079 container_of(work, struct smu_context, swctf_delayed_work.work);
1080 struct smu_temperature_range *range =
1081 &smu->thermal_range;
1082 struct amdgpu_device *adev = smu->adev;
1083 uint32_t hotspot_tmp, size;
1084
1085 /*
1086 * If the hotspot temperature is confirmed as below SW CTF setting point
1087 * after the delay enforced, nothing will be done.
1088 * Otherwise, a graceful shutdown will be performed to prevent further damage.
1089 */
1090 if (range->software_shutdown_temp &&
1091 smu->ppt_funcs->read_sensor &&
1092 !smu->ppt_funcs->read_sensor(smu,
1093 AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
1094 &hotspot_tmp,
1095 &size) &&
1096 hotspot_tmp / 1000 < range->software_shutdown_temp)
1097 return;
1098
1099 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1100 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1101 orderly_poweroff(true);
1102 }
1103
smu_sw_init(void * handle)1104 static int smu_sw_init(void *handle)
1105 {
1106 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1107 struct smu_context *smu = adev->powerplay.pp_handle;
1108 int ret;
1109
1110 smu->pool_size = adev->pm.smu_prv_buffer_size;
1111 smu->smu_feature.feature_num = SMU_FEATURE_MAX;
1112 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
1113 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
1114
1115 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
1116 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn);
1117 atomic64_set(&smu->throttle_int_counter, 0);
1118 smu->watermarks_bitmap = 0;
1119 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1120 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1121
1122 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
1123 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
1124
1125 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
1126 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
1127 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
1128 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
1129 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
1130 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
1131 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
1132 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
1133
1134 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1135 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1136 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
1137 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
1138 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
1139 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
1140 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
1141 smu->display_config = &adev->pm.pm_display_cfg;
1142
1143 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1144 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1145
1146 INIT_DELAYED_WORK(&smu->swctf_delayed_work,
1147 smu_swctf_delayed_work_handler);
1148
1149 ret = smu_smc_table_sw_init(smu);
1150 if (ret) {
1151 dev_err(adev->dev, "Failed to sw init smc table!\n");
1152 return ret;
1153 }
1154
1155 /* get boot_values from vbios to set revision, gfxclk, and etc. */
1156 ret = smu_get_vbios_bootup_values(smu);
1157 if (ret) {
1158 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1159 return ret;
1160 }
1161
1162 ret = smu_init_pptable_microcode(smu);
1163 if (ret) {
1164 dev_err(adev->dev, "Failed to setup pptable firmware!\n");
1165 return ret;
1166 }
1167
1168 ret = smu_register_irq_handler(smu);
1169 if (ret) {
1170 dev_err(adev->dev, "Failed to register smc irq handler!\n");
1171 return ret;
1172 }
1173
1174 /* If there is no way to query fan control mode, fan control is not supported */
1175 if (!smu->ppt_funcs->get_fan_control_mode)
1176 smu->adev->pm.no_fan = true;
1177
1178 return 0;
1179 }
1180
smu_sw_fini(void * handle)1181 static int smu_sw_fini(void *handle)
1182 {
1183 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1184 struct smu_context *smu = adev->powerplay.pp_handle;
1185 int ret;
1186
1187 ret = smu_smc_table_sw_fini(smu);
1188 if (ret) {
1189 dev_err(adev->dev, "Failed to sw fini smc table!\n");
1190 return ret;
1191 }
1192
1193 smu_fini_microcode(smu);
1194
1195 return 0;
1196 }
1197
smu_get_thermal_temperature_range(struct smu_context * smu)1198 static int smu_get_thermal_temperature_range(struct smu_context *smu)
1199 {
1200 struct amdgpu_device *adev = smu->adev;
1201 struct smu_temperature_range *range =
1202 &smu->thermal_range;
1203 int ret = 0;
1204
1205 if (!smu->ppt_funcs->get_thermal_temperature_range)
1206 return 0;
1207
1208 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
1209 if (ret)
1210 return ret;
1211
1212 adev->pm.dpm.thermal.min_temp = range->min;
1213 adev->pm.dpm.thermal.max_temp = range->max;
1214 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
1215 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
1216 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
1217 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
1218 adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
1219 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
1220 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
1221
1222 return ret;
1223 }
1224
smu_smc_hw_setup(struct smu_context * smu)1225 static int smu_smc_hw_setup(struct smu_context *smu)
1226 {
1227 struct smu_feature *feature = &smu->smu_feature;
1228 struct amdgpu_device *adev = smu->adev;
1229 uint8_t pcie_gen = 0, pcie_width = 0;
1230 uint64_t features_supported;
1231 int ret = 0;
1232
1233 switch (adev->ip_versions[MP1_HWIP][0]) {
1234 case IP_VERSION(11, 0, 7):
1235 case IP_VERSION(11, 0, 11):
1236 case IP_VERSION(11, 5, 0):
1237 case IP_VERSION(11, 0, 12):
1238 if (adev->in_suspend && smu_is_dpm_running(smu)) {
1239 dev_info(adev->dev, "dpm has been enabled\n");
1240 ret = smu_system_features_control(smu, true);
1241 if (ret)
1242 dev_err(adev->dev, "Failed system features control!\n");
1243 return ret;
1244 }
1245 break;
1246 default:
1247 break;
1248 }
1249
1250 ret = smu_init_display_count(smu, 0);
1251 if (ret) {
1252 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
1253 return ret;
1254 }
1255
1256 ret = smu_set_driver_table_location(smu);
1257 if (ret) {
1258 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
1259 return ret;
1260 }
1261
1262 /*
1263 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1264 */
1265 ret = smu_set_tool_table_location(smu);
1266 if (ret) {
1267 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
1268 return ret;
1269 }
1270
1271 /*
1272 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1273 * pool location.
1274 */
1275 ret = smu_notify_memory_pool_location(smu);
1276 if (ret) {
1277 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
1278 return ret;
1279 }
1280
1281 /*
1282 * It is assumed the pptable used before runpm is same as
1283 * the one used afterwards. Thus, we can reuse the stored
1284 * copy and do not need to resetup the pptable again.
1285 */
1286 if (!adev->in_runpm) {
1287 ret = smu_setup_pptable(smu);
1288 if (ret) {
1289 dev_err(adev->dev, "Failed to setup pptable!\n");
1290 return ret;
1291 }
1292 }
1293
1294 /* smu_dump_pptable(smu); */
1295
1296 /*
1297 * With SCPM enabled, PSP is responsible for the PPTable transferring
1298 * (to SMU). Driver involvement is not needed and permitted.
1299 */
1300 if (!adev->scpm_enabled) {
1301 /*
1302 * Copy pptable bo in the vram to smc with SMU MSGs such as
1303 * SetDriverDramAddr and TransferTableDram2Smu.
1304 */
1305 ret = smu_write_pptable(smu);
1306 if (ret) {
1307 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
1308 return ret;
1309 }
1310 }
1311
1312 /* issue Run*Btc msg */
1313 ret = smu_run_btc(smu);
1314 if (ret)
1315 return ret;
1316
1317 /*
1318 * With SCPM enabled, these actions(and relevant messages) are
1319 * not needed and permitted.
1320 */
1321 if (!adev->scpm_enabled) {
1322 ret = smu_feature_set_allowed_mask(smu);
1323 if (ret) {
1324 dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
1325 return ret;
1326 }
1327 }
1328
1329 ret = smu_system_features_control(smu, true);
1330 if (ret) {
1331 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
1332 return ret;
1333 }
1334
1335 ret = smu_feature_get_enabled_mask(smu, &features_supported);
1336 if (ret) {
1337 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n");
1338 return ret;
1339 }
1340 bitmap_copy(feature->supported,
1341 (unsigned long *)&features_supported,
1342 feature->feature_num);
1343
1344 if (!smu_is_dpm_running(smu))
1345 dev_info(adev->dev, "dpm has been disabled\n");
1346
1347 /*
1348 * Set initialized values (get from vbios) to dpm tables context such as
1349 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1350 * type of clks.
1351 */
1352 ret = smu_set_default_dpm_table(smu);
1353 if (ret) {
1354 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
1355 return ret;
1356 }
1357
1358 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1359 pcie_gen = 3;
1360 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1361 pcie_gen = 2;
1362 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1363 pcie_gen = 1;
1364 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1365 pcie_gen = 0;
1366
1367 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1368 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1369 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
1370 */
1371 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1372 pcie_width = 6;
1373 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1374 pcie_width = 5;
1375 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1376 pcie_width = 4;
1377 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1378 pcie_width = 3;
1379 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1380 pcie_width = 2;
1381 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1382 pcie_width = 1;
1383 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1384 if (ret) {
1385 dev_err(adev->dev, "Attempt to override pcie params failed!\n");
1386 return ret;
1387 }
1388
1389 ret = smu_get_thermal_temperature_range(smu);
1390 if (ret) {
1391 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
1392 return ret;
1393 }
1394
1395 ret = smu_enable_thermal_alert(smu);
1396 if (ret) {
1397 dev_err(adev->dev, "Failed to enable thermal alert!\n");
1398 return ret;
1399 }
1400
1401 ret = smu_notify_display_change(smu);
1402 if (ret) {
1403 dev_err(adev->dev, "Failed to notify display change!\n");
1404 return ret;
1405 }
1406
1407 /*
1408 * Set min deep sleep dce fclk with bootup value from vbios via
1409 * SetMinDeepSleepDcefclk MSG.
1410 */
1411 ret = smu_set_min_dcef_deep_sleep(smu,
1412 smu->smu_table.boot_values.dcefclk / 100);
1413
1414 return ret;
1415 }
1416
smu_start_smc_engine(struct smu_context * smu)1417 static int smu_start_smc_engine(struct smu_context *smu)
1418 {
1419 struct amdgpu_device *adev = smu->adev;
1420 int ret = 0;
1421
1422 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1423 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) {
1424 if (smu->ppt_funcs->load_microcode) {
1425 ret = smu->ppt_funcs->load_microcode(smu);
1426 if (ret)
1427 return ret;
1428 }
1429 }
1430 }
1431
1432 if (smu->ppt_funcs->check_fw_status) {
1433 ret = smu->ppt_funcs->check_fw_status(smu);
1434 if (ret) {
1435 dev_err(adev->dev, "SMC is not ready\n");
1436 return ret;
1437 }
1438 }
1439
1440 /*
1441 * Send msg GetDriverIfVersion to check if the return value is equal
1442 * with DRIVER_IF_VERSION of smc header.
1443 */
1444 ret = smu_check_fw_version(smu);
1445 if (ret)
1446 return ret;
1447
1448 return ret;
1449 }
1450
smu_hw_init(void * handle)1451 static int smu_hw_init(void *handle)
1452 {
1453 int ret;
1454 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1455 struct smu_context *smu = adev->powerplay.pp_handle;
1456
1457 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
1458 smu->pm_enabled = false;
1459 return 0;
1460 }
1461
1462 ret = smu_start_smc_engine(smu);
1463 if (ret) {
1464 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1465 return ret;
1466 }
1467
1468 if (smu->is_apu) {
1469 ret = smu_set_gfx_imu_enable(smu);
1470 if (ret)
1471 return ret;
1472 smu_dpm_set_vcn_enable(smu, true);
1473 smu_dpm_set_jpeg_enable(smu, true);
1474 smu_set_gfx_cgpg(smu, true);
1475 }
1476
1477 if (!smu->pm_enabled)
1478 return 0;
1479
1480 ret = smu_get_driver_allowed_feature_mask(smu);
1481 if (ret)
1482 return ret;
1483
1484 ret = smu_smc_hw_setup(smu);
1485 if (ret) {
1486 dev_err(adev->dev, "Failed to setup smc hw!\n");
1487 return ret;
1488 }
1489
1490 /*
1491 * Move maximum sustainable clock retrieving here considering
1492 * 1. It is not needed on resume(from S3).
1493 * 2. DAL settings come between .hw_init and .late_init of SMU.
1494 * And DAL needs to know the maximum sustainable clocks. Thus
1495 * it cannot be put in .late_init().
1496 */
1497 ret = smu_init_max_sustainable_clocks(smu);
1498 if (ret) {
1499 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1500 return ret;
1501 }
1502
1503 adev->pm.dpm_enabled = true;
1504
1505 dev_info(adev->dev, "SMU is initialized successfully!\n");
1506
1507 return 0;
1508 }
1509
smu_disable_dpms(struct smu_context * smu)1510 static int smu_disable_dpms(struct smu_context *smu)
1511 {
1512 struct amdgpu_device *adev = smu->adev;
1513 int ret = 0;
1514 bool use_baco = !smu->is_apu &&
1515 ((amdgpu_in_reset(adev) &&
1516 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1517 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev)));
1518
1519 /*
1520 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others)
1521 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues.
1522 */
1523 switch (adev->ip_versions[MP1_HWIP][0]) {
1524 case IP_VERSION(13, 0, 0):
1525 case IP_VERSION(13, 0, 7):
1526 case IP_VERSION(13, 0, 10):
1527 return 0;
1528 default:
1529 break;
1530 }
1531
1532 /*
1533 * For custom pptable uploading, skip the DPM features
1534 * disable process on Navi1x ASICs.
1535 * - As the gfx related features are under control of
1536 * RLC on those ASICs. RLC reinitialization will be
1537 * needed to reenable them. That will cost much more
1538 * efforts.
1539 *
1540 * - SMU firmware can handle the DPM reenablement
1541 * properly.
1542 */
1543 if (smu->uploading_custom_pp_table) {
1544 switch (adev->ip_versions[MP1_HWIP][0]) {
1545 case IP_VERSION(11, 0, 0):
1546 case IP_VERSION(11, 0, 5):
1547 case IP_VERSION(11, 0, 9):
1548 case IP_VERSION(11, 0, 7):
1549 case IP_VERSION(11, 0, 11):
1550 case IP_VERSION(11, 5, 0):
1551 case IP_VERSION(11, 0, 12):
1552 case IP_VERSION(11, 0, 13):
1553 return 0;
1554 default:
1555 break;
1556 }
1557 }
1558
1559 /*
1560 * For Sienna_Cichlid, PMFW will handle the features disablement properly
1561 * on BACO in. Driver involvement is unnecessary.
1562 */
1563 if (use_baco) {
1564 switch (adev->ip_versions[MP1_HWIP][0]) {
1565 case IP_VERSION(11, 0, 7):
1566 case IP_VERSION(11, 0, 0):
1567 case IP_VERSION(11, 0, 5):
1568 case IP_VERSION(11, 0, 9):
1569 case IP_VERSION(13, 0, 7):
1570 return 0;
1571 default:
1572 break;
1573 }
1574 }
1575
1576 /*
1577 * For SMU 13.0.4/11, PMFW will handle the features disablement properly
1578 * for gpu reset and S0i3 cases. Driver involvement is unnecessary.
1579 */
1580 if (amdgpu_in_reset(adev) || adev->in_s0ix) {
1581 switch (adev->ip_versions[MP1_HWIP][0]) {
1582 case IP_VERSION(13, 0, 4):
1583 case IP_VERSION(13, 0, 11):
1584 return 0;
1585 default:
1586 break;
1587 }
1588 }
1589
1590 /*
1591 * For gpu reset, runpm and hibernation through BACO,
1592 * BACO feature has to be kept enabled.
1593 */
1594 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1595 ret = smu_disable_all_features_with_exception(smu,
1596 SMU_FEATURE_BACO_BIT);
1597 if (ret)
1598 dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
1599 } else {
1600 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */
1601 if (!adev->scpm_enabled) {
1602 ret = smu_system_features_control(smu, false);
1603 if (ret)
1604 dev_err(adev->dev, "Failed to disable smu features.\n");
1605 }
1606 }
1607
1608 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) &&
1609 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop)
1610 adev->gfx.rlc.funcs->stop(adev);
1611
1612 return ret;
1613 }
1614
smu_smc_hw_cleanup(struct smu_context * smu)1615 static int smu_smc_hw_cleanup(struct smu_context *smu)
1616 {
1617 struct amdgpu_device *adev = smu->adev;
1618 int ret = 0;
1619
1620 cancel_work_sync(&smu->throttling_logging_work);
1621 cancel_work_sync(&smu->interrupt_work);
1622
1623 ret = smu_disable_thermal_alert(smu);
1624 if (ret) {
1625 dev_err(adev->dev, "Fail to disable thermal alert!\n");
1626 return ret;
1627 }
1628
1629 cancel_delayed_work_sync(&smu->swctf_delayed_work);
1630
1631 ret = smu_disable_dpms(smu);
1632 if (ret) {
1633 dev_err(adev->dev, "Fail to disable dpm features!\n");
1634 return ret;
1635 }
1636
1637 return 0;
1638 }
1639
smu_hw_fini(void * handle)1640 static int smu_hw_fini(void *handle)
1641 {
1642 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1643 struct smu_context *smu = adev->powerplay.pp_handle;
1644
1645 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1646 return 0;
1647
1648 smu_dpm_set_vcn_enable(smu, false);
1649 smu_dpm_set_jpeg_enable(smu, false);
1650
1651 adev->vcn.cur_state = AMD_PG_STATE_GATE;
1652 adev->jpeg.cur_state = AMD_PG_STATE_GATE;
1653
1654 if (!smu->pm_enabled)
1655 return 0;
1656
1657 adev->pm.dpm_enabled = false;
1658
1659 return smu_smc_hw_cleanup(smu);
1660 }
1661
smu_late_fini(void * handle)1662 static void smu_late_fini(void *handle)
1663 {
1664 struct amdgpu_device *adev = handle;
1665 struct smu_context *smu = adev->powerplay.pp_handle;
1666
1667 kfree(smu);
1668 }
1669
smu_reset(struct smu_context * smu)1670 static int smu_reset(struct smu_context *smu)
1671 {
1672 struct amdgpu_device *adev = smu->adev;
1673 int ret;
1674
1675 ret = smu_hw_fini(adev);
1676 if (ret)
1677 return ret;
1678
1679 ret = smu_hw_init(adev);
1680 if (ret)
1681 return ret;
1682
1683 ret = smu_late_init(adev);
1684 if (ret)
1685 return ret;
1686
1687 return 0;
1688 }
1689
smu_suspend(void * handle)1690 static int smu_suspend(void *handle)
1691 {
1692 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1693 struct smu_context *smu = adev->powerplay.pp_handle;
1694 int ret;
1695 uint64_t count;
1696
1697 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1698 return 0;
1699
1700 if (!smu->pm_enabled)
1701 return 0;
1702
1703 adev->pm.dpm_enabled = false;
1704
1705 ret = smu_smc_hw_cleanup(smu);
1706 if (ret)
1707 return ret;
1708
1709 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1710
1711 smu_set_gfx_cgpg(smu, false);
1712
1713 /*
1714 * pwfw resets entrycount when device is suspended, so we save the
1715 * last value to be used when we resume to keep it consistent
1716 */
1717 ret = smu_get_entrycount_gfxoff(smu, &count);
1718 if (!ret)
1719 adev->gfx.gfx_off_entrycount = count;
1720
1721 return 0;
1722 }
1723
smu_resume(void * handle)1724 static int smu_resume(void *handle)
1725 {
1726 int ret;
1727 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1728 struct smu_context *smu = adev->powerplay.pp_handle;
1729
1730 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1731 return 0;
1732
1733 if (!smu->pm_enabled)
1734 return 0;
1735
1736 dev_info(adev->dev, "SMU is resuming...\n");
1737
1738 ret = smu_start_smc_engine(smu);
1739 if (ret) {
1740 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1741 return ret;
1742 }
1743
1744 ret = smu_smc_hw_setup(smu);
1745 if (ret) {
1746 dev_err(adev->dev, "Failed to setup smc hw!\n");
1747 return ret;
1748 }
1749
1750 ret = smu_set_gfx_imu_enable(smu);
1751 if (ret)
1752 return ret;
1753
1754 smu_set_gfx_cgpg(smu, true);
1755
1756 smu->disable_uclk_switch = 0;
1757
1758 adev->pm.dpm_enabled = true;
1759
1760 dev_info(adev->dev, "SMU is resumed successfully!\n");
1761
1762 return 0;
1763 }
1764
smu_display_configuration_change(void * handle,const struct amd_pp_display_configuration * display_config)1765 static int smu_display_configuration_change(void *handle,
1766 const struct amd_pp_display_configuration *display_config)
1767 {
1768 struct smu_context *smu = handle;
1769
1770 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1771 return -EOPNOTSUPP;
1772
1773 if (!display_config)
1774 return -EINVAL;
1775
1776 smu_set_min_dcef_deep_sleep(smu,
1777 display_config->min_dcef_deep_sleep_set_clk / 100);
1778
1779 return 0;
1780 }
1781
smu_set_clockgating_state(void * handle,enum amd_clockgating_state state)1782 static int smu_set_clockgating_state(void *handle,
1783 enum amd_clockgating_state state)
1784 {
1785 return 0;
1786 }
1787
smu_set_powergating_state(void * handle,enum amd_powergating_state state)1788 static int smu_set_powergating_state(void *handle,
1789 enum amd_powergating_state state)
1790 {
1791 return 0;
1792 }
1793
smu_enable_umd_pstate(void * handle,enum amd_dpm_forced_level * level)1794 static int smu_enable_umd_pstate(void *handle,
1795 enum amd_dpm_forced_level *level)
1796 {
1797 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1798 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1799 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1800 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1801
1802 struct smu_context *smu = (struct smu_context*)(handle);
1803 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1804
1805 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1806 return -EINVAL;
1807
1808 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1809 /* enter umd pstate, save current level, disable gfx cg*/
1810 if (*level & profile_mode_mask) {
1811 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1812 smu_gpo_control(smu, false);
1813 smu_gfx_ulv_control(smu, false);
1814 smu_deep_sleep_control(smu, false);
1815 amdgpu_asic_update_umd_stable_pstate(smu->adev, true);
1816 }
1817 } else {
1818 /* exit umd pstate, restore level, enable gfx cg*/
1819 if (!(*level & profile_mode_mask)) {
1820 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1821 *level = smu_dpm_ctx->saved_dpm_level;
1822 amdgpu_asic_update_umd_stable_pstate(smu->adev, false);
1823 smu_deep_sleep_control(smu, true);
1824 smu_gfx_ulv_control(smu, true);
1825 smu_gpo_control(smu, true);
1826 }
1827 }
1828
1829 return 0;
1830 }
1831
smu_bump_power_profile_mode(struct smu_context * smu,long * param,uint32_t param_size)1832 static int smu_bump_power_profile_mode(struct smu_context *smu,
1833 long *param,
1834 uint32_t param_size)
1835 {
1836 int ret = 0;
1837
1838 if (smu->ppt_funcs->set_power_profile_mode)
1839 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
1840
1841 return ret;
1842 }
1843
smu_adjust_power_state_dynamic(struct smu_context * smu,enum amd_dpm_forced_level level,bool skip_display_settings,bool init)1844 static int smu_adjust_power_state_dynamic(struct smu_context *smu,
1845 enum amd_dpm_forced_level level,
1846 bool skip_display_settings,
1847 bool init)
1848 {
1849 int ret = 0;
1850 int index = 0;
1851 long workload[1];
1852 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1853
1854 if (!skip_display_settings) {
1855 ret = smu_display_config_changed(smu);
1856 if (ret) {
1857 dev_err(smu->adev->dev, "Failed to change display config!");
1858 return ret;
1859 }
1860 }
1861
1862 ret = smu_apply_clocks_adjust_rules(smu);
1863 if (ret) {
1864 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
1865 return ret;
1866 }
1867
1868 if (!skip_display_settings) {
1869 ret = smu_notify_smc_display_config(smu);
1870 if (ret) {
1871 dev_err(smu->adev->dev, "Failed to notify smc display config!");
1872 return ret;
1873 }
1874 }
1875
1876 if (smu_dpm_ctx->dpm_level != level) {
1877 ret = smu_asic_set_performance_level(smu, level);
1878 if (ret) {
1879 dev_err(smu->adev->dev, "Failed to set performance level!");
1880 return ret;
1881 }
1882
1883 /* update the saved copy */
1884 smu_dpm_ctx->dpm_level = level;
1885 }
1886
1887 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
1888 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1889 index = fls(smu->workload_mask);
1890 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1891 workload[0] = smu->workload_setting[index];
1892
1893 if (init || smu->power_profile_mode != workload[0])
1894 smu_bump_power_profile_mode(smu, workload, 0);
1895 }
1896
1897 return ret;
1898 }
1899
smu_handle_task(struct smu_context * smu,enum amd_dpm_forced_level level,enum amd_pp_task task_id)1900 static int smu_handle_task(struct smu_context *smu,
1901 enum amd_dpm_forced_level level,
1902 enum amd_pp_task task_id)
1903 {
1904 int ret = 0;
1905
1906 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1907 return -EOPNOTSUPP;
1908
1909 switch (task_id) {
1910 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1911 ret = smu_pre_display_config_changed(smu);
1912 if (ret)
1913 return ret;
1914 ret = smu_adjust_power_state_dynamic(smu, level, false, false);
1915 break;
1916 case AMD_PP_TASK_COMPLETE_INIT:
1917 ret = smu_adjust_power_state_dynamic(smu, level, true, true);
1918 break;
1919 case AMD_PP_TASK_READJUST_POWER_STATE:
1920 ret = smu_adjust_power_state_dynamic(smu, level, true, false);
1921 break;
1922 default:
1923 break;
1924 }
1925
1926 return ret;
1927 }
1928
smu_handle_dpm_task(void * handle,enum amd_pp_task task_id,enum amd_pm_state_type * user_state)1929 static int smu_handle_dpm_task(void *handle,
1930 enum amd_pp_task task_id,
1931 enum amd_pm_state_type *user_state)
1932 {
1933 struct smu_context *smu = handle;
1934 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1935
1936 return smu_handle_task(smu, smu_dpm->dpm_level, task_id);
1937
1938 }
1939
smu_switch_power_profile(void * handle,enum PP_SMC_POWER_PROFILE type,bool en)1940 static int smu_switch_power_profile(void *handle,
1941 enum PP_SMC_POWER_PROFILE type,
1942 bool en)
1943 {
1944 struct smu_context *smu = handle;
1945 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1946 long workload[1];
1947 uint32_t index;
1948
1949 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1950 return -EOPNOTSUPP;
1951
1952 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1953 return -EINVAL;
1954
1955 if (!en) {
1956 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1957 index = fls(smu->workload_mask);
1958 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1959 workload[0] = smu->workload_setting[index];
1960 } else {
1961 smu->workload_mask |= (1 << smu->workload_prority[type]);
1962 index = fls(smu->workload_mask);
1963 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1964 workload[0] = smu->workload_setting[index];
1965 }
1966
1967 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
1968 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
1969 smu_bump_power_profile_mode(smu, workload, 0);
1970
1971 return 0;
1972 }
1973
smu_get_performance_level(void * handle)1974 static enum amd_dpm_forced_level smu_get_performance_level(void *handle)
1975 {
1976 struct smu_context *smu = handle;
1977 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1978
1979 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1980 return -EOPNOTSUPP;
1981
1982 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1983 return -EINVAL;
1984
1985 return smu_dpm_ctx->dpm_level;
1986 }
1987
smu_force_performance_level(void * handle,enum amd_dpm_forced_level level)1988 static int smu_force_performance_level(void *handle,
1989 enum amd_dpm_forced_level level)
1990 {
1991 struct smu_context *smu = handle;
1992 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1993 int ret = 0;
1994
1995 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1996 return -EOPNOTSUPP;
1997
1998 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1999 return -EINVAL;
2000
2001 ret = smu_enable_umd_pstate(smu, &level);
2002 if (ret)
2003 return ret;
2004
2005 ret = smu_handle_task(smu, level,
2006 AMD_PP_TASK_READJUST_POWER_STATE);
2007
2008 /* reset user dpm clock state */
2009 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
2010 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask));
2011 smu->user_dpm_profile.clk_dependency = 0;
2012 }
2013
2014 return ret;
2015 }
2016
smu_set_display_count(void * handle,uint32_t count)2017 static int smu_set_display_count(void *handle, uint32_t count)
2018 {
2019 struct smu_context *smu = handle;
2020
2021 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2022 return -EOPNOTSUPP;
2023
2024 return smu_init_display_count(smu, count);
2025 }
2026
smu_force_smuclk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)2027 static int smu_force_smuclk_levels(struct smu_context *smu,
2028 enum smu_clk_type clk_type,
2029 uint32_t mask)
2030 {
2031 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2032 int ret = 0;
2033
2034 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2035 return -EOPNOTSUPP;
2036
2037 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
2038 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
2039 return -EINVAL;
2040 }
2041
2042 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) {
2043 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
2044 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2045 smu->user_dpm_profile.clk_mask[clk_type] = mask;
2046 smu_set_user_clk_dependencies(smu, clk_type);
2047 }
2048 }
2049
2050 return ret;
2051 }
2052
smu_force_ppclk_levels(void * handle,enum pp_clock_type type,uint32_t mask)2053 static int smu_force_ppclk_levels(void *handle,
2054 enum pp_clock_type type,
2055 uint32_t mask)
2056 {
2057 struct smu_context *smu = handle;
2058 enum smu_clk_type clk_type;
2059
2060 switch (type) {
2061 case PP_SCLK:
2062 clk_type = SMU_SCLK; break;
2063 case PP_MCLK:
2064 clk_type = SMU_MCLK; break;
2065 case PP_PCIE:
2066 clk_type = SMU_PCIE; break;
2067 case PP_SOCCLK:
2068 clk_type = SMU_SOCCLK; break;
2069 case PP_FCLK:
2070 clk_type = SMU_FCLK; break;
2071 case PP_DCEFCLK:
2072 clk_type = SMU_DCEFCLK; break;
2073 case PP_VCLK:
2074 clk_type = SMU_VCLK; break;
2075 case PP_VCLK1:
2076 clk_type = SMU_VCLK1; break;
2077 case PP_DCLK:
2078 clk_type = SMU_DCLK; break;
2079 case PP_DCLK1:
2080 clk_type = SMU_DCLK1; break;
2081 case OD_SCLK:
2082 clk_type = SMU_OD_SCLK; break;
2083 case OD_MCLK:
2084 clk_type = SMU_OD_MCLK; break;
2085 case OD_VDDC_CURVE:
2086 clk_type = SMU_OD_VDDC_CURVE; break;
2087 case OD_RANGE:
2088 clk_type = SMU_OD_RANGE; break;
2089 default:
2090 return -EINVAL;
2091 }
2092
2093 return smu_force_smuclk_levels(smu, clk_type, mask);
2094 }
2095
2096 /*
2097 * On system suspending or resetting, the dpm_enabled
2098 * flag will be cleared. So that those SMU services which
2099 * are not supported will be gated.
2100 * However, the mp1 state setting should still be granted
2101 * even if the dpm_enabled cleared.
2102 */
smu_set_mp1_state(void * handle,enum pp_mp1_state mp1_state)2103 static int smu_set_mp1_state(void *handle,
2104 enum pp_mp1_state mp1_state)
2105 {
2106 struct smu_context *smu = handle;
2107 int ret = 0;
2108
2109 if (!smu->pm_enabled)
2110 return -EOPNOTSUPP;
2111
2112 if (smu->ppt_funcs &&
2113 smu->ppt_funcs->set_mp1_state)
2114 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state);
2115
2116 return ret;
2117 }
2118
smu_set_df_cstate(void * handle,enum pp_df_cstate state)2119 static int smu_set_df_cstate(void *handle,
2120 enum pp_df_cstate state)
2121 {
2122 struct smu_context *smu = handle;
2123 int ret = 0;
2124
2125 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2126 return -EOPNOTSUPP;
2127
2128 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
2129 return 0;
2130
2131 ret = smu->ppt_funcs->set_df_cstate(smu, state);
2132 if (ret)
2133 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
2134
2135 return ret;
2136 }
2137
smu_allow_xgmi_power_down(struct smu_context * smu,bool en)2138 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
2139 {
2140 int ret = 0;
2141
2142 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2143 return -EOPNOTSUPP;
2144
2145 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down)
2146 return 0;
2147
2148 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
2149 if (ret)
2150 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n");
2151
2152 return ret;
2153 }
2154
smu_write_watermarks_table(struct smu_context * smu)2155 int smu_write_watermarks_table(struct smu_context *smu)
2156 {
2157 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2158 return -EOPNOTSUPP;
2159
2160 return smu_set_watermarks_table(smu, NULL);
2161 }
2162
smu_set_watermarks_for_clock_ranges(void * handle,struct pp_smu_wm_range_sets * clock_ranges)2163 static int smu_set_watermarks_for_clock_ranges(void *handle,
2164 struct pp_smu_wm_range_sets *clock_ranges)
2165 {
2166 struct smu_context *smu = handle;
2167
2168 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2169 return -EOPNOTSUPP;
2170
2171 if (smu->disable_watermark)
2172 return 0;
2173
2174 return smu_set_watermarks_table(smu, clock_ranges);
2175 }
2176
smu_set_ac_dc(struct smu_context * smu)2177 int smu_set_ac_dc(struct smu_context *smu)
2178 {
2179 int ret = 0;
2180
2181 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2182 return -EOPNOTSUPP;
2183
2184 /* controlled by firmware */
2185 if (smu->dc_controlled_by_gpio)
2186 return 0;
2187
2188 ret = smu_set_power_source(smu,
2189 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
2190 SMU_POWER_SOURCE_DC);
2191 if (ret)
2192 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
2193 smu->adev->pm.ac_power ? "AC" : "DC");
2194
2195 return ret;
2196 }
2197
2198 const struct amd_ip_funcs smu_ip_funcs = {
2199 .name = "smu",
2200 .early_init = smu_early_init,
2201 .late_init = smu_late_init,
2202 .sw_init = smu_sw_init,
2203 .sw_fini = smu_sw_fini,
2204 .hw_init = smu_hw_init,
2205 .hw_fini = smu_hw_fini,
2206 .late_fini = smu_late_fini,
2207 .suspend = smu_suspend,
2208 .resume = smu_resume,
2209 .is_idle = NULL,
2210 .check_soft_reset = NULL,
2211 .wait_for_idle = NULL,
2212 .soft_reset = NULL,
2213 .set_clockgating_state = smu_set_clockgating_state,
2214 .set_powergating_state = smu_set_powergating_state,
2215 };
2216
2217 const struct amdgpu_ip_block_version smu_v11_0_ip_block = {
2218 .type = AMD_IP_BLOCK_TYPE_SMC,
2219 .major = 11,
2220 .minor = 0,
2221 .rev = 0,
2222 .funcs = &smu_ip_funcs,
2223 };
2224
2225 const struct amdgpu_ip_block_version smu_v12_0_ip_block = {
2226 .type = AMD_IP_BLOCK_TYPE_SMC,
2227 .major = 12,
2228 .minor = 0,
2229 .rev = 0,
2230 .funcs = &smu_ip_funcs,
2231 };
2232
2233 const struct amdgpu_ip_block_version smu_v13_0_ip_block = {
2234 .type = AMD_IP_BLOCK_TYPE_SMC,
2235 .major = 13,
2236 .minor = 0,
2237 .rev = 0,
2238 .funcs = &smu_ip_funcs,
2239 };
2240
smu_load_microcode(void * handle)2241 static int smu_load_microcode(void *handle)
2242 {
2243 struct smu_context *smu = handle;
2244 struct amdgpu_device *adev = smu->adev;
2245 int ret = 0;
2246
2247 if (!smu->pm_enabled)
2248 return -EOPNOTSUPP;
2249
2250 /* This should be used for non PSP loading */
2251 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
2252 return 0;
2253
2254 if (smu->ppt_funcs->load_microcode) {
2255 ret = smu->ppt_funcs->load_microcode(smu);
2256 if (ret) {
2257 dev_err(adev->dev, "Load microcode failed\n");
2258 return ret;
2259 }
2260 }
2261
2262 if (smu->ppt_funcs->check_fw_status) {
2263 ret = smu->ppt_funcs->check_fw_status(smu);
2264 if (ret) {
2265 dev_err(adev->dev, "SMC is not ready\n");
2266 return ret;
2267 }
2268 }
2269
2270 return ret;
2271 }
2272
smu_set_gfx_cgpg(struct smu_context * smu,bool enabled)2273 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2274 {
2275 int ret = 0;
2276
2277 if (smu->ppt_funcs->set_gfx_cgpg)
2278 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2279
2280 return ret;
2281 }
2282
smu_set_fan_speed_rpm(void * handle,uint32_t speed)2283 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
2284 {
2285 struct smu_context *smu = handle;
2286 int ret = 0;
2287
2288 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2289 return -EOPNOTSUPP;
2290
2291 if (!smu->ppt_funcs->set_fan_speed_rpm)
2292 return -EOPNOTSUPP;
2293
2294 if (speed == U32_MAX)
2295 return -EINVAL;
2296
2297 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
2298 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2299 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM;
2300 smu->user_dpm_profile.fan_speed_rpm = speed;
2301
2302 /* Override custom PWM setting as they cannot co-exist */
2303 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM;
2304 smu->user_dpm_profile.fan_speed_pwm = 0;
2305 }
2306
2307 return ret;
2308 }
2309
2310 /**
2311 * smu_get_power_limit - Request one of the SMU Power Limits
2312 *
2313 * @handle: pointer to smu context
2314 * @limit: requested limit is written back to this variable
2315 * @pp_limit_level: &pp_power_limit_level which limit of the power to return
2316 * @pp_power_type: &pp_power_type type of power
2317 * Return: 0 on success, <0 on error
2318 *
2319 */
smu_get_power_limit(void * handle,uint32_t * limit,enum pp_power_limit_level pp_limit_level,enum pp_power_type pp_power_type)2320 int smu_get_power_limit(void *handle,
2321 uint32_t *limit,
2322 enum pp_power_limit_level pp_limit_level,
2323 enum pp_power_type pp_power_type)
2324 {
2325 struct smu_context *smu = handle;
2326 struct amdgpu_device *adev = smu->adev;
2327 enum smu_ppt_limit_level limit_level;
2328 uint32_t limit_type;
2329 int ret = 0;
2330
2331 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2332 return -EOPNOTSUPP;
2333
2334 switch (pp_power_type) {
2335 case PP_PWR_TYPE_SUSTAINED:
2336 limit_type = SMU_DEFAULT_PPT_LIMIT;
2337 break;
2338 case PP_PWR_TYPE_FAST:
2339 limit_type = SMU_FAST_PPT_LIMIT;
2340 break;
2341 default:
2342 return -EOPNOTSUPP;
2343 break;
2344 }
2345
2346 switch (pp_limit_level) {
2347 case PP_PWR_LIMIT_CURRENT:
2348 limit_level = SMU_PPT_LIMIT_CURRENT;
2349 break;
2350 case PP_PWR_LIMIT_DEFAULT:
2351 limit_level = SMU_PPT_LIMIT_DEFAULT;
2352 break;
2353 case PP_PWR_LIMIT_MAX:
2354 limit_level = SMU_PPT_LIMIT_MAX;
2355 break;
2356 case PP_PWR_LIMIT_MIN:
2357 default:
2358 return -EOPNOTSUPP;
2359 break;
2360 }
2361
2362 if (limit_type != SMU_DEFAULT_PPT_LIMIT) {
2363 if (smu->ppt_funcs->get_ppt_limit)
2364 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level);
2365 } else {
2366 switch (limit_level) {
2367 case SMU_PPT_LIMIT_CURRENT:
2368 switch (adev->ip_versions[MP1_HWIP][0]) {
2369 case IP_VERSION(13, 0, 2):
2370 case IP_VERSION(11, 0, 7):
2371 case IP_VERSION(11, 0, 11):
2372 case IP_VERSION(11, 0, 12):
2373 case IP_VERSION(11, 0, 13):
2374 ret = smu_get_asic_power_limits(smu,
2375 &smu->current_power_limit,
2376 NULL,
2377 NULL);
2378 break;
2379 default:
2380 break;
2381 }
2382 *limit = smu->current_power_limit;
2383 break;
2384 case SMU_PPT_LIMIT_DEFAULT:
2385 *limit = smu->default_power_limit;
2386 break;
2387 case SMU_PPT_LIMIT_MAX:
2388 *limit = smu->max_power_limit;
2389 break;
2390 default:
2391 break;
2392 }
2393 }
2394
2395 return ret;
2396 }
2397
smu_set_power_limit(void * handle,uint32_t limit)2398 static int smu_set_power_limit(void *handle, uint32_t limit)
2399 {
2400 struct smu_context *smu = handle;
2401 uint32_t limit_type = limit >> 24;
2402 int ret = 0;
2403
2404 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2405 return -EOPNOTSUPP;
2406
2407 limit &= (1<<24)-1;
2408 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
2409 if (smu->ppt_funcs->set_power_limit)
2410 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit);
2411
2412 if (limit > smu->max_power_limit) {
2413 dev_err(smu->adev->dev,
2414 "New power limit (%d) is over the max allowed %d\n",
2415 limit, smu->max_power_limit);
2416 return -EINVAL;
2417 }
2418
2419 if (!limit)
2420 limit = smu->current_power_limit;
2421
2422 if (smu->ppt_funcs->set_power_limit) {
2423 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit);
2424 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
2425 smu->user_dpm_profile.power_limit = limit;
2426 }
2427
2428 return ret;
2429 }
2430
smu_print_smuclk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)2431 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2432 {
2433 int ret = 0;
2434
2435 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2436 return -EOPNOTSUPP;
2437
2438 if (smu->ppt_funcs->print_clk_levels)
2439 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2440
2441 return ret;
2442 }
2443
smu_convert_to_smuclk(enum pp_clock_type type)2444 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type)
2445 {
2446 enum smu_clk_type clk_type;
2447
2448 switch (type) {
2449 case PP_SCLK:
2450 clk_type = SMU_SCLK; break;
2451 case PP_MCLK:
2452 clk_type = SMU_MCLK; break;
2453 case PP_PCIE:
2454 clk_type = SMU_PCIE; break;
2455 case PP_SOCCLK:
2456 clk_type = SMU_SOCCLK; break;
2457 case PP_FCLK:
2458 clk_type = SMU_FCLK; break;
2459 case PP_DCEFCLK:
2460 clk_type = SMU_DCEFCLK; break;
2461 case PP_VCLK:
2462 clk_type = SMU_VCLK; break;
2463 case PP_VCLK1:
2464 clk_type = SMU_VCLK1; break;
2465 case PP_DCLK:
2466 clk_type = SMU_DCLK; break;
2467 case PP_DCLK1:
2468 clk_type = SMU_DCLK1; break;
2469 case OD_SCLK:
2470 clk_type = SMU_OD_SCLK; break;
2471 case OD_MCLK:
2472 clk_type = SMU_OD_MCLK; break;
2473 case OD_VDDC_CURVE:
2474 clk_type = SMU_OD_VDDC_CURVE; break;
2475 case OD_RANGE:
2476 clk_type = SMU_OD_RANGE; break;
2477 case OD_VDDGFX_OFFSET:
2478 clk_type = SMU_OD_VDDGFX_OFFSET; break;
2479 case OD_CCLK:
2480 clk_type = SMU_OD_CCLK; break;
2481 default:
2482 clk_type = SMU_CLK_COUNT; break;
2483 }
2484
2485 return clk_type;
2486 }
2487
smu_print_ppclk_levels(void * handle,enum pp_clock_type type,char * buf)2488 static int smu_print_ppclk_levels(void *handle,
2489 enum pp_clock_type type,
2490 char *buf)
2491 {
2492 struct smu_context *smu = handle;
2493 enum smu_clk_type clk_type;
2494
2495 clk_type = smu_convert_to_smuclk(type);
2496 if (clk_type == SMU_CLK_COUNT)
2497 return -EINVAL;
2498
2499 return smu_print_smuclk_levels(smu, clk_type, buf);
2500 }
2501
smu_emit_ppclk_levels(void * handle,enum pp_clock_type type,char * buf,int * offset)2502 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset)
2503 {
2504 struct smu_context *smu = handle;
2505 enum smu_clk_type clk_type;
2506
2507 clk_type = smu_convert_to_smuclk(type);
2508 if (clk_type == SMU_CLK_COUNT)
2509 return -EINVAL;
2510
2511 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2512 return -EOPNOTSUPP;
2513
2514 if (!smu->ppt_funcs->emit_clk_levels)
2515 return -ENOENT;
2516
2517 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset);
2518
2519 }
2520
smu_od_edit_dpm_table(void * handle,enum PP_OD_DPM_TABLE_COMMAND type,long * input,uint32_t size)2521 static int smu_od_edit_dpm_table(void *handle,
2522 enum PP_OD_DPM_TABLE_COMMAND type,
2523 long *input, uint32_t size)
2524 {
2525 struct smu_context *smu = handle;
2526 int ret = 0;
2527
2528 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2529 return -EOPNOTSUPP;
2530
2531 if (smu->ppt_funcs->od_edit_dpm_table) {
2532 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2533 }
2534
2535 return ret;
2536 }
2537
smu_read_sensor(void * handle,int sensor,void * data,int * size_arg)2538 static int smu_read_sensor(void *handle,
2539 int sensor,
2540 void *data,
2541 int *size_arg)
2542 {
2543 struct smu_context *smu = handle;
2544 struct smu_umd_pstate_table *pstate_table =
2545 &smu->pstate_table;
2546 int ret = 0;
2547 uint32_t *size, size_val;
2548
2549 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2550 return -EOPNOTSUPP;
2551
2552 if (!data || !size_arg)
2553 return -EINVAL;
2554
2555 size_val = *size_arg;
2556 size = &size_val;
2557
2558 if (smu->ppt_funcs->read_sensor)
2559 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
2560 goto unlock;
2561
2562 switch (sensor) {
2563 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
2564 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
2565 *size = 4;
2566 break;
2567 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
2568 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
2569 *size = 4;
2570 break;
2571 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK:
2572 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100;
2573 *size = 4;
2574 break;
2575 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK:
2576 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100;
2577 *size = 4;
2578 break;
2579 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2580 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data);
2581 *size = 8;
2582 break;
2583 case AMDGPU_PP_SENSOR_UVD_POWER:
2584 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
2585 *size = 4;
2586 break;
2587 case AMDGPU_PP_SENSOR_VCE_POWER:
2588 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
2589 *size = 4;
2590 break;
2591 case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
2592 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1;
2593 *size = 4;
2594 break;
2595 case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
2596 *(uint32_t *)data = 0;
2597 *size = 4;
2598 break;
2599 default:
2600 *size = 0;
2601 ret = -EOPNOTSUPP;
2602 break;
2603 }
2604
2605 unlock:
2606 // assign uint32_t to int
2607 *size_arg = size_val;
2608
2609 return ret;
2610 }
2611
smu_get_apu_thermal_limit(void * handle,uint32_t * limit)2612 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit)
2613 {
2614 int ret = -EINVAL;
2615 struct smu_context *smu = handle;
2616
2617 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit)
2618 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit);
2619
2620 return ret;
2621 }
2622
smu_set_apu_thermal_limit(void * handle,uint32_t limit)2623 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit)
2624 {
2625 int ret = -EINVAL;
2626 struct smu_context *smu = handle;
2627
2628 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit)
2629 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit);
2630
2631 return ret;
2632 }
2633
smu_get_power_profile_mode(void * handle,char * buf)2634 static int smu_get_power_profile_mode(void *handle, char *buf)
2635 {
2636 struct smu_context *smu = handle;
2637
2638 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
2639 !smu->ppt_funcs->get_power_profile_mode)
2640 return -EOPNOTSUPP;
2641 if (!buf)
2642 return -EINVAL;
2643
2644 return smu->ppt_funcs->get_power_profile_mode(smu, buf);
2645 }
2646
smu_set_power_profile_mode(void * handle,long * param,uint32_t param_size)2647 static int smu_set_power_profile_mode(void *handle,
2648 long *param,
2649 uint32_t param_size)
2650 {
2651 struct smu_context *smu = handle;
2652
2653 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
2654 !smu->ppt_funcs->set_power_profile_mode)
2655 return -EOPNOTSUPP;
2656
2657 return smu_bump_power_profile_mode(smu, param, param_size);
2658 }
2659
smu_get_fan_control_mode(void * handle,u32 * fan_mode)2660 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode)
2661 {
2662 struct smu_context *smu = handle;
2663
2664 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2665 return -EOPNOTSUPP;
2666
2667 if (!smu->ppt_funcs->get_fan_control_mode)
2668 return -EOPNOTSUPP;
2669
2670 if (!fan_mode)
2671 return -EINVAL;
2672
2673 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu);
2674
2675 return 0;
2676 }
2677
smu_set_fan_control_mode(void * handle,u32 value)2678 static int smu_set_fan_control_mode(void *handle, u32 value)
2679 {
2680 struct smu_context *smu = handle;
2681 int ret = 0;
2682
2683 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2684 return -EOPNOTSUPP;
2685
2686 if (!smu->ppt_funcs->set_fan_control_mode)
2687 return -EOPNOTSUPP;
2688
2689 if (value == U32_MAX)
2690 return -EINVAL;
2691
2692 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2693 if (ret)
2694 goto out;
2695
2696 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2697 smu->user_dpm_profile.fan_mode = value;
2698
2699 /* reset user dpm fan speed */
2700 if (value != AMD_FAN_CTRL_MANUAL) {
2701 smu->user_dpm_profile.fan_speed_pwm = 0;
2702 smu->user_dpm_profile.fan_speed_rpm = 0;
2703 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM);
2704 }
2705 }
2706
2707 out:
2708 return ret;
2709 }
2710
smu_get_fan_speed_pwm(void * handle,u32 * speed)2711 static int smu_get_fan_speed_pwm(void *handle, u32 *speed)
2712 {
2713 struct smu_context *smu = handle;
2714 int ret = 0;
2715
2716 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2717 return -EOPNOTSUPP;
2718
2719 if (!smu->ppt_funcs->get_fan_speed_pwm)
2720 return -EOPNOTSUPP;
2721
2722 if (!speed)
2723 return -EINVAL;
2724
2725 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed);
2726
2727 return ret;
2728 }
2729
smu_set_fan_speed_pwm(void * handle,u32 speed)2730 static int smu_set_fan_speed_pwm(void *handle, u32 speed)
2731 {
2732 struct smu_context *smu = handle;
2733 int ret = 0;
2734
2735 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2736 return -EOPNOTSUPP;
2737
2738 if (!smu->ppt_funcs->set_fan_speed_pwm)
2739 return -EOPNOTSUPP;
2740
2741 if (speed == U32_MAX)
2742 return -EINVAL;
2743
2744 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed);
2745 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2746 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM;
2747 smu->user_dpm_profile.fan_speed_pwm = speed;
2748
2749 /* Override custom RPM setting as they cannot co-exist */
2750 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM;
2751 smu->user_dpm_profile.fan_speed_rpm = 0;
2752 }
2753
2754 return ret;
2755 }
2756
smu_get_fan_speed_rpm(void * handle,uint32_t * speed)2757 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed)
2758 {
2759 struct smu_context *smu = handle;
2760 int ret = 0;
2761
2762 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2763 return -EOPNOTSUPP;
2764
2765 if (!smu->ppt_funcs->get_fan_speed_rpm)
2766 return -EOPNOTSUPP;
2767
2768 if (!speed)
2769 return -EINVAL;
2770
2771 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2772
2773 return ret;
2774 }
2775
smu_set_deep_sleep_dcefclk(void * handle,uint32_t clk)2776 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk)
2777 {
2778 struct smu_context *smu = handle;
2779
2780 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2781 return -EOPNOTSUPP;
2782
2783 return smu_set_min_dcef_deep_sleep(smu, clk);
2784 }
2785
smu_get_clock_by_type_with_latency(void * handle,enum amd_pp_clock_type type,struct pp_clock_levels_with_latency * clocks)2786 static int smu_get_clock_by_type_with_latency(void *handle,
2787 enum amd_pp_clock_type type,
2788 struct pp_clock_levels_with_latency *clocks)
2789 {
2790 struct smu_context *smu = handle;
2791 enum smu_clk_type clk_type;
2792 int ret = 0;
2793
2794 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2795 return -EOPNOTSUPP;
2796
2797 if (smu->ppt_funcs->get_clock_by_type_with_latency) {
2798 switch (type) {
2799 case amd_pp_sys_clock:
2800 clk_type = SMU_GFXCLK;
2801 break;
2802 case amd_pp_mem_clock:
2803 clk_type = SMU_MCLK;
2804 break;
2805 case amd_pp_dcef_clock:
2806 clk_type = SMU_DCEFCLK;
2807 break;
2808 case amd_pp_disp_clock:
2809 clk_type = SMU_DISPCLK;
2810 break;
2811 default:
2812 dev_err(smu->adev->dev, "Invalid clock type!\n");
2813 return -EINVAL;
2814 }
2815
2816 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2817 }
2818
2819 return ret;
2820 }
2821
smu_display_clock_voltage_request(void * handle,struct pp_display_clock_request * clock_req)2822 static int smu_display_clock_voltage_request(void *handle,
2823 struct pp_display_clock_request *clock_req)
2824 {
2825 struct smu_context *smu = handle;
2826 int ret = 0;
2827
2828 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2829 return -EOPNOTSUPP;
2830
2831 if (smu->ppt_funcs->display_clock_voltage_request)
2832 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2833
2834 return ret;
2835 }
2836
2837
smu_display_disable_memory_clock_switch(void * handle,bool disable_memory_clock_switch)2838 static int smu_display_disable_memory_clock_switch(void *handle,
2839 bool disable_memory_clock_switch)
2840 {
2841 struct smu_context *smu = handle;
2842 int ret = -EINVAL;
2843
2844 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2845 return -EOPNOTSUPP;
2846
2847 if (smu->ppt_funcs->display_disable_memory_clock_switch)
2848 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2849
2850 return ret;
2851 }
2852
smu_set_xgmi_pstate(void * handle,uint32_t pstate)2853 static int smu_set_xgmi_pstate(void *handle,
2854 uint32_t pstate)
2855 {
2856 struct smu_context *smu = handle;
2857 int ret = 0;
2858
2859 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2860 return -EOPNOTSUPP;
2861
2862 if (smu->ppt_funcs->set_xgmi_pstate)
2863 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2864
2865 if (ret)
2866 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
2867
2868 return ret;
2869 }
2870
smu_get_baco_capability(void * handle,bool * cap)2871 static int smu_get_baco_capability(void *handle, bool *cap)
2872 {
2873 struct smu_context *smu = handle;
2874
2875 *cap = false;
2876
2877 if (!smu->pm_enabled)
2878 return 0;
2879
2880 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2881 *cap = smu->ppt_funcs->baco_is_support(smu);
2882
2883 return 0;
2884 }
2885
smu_baco_set_state(void * handle,int state)2886 static int smu_baco_set_state(void *handle, int state)
2887 {
2888 struct smu_context *smu = handle;
2889 int ret = 0;
2890
2891 if (!smu->pm_enabled)
2892 return -EOPNOTSUPP;
2893
2894 if (state == 0) {
2895 if (smu->ppt_funcs->baco_exit)
2896 ret = smu->ppt_funcs->baco_exit(smu);
2897 } else if (state == 1) {
2898 if (smu->ppt_funcs->baco_enter)
2899 ret = smu->ppt_funcs->baco_enter(smu);
2900 } else {
2901 return -EINVAL;
2902 }
2903
2904 if (ret)
2905 dev_err(smu->adev->dev, "Failed to %s BACO state!\n",
2906 (state)?"enter":"exit");
2907
2908 return ret;
2909 }
2910
smu_mode1_reset_is_support(struct smu_context * smu)2911 bool smu_mode1_reset_is_support(struct smu_context *smu)
2912 {
2913 bool ret = false;
2914
2915 if (!smu->pm_enabled)
2916 return false;
2917
2918 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
2919 ret = smu->ppt_funcs->mode1_reset_is_support(smu);
2920
2921 return ret;
2922 }
2923
smu_mode2_reset_is_support(struct smu_context * smu)2924 bool smu_mode2_reset_is_support(struct smu_context *smu)
2925 {
2926 bool ret = false;
2927
2928 if (!smu->pm_enabled)
2929 return false;
2930
2931 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support)
2932 ret = smu->ppt_funcs->mode2_reset_is_support(smu);
2933
2934 return ret;
2935 }
2936
smu_mode1_reset(struct smu_context * smu)2937 int smu_mode1_reset(struct smu_context *smu)
2938 {
2939 int ret = 0;
2940
2941 if (!smu->pm_enabled)
2942 return -EOPNOTSUPP;
2943
2944 if (smu->ppt_funcs->mode1_reset)
2945 ret = smu->ppt_funcs->mode1_reset(smu);
2946
2947 return ret;
2948 }
2949
smu_mode2_reset(void * handle)2950 static int smu_mode2_reset(void *handle)
2951 {
2952 struct smu_context *smu = handle;
2953 int ret = 0;
2954
2955 if (!smu->pm_enabled)
2956 return -EOPNOTSUPP;
2957
2958 if (smu->ppt_funcs->mode2_reset)
2959 ret = smu->ppt_funcs->mode2_reset(smu);
2960
2961 if (ret)
2962 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
2963
2964 return ret;
2965 }
2966
smu_enable_gfx_features(void * handle)2967 static int smu_enable_gfx_features(void *handle)
2968 {
2969 struct smu_context *smu = handle;
2970 int ret = 0;
2971
2972 if (!smu->pm_enabled)
2973 return -EOPNOTSUPP;
2974
2975 if (smu->ppt_funcs->enable_gfx_features)
2976 ret = smu->ppt_funcs->enable_gfx_features(smu);
2977
2978 if (ret)
2979 dev_err(smu->adev->dev, "enable gfx features failed!\n");
2980
2981 return ret;
2982 }
2983
smu_get_max_sustainable_clocks_by_dc(void * handle,struct pp_smu_nv_clock_table * max_clocks)2984 static int smu_get_max_sustainable_clocks_by_dc(void *handle,
2985 struct pp_smu_nv_clock_table *max_clocks)
2986 {
2987 struct smu_context *smu = handle;
2988 int ret = 0;
2989
2990 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2991 return -EOPNOTSUPP;
2992
2993 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2994 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2995
2996 return ret;
2997 }
2998
smu_get_uclk_dpm_states(void * handle,unsigned int * clock_values_in_khz,unsigned int * num_states)2999 static int smu_get_uclk_dpm_states(void *handle,
3000 unsigned int *clock_values_in_khz,
3001 unsigned int *num_states)
3002 {
3003 struct smu_context *smu = handle;
3004 int ret = 0;
3005
3006 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3007 return -EOPNOTSUPP;
3008
3009 if (smu->ppt_funcs->get_uclk_dpm_states)
3010 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
3011
3012 return ret;
3013 }
3014
smu_get_current_power_state(void * handle)3015 static enum amd_pm_state_type smu_get_current_power_state(void *handle)
3016 {
3017 struct smu_context *smu = handle;
3018 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
3019
3020 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3021 return -EOPNOTSUPP;
3022
3023 if (smu->ppt_funcs->get_current_power_state)
3024 pm_state = smu->ppt_funcs->get_current_power_state(smu);
3025
3026 return pm_state;
3027 }
3028
smu_get_dpm_clock_table(void * handle,struct dpm_clocks * clock_table)3029 static int smu_get_dpm_clock_table(void *handle,
3030 struct dpm_clocks *clock_table)
3031 {
3032 struct smu_context *smu = handle;
3033 int ret = 0;
3034
3035 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3036 return -EOPNOTSUPP;
3037
3038 if (smu->ppt_funcs->get_dpm_clock_table)
3039 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
3040
3041 return ret;
3042 }
3043
smu_sys_get_gpu_metrics(void * handle,void ** table)3044 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table)
3045 {
3046 struct smu_context *smu = handle;
3047
3048 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3049 return -EOPNOTSUPP;
3050
3051 if (!smu->ppt_funcs->get_gpu_metrics)
3052 return -EOPNOTSUPP;
3053
3054 return smu->ppt_funcs->get_gpu_metrics(smu, table);
3055 }
3056
smu_enable_mgpu_fan_boost(void * handle)3057 static int smu_enable_mgpu_fan_boost(void *handle)
3058 {
3059 struct smu_context *smu = handle;
3060 int ret = 0;
3061
3062 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3063 return -EOPNOTSUPP;
3064
3065 if (smu->ppt_funcs->enable_mgpu_fan_boost)
3066 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu);
3067
3068 return ret;
3069 }
3070
smu_gfx_state_change_set(void * handle,uint32_t state)3071 static int smu_gfx_state_change_set(void *handle,
3072 uint32_t state)
3073 {
3074 struct smu_context *smu = handle;
3075 int ret = 0;
3076
3077 if (smu->ppt_funcs->gfx_state_change_set)
3078 ret = smu->ppt_funcs->gfx_state_change_set(smu, state);
3079
3080 return ret;
3081 }
3082
smu_handle_passthrough_sbr(struct smu_context * smu,bool enable)3083 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
3084 {
3085 int ret = 0;
3086
3087 if (smu->ppt_funcs->smu_handle_passthrough_sbr)
3088 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable);
3089
3090 return ret;
3091 }
3092
smu_get_ecc_info(struct smu_context * smu,void * umc_ecc)3093 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc)
3094 {
3095 int ret = -EOPNOTSUPP;
3096
3097 if (smu->ppt_funcs &&
3098 smu->ppt_funcs->get_ecc_info)
3099 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc);
3100
3101 return ret;
3102
3103 }
3104
smu_get_prv_buffer_details(void * handle,void ** addr,size_t * size)3105 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size)
3106 {
3107 struct smu_context *smu = handle;
3108 struct smu_table_context *smu_table = &smu->smu_table;
3109 struct smu_table *memory_pool = &smu_table->memory_pool;
3110
3111 if (!addr || !size)
3112 return -EINVAL;
3113
3114 *addr = NULL;
3115 *size = 0;
3116 if (memory_pool->bo) {
3117 *addr = memory_pool->cpu_addr;
3118 *size = memory_pool->size;
3119 }
3120
3121 return 0;
3122 }
3123
3124 static const struct amd_pm_funcs swsmu_pm_funcs = {
3125 /* export for sysfs */
3126 .set_fan_control_mode = smu_set_fan_control_mode,
3127 .get_fan_control_mode = smu_get_fan_control_mode,
3128 .set_fan_speed_pwm = smu_set_fan_speed_pwm,
3129 .get_fan_speed_pwm = smu_get_fan_speed_pwm,
3130 .force_clock_level = smu_force_ppclk_levels,
3131 .print_clock_levels = smu_print_ppclk_levels,
3132 .emit_clock_levels = smu_emit_ppclk_levels,
3133 .force_performance_level = smu_force_performance_level,
3134 .read_sensor = smu_read_sensor,
3135 .get_apu_thermal_limit = smu_get_apu_thermal_limit,
3136 .set_apu_thermal_limit = smu_set_apu_thermal_limit,
3137 .get_performance_level = smu_get_performance_level,
3138 .get_current_power_state = smu_get_current_power_state,
3139 .get_fan_speed_rpm = smu_get_fan_speed_rpm,
3140 .set_fan_speed_rpm = smu_set_fan_speed_rpm,
3141 .get_pp_num_states = smu_get_power_num_states,
3142 .get_pp_table = smu_sys_get_pp_table,
3143 .set_pp_table = smu_sys_set_pp_table,
3144 .switch_power_profile = smu_switch_power_profile,
3145 /* export to amdgpu */
3146 .dispatch_tasks = smu_handle_dpm_task,
3147 .load_firmware = smu_load_microcode,
3148 .set_powergating_by_smu = smu_dpm_set_power_gate,
3149 .set_power_limit = smu_set_power_limit,
3150 .get_power_limit = smu_get_power_limit,
3151 .get_power_profile_mode = smu_get_power_profile_mode,
3152 .set_power_profile_mode = smu_set_power_profile_mode,
3153 .odn_edit_dpm_table = smu_od_edit_dpm_table,
3154 .set_mp1_state = smu_set_mp1_state,
3155 .gfx_state_change_set = smu_gfx_state_change_set,
3156 /* export to DC */
3157 .get_sclk = smu_get_sclk,
3158 .get_mclk = smu_get_mclk,
3159 .display_configuration_change = smu_display_configuration_change,
3160 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency,
3161 .display_clock_voltage_request = smu_display_clock_voltage_request,
3162 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost,
3163 .set_active_display_count = smu_set_display_count,
3164 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk,
3165 .get_asic_baco_capability = smu_get_baco_capability,
3166 .set_asic_baco_state = smu_baco_set_state,
3167 .get_ppfeature_status = smu_sys_get_pp_feature_mask,
3168 .set_ppfeature_status = smu_sys_set_pp_feature_mask,
3169 .asic_reset_mode_2 = smu_mode2_reset,
3170 .asic_reset_enable_gfx_features = smu_enable_gfx_features,
3171 .set_df_cstate = smu_set_df_cstate,
3172 .set_xgmi_pstate = smu_set_xgmi_pstate,
3173 .get_gpu_metrics = smu_sys_get_gpu_metrics,
3174 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges,
3175 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch,
3176 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc,
3177 .get_uclk_dpm_states = smu_get_uclk_dpm_states,
3178 .get_dpm_clock_table = smu_get_dpm_clock_table,
3179 .get_smu_prv_buf_details = smu_get_prv_buffer_details,
3180 };
3181
smu_wait_for_event(struct smu_context * smu,enum smu_event_type event,uint64_t event_arg)3182 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event,
3183 uint64_t event_arg)
3184 {
3185 int ret = -EINVAL;
3186
3187 if (smu->ppt_funcs->wait_for_event)
3188 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg);
3189
3190 return ret;
3191 }
3192
smu_stb_collect_info(struct smu_context * smu,void * buf,uint32_t size)3193 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size)
3194 {
3195
3196 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled)
3197 return -EOPNOTSUPP;
3198
3199 /* Confirm the buffer allocated is of correct size */
3200 if (size != smu->stb_context.stb_buf_size)
3201 return -EINVAL;
3202
3203 /*
3204 * No need to lock smu mutex as we access STB directly through MMIO
3205 * and not going through SMU messaging route (for now at least).
3206 * For registers access rely on implementation internal locking.
3207 */
3208 return smu->ppt_funcs->stb_collect_info(smu, buf, size);
3209 }
3210
3211 #if defined(CONFIG_DEBUG_FS)
3212
smu_stb_debugfs_open(struct inode * inode,struct file * filp)3213 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp)
3214 {
3215 struct amdgpu_device *adev = filp->f_inode->i_private;
3216 struct smu_context *smu = adev->powerplay.pp_handle;
3217 unsigned char *buf;
3218 int r;
3219
3220 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL);
3221 if (!buf)
3222 return -ENOMEM;
3223
3224 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size);
3225 if (r)
3226 goto out;
3227
3228 filp->private_data = buf;
3229
3230 return 0;
3231
3232 out:
3233 kvfree(buf);
3234 return r;
3235 }
3236
smu_stb_debugfs_read(struct file * filp,char __user * buf,size_t size,loff_t * pos)3237 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
3238 loff_t *pos)
3239 {
3240 struct amdgpu_device *adev = filp->f_inode->i_private;
3241 struct smu_context *smu = adev->powerplay.pp_handle;
3242
3243
3244 if (!filp->private_data)
3245 return -EINVAL;
3246
3247 return simple_read_from_buffer(buf,
3248 size,
3249 pos, filp->private_data,
3250 smu->stb_context.stb_buf_size);
3251 }
3252
smu_stb_debugfs_release(struct inode * inode,struct file * filp)3253 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp)
3254 {
3255 kvfree(filp->private_data);
3256 filp->private_data = NULL;
3257
3258 return 0;
3259 }
3260
3261 /*
3262 * We have to define not only read method but also
3263 * open and release because .read takes up to PAGE_SIZE
3264 * data each time so and so is invoked multiple times.
3265 * We allocate the STB buffer in .open and release it
3266 * in .release
3267 */
3268 static const struct file_operations smu_stb_debugfs_fops = {
3269 .owner = THIS_MODULE,
3270 .open = smu_stb_debugfs_open,
3271 .read = smu_stb_debugfs_read,
3272 .release = smu_stb_debugfs_release,
3273 .llseek = default_llseek,
3274 };
3275
3276 #endif
3277
amdgpu_smu_stb_debug_fs_init(struct amdgpu_device * adev)3278 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev)
3279 {
3280 #if defined(CONFIG_DEBUG_FS)
3281
3282 struct smu_context *smu = adev->powerplay.pp_handle;
3283
3284 if (!smu || (!smu->stb_context.stb_buf_size))
3285 return;
3286
3287 debugfs_create_file_size("amdgpu_smu_stb_dump",
3288 S_IRUSR,
3289 adev_to_drm(adev)->primary->debugfs_root,
3290 adev,
3291 &smu_stb_debugfs_fops,
3292 smu->stb_context.stb_buf_size);
3293 #endif
3294 }
3295
smu_send_hbm_bad_pages_num(struct smu_context * smu,uint32_t size)3296 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size)
3297 {
3298 int ret = 0;
3299
3300 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num)
3301 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size);
3302
3303 return ret;
3304 }
3305
smu_send_hbm_bad_channel_flag(struct smu_context * smu,uint32_t size)3306 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size)
3307 {
3308 int ret = 0;
3309
3310 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag)
3311 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size);
3312
3313 return ret;
3314 }
3315