1 /*
2 * Shakti C-class SoC emulation
3 *
4 * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include "qemu/osdep.h"
20 #include "hw/boards.h"
21 #include "hw/riscv/shakti_c.h"
22 #include "qapi/error.h"
23 #include "qemu/error-report.h"
24 #include "hw/intc/sifive_plic.h"
25 #include "hw/intc/riscv_aclint.h"
26 #include "sysemu/sysemu.h"
27 #include "hw/qdev-properties.h"
28 #include "exec/address-spaces.h"
29 #include "hw/riscv/boot.h"
30
31 static const struct MemmapEntry {
32 hwaddr base;
33 hwaddr size;
34 } shakti_c_memmap[] = {
35 [SHAKTI_C_ROM] = { 0x00001000, 0x2000 },
36 [SHAKTI_C_RAM] = { 0x80000000, 0x0 },
37 [SHAKTI_C_UART] = { 0x00011300, 0x00040 },
38 [SHAKTI_C_GPIO] = { 0x020d0000, 0x00100 },
39 [SHAKTI_C_PLIC] = { 0x0c000000, 0x20000 },
40 [SHAKTI_C_CLINT] = { 0x02000000, 0xc0000 },
41 [SHAKTI_C_I2C] = { 0x20c00000, 0x00100 },
42 };
43
shakti_c_machine_state_init(MachineState * mstate)44 static void shakti_c_machine_state_init(MachineState *mstate)
45 {
46 ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
47 MemoryRegion *system_memory = get_system_memory();
48 hwaddr firmware_load_addr = shakti_c_memmap[SHAKTI_C_RAM].base;
49
50 /* Initialize SoC */
51 object_initialize_child(OBJECT(mstate), "soc", &sms->soc,
52 TYPE_RISCV_SHAKTI_SOC);
53 qdev_realize(DEVICE(&sms->soc), NULL, &error_abort);
54
55 /* register RAM */
56 memory_region_add_subregion(system_memory,
57 shakti_c_memmap[SHAKTI_C_RAM].base,
58 mstate->ram);
59
60 if (mstate->firmware) {
61 riscv_load_firmware(mstate->firmware, &firmware_load_addr, NULL);
62 }
63
64 /* ROM reset vector */
65 riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus, firmware_load_addr,
66 shakti_c_memmap[SHAKTI_C_ROM].base,
67 shakti_c_memmap[SHAKTI_C_ROM].size, 0, 0);
68 }
69
shakti_c_machine_instance_init(Object * obj)70 static void shakti_c_machine_instance_init(Object *obj)
71 {
72 }
73
shakti_c_machine_class_init(ObjectClass * klass,void * data)74 static void shakti_c_machine_class_init(ObjectClass *klass, void *data)
75 {
76 MachineClass *mc = MACHINE_CLASS(klass);
77 static const char * const valid_cpu_types[] = {
78 RISCV_CPU_TYPE_NAME("shakti-c"),
79 NULL
80 };
81
82 mc->desc = "RISC-V Board compatible with Shakti SDK";
83 mc->init = shakti_c_machine_state_init;
84 mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C;
85 mc->valid_cpu_types = valid_cpu_types;
86 mc->default_ram_id = "riscv.shakti.c.ram";
87 }
88
89 static const TypeInfo shakti_c_machine_type_info = {
90 .name = TYPE_RISCV_SHAKTI_MACHINE,
91 .parent = TYPE_MACHINE,
92 .class_init = shakti_c_machine_class_init,
93 .instance_init = shakti_c_machine_instance_init,
94 .instance_size = sizeof(ShaktiCMachineState),
95 };
96
shakti_c_machine_type_info_register(void)97 static void shakti_c_machine_type_info_register(void)
98 {
99 type_register_static(&shakti_c_machine_type_info);
100 }
type_init(shakti_c_machine_type_info_register)101 type_init(shakti_c_machine_type_info_register)
102
103 static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
104 {
105 MachineState *ms = MACHINE(qdev_get_machine());
106 ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(dev);
107 MemoryRegion *system_memory = get_system_memory();
108
109 sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort);
110
111 sss->plic = sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base,
112 (char *)SHAKTI_C_PLIC_HART_CONFIG, ms->smp.cpus, 0,
113 SHAKTI_C_PLIC_NUM_SOURCES,
114 SHAKTI_C_PLIC_NUM_PRIORITIES,
115 SHAKTI_C_PLIC_PRIORITY_BASE,
116 SHAKTI_C_PLIC_PENDING_BASE,
117 SHAKTI_C_PLIC_ENABLE_BASE,
118 SHAKTI_C_PLIC_ENABLE_STRIDE,
119 SHAKTI_C_PLIC_CONTEXT_BASE,
120 SHAKTI_C_PLIC_CONTEXT_STRIDE,
121 shakti_c_memmap[SHAKTI_C_PLIC].size);
122
123 riscv_aclint_swi_create(shakti_c_memmap[SHAKTI_C_CLINT].base,
124 0, 1, false);
125 riscv_aclint_mtimer_create(shakti_c_memmap[SHAKTI_C_CLINT].base +
126 RISCV_ACLINT_SWI_SIZE,
127 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, 1,
128 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
129 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false);
130
131 qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0));
132 if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) {
133 return;
134 }
135 sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0,
136 shakti_c_memmap[SHAKTI_C_UART].base);
137
138 /* ROM */
139 memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
140 shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
141 memory_region_add_subregion(system_memory,
142 shakti_c_memmap[SHAKTI_C_ROM].base, &sss->rom);
143 }
144
shakti_c_soc_class_init(ObjectClass * klass,void * data)145 static void shakti_c_soc_class_init(ObjectClass *klass, void *data)
146 {
147 DeviceClass *dc = DEVICE_CLASS(klass);
148 dc->realize = shakti_c_soc_state_realize;
149 /*
150 * Reasons:
151 * - Creates CPUS in riscv_hart_realize(), and can create unintended
152 * CPUs
153 * - Uses serial_hds in realize function, thus can't be used twice
154 */
155 dc->user_creatable = false;
156 }
157
shakti_c_soc_instance_init(Object * obj)158 static void shakti_c_soc_instance_init(Object *obj)
159 {
160 ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
161
162 object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
163 object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART);
164
165 /*
166 * CPU type is fixed and we are not supporting passing from commandline yet.
167 * So let it be in instance_init. When supported should use ms->cpu_type
168 * instead of TYPE_RISCV_CPU_SHAKTI_C
169 */
170 object_property_set_str(OBJECT(&sss->cpus), "cpu-type",
171 TYPE_RISCV_CPU_SHAKTI_C, &error_abort);
172 object_property_set_int(OBJECT(&sss->cpus), "num-harts", 1,
173 &error_abort);
174 }
175
176 static const TypeInfo shakti_c_type_info = {
177 .name = TYPE_RISCV_SHAKTI_SOC,
178 .parent = TYPE_DEVICE,
179 .class_init = shakti_c_soc_class_init,
180 .instance_init = shakti_c_soc_instance_init,
181 .instance_size = sizeof(ShaktiCSoCState),
182 };
183
shakti_c_type_info_register(void)184 static void shakti_c_type_info_register(void)
185 {
186 type_register_static(&shakti_c_type_info);
187 }
188 type_init(shakti_c_type_info_register)
189