1 /*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/acpi.h>
34 #include <linux/etherdevice.h>
35 #include <linux/interrupt.h>
36 #include <linux/iopoll.h>
37 #include <linux/kernel.h>
38 #include <linux/types.h>
39 #include <net/addrconf.h>
40 #include <rdma/ib_addr.h>
41 #include <rdma/ib_cache.h>
42 #include <rdma/ib_umem.h>
43 #include <rdma/uverbs_ioctl.h>
44
45 #include "hnae3.h"
46 #include "hns_roce_common.h"
47 #include "hns_roce_device.h"
48 #include "hns_roce_cmd.h"
49 #include "hns_roce_hem.h"
50 #include "hns_roce_hw_v2.h"
51
52 enum {
53 CMD_RST_PRC_OTHERS,
54 CMD_RST_PRC_SUCCESS,
55 CMD_RST_PRC_EBUSY,
56 };
57
58 enum ecc_resource_type {
59 ECC_RESOURCE_QPC,
60 ECC_RESOURCE_CQC,
61 ECC_RESOURCE_MPT,
62 ECC_RESOURCE_SRQC,
63 ECC_RESOURCE_GMV,
64 ECC_RESOURCE_QPC_TIMER,
65 ECC_RESOURCE_CQC_TIMER,
66 ECC_RESOURCE_SCCC,
67 ECC_RESOURCE_COUNT,
68 };
69
70 static const struct {
71 const char *name;
72 u8 read_bt0_op;
73 u8 write_bt0_op;
74 } fmea_ram_res[] = {
75 { "ECC_RESOURCE_QPC",
76 HNS_ROCE_CMD_READ_QPC_BT0, HNS_ROCE_CMD_WRITE_QPC_BT0 },
77 { "ECC_RESOURCE_CQC",
78 HNS_ROCE_CMD_READ_CQC_BT0, HNS_ROCE_CMD_WRITE_CQC_BT0 },
79 { "ECC_RESOURCE_MPT",
80 HNS_ROCE_CMD_READ_MPT_BT0, HNS_ROCE_CMD_WRITE_MPT_BT0 },
81 { "ECC_RESOURCE_SRQC",
82 HNS_ROCE_CMD_READ_SRQC_BT0, HNS_ROCE_CMD_WRITE_SRQC_BT0 },
83 /* ECC_RESOURCE_GMV is handled by cmdq, not mailbox */
84 { "ECC_RESOURCE_GMV",
85 0, 0 },
86 { "ECC_RESOURCE_QPC_TIMER",
87 HNS_ROCE_CMD_READ_QPC_TIMER_BT0, HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 },
88 { "ECC_RESOURCE_CQC_TIMER",
89 HNS_ROCE_CMD_READ_CQC_TIMER_BT0, HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 },
90 { "ECC_RESOURCE_SCCC",
91 HNS_ROCE_CMD_READ_SCCC_BT0, HNS_ROCE_CMD_WRITE_SCCC_BT0 },
92 };
93
set_data_seg_v2(struct hns_roce_v2_wqe_data_seg * dseg,struct ib_sge * sg)94 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
95 struct ib_sge *sg)
96 {
97 dseg->lkey = cpu_to_le32(sg->lkey);
98 dseg->addr = cpu_to_le64(sg->addr);
99 dseg->len = cpu_to_le32(sg->length);
100 }
101
102 /*
103 * mapped-value = 1 + real-value
104 * The hns wr opcode real value is start from 0, In order to distinguish between
105 * initialized and uninitialized map values, we plus 1 to the actual value when
106 * defining the mapping, so that the validity can be identified by checking the
107 * mapped value is greater than 0.
108 */
109 #define HR_OPC_MAP(ib_key, hr_key) \
110 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key
111
112 static const u32 hns_roce_op_code[] = {
113 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE),
114 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM),
115 HR_OPC_MAP(SEND, SEND),
116 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM),
117 HR_OPC_MAP(RDMA_READ, RDMA_READ),
118 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP),
119 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD),
120 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV),
121 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP),
122 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD),
123 HR_OPC_MAP(REG_MR, FAST_REG_PMR),
124 };
125
to_hr_opcode(u32 ib_opcode)126 static u32 to_hr_opcode(u32 ib_opcode)
127 {
128 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code))
129 return HNS_ROCE_V2_WQE_OP_MASK;
130
131 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 :
132 HNS_ROCE_V2_WQE_OP_MASK;
133 }
134
set_frmr_seg(struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,const struct ib_reg_wr * wr)135 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
136 const struct ib_reg_wr *wr)
137 {
138 struct hns_roce_wqe_frmr_seg *fseg =
139 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
140 struct hns_roce_mr *mr = to_hr_mr(wr->mr);
141 u64 pbl_ba;
142
143 /* use ib_access_flags */
144 hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND);
145 hr_reg_write_bool(fseg, FRMR_ATOMIC,
146 wr->access & IB_ACCESS_REMOTE_ATOMIC);
147 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ);
148 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE);
149 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE);
150
151 /* Data structure reuse may lead to confusion */
152 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba;
153 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba));
154 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba));
155
156 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff);
157 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32);
158 rc_sq_wqe->rkey = cpu_to_le32(wr->key);
159 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova);
160
161 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages);
162 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ,
163 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
164 hr_reg_clear(fseg, FRMR_BLK_MODE);
165 }
166
set_atomic_seg(const struct ib_send_wr * wr,struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,unsigned int valid_num_sge)167 static void set_atomic_seg(const struct ib_send_wr *wr,
168 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
169 unsigned int valid_num_sge)
170 {
171 struct hns_roce_v2_wqe_data_seg *dseg =
172 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
173 struct hns_roce_wqe_atomic_seg *aseg =
174 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg);
175
176 set_data_seg_v2(dseg, wr->sg_list);
177
178 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
179 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap);
180 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add);
181 } else {
182 aseg->fetchadd_swap_data =
183 cpu_to_le64(atomic_wr(wr)->compare_add);
184 aseg->cmp_data = 0;
185 }
186
187 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge);
188 }
189
fill_ext_sge_inl_data(struct hns_roce_qp * qp,const struct ib_send_wr * wr,unsigned int * sge_idx,u32 msg_len)190 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp,
191 const struct ib_send_wr *wr,
192 unsigned int *sge_idx, u32 msg_len)
193 {
194 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev;
195 unsigned int left_len_in_pg;
196 unsigned int idx = *sge_idx;
197 unsigned int i = 0;
198 unsigned int len;
199 void *addr;
200 void *dseg;
201
202 if (msg_len > qp->sq.ext_sge_cnt * HNS_ROCE_SGE_SIZE) {
203 ibdev_err(ibdev,
204 "no enough extended sge space for inline data.\n");
205 return -EINVAL;
206 }
207
208 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1));
209 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg;
210 len = wr->sg_list[0].length;
211 addr = (void *)(unsigned long)(wr->sg_list[0].addr);
212
213 /* When copying data to extended sge space, the left length in page may
214 * not long enough for current user's sge. So the data should be
215 * splited into several parts, one in the first page, and the others in
216 * the subsequent pages.
217 */
218 while (1) {
219 if (len <= left_len_in_pg) {
220 memcpy(dseg, addr, len);
221
222 idx += len / HNS_ROCE_SGE_SIZE;
223
224 i++;
225 if (i >= wr->num_sge)
226 break;
227
228 left_len_in_pg -= len;
229 len = wr->sg_list[i].length;
230 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
231 dseg += len;
232 } else {
233 memcpy(dseg, addr, left_len_in_pg);
234
235 len -= left_len_in_pg;
236 addr += left_len_in_pg;
237 idx += left_len_in_pg / HNS_ROCE_SGE_SIZE;
238 dseg = hns_roce_get_extend_sge(qp,
239 idx & (qp->sge.sge_cnt - 1));
240 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT;
241 }
242 }
243
244 *sge_idx = idx;
245
246 return 0;
247 }
248
set_extend_sge(struct hns_roce_qp * qp,struct ib_sge * sge,unsigned int * sge_ind,unsigned int cnt)249 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge,
250 unsigned int *sge_ind, unsigned int cnt)
251 {
252 struct hns_roce_v2_wqe_data_seg *dseg;
253 unsigned int idx = *sge_ind;
254
255 while (cnt > 0) {
256 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1));
257 if (likely(sge->length)) {
258 set_data_seg_v2(dseg, sge);
259 idx++;
260 cnt--;
261 }
262 sge++;
263 }
264
265 *sge_ind = idx;
266 }
267
check_inl_data_len(struct hns_roce_qp * qp,unsigned int len)268 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len)
269 {
270 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
271 int mtu = ib_mtu_enum_to_int(qp->path_mtu);
272
273 if (mtu < 0 || len > qp->max_inline_data || len > mtu) {
274 ibdev_err(&hr_dev->ib_dev,
275 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n",
276 len, qp->max_inline_data, mtu);
277 return false;
278 }
279
280 return true;
281 }
282
set_rc_inl(struct hns_roce_qp * qp,const struct ib_send_wr * wr,struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,unsigned int * sge_idx)283 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr,
284 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
285 unsigned int *sge_idx)
286 {
287 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
288 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len);
289 struct ib_device *ibdev = &hr_dev->ib_dev;
290 unsigned int curr_idx = *sge_idx;
291 void *dseg = rc_sq_wqe;
292 unsigned int i;
293 int ret;
294
295 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) {
296 ibdev_err(ibdev, "invalid inline parameters!\n");
297 return -EINVAL;
298 }
299
300 if (!check_inl_data_len(qp, msg_len))
301 return -EINVAL;
302
303 dseg += sizeof(struct hns_roce_v2_rc_send_wqe);
304
305 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) {
306 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE);
307
308 for (i = 0; i < wr->num_sge; i++) {
309 memcpy(dseg, ((void *)wr->sg_list[i].addr),
310 wr->sg_list[i].length);
311 dseg += wr->sg_list[i].length;
312 }
313 } else {
314 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE);
315
316 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len);
317 if (ret)
318 return ret;
319
320 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx);
321 }
322
323 *sge_idx = curr_idx;
324
325 return 0;
326 }
327
set_rwqe_data_seg(struct ib_qp * ibqp,const struct ib_send_wr * wr,struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,unsigned int * sge_ind,unsigned int valid_num_sge)328 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr,
329 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
330 unsigned int *sge_ind,
331 unsigned int valid_num_sge)
332 {
333 struct hns_roce_v2_wqe_data_seg *dseg =
334 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
335 struct hns_roce_qp *qp = to_hr_qp(ibqp);
336 int j = 0;
337 int i;
338
339 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX,
340 (*sge_ind) & (qp->sge.sge_cnt - 1));
341
342 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE,
343 !!(wr->send_flags & IB_SEND_INLINE));
344 if (wr->send_flags & IB_SEND_INLINE)
345 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind);
346
347 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) {
348 for (i = 0; i < wr->num_sge; i++) {
349 if (likely(wr->sg_list[i].length)) {
350 set_data_seg_v2(dseg, wr->sg_list + i);
351 dseg++;
352 }
353 }
354 } else {
355 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) {
356 if (likely(wr->sg_list[i].length)) {
357 set_data_seg_v2(dseg, wr->sg_list + i);
358 dseg++;
359 j++;
360 }
361 }
362
363 set_extend_sge(qp, wr->sg_list + i, sge_ind,
364 valid_num_sge - HNS_ROCE_SGE_IN_WQE);
365 }
366
367 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge);
368
369 return 0;
370 }
371
check_send_valid(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp)372 static int check_send_valid(struct hns_roce_dev *hr_dev,
373 struct hns_roce_qp *hr_qp)
374 {
375 if (unlikely(hr_qp->state == IB_QPS_RESET ||
376 hr_qp->state == IB_QPS_INIT ||
377 hr_qp->state == IB_QPS_RTR))
378 return -EINVAL;
379 else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN))
380 return -EIO;
381
382 return 0;
383 }
384
calc_wr_sge_num(const struct ib_send_wr * wr,unsigned int * sge_len)385 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr,
386 unsigned int *sge_len)
387 {
388 unsigned int valid_num = 0;
389 unsigned int len = 0;
390 int i;
391
392 for (i = 0; i < wr->num_sge; i++) {
393 if (likely(wr->sg_list[i].length)) {
394 len += wr->sg_list[i].length;
395 valid_num++;
396 }
397 }
398
399 *sge_len = len;
400 return valid_num;
401 }
402
get_immtdata(const struct ib_send_wr * wr)403 static __le32 get_immtdata(const struct ib_send_wr *wr)
404 {
405 switch (wr->opcode) {
406 case IB_WR_SEND_WITH_IMM:
407 case IB_WR_RDMA_WRITE_WITH_IMM:
408 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
409 default:
410 return 0;
411 }
412 }
413
set_ud_opcode(struct hns_roce_v2_ud_send_wqe * ud_sq_wqe,const struct ib_send_wr * wr)414 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe,
415 const struct ib_send_wr *wr)
416 {
417 u32 ib_op = wr->opcode;
418
419 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM)
420 return -EINVAL;
421
422 ud_sq_wqe->immtdata = get_immtdata(wr);
423
424 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op));
425
426 return 0;
427 }
428
fill_ud_av(struct hns_roce_v2_ud_send_wqe * ud_sq_wqe,struct hns_roce_ah * ah)429 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe,
430 struct hns_roce_ah *ah)
431 {
432 struct ib_device *ib_dev = ah->ibah.device;
433 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
434
435 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport);
436 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit);
437 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass);
438 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel);
439
440 if (WARN_ON(ah->av.sl > MAX_SERVICE_LEVEL))
441 return -EINVAL;
442
443 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl);
444
445 ud_sq_wqe->sgid_index = ah->av.gid_index;
446
447 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN);
448 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2);
449
450 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
451 return 0;
452
453 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en);
454 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id);
455
456 return 0;
457 }
458
set_ud_wqe(struct hns_roce_qp * qp,const struct ib_send_wr * wr,void * wqe,unsigned int * sge_idx,unsigned int owner_bit)459 static inline int set_ud_wqe(struct hns_roce_qp *qp,
460 const struct ib_send_wr *wr,
461 void *wqe, unsigned int *sge_idx,
462 unsigned int owner_bit)
463 {
464 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
465 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe;
466 unsigned int curr_idx = *sge_idx;
467 unsigned int valid_num_sge;
468 u32 msg_len = 0;
469 int ret;
470
471 valid_num_sge = calc_wr_sge_num(wr, &msg_len);
472
473 ret = set_ud_opcode(ud_sq_wqe, wr);
474 if (WARN_ON_ONCE(ret))
475 return ret;
476
477 ud_sq_wqe->msg_len = cpu_to_le32(msg_len);
478
479 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE,
480 !!(wr->send_flags & IB_SEND_SIGNALED));
481 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE,
482 !!(wr->send_flags & IB_SEND_SOLICITED));
483
484 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn);
485 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge);
486 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX,
487 curr_idx & (qp->sge.sge_cnt - 1));
488
489 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ?
490 qp->qkey : ud_wr(wr)->remote_qkey);
491 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn);
492
493 ret = fill_ud_av(ud_sq_wqe, ah);
494 if (ret)
495 return ret;
496
497 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl;
498
499 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge);
500
501 /*
502 * The pipeline can sequentially post all valid WQEs into WQ buffer,
503 * including new WQEs waiting for the doorbell to update the PI again.
504 * Therefore, the owner bit of WQE MUST be updated after all fields
505 * and extSGEs have been written into DDR instead of cache.
506 */
507 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
508 dma_wmb();
509
510 *sge_idx = curr_idx;
511 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit);
512
513 return 0;
514 }
515
set_rc_opcode(struct hns_roce_dev * hr_dev,struct hns_roce_v2_rc_send_wqe * rc_sq_wqe,const struct ib_send_wr * wr)516 static int set_rc_opcode(struct hns_roce_dev *hr_dev,
517 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
518 const struct ib_send_wr *wr)
519 {
520 u32 ib_op = wr->opcode;
521 int ret = 0;
522
523 rc_sq_wqe->immtdata = get_immtdata(wr);
524
525 switch (ib_op) {
526 case IB_WR_RDMA_READ:
527 case IB_WR_RDMA_WRITE:
528 case IB_WR_RDMA_WRITE_WITH_IMM:
529 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey);
530 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr);
531 break;
532 case IB_WR_SEND:
533 case IB_WR_SEND_WITH_IMM:
534 break;
535 case IB_WR_ATOMIC_CMP_AND_SWP:
536 case IB_WR_ATOMIC_FETCH_AND_ADD:
537 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey);
538 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr);
539 break;
540 case IB_WR_REG_MR:
541 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
542 set_frmr_seg(rc_sq_wqe, reg_wr(wr));
543 else
544 ret = -EOPNOTSUPP;
545 break;
546 case IB_WR_SEND_WITH_INV:
547 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey);
548 break;
549 default:
550 ret = -EINVAL;
551 }
552
553 if (unlikely(ret))
554 return ret;
555
556 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op));
557
558 return ret;
559 }
560
set_rc_wqe(struct hns_roce_qp * qp,const struct ib_send_wr * wr,void * wqe,unsigned int * sge_idx,unsigned int owner_bit)561 static inline int set_rc_wqe(struct hns_roce_qp *qp,
562 const struct ib_send_wr *wr,
563 void *wqe, unsigned int *sge_idx,
564 unsigned int owner_bit)
565 {
566 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
567 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
568 unsigned int curr_idx = *sge_idx;
569 unsigned int valid_num_sge;
570 u32 msg_len = 0;
571 int ret;
572
573 valid_num_sge = calc_wr_sge_num(wr, &msg_len);
574
575 rc_sq_wqe->msg_len = cpu_to_le32(msg_len);
576
577 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr);
578 if (WARN_ON_ONCE(ret))
579 return ret;
580
581 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SO,
582 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
583
584 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE,
585 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
586
587 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE,
588 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
589
590 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
591 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) {
592 if (msg_len != ATOMIC_WR_LEN)
593 return -EINVAL;
594 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge);
595 } else if (wr->opcode != IB_WR_REG_MR) {
596 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe,
597 &curr_idx, valid_num_sge);
598 if (ret)
599 return ret;
600 }
601
602 /*
603 * The pipeline can sequentially post all valid WQEs into WQ buffer,
604 * including new WQEs waiting for the doorbell to update the PI again.
605 * Therefore, the owner bit of WQE MUST be updated after all fields
606 * and extSGEs have been written into DDR instead of cache.
607 */
608 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
609 dma_wmb();
610
611 *sge_idx = curr_idx;
612 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit);
613
614 return ret;
615 }
616
update_sq_db(struct hns_roce_dev * hr_dev,struct hns_roce_qp * qp)617 static inline void update_sq_db(struct hns_roce_dev *hr_dev,
618 struct hns_roce_qp *qp)
619 {
620 if (unlikely(qp->state == IB_QPS_ERR)) {
621 flush_cqe(hr_dev, qp);
622 } else {
623 struct hns_roce_v2_db sq_db = {};
624
625 hr_reg_write(&sq_db, DB_TAG, qp->qpn);
626 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB);
627 hr_reg_write(&sq_db, DB_PI, qp->sq.head);
628 hr_reg_write(&sq_db, DB_SL, qp->sl);
629
630 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg);
631 }
632 }
633
update_rq_db(struct hns_roce_dev * hr_dev,struct hns_roce_qp * qp)634 static inline void update_rq_db(struct hns_roce_dev *hr_dev,
635 struct hns_roce_qp *qp)
636 {
637 if (unlikely(qp->state == IB_QPS_ERR)) {
638 flush_cqe(hr_dev, qp);
639 } else {
640 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) {
641 *qp->rdb.db_record =
642 qp->rq.head & V2_DB_PRODUCER_IDX_M;
643 } else {
644 struct hns_roce_v2_db rq_db = {};
645
646 hr_reg_write(&rq_db, DB_TAG, qp->qpn);
647 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB);
648 hr_reg_write(&rq_db, DB_PI, qp->rq.head);
649
650 hns_roce_write64(hr_dev, (__le32 *)&rq_db,
651 qp->rq.db_reg);
652 }
653 }
654 }
655
hns_roce_write512(struct hns_roce_dev * hr_dev,u64 * val,u64 __iomem * dest)656 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val,
657 u64 __iomem *dest)
658 {
659 #define HNS_ROCE_WRITE_TIMES 8
660 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
661 struct hnae3_handle *handle = priv->handle;
662 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
663 int i;
664
665 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle))
666 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++)
667 writeq_relaxed(*(val + i), dest + i);
668 }
669
write_dwqe(struct hns_roce_dev * hr_dev,struct hns_roce_qp * qp,void * wqe)670 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
671 void *wqe)
672 {
673 #define HNS_ROCE_SL_SHIFT 2
674 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
675
676 if (unlikely(qp->state == IB_QPS_ERR)) {
677 flush_cqe(hr_dev, qp);
678 return;
679 }
680 /* All kinds of DirectWQE have the same header field layout */
681 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG);
682 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl);
683 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H,
684 qp->sl >> HNS_ROCE_SL_SHIFT);
685 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head);
686
687 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg);
688 }
689
hns_roce_v2_post_send(struct ib_qp * ibqp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr)690 static int hns_roce_v2_post_send(struct ib_qp *ibqp,
691 const struct ib_send_wr *wr,
692 const struct ib_send_wr **bad_wr)
693 {
694 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
695 struct ib_device *ibdev = &hr_dev->ib_dev;
696 struct hns_roce_qp *qp = to_hr_qp(ibqp);
697 unsigned long flags = 0;
698 unsigned int owner_bit;
699 unsigned int sge_idx;
700 unsigned int wqe_idx;
701 void *wqe = NULL;
702 u32 nreq;
703 int ret;
704
705 spin_lock_irqsave(&qp->sq.lock, flags);
706
707 ret = check_send_valid(hr_dev, qp);
708 if (unlikely(ret)) {
709 *bad_wr = wr;
710 nreq = 0;
711 goto out;
712 }
713
714 sge_idx = qp->next_sge;
715
716 for (nreq = 0; wr; ++nreq, wr = wr->next) {
717 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
718 ret = -ENOMEM;
719 *bad_wr = wr;
720 goto out;
721 }
722
723 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1);
724
725 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
726 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n",
727 wr->num_sge, qp->sq.max_gs);
728 ret = -EINVAL;
729 *bad_wr = wr;
730 goto out;
731 }
732
733 wqe = hns_roce_get_send_wqe(qp, wqe_idx);
734 qp->sq.wrid[wqe_idx] = wr->wr_id;
735 owner_bit =
736 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1);
737
738 /* Corresponding to the QP type, wqe process separately */
739 if (ibqp->qp_type == IB_QPT_RC)
740 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit);
741 else
742 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit);
743
744 if (unlikely(ret)) {
745 *bad_wr = wr;
746 goto out;
747 }
748 }
749
750 out:
751 if (likely(nreq)) {
752 qp->sq.head += nreq;
753 qp->next_sge = sge_idx;
754
755 if (nreq == 1 && !ret &&
756 (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE))
757 write_dwqe(hr_dev, qp, wqe);
758 else
759 update_sq_db(hr_dev, qp);
760 }
761
762 spin_unlock_irqrestore(&qp->sq.lock, flags);
763
764 return ret;
765 }
766
check_recv_valid(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp)767 static int check_recv_valid(struct hns_roce_dev *hr_dev,
768 struct hns_roce_qp *hr_qp)
769 {
770 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN))
771 return -EIO;
772
773 if (hr_qp->state == IB_QPS_RESET)
774 return -EINVAL;
775
776 return 0;
777 }
778
fill_recv_sge_to_wqe(const struct ib_recv_wr * wr,void * wqe,u32 max_sge,bool rsv)779 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe,
780 u32 max_sge, bool rsv)
781 {
782 struct hns_roce_v2_wqe_data_seg *dseg = wqe;
783 u32 i, cnt;
784
785 for (i = 0, cnt = 0; i < wr->num_sge; i++) {
786 /* Skip zero-length sge */
787 if (!wr->sg_list[i].length)
788 continue;
789 set_data_seg_v2(dseg + cnt, wr->sg_list + i);
790 cnt++;
791 }
792
793 /* Fill a reserved sge to make hw stop reading remaining segments */
794 if (rsv) {
795 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);
796 dseg[cnt].addr = 0;
797 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH);
798 } else {
799 /* Clear remaining segments to make ROCEE ignore sges */
800 if (cnt < max_sge)
801 memset(dseg + cnt, 0,
802 (max_sge - cnt) * HNS_ROCE_SGE_SIZE);
803 }
804 }
805
fill_rq_wqe(struct hns_roce_qp * hr_qp,const struct ib_recv_wr * wr,u32 wqe_idx,u32 max_sge)806 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr,
807 u32 wqe_idx, u32 max_sge)
808 {
809 void *wqe = NULL;
810
811 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx);
812 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge);
813 }
814
hns_roce_v2_post_recv(struct ib_qp * ibqp,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)815 static int hns_roce_v2_post_recv(struct ib_qp *ibqp,
816 const struct ib_recv_wr *wr,
817 const struct ib_recv_wr **bad_wr)
818 {
819 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
820 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
821 struct ib_device *ibdev = &hr_dev->ib_dev;
822 u32 wqe_idx, nreq, max_sge;
823 unsigned long flags;
824 int ret;
825
826 spin_lock_irqsave(&hr_qp->rq.lock, flags);
827
828 ret = check_recv_valid(hr_dev, hr_qp);
829 if (unlikely(ret)) {
830 *bad_wr = wr;
831 nreq = 0;
832 goto out;
833 }
834
835 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge;
836 for (nreq = 0; wr; ++nreq, wr = wr->next) {
837 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq,
838 hr_qp->ibqp.recv_cq))) {
839 ret = -ENOMEM;
840 *bad_wr = wr;
841 goto out;
842 }
843
844 if (unlikely(wr->num_sge > max_sge)) {
845 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n",
846 wr->num_sge, max_sge);
847 ret = -EINVAL;
848 *bad_wr = wr;
849 goto out;
850 }
851
852 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
853 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge);
854 hr_qp->rq.wrid[wqe_idx] = wr->wr_id;
855 }
856
857 out:
858 if (likely(nreq)) {
859 hr_qp->rq.head += nreq;
860
861 update_rq_db(hr_dev, hr_qp);
862 }
863 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
864
865 return ret;
866 }
867
get_srq_wqe_buf(struct hns_roce_srq * srq,u32 n)868 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n)
869 {
870 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift);
871 }
872
get_idx_buf(struct hns_roce_idx_que * idx_que,u32 n)873 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n)
874 {
875 return hns_roce_buf_offset(idx_que->mtr.kmem,
876 n << idx_que->entry_shift);
877 }
878
hns_roce_free_srq_wqe(struct hns_roce_srq * srq,u32 wqe_index)879 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index)
880 {
881 /* always called with interrupts disabled. */
882 spin_lock(&srq->lock);
883
884 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1);
885 srq->idx_que.tail++;
886
887 spin_unlock(&srq->lock);
888 }
889
hns_roce_srqwq_overflow(struct hns_roce_srq * srq)890 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq)
891 {
892 struct hns_roce_idx_que *idx_que = &srq->idx_que;
893
894 return idx_que->head - idx_que->tail >= srq->wqe_cnt;
895 }
896
check_post_srq_valid(struct hns_roce_srq * srq,u32 max_sge,const struct ib_recv_wr * wr)897 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge,
898 const struct ib_recv_wr *wr)
899 {
900 struct ib_device *ib_dev = srq->ibsrq.device;
901
902 if (unlikely(wr->num_sge > max_sge)) {
903 ibdev_err(ib_dev,
904 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n",
905 wr->num_sge, max_sge);
906 return -EINVAL;
907 }
908
909 if (unlikely(hns_roce_srqwq_overflow(srq))) {
910 ibdev_err(ib_dev,
911 "failed to check srqwq status, srqwq is full.\n");
912 return -ENOMEM;
913 }
914
915 return 0;
916 }
917
get_srq_wqe_idx(struct hns_roce_srq * srq,u32 * wqe_idx)918 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx)
919 {
920 struct hns_roce_idx_que *idx_que = &srq->idx_que;
921 u32 pos;
922
923 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt);
924 if (unlikely(pos == srq->wqe_cnt))
925 return -ENOSPC;
926
927 bitmap_set(idx_que->bitmap, pos, 1);
928 *wqe_idx = pos;
929 return 0;
930 }
931
fill_wqe_idx(struct hns_roce_srq * srq,unsigned int wqe_idx)932 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx)
933 {
934 struct hns_roce_idx_que *idx_que = &srq->idx_que;
935 unsigned int head;
936 __le32 *buf;
937
938 head = idx_que->head & (srq->wqe_cnt - 1);
939
940 buf = get_idx_buf(idx_que, head);
941 *buf = cpu_to_le32(wqe_idx);
942
943 idx_que->head++;
944 }
945
update_srq_db(struct hns_roce_v2_db * db,struct hns_roce_srq * srq)946 static void update_srq_db(struct hns_roce_v2_db *db, struct hns_roce_srq *srq)
947 {
948 hr_reg_write(db, DB_TAG, srq->srqn);
949 hr_reg_write(db, DB_CMD, HNS_ROCE_V2_SRQ_DB);
950 hr_reg_write(db, DB_PI, srq->idx_que.head);
951 }
952
hns_roce_v2_post_srq_recv(struct ib_srq * ibsrq,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)953 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq,
954 const struct ib_recv_wr *wr,
955 const struct ib_recv_wr **bad_wr)
956 {
957 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
958 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
959 struct hns_roce_v2_db srq_db;
960 unsigned long flags;
961 int ret = 0;
962 u32 max_sge;
963 u32 wqe_idx;
964 void *wqe;
965 u32 nreq;
966
967 spin_lock_irqsave(&srq->lock, flags);
968
969 max_sge = srq->max_gs - srq->rsv_sge;
970 for (nreq = 0; wr; ++nreq, wr = wr->next) {
971 ret = check_post_srq_valid(srq, max_sge, wr);
972 if (ret) {
973 *bad_wr = wr;
974 break;
975 }
976
977 ret = get_srq_wqe_idx(srq, &wqe_idx);
978 if (unlikely(ret)) {
979 *bad_wr = wr;
980 break;
981 }
982
983 wqe = get_srq_wqe_buf(srq, wqe_idx);
984 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge);
985 fill_wqe_idx(srq, wqe_idx);
986 srq->wrid[wqe_idx] = wr->wr_id;
987 }
988
989 if (likely(nreq)) {
990 update_srq_db(&srq_db, srq);
991
992 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg);
993 }
994
995 spin_unlock_irqrestore(&srq->lock, flags);
996
997 return ret;
998 }
999
hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev * hr_dev,unsigned long instance_stage,unsigned long reset_stage)1000 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev,
1001 unsigned long instance_stage,
1002 unsigned long reset_stage)
1003 {
1004 /* When hardware reset has been completed once or more, we should stop
1005 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance()
1006 * function, we should exit with error. If now at HNAE3_INIT_CLIENT
1007 * stage of soft reset process, we should exit with error, and then
1008 * HNAE3_INIT_CLIENT related process can rollback the operation like
1009 * notifing hardware to free resources, HNAE3_INIT_CLIENT related
1010 * process will exit with error to notify NIC driver to reschedule soft
1011 * reset process once again.
1012 */
1013 hr_dev->is_reset = true;
1014 hr_dev->dis_db = true;
1015
1016 if (reset_stage == HNS_ROCE_STATE_RST_INIT ||
1017 instance_stage == HNS_ROCE_STATE_INIT)
1018 return CMD_RST_PRC_EBUSY;
1019
1020 return CMD_RST_PRC_SUCCESS;
1021 }
1022
hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev * hr_dev,unsigned long instance_stage,unsigned long reset_stage)1023 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev,
1024 unsigned long instance_stage,
1025 unsigned long reset_stage)
1026 {
1027 #define HW_RESET_TIMEOUT_US 1000000
1028 #define HW_RESET_SLEEP_US 1000
1029
1030 struct hns_roce_v2_priv *priv = hr_dev->priv;
1031 struct hnae3_handle *handle = priv->handle;
1032 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1033 unsigned long val;
1034 int ret;
1035
1036 /* When hardware reset is detected, we should stop sending mailbox&cmq&
1037 * doorbell to hardware. If now in .init_instance() function, we should
1038 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset
1039 * process, we should exit with error, and then HNAE3_INIT_CLIENT
1040 * related process can rollback the operation like notifing hardware to
1041 * free resources, HNAE3_INIT_CLIENT related process will exit with
1042 * error to notify NIC driver to reschedule soft reset process once
1043 * again.
1044 */
1045 hr_dev->dis_db = true;
1046
1047 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val,
1048 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US,
1049 HW_RESET_TIMEOUT_US, false, handle);
1050 if (!ret)
1051 hr_dev->is_reset = true;
1052
1053 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT ||
1054 instance_stage == HNS_ROCE_STATE_INIT)
1055 return CMD_RST_PRC_EBUSY;
1056
1057 return CMD_RST_PRC_SUCCESS;
1058 }
1059
hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev * hr_dev)1060 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev)
1061 {
1062 struct hns_roce_v2_priv *priv = hr_dev->priv;
1063 struct hnae3_handle *handle = priv->handle;
1064 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1065
1066 /* When software reset is detected at .init_instance() function, we
1067 * should stop sending mailbox&cmq&doorbell to hardware, and exit
1068 * with error.
1069 */
1070 hr_dev->dis_db = true;
1071 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt)
1072 hr_dev->is_reset = true;
1073
1074 return CMD_RST_PRC_EBUSY;
1075 }
1076
check_aedev_reset_status(struct hns_roce_dev * hr_dev,struct hnae3_handle * handle)1077 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev,
1078 struct hnae3_handle *handle)
1079 {
1080 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1081 unsigned long instance_stage; /* the current instance stage */
1082 unsigned long reset_stage; /* the current reset stage */
1083 unsigned long reset_cnt;
1084 bool sw_resetting;
1085 bool hw_resetting;
1086
1087 /* Get information about reset from NIC driver or RoCE driver itself,
1088 * the meaning of the following variables from NIC driver are described
1089 * as below:
1090 * reset_cnt -- The count value of completed hardware reset.
1091 * hw_resetting -- Whether hardware device is resetting now.
1092 * sw_resetting -- Whether NIC's software reset process is running now.
1093 */
1094 instance_stage = handle->rinfo.instance_state;
1095 reset_stage = handle->rinfo.reset_state;
1096 reset_cnt = ops->ae_dev_reset_cnt(handle);
1097 if (reset_cnt != hr_dev->reset_cnt)
1098 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage,
1099 reset_stage);
1100
1101 hw_resetting = ops->get_cmdq_stat(handle);
1102 if (hw_resetting)
1103 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage,
1104 reset_stage);
1105
1106 sw_resetting = ops->ae_dev_resetting(handle);
1107 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT)
1108 return hns_roce_v2_cmd_sw_resetting(hr_dev);
1109
1110 return CMD_RST_PRC_OTHERS;
1111 }
1112
check_device_is_in_reset(struct hns_roce_dev * hr_dev)1113 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev)
1114 {
1115 struct hns_roce_v2_priv *priv = hr_dev->priv;
1116 struct hnae3_handle *handle = priv->handle;
1117 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1118
1119 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle))
1120 return true;
1121
1122 if (ops->get_hw_reset_stat(handle))
1123 return true;
1124
1125 if (ops->ae_dev_resetting(handle))
1126 return true;
1127
1128 return false;
1129 }
1130
v2_chk_mbox_is_avail(struct hns_roce_dev * hr_dev,bool * busy)1131 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy)
1132 {
1133 struct hns_roce_v2_priv *priv = hr_dev->priv;
1134 u32 status;
1135
1136 if (hr_dev->is_reset)
1137 status = CMD_RST_PRC_SUCCESS;
1138 else
1139 status = check_aedev_reset_status(hr_dev, priv->handle);
1140
1141 *busy = (status == CMD_RST_PRC_EBUSY);
1142
1143 return status == CMD_RST_PRC_OTHERS;
1144 }
1145
hns_roce_alloc_cmq_desc(struct hns_roce_dev * hr_dev,struct hns_roce_v2_cmq_ring * ring)1146 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
1147 struct hns_roce_v2_cmq_ring *ring)
1148 {
1149 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc);
1150
1151 ring->desc = dma_alloc_coherent(hr_dev->dev, size,
1152 &ring->desc_dma_addr, GFP_KERNEL);
1153 if (!ring->desc)
1154 return -ENOMEM;
1155
1156 return 0;
1157 }
1158
hns_roce_free_cmq_desc(struct hns_roce_dev * hr_dev,struct hns_roce_v2_cmq_ring * ring)1159 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
1160 struct hns_roce_v2_cmq_ring *ring)
1161 {
1162 dma_free_coherent(hr_dev->dev,
1163 ring->desc_num * sizeof(struct hns_roce_cmq_desc),
1164 ring->desc, ring->desc_dma_addr);
1165
1166 ring->desc_dma_addr = 0;
1167 }
1168
init_csq(struct hns_roce_dev * hr_dev,struct hns_roce_v2_cmq_ring * csq)1169 static int init_csq(struct hns_roce_dev *hr_dev,
1170 struct hns_roce_v2_cmq_ring *csq)
1171 {
1172 dma_addr_t dma;
1173 int ret;
1174
1175 csq->desc_num = CMD_CSQ_DESC_NUM;
1176 spin_lock_init(&csq->lock);
1177 csq->flag = TYPE_CSQ;
1178 csq->head = 0;
1179
1180 ret = hns_roce_alloc_cmq_desc(hr_dev, csq);
1181 if (ret)
1182 return ret;
1183
1184 dma = csq->desc_dma_addr;
1185 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma));
1186 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma));
1187 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
1188 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
1189
1190 /* Make sure to write CI first and then PI */
1191 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0);
1192 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0);
1193
1194 return 0;
1195 }
1196
hns_roce_v2_cmq_init(struct hns_roce_dev * hr_dev)1197 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
1198 {
1199 struct hns_roce_v2_priv *priv = hr_dev->priv;
1200 int ret;
1201
1202 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
1203
1204 ret = init_csq(hr_dev, &priv->cmq.csq);
1205 if (ret)
1206 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret);
1207
1208 return ret;
1209 }
1210
hns_roce_v2_cmq_exit(struct hns_roce_dev * hr_dev)1211 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
1212 {
1213 struct hns_roce_v2_priv *priv = hr_dev->priv;
1214
1215 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
1216 }
1217
hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc * desc,enum hns_roce_opcode_type opcode,bool is_read)1218 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
1219 enum hns_roce_opcode_type opcode,
1220 bool is_read)
1221 {
1222 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));
1223 desc->opcode = cpu_to_le16(opcode);
1224 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN);
1225 if (is_read)
1226 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);
1227 else
1228 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1229 }
1230
hns_roce_cmq_csq_done(struct hns_roce_dev * hr_dev)1231 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
1232 {
1233 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG);
1234 struct hns_roce_v2_priv *priv = hr_dev->priv;
1235
1236 return tail == priv->cmq.csq.head;
1237 }
1238
update_cmdq_status(struct hns_roce_dev * hr_dev)1239 static void update_cmdq_status(struct hns_roce_dev *hr_dev)
1240 {
1241 struct hns_roce_v2_priv *priv = hr_dev->priv;
1242 struct hnae3_handle *handle = priv->handle;
1243
1244 if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT ||
1245 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT)
1246 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR;
1247 }
1248
hns_roce_cmd_err_convert_errno(u16 desc_ret)1249 static int hns_roce_cmd_err_convert_errno(u16 desc_ret)
1250 {
1251 struct hns_roce_cmd_errcode errcode_table[] = {
1252 {CMD_EXEC_SUCCESS, 0},
1253 {CMD_NO_AUTH, -EPERM},
1254 {CMD_NOT_EXIST, -EOPNOTSUPP},
1255 {CMD_CRQ_FULL, -EXFULL},
1256 {CMD_NEXT_ERR, -ENOSR},
1257 {CMD_NOT_EXEC, -ENOTBLK},
1258 {CMD_PARA_ERR, -EINVAL},
1259 {CMD_RESULT_ERR, -ERANGE},
1260 {CMD_TIMEOUT, -ETIME},
1261 {CMD_HILINK_ERR, -ENOLINK},
1262 {CMD_INFO_ILLEGAL, -ENXIO},
1263 {CMD_INVALID, -EBADR},
1264 };
1265 u16 i;
1266
1267 for (i = 0; i < ARRAY_SIZE(errcode_table); i++)
1268 if (desc_ret == errcode_table[i].return_status)
1269 return errcode_table[i].errno;
1270 return -EIO;
1271 }
1272
__hns_roce_cmq_send(struct hns_roce_dev * hr_dev,struct hns_roce_cmq_desc * desc,int num)1273 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1274 struct hns_roce_cmq_desc *desc, int num)
1275 {
1276 struct hns_roce_v2_priv *priv = hr_dev->priv;
1277 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1278 u32 timeout = 0;
1279 u16 desc_ret;
1280 u32 tail;
1281 int ret;
1282 int i;
1283
1284 spin_lock_bh(&csq->lock);
1285
1286 tail = csq->head;
1287
1288 for (i = 0; i < num; i++) {
1289 csq->desc[csq->head++] = desc[i];
1290 if (csq->head == csq->desc_num)
1291 csq->head = 0;
1292 }
1293
1294 /* Write to hardware */
1295 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head);
1296
1297 do {
1298 if (hns_roce_cmq_csq_done(hr_dev))
1299 break;
1300 udelay(1);
1301 } while (++timeout < priv->cmq.tx_timeout);
1302
1303 if (hns_roce_cmq_csq_done(hr_dev)) {
1304 ret = 0;
1305 for (i = 0; i < num; i++) {
1306 /* check the result of hardware write back */
1307 desc[i] = csq->desc[tail++];
1308 if (tail == csq->desc_num)
1309 tail = 0;
1310
1311 desc_ret = le16_to_cpu(desc[i].retval);
1312 if (likely(desc_ret == CMD_EXEC_SUCCESS))
1313 continue;
1314
1315 dev_err_ratelimited(hr_dev->dev,
1316 "Cmdq IO error, opcode = 0x%x, return = 0x%x.\n",
1317 desc->opcode, desc_ret);
1318 ret = hns_roce_cmd_err_convert_errno(desc_ret);
1319 }
1320 } else {
1321 /* FW/HW reset or incorrect number of desc */
1322 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG);
1323 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n",
1324 csq->head, tail);
1325 csq->head = tail;
1326
1327 update_cmdq_status(hr_dev);
1328
1329 ret = -EAGAIN;
1330 }
1331
1332 spin_unlock_bh(&csq->lock);
1333
1334 return ret;
1335 }
1336
hns_roce_cmq_send(struct hns_roce_dev * hr_dev,struct hns_roce_cmq_desc * desc,int num)1337 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1338 struct hns_roce_cmq_desc *desc, int num)
1339 {
1340 bool busy;
1341 int ret;
1342
1343 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
1344 return -EIO;
1345
1346 if (!v2_chk_mbox_is_avail(hr_dev, &busy))
1347 return busy ? -EBUSY : 0;
1348
1349 ret = __hns_roce_cmq_send(hr_dev, desc, num);
1350 if (ret) {
1351 if (!v2_chk_mbox_is_avail(hr_dev, &busy))
1352 return busy ? -EBUSY : 0;
1353 }
1354
1355 return ret;
1356 }
1357
config_hem_ba_to_hw(struct hns_roce_dev * hr_dev,dma_addr_t base_addr,u8 cmd,unsigned long tag)1358 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev,
1359 dma_addr_t base_addr, u8 cmd, unsigned long tag)
1360 {
1361 struct hns_roce_cmd_mailbox *mbox;
1362 int ret;
1363
1364 mbox = hns_roce_alloc_cmd_mailbox(hr_dev);
1365 if (IS_ERR(mbox))
1366 return PTR_ERR(mbox);
1367
1368 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag);
1369 hns_roce_free_cmd_mailbox(hr_dev, mbox);
1370 return ret;
1371 }
1372
hns_roce_cmq_query_hw_info(struct hns_roce_dev * hr_dev)1373 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
1374 {
1375 struct hns_roce_query_version *resp;
1376 struct hns_roce_cmq_desc desc;
1377 int ret;
1378
1379 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true);
1380 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1381 if (ret)
1382 return ret;
1383
1384 resp = (struct hns_roce_query_version *)desc.data;
1385 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version);
1386 hr_dev->vendor_id = hr_dev->pci_dev->vendor;
1387
1388 return 0;
1389 }
1390
func_clr_hw_resetting_state(struct hns_roce_dev * hr_dev,struct hnae3_handle * handle)1391 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev,
1392 struct hnae3_handle *handle)
1393 {
1394 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1395 unsigned long end;
1396
1397 hr_dev->dis_db = true;
1398
1399 dev_warn(hr_dev->dev,
1400 "func clear is pending, device in resetting state.\n");
1401 end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1402 while (end) {
1403 if (!ops->get_hw_reset_stat(handle)) {
1404 hr_dev->is_reset = true;
1405 dev_info(hr_dev->dev,
1406 "func clear success after reset.\n");
1407 return;
1408 }
1409 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1410 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1411 }
1412
1413 dev_warn(hr_dev->dev, "func clear failed.\n");
1414 }
1415
func_clr_sw_resetting_state(struct hns_roce_dev * hr_dev,struct hnae3_handle * handle)1416 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev,
1417 struct hnae3_handle *handle)
1418 {
1419 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1420 unsigned long end;
1421
1422 hr_dev->dis_db = true;
1423
1424 dev_warn(hr_dev->dev,
1425 "func clear is pending, device in resetting state.\n");
1426 end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1427 while (end) {
1428 if (ops->ae_dev_reset_cnt(handle) !=
1429 hr_dev->reset_cnt) {
1430 hr_dev->is_reset = true;
1431 dev_info(hr_dev->dev,
1432 "func clear success after sw reset\n");
1433 return;
1434 }
1435 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1436 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1437 }
1438
1439 dev_warn(hr_dev->dev, "func clear failed because of unfinished sw reset\n");
1440 }
1441
hns_roce_func_clr_rst_proc(struct hns_roce_dev * hr_dev,int retval,int flag)1442 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval,
1443 int flag)
1444 {
1445 struct hns_roce_v2_priv *priv = hr_dev->priv;
1446 struct hnae3_handle *handle = priv->handle;
1447 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1448
1449 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) {
1450 hr_dev->dis_db = true;
1451 hr_dev->is_reset = true;
1452 dev_info(hr_dev->dev, "func clear success after reset.\n");
1453 return;
1454 }
1455
1456 if (ops->get_hw_reset_stat(handle)) {
1457 func_clr_hw_resetting_state(hr_dev, handle);
1458 return;
1459 }
1460
1461 if (ops->ae_dev_resetting(handle) &&
1462 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) {
1463 func_clr_sw_resetting_state(hr_dev, handle);
1464 return;
1465 }
1466
1467 if (retval && !flag)
1468 dev_warn(hr_dev->dev,
1469 "func clear read failed, ret = %d.\n", retval);
1470
1471 dev_warn(hr_dev->dev, "func clear failed.\n");
1472 }
1473
__hns_roce_function_clear(struct hns_roce_dev * hr_dev,int vf_id)1474 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id)
1475 {
1476 bool fclr_write_fail_flag = false;
1477 struct hns_roce_func_clear *resp;
1478 struct hns_roce_cmq_desc desc;
1479 unsigned long end;
1480 int ret = 0;
1481
1482 if (check_device_is_in_reset(hr_dev))
1483 goto out;
1484
1485 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false);
1486 resp = (struct hns_roce_func_clear *)desc.data;
1487 resp->rst_funcid_en = cpu_to_le32(vf_id);
1488
1489 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1490 if (ret) {
1491 fclr_write_fail_flag = true;
1492 dev_err(hr_dev->dev, "func clear write failed, ret = %d.\n",
1493 ret);
1494 goto out;
1495 }
1496
1497 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL);
1498 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS;
1499 while (end) {
1500 if (check_device_is_in_reset(hr_dev))
1501 goto out;
1502 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT);
1503 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT;
1504
1505 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR,
1506 true);
1507
1508 resp->rst_funcid_en = cpu_to_le32(vf_id);
1509 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1510 if (ret)
1511 continue;
1512
1513 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) {
1514 if (vf_id == 0)
1515 hr_dev->is_reset = true;
1516 return;
1517 }
1518 }
1519
1520 out:
1521 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag);
1522 }
1523
hns_roce_free_vf_resource(struct hns_roce_dev * hr_dev,int vf_id)1524 static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id)
1525 {
1526 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES;
1527 struct hns_roce_cmq_desc desc[2];
1528 struct hns_roce_cmq_req *req_a;
1529
1530 req_a = (struct hns_roce_cmq_req *)desc[0].data;
1531 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
1532 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1533 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
1534 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id);
1535
1536 return hns_roce_cmq_send(hr_dev, desc, 2);
1537 }
1538
hns_roce_function_clear(struct hns_roce_dev * hr_dev)1539 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev)
1540 {
1541 int ret;
1542 int i;
1543
1544 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
1545 return;
1546
1547 for (i = hr_dev->func_num - 1; i >= 0; i--) {
1548 __hns_roce_function_clear(hr_dev, i);
1549
1550 if (i == 0)
1551 continue;
1552
1553 ret = hns_roce_free_vf_resource(hr_dev, i);
1554 if (ret)
1555 ibdev_err(&hr_dev->ib_dev,
1556 "failed to free vf resource, vf_id = %d, ret = %d.\n",
1557 i, ret);
1558 }
1559 }
1560
hns_roce_clear_extdb_list_info(struct hns_roce_dev * hr_dev)1561 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev)
1562 {
1563 struct hns_roce_cmq_desc desc;
1564 int ret;
1565
1566 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO,
1567 false);
1568 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1569 if (ret)
1570 ibdev_err(&hr_dev->ib_dev,
1571 "failed to clear extended doorbell info, ret = %d.\n",
1572 ret);
1573
1574 return ret;
1575 }
1576
hns_roce_query_fw_ver(struct hns_roce_dev * hr_dev)1577 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev)
1578 {
1579 struct hns_roce_query_fw_info *resp;
1580 struct hns_roce_cmq_desc desc;
1581 int ret;
1582
1583 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true);
1584 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1585 if (ret)
1586 return ret;
1587
1588 resp = (struct hns_roce_query_fw_info *)desc.data;
1589 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver));
1590
1591 return 0;
1592 }
1593
hns_roce_query_func_info(struct hns_roce_dev * hr_dev)1594 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev)
1595 {
1596 struct hns_roce_cmq_desc desc;
1597 int ret;
1598
1599 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
1600 hr_dev->func_num = 1;
1601 return 0;
1602 }
1603
1604 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO,
1605 true);
1606 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1607 if (ret) {
1608 hr_dev->func_num = 1;
1609 return ret;
1610 }
1611
1612 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num);
1613 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id);
1614
1615 return 0;
1616 }
1617
hns_roce_hw_v2_query_counter(struct hns_roce_dev * hr_dev,u64 * stats,u32 port,int * num_counters)1618 static int hns_roce_hw_v2_query_counter(struct hns_roce_dev *hr_dev,
1619 u64 *stats, u32 port, int *num_counters)
1620 {
1621 #define CNT_PER_DESC 3
1622 struct hns_roce_cmq_desc *desc;
1623 int bd_idx, cnt_idx;
1624 __le64 *cnt_data;
1625 int desc_num;
1626 int ret;
1627 int i;
1628
1629 if (port > hr_dev->caps.num_ports)
1630 return -EINVAL;
1631
1632 desc_num = DIV_ROUND_UP(HNS_ROCE_HW_CNT_TOTAL, CNT_PER_DESC);
1633 desc = kcalloc(desc_num, sizeof(*desc), GFP_KERNEL);
1634 if (!desc)
1635 return -ENOMEM;
1636
1637 for (i = 0; i < desc_num; i++) {
1638 hns_roce_cmq_setup_basic_desc(&desc[i],
1639 HNS_ROCE_OPC_QUERY_COUNTER, true);
1640 if (i != desc_num - 1)
1641 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1642 }
1643
1644 ret = hns_roce_cmq_send(hr_dev, desc, desc_num);
1645 if (ret) {
1646 ibdev_err(&hr_dev->ib_dev,
1647 "failed to get counter, ret = %d.\n", ret);
1648 goto err_out;
1649 }
1650
1651 for (i = 0; i < HNS_ROCE_HW_CNT_TOTAL && i < *num_counters; i++) {
1652 bd_idx = i / CNT_PER_DESC;
1653 if (bd_idx != HNS_ROCE_HW_CNT_TOTAL / CNT_PER_DESC &&
1654 !(desc[bd_idx].flag & cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT)))
1655 break;
1656
1657 cnt_data = (__le64 *)&desc[bd_idx].data[0];
1658 cnt_idx = i % CNT_PER_DESC;
1659 stats[i] = le64_to_cpu(cnt_data[cnt_idx]);
1660 }
1661 *num_counters = i;
1662
1663 err_out:
1664 kfree(desc);
1665 return ret;
1666 }
1667
hns_roce_config_global_param(struct hns_roce_dev * hr_dev)1668 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev)
1669 {
1670 struct hns_roce_cmq_desc desc;
1671 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1672 u32 clock_cycles_of_1us;
1673
1674 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM,
1675 false);
1676
1677 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
1678 clock_cycles_of_1us = HNS_ROCE_1NS_CFG;
1679 else
1680 clock_cycles_of_1us = HNS_ROCE_1US_CFG;
1681
1682 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us);
1683 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT);
1684
1685 return hns_roce_cmq_send(hr_dev, &desc, 1);
1686 }
1687
load_func_res_caps(struct hns_roce_dev * hr_dev,bool is_vf)1688 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf)
1689 {
1690 struct hns_roce_cmq_desc desc[2];
1691 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
1692 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
1693 struct hns_roce_caps *caps = &hr_dev->caps;
1694 enum hns_roce_opcode_type opcode;
1695 u32 func_num;
1696 int ret;
1697
1698 if (is_vf) {
1699 opcode = HNS_ROCE_OPC_QUERY_VF_RES;
1700 func_num = 1;
1701 } else {
1702 opcode = HNS_ROCE_OPC_QUERY_PF_RES;
1703 func_num = hr_dev->func_num;
1704 }
1705
1706 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true);
1707 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1708 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true);
1709
1710 ret = hns_roce_cmq_send(hr_dev, desc, 2);
1711 if (ret)
1712 return ret;
1713
1714 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num;
1715 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num;
1716 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num;
1717 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num;
1718 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num;
1719 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num;
1720 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num;
1721 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num;
1722
1723 if (is_vf) {
1724 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num;
1725 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) /
1726 func_num;
1727 } else {
1728 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num;
1729 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) /
1730 func_num;
1731 }
1732
1733 return 0;
1734 }
1735
load_pf_timer_res_caps(struct hns_roce_dev * hr_dev)1736 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev)
1737 {
1738 struct hns_roce_cmq_desc desc;
1739 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1740 struct hns_roce_caps *caps = &hr_dev->caps;
1741 int ret;
1742
1743 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES,
1744 true);
1745
1746 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1747 if (ret)
1748 return ret;
1749
1750 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM);
1751 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM);
1752
1753 return 0;
1754 }
1755
hns_roce_query_pf_resource(struct hns_roce_dev * hr_dev)1756 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
1757 {
1758 struct device *dev = hr_dev->dev;
1759 int ret;
1760
1761 ret = load_func_res_caps(hr_dev, false);
1762 if (ret) {
1763 dev_err(dev, "failed to load pf res caps, ret = %d.\n", ret);
1764 return ret;
1765 }
1766
1767 ret = load_pf_timer_res_caps(hr_dev);
1768 if (ret)
1769 dev_err(dev, "failed to load pf timer resource, ret = %d.\n",
1770 ret);
1771
1772 return ret;
1773 }
1774
hns_roce_query_vf_resource(struct hns_roce_dev * hr_dev)1775 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev)
1776 {
1777 struct device *dev = hr_dev->dev;
1778 int ret;
1779
1780 ret = load_func_res_caps(hr_dev, true);
1781 if (ret)
1782 dev_err(dev, "failed to load vf res caps, ret = %d.\n", ret);
1783
1784 return ret;
1785 }
1786
__hns_roce_set_vf_switch_param(struct hns_roce_dev * hr_dev,u32 vf_id)1787 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev,
1788 u32 vf_id)
1789 {
1790 struct hns_roce_vf_switch *swt;
1791 struct hns_roce_cmq_desc desc;
1792 int ret;
1793
1794 swt = (struct hns_roce_vf_switch *)desc.data;
1795 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true);
1796 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL);
1797 hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id);
1798 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1799 if (ret)
1800 return ret;
1801
1802 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN);
1803 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1804 hr_reg_enable(swt, VF_SWITCH_ALW_LPBK);
1805 hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK);
1806 hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD);
1807
1808 return hns_roce_cmq_send(hr_dev, &desc, 1);
1809 }
1810
hns_roce_set_vf_switch_param(struct hns_roce_dev * hr_dev)1811 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev)
1812 {
1813 u32 vf_id;
1814 int ret;
1815
1816 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) {
1817 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id);
1818 if (ret)
1819 return ret;
1820 }
1821 return 0;
1822 }
1823
config_vf_hem_resource(struct hns_roce_dev * hr_dev,int vf_id)1824 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id)
1825 {
1826 struct hns_roce_cmq_desc desc[2];
1827 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
1828 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
1829 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES;
1830 struct hns_roce_caps *caps = &hr_dev->caps;
1831
1832 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
1833 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1834 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
1835
1836 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id);
1837
1838 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num);
1839 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num);
1840 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num);
1841 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num);
1842 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num);
1843 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num);
1844 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num);
1845 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num);
1846 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num);
1847 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num);
1848 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num);
1849 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num);
1850 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num);
1851 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num);
1852
1853 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
1854 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num);
1855 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX,
1856 vf_id * caps->gmv_bt_num);
1857 } else {
1858 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num);
1859 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX,
1860 vf_id * caps->sgid_bt_num);
1861 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num);
1862 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX,
1863 vf_id * caps->smac_bt_num);
1864 }
1865
1866 return hns_roce_cmq_send(hr_dev, desc, 2);
1867 }
1868
hns_roce_alloc_vf_resource(struct hns_roce_dev * hr_dev)1869 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)
1870 {
1871 u32 func_num = max_t(u32, 1, hr_dev->func_num);
1872 u32 vf_id;
1873 int ret;
1874
1875 for (vf_id = 0; vf_id < func_num; vf_id++) {
1876 ret = config_vf_hem_resource(hr_dev, vf_id);
1877 if (ret) {
1878 dev_err(hr_dev->dev,
1879 "failed to config vf-%u hem res, ret = %d.\n",
1880 vf_id, ret);
1881 return ret;
1882 }
1883 }
1884
1885 return 0;
1886 }
1887
hns_roce_v2_set_bt(struct hns_roce_dev * hr_dev)1888 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
1889 {
1890 struct hns_roce_cmq_desc desc;
1891 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1892 struct hns_roce_caps *caps = &hr_dev->caps;
1893
1894 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false);
1895
1896 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ,
1897 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET);
1898 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ,
1899 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET);
1900 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM,
1901 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps));
1902
1903 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ,
1904 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET);
1905 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ,
1906 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET);
1907 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM,
1908 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs));
1909
1910 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ,
1911 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET);
1912 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ,
1913 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET);
1914 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM,
1915 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs));
1916
1917 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ,
1918 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET);
1919 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ,
1920 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET);
1921 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM,
1922 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts));
1923
1924 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ,
1925 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET);
1926 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ,
1927 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET);
1928 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM,
1929 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps));
1930
1931 return hns_roce_cmq_send(hr_dev, &desc, 1);
1932 }
1933
calc_pg_sz(u32 obj_num,u32 obj_size,u32 hop_num,u32 ctx_bt_num,u32 * buf_page_size,u32 * bt_page_size,u32 hem_type)1934 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num,
1935 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type)
1936 {
1937 u64 obj_per_chunk;
1938 u64 bt_chunk_size = PAGE_SIZE;
1939 u64 buf_chunk_size = PAGE_SIZE;
1940 u64 obj_per_chunk_default = buf_chunk_size / obj_size;
1941
1942 *buf_page_size = 0;
1943 *bt_page_size = 0;
1944
1945 switch (hop_num) {
1946 case 3:
1947 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1948 (bt_chunk_size / BA_BYTE_LEN) *
1949 (bt_chunk_size / BA_BYTE_LEN) *
1950 obj_per_chunk_default;
1951 break;
1952 case 2:
1953 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1954 (bt_chunk_size / BA_BYTE_LEN) *
1955 obj_per_chunk_default;
1956 break;
1957 case 1:
1958 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1959 obj_per_chunk_default;
1960 break;
1961 case HNS_ROCE_HOP_NUM_0:
1962 obj_per_chunk = ctx_bt_num * obj_per_chunk_default;
1963 break;
1964 default:
1965 pr_err("table %u not support hop_num = %u!\n", hem_type,
1966 hop_num);
1967 return;
1968 }
1969
1970 if (hem_type >= HEM_TYPE_MTT)
1971 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
1972 else
1973 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
1974 }
1975
set_hem_page_size(struct hns_roce_dev * hr_dev)1976 static void set_hem_page_size(struct hns_roce_dev *hr_dev)
1977 {
1978 struct hns_roce_caps *caps = &hr_dev->caps;
1979
1980 /* EQ */
1981 caps->eqe_ba_pg_sz = 0;
1982 caps->eqe_buf_pg_sz = 0;
1983
1984 /* Link Table */
1985 caps->llm_buf_pg_sz = 0;
1986
1987 /* MR */
1988 caps->mpt_ba_pg_sz = 0;
1989 caps->mpt_buf_pg_sz = 0;
1990 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K;
1991 caps->pbl_buf_pg_sz = 0;
1992 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num,
1993 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz,
1994 HEM_TYPE_MTPT);
1995
1996 /* QP */
1997 caps->qpc_ba_pg_sz = 0;
1998 caps->qpc_buf_pg_sz = 0;
1999 caps->qpc_timer_ba_pg_sz = 0;
2000 caps->qpc_timer_buf_pg_sz = 0;
2001 caps->sccc_ba_pg_sz = 0;
2002 caps->sccc_buf_pg_sz = 0;
2003 caps->mtt_ba_pg_sz = 0;
2004 caps->mtt_buf_pg_sz = 0;
2005 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num,
2006 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz,
2007 HEM_TYPE_QPC);
2008
2009 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
2010 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num,
2011 caps->sccc_bt_num, &caps->sccc_buf_pg_sz,
2012 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC);
2013
2014 /* CQ */
2015 caps->cqc_ba_pg_sz = 0;
2016 caps->cqc_buf_pg_sz = 0;
2017 caps->cqc_timer_ba_pg_sz = 0;
2018 caps->cqc_timer_buf_pg_sz = 0;
2019 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K;
2020 caps->cqe_buf_pg_sz = 0;
2021 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num,
2022 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz,
2023 HEM_TYPE_CQC);
2024 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num,
2025 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE);
2026
2027 /* SRQ */
2028 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) {
2029 caps->srqc_ba_pg_sz = 0;
2030 caps->srqc_buf_pg_sz = 0;
2031 caps->srqwqe_ba_pg_sz = 0;
2032 caps->srqwqe_buf_pg_sz = 0;
2033 caps->idx_ba_pg_sz = 0;
2034 caps->idx_buf_pg_sz = 0;
2035 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz,
2036 caps->srqc_hop_num, caps->srqc_bt_num,
2037 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz,
2038 HEM_TYPE_SRQC);
2039 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz,
2040 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz,
2041 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE);
2042 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz,
2043 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz,
2044 &caps->idx_ba_pg_sz, HEM_TYPE_IDX);
2045 }
2046
2047 /* GMV */
2048 caps->gmv_ba_pg_sz = 0;
2049 caps->gmv_buf_pg_sz = 0;
2050 }
2051
2052 /* Apply all loaded caps before setting to hardware */
apply_func_caps(struct hns_roce_dev * hr_dev)2053 static void apply_func_caps(struct hns_roce_dev *hr_dev)
2054 {
2055 struct hns_roce_caps *caps = &hr_dev->caps;
2056 struct hns_roce_v2_priv *priv = hr_dev->priv;
2057
2058 /* The following configurations don't need to be got from firmware. */
2059 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ;
2060 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
2061 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
2062
2063 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
2064 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2065 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2066
2067 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
2068 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
2069
2070 if (!caps->num_comp_vectors)
2071 caps->num_comp_vectors =
2072 min_t(u32, caps->eqc_bt_num - HNS_ROCE_V2_AEQE_VEC_NUM,
2073 (u32)priv->handle->rinfo.num_vectors -
2074 (HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM));
2075
2076 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
2077 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM;
2078 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
2079 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
2080
2081 /* The following configurations will be overwritten */
2082 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ;
2083 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE;
2084 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ;
2085
2086 /* The following configurations are not got from firmware */
2087 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ;
2088
2089 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0;
2090 caps->gid_table_len[0] = caps->gmv_bt_num *
2091 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz);
2092
2093 caps->gmv_entry_num = caps->gmv_bt_num * (HNS_HW_PAGE_SIZE /
2094 caps->gmv_entry_sz);
2095 } else {
2096 u32 func_num = max_t(u32, 1, hr_dev->func_num);
2097
2098 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM;
2099 caps->ceqe_size = HNS_ROCE_CEQE_SIZE;
2100 caps->aeqe_size = HNS_ROCE_AEQE_SIZE;
2101 caps->gid_table_len[0] /= func_num;
2102 }
2103
2104 if (hr_dev->is_vf) {
2105 caps->default_aeq_arm_st = 0x3;
2106 caps->default_ceq_arm_st = 0x3;
2107 caps->default_ceq_max_cnt = 0x1;
2108 caps->default_ceq_period = 0x10;
2109 caps->default_aeq_max_cnt = 0x1;
2110 caps->default_aeq_period = 0x10;
2111 }
2112
2113 set_hem_page_size(hr_dev);
2114 }
2115
hns_roce_query_caps(struct hns_roce_dev * hr_dev)2116 static int hns_roce_query_caps(struct hns_roce_dev *hr_dev)
2117 {
2118 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM];
2119 struct hns_roce_caps *caps = &hr_dev->caps;
2120 struct hns_roce_query_pf_caps_a *resp_a;
2121 struct hns_roce_query_pf_caps_b *resp_b;
2122 struct hns_roce_query_pf_caps_c *resp_c;
2123 struct hns_roce_query_pf_caps_d *resp_d;
2124 struct hns_roce_query_pf_caps_e *resp_e;
2125 enum hns_roce_opcode_type cmd;
2126 int ctx_hop_num;
2127 int pbl_hop_num;
2128 int ret;
2129 int i;
2130
2131 cmd = hr_dev->is_vf ? HNS_ROCE_OPC_QUERY_VF_CAPS_NUM :
2132 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM;
2133
2134 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) {
2135 hns_roce_cmq_setup_basic_desc(&desc[i], cmd, true);
2136 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1))
2137 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2138 else
2139 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2140 }
2141
2142 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM);
2143 if (ret)
2144 return ret;
2145
2146 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data;
2147 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data;
2148 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data;
2149 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data;
2150 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data;
2151
2152 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay;
2153 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg);
2154 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline);
2155 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg);
2156 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg);
2157 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges);
2158 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges);
2159 caps->num_aeq_vectors = resp_a->num_aeq_vectors;
2160 caps->num_other_vectors = resp_a->num_other_vectors;
2161 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz;
2162 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz;
2163
2164 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz;
2165 caps->irrl_entry_sz = resp_b->irrl_entry_sz;
2166 caps->trrl_entry_sz = resp_b->trrl_entry_sz;
2167 caps->cqc_entry_sz = resp_b->cqc_entry_sz;
2168 caps->srqc_entry_sz = resp_b->srqc_entry_sz;
2169 caps->idx_entry_sz = resp_b->idx_entry_sz;
2170 caps->sccc_sz = resp_b->sccc_sz;
2171 caps->max_mtu = resp_b->max_mtu;
2172 caps->min_cqes = resp_b->min_cqes;
2173 caps->min_wqes = resp_b->min_wqes;
2174 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap);
2175 caps->pkey_table_len[0] = resp_b->pkey_table_len;
2176 caps->phy_num_uars = resp_b->phy_num_uars;
2177 ctx_hop_num = resp_b->ctx_hop_num;
2178 pbl_hop_num = resp_b->pbl_hop_num;
2179
2180 caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS);
2181
2182 caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS);
2183 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) <<
2184 HNS_ROCE_CAP_FLAGS_EX_SHIFT;
2185
2186 caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS);
2187 caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID);
2188 caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH);
2189 caps->num_xrcds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_XRCDS);
2190 caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS);
2191 caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS);
2192 caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD);
2193 caps->max_qp_dest_rdma = caps->max_qp_init_rdma;
2194 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth);
2195
2196 caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS);
2197 caps->cong_type = hr_reg_read(resp_d, PF_CAPS_D_CONG_TYPE);
2198 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth);
2199 caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH);
2200 caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS);
2201 caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH);
2202 caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS);
2203 caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS);
2204 caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS);
2205 caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS);
2206
2207 caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS);
2208 caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT);
2209 caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS);
2210 caps->reserved_xrcds = hr_reg_read(resp_e, PF_CAPS_E_RSV_XRCDS);
2211 caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS);
2212 caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS);
2213
2214 caps->qpc_hop_num = ctx_hop_num;
2215 caps->sccc_hop_num = ctx_hop_num;
2216 caps->srqc_hop_num = ctx_hop_num;
2217 caps->cqc_hop_num = ctx_hop_num;
2218 caps->mpt_hop_num = ctx_hop_num;
2219 caps->mtt_hop_num = pbl_hop_num;
2220 caps->cqe_hop_num = pbl_hop_num;
2221 caps->srqwqe_hop_num = pbl_hop_num;
2222 caps->idx_hop_num = pbl_hop_num;
2223 caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM);
2224 caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM);
2225 caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM);
2226
2227 if (!(caps->page_size_cap & PAGE_SIZE))
2228 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
2229
2230 if (!hr_dev->is_vf) {
2231 caps->cqe_sz = resp_a->cqe_sz;
2232 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz);
2233 caps->default_aeq_arm_st =
2234 hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST);
2235 caps->default_ceq_arm_st =
2236 hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST);
2237 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt);
2238 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period);
2239 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt);
2240 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period);
2241 }
2242
2243 return 0;
2244 }
2245
config_hem_entry_size(struct hns_roce_dev * hr_dev,u32 type,u32 val)2246 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val)
2247 {
2248 struct hns_roce_cmq_desc desc;
2249 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
2250
2251 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE,
2252 false);
2253
2254 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type);
2255 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val);
2256
2257 return hns_roce_cmq_send(hr_dev, &desc, 1);
2258 }
2259
hns_roce_config_entry_size(struct hns_roce_dev * hr_dev)2260 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev)
2261 {
2262 struct hns_roce_caps *caps = &hr_dev->caps;
2263 int ret;
2264
2265 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
2266 return 0;
2267
2268 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE,
2269 caps->qpc_sz);
2270 if (ret) {
2271 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret);
2272 return ret;
2273 }
2274
2275 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE,
2276 caps->sccc_sz);
2277 if (ret)
2278 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret);
2279
2280 return ret;
2281 }
2282
hns_roce_v2_vf_profile(struct hns_roce_dev * hr_dev)2283 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev)
2284 {
2285 struct device *dev = hr_dev->dev;
2286 int ret;
2287
2288 hr_dev->func_num = 1;
2289
2290 ret = hns_roce_query_caps(hr_dev);
2291 if (ret) {
2292 dev_err(dev, "failed to query VF caps, ret = %d.\n", ret);
2293 return ret;
2294 }
2295
2296 ret = hns_roce_query_vf_resource(hr_dev);
2297 if (ret) {
2298 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret);
2299 return ret;
2300 }
2301
2302 apply_func_caps(hr_dev);
2303
2304 ret = hns_roce_v2_set_bt(hr_dev);
2305 if (ret)
2306 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret);
2307
2308 return ret;
2309 }
2310
hns_roce_v2_pf_profile(struct hns_roce_dev * hr_dev)2311 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev)
2312 {
2313 struct device *dev = hr_dev->dev;
2314 int ret;
2315
2316 ret = hns_roce_query_func_info(hr_dev);
2317 if (ret) {
2318 dev_err(dev, "failed to query func info, ret = %d.\n", ret);
2319 return ret;
2320 }
2321
2322 ret = hns_roce_config_global_param(hr_dev);
2323 if (ret) {
2324 dev_err(dev, "failed to config global param, ret = %d.\n", ret);
2325 return ret;
2326 }
2327
2328 ret = hns_roce_set_vf_switch_param(hr_dev);
2329 if (ret) {
2330 dev_err(dev, "failed to set switch param, ret = %d.\n", ret);
2331 return ret;
2332 }
2333
2334 ret = hns_roce_query_caps(hr_dev);
2335 if (ret) {
2336 dev_err(dev, "failed to query PF caps, ret = %d.\n", ret);
2337 return ret;
2338 }
2339
2340 ret = hns_roce_query_pf_resource(hr_dev);
2341 if (ret) {
2342 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret);
2343 return ret;
2344 }
2345
2346 apply_func_caps(hr_dev);
2347
2348 ret = hns_roce_alloc_vf_resource(hr_dev);
2349 if (ret) {
2350 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret);
2351 return ret;
2352 }
2353
2354 ret = hns_roce_v2_set_bt(hr_dev);
2355 if (ret) {
2356 dev_err(dev, "failed to config BA table, ret = %d.\n", ret);
2357 return ret;
2358 }
2359
2360 /* Configure the size of QPC, SCCC, etc. */
2361 return hns_roce_config_entry_size(hr_dev);
2362 }
2363
hns_roce_v2_profile(struct hns_roce_dev * hr_dev)2364 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
2365 {
2366 struct device *dev = hr_dev->dev;
2367 int ret;
2368
2369 ret = hns_roce_cmq_query_hw_info(hr_dev);
2370 if (ret) {
2371 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret);
2372 return ret;
2373 }
2374
2375 ret = hns_roce_query_fw_ver(hr_dev);
2376 if (ret) {
2377 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret);
2378 return ret;
2379 }
2380
2381 hr_dev->vendor_part_id = hr_dev->pci_dev->device;
2382 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid);
2383
2384 if (hr_dev->is_vf)
2385 return hns_roce_v2_vf_profile(hr_dev);
2386 else
2387 return hns_roce_v2_pf_profile(hr_dev);
2388 }
2389
config_llm_table(struct hns_roce_buf * data_buf,void * cfg_buf)2390 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf)
2391 {
2392 u32 i, next_ptr, page_num;
2393 __le64 *entry = cfg_buf;
2394 dma_addr_t addr;
2395 u64 val;
2396
2397 page_num = data_buf->npages;
2398 for (i = 0; i < page_num; i++) {
2399 addr = hns_roce_buf_page(data_buf, i);
2400 if (i == (page_num - 1))
2401 next_ptr = 0;
2402 else
2403 next_ptr = i + 1;
2404
2405 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr);
2406 entry[i] = cpu_to_le64(val);
2407 }
2408 }
2409
set_llm_cfg_to_hw(struct hns_roce_dev * hr_dev,struct hns_roce_link_table * table)2410 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev,
2411 struct hns_roce_link_table *table)
2412 {
2413 struct hns_roce_cmq_desc desc[2];
2414 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
2415 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
2416 struct hns_roce_buf *buf = table->buf;
2417 enum hns_roce_opcode_type opcode;
2418 dma_addr_t addr;
2419
2420 opcode = HNS_ROCE_OPC_CFG_EXT_LLM;
2421 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
2422 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2423 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
2424
2425 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map));
2426 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map));
2427 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages);
2428 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift));
2429 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN);
2430
2431 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0));
2432 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr));
2433 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr));
2434 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1);
2435 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0);
2436
2437 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1));
2438 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr));
2439 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr));
2440 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1);
2441
2442 return hns_roce_cmq_send(hr_dev, desc, 2);
2443 }
2444
2445 static struct hns_roce_link_table *
alloc_link_table_buf(struct hns_roce_dev * hr_dev)2446 alloc_link_table_buf(struct hns_roce_dev *hr_dev)
2447 {
2448 u16 total_sl = hr_dev->caps.sl_num * hr_dev->func_num;
2449 struct hns_roce_v2_priv *priv = hr_dev->priv;
2450 struct hns_roce_link_table *link_tbl;
2451 u32 pg_shift, size, min_size;
2452
2453 link_tbl = &priv->ext_llm;
2454 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT;
2455 size = hr_dev->caps.num_qps * hr_dev->func_num *
2456 HNS_ROCE_V2_EXT_LLM_ENTRY_SZ;
2457 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(total_sl) << pg_shift;
2458
2459 /* Alloc data table */
2460 size = max(size, min_size);
2461 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0);
2462 if (IS_ERR(link_tbl->buf))
2463 return ERR_PTR(-ENOMEM);
2464
2465 /* Alloc config table */
2466 size = link_tbl->buf->npages * sizeof(u64);
2467 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size,
2468 &link_tbl->table.map,
2469 GFP_KERNEL);
2470 if (!link_tbl->table.buf) {
2471 hns_roce_buf_free(hr_dev, link_tbl->buf);
2472 return ERR_PTR(-ENOMEM);
2473 }
2474
2475 return link_tbl;
2476 }
2477
free_link_table_buf(struct hns_roce_dev * hr_dev,struct hns_roce_link_table * tbl)2478 static void free_link_table_buf(struct hns_roce_dev *hr_dev,
2479 struct hns_roce_link_table *tbl)
2480 {
2481 if (tbl->buf) {
2482 u32 size = tbl->buf->npages * sizeof(u64);
2483
2484 dma_free_coherent(hr_dev->dev, size, tbl->table.buf,
2485 tbl->table.map);
2486 }
2487
2488 hns_roce_buf_free(hr_dev, tbl->buf);
2489 }
2490
hns_roce_init_link_table(struct hns_roce_dev * hr_dev)2491 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev)
2492 {
2493 struct hns_roce_link_table *link_tbl;
2494 int ret;
2495
2496 link_tbl = alloc_link_table_buf(hr_dev);
2497 if (IS_ERR(link_tbl))
2498 return -ENOMEM;
2499
2500 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) {
2501 ret = -EINVAL;
2502 goto err_alloc;
2503 }
2504
2505 config_llm_table(link_tbl->buf, link_tbl->table.buf);
2506 ret = set_llm_cfg_to_hw(hr_dev, link_tbl);
2507 if (ret)
2508 goto err_alloc;
2509
2510 return 0;
2511
2512 err_alloc:
2513 free_link_table_buf(hr_dev, link_tbl);
2514 return ret;
2515 }
2516
hns_roce_free_link_table(struct hns_roce_dev * hr_dev)2517 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev)
2518 {
2519 struct hns_roce_v2_priv *priv = hr_dev->priv;
2520
2521 free_link_table_buf(hr_dev, &priv->ext_llm);
2522 }
2523
free_dip_list(struct hns_roce_dev * hr_dev)2524 static void free_dip_list(struct hns_roce_dev *hr_dev)
2525 {
2526 struct hns_roce_dip *hr_dip;
2527 struct hns_roce_dip *tmp;
2528 unsigned long flags;
2529
2530 spin_lock_irqsave(&hr_dev->dip_list_lock, flags);
2531
2532 list_for_each_entry_safe(hr_dip, tmp, &hr_dev->dip_list, node) {
2533 list_del(&hr_dip->node);
2534 kfree(hr_dip);
2535 }
2536
2537 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags);
2538 }
2539
free_mr_init_pd(struct hns_roce_dev * hr_dev)2540 static struct ib_pd *free_mr_init_pd(struct hns_roce_dev *hr_dev)
2541 {
2542 struct hns_roce_v2_priv *priv = hr_dev->priv;
2543 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2544 struct ib_device *ibdev = &hr_dev->ib_dev;
2545 struct hns_roce_pd *hr_pd;
2546 struct ib_pd *pd;
2547
2548 hr_pd = kzalloc(sizeof(*hr_pd), GFP_KERNEL);
2549 if (ZERO_OR_NULL_PTR(hr_pd))
2550 return NULL;
2551 pd = &hr_pd->ibpd;
2552 pd->device = ibdev;
2553
2554 if (hns_roce_alloc_pd(pd, NULL)) {
2555 ibdev_err(ibdev, "failed to create pd for free mr.\n");
2556 kfree(hr_pd);
2557 return NULL;
2558 }
2559 free_mr->rsv_pd = to_hr_pd(pd);
2560 free_mr->rsv_pd->ibpd.device = &hr_dev->ib_dev;
2561 free_mr->rsv_pd->ibpd.uobject = NULL;
2562 free_mr->rsv_pd->ibpd.__internal_mr = NULL;
2563 atomic_set(&free_mr->rsv_pd->ibpd.usecnt, 0);
2564
2565 return pd;
2566 }
2567
free_mr_init_cq(struct hns_roce_dev * hr_dev)2568 static struct ib_cq *free_mr_init_cq(struct hns_roce_dev *hr_dev)
2569 {
2570 struct hns_roce_v2_priv *priv = hr_dev->priv;
2571 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2572 struct ib_device *ibdev = &hr_dev->ib_dev;
2573 struct ib_cq_init_attr cq_init_attr = {};
2574 struct hns_roce_cq *hr_cq;
2575 struct ib_cq *cq;
2576
2577 cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM;
2578
2579 hr_cq = kzalloc(sizeof(*hr_cq), GFP_KERNEL);
2580 if (ZERO_OR_NULL_PTR(hr_cq))
2581 return NULL;
2582
2583 cq = &hr_cq->ib_cq;
2584 cq->device = ibdev;
2585
2586 if (hns_roce_create_cq(cq, &cq_init_attr, NULL)) {
2587 ibdev_err(ibdev, "failed to create cq for free mr.\n");
2588 kfree(hr_cq);
2589 return NULL;
2590 }
2591 free_mr->rsv_cq = to_hr_cq(cq);
2592 free_mr->rsv_cq->ib_cq.device = &hr_dev->ib_dev;
2593 free_mr->rsv_cq->ib_cq.uobject = NULL;
2594 free_mr->rsv_cq->ib_cq.comp_handler = NULL;
2595 free_mr->rsv_cq->ib_cq.event_handler = NULL;
2596 free_mr->rsv_cq->ib_cq.cq_context = NULL;
2597 atomic_set(&free_mr->rsv_cq->ib_cq.usecnt, 0);
2598
2599 return cq;
2600 }
2601
free_mr_init_qp(struct hns_roce_dev * hr_dev,struct ib_cq * cq,struct ib_qp_init_attr * init_attr,int i)2602 static int free_mr_init_qp(struct hns_roce_dev *hr_dev, struct ib_cq *cq,
2603 struct ib_qp_init_attr *init_attr, int i)
2604 {
2605 struct hns_roce_v2_priv *priv = hr_dev->priv;
2606 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2607 struct ib_device *ibdev = &hr_dev->ib_dev;
2608 struct hns_roce_qp *hr_qp;
2609 struct ib_qp *qp;
2610 int ret;
2611
2612 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL);
2613 if (ZERO_OR_NULL_PTR(hr_qp))
2614 return -ENOMEM;
2615
2616 qp = &hr_qp->ibqp;
2617 qp->device = ibdev;
2618
2619 ret = hns_roce_create_qp(qp, init_attr, NULL);
2620 if (ret) {
2621 ibdev_err(ibdev, "failed to create qp for free mr.\n");
2622 kfree(hr_qp);
2623 return ret;
2624 }
2625
2626 free_mr->rsv_qp[i] = hr_qp;
2627 free_mr->rsv_qp[i]->ibqp.recv_cq = cq;
2628 free_mr->rsv_qp[i]->ibqp.send_cq = cq;
2629
2630 return 0;
2631 }
2632
free_mr_exit(struct hns_roce_dev * hr_dev)2633 static void free_mr_exit(struct hns_roce_dev *hr_dev)
2634 {
2635 struct hns_roce_v2_priv *priv = hr_dev->priv;
2636 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2637 struct ib_qp *qp;
2638 int i;
2639
2640 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2641 if (free_mr->rsv_qp[i]) {
2642 qp = &free_mr->rsv_qp[i]->ibqp;
2643 hns_roce_v2_destroy_qp(qp, NULL);
2644 kfree(free_mr->rsv_qp[i]);
2645 free_mr->rsv_qp[i] = NULL;
2646 }
2647 }
2648
2649 if (free_mr->rsv_cq) {
2650 hns_roce_destroy_cq(&free_mr->rsv_cq->ib_cq, NULL);
2651 kfree(free_mr->rsv_cq);
2652 free_mr->rsv_cq = NULL;
2653 }
2654
2655 if (free_mr->rsv_pd) {
2656 hns_roce_dealloc_pd(&free_mr->rsv_pd->ibpd, NULL);
2657 kfree(free_mr->rsv_pd);
2658 free_mr->rsv_pd = NULL;
2659 }
2660 }
2661
free_mr_alloc_res(struct hns_roce_dev * hr_dev)2662 static int free_mr_alloc_res(struct hns_roce_dev *hr_dev)
2663 {
2664 struct hns_roce_v2_priv *priv = hr_dev->priv;
2665 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2666 struct ib_qp_init_attr qp_init_attr = {};
2667 struct ib_pd *pd;
2668 struct ib_cq *cq;
2669 int ret;
2670 int i;
2671
2672 pd = free_mr_init_pd(hr_dev);
2673 if (!pd)
2674 return -ENOMEM;
2675
2676 cq = free_mr_init_cq(hr_dev);
2677 if (!cq) {
2678 ret = -ENOMEM;
2679 goto create_failed_cq;
2680 }
2681
2682 qp_init_attr.qp_type = IB_QPT_RC;
2683 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
2684 qp_init_attr.send_cq = cq;
2685 qp_init_attr.recv_cq = cq;
2686 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2687 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM;
2688 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM;
2689 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM;
2690 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM;
2691
2692 ret = free_mr_init_qp(hr_dev, cq, &qp_init_attr, i);
2693 if (ret)
2694 goto create_failed_qp;
2695 }
2696
2697 return 0;
2698
2699 create_failed_qp:
2700 for (i--; i >= 0; i--) {
2701 hns_roce_v2_destroy_qp(&free_mr->rsv_qp[i]->ibqp, NULL);
2702 kfree(free_mr->rsv_qp[i]);
2703 }
2704 hns_roce_destroy_cq(cq, NULL);
2705 kfree(cq);
2706
2707 create_failed_cq:
2708 hns_roce_dealloc_pd(pd, NULL);
2709 kfree(pd);
2710
2711 return ret;
2712 }
2713
free_mr_modify_rsv_qp(struct hns_roce_dev * hr_dev,struct ib_qp_attr * attr,int sl_num)2714 static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev,
2715 struct ib_qp_attr *attr, int sl_num)
2716 {
2717 struct hns_roce_v2_priv *priv = hr_dev->priv;
2718 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2719 struct ib_device *ibdev = &hr_dev->ib_dev;
2720 struct hns_roce_qp *hr_qp;
2721 int loopback;
2722 int mask;
2723 int ret;
2724
2725 hr_qp = to_hr_qp(&free_mr->rsv_qp[sl_num]->ibqp);
2726 hr_qp->free_mr_en = 1;
2727 hr_qp->ibqp.device = ibdev;
2728 hr_qp->ibqp.qp_type = IB_QPT_RC;
2729
2730 mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS;
2731 attr->qp_state = IB_QPS_INIT;
2732 attr->port_num = 1;
2733 attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE;
2734 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT,
2735 IB_QPS_INIT, NULL);
2736 if (ret) {
2737 ibdev_err_ratelimited(ibdev, "failed to modify qp to init, ret = %d.\n",
2738 ret);
2739 return ret;
2740 }
2741
2742 loopback = hr_dev->loop_idc;
2743 /* Set qpc lbi = 1 incidate loopback IO */
2744 hr_dev->loop_idc = 1;
2745
2746 mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN |
2747 IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER;
2748 attr->qp_state = IB_QPS_RTR;
2749 attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
2750 attr->path_mtu = IB_MTU_256;
2751 attr->dest_qp_num = hr_qp->qpn;
2752 attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN;
2753
2754 rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num);
2755
2756 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT,
2757 IB_QPS_RTR, NULL);
2758 hr_dev->loop_idc = loopback;
2759 if (ret) {
2760 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n",
2761 ret);
2762 return ret;
2763 }
2764
2765 mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT |
2766 IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC;
2767 attr->qp_state = IB_QPS_RTS;
2768 attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN;
2769 attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT;
2770 attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT;
2771 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_RTR,
2772 IB_QPS_RTS, NULL);
2773 if (ret)
2774 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n",
2775 ret);
2776
2777 return ret;
2778 }
2779
free_mr_modify_qp(struct hns_roce_dev * hr_dev)2780 static int free_mr_modify_qp(struct hns_roce_dev *hr_dev)
2781 {
2782 struct hns_roce_v2_priv *priv = hr_dev->priv;
2783 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2784 struct ib_qp_attr attr = {};
2785 int ret;
2786 int i;
2787
2788 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
2789 rdma_ah_set_static_rate(&attr.ah_attr, 3);
2790 rdma_ah_set_port_num(&attr.ah_attr, 1);
2791
2792 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2793 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i);
2794 if (ret)
2795 return ret;
2796 }
2797
2798 return 0;
2799 }
2800
free_mr_init(struct hns_roce_dev * hr_dev)2801 static int free_mr_init(struct hns_roce_dev *hr_dev)
2802 {
2803 struct hns_roce_v2_priv *priv = hr_dev->priv;
2804 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2805 int ret;
2806
2807 mutex_init(&free_mr->mutex);
2808
2809 ret = free_mr_alloc_res(hr_dev);
2810 if (ret)
2811 return ret;
2812
2813 ret = free_mr_modify_qp(hr_dev);
2814 if (ret)
2815 goto err_modify_qp;
2816
2817 return 0;
2818
2819 err_modify_qp:
2820 free_mr_exit(hr_dev);
2821
2822 return ret;
2823 }
2824
get_hem_table(struct hns_roce_dev * hr_dev)2825 static int get_hem_table(struct hns_roce_dev *hr_dev)
2826 {
2827 unsigned int qpc_count;
2828 unsigned int cqc_count;
2829 unsigned int gmv_count;
2830 int ret;
2831 int i;
2832
2833 /* Alloc memory for source address table buffer space chunk */
2834 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num;
2835 gmv_count++) {
2836 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count);
2837 if (ret)
2838 goto err_gmv_failed;
2839 }
2840
2841 if (hr_dev->is_vf)
2842 return 0;
2843
2844 /* Alloc memory for QPC Timer buffer space chunk */
2845 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num;
2846 qpc_count++) {
2847 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table,
2848 qpc_count);
2849 if (ret) {
2850 dev_err(hr_dev->dev, "QPC Timer get failed\n");
2851 goto err_qpc_timer_failed;
2852 }
2853 }
2854
2855 /* Alloc memory for CQC Timer buffer space chunk */
2856 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num;
2857 cqc_count++) {
2858 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table,
2859 cqc_count);
2860 if (ret) {
2861 dev_err(hr_dev->dev, "CQC Timer get failed\n");
2862 goto err_cqc_timer_failed;
2863 }
2864 }
2865
2866 return 0;
2867
2868 err_cqc_timer_failed:
2869 for (i = 0; i < cqc_count; i++)
2870 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
2871
2872 err_qpc_timer_failed:
2873 for (i = 0; i < qpc_count; i++)
2874 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
2875
2876 err_gmv_failed:
2877 for (i = 0; i < gmv_count; i++)
2878 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i);
2879
2880 return ret;
2881 }
2882
put_hem_table(struct hns_roce_dev * hr_dev)2883 static void put_hem_table(struct hns_roce_dev *hr_dev)
2884 {
2885 int i;
2886
2887 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++)
2888 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i);
2889
2890 if (hr_dev->is_vf)
2891 return;
2892
2893 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++)
2894 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
2895
2896 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++)
2897 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
2898 }
2899
hns_roce_v2_init(struct hns_roce_dev * hr_dev)2900 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev)
2901 {
2902 int ret;
2903
2904 /* The hns ROCEE requires the extdb info to be cleared before using */
2905 ret = hns_roce_clear_extdb_list_info(hr_dev);
2906 if (ret)
2907 return ret;
2908
2909 ret = get_hem_table(hr_dev);
2910 if (ret)
2911 return ret;
2912
2913 if (hr_dev->is_vf)
2914 return 0;
2915
2916 ret = hns_roce_init_link_table(hr_dev);
2917 if (ret) {
2918 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret);
2919 goto err_llm_init_failed;
2920 }
2921
2922 return 0;
2923
2924 err_llm_init_failed:
2925 put_hem_table(hr_dev);
2926
2927 return ret;
2928 }
2929
hns_roce_v2_exit(struct hns_roce_dev * hr_dev)2930 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
2931 {
2932 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
2933 free_mr_exit(hr_dev);
2934
2935 hns_roce_function_clear(hr_dev);
2936
2937 if (!hr_dev->is_vf)
2938 hns_roce_free_link_table(hr_dev);
2939
2940 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09)
2941 free_dip_list(hr_dev);
2942 }
2943
hns_roce_mbox_post(struct hns_roce_dev * hr_dev,struct hns_roce_mbox_msg * mbox_msg)2944 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev,
2945 struct hns_roce_mbox_msg *mbox_msg)
2946 {
2947 struct hns_roce_cmq_desc desc;
2948 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data;
2949
2950 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false);
2951
2952 mb->in_param_l = cpu_to_le32(mbox_msg->in_param);
2953 mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32);
2954 mb->out_param_l = cpu_to_le32(mbox_msg->out_param);
2955 mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32);
2956 mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd);
2957 mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 |
2958 mbox_msg->token);
2959
2960 return hns_roce_cmq_send(hr_dev, &desc, 1);
2961 }
2962
v2_wait_mbox_complete(struct hns_roce_dev * hr_dev,u32 timeout,u8 * complete_status)2963 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout,
2964 u8 *complete_status)
2965 {
2966 struct hns_roce_mbox_status *mb_st;
2967 struct hns_roce_cmq_desc desc;
2968 unsigned long end;
2969 int ret = -EBUSY;
2970 u32 status;
2971 bool busy;
2972
2973 mb_st = (struct hns_roce_mbox_status *)desc.data;
2974 end = msecs_to_jiffies(timeout) + jiffies;
2975 while (v2_chk_mbox_is_avail(hr_dev, &busy)) {
2976 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
2977 return -EIO;
2978
2979 status = 0;
2980 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST,
2981 true);
2982 ret = __hns_roce_cmq_send(hr_dev, &desc, 1);
2983 if (!ret) {
2984 status = le32_to_cpu(mb_st->mb_status_hw_run);
2985 /* No pending message exists in ROCEE mbox. */
2986 if (!(status & MB_ST_HW_RUN_M))
2987 break;
2988 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) {
2989 break;
2990 }
2991
2992 if (time_after(jiffies, end)) {
2993 dev_err_ratelimited(hr_dev->dev,
2994 "failed to wait mbox status 0x%x\n",
2995 status);
2996 return -ETIMEDOUT;
2997 }
2998
2999 cond_resched();
3000 ret = -EBUSY;
3001 }
3002
3003 if (!ret) {
3004 *complete_status = (u8)(status & MB_ST_COMPLETE_M);
3005 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) {
3006 /* Ignore all errors if the mbox is unavailable. */
3007 ret = 0;
3008 *complete_status = MB_ST_COMPLETE_M;
3009 }
3010
3011 return ret;
3012 }
3013
v2_post_mbox(struct hns_roce_dev * hr_dev,struct hns_roce_mbox_msg * mbox_msg)3014 static int v2_post_mbox(struct hns_roce_dev *hr_dev,
3015 struct hns_roce_mbox_msg *mbox_msg)
3016 {
3017 u8 status = 0;
3018 int ret;
3019
3020 /* Waiting for the mbox to be idle */
3021 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS,
3022 &status);
3023 if (unlikely(ret)) {
3024 dev_err_ratelimited(hr_dev->dev,
3025 "failed to check post mbox status = 0x%x, ret = %d.\n",
3026 status, ret);
3027 return ret;
3028 }
3029
3030 /* Post new message to mbox */
3031 ret = hns_roce_mbox_post(hr_dev, mbox_msg);
3032 if (ret)
3033 dev_err_ratelimited(hr_dev->dev,
3034 "failed to post mailbox, ret = %d.\n", ret);
3035
3036 return ret;
3037 }
3038
v2_poll_mbox_done(struct hns_roce_dev * hr_dev)3039 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev)
3040 {
3041 u8 status = 0;
3042 int ret;
3043
3044 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS,
3045 &status);
3046 if (!ret) {
3047 if (status != MB_ST_COMPLETE_SUCC)
3048 return -EBUSY;
3049 } else {
3050 dev_err_ratelimited(hr_dev->dev,
3051 "failed to check mbox status = 0x%x, ret = %d.\n",
3052 status, ret);
3053 }
3054
3055 return ret;
3056 }
3057
copy_gid(void * dest,const union ib_gid * gid)3058 static void copy_gid(void *dest, const union ib_gid *gid)
3059 {
3060 #define GID_SIZE 4
3061 const union ib_gid *src = gid;
3062 __le32 (*p)[GID_SIZE] = dest;
3063 int i;
3064
3065 if (!gid)
3066 src = &zgid;
3067
3068 for (i = 0; i < GID_SIZE; i++)
3069 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]);
3070 }
3071
config_sgid_table(struct hns_roce_dev * hr_dev,int gid_index,const union ib_gid * gid,enum hns_roce_sgid_type sgid_type)3072 static int config_sgid_table(struct hns_roce_dev *hr_dev,
3073 int gid_index, const union ib_gid *gid,
3074 enum hns_roce_sgid_type sgid_type)
3075 {
3076 struct hns_roce_cmq_desc desc;
3077 struct hns_roce_cfg_sgid_tb *sgid_tb =
3078 (struct hns_roce_cfg_sgid_tb *)desc.data;
3079
3080 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false);
3081
3082 hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index);
3083 hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type);
3084
3085 copy_gid(&sgid_tb->vf_sgid_l, gid);
3086
3087 return hns_roce_cmq_send(hr_dev, &desc, 1);
3088 }
3089
config_gmv_table(struct hns_roce_dev * hr_dev,int gid_index,const union ib_gid * gid,enum hns_roce_sgid_type sgid_type,const struct ib_gid_attr * attr)3090 static int config_gmv_table(struct hns_roce_dev *hr_dev,
3091 int gid_index, const union ib_gid *gid,
3092 enum hns_roce_sgid_type sgid_type,
3093 const struct ib_gid_attr *attr)
3094 {
3095 struct hns_roce_cmq_desc desc[2];
3096 struct hns_roce_cfg_gmv_tb_a *tb_a =
3097 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data;
3098 struct hns_roce_cfg_gmv_tb_b *tb_b =
3099 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data;
3100
3101 u16 vlan_id = VLAN_CFI_MASK;
3102 u8 mac[ETH_ALEN] = {};
3103 int ret;
3104
3105 if (gid) {
3106 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac);
3107 if (ret)
3108 return ret;
3109 }
3110
3111 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false);
3112 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
3113
3114 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false);
3115
3116 copy_gid(&tb_a->vf_sgid_l, gid);
3117
3118 hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type);
3119 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK);
3120 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id);
3121
3122 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac);
3123
3124 hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]);
3125 hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index);
3126
3127 return hns_roce_cmq_send(hr_dev, desc, 2);
3128 }
3129
hns_roce_v2_set_gid(struct hns_roce_dev * hr_dev,int gid_index,const union ib_gid * gid,const struct ib_gid_attr * attr)3130 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index,
3131 const union ib_gid *gid,
3132 const struct ib_gid_attr *attr)
3133 {
3134 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
3135 int ret;
3136
3137 if (gid) {
3138 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
3139 if (ipv6_addr_v4mapped((void *)gid))
3140 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4;
3141 else
3142 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;
3143 } else if (attr->gid_type == IB_GID_TYPE_ROCE) {
3144 sgid_type = GID_TYPE_FLAG_ROCE_V1;
3145 }
3146 }
3147
3148 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
3149 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr);
3150 else
3151 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type);
3152
3153 if (ret)
3154 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n",
3155 ret);
3156
3157 return ret;
3158 }
3159
hns_roce_v2_set_mac(struct hns_roce_dev * hr_dev,u8 phy_port,const u8 * addr)3160 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
3161 const u8 *addr)
3162 {
3163 struct hns_roce_cmq_desc desc;
3164 struct hns_roce_cfg_smac_tb *smac_tb =
3165 (struct hns_roce_cfg_smac_tb *)desc.data;
3166 u16 reg_smac_h;
3167 u32 reg_smac_l;
3168
3169 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false);
3170
3171 reg_smac_l = *(u32 *)(&addr[0]);
3172 reg_smac_h = *(u16 *)(&addr[4]);
3173
3174 hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port);
3175 hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h);
3176 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l);
3177
3178 return hns_roce_cmq_send(hr_dev, &desc, 1);
3179 }
3180
set_mtpt_pbl(struct hns_roce_dev * hr_dev,struct hns_roce_v2_mpt_entry * mpt_entry,struct hns_roce_mr * mr)3181 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev,
3182 struct hns_roce_v2_mpt_entry *mpt_entry,
3183 struct hns_roce_mr *mr)
3184 {
3185 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 };
3186 struct ib_device *ibdev = &hr_dev->ib_dev;
3187 dma_addr_t pbl_ba;
3188 int ret;
3189 int i;
3190
3191 ret = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages,
3192 min_t(int, ARRAY_SIZE(pages), mr->npages));
3193 if (ret) {
3194 ibdev_err(ibdev, "failed to find PBL mtr, ret = %d.\n", ret);
3195 return ret;
3196 }
3197
3198 /* Aligned to the hardware address access unit */
3199 for (i = 0; i < ARRAY_SIZE(pages); i++)
3200 pages[i] >>= 6;
3201
3202 pbl_ba = hns_roce_get_mtr_ba(&mr->pbl_mtr);
3203
3204 mpt_entry->pbl_size = cpu_to_le32(mr->npages);
3205 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3);
3206 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3));
3207
3208 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
3209 hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0]));
3210
3211 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
3212 hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1]));
3213 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3214 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
3215
3216 return 0;
3217 }
3218
hns_roce_v2_write_mtpt(struct hns_roce_dev * hr_dev,void * mb_buf,struct hns_roce_mr * mr)3219 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev,
3220 void *mb_buf, struct hns_roce_mr *mr)
3221 {
3222 struct hns_roce_v2_mpt_entry *mpt_entry;
3223
3224 mpt_entry = mb_buf;
3225 memset(mpt_entry, 0, sizeof(*mpt_entry));
3226
3227 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID);
3228 hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3229
3230 hr_reg_write_bool(mpt_entry, MPT_BIND_EN,
3231 mr->access & IB_ACCESS_MW_BIND);
3232 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN,
3233 mr->access & IB_ACCESS_REMOTE_ATOMIC);
3234 hr_reg_write_bool(mpt_entry, MPT_RR_EN,
3235 mr->access & IB_ACCESS_REMOTE_READ);
3236 hr_reg_write_bool(mpt_entry, MPT_RW_EN,
3237 mr->access & IB_ACCESS_REMOTE_WRITE);
3238 hr_reg_write_bool(mpt_entry, MPT_LW_EN,
3239 mr->access & IB_ACCESS_LOCAL_WRITE);
3240
3241 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
3242 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
3243 mpt_entry->lkey = cpu_to_le32(mr->key);
3244 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
3245 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
3246
3247 if (mr->type != MR_TYPE_MR)
3248 hr_reg_enable(mpt_entry, MPT_PA);
3249
3250 if (mr->type == MR_TYPE_DMA)
3251 return 0;
3252
3253 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0)
3254 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num);
3255
3256 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3257 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
3258 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD);
3259
3260 return set_mtpt_pbl(hr_dev, mpt_entry, mr);
3261 }
3262
hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev * hr_dev,struct hns_roce_mr * mr,int flags,void * mb_buf)3263 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
3264 struct hns_roce_mr *mr, int flags,
3265 void *mb_buf)
3266 {
3267 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
3268 u32 mr_access_flags = mr->access;
3269 int ret = 0;
3270
3271 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID);
3272 hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3273
3274 if (flags & IB_MR_REREG_ACCESS) {
3275 hr_reg_write(mpt_entry, MPT_BIND_EN,
3276 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0));
3277 hr_reg_write(mpt_entry, MPT_ATOMIC_EN,
3278 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
3279 hr_reg_write(mpt_entry, MPT_RR_EN,
3280 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0);
3281 hr_reg_write(mpt_entry, MPT_RW_EN,
3282 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
3283 hr_reg_write(mpt_entry, MPT_LW_EN,
3284 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
3285 }
3286
3287 if (flags & IB_MR_REREG_TRANS) {
3288 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
3289 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
3290 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
3291 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
3292
3293 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr);
3294 }
3295
3296 return ret;
3297 }
3298
hns_roce_v2_frmr_write_mtpt(void * mb_buf,struct hns_roce_mr * mr)3299 static int hns_roce_v2_frmr_write_mtpt(void *mb_buf, struct hns_roce_mr *mr)
3300 {
3301 dma_addr_t pbl_ba = hns_roce_get_mtr_ba(&mr->pbl_mtr);
3302 struct hns_roce_v2_mpt_entry *mpt_entry;
3303
3304 mpt_entry = mb_buf;
3305 memset(mpt_entry, 0, sizeof(*mpt_entry));
3306
3307 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE);
3308 hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3309
3310 hr_reg_enable(mpt_entry, MPT_RA_EN);
3311 hr_reg_enable(mpt_entry, MPT_R_INV_EN);
3312
3313 hr_reg_enable(mpt_entry, MPT_FRE);
3314 hr_reg_clear(mpt_entry, MPT_MR_MW);
3315 hr_reg_enable(mpt_entry, MPT_BPD);
3316 hr_reg_clear(mpt_entry, MPT_PA);
3317
3318 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1);
3319 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3320 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
3321 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3322 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
3323
3324 mpt_entry->pbl_size = cpu_to_le32(mr->npages);
3325
3326 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3));
3327 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3));
3328
3329 return 0;
3330 }
3331
hns_roce_v2_mw_write_mtpt(void * mb_buf,struct hns_roce_mw * mw)3332 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw)
3333 {
3334 struct hns_roce_v2_mpt_entry *mpt_entry;
3335
3336 mpt_entry = mb_buf;
3337 memset(mpt_entry, 0, sizeof(*mpt_entry));
3338
3339 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE);
3340 hr_reg_write(mpt_entry, MPT_PD, mw->pdn);
3341
3342 hr_reg_enable(mpt_entry, MPT_R_INV_EN);
3343 hr_reg_enable(mpt_entry, MPT_LW_EN);
3344
3345 hr_reg_enable(mpt_entry, MPT_MR_MW);
3346 hr_reg_enable(mpt_entry, MPT_BPD);
3347 hr_reg_clear(mpt_entry, MPT_PA);
3348 hr_reg_write(mpt_entry, MPT_BQP,
3349 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1);
3350
3351 mpt_entry->lkey = cpu_to_le32(mw->rkey);
3352
3353 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM,
3354 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 :
3355 mw->pbl_hop_num);
3356 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3357 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
3358 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3359 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
3360
3361 return 0;
3362 }
3363
free_mr_post_send_lp_wqe(struct hns_roce_qp * hr_qp)3364 static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp)
3365 {
3366 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
3367 struct ib_device *ibdev = &hr_dev->ib_dev;
3368 const struct ib_send_wr *bad_wr;
3369 struct ib_rdma_wr rdma_wr = {};
3370 struct ib_send_wr *send_wr;
3371 int ret;
3372
3373 send_wr = &rdma_wr.wr;
3374 send_wr->opcode = IB_WR_RDMA_WRITE;
3375
3376 ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr);
3377 if (ret) {
3378 ibdev_err_ratelimited(ibdev, "failed to post wqe for free mr, ret = %d.\n",
3379 ret);
3380 return ret;
3381 }
3382
3383 return 0;
3384 }
3385
3386 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
3387 struct ib_wc *wc);
3388
free_mr_send_cmd_to_hw(struct hns_roce_dev * hr_dev)3389 static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev)
3390 {
3391 struct hns_roce_v2_priv *priv = hr_dev->priv;
3392 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
3393 struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)];
3394 struct ib_device *ibdev = &hr_dev->ib_dev;
3395 struct hns_roce_qp *hr_qp;
3396 unsigned long end;
3397 int cqe_cnt = 0;
3398 int npolled;
3399 int ret;
3400 int i;
3401
3402 /*
3403 * If the device initialization is not complete or in the uninstall
3404 * process, then there is no need to execute free mr.
3405 */
3406 if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT ||
3407 priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT ||
3408 hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT)
3409 return;
3410
3411 mutex_lock(&free_mr->mutex);
3412
3413 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
3414 hr_qp = free_mr->rsv_qp[i];
3415
3416 ret = free_mr_post_send_lp_wqe(hr_qp);
3417 if (ret) {
3418 ibdev_err_ratelimited(ibdev,
3419 "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n",
3420 hr_qp->qpn, ret);
3421 break;
3422 }
3423
3424 cqe_cnt++;
3425 }
3426
3427 end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies;
3428 while (cqe_cnt) {
3429 npolled = hns_roce_v2_poll_cq(&free_mr->rsv_cq->ib_cq, cqe_cnt, wc);
3430 if (npolled < 0) {
3431 ibdev_err_ratelimited(ibdev,
3432 "failed to poll cqe for free mr, remain %d cqe.\n",
3433 cqe_cnt);
3434 goto out;
3435 }
3436
3437 if (time_after(jiffies, end)) {
3438 ibdev_err_ratelimited(ibdev,
3439 "failed to poll cqe for free mr and timeout, remain %d cqe.\n",
3440 cqe_cnt);
3441 goto out;
3442 }
3443 cqe_cnt -= npolled;
3444 }
3445
3446 out:
3447 mutex_unlock(&free_mr->mutex);
3448 }
3449
hns_roce_v2_dereg_mr(struct hns_roce_dev * hr_dev)3450 static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev)
3451 {
3452 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
3453 free_mr_send_cmd_to_hw(hr_dev);
3454 }
3455
get_cqe_v2(struct hns_roce_cq * hr_cq,int n)3456 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
3457 {
3458 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size);
3459 }
3460
get_sw_cqe_v2(struct hns_roce_cq * hr_cq,unsigned int n)3461 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n)
3462 {
3463 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
3464
3465 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
3466 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe :
3467 NULL;
3468 }
3469
update_cq_db(struct hns_roce_dev * hr_dev,struct hns_roce_cq * hr_cq)3470 static inline void update_cq_db(struct hns_roce_dev *hr_dev,
3471 struct hns_roce_cq *hr_cq)
3472 {
3473 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) {
3474 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M;
3475 } else {
3476 struct hns_roce_v2_db cq_db = {};
3477
3478 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn);
3479 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB);
3480 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index);
3481 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1);
3482
3483 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg);
3484 }
3485 }
3486
__hns_roce_v2_cq_clean(struct hns_roce_cq * hr_cq,u32 qpn,struct hns_roce_srq * srq)3487 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
3488 struct hns_roce_srq *srq)
3489 {
3490 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3491 struct hns_roce_v2_cqe *cqe, *dest;
3492 u32 prod_index;
3493 int nfreed = 0;
3494 int wqe_index;
3495 u8 owner_bit;
3496
3497 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index);
3498 ++prod_index) {
3499 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe)
3500 break;
3501 }
3502
3503 /*
3504 * Now backwards through the CQ, removing CQ entries
3505 * that match our QP by overwriting them with next entries.
3506 */
3507 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
3508 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe);
3509 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) {
3510 if (srq && hr_reg_read(cqe, CQE_S_R)) {
3511 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX);
3512 hns_roce_free_srq_wqe(srq, wqe_index);
3513 }
3514 ++nfreed;
3515 } else if (nfreed) {
3516 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) &
3517 hr_cq->ib_cq.cqe);
3518 owner_bit = hr_reg_read(dest, CQE_OWNER);
3519 memcpy(dest, cqe, hr_cq->cqe_size);
3520 hr_reg_write(dest, CQE_OWNER, owner_bit);
3521 }
3522 }
3523
3524 if (nfreed) {
3525 hr_cq->cons_index += nfreed;
3526 update_cq_db(hr_dev, hr_cq);
3527 }
3528 }
3529
hns_roce_v2_cq_clean(struct hns_roce_cq * hr_cq,u32 qpn,struct hns_roce_srq * srq)3530 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
3531 struct hns_roce_srq *srq)
3532 {
3533 spin_lock_irq(&hr_cq->lock);
3534 __hns_roce_v2_cq_clean(hr_cq, qpn, srq);
3535 spin_unlock_irq(&hr_cq->lock);
3536 }
3537
hns_roce_v2_write_cqc(struct hns_roce_dev * hr_dev,struct hns_roce_cq * hr_cq,void * mb_buf,u64 * mtts,dma_addr_t dma_handle)3538 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
3539 struct hns_roce_cq *hr_cq, void *mb_buf,
3540 u64 *mtts, dma_addr_t dma_handle)
3541 {
3542 struct hns_roce_v2_cq_context *cq_context;
3543
3544 cq_context = mb_buf;
3545 memset(cq_context, 0, sizeof(*cq_context));
3546
3547 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID);
3548 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED);
3549 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth));
3550 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector);
3551 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn);
3552
3553 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE)
3554 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B);
3555
3556 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH)
3557 hr_reg_enable(cq_context, CQC_STASH);
3558
3559 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L,
3560 to_hr_hw_page_addr(mtts[0]));
3561 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H,
3562 upper_32_bits(to_hr_hw_page_addr(mtts[0])));
3563 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num ==
3564 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num);
3565 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L,
3566 to_hr_hw_page_addr(mtts[1]));
3567 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H,
3568 upper_32_bits(to_hr_hw_page_addr(mtts[1])));
3569 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ,
3570 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift));
3571 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ,
3572 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift));
3573 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> 3);
3574 hr_reg_write(cq_context, CQC_CQE_BA_H, (dma_handle >> (32 + 3)));
3575 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN,
3576 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB);
3577 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L,
3578 ((u32)hr_cq->db.dma) >> 1);
3579 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H,
3580 hr_cq->db.dma >> 32);
3581 hr_reg_write(cq_context, CQC_CQ_MAX_CNT,
3582 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM);
3583 hr_reg_write(cq_context, CQC_CQ_PERIOD,
3584 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL);
3585 }
3586
hns_roce_v2_req_notify_cq(struct ib_cq * ibcq,enum ib_cq_notify_flags flags)3587 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
3588 enum ib_cq_notify_flags flags)
3589 {
3590 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3591 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3592 struct hns_roce_v2_db cq_db = {};
3593 u32 notify_flag;
3594
3595 /*
3596 * flags = 0, then notify_flag : next
3597 * flags = 1, then notify flag : solocited
3598 */
3599 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
3600 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
3601
3602 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn);
3603 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY);
3604 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index);
3605 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn);
3606 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag);
3607
3608 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg);
3609
3610 return 0;
3611 }
3612
sw_comp(struct hns_roce_qp * hr_qp,struct hns_roce_wq * wq,int num_entries,struct ib_wc * wc)3613 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq,
3614 int num_entries, struct ib_wc *wc)
3615 {
3616 unsigned int left;
3617 int npolled = 0;
3618
3619 left = wq->head - wq->tail;
3620 if (left == 0)
3621 return 0;
3622
3623 left = min_t(unsigned int, (unsigned int)num_entries, left);
3624 while (npolled < left) {
3625 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3626 wc->status = IB_WC_WR_FLUSH_ERR;
3627 wc->vendor_err = 0;
3628 wc->qp = &hr_qp->ibqp;
3629
3630 wq->tail++;
3631 wc++;
3632 npolled++;
3633 }
3634
3635 return npolled;
3636 }
3637
hns_roce_v2_sw_poll_cq(struct hns_roce_cq * hr_cq,int num_entries,struct ib_wc * wc)3638 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries,
3639 struct ib_wc *wc)
3640 {
3641 struct hns_roce_qp *hr_qp;
3642 int npolled = 0;
3643
3644 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) {
3645 npolled += sw_comp(hr_qp, &hr_qp->sq,
3646 num_entries - npolled, wc + npolled);
3647 if (npolled >= num_entries)
3648 goto out;
3649 }
3650
3651 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) {
3652 npolled += sw_comp(hr_qp, &hr_qp->rq,
3653 num_entries - npolled, wc + npolled);
3654 if (npolled >= num_entries)
3655 goto out;
3656 }
3657
3658 out:
3659 return npolled;
3660 }
3661
get_cqe_status(struct hns_roce_dev * hr_dev,struct hns_roce_qp * qp,struct hns_roce_cq * cq,struct hns_roce_v2_cqe * cqe,struct ib_wc * wc)3662 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
3663 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe,
3664 struct ib_wc *wc)
3665 {
3666 static const struct {
3667 u32 cqe_status;
3668 enum ib_wc_status wc_status;
3669 } map[] = {
3670 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS },
3671 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR },
3672 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR },
3673 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR },
3674 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR },
3675 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR },
3676 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR },
3677 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR },
3678 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR },
3679 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR },
3680 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR },
3681 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR,
3682 IB_WC_RETRY_EXC_ERR },
3683 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR },
3684 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR },
3685 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR}
3686 };
3687
3688 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS);
3689 int i;
3690
3691 wc->status = IB_WC_GENERAL_ERR;
3692 for (i = 0; i < ARRAY_SIZE(map); i++)
3693 if (cqe_status == map[i].cqe_status) {
3694 wc->status = map[i].wc_status;
3695 break;
3696 }
3697
3698 if (likely(wc->status == IB_WC_SUCCESS ||
3699 wc->status == IB_WC_WR_FLUSH_ERR))
3700 return;
3701
3702 ibdev_err_ratelimited(&hr_dev->ib_dev, "error cqe status 0x%x:\n",
3703 cqe_status);
3704 print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_NONE, 16, 4, cqe,
3705 cq->cqe_size, false);
3706 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS);
3707
3708 /*
3709 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in
3710 * the standard protocol, the driver must ignore it and needn't to set
3711 * the QP to an error state.
3712 */
3713 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR)
3714 return;
3715
3716 flush_cqe(hr_dev, qp);
3717 }
3718
get_cur_qp(struct hns_roce_cq * hr_cq,struct hns_roce_v2_cqe * cqe,struct hns_roce_qp ** cur_qp)3719 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe,
3720 struct hns_roce_qp **cur_qp)
3721 {
3722 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3723 struct hns_roce_qp *hr_qp = *cur_qp;
3724 u32 qpn;
3725
3726 qpn = hr_reg_read(cqe, CQE_LCL_QPN);
3727
3728 if (!hr_qp || qpn != hr_qp->qpn) {
3729 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
3730 if (unlikely(!hr_qp)) {
3731 ibdev_err(&hr_dev->ib_dev,
3732 "CQ %06lx with entry for unknown QPN %06x\n",
3733 hr_cq->cqn, qpn);
3734 return -EINVAL;
3735 }
3736 *cur_qp = hr_qp;
3737 }
3738
3739 return 0;
3740 }
3741
3742 /*
3743 * mapped-value = 1 + real-value
3744 * The ib wc opcode's real value is start from 0, In order to distinguish
3745 * between initialized and uninitialized map values, we plus 1 to the actual
3746 * value when defining the mapping, so that the validity can be identified by
3747 * checking whether the mapped value is greater than 0.
3748 */
3749 #define HR_WC_OP_MAP(hr_key, ib_key) \
3750 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key
3751
3752 static const u32 wc_send_op_map[] = {
3753 HR_WC_OP_MAP(SEND, SEND),
3754 HR_WC_OP_MAP(SEND_WITH_INV, SEND),
3755 HR_WC_OP_MAP(SEND_WITH_IMM, SEND),
3756 HR_WC_OP_MAP(RDMA_READ, RDMA_READ),
3757 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE),
3758 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE),
3759 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP),
3760 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD),
3761 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP),
3762 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD),
3763 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR),
3764 HR_WC_OP_MAP(BIND_MW, REG_MR),
3765 };
3766
to_ib_wc_send_op(u32 hr_opcode)3767 static int to_ib_wc_send_op(u32 hr_opcode)
3768 {
3769 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map))
3770 return -EINVAL;
3771
3772 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 :
3773 -EINVAL;
3774 }
3775
3776 static const u32 wc_recv_op_map[] = {
3777 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM),
3778 HR_WC_OP_MAP(SEND, RECV),
3779 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM),
3780 HR_WC_OP_MAP(SEND_WITH_INV, RECV),
3781 };
3782
to_ib_wc_recv_op(u32 hr_opcode)3783 static int to_ib_wc_recv_op(u32 hr_opcode)
3784 {
3785 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map))
3786 return -EINVAL;
3787
3788 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 :
3789 -EINVAL;
3790 }
3791
fill_send_wc(struct ib_wc * wc,struct hns_roce_v2_cqe * cqe)3792 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe)
3793 {
3794 u32 hr_opcode;
3795 int ib_opcode;
3796
3797 wc->wc_flags = 0;
3798
3799 hr_opcode = hr_reg_read(cqe, CQE_OPCODE);
3800 switch (hr_opcode) {
3801 case HNS_ROCE_V2_WQE_OP_RDMA_READ:
3802 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3803 break;
3804 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM:
3805 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM:
3806 wc->wc_flags |= IB_WC_WITH_IMM;
3807 break;
3808 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP:
3809 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD:
3810 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP:
3811 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD:
3812 wc->byte_len = 8;
3813 break;
3814 default:
3815 break;
3816 }
3817
3818 ib_opcode = to_ib_wc_send_op(hr_opcode);
3819 if (ib_opcode < 0)
3820 wc->status = IB_WC_GENERAL_ERR;
3821 else
3822 wc->opcode = ib_opcode;
3823 }
3824
fill_recv_wc(struct ib_wc * wc,struct hns_roce_v2_cqe * cqe)3825 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe)
3826 {
3827 u32 hr_opcode;
3828 int ib_opcode;
3829
3830 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3831
3832 hr_opcode = hr_reg_read(cqe, CQE_OPCODE);
3833 switch (hr_opcode) {
3834 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
3835 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
3836 wc->wc_flags = IB_WC_WITH_IMM;
3837 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata));
3838 break;
3839 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
3840 wc->wc_flags = IB_WC_WITH_INVALIDATE;
3841 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey);
3842 break;
3843 default:
3844 wc->wc_flags = 0;
3845 }
3846
3847 ib_opcode = to_ib_wc_recv_op(hr_opcode);
3848 if (ib_opcode < 0)
3849 wc->status = IB_WC_GENERAL_ERR;
3850 else
3851 wc->opcode = ib_opcode;
3852
3853 wc->sl = hr_reg_read(cqe, CQE_SL);
3854 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN);
3855 wc->slid = 0;
3856 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0;
3857 wc->port_num = hr_reg_read(cqe, CQE_PORTN);
3858 wc->pkey_index = 0;
3859
3860 if (hr_reg_read(cqe, CQE_VID_VLD)) {
3861 wc->vlan_id = hr_reg_read(cqe, CQE_VID);
3862 wc->wc_flags |= IB_WC_WITH_VLAN;
3863 } else {
3864 wc->vlan_id = 0xffff;
3865 }
3866
3867 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE);
3868
3869 return 0;
3870 }
3871
hns_roce_v2_poll_one(struct hns_roce_cq * hr_cq,struct hns_roce_qp ** cur_qp,struct ib_wc * wc)3872 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
3873 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
3874 {
3875 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3876 struct hns_roce_qp *qp = *cur_qp;
3877 struct hns_roce_srq *srq = NULL;
3878 struct hns_roce_v2_cqe *cqe;
3879 struct hns_roce_wq *wq;
3880 int is_send;
3881 u16 wqe_idx;
3882 int ret;
3883
3884 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
3885 if (!cqe)
3886 return -EAGAIN;
3887
3888 ++hr_cq->cons_index;
3889 /* Memory barrier */
3890 rmb();
3891
3892 ret = get_cur_qp(hr_cq, cqe, &qp);
3893 if (ret)
3894 return ret;
3895
3896 wc->qp = &qp->ibqp;
3897 wc->vendor_err = 0;
3898
3899 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX);
3900
3901 is_send = !hr_reg_read(cqe, CQE_S_R);
3902 if (is_send) {
3903 wq = &qp->sq;
3904
3905 /* If sg_signal_bit is set, tail pointer will be updated to
3906 * the WQE corresponding to the current CQE.
3907 */
3908 if (qp->sq_signal_bits)
3909 wq->tail += (wqe_idx - (u16)wq->tail) &
3910 (wq->wqe_cnt - 1);
3911
3912 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3913 ++wq->tail;
3914
3915 fill_send_wc(wc, cqe);
3916 } else {
3917 if (qp->ibqp.srq) {
3918 srq = to_hr_srq(qp->ibqp.srq);
3919 wc->wr_id = srq->wrid[wqe_idx];
3920 hns_roce_free_srq_wqe(srq, wqe_idx);
3921 } else {
3922 wq = &qp->rq;
3923 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3924 ++wq->tail;
3925 }
3926
3927 ret = fill_recv_wc(wc, cqe);
3928 }
3929
3930 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc);
3931 if (unlikely(wc->status != IB_WC_SUCCESS))
3932 return 0;
3933
3934 return ret;
3935 }
3936
hns_roce_v2_poll_cq(struct ib_cq * ibcq,int num_entries,struct ib_wc * wc)3937 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
3938 struct ib_wc *wc)
3939 {
3940 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3941 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3942 struct hns_roce_qp *cur_qp = NULL;
3943 unsigned long flags;
3944 int npolled;
3945
3946 spin_lock_irqsave(&hr_cq->lock, flags);
3947
3948 /*
3949 * When the device starts to reset, the state is RST_DOWN. At this time,
3950 * there may still be some valid CQEs in the hardware that are not
3951 * polled. Therefore, it is not allowed to switch to the software mode
3952 * immediately. When the state changes to UNINIT, CQE no longer exists
3953 * in the hardware, and then switch to software mode.
3954 */
3955 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) {
3956 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc);
3957 goto out;
3958 }
3959
3960 for (npolled = 0; npolled < num_entries; ++npolled) {
3961 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
3962 break;
3963 }
3964
3965 if (npolled)
3966 update_cq_db(hr_dev, hr_cq);
3967
3968 out:
3969 spin_unlock_irqrestore(&hr_cq->lock, flags);
3970
3971 return npolled;
3972 }
3973
get_op_for_set_hem(struct hns_roce_dev * hr_dev,u32 type,u32 step_idx,u8 * mbox_cmd)3974 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type,
3975 u32 step_idx, u8 *mbox_cmd)
3976 {
3977 u8 cmd;
3978
3979 switch (type) {
3980 case HEM_TYPE_QPC:
3981 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0;
3982 break;
3983 case HEM_TYPE_MTPT:
3984 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0;
3985 break;
3986 case HEM_TYPE_CQC:
3987 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0;
3988 break;
3989 case HEM_TYPE_SRQC:
3990 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0;
3991 break;
3992 case HEM_TYPE_SCCC:
3993 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0;
3994 break;
3995 case HEM_TYPE_QPC_TIMER:
3996 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0;
3997 break;
3998 case HEM_TYPE_CQC_TIMER:
3999 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0;
4000 break;
4001 default:
4002 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type);
4003 return -EINVAL;
4004 }
4005
4006 *mbox_cmd = cmd + step_idx;
4007
4008 return 0;
4009 }
4010
config_gmv_ba_to_hw(struct hns_roce_dev * hr_dev,unsigned long obj,dma_addr_t base_addr)4011 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj,
4012 dma_addr_t base_addr)
4013 {
4014 struct hns_roce_cmq_desc desc;
4015 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
4016 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz);
4017 u64 addr = to_hr_hw_page_addr(base_addr);
4018
4019 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false);
4020
4021 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr));
4022 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr));
4023 hr_reg_write(req, CFG_GMV_BT_IDX, idx);
4024
4025 return hns_roce_cmq_send(hr_dev, &desc, 1);
4026 }
4027
set_hem_to_hw(struct hns_roce_dev * hr_dev,int obj,dma_addr_t base_addr,u32 hem_type,u32 step_idx)4028 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj,
4029 dma_addr_t base_addr, u32 hem_type, u32 step_idx)
4030 {
4031 int ret;
4032 u8 cmd;
4033
4034 if (unlikely(hem_type == HEM_TYPE_GMV))
4035 return config_gmv_ba_to_hw(hr_dev, obj, base_addr);
4036
4037 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx))
4038 return 0;
4039
4040 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd);
4041 if (ret < 0)
4042 return ret;
4043
4044 return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj);
4045 }
4046
hns_roce_v2_set_hem(struct hns_roce_dev * hr_dev,struct hns_roce_hem_table * table,int obj,u32 step_idx)4047 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
4048 struct hns_roce_hem_table *table, int obj,
4049 u32 step_idx)
4050 {
4051 struct hns_roce_hem_iter iter;
4052 struct hns_roce_hem_mhop mhop;
4053 struct hns_roce_hem *hem;
4054 unsigned long mhop_obj = obj;
4055 int i, j, k;
4056 int ret = 0;
4057 u64 hem_idx = 0;
4058 u64 l1_idx = 0;
4059 u64 bt_ba = 0;
4060 u32 chunk_ba_num;
4061 u32 hop_num;
4062
4063 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
4064 return 0;
4065
4066 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
4067 i = mhop.l0_idx;
4068 j = mhop.l1_idx;
4069 k = mhop.l2_idx;
4070 hop_num = mhop.hop_num;
4071 chunk_ba_num = mhop.bt_chunk_size / 8;
4072
4073 if (hop_num == 2) {
4074 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num +
4075 k;
4076 l1_idx = i * chunk_ba_num + j;
4077 } else if (hop_num == 1) {
4078 hem_idx = i * chunk_ba_num + j;
4079 } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
4080 hem_idx = i;
4081 }
4082
4083 if (table->type == HEM_TYPE_SCCC)
4084 obj = mhop.l0_idx;
4085
4086 if (check_whether_last_step(hop_num, step_idx)) {
4087 hem = table->hem[hem_idx];
4088 for (hns_roce_hem_first(hem, &iter);
4089 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
4090 bt_ba = hns_roce_hem_addr(&iter);
4091 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type,
4092 step_idx);
4093 }
4094 } else {
4095 if (step_idx == 0)
4096 bt_ba = table->bt_l0_dma_addr[i];
4097 else if (step_idx == 1 && hop_num == 2)
4098 bt_ba = table->bt_l1_dma_addr[l1_idx];
4099
4100 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx);
4101 }
4102
4103 return ret;
4104 }
4105
hns_roce_v2_clear_hem(struct hns_roce_dev * hr_dev,struct hns_roce_hem_table * table,int tag,u32 step_idx)4106 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
4107 struct hns_roce_hem_table *table,
4108 int tag, u32 step_idx)
4109 {
4110 struct hns_roce_cmd_mailbox *mailbox;
4111 struct device *dev = hr_dev->dev;
4112 u8 cmd = 0xff;
4113 int ret;
4114
4115 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
4116 return 0;
4117
4118 switch (table->type) {
4119 case HEM_TYPE_QPC:
4120 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0;
4121 break;
4122 case HEM_TYPE_MTPT:
4123 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0;
4124 break;
4125 case HEM_TYPE_CQC:
4126 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0;
4127 break;
4128 case HEM_TYPE_SRQC:
4129 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
4130 break;
4131 case HEM_TYPE_SCCC:
4132 case HEM_TYPE_QPC_TIMER:
4133 case HEM_TYPE_CQC_TIMER:
4134 case HEM_TYPE_GMV:
4135 return 0;
4136 default:
4137 dev_warn(dev, "table %u not to be destroyed by mailbox!\n",
4138 table->type);
4139 return 0;
4140 }
4141
4142 cmd += step_idx;
4143
4144 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4145 if (IS_ERR(mailbox))
4146 return PTR_ERR(mailbox);
4147
4148 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag);
4149
4150 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4151 return ret;
4152 }
4153
hns_roce_v2_qp_modify(struct hns_roce_dev * hr_dev,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask,struct hns_roce_qp * hr_qp)4154 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
4155 struct hns_roce_v2_qp_context *context,
4156 struct hns_roce_v2_qp_context *qpc_mask,
4157 struct hns_roce_qp *hr_qp)
4158 {
4159 struct hns_roce_cmd_mailbox *mailbox;
4160 int qpc_size;
4161 int ret;
4162
4163 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4164 if (IS_ERR(mailbox))
4165 return PTR_ERR(mailbox);
4166
4167 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */
4168 qpc_size = hr_dev->caps.qpc_sz;
4169 memcpy(mailbox->buf, context, qpc_size);
4170 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size);
4171
4172 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
4173 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn);
4174
4175 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4176
4177 return ret;
4178 }
4179
set_access_flags(struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask,const struct ib_qp_attr * attr,int attr_mask)4180 static void set_access_flags(struct hns_roce_qp *hr_qp,
4181 struct hns_roce_v2_qp_context *context,
4182 struct hns_roce_v2_qp_context *qpc_mask,
4183 const struct ib_qp_attr *attr, int attr_mask)
4184 {
4185 u8 dest_rd_atomic;
4186 u32 access_flags;
4187
4188 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ?
4189 attr->max_dest_rd_atomic : hr_qp->resp_depth;
4190
4191 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ?
4192 attr->qp_access_flags : hr_qp->atomic_rd_en;
4193
4194 if (!dest_rd_atomic)
4195 access_flags &= IB_ACCESS_REMOTE_WRITE;
4196
4197 hr_reg_write_bool(context, QPC_RRE,
4198 access_flags & IB_ACCESS_REMOTE_READ);
4199 hr_reg_clear(qpc_mask, QPC_RRE);
4200
4201 hr_reg_write_bool(context, QPC_RWE,
4202 access_flags & IB_ACCESS_REMOTE_WRITE);
4203 hr_reg_clear(qpc_mask, QPC_RWE);
4204
4205 hr_reg_write_bool(context, QPC_ATE,
4206 access_flags & IB_ACCESS_REMOTE_ATOMIC);
4207 hr_reg_clear(qpc_mask, QPC_ATE);
4208 hr_reg_write_bool(context, QPC_EXT_ATE,
4209 access_flags & IB_ACCESS_REMOTE_ATOMIC);
4210 hr_reg_clear(qpc_mask, QPC_EXT_ATE);
4211 }
4212
set_qpc_wqe_cnt(struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * context)4213 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp,
4214 struct hns_roce_v2_qp_context *context)
4215 {
4216 hr_reg_write(context, QPC_SGE_SHIFT,
4217 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt,
4218 hr_qp->sge.sge_shift));
4219
4220 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt));
4221
4222 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt));
4223 }
4224
get_cqn(struct ib_cq * ib_cq)4225 static inline int get_cqn(struct ib_cq *ib_cq)
4226 {
4227 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0;
4228 }
4229
get_pdn(struct ib_pd * ib_pd)4230 static inline int get_pdn(struct ib_pd *ib_pd)
4231 {
4232 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0;
4233 }
4234
modify_qp_reset_to_init(struct ib_qp * ibqp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4235 static void modify_qp_reset_to_init(struct ib_qp *ibqp,
4236 struct hns_roce_v2_qp_context *context,
4237 struct hns_roce_v2_qp_context *qpc_mask)
4238 {
4239 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4240 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4241
4242 /*
4243 * In v2 engine, software pass context and context mask to hardware
4244 * when modifying qp. If software need modify some fields in context,
4245 * we should set all bits of the relevant fields in context mask to
4246 * 0 at the same time, else set them to 0x1.
4247 */
4248 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type));
4249
4250 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd));
4251
4252 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs));
4253
4254 set_qpc_wqe_cnt(hr_qp, context);
4255
4256 /* No VLAN need to set 0xFFF */
4257 hr_reg_write(context, QPC_VLAN_ID, 0xfff);
4258
4259 if (ibqp->qp_type == IB_QPT_XRC_TGT) {
4260 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn);
4261
4262 hr_reg_enable(context, QPC_XRC_QP_TYPE);
4263 }
4264
4265 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
4266 hr_reg_enable(context, QPC_RQ_RECORD_EN);
4267
4268 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
4269 hr_reg_enable(context, QPC_OWNER_MODE);
4270
4271 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L,
4272 lower_32_bits(hr_qp->rdb.dma) >> 1);
4273 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H,
4274 upper_32_bits(hr_qp->rdb.dma));
4275
4276 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq));
4277
4278 if (ibqp->srq) {
4279 hr_reg_enable(context, QPC_SRQ_EN);
4280 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn);
4281 }
4282
4283 hr_reg_enable(context, QPC_FRE);
4284
4285 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq));
4286
4287 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ)
4288 return;
4289
4290 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH)
4291 hr_reg_enable(&context->ext, QPCEX_STASH);
4292 }
4293
modify_qp_init_to_init(struct ib_qp * ibqp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4294 static void modify_qp_init_to_init(struct ib_qp *ibqp,
4295 struct hns_roce_v2_qp_context *context,
4296 struct hns_roce_v2_qp_context *qpc_mask)
4297 {
4298 /*
4299 * In v2 engine, software pass context and context mask to hardware
4300 * when modifying qp. If software need modify some fields in context,
4301 * we should set all bits of the relevant fields in context mask to
4302 * 0 at the same time, else set them to 0x1.
4303 */
4304 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type));
4305 hr_reg_clear(qpc_mask, QPC_TST);
4306
4307 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd));
4308 hr_reg_clear(qpc_mask, QPC_PD);
4309
4310 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq));
4311 hr_reg_clear(qpc_mask, QPC_RX_CQN);
4312
4313 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq));
4314 hr_reg_clear(qpc_mask, QPC_TX_CQN);
4315
4316 if (ibqp->srq) {
4317 hr_reg_enable(context, QPC_SRQ_EN);
4318 hr_reg_clear(qpc_mask, QPC_SRQ_EN);
4319 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn);
4320 hr_reg_clear(qpc_mask, QPC_SRQN);
4321 }
4322 }
4323
config_qp_rq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4324 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev,
4325 struct hns_roce_qp *hr_qp,
4326 struct hns_roce_v2_qp_context *context,
4327 struct hns_roce_v2_qp_context *qpc_mask)
4328 {
4329 u64 mtts[MTT_MIN_COUNT] = { 0 };
4330 u64 wqe_sge_ba;
4331 int ret;
4332
4333 /* Search qp buf's mtts */
4334 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts,
4335 MTT_MIN_COUNT);
4336 if (hr_qp->rq.wqe_cnt && ret) {
4337 ibdev_err(&hr_dev->ib_dev,
4338 "failed to find QP(0x%lx) RQ WQE buf, ret = %d.\n",
4339 hr_qp->qpn, ret);
4340 return ret;
4341 }
4342
4343 wqe_sge_ba = hns_roce_get_mtr_ba(&hr_qp->mtr);
4344
4345 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3);
4346 qpc_mask->wqe_sge_ba = 0;
4347
4348 /*
4349 * In v2 engine, software pass context and context mask to hardware
4350 * when modifying qp. If software need modify some fields in context,
4351 * we should set all bits of the relevant fields in context mask to
4352 * 0 at the same time, else set them to 0x1.
4353 */
4354 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3));
4355 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H);
4356
4357 hr_reg_write(context, QPC_SQ_HOP_NUM,
4358 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num,
4359 hr_qp->sq.wqe_cnt));
4360 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM);
4361
4362 hr_reg_write(context, QPC_SGE_HOP_NUM,
4363 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num,
4364 hr_qp->sge.sge_cnt));
4365 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM);
4366
4367 hr_reg_write(context, QPC_RQ_HOP_NUM,
4368 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num,
4369 hr_qp->rq.wqe_cnt));
4370
4371 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM);
4372
4373 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ,
4374 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift));
4375 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ);
4376
4377 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ,
4378 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift));
4379 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ);
4380
4381 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0]));
4382 qpc_mask->rq_cur_blk_addr = 0;
4383
4384 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H,
4385 upper_32_bits(to_hr_hw_page_addr(mtts[0])));
4386 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H);
4387
4388 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
4389 context->rq_nxt_blk_addr =
4390 cpu_to_le32(to_hr_hw_page_addr(mtts[1]));
4391 qpc_mask->rq_nxt_blk_addr = 0;
4392 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H,
4393 upper_32_bits(to_hr_hw_page_addr(mtts[1])));
4394 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H);
4395 }
4396
4397 return 0;
4398 }
4399
config_qp_sq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4400 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev,
4401 struct hns_roce_qp *hr_qp,
4402 struct hns_roce_v2_qp_context *context,
4403 struct hns_roce_v2_qp_context *qpc_mask)
4404 {
4405 struct ib_device *ibdev = &hr_dev->ib_dev;
4406 u64 sge_cur_blk = 0;
4407 u64 sq_cur_blk = 0;
4408 int ret;
4409
4410 /* search qp buf's mtts */
4411 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->sq.offset,
4412 &sq_cur_blk, 1);
4413 if (ret) {
4414 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ WQE buf, ret = %d.\n",
4415 hr_qp->qpn, ret);
4416 return ret;
4417 }
4418 if (hr_qp->sge.sge_cnt > 0) {
4419 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr,
4420 hr_qp->sge.offset, &sge_cur_blk, 1);
4421 if (ret) {
4422 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf, ret = %d.\n",
4423 hr_qp->qpn, ret);
4424 return ret;
4425 }
4426 }
4427
4428 /*
4429 * In v2 engine, software pass context and context mask to hardware
4430 * when modifying qp. If software need modify some fields in context,
4431 * we should set all bits of the relevant fields in context mask to
4432 * 0 at the same time, else set them to 0x1.
4433 */
4434 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L,
4435 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4436 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H,
4437 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4438 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L);
4439 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H);
4440
4441 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L,
4442 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk)));
4443 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H,
4444 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk)));
4445 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L);
4446 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H);
4447
4448 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L,
4449 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4450 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H,
4451 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4452 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L);
4453 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H);
4454
4455 return 0;
4456 }
4457
get_mtu(struct ib_qp * ibqp,const struct ib_qp_attr * attr)4458 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp,
4459 const struct ib_qp_attr *attr)
4460 {
4461 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD)
4462 return IB_MTU_4096;
4463
4464 return attr->path_mtu;
4465 }
4466
modify_qp_init_to_rtr(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask,struct ib_udata * udata)4467 static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
4468 const struct ib_qp_attr *attr, int attr_mask,
4469 struct hns_roce_v2_qp_context *context,
4470 struct hns_roce_v2_qp_context *qpc_mask,
4471 struct ib_udata *udata)
4472 {
4473 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(udata,
4474 struct hns_roce_ucontext, ibucontext);
4475 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4476 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4477 struct ib_device *ibdev = &hr_dev->ib_dev;
4478 dma_addr_t trrl_ba;
4479 dma_addr_t irrl_ba;
4480 enum ib_mtu ib_mtu;
4481 const u8 *smac;
4482 u8 lp_pktn_ini;
4483 u64 *mtts;
4484 u8 *dmac;
4485 u32 port;
4486 int mtu;
4487 int ret;
4488
4489 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask);
4490 if (ret) {
4491 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret);
4492 return ret;
4493 }
4494
4495 /* Search IRRL's mtts */
4496 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
4497 hr_qp->qpn, &irrl_ba);
4498 if (!mtts) {
4499 ibdev_err(ibdev, "failed to find qp irrl_table.\n");
4500 return -EINVAL;
4501 }
4502
4503 /* Search TRRL's mtts */
4504 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,
4505 hr_qp->qpn, &trrl_ba);
4506 if (!mtts) {
4507 ibdev_err(ibdev, "failed to find qp trrl_table.\n");
4508 return -EINVAL;
4509 }
4510
4511 if (attr_mask & IB_QP_ALT_PATH) {
4512 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n",
4513 attr_mask);
4514 return -EINVAL;
4515 }
4516
4517 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> 4);
4518 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L);
4519 context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4));
4520 qpc_mask->trrl_ba = 0;
4521 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> (32 + 16 + 4));
4522 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H);
4523
4524 context->irrl_ba = cpu_to_le32(irrl_ba >> 6);
4525 qpc_mask->irrl_ba = 0;
4526 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> (32 + 6));
4527 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H);
4528
4529 hr_reg_enable(context, QPC_RMT_E2E);
4530 hr_reg_clear(qpc_mask, QPC_RMT_E2E);
4531
4532 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits);
4533 hr_reg_clear(qpc_mask, QPC_SIG_TYPE);
4534
4535 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port;
4536
4537 smac = (const u8 *)hr_dev->dev_addr[port];
4538 dmac = (u8 *)attr->ah_attr.roce.dmac;
4539 /* when dmac equals smac or loop_idc is 1, it should loopback */
4540 if (ether_addr_equal_unaligned(dmac, smac) ||
4541 hr_dev->loop_idc == 0x1) {
4542 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc);
4543 hr_reg_clear(qpc_mask, QPC_LBI);
4544 }
4545
4546 if (attr_mask & IB_QP_DEST_QPN) {
4547 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num);
4548 hr_reg_clear(qpc_mask, QPC_DQPN);
4549 }
4550
4551 memcpy(&context->dmac, dmac, sizeof(u32));
4552 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4])));
4553 qpc_mask->dmac = 0;
4554 hr_reg_clear(qpc_mask, QPC_DMAC_H);
4555
4556 ib_mtu = get_mtu(ibqp, attr);
4557 hr_qp->path_mtu = ib_mtu;
4558
4559 mtu = ib_mtu_enum_to_int(ib_mtu);
4560 if (WARN_ON(mtu <= 0))
4561 return -EINVAL;
4562 #define MIN_LP_MSG_LEN 1024
4563 /* mtu * (2 ^ lp_pktn_ini) should be in the range of 1024 to mtu */
4564 lp_pktn_ini = ilog2(max(mtu, MIN_LP_MSG_LEN) / mtu);
4565
4566 if (attr_mask & IB_QP_PATH_MTU) {
4567 hr_reg_write(context, QPC_MTU, ib_mtu);
4568 hr_reg_clear(qpc_mask, QPC_MTU);
4569 }
4570
4571 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini);
4572 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI);
4573
4574 /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */
4575 hr_reg_write(context, QPC_ACK_REQ_FREQ, lp_pktn_ini);
4576 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ);
4577
4578 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR);
4579 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN);
4580 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE);
4581
4582 context->rq_rnr_timer = 0;
4583 qpc_mask->rq_rnr_timer = 0;
4584
4585 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX);
4586 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX);
4587
4588 /* rocee send 2^lp_sgen_ini segs every time */
4589 hr_reg_write(context, QPC_LP_SGEN_INI, 3);
4590 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI);
4591
4592 if (udata && ibqp->qp_type == IB_QPT_RC &&
4593 (uctx->config & HNS_ROCE_RQ_INLINE_FLAGS)) {
4594 hr_reg_write_bool(context, QPC_RQIE,
4595 hr_dev->caps.flags &
4596 HNS_ROCE_CAP_FLAG_RQ_INLINE);
4597 hr_reg_clear(qpc_mask, QPC_RQIE);
4598 }
4599
4600 if (udata &&
4601 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_XRC_TGT) &&
4602 (uctx->config & HNS_ROCE_CQE_INLINE_FLAGS)) {
4603 hr_reg_write_bool(context, QPC_CQEIE,
4604 hr_dev->caps.flags &
4605 HNS_ROCE_CAP_FLAG_CQE_INLINE);
4606 hr_reg_clear(qpc_mask, QPC_CQEIE);
4607
4608 hr_reg_write(context, QPC_CQEIS, 0);
4609 hr_reg_clear(qpc_mask, QPC_CQEIS);
4610 }
4611
4612 return 0;
4613 }
4614
modify_qp_rtr_to_rts(struct ib_qp * ibqp,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4615 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, int attr_mask,
4616 struct hns_roce_v2_qp_context *context,
4617 struct hns_roce_v2_qp_context *qpc_mask)
4618 {
4619 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4620 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4621 struct ib_device *ibdev = &hr_dev->ib_dev;
4622 int ret;
4623
4624 /* Not support alternate path and path migration */
4625 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) {
4626 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask);
4627 return -EINVAL;
4628 }
4629
4630 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask);
4631 if (ret) {
4632 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret);
4633 return ret;
4634 }
4635
4636 /*
4637 * Set some fields in context to zero, Because the default values
4638 * of all fields in context are zero, we need not set them to 0 again.
4639 * but we should set the relevant fields of context mask to 0.
4640 */
4641 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX);
4642
4643 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN);
4644
4645 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE);
4646 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD);
4647 hr_reg_clear(qpc_mask, QPC_IRRL_PSN);
4648
4649 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL);
4650
4651 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN);
4652
4653 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG);
4654
4655 hr_reg_clear(qpc_mask, QPC_CHECK_FLG);
4656
4657 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD);
4658
4659 return 0;
4660 }
4661
get_dip_ctx_idx(struct ib_qp * ibqp,const struct ib_qp_attr * attr,u32 * dip_idx)4662 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
4663 u32 *dip_idx)
4664 {
4665 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4666 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4667 u32 *spare_idx = hr_dev->qp_table.idx_table.spare_idx;
4668 u32 *head = &hr_dev->qp_table.idx_table.head;
4669 u32 *tail = &hr_dev->qp_table.idx_table.tail;
4670 struct hns_roce_dip *hr_dip;
4671 unsigned long flags;
4672 int ret = 0;
4673
4674 spin_lock_irqsave(&hr_dev->dip_list_lock, flags);
4675
4676 spare_idx[*tail] = ibqp->qp_num;
4677 *tail = (*tail == hr_dev->caps.num_qps - 1) ? 0 : (*tail + 1);
4678
4679 list_for_each_entry(hr_dip, &hr_dev->dip_list, node) {
4680 if (!memcmp(grh->dgid.raw, hr_dip->dgid, 16)) {
4681 *dip_idx = hr_dip->dip_idx;
4682 goto out;
4683 }
4684 }
4685
4686 /* If no dgid is found, a new dip and a mapping between dgid and
4687 * dip_idx will be created.
4688 */
4689 hr_dip = kzalloc(sizeof(*hr_dip), GFP_ATOMIC);
4690 if (!hr_dip) {
4691 ret = -ENOMEM;
4692 goto out;
4693 }
4694
4695 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
4696 hr_dip->dip_idx = *dip_idx = spare_idx[*head];
4697 *head = (*head == hr_dev->caps.num_qps - 1) ? 0 : (*head + 1);
4698 list_add_tail(&hr_dip->node, &hr_dev->dip_list);
4699
4700 out:
4701 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags);
4702 return ret;
4703 }
4704
4705 enum {
4706 CONG_DCQCN,
4707 CONG_WINDOW,
4708 };
4709
4710 enum {
4711 UNSUPPORT_CONG_LEVEL,
4712 SUPPORT_CONG_LEVEL,
4713 };
4714
4715 enum {
4716 CONG_LDCP,
4717 CONG_HC3,
4718 };
4719
4720 enum {
4721 DIP_INVALID,
4722 DIP_VALID,
4723 };
4724
4725 enum {
4726 WND_LIMIT,
4727 WND_UNLIMIT,
4728 };
4729
check_cong_type(struct ib_qp * ibqp,struct hns_roce_congestion_algorithm * cong_alg)4730 static int check_cong_type(struct ib_qp *ibqp,
4731 struct hns_roce_congestion_algorithm *cong_alg)
4732 {
4733 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4734 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4735
4736 if (ibqp->qp_type == IB_QPT_UD || ibqp->qp_type == IB_QPT_GSI)
4737 hr_qp->cong_type = CONG_TYPE_DCQCN;
4738 else
4739 hr_qp->cong_type = hr_dev->caps.cong_type;
4740
4741 /* different congestion types match different configurations */
4742 switch (hr_qp->cong_type) {
4743 case CONG_TYPE_DCQCN:
4744 cong_alg->alg_sel = CONG_DCQCN;
4745 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4746 cong_alg->dip_vld = DIP_INVALID;
4747 cong_alg->wnd_mode_sel = WND_LIMIT;
4748 break;
4749 case CONG_TYPE_LDCP:
4750 cong_alg->alg_sel = CONG_WINDOW;
4751 cong_alg->alg_sub_sel = CONG_LDCP;
4752 cong_alg->dip_vld = DIP_INVALID;
4753 cong_alg->wnd_mode_sel = WND_UNLIMIT;
4754 break;
4755 case CONG_TYPE_HC3:
4756 cong_alg->alg_sel = CONG_WINDOW;
4757 cong_alg->alg_sub_sel = CONG_HC3;
4758 cong_alg->dip_vld = DIP_INVALID;
4759 cong_alg->wnd_mode_sel = WND_LIMIT;
4760 break;
4761 case CONG_TYPE_DIP:
4762 cong_alg->alg_sel = CONG_DCQCN;
4763 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4764 cong_alg->dip_vld = DIP_VALID;
4765 cong_alg->wnd_mode_sel = WND_LIMIT;
4766 break;
4767 default:
4768 ibdev_warn(&hr_dev->ib_dev,
4769 "invalid type(%u) for congestion selection.\n",
4770 hr_qp->cong_type);
4771 hr_qp->cong_type = CONG_TYPE_DCQCN;
4772 cong_alg->alg_sel = CONG_DCQCN;
4773 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4774 cong_alg->dip_vld = DIP_INVALID;
4775 cong_alg->wnd_mode_sel = WND_LIMIT;
4776 break;
4777 }
4778
4779 return 0;
4780 }
4781
fill_cong_field(struct ib_qp * ibqp,const struct ib_qp_attr * attr,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4782 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
4783 struct hns_roce_v2_qp_context *context,
4784 struct hns_roce_v2_qp_context *qpc_mask)
4785 {
4786 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4787 struct hns_roce_congestion_algorithm cong_field;
4788 struct ib_device *ibdev = ibqp->device;
4789 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
4790 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4791 u32 dip_idx = 0;
4792 int ret;
4793
4794 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ||
4795 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE)
4796 return 0;
4797
4798 ret = check_cong_type(ibqp, &cong_field);
4799 if (ret)
4800 return ret;
4801
4802 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id +
4803 hr_qp->cong_type * HNS_ROCE_CONG_SIZE);
4804 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID);
4805 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel);
4806 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL);
4807 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL,
4808 cong_field.alg_sub_sel);
4809 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL);
4810 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld);
4811 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD);
4812 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN,
4813 cong_field.wnd_mode_sel);
4814 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN);
4815
4816 /* if dip is disabled, there is no need to set dip idx */
4817 if (cong_field.dip_vld == 0)
4818 return 0;
4819
4820 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx);
4821 if (ret) {
4822 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret);
4823 return ret;
4824 }
4825
4826 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx);
4827 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0);
4828
4829 return 0;
4830 }
4831
hns_roce_v2_set_path(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)4832 static int hns_roce_v2_set_path(struct ib_qp *ibqp,
4833 const struct ib_qp_attr *attr,
4834 int attr_mask,
4835 struct hns_roce_v2_qp_context *context,
4836 struct hns_roce_v2_qp_context *qpc_mask)
4837 {
4838 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4839 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4840 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4841 struct ib_device *ibdev = &hr_dev->ib_dev;
4842 const struct ib_gid_attr *gid_attr = NULL;
4843 u8 sl = rdma_ah_get_sl(&attr->ah_attr);
4844 int is_roce_protocol;
4845 u16 vlan_id = 0xffff;
4846 bool is_udp = false;
4847 u32 max_sl;
4848 u8 ib_port;
4849 u8 hr_port;
4850 int ret;
4851
4852 max_sl = min_t(u32, MAX_SERVICE_LEVEL, hr_dev->caps.sl_num - 1);
4853 if (unlikely(sl > max_sl)) {
4854 ibdev_err_ratelimited(ibdev,
4855 "failed to fill QPC, sl (%u) shouldn't be larger than %u.\n",
4856 sl, max_sl);
4857 return -EINVAL;
4858 }
4859
4860 /*
4861 * If free_mr_en of qp is set, it means that this qp comes from
4862 * free mr. This qp will perform the loopback operation.
4863 * In the loopback scenario, only sl needs to be set.
4864 */
4865 if (hr_qp->free_mr_en) {
4866 hr_reg_write(context, QPC_SL, sl);
4867 hr_reg_clear(qpc_mask, QPC_SL);
4868 hr_qp->sl = sl;
4869 return 0;
4870 }
4871
4872 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1;
4873 hr_port = ib_port - 1;
4874 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) &&
4875 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
4876
4877 if (is_roce_protocol) {
4878 gid_attr = attr->ah_attr.grh.sgid_attr;
4879 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL);
4880 if (ret)
4881 return ret;
4882
4883 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP);
4884 }
4885
4886 /* Only HIP08 needs to set the vlan_en bits in QPC */
4887 if (vlan_id < VLAN_N_VID &&
4888 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
4889 hr_reg_enable(context, QPC_RQ_VLAN_EN);
4890 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN);
4891 hr_reg_enable(context, QPC_SQ_VLAN_EN);
4892 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN);
4893 }
4894
4895 hr_reg_write(context, QPC_VLAN_ID, vlan_id);
4896 hr_reg_clear(qpc_mask, QPC_VLAN_ID);
4897
4898 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) {
4899 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n",
4900 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]);
4901 return -EINVAL;
4902 }
4903
4904 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) {
4905 ibdev_err(ibdev, "ah attr is not RDMA roce type\n");
4906 return -EINVAL;
4907 }
4908
4909 hr_reg_write(context, QPC_UDPSPN,
4910 is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num,
4911 attr->dest_qp_num) :
4912 0);
4913
4914 hr_reg_clear(qpc_mask, QPC_UDPSPN);
4915
4916 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index);
4917
4918 hr_reg_clear(qpc_mask, QPC_GMV_IDX);
4919
4920 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit);
4921 hr_reg_clear(qpc_mask, QPC_HOPLIMIT);
4922
4923 ret = fill_cong_field(ibqp, attr, context, qpc_mask);
4924 if (ret)
4925 return ret;
4926
4927 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh));
4928 hr_reg_clear(qpc_mask, QPC_TC);
4929
4930 hr_reg_write(context, QPC_FL, grh->flow_label);
4931 hr_reg_clear(qpc_mask, QPC_FL);
4932 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
4933 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw));
4934
4935 hr_qp->sl = sl;
4936 hr_reg_write(context, QPC_SL, hr_qp->sl);
4937 hr_reg_clear(qpc_mask, QPC_SL);
4938
4939 return 0;
4940 }
4941
check_qp_state(enum ib_qp_state cur_state,enum ib_qp_state new_state)4942 static bool check_qp_state(enum ib_qp_state cur_state,
4943 enum ib_qp_state new_state)
4944 {
4945 static const bool sm[][IB_QPS_ERR + 1] = {
4946 [IB_QPS_RESET] = { [IB_QPS_RESET] = true,
4947 [IB_QPS_INIT] = true },
4948 [IB_QPS_INIT] = { [IB_QPS_RESET] = true,
4949 [IB_QPS_INIT] = true,
4950 [IB_QPS_RTR] = true,
4951 [IB_QPS_ERR] = true },
4952 [IB_QPS_RTR] = { [IB_QPS_RESET] = true,
4953 [IB_QPS_RTS] = true,
4954 [IB_QPS_ERR] = true },
4955 [IB_QPS_RTS] = { [IB_QPS_RESET] = true,
4956 [IB_QPS_RTS] = true,
4957 [IB_QPS_ERR] = true },
4958 [IB_QPS_SQD] = {},
4959 [IB_QPS_SQE] = {},
4960 [IB_QPS_ERR] = { [IB_QPS_RESET] = true,
4961 [IB_QPS_ERR] = true }
4962 };
4963
4964 return sm[cur_state][new_state];
4965 }
4966
hns_roce_v2_set_abs_fields(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask,struct ib_udata * udata)4967 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp,
4968 const struct ib_qp_attr *attr,
4969 int attr_mask,
4970 enum ib_qp_state cur_state,
4971 enum ib_qp_state new_state,
4972 struct hns_roce_v2_qp_context *context,
4973 struct hns_roce_v2_qp_context *qpc_mask,
4974 struct ib_udata *udata)
4975 {
4976 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4977 int ret = 0;
4978
4979 if (!check_qp_state(cur_state, new_state))
4980 return -EINVAL;
4981
4982 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
4983 memset(qpc_mask, 0, hr_dev->caps.qpc_sz);
4984 modify_qp_reset_to_init(ibqp, context, qpc_mask);
4985 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
4986 modify_qp_init_to_init(ibqp, context, qpc_mask);
4987 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
4988 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context,
4989 qpc_mask, udata);
4990 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
4991 ret = modify_qp_rtr_to_rts(ibqp, attr_mask, context, qpc_mask);
4992 }
4993
4994 return ret;
4995 }
4996
check_qp_timeout_cfg_range(struct hns_roce_dev * hr_dev,u8 * timeout)4997 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout)
4998 {
4999 #define QP_ACK_TIMEOUT_MAX_HIP08 20
5000 #define QP_ACK_TIMEOUT_MAX 31
5001
5002 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
5003 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) {
5004 ibdev_warn(&hr_dev->ib_dev,
5005 "local ACK timeout shall be 0 to 20.\n");
5006 return false;
5007 }
5008 *timeout += HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08;
5009 } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) {
5010 if (*timeout > QP_ACK_TIMEOUT_MAX) {
5011 ibdev_warn(&hr_dev->ib_dev,
5012 "local ACK timeout shall be 0 to 31.\n");
5013 return false;
5014 }
5015 }
5016
5017 return true;
5018 }
5019
hns_roce_v2_set_opt_fields(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)5020 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp,
5021 const struct ib_qp_attr *attr,
5022 int attr_mask,
5023 struct hns_roce_v2_qp_context *context,
5024 struct hns_roce_v2_qp_context *qpc_mask)
5025 {
5026 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5027 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5028 int ret = 0;
5029 u8 timeout;
5030
5031 if (attr_mask & IB_QP_AV) {
5032 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context,
5033 qpc_mask);
5034 if (ret)
5035 return ret;
5036 }
5037
5038 if (attr_mask & IB_QP_TIMEOUT) {
5039 timeout = attr->timeout;
5040 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) {
5041 hr_reg_write(context, QPC_AT, timeout);
5042 hr_reg_clear(qpc_mask, QPC_AT);
5043 }
5044 }
5045
5046 if (attr_mask & IB_QP_RETRY_CNT) {
5047 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt);
5048 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT);
5049
5050 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt);
5051 hr_reg_clear(qpc_mask, QPC_RETRY_CNT);
5052 }
5053
5054 if (attr_mask & IB_QP_RNR_RETRY) {
5055 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry);
5056 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT);
5057
5058 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry);
5059 hr_reg_clear(qpc_mask, QPC_RNR_CNT);
5060 }
5061
5062 if (attr_mask & IB_QP_SQ_PSN) {
5063 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn);
5064 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN);
5065
5066 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn);
5067 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN);
5068
5069 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn);
5070 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L);
5071
5072 hr_reg_write(context, QPC_RETRY_MSG_PSN_H,
5073 attr->sq_psn >> RETRY_MSG_PSN_SHIFT);
5074 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H);
5075
5076 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn);
5077 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN);
5078
5079 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn);
5080 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN);
5081 }
5082
5083 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) &&
5084 attr->max_dest_rd_atomic) {
5085 hr_reg_write(context, QPC_RR_MAX,
5086 fls(attr->max_dest_rd_atomic - 1));
5087 hr_reg_clear(qpc_mask, QPC_RR_MAX);
5088 }
5089
5090 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) {
5091 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1));
5092 hr_reg_clear(qpc_mask, QPC_SR_MAX);
5093 }
5094
5095 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
5096 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask);
5097
5098 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
5099 hr_reg_write(context, QPC_MIN_RNR_TIME,
5100 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ?
5101 HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer);
5102 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME);
5103 }
5104
5105 if (attr_mask & IB_QP_RQ_PSN) {
5106 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn);
5107 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN);
5108
5109 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1);
5110 hr_reg_clear(qpc_mask, QPC_RAQ_PSN);
5111 }
5112
5113 if (attr_mask & IB_QP_QKEY) {
5114 context->qkey_xrcd = cpu_to_le32(attr->qkey);
5115 qpc_mask->qkey_xrcd = 0;
5116 hr_qp->qkey = attr->qkey;
5117 }
5118
5119 return ret;
5120 }
5121
hns_roce_v2_record_opt_fields(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask)5122 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp,
5123 const struct ib_qp_attr *attr,
5124 int attr_mask)
5125 {
5126 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5127 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5128
5129 if (attr_mask & IB_QP_ACCESS_FLAGS)
5130 hr_qp->atomic_rd_en = attr->qp_access_flags;
5131
5132 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
5133 hr_qp->resp_depth = attr->max_dest_rd_atomic;
5134 if (attr_mask & IB_QP_PORT) {
5135 hr_qp->port = attr->port_num - 1;
5136 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
5137 }
5138 }
5139
clear_qp(struct hns_roce_qp * hr_qp)5140 static void clear_qp(struct hns_roce_qp *hr_qp)
5141 {
5142 struct ib_qp *ibqp = &hr_qp->ibqp;
5143
5144 if (ibqp->send_cq)
5145 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq),
5146 hr_qp->qpn, NULL);
5147
5148 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq)
5149 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq),
5150 hr_qp->qpn, ibqp->srq ?
5151 to_hr_srq(ibqp->srq) : NULL);
5152
5153 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
5154 *hr_qp->rdb.db_record = 0;
5155
5156 hr_qp->rq.head = 0;
5157 hr_qp->rq.tail = 0;
5158 hr_qp->sq.head = 0;
5159 hr_qp->sq.tail = 0;
5160 hr_qp->next_sge = 0;
5161 }
5162
v2_set_flushed_fields(struct ib_qp * ibqp,struct hns_roce_v2_qp_context * context,struct hns_roce_v2_qp_context * qpc_mask)5163 static void v2_set_flushed_fields(struct ib_qp *ibqp,
5164 struct hns_roce_v2_qp_context *context,
5165 struct hns_roce_v2_qp_context *qpc_mask)
5166 {
5167 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5168 unsigned long sq_flag = 0;
5169 unsigned long rq_flag = 0;
5170
5171 if (ibqp->qp_type == IB_QPT_XRC_TGT)
5172 return;
5173
5174 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag);
5175 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head);
5176 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX);
5177 hr_qp->state = IB_QPS_ERR;
5178 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag);
5179
5180 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */
5181 return;
5182
5183 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag);
5184 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head);
5185 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX);
5186 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag);
5187 }
5188
hns_roce_v2_modify_qp(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state,struct ib_udata * udata)5189 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
5190 const struct ib_qp_attr *attr,
5191 int attr_mask, enum ib_qp_state cur_state,
5192 enum ib_qp_state new_state, struct ib_udata *udata)
5193 {
5194 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5195 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5196 struct hns_roce_v2_qp_context ctx[2];
5197 struct hns_roce_v2_qp_context *context = ctx;
5198 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1;
5199 struct ib_device *ibdev = &hr_dev->ib_dev;
5200 int ret;
5201
5202 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
5203 return -EOPNOTSUPP;
5204
5205 /*
5206 * In v2 engine, software pass context and context mask to hardware
5207 * when modifying qp. If software need modify some fields in context,
5208 * we should set all bits of the relevant fields in context mask to
5209 * 0 at the same time, else set them to 0x1.
5210 */
5211 memset(context, 0, hr_dev->caps.qpc_sz);
5212 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz);
5213
5214 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state,
5215 new_state, context, qpc_mask, udata);
5216 if (ret)
5217 goto out;
5218
5219 /* When QP state is err, SQ and RQ WQE should be flushed */
5220 if (new_state == IB_QPS_ERR)
5221 v2_set_flushed_fields(ibqp, context, qpc_mask);
5222
5223 /* Configure the optional fields */
5224 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context,
5225 qpc_mask);
5226 if (ret)
5227 goto out;
5228
5229 hr_reg_write_bool(context, QPC_INV_CREDIT,
5230 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC ||
5231 ibqp->srq);
5232 hr_reg_clear(qpc_mask, QPC_INV_CREDIT);
5233
5234 /* Every status migrate must change state */
5235 hr_reg_write(context, QPC_QP_ST, new_state);
5236 hr_reg_clear(qpc_mask, QPC_QP_ST);
5237
5238 /* SW pass context to HW */
5239 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp);
5240 if (ret) {
5241 ibdev_err_ratelimited(ibdev, "failed to modify QP, ret = %d.\n", ret);
5242 goto out;
5243 }
5244
5245 hr_qp->state = new_state;
5246
5247 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask);
5248
5249 if (new_state == IB_QPS_RESET && !ibqp->uobject)
5250 clear_qp(hr_qp);
5251
5252 out:
5253 return ret;
5254 }
5255
to_ib_qp_st(enum hns_roce_v2_qp_state state)5256 static int to_ib_qp_st(enum hns_roce_v2_qp_state state)
5257 {
5258 static const enum ib_qp_state map[] = {
5259 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET,
5260 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT,
5261 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR,
5262 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS,
5263 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD,
5264 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE,
5265 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR,
5266 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD
5267 };
5268
5269 return (state < ARRAY_SIZE(map)) ? map[state] : -1;
5270 }
5271
hns_roce_v2_query_qpc(struct hns_roce_dev * hr_dev,u32 qpn,void * buffer)5272 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn,
5273 void *buffer)
5274 {
5275 struct hns_roce_cmd_mailbox *mailbox;
5276 int ret;
5277
5278 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5279 if (IS_ERR(mailbox))
5280 return PTR_ERR(mailbox);
5281
5282 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC,
5283 qpn);
5284 if (ret)
5285 goto out;
5286
5287 memcpy(buffer, mailbox->buf, hr_dev->caps.qpc_sz);
5288
5289 out:
5290 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5291 return ret;
5292 }
5293
get_qp_timeout_attr(struct hns_roce_dev * hr_dev,struct hns_roce_v2_qp_context * context)5294 static u8 get_qp_timeout_attr(struct hns_roce_dev *hr_dev,
5295 struct hns_roce_v2_qp_context *context)
5296 {
5297 u8 timeout;
5298
5299 timeout = (u8)hr_reg_read(context, QPC_AT);
5300 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
5301 timeout -= HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08;
5302
5303 return timeout;
5304 }
5305
hns_roce_v2_query_qp(struct ib_qp * ibqp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)5306 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5307 int qp_attr_mask,
5308 struct ib_qp_init_attr *qp_init_attr)
5309 {
5310 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5311 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5312 struct hns_roce_v2_qp_context context = {};
5313 struct ib_device *ibdev = &hr_dev->ib_dev;
5314 int tmp_qp_state;
5315 int state;
5316 int ret;
5317
5318 memset(qp_attr, 0, sizeof(*qp_attr));
5319 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5320
5321 mutex_lock(&hr_qp->mutex);
5322
5323 if (hr_qp->state == IB_QPS_RESET) {
5324 qp_attr->qp_state = IB_QPS_RESET;
5325 ret = 0;
5326 goto done;
5327 }
5328
5329 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp->qpn, &context);
5330 if (ret) {
5331 ibdev_err_ratelimited(ibdev,
5332 "failed to query QPC, ret = %d.\n",
5333 ret);
5334 ret = -EINVAL;
5335 goto out;
5336 }
5337
5338 state = hr_reg_read(&context, QPC_QP_ST);
5339 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
5340 if (tmp_qp_state == -1) {
5341 ibdev_err_ratelimited(ibdev, "Illegal ib_qp_state\n");
5342 ret = -EINVAL;
5343 goto out;
5344 }
5345 hr_qp->state = (u8)tmp_qp_state;
5346 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
5347 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU);
5348 qp_attr->path_mig_state = IB_MIG_ARMED;
5349 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
5350 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
5351 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd);
5352
5353 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN);
5354 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN);
5355 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN);
5356 qp_attr->qp_access_flags =
5357 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) |
5358 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) |
5359 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S);
5360
5361 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
5362 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
5363 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) {
5364 struct ib_global_route *grh =
5365 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
5366
5367 rdma_ah_set_sl(&qp_attr->ah_attr,
5368 hr_reg_read(&context, QPC_SL));
5369 rdma_ah_set_port_num(&qp_attr->ah_attr, hr_qp->port + 1);
5370 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH);
5371 grh->flow_label = hr_reg_read(&context, QPC_FL);
5372 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX);
5373 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT);
5374 grh->traffic_class = hr_reg_read(&context, QPC_TC);
5375
5376 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw));
5377 }
5378
5379 qp_attr->port_num = hr_qp->port + 1;
5380 qp_attr->sq_draining = 0;
5381 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX);
5382 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX);
5383
5384 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME);
5385 qp_attr->timeout = get_qp_timeout_attr(hr_dev, &context);
5386 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT);
5387 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT);
5388
5389 done:
5390 qp_attr->cur_qp_state = qp_attr->qp_state;
5391 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
5392 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge;
5393 qp_attr->cap.max_inline_data = hr_qp->max_inline_data;
5394
5395 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
5396 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
5397
5398 qp_init_attr->qp_context = ibqp->qp_context;
5399 qp_init_attr->qp_type = ibqp->qp_type;
5400 qp_init_attr->recv_cq = ibqp->recv_cq;
5401 qp_init_attr->send_cq = ibqp->send_cq;
5402 qp_init_attr->srq = ibqp->srq;
5403 qp_init_attr->cap = qp_attr->cap;
5404 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits;
5405
5406 out:
5407 mutex_unlock(&hr_qp->mutex);
5408 return ret;
5409 }
5410
modify_qp_is_ok(struct hns_roce_qp * hr_qp)5411 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp)
5412 {
5413 return ((hr_qp->ibqp.qp_type == IB_QPT_RC ||
5414 hr_qp->ibqp.qp_type == IB_QPT_UD ||
5415 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
5416 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) &&
5417 hr_qp->state != IB_QPS_RESET);
5418 }
5419
hns_roce_v2_destroy_qp_common(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,struct ib_udata * udata)5420 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
5421 struct hns_roce_qp *hr_qp,
5422 struct ib_udata *udata)
5423 {
5424 struct ib_device *ibdev = &hr_dev->ib_dev;
5425 struct hns_roce_cq *send_cq, *recv_cq;
5426 unsigned long flags;
5427 int ret = 0;
5428
5429 if (modify_qp_is_ok(hr_qp)) {
5430 /* Modify qp to reset before destroying qp */
5431 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
5432 hr_qp->state, IB_QPS_RESET, udata);
5433 if (ret)
5434 ibdev_err_ratelimited(ibdev,
5435 "failed to modify QP to RST, ret = %d.\n",
5436 ret);
5437 }
5438
5439 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL;
5440 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL;
5441
5442 spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
5443 hns_roce_lock_cqs(send_cq, recv_cq);
5444
5445 if (!udata) {
5446 if (recv_cq)
5447 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn,
5448 (hr_qp->ibqp.srq ?
5449 to_hr_srq(hr_qp->ibqp.srq) :
5450 NULL));
5451
5452 if (send_cq && send_cq != recv_cq)
5453 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL);
5454 }
5455
5456 hns_roce_qp_remove(hr_dev, hr_qp);
5457
5458 hns_roce_unlock_cqs(send_cq, recv_cq);
5459 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
5460
5461 return ret;
5462 }
5463
hns_roce_v2_destroy_qp(struct ib_qp * ibqp,struct ib_udata * udata)5464 int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
5465 {
5466 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5467 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5468 int ret;
5469
5470 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata);
5471 if (ret)
5472 ibdev_err_ratelimited(&hr_dev->ib_dev,
5473 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n",
5474 hr_qp->qpn, ret);
5475
5476 hns_roce_qp_destroy(hr_dev, hr_qp, udata);
5477
5478 return 0;
5479 }
5480
hns_roce_v2_qp_flow_control_init(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp)5481 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev,
5482 struct hns_roce_qp *hr_qp)
5483 {
5484 struct ib_device *ibdev = &hr_dev->ib_dev;
5485 struct hns_roce_sccc_clr_done *resp;
5486 struct hns_roce_sccc_clr *clr;
5487 struct hns_roce_cmq_desc desc;
5488 int ret, i;
5489
5490 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
5491 return 0;
5492
5493 mutex_lock(&hr_dev->qp_table.scc_mutex);
5494
5495 /* set scc ctx clear done flag */
5496 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false);
5497 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5498 if (ret) {
5499 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret);
5500 goto out;
5501 }
5502
5503 /* clear scc context */
5504 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false);
5505 clr = (struct hns_roce_sccc_clr *)desc.data;
5506 clr->qpn = cpu_to_le32(hr_qp->qpn);
5507 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5508 if (ret) {
5509 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret);
5510 goto out;
5511 }
5512
5513 /* query scc context clear is done or not */
5514 resp = (struct hns_roce_sccc_clr_done *)desc.data;
5515 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) {
5516 hns_roce_cmq_setup_basic_desc(&desc,
5517 HNS_ROCE_OPC_QUERY_SCCC, true);
5518 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5519 if (ret) {
5520 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n",
5521 ret);
5522 goto out;
5523 }
5524
5525 if (resp->clr_done)
5526 goto out;
5527
5528 msleep(20);
5529 }
5530
5531 ibdev_err(ibdev, "query SCC clr done flag overtime.\n");
5532 ret = -ETIMEDOUT;
5533
5534 out:
5535 mutex_unlock(&hr_dev->qp_table.scc_mutex);
5536 return ret;
5537 }
5538
5539 #define DMA_IDX_SHIFT 3
5540 #define DMA_WQE_SHIFT 3
5541
hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq * srq,struct hns_roce_srq_context * ctx)5542 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq,
5543 struct hns_roce_srq_context *ctx)
5544 {
5545 struct hns_roce_idx_que *idx_que = &srq->idx_que;
5546 struct ib_device *ibdev = srq->ibsrq.device;
5547 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
5548 u64 mtts_idx[MTT_MIN_COUNT] = {};
5549 dma_addr_t dma_handle_idx;
5550 int ret;
5551
5552 /* Get physical address of idx que buf */
5553 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx,
5554 ARRAY_SIZE(mtts_idx));
5555 if (ret) {
5556 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n",
5557 ret);
5558 return ret;
5559 }
5560
5561 dma_handle_idx = hns_roce_get_mtr_ba(&idx_que->mtr);
5562
5563 hr_reg_write(ctx, SRQC_IDX_HOP_NUM,
5564 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt));
5565
5566 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT);
5567 hr_reg_write(ctx, SRQC_IDX_BT_BA_H,
5568 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT));
5569
5570 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ,
5571 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift));
5572 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ,
5573 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift));
5574
5575 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L,
5576 to_hr_hw_page_addr(mtts_idx[0]));
5577 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H,
5578 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0])));
5579
5580 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L,
5581 to_hr_hw_page_addr(mtts_idx[1]));
5582 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H,
5583 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1])));
5584
5585 return 0;
5586 }
5587
hns_roce_v2_write_srqc(struct hns_roce_srq * srq,void * mb_buf)5588 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf)
5589 {
5590 struct ib_device *ibdev = srq->ibsrq.device;
5591 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
5592 struct hns_roce_srq_context *ctx = mb_buf;
5593 u64 mtts_wqe[MTT_MIN_COUNT] = {};
5594 dma_addr_t dma_handle_wqe;
5595 int ret;
5596
5597 memset(ctx, 0, sizeof(*ctx));
5598
5599 /* Get the physical address of srq buf */
5600 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe,
5601 ARRAY_SIZE(mtts_wqe));
5602 if (ret) {
5603 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n",
5604 ret);
5605 return ret;
5606 }
5607
5608 dma_handle_wqe = hns_roce_get_mtr_ba(&srq->buf_mtr);
5609
5610 hr_reg_write(ctx, SRQC_SRQ_ST, 1);
5611 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE,
5612 srq->ibsrq.srq_type == IB_SRQT_XRC);
5613 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn);
5614 hr_reg_write(ctx, SRQC_SRQN, srq->srqn);
5615 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn);
5616 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn);
5617 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt));
5618 hr_reg_write(ctx, SRQC_RQWS,
5619 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1));
5620
5621 hr_reg_write(ctx, SRQC_WQE_HOP_NUM,
5622 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num,
5623 srq->wqe_cnt));
5624
5625 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT);
5626 hr_reg_write(ctx, SRQC_WQE_BT_BA_H,
5627 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT));
5628
5629 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ,
5630 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift));
5631 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ,
5632 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift));
5633
5634 return hns_roce_v2_write_srqc_index_queue(srq, ctx);
5635 }
5636
hns_roce_v2_modify_srq(struct ib_srq * ibsrq,struct ib_srq_attr * srq_attr,enum ib_srq_attr_mask srq_attr_mask,struct ib_udata * udata)5637 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq,
5638 struct ib_srq_attr *srq_attr,
5639 enum ib_srq_attr_mask srq_attr_mask,
5640 struct ib_udata *udata)
5641 {
5642 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5643 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5644 struct hns_roce_srq_context *srq_context;
5645 struct hns_roce_srq_context *srqc_mask;
5646 struct hns_roce_cmd_mailbox *mailbox;
5647 int ret;
5648
5649 /* Resizing SRQs is not supported yet */
5650 if (srq_attr_mask & IB_SRQ_MAX_WR)
5651 return -EOPNOTSUPP;
5652
5653 if (srq_attr_mask & IB_SRQ_LIMIT) {
5654 if (srq_attr->srq_limit > srq->wqe_cnt)
5655 return -EINVAL;
5656
5657 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5658 if (IS_ERR(mailbox))
5659 return PTR_ERR(mailbox);
5660
5661 srq_context = mailbox->buf;
5662 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1;
5663
5664 memset(srqc_mask, 0xff, sizeof(*srqc_mask));
5665
5666 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit);
5667 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL);
5668
5669 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
5670 HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn);
5671 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5672 if (ret) {
5673 ibdev_err(&hr_dev->ib_dev,
5674 "failed to handle cmd of modifying SRQ, ret = %d.\n",
5675 ret);
5676 return ret;
5677 }
5678 }
5679
5680 return 0;
5681 }
5682
hns_roce_v2_query_srq(struct ib_srq * ibsrq,struct ib_srq_attr * attr)5683 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr)
5684 {
5685 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5686 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5687 struct hns_roce_srq_context *srq_context;
5688 struct hns_roce_cmd_mailbox *mailbox;
5689 int ret;
5690
5691 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5692 if (IS_ERR(mailbox))
5693 return PTR_ERR(mailbox);
5694
5695 srq_context = mailbox->buf;
5696 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma,
5697 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn);
5698 if (ret) {
5699 ibdev_err(&hr_dev->ib_dev,
5700 "failed to process cmd of querying SRQ, ret = %d.\n",
5701 ret);
5702 goto out;
5703 }
5704
5705 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL);
5706 attr->max_wr = srq->wqe_cnt;
5707 attr->max_sge = srq->max_gs - srq->rsv_sge;
5708
5709 out:
5710 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5711 return ret;
5712 }
5713
hns_roce_v2_modify_cq(struct ib_cq * cq,u16 cq_count,u16 cq_period)5714 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
5715 {
5716 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device);
5717 struct hns_roce_v2_cq_context *cq_context;
5718 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
5719 struct hns_roce_v2_cq_context *cqc_mask;
5720 struct hns_roce_cmd_mailbox *mailbox;
5721 int ret;
5722
5723 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5724 if (IS_ERR(mailbox))
5725 return PTR_ERR(mailbox);
5726
5727 cq_context = mailbox->buf;
5728 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1;
5729
5730 memset(cqc_mask, 0xff, sizeof(*cqc_mask));
5731
5732 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count);
5733 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT);
5734
5735 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
5736 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) {
5737 dev_info(hr_dev->dev,
5738 "cq_period(%u) reached the upper limit, adjusted to 65.\n",
5739 cq_period);
5740 cq_period = HNS_ROCE_MAX_CQ_PERIOD;
5741 }
5742 cq_period *= HNS_ROCE_CLOCK_ADJUST;
5743 }
5744 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period);
5745 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD);
5746
5747 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
5748 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn);
5749 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5750 if (ret)
5751 ibdev_err_ratelimited(&hr_dev->ib_dev,
5752 "failed to process cmd when modifying CQ, ret = %d.\n",
5753 ret);
5754
5755 return ret;
5756 }
5757
hns_roce_v2_query_cqc(struct hns_roce_dev * hr_dev,u32 cqn,void * buffer)5758 static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn,
5759 void *buffer)
5760 {
5761 struct hns_roce_v2_cq_context *context;
5762 struct hns_roce_cmd_mailbox *mailbox;
5763 int ret;
5764
5765 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5766 if (IS_ERR(mailbox))
5767 return PTR_ERR(mailbox);
5768
5769 context = mailbox->buf;
5770 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma,
5771 HNS_ROCE_CMD_QUERY_CQC, cqn);
5772 if (ret) {
5773 ibdev_err_ratelimited(&hr_dev->ib_dev,
5774 "failed to process cmd when querying CQ, ret = %d.\n",
5775 ret);
5776 goto err_mailbox;
5777 }
5778
5779 memcpy(buffer, context, sizeof(*context));
5780
5781 err_mailbox:
5782 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5783
5784 return ret;
5785 }
5786
hns_roce_v2_query_mpt(struct hns_roce_dev * hr_dev,u32 key,void * buffer)5787 static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key,
5788 void *buffer)
5789 {
5790 struct hns_roce_v2_mpt_entry *context;
5791 struct hns_roce_cmd_mailbox *mailbox;
5792 int ret;
5793
5794 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5795 if (IS_ERR(mailbox))
5796 return PTR_ERR(mailbox);
5797
5798 context = mailbox->buf;
5799 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT,
5800 key_to_hw_index(key));
5801 if (ret) {
5802 ibdev_err(&hr_dev->ib_dev,
5803 "failed to process cmd when querying MPT, ret = %d.\n",
5804 ret);
5805 goto err_mailbox;
5806 }
5807
5808 memcpy(buffer, context, sizeof(*context));
5809
5810 err_mailbox:
5811 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5812
5813 return ret;
5814 }
5815
dump_aeqe_log(struct hns_roce_work * irq_work)5816 static void dump_aeqe_log(struct hns_roce_work *irq_work)
5817 {
5818 struct hns_roce_dev *hr_dev = irq_work->hr_dev;
5819 struct ib_device *ibdev = &hr_dev->ib_dev;
5820
5821 switch (irq_work->event_type) {
5822 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
5823 ibdev_info(ibdev, "path migrated succeeded.\n");
5824 break;
5825 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
5826 ibdev_warn(ibdev, "path migration failed.\n");
5827 break;
5828 case HNS_ROCE_EVENT_TYPE_COMM_EST:
5829 break;
5830 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
5831 ibdev_dbg(ibdev, "send queue drained.\n");
5832 break;
5833 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
5834 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n",
5835 irq_work->queue_num, irq_work->sub_type);
5836 break;
5837 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
5838 ibdev_err(ibdev, "invalid request local work queue 0x%x error.\n",
5839 irq_work->queue_num);
5840 break;
5841 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
5842 ibdev_err(ibdev, "local access violation work queue 0x%x error, sub_event type is: %d\n",
5843 irq_work->queue_num, irq_work->sub_type);
5844 break;
5845 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
5846 ibdev_dbg(ibdev, "SRQ limit reach.\n");
5847 break;
5848 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
5849 ibdev_dbg(ibdev, "SRQ last wqe reach.\n");
5850 break;
5851 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
5852 ibdev_err(ibdev, "SRQ catas error.\n");
5853 break;
5854 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
5855 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num);
5856 break;
5857 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
5858 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num);
5859 break;
5860 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
5861 ibdev_warn(ibdev, "DB overflow.\n");
5862 break;
5863 case HNS_ROCE_EVENT_TYPE_MB:
5864 break;
5865 case HNS_ROCE_EVENT_TYPE_FLR:
5866 ibdev_warn(ibdev, "function level reset.\n");
5867 break;
5868 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
5869 ibdev_err(ibdev, "xrc domain violation error.\n");
5870 break;
5871 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
5872 ibdev_err(ibdev, "invalid xrceth error.\n");
5873 break;
5874 default:
5875 ibdev_info(ibdev, "Undefined event %d.\n",
5876 irq_work->event_type);
5877 break;
5878 }
5879 }
5880
hns_roce_irq_work_handle(struct work_struct * work)5881 static void hns_roce_irq_work_handle(struct work_struct *work)
5882 {
5883 struct hns_roce_work *irq_work =
5884 container_of(work, struct hns_roce_work, work);
5885 struct hns_roce_dev *hr_dev = irq_work->hr_dev;
5886 int event_type = irq_work->event_type;
5887 u32 queue_num = irq_work->queue_num;
5888
5889 switch (event_type) {
5890 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
5891 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
5892 case HNS_ROCE_EVENT_TYPE_COMM_EST:
5893 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
5894 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
5895 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
5896 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
5897 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
5898 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
5899 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
5900 hns_roce_qp_event(hr_dev, queue_num, event_type);
5901 break;
5902 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
5903 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
5904 hns_roce_srq_event(hr_dev, queue_num, event_type);
5905 break;
5906 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
5907 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
5908 hns_roce_cq_event(hr_dev, queue_num, event_type);
5909 break;
5910 default:
5911 break;
5912 }
5913
5914 dump_aeqe_log(irq_work);
5915
5916 kfree(irq_work);
5917 }
5918
hns_roce_v2_init_irq_work(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq,u32 queue_num)5919 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev,
5920 struct hns_roce_eq *eq, u32 queue_num)
5921 {
5922 struct hns_roce_work *irq_work;
5923
5924 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC);
5925 if (!irq_work)
5926 return;
5927
5928 INIT_WORK(&irq_work->work, hns_roce_irq_work_handle);
5929 irq_work->hr_dev = hr_dev;
5930 irq_work->event_type = eq->event_type;
5931 irq_work->sub_type = eq->sub_type;
5932 irq_work->queue_num = queue_num;
5933 queue_work(hr_dev->irq_workq, &irq_work->work);
5934 }
5935
update_eq_db(struct hns_roce_eq * eq)5936 static void update_eq_db(struct hns_roce_eq *eq)
5937 {
5938 struct hns_roce_dev *hr_dev = eq->hr_dev;
5939 struct hns_roce_v2_db eq_db = {};
5940
5941 if (eq->type_flag == HNS_ROCE_AEQ) {
5942 hr_reg_write(&eq_db, EQ_DB_CMD,
5943 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
5944 HNS_ROCE_EQ_DB_CMD_AEQ :
5945 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED);
5946 } else {
5947 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn);
5948
5949 hr_reg_write(&eq_db, EQ_DB_CMD,
5950 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
5951 HNS_ROCE_EQ_DB_CMD_CEQ :
5952 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED);
5953 }
5954
5955 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index);
5956
5957 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg);
5958 }
5959
next_aeqe_sw_v2(struct hns_roce_eq * eq)5960 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
5961 {
5962 struct hns_roce_aeqe *aeqe;
5963
5964 aeqe = hns_roce_buf_offset(eq->mtr.kmem,
5965 (eq->cons_index & (eq->entries - 1)) *
5966 eq->eqe_size);
5967
5968 return (hr_reg_read(aeqe, AEQE_OWNER) ^
5969 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
5970 }
5971
hns_roce_v2_aeq_int(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)5972 static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,
5973 struct hns_roce_eq *eq)
5974 {
5975 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq);
5976 irqreturn_t aeqe_found = IRQ_NONE;
5977 int num_aeqes = 0;
5978 int event_type;
5979 u32 queue_num;
5980 int sub_type;
5981
5982 while (aeqe && num_aeqes < HNS_AEQ_POLLING_BUDGET) {
5983 /* Make sure we read AEQ entry after we have checked the
5984 * ownership bit
5985 */
5986 dma_rmb();
5987
5988 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE);
5989 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE);
5990 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM);
5991
5992 switch (event_type) {
5993 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
5994 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
5995 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
5996 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
5997 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
5998 hns_roce_flush_cqe(hr_dev, queue_num);
5999 break;
6000 case HNS_ROCE_EVENT_TYPE_MB:
6001 hns_roce_cmd_event(hr_dev,
6002 le16_to_cpu(aeqe->event.cmd.token),
6003 aeqe->event.cmd.status,
6004 le64_to_cpu(aeqe->event.cmd.out_param));
6005 break;
6006 default:
6007 break;
6008 }
6009
6010 eq->event_type = event_type;
6011 eq->sub_type = sub_type;
6012 ++eq->cons_index;
6013 aeqe_found = IRQ_HANDLED;
6014
6015 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num);
6016
6017 aeqe = next_aeqe_sw_v2(eq);
6018 ++num_aeqes;
6019 }
6020
6021 update_eq_db(eq);
6022
6023 return IRQ_RETVAL(aeqe_found);
6024 }
6025
next_ceqe_sw_v2(struct hns_roce_eq * eq)6026 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
6027 {
6028 struct hns_roce_ceqe *ceqe;
6029
6030 ceqe = hns_roce_buf_offset(eq->mtr.kmem,
6031 (eq->cons_index & (eq->entries - 1)) *
6032 eq->eqe_size);
6033
6034 return (hr_reg_read(ceqe, CEQE_OWNER) ^
6035 !!(eq->cons_index & eq->entries)) ? ceqe : NULL;
6036 }
6037
hns_roce_v2_ceq_int(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6038 static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,
6039 struct hns_roce_eq *eq)
6040 {
6041 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq);
6042 irqreturn_t ceqe_found = IRQ_NONE;
6043 u32 cqn;
6044
6045 while (ceqe) {
6046 /* Make sure we read CEQ entry after we have checked the
6047 * ownership bit
6048 */
6049 dma_rmb();
6050
6051 cqn = hr_reg_read(ceqe, CEQE_CQN);
6052
6053 hns_roce_cq_completion(hr_dev, cqn);
6054
6055 ++eq->cons_index;
6056 ceqe_found = IRQ_HANDLED;
6057
6058 ceqe = next_ceqe_sw_v2(eq);
6059 }
6060
6061 update_eq_db(eq);
6062
6063 return IRQ_RETVAL(ceqe_found);
6064 }
6065
hns_roce_v2_msix_interrupt_eq(int irq,void * eq_ptr)6066 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr)
6067 {
6068 struct hns_roce_eq *eq = eq_ptr;
6069 struct hns_roce_dev *hr_dev = eq->hr_dev;
6070 irqreturn_t int_work;
6071
6072 if (eq->type_flag == HNS_ROCE_CEQ)
6073 /* Completion event interrupt */
6074 int_work = hns_roce_v2_ceq_int(hr_dev, eq);
6075 else
6076 /* Asynchronous event interrupt */
6077 int_work = hns_roce_v2_aeq_int(hr_dev, eq);
6078
6079 return IRQ_RETVAL(int_work);
6080 }
6081
abnormal_interrupt_basic(struct hns_roce_dev * hr_dev,u32 int_st)6082 static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev,
6083 u32 int_st)
6084 {
6085 struct pci_dev *pdev = hr_dev->pci_dev;
6086 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
6087 const struct hnae3_ae_ops *ops = ae_dev->ops;
6088 enum hnae3_reset_type reset_type;
6089 irqreturn_t int_work = IRQ_NONE;
6090 u32 int_en;
6091
6092 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG);
6093
6094 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) {
6095 dev_err(hr_dev->dev, "AEQ overflow!\n");
6096
6097 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG,
6098 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S);
6099
6100 reset_type = hr_dev->is_vf ?
6101 HNAE3_VF_FUNC_RESET : HNAE3_FUNC_RESET;
6102
6103 /* Set reset level for reset_event() */
6104 if (ops->set_default_reset_request)
6105 ops->set_default_reset_request(ae_dev, reset_type);
6106 if (ops->reset_event)
6107 ops->reset_event(pdev, NULL);
6108
6109 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
6110 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
6111
6112 int_work = IRQ_HANDLED;
6113 } else {
6114 dev_err(hr_dev->dev, "there is no basic abn irq found.\n");
6115 }
6116
6117 return IRQ_RETVAL(int_work);
6118 }
6119
fmea_ram_ecc_query(struct hns_roce_dev * hr_dev,struct fmea_ram_ecc * ecc_info)6120 static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev,
6121 struct fmea_ram_ecc *ecc_info)
6122 {
6123 struct hns_roce_cmq_desc desc;
6124 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
6125 int ret;
6126
6127 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_QUERY_RAM_ECC, true);
6128 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
6129 if (ret)
6130 return ret;
6131
6132 ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR);
6133 ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE);
6134 ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG);
6135
6136 return 0;
6137 }
6138
fmea_recover_gmv(struct hns_roce_dev * hr_dev,u32 idx)6139 static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx)
6140 {
6141 struct hns_roce_cmq_desc desc;
6142 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
6143 u32 addr_upper;
6144 u32 addr_low;
6145 int ret;
6146
6147 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, true);
6148 hr_reg_write(req, CFG_GMV_BT_IDX, idx);
6149
6150 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
6151 if (ret) {
6152 dev_err(hr_dev->dev,
6153 "failed to execute cmd to read gmv, ret = %d.\n", ret);
6154 return ret;
6155 }
6156
6157 addr_low = hr_reg_read(req, CFG_GMV_BT_BA_L);
6158 addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H);
6159
6160 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false);
6161 hr_reg_write(req, CFG_GMV_BT_BA_L, addr_low);
6162 hr_reg_write(req, CFG_GMV_BT_BA_H, addr_upper);
6163 hr_reg_write(req, CFG_GMV_BT_IDX, idx);
6164
6165 return hns_roce_cmq_send(hr_dev, &desc, 1);
6166 }
6167
fmea_get_ram_res_addr(u32 res_type,__le64 * data)6168 static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data)
6169 {
6170 if (res_type == ECC_RESOURCE_QPC_TIMER ||
6171 res_type == ECC_RESOURCE_CQC_TIMER ||
6172 res_type == ECC_RESOURCE_SCCC)
6173 return le64_to_cpu(*data);
6174
6175 return le64_to_cpu(*data) << HNS_HW_PAGE_SHIFT;
6176 }
6177
fmea_recover_others(struct hns_roce_dev * hr_dev,u32 res_type,u32 index)6178 static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type,
6179 u32 index)
6180 {
6181 u8 write_bt0_op = fmea_ram_res[res_type].write_bt0_op;
6182 u8 read_bt0_op = fmea_ram_res[res_type].read_bt0_op;
6183 struct hns_roce_cmd_mailbox *mailbox;
6184 u64 addr;
6185 int ret;
6186
6187 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
6188 if (IS_ERR(mailbox))
6189 return PTR_ERR(mailbox);
6190
6191 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, read_bt0_op, index);
6192 if (ret) {
6193 dev_err(hr_dev->dev,
6194 "failed to execute cmd to read fmea ram, ret = %d.\n",
6195 ret);
6196 goto out;
6197 }
6198
6199 addr = fmea_get_ram_res_addr(res_type, mailbox->buf);
6200
6201 ret = hns_roce_cmd_mbox(hr_dev, addr, 0, write_bt0_op, index);
6202 if (ret)
6203 dev_err(hr_dev->dev,
6204 "failed to execute cmd to write fmea ram, ret = %d.\n",
6205 ret);
6206
6207 out:
6208 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6209 return ret;
6210 }
6211
fmea_ram_ecc_recover(struct hns_roce_dev * hr_dev,struct fmea_ram_ecc * ecc_info)6212 static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev,
6213 struct fmea_ram_ecc *ecc_info)
6214 {
6215 u32 res_type = ecc_info->res_type;
6216 u32 index = ecc_info->index;
6217 int ret;
6218
6219 BUILD_BUG_ON(ARRAY_SIZE(fmea_ram_res) != ECC_RESOURCE_COUNT);
6220
6221 if (res_type >= ECC_RESOURCE_COUNT) {
6222 dev_err(hr_dev->dev, "unsupported fmea ram ecc type %u.\n",
6223 res_type);
6224 return;
6225 }
6226
6227 if (res_type == ECC_RESOURCE_GMV)
6228 ret = fmea_recover_gmv(hr_dev, index);
6229 else
6230 ret = fmea_recover_others(hr_dev, res_type, index);
6231 if (ret)
6232 dev_err(hr_dev->dev,
6233 "failed to recover %s, index = %u, ret = %d.\n",
6234 fmea_ram_res[res_type].name, index, ret);
6235 }
6236
fmea_ram_ecc_work(struct work_struct * ecc_work)6237 static void fmea_ram_ecc_work(struct work_struct *ecc_work)
6238 {
6239 struct hns_roce_dev *hr_dev =
6240 container_of(ecc_work, struct hns_roce_dev, ecc_work);
6241 struct fmea_ram_ecc ecc_info = {};
6242
6243 if (fmea_ram_ecc_query(hr_dev, &ecc_info)) {
6244 dev_err(hr_dev->dev, "failed to query fmea ram ecc.\n");
6245 return;
6246 }
6247
6248 if (!ecc_info.is_ecc_err) {
6249 dev_err(hr_dev->dev, "there is no fmea ram ecc err found.\n");
6250 return;
6251 }
6252
6253 fmea_ram_ecc_recover(hr_dev, &ecc_info);
6254 }
6255
hns_roce_v2_msix_interrupt_abn(int irq,void * dev_id)6256 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
6257 {
6258 struct hns_roce_dev *hr_dev = dev_id;
6259 irqreturn_t int_work = IRQ_NONE;
6260 u32 int_st;
6261
6262 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG);
6263
6264 if (int_st) {
6265 int_work = abnormal_interrupt_basic(hr_dev, int_st);
6266 } else if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
6267 queue_work(hr_dev->irq_workq, &hr_dev->ecc_work);
6268 int_work = IRQ_HANDLED;
6269 } else {
6270 dev_err(hr_dev->dev, "there is no abnormal irq found.\n");
6271 }
6272
6273 return IRQ_RETVAL(int_work);
6274 }
6275
hns_roce_v2_int_mask_enable(struct hns_roce_dev * hr_dev,int eq_num,u32 enable_flag)6276 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,
6277 int eq_num, u32 enable_flag)
6278 {
6279 int i;
6280
6281 for (i = 0; i < eq_num; i++)
6282 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
6283 i * EQ_REG_OFFSET, enable_flag);
6284
6285 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag);
6286 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag);
6287 }
6288
free_eq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6289 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6290 {
6291 hns_roce_mtr_destroy(hr_dev, &eq->mtr);
6292 }
6293
hns_roce_v2_destroy_eqc(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6294 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev,
6295 struct hns_roce_eq *eq)
6296 {
6297 struct device *dev = hr_dev->dev;
6298 int eqn = eq->eqn;
6299 int ret;
6300 u8 cmd;
6301
6302 if (eqn < hr_dev->caps.num_comp_vectors)
6303 cmd = HNS_ROCE_CMD_DESTROY_CEQC;
6304 else
6305 cmd = HNS_ROCE_CMD_DESTROY_AEQC;
6306
6307 ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M);
6308 if (ret)
6309 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn);
6310
6311 free_eq_buf(hr_dev, eq);
6312 }
6313
init_eq_config(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6314 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6315 {
6316 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
6317 eq->cons_index = 0;
6318 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
6319 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
6320 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
6321 eq->shift = ilog2((unsigned int)eq->entries);
6322 }
6323
config_eqc(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq,void * mb_buf)6324 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq,
6325 void *mb_buf)
6326 {
6327 u64 eqe_ba[MTT_MIN_COUNT] = { 0 };
6328 struct hns_roce_eq_context *eqc;
6329 u64 bt_ba = 0;
6330 int ret;
6331
6332 eqc = mb_buf;
6333 memset(eqc, 0, sizeof(struct hns_roce_eq_context));
6334
6335 init_eq_config(hr_dev, eq);
6336
6337 /* if not multi-hop, eqe buffer only use one trunk */
6338 ret = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba,
6339 ARRAY_SIZE(eqe_ba));
6340 if (ret) {
6341 dev_err(hr_dev->dev, "failed to find EQE mtr, ret = %d\n", ret);
6342 return ret;
6343 }
6344
6345 bt_ba = hns_roce_get_mtr_ba(&eq->mtr);
6346
6347 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID);
6348 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num);
6349 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore);
6350 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce);
6351 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st);
6352 hr_reg_write(eqc, EQC_EQN, eq->eqn);
6353 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT);
6354 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ,
6355 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift));
6356 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ,
6357 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift));
6358 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX);
6359 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt);
6360
6361 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
6362 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) {
6363 dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n",
6364 eq->eq_period);
6365 eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD;
6366 }
6367 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST;
6368 }
6369
6370 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period);
6371 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER);
6372 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3);
6373 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35);
6374 hr_reg_write(eqc, EQC_SHIFT, eq->shift);
6375 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX);
6376 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12);
6377 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28);
6378 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60);
6379 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX);
6380 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12);
6381 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44);
6382 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE);
6383
6384 return 0;
6385 }
6386
alloc_eq_buf(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)6387 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6388 {
6389 struct hns_roce_buf_attr buf_attr = {};
6390 int err;
6391
6392 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0)
6393 eq->hop_num = 0;
6394 else
6395 eq->hop_num = hr_dev->caps.eqe_hop_num;
6396
6397 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT;
6398 buf_attr.region[0].size = eq->entries * eq->eqe_size;
6399 buf_attr.region[0].hopnum = eq->hop_num;
6400 buf_attr.region_count = 1;
6401
6402 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr,
6403 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL,
6404 0);
6405 if (err)
6406 dev_err(hr_dev->dev, "failed to alloc EQE mtr, err %d\n", err);
6407
6408 return err;
6409 }
6410
hns_roce_v2_create_eq(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq,u8 eq_cmd)6411 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev,
6412 struct hns_roce_eq *eq, u8 eq_cmd)
6413 {
6414 struct hns_roce_cmd_mailbox *mailbox;
6415 int ret;
6416
6417 /* Allocate mailbox memory */
6418 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
6419 if (IS_ERR(mailbox))
6420 return PTR_ERR(mailbox);
6421
6422 ret = alloc_eq_buf(hr_dev, eq);
6423 if (ret)
6424 goto free_cmd_mbox;
6425
6426 ret = config_eqc(hr_dev, eq, mailbox->buf);
6427 if (ret)
6428 goto err_cmd_mbox;
6429
6430 ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn);
6431 if (ret) {
6432 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n");
6433 goto err_cmd_mbox;
6434 }
6435
6436 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6437
6438 return 0;
6439
6440 err_cmd_mbox:
6441 free_eq_buf(hr_dev, eq);
6442
6443 free_cmd_mbox:
6444 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6445
6446 return ret;
6447 }
6448
__hns_roce_request_irq(struct hns_roce_dev * hr_dev,int irq_num,int comp_num,int aeq_num,int other_num)6449 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num,
6450 int comp_num, int aeq_num, int other_num)
6451 {
6452 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6453 int i, j;
6454 int ret;
6455
6456 for (i = 0; i < irq_num; i++) {
6457 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN,
6458 GFP_KERNEL);
6459 if (!hr_dev->irq_names[i]) {
6460 ret = -ENOMEM;
6461 goto err_kzalloc_failed;
6462 }
6463 }
6464
6465 /* irq contains: abnormal + AEQ + CEQ */
6466 for (j = 0; j < other_num; j++)
6467 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6468 "hns-abn-%d", j);
6469
6470 for (j = other_num; j < (other_num + aeq_num); j++)
6471 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6472 "hns-aeq-%d", j - other_num);
6473
6474 for (j = (other_num + aeq_num); j < irq_num; j++)
6475 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6476 "hns-ceq-%d", j - other_num - aeq_num);
6477
6478 for (j = 0; j < irq_num; j++) {
6479 if (j < other_num)
6480 ret = request_irq(hr_dev->irq[j],
6481 hns_roce_v2_msix_interrupt_abn,
6482 0, hr_dev->irq_names[j], hr_dev);
6483
6484 else if (j < (other_num + comp_num))
6485 ret = request_irq(eq_table->eq[j - other_num].irq,
6486 hns_roce_v2_msix_interrupt_eq,
6487 0, hr_dev->irq_names[j + aeq_num],
6488 &eq_table->eq[j - other_num]);
6489 else
6490 ret = request_irq(eq_table->eq[j - other_num].irq,
6491 hns_roce_v2_msix_interrupt_eq,
6492 0, hr_dev->irq_names[j - comp_num],
6493 &eq_table->eq[j - other_num]);
6494 if (ret) {
6495 dev_err(hr_dev->dev, "request irq error!\n");
6496 goto err_request_failed;
6497 }
6498 }
6499
6500 return 0;
6501
6502 err_request_failed:
6503 for (j -= 1; j >= 0; j--)
6504 if (j < other_num)
6505 free_irq(hr_dev->irq[j], hr_dev);
6506 else
6507 free_irq(eq_table->eq[j - other_num].irq,
6508 &eq_table->eq[j - other_num]);
6509
6510 err_kzalloc_failed:
6511 for (i -= 1; i >= 0; i--)
6512 kfree(hr_dev->irq_names[i]);
6513
6514 return ret;
6515 }
6516
__hns_roce_free_irq(struct hns_roce_dev * hr_dev)6517 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev)
6518 {
6519 int irq_num;
6520 int eq_num;
6521 int i;
6522
6523 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
6524 irq_num = eq_num + hr_dev->caps.num_other_vectors;
6525
6526 for (i = 0; i < hr_dev->caps.num_other_vectors; i++)
6527 free_irq(hr_dev->irq[i], hr_dev);
6528
6529 for (i = 0; i < eq_num; i++)
6530 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]);
6531
6532 for (i = 0; i < irq_num; i++)
6533 kfree(hr_dev->irq_names[i]);
6534 }
6535
hns_roce_v2_init_eq_table(struct hns_roce_dev * hr_dev)6536 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
6537 {
6538 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6539 struct device *dev = hr_dev->dev;
6540 struct hns_roce_eq *eq;
6541 int other_num;
6542 int comp_num;
6543 int aeq_num;
6544 int irq_num;
6545 int eq_num;
6546 u8 eq_cmd;
6547 int ret;
6548 int i;
6549
6550 if (hr_dev->caps.aeqe_depth < HNS_AEQ_POLLING_BUDGET)
6551 return -EINVAL;
6552
6553 other_num = hr_dev->caps.num_other_vectors;
6554 comp_num = hr_dev->caps.num_comp_vectors;
6555 aeq_num = hr_dev->caps.num_aeq_vectors;
6556
6557 eq_num = comp_num + aeq_num;
6558 irq_num = eq_num + other_num;
6559
6560 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
6561 if (!eq_table->eq)
6562 return -ENOMEM;
6563
6564 /* create eq */
6565 for (i = 0; i < eq_num; i++) {
6566 eq = &eq_table->eq[i];
6567 eq->hr_dev = hr_dev;
6568 eq->eqn = i;
6569 if (i < comp_num) {
6570 /* CEQ */
6571 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
6572 eq->type_flag = HNS_ROCE_CEQ;
6573 eq->entries = hr_dev->caps.ceqe_depth;
6574 eq->eqe_size = hr_dev->caps.ceqe_size;
6575 eq->irq = hr_dev->irq[i + other_num + aeq_num];
6576 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
6577 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
6578 } else {
6579 /* AEQ */
6580 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
6581 eq->type_flag = HNS_ROCE_AEQ;
6582 eq->entries = hr_dev->caps.aeqe_depth;
6583 eq->eqe_size = hr_dev->caps.aeqe_size;
6584 eq->irq = hr_dev->irq[i - comp_num + other_num];
6585 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
6586 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
6587 }
6588
6589 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd);
6590 if (ret) {
6591 dev_err(dev, "failed to create eq.\n");
6592 goto err_create_eq_fail;
6593 }
6594 }
6595
6596 INIT_WORK(&hr_dev->ecc_work, fmea_ram_ecc_work);
6597
6598 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0);
6599 if (!hr_dev->irq_workq) {
6600 dev_err(dev, "failed to create irq workqueue.\n");
6601 ret = -ENOMEM;
6602 goto err_create_eq_fail;
6603 }
6604
6605 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num,
6606 other_num);
6607 if (ret) {
6608 dev_err(dev, "failed to request irq.\n");
6609 goto err_request_irq_fail;
6610 }
6611
6612 /* enable irq */
6613 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE);
6614
6615 return 0;
6616
6617 err_request_irq_fail:
6618 destroy_workqueue(hr_dev->irq_workq);
6619
6620 err_create_eq_fail:
6621 for (i -= 1; i >= 0; i--)
6622 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]);
6623 kfree(eq_table->eq);
6624
6625 return ret;
6626 }
6627
hns_roce_v2_cleanup_eq_table(struct hns_roce_dev * hr_dev)6628 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev)
6629 {
6630 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6631 int eq_num;
6632 int i;
6633
6634 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
6635
6636 /* Disable irq */
6637 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
6638
6639 __hns_roce_free_irq(hr_dev);
6640 destroy_workqueue(hr_dev->irq_workq);
6641
6642 for (i = 0; i < eq_num; i++)
6643 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]);
6644
6645 kfree(eq_table->eq);
6646 }
6647
6648 static const struct ib_device_ops hns_roce_v2_dev_ops = {
6649 .destroy_qp = hns_roce_v2_destroy_qp,
6650 .modify_cq = hns_roce_v2_modify_cq,
6651 .poll_cq = hns_roce_v2_poll_cq,
6652 .post_recv = hns_roce_v2_post_recv,
6653 .post_send = hns_roce_v2_post_send,
6654 .query_qp = hns_roce_v2_query_qp,
6655 .req_notify_cq = hns_roce_v2_req_notify_cq,
6656 };
6657
6658 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = {
6659 .modify_srq = hns_roce_v2_modify_srq,
6660 .post_srq_recv = hns_roce_v2_post_srq_recv,
6661 .query_srq = hns_roce_v2_query_srq,
6662 };
6663
6664 static const struct hns_roce_hw hns_roce_hw_v2 = {
6665 .cmq_init = hns_roce_v2_cmq_init,
6666 .cmq_exit = hns_roce_v2_cmq_exit,
6667 .hw_profile = hns_roce_v2_profile,
6668 .hw_init = hns_roce_v2_init,
6669 .hw_exit = hns_roce_v2_exit,
6670 .post_mbox = v2_post_mbox,
6671 .poll_mbox_done = v2_poll_mbox_done,
6672 .chk_mbox_avail = v2_chk_mbox_is_avail,
6673 .set_gid = hns_roce_v2_set_gid,
6674 .set_mac = hns_roce_v2_set_mac,
6675 .write_mtpt = hns_roce_v2_write_mtpt,
6676 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
6677 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt,
6678 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt,
6679 .write_cqc = hns_roce_v2_write_cqc,
6680 .set_hem = hns_roce_v2_set_hem,
6681 .clear_hem = hns_roce_v2_clear_hem,
6682 .modify_qp = hns_roce_v2_modify_qp,
6683 .dereg_mr = hns_roce_v2_dereg_mr,
6684 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init,
6685 .init_eq = hns_roce_v2_init_eq_table,
6686 .cleanup_eq = hns_roce_v2_cleanup_eq_table,
6687 .write_srqc = hns_roce_v2_write_srqc,
6688 .query_cqc = hns_roce_v2_query_cqc,
6689 .query_qpc = hns_roce_v2_query_qpc,
6690 .query_mpt = hns_roce_v2_query_mpt,
6691 .query_hw_counter = hns_roce_hw_v2_query_counter,
6692 .hns_roce_dev_ops = &hns_roce_v2_dev_ops,
6693 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops,
6694 };
6695
6696 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
6697 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
6698 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
6699 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
6700 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
6701 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
6702 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0},
6703 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
6704 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
6705 /* required last entry */
6706 {0, }
6707 };
6708
6709 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl);
6710
hns_roce_hw_v2_get_cfg(struct hns_roce_dev * hr_dev,struct hnae3_handle * handle)6711 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
6712 struct hnae3_handle *handle)
6713 {
6714 struct hns_roce_v2_priv *priv = hr_dev->priv;
6715 const struct pci_device_id *id;
6716 int i;
6717
6718 hr_dev->pci_dev = handle->pdev;
6719 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev);
6720 hr_dev->is_vf = id->driver_data;
6721 hr_dev->dev = &handle->pdev->dev;
6722 hr_dev->hw = &hns_roce_hw_v2;
6723 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
6724 hr_dev->odb_offset = hr_dev->sdb_offset;
6725
6726 /* Get info from NIC driver. */
6727 hr_dev->reg_base = handle->rinfo.roce_io_base;
6728 hr_dev->mem_base = handle->rinfo.roce_mem_base;
6729 hr_dev->caps.num_ports = 1;
6730 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
6731 hr_dev->iboe.phy_port[0] = 0;
6732
6733 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid,
6734 hr_dev->iboe.netdevs[0]->dev_addr);
6735
6736 for (i = 0; i < handle->rinfo.num_vectors; i++)
6737 hr_dev->irq[i] = pci_irq_vector(handle->pdev,
6738 i + handle->rinfo.base_vector);
6739
6740 /* cmd issue mode: 0 is poll, 1 is event */
6741 hr_dev->cmd_mod = 1;
6742 hr_dev->loop_idc = 0;
6743
6744 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle);
6745 priv->handle = handle;
6746 }
6747
__hns_roce_hw_v2_init_instance(struct hnae3_handle * handle)6748 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
6749 {
6750 struct hns_roce_dev *hr_dev;
6751 int ret;
6752
6753 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
6754 if (!hr_dev)
6755 return -ENOMEM;
6756
6757 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL);
6758 if (!hr_dev->priv) {
6759 ret = -ENOMEM;
6760 goto error_failed_kzalloc;
6761 }
6762
6763 hns_roce_hw_v2_get_cfg(hr_dev, handle);
6764
6765 ret = hns_roce_init(hr_dev);
6766 if (ret) {
6767 dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
6768 goto error_failed_roce_init;
6769 }
6770
6771 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
6772 ret = free_mr_init(hr_dev);
6773 if (ret) {
6774 dev_err(hr_dev->dev, "failed to init free mr!\n");
6775 goto error_failed_free_mr_init;
6776 }
6777 }
6778
6779 handle->priv = hr_dev;
6780
6781 return 0;
6782
6783 error_failed_free_mr_init:
6784 hns_roce_exit(hr_dev);
6785
6786 error_failed_roce_init:
6787 kfree(hr_dev->priv);
6788
6789 error_failed_kzalloc:
6790 ib_dealloc_device(&hr_dev->ib_dev);
6791
6792 return ret;
6793 }
6794
__hns_roce_hw_v2_uninit_instance(struct hnae3_handle * handle,bool reset)6795 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
6796 bool reset)
6797 {
6798 struct hns_roce_dev *hr_dev = handle->priv;
6799
6800 if (!hr_dev)
6801 return;
6802
6803 handle->priv = NULL;
6804
6805 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT;
6806 hns_roce_handle_device_err(hr_dev);
6807
6808 hns_roce_exit(hr_dev);
6809 kfree(hr_dev->priv);
6810 ib_dealloc_device(&hr_dev->ib_dev);
6811 }
6812
hns_roce_hw_v2_init_instance(struct hnae3_handle * handle)6813 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
6814 {
6815 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
6816 const struct pci_device_id *id;
6817 struct device *dev = &handle->pdev->dev;
6818 int ret;
6819
6820 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT;
6821
6822 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) {
6823 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6824 goto reset_chk_err;
6825 }
6826
6827 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev);
6828 if (!id)
6829 return 0;
6830
6831 if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08)
6832 return 0;
6833
6834 ret = __hns_roce_hw_v2_init_instance(handle);
6835 if (ret) {
6836 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6837 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret);
6838 if (ops->ae_dev_resetting(handle) ||
6839 ops->get_hw_reset_stat(handle))
6840 goto reset_chk_err;
6841 else
6842 return ret;
6843 }
6844
6845 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED;
6846
6847 return 0;
6848
6849 reset_chk_err:
6850 dev_err(dev, "Device is busy in resetting state.\n"
6851 "please retry later.\n");
6852
6853 return -EBUSY;
6854 }
6855
hns_roce_hw_v2_uninit_instance(struct hnae3_handle * handle,bool reset)6856 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
6857 bool reset)
6858 {
6859 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED)
6860 return;
6861
6862 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT;
6863
6864 __hns_roce_hw_v2_uninit_instance(handle, reset);
6865
6866 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6867 }
hns_roce_hw_v2_reset_notify_down(struct hnae3_handle * handle)6868 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle)
6869 {
6870 struct hns_roce_dev *hr_dev;
6871
6872 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) {
6873 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6874 return 0;
6875 }
6876
6877 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN;
6878 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6879
6880 hr_dev = handle->priv;
6881 if (!hr_dev)
6882 return 0;
6883
6884 hr_dev->active = false;
6885 hr_dev->dis_db = true;
6886 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN;
6887
6888 return 0;
6889 }
6890
hns_roce_hw_v2_reset_notify_init(struct hnae3_handle * handle)6891 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle)
6892 {
6893 struct device *dev = &handle->pdev->dev;
6894 int ret;
6895
6896 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN,
6897 &handle->rinfo.state)) {
6898 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6899 return 0;
6900 }
6901
6902 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT;
6903
6904 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n");
6905 ret = __hns_roce_hw_v2_init_instance(handle);
6906 if (ret) {
6907 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify
6908 * callback function, RoCE Engine reinitialize. If RoCE reinit
6909 * failed, we should inform NIC driver.
6910 */
6911 handle->priv = NULL;
6912 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret);
6913 } else {
6914 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6915 dev_info(dev, "reset done, RoCE client reinit finished.\n");
6916 }
6917
6918 return ret;
6919 }
6920
hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle * handle)6921 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle)
6922 {
6923 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state))
6924 return 0;
6925
6926 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT;
6927 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n");
6928 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY);
6929 __hns_roce_hw_v2_uninit_instance(handle, false);
6930
6931 return 0;
6932 }
6933
hns_roce_hw_v2_reset_notify(struct hnae3_handle * handle,enum hnae3_reset_notify_type type)6934 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle,
6935 enum hnae3_reset_notify_type type)
6936 {
6937 int ret = 0;
6938
6939 switch (type) {
6940 case HNAE3_DOWN_CLIENT:
6941 ret = hns_roce_hw_v2_reset_notify_down(handle);
6942 break;
6943 case HNAE3_INIT_CLIENT:
6944 ret = hns_roce_hw_v2_reset_notify_init(handle);
6945 break;
6946 case HNAE3_UNINIT_CLIENT:
6947 ret = hns_roce_hw_v2_reset_notify_uninit(handle);
6948 break;
6949 default:
6950 break;
6951 }
6952
6953 return ret;
6954 }
6955
6956 static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
6957 .init_instance = hns_roce_hw_v2_init_instance,
6958 .uninit_instance = hns_roce_hw_v2_uninit_instance,
6959 .reset_notify = hns_roce_hw_v2_reset_notify,
6960 };
6961
6962 static struct hnae3_client hns_roce_hw_v2_client = {
6963 .name = "hns_roce_hw_v2",
6964 .type = HNAE3_CLIENT_ROCE,
6965 .ops = &hns_roce_hw_v2_ops,
6966 };
6967
hns_roce_hw_v2_init(void)6968 static int __init hns_roce_hw_v2_init(void)
6969 {
6970 return hnae3_register_client(&hns_roce_hw_v2_client);
6971 }
6972
hns_roce_hw_v2_exit(void)6973 static void __exit hns_roce_hw_v2_exit(void)
6974 {
6975 hnae3_unregister_client(&hns_roce_hw_v2_client);
6976 }
6977
6978 module_init(hns_roce_hw_v2_init);
6979 module_exit(hns_roce_hw_v2_exit);
6980
6981 MODULE_LICENSE("Dual BSD/GPL");
6982 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
6983 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
6984 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
6985 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");
6986