xref: /openbmc/qemu/tests/tcg/riscv64/issue1060.S (revision e8e86b484eac70cd86e15fa10a2f0038a536cbba)
1	.option	norvc
2
3	.text
4	.global _start
5_start:
6	lla	t0, trap
7	csrw	mtvec, t0
8
9	# These are all illegal instructions
10	csrw	time, x0
11	.insn	i CUSTOM_0, 0, x0, x0, 0x321
12	csrw	time, x0
13	.insn	i CUSTOM_0, 0, x0, x0, 0x123
14	csrw	cycle, x0
15
16	# Success!
17	li	a0, 0
18	j	_exit
19
20trap:
21	# When an instruction traps, compare it to the insn in memory.
22	csrr	t0, mepc
23	csrr	t1, mtval
24	lwu	t2, 0(t0)
25	bne	t1, t2, fail
26
27	# Skip the insn and continue.
28	addi	t0, t0, 4
29	csrw	mepc, t0
30	mret
31
32fail:
33	li	a0, 1
34
35# Exit code in a0
36_exit:
37	lla	a1, semiargs
38	li	t0, 0x20026	# ADP_Stopped_ApplicationExit
39	sd	t0, 0(a1)
40	sd	a0, 8(a1)
41	li	a0, 0x20	# TARGET_SYS_EXIT_EXTENDED
42
43	# Semihosting call sequence
44	.balign	16
45	slli	zero, zero, 0x1f
46	ebreak
47	srai	zero, zero, 0x7
48	j	.
49
50	.data
51	.balign	16
52semiargs:
53	.space	16
54