1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
4 *
5 * Copyright (C) 2012, Samsung Electronics Co., Ltd.
6 */
7
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/clk.h>
11 #include <linux/mmc/host.h>
12 #include <linux/mmc/mmc.h>
13 #include <linux/of.h>
14 #include <linux/of_gpio.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/slab.h>
17
18 #include "dw_mmc.h"
19 #include "dw_mmc-pltfm.h"
20 #include "dw_mmc-exynos.h"
21
22 /* Variations in Exynos specific dw-mshc controller */
23 enum dw_mci_exynos_type {
24 DW_MCI_TYPE_EXYNOS4210,
25 DW_MCI_TYPE_EXYNOS4412,
26 DW_MCI_TYPE_EXYNOS5250,
27 DW_MCI_TYPE_EXYNOS5420,
28 DW_MCI_TYPE_EXYNOS5420_SMU,
29 DW_MCI_TYPE_EXYNOS7,
30 DW_MCI_TYPE_EXYNOS7_SMU,
31 DW_MCI_TYPE_EXYNOS7870,
32 DW_MCI_TYPE_EXYNOS7870_SMU,
33 DW_MCI_TYPE_ARTPEC8,
34 };
35
36 /* Exynos implementation specific driver private data */
37 struct dw_mci_exynos_priv_data {
38 enum dw_mci_exynos_type ctrl_type;
39 u8 ciu_div;
40 u32 sdr_timing;
41 u32 ddr_timing;
42 u32 hs400_timing;
43 u32 tuned_sample;
44 u32 cur_speed;
45 u32 dqs_delay;
46 u32 saved_dqs_en;
47 u32 saved_strobe_ctrl;
48 };
49
50 static struct dw_mci_exynos_compatible {
51 char *compatible;
52 enum dw_mci_exynos_type ctrl_type;
53 } exynos_compat[] = {
54 {
55 .compatible = "samsung,exynos4210-dw-mshc",
56 .ctrl_type = DW_MCI_TYPE_EXYNOS4210,
57 }, {
58 .compatible = "samsung,exynos4412-dw-mshc",
59 .ctrl_type = DW_MCI_TYPE_EXYNOS4412,
60 }, {
61 .compatible = "samsung,exynos5250-dw-mshc",
62 .ctrl_type = DW_MCI_TYPE_EXYNOS5250,
63 }, {
64 .compatible = "samsung,exynos5420-dw-mshc",
65 .ctrl_type = DW_MCI_TYPE_EXYNOS5420,
66 }, {
67 .compatible = "samsung,exynos5420-dw-mshc-smu",
68 .ctrl_type = DW_MCI_TYPE_EXYNOS5420_SMU,
69 }, {
70 .compatible = "samsung,exynos7-dw-mshc",
71 .ctrl_type = DW_MCI_TYPE_EXYNOS7,
72 }, {
73 .compatible = "samsung,exynos7-dw-mshc-smu",
74 .ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU,
75 }, {
76 .compatible = "samsung,exynos7870-dw-mshc",
77 .ctrl_type = DW_MCI_TYPE_EXYNOS7870,
78 }, {
79 .compatible = "samsung,exynos7870-dw-mshc-smu",
80 .ctrl_type = DW_MCI_TYPE_EXYNOS7870_SMU,
81 }, {
82 .compatible = "axis,artpec8-dw-mshc",
83 .ctrl_type = DW_MCI_TYPE_ARTPEC8,
84 },
85 };
86
dw_mci_exynos_get_ciu_div(struct dw_mci * host)87 static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host)
88 {
89 struct dw_mci_exynos_priv_data *priv = host->priv;
90
91 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
92 return EXYNOS4412_FIXED_CIU_CLK_DIV;
93 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
94 return EXYNOS4210_FIXED_CIU_CLK_DIV;
95 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
96 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
97 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
98 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
99 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
100 return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1;
101 else
102 return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1;
103 }
104
dw_mci_exynos_config_smu(struct dw_mci * host)105 static void dw_mci_exynos_config_smu(struct dw_mci *host)
106 {
107 struct dw_mci_exynos_priv_data *priv = host->priv;
108
109 /*
110 * If Exynos is provided the Security management,
111 * set for non-ecryption mode at this time.
112 */
113 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU ||
114 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
115 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU) {
116 mci_writel(host, MPSBEGIN0, 0);
117 mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX);
118 mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT |
119 SDMMC_MPSCTRL_NON_SECURE_READ_BIT |
120 SDMMC_MPSCTRL_VALID |
121 SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT);
122 }
123 }
124
dw_mci_exynos_priv_init(struct dw_mci * host)125 static int dw_mci_exynos_priv_init(struct dw_mci *host)
126 {
127 struct dw_mci_exynos_priv_data *priv = host->priv;
128
129 dw_mci_exynos_config_smu(host);
130
131 if (priv->ctrl_type >= DW_MCI_TYPE_EXYNOS5420) {
132 priv->saved_strobe_ctrl = mci_readl(host, HS400_DLINE_CTRL);
133 priv->saved_dqs_en = mci_readl(host, HS400_DQS_EN);
134 priv->saved_dqs_en |= AXI_NON_BLOCKING_WR;
135 mci_writel(host, HS400_DQS_EN, priv->saved_dqs_en);
136 if (!priv->dqs_delay)
137 priv->dqs_delay =
138 DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl);
139 }
140
141 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
142 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU) {
143 /* Quirk needed for certain Exynos SoCs */
144 host->quirks |= DW_MMC_QUIRK_FIFO64_32;
145 }
146
147 if (priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) {
148 /* Quirk needed for the ARTPEC-8 SoC */
149 host->quirks |= DW_MMC_QUIRK_EXTENDED_TMOUT;
150 }
151
152 host->bus_hz /= (priv->ciu_div + 1);
153
154 return 0;
155 }
156
dw_mci_exynos_set_clksel_timing(struct dw_mci * host,u32 timing)157 static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing)
158 {
159 struct dw_mci_exynos_priv_data *priv = host->priv;
160 u32 clksel;
161
162 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
163 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
164 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
165 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
166 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
167 clksel = mci_readl(host, CLKSEL64);
168 else
169 clksel = mci_readl(host, CLKSEL);
170
171 clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing;
172
173 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
174 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
175 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
176 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
177 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
178 mci_writel(host, CLKSEL64, clksel);
179 else
180 mci_writel(host, CLKSEL, clksel);
181
182 /*
183 * Exynos4412 and Exynos5250 extends the use of CMD register with the
184 * use of bit 29 (which is reserved on standard MSHC controllers) for
185 * optionally bypassing the HOLD register for command and data. The
186 * HOLD register should be bypassed in case there is no phase shift
187 * applied on CMD/DATA that is sent to the card.
188 */
189 if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel) && host->slot)
190 set_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags);
191 }
192
193 #ifdef CONFIG_PM
dw_mci_exynos_runtime_resume(struct device * dev)194 static int dw_mci_exynos_runtime_resume(struct device *dev)
195 {
196 struct dw_mci *host = dev_get_drvdata(dev);
197 int ret;
198
199 ret = dw_mci_runtime_resume(dev);
200 if (ret)
201 return ret;
202
203 dw_mci_exynos_config_smu(host);
204
205 return ret;
206 }
207 #endif /* CONFIG_PM */
208
209 #ifdef CONFIG_PM_SLEEP
210 /**
211 * dw_mci_exynos_suspend_noirq - Exynos-specific suspend code
212 * @dev: Device to suspend (this device)
213 *
214 * This ensures that device will be in runtime active state in
215 * dw_mci_exynos_resume_noirq after calling pm_runtime_force_resume()
216 */
dw_mci_exynos_suspend_noirq(struct device * dev)217 static int dw_mci_exynos_suspend_noirq(struct device *dev)
218 {
219 pm_runtime_get_noresume(dev);
220 return pm_runtime_force_suspend(dev);
221 }
222
223 /**
224 * dw_mci_exynos_resume_noirq - Exynos-specific resume code
225 * @dev: Device to resume (this device)
226 *
227 * On exynos5420 there is a silicon errata that will sometimes leave the
228 * WAKEUP_INT bit in the CLKSEL register asserted. This bit is 1 to indicate
229 * that it fired and we can clear it by writing a 1 back. Clear it to prevent
230 * interrupts from going off constantly.
231 *
232 * We run this code on all exynos variants because it doesn't hurt.
233 */
dw_mci_exynos_resume_noirq(struct device * dev)234 static int dw_mci_exynos_resume_noirq(struct device *dev)
235 {
236 struct dw_mci *host = dev_get_drvdata(dev);
237 struct dw_mci_exynos_priv_data *priv = host->priv;
238 u32 clksel;
239 int ret;
240
241 ret = pm_runtime_force_resume(dev);
242 if (ret)
243 return ret;
244
245 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
246 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
247 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
248 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
249 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
250 clksel = mci_readl(host, CLKSEL64);
251 else
252 clksel = mci_readl(host, CLKSEL);
253
254 if (clksel & SDMMC_CLKSEL_WAKEUP_INT) {
255 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
256 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
257 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
258 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
259 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
260 mci_writel(host, CLKSEL64, clksel);
261 else
262 mci_writel(host, CLKSEL, clksel);
263 }
264
265 pm_runtime_put(dev);
266
267 return 0;
268 }
269 #endif /* CONFIG_PM_SLEEP */
270
dw_mci_exynos_config_hs400(struct dw_mci * host,u32 timing)271 static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing)
272 {
273 struct dw_mci_exynos_priv_data *priv = host->priv;
274 u32 dqs, strobe;
275
276 /*
277 * Not supported to configure register
278 * related to HS400
279 */
280 if ((priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420) ||
281 (priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)) {
282 if (timing == MMC_TIMING_MMC_HS400)
283 dev_warn(host->dev,
284 "cannot configure HS400, unsupported chipset\n");
285 return;
286 }
287
288 dqs = priv->saved_dqs_en;
289 strobe = priv->saved_strobe_ctrl;
290
291 if (timing == MMC_TIMING_MMC_HS400) {
292 dqs |= DATA_STROBE_EN;
293 strobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay);
294 } else if (timing == MMC_TIMING_UHS_SDR104) {
295 dqs &= 0xffffff00;
296 } else {
297 dqs &= ~DATA_STROBE_EN;
298 }
299
300 mci_writel(host, HS400_DQS_EN, dqs);
301 mci_writel(host, HS400_DLINE_CTRL, strobe);
302 }
303
dw_mci_exynos_adjust_clock(struct dw_mci * host,unsigned int wanted)304 static void dw_mci_exynos_adjust_clock(struct dw_mci *host, unsigned int wanted)
305 {
306 struct dw_mci_exynos_priv_data *priv = host->priv;
307 unsigned long actual;
308 u8 div;
309 int ret;
310 /*
311 * Don't care if wanted clock is zero or
312 * ciu clock is unavailable
313 */
314 if (!wanted || IS_ERR(host->ciu_clk))
315 return;
316
317 /* Guaranteed minimum frequency for cclkin */
318 if (wanted < EXYNOS_CCLKIN_MIN)
319 wanted = EXYNOS_CCLKIN_MIN;
320
321 if (wanted == priv->cur_speed)
322 return;
323
324 div = dw_mci_exynos_get_ciu_div(host);
325 ret = clk_set_rate(host->ciu_clk, wanted * div);
326 if (ret)
327 dev_warn(host->dev,
328 "failed to set clk-rate %u error: %d\n",
329 wanted * div, ret);
330 actual = clk_get_rate(host->ciu_clk);
331 host->bus_hz = actual / div;
332 priv->cur_speed = wanted;
333 host->current_speed = 0;
334 }
335
dw_mci_exynos_set_ios(struct dw_mci * host,struct mmc_ios * ios)336 static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
337 {
338 struct dw_mci_exynos_priv_data *priv = host->priv;
339 unsigned int wanted = ios->clock;
340 u32 timing = ios->timing, clksel;
341
342 switch (timing) {
343 case MMC_TIMING_MMC_HS400:
344 /* Update tuned sample timing */
345 clksel = SDMMC_CLKSEL_UP_SAMPLE(
346 priv->hs400_timing, priv->tuned_sample);
347 wanted <<= 1;
348 break;
349 case MMC_TIMING_MMC_DDR52:
350 clksel = priv->ddr_timing;
351 /* Should be double rate for DDR mode */
352 if (ios->bus_width == MMC_BUS_WIDTH_8)
353 wanted <<= 1;
354 break;
355 case MMC_TIMING_UHS_SDR104:
356 case MMC_TIMING_UHS_SDR50:
357 clksel = (priv->sdr_timing & 0xfff8ffff) |
358 (priv->ciu_div << 16);
359 break;
360 case MMC_TIMING_UHS_DDR50:
361 clksel = (priv->ddr_timing & 0xfff8ffff) |
362 (priv->ciu_div << 16);
363 break;
364 default:
365 clksel = priv->sdr_timing;
366 }
367
368 /* Set clock timing for the requested speed mode*/
369 dw_mci_exynos_set_clksel_timing(host, clksel);
370
371 /* Configure setting for HS400 */
372 dw_mci_exynos_config_hs400(host, timing);
373
374 /* Configure clock rate */
375 dw_mci_exynos_adjust_clock(host, wanted);
376 }
377
dw_mci_exynos_parse_dt(struct dw_mci * host)378 static int dw_mci_exynos_parse_dt(struct dw_mci *host)
379 {
380 struct dw_mci_exynos_priv_data *priv;
381 struct device_node *np = host->dev->of_node;
382 u32 timing[2];
383 u32 div = 0;
384 int idx;
385 int ret;
386
387 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
388 if (!priv)
389 return -ENOMEM;
390
391 for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
392 if (of_device_is_compatible(np, exynos_compat[idx].compatible))
393 priv->ctrl_type = exynos_compat[idx].ctrl_type;
394 }
395
396 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
397 priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1;
398 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
399 priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1;
400 else {
401 of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
402 priv->ciu_div = div;
403 }
404
405 ret = of_property_read_u32_array(np,
406 "samsung,dw-mshc-sdr-timing", timing, 2);
407 if (ret)
408 return ret;
409
410 priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
411
412 ret = of_property_read_u32_array(np,
413 "samsung,dw-mshc-ddr-timing", timing, 2);
414 if (ret)
415 return ret;
416
417 priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
418
419 ret = of_property_read_u32_array(np,
420 "samsung,dw-mshc-hs400-timing", timing, 2);
421 if (!ret && of_property_read_u32(np,
422 "samsung,read-strobe-delay", &priv->dqs_delay))
423 dev_dbg(host->dev,
424 "read-strobe-delay is not found, assuming usage of default value\n");
425
426 priv->hs400_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1],
427 HS400_FIXED_CIU_CLK_DIV);
428 host->priv = priv;
429 return 0;
430 }
431
dw_mci_exynos_get_clksmpl(struct dw_mci * host)432 static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host)
433 {
434 struct dw_mci_exynos_priv_data *priv = host->priv;
435
436 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
437 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
438 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
439 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
440 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
441 return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64));
442 else
443 return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
444 }
445
dw_mci_exynos_set_clksmpl(struct dw_mci * host,u8 sample)446 static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample)
447 {
448 u32 clksel;
449 struct dw_mci_exynos_priv_data *priv = host->priv;
450
451 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
452 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
453 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
454 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
455 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
456 clksel = mci_readl(host, CLKSEL64);
457 else
458 clksel = mci_readl(host, CLKSEL);
459 clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
460 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
461 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
462 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
463 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
464 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
465 mci_writel(host, CLKSEL64, clksel);
466 else
467 mci_writel(host, CLKSEL, clksel);
468 }
469
dw_mci_exynos_move_next_clksmpl(struct dw_mci * host)470 static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
471 {
472 struct dw_mci_exynos_priv_data *priv = host->priv;
473 u32 clksel;
474 u8 sample;
475
476 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
477 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
478 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
479 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
480 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
481 clksel = mci_readl(host, CLKSEL64);
482 else
483 clksel = mci_readl(host, CLKSEL);
484
485 sample = (clksel + 1) & 0x7;
486 clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
487
488 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
489 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
490 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
491 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
492 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
493 mci_writel(host, CLKSEL64, clksel);
494 else
495 mci_writel(host, CLKSEL, clksel);
496
497 return sample;
498 }
499
dw_mci_exynos_get_best_clksmpl(u8 candidates)500 static s8 dw_mci_exynos_get_best_clksmpl(u8 candidates)
501 {
502 const u8 iter = 8;
503 u8 __c;
504 s8 i, loc = -1;
505
506 for (i = 0; i < iter; i++) {
507 __c = ror8(candidates, i);
508 if ((__c & 0xc7) == 0xc7) {
509 loc = i;
510 goto out;
511 }
512 }
513
514 for (i = 0; i < iter; i++) {
515 __c = ror8(candidates, i);
516 if ((__c & 0x83) == 0x83) {
517 loc = i;
518 goto out;
519 }
520 }
521
522 /*
523 * If there is no cadiates value, then it needs to return -EIO.
524 * If there are candidates values and don't find bset clk sample value,
525 * then use a first candidates clock sample value.
526 */
527 for (i = 0; i < iter; i++) {
528 __c = ror8(candidates, i);
529 if ((__c & 0x1) == 0x1) {
530 loc = i;
531 goto out;
532 }
533 }
534 out:
535 return loc;
536 }
537
dw_mci_exynos_execute_tuning(struct dw_mci_slot * slot,u32 opcode)538 static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
539 {
540 struct dw_mci *host = slot->host;
541 struct dw_mci_exynos_priv_data *priv = host->priv;
542 struct mmc_host *mmc = slot->mmc;
543 u8 start_smpl, smpl, candidates = 0;
544 s8 found;
545 int ret = 0;
546
547 start_smpl = dw_mci_exynos_get_clksmpl(host);
548
549 do {
550 mci_writel(host, TMOUT, ~0);
551 smpl = dw_mci_exynos_move_next_clksmpl(host);
552
553 if (!mmc_send_tuning(mmc, opcode, NULL))
554 candidates |= (1 << smpl);
555
556 } while (start_smpl != smpl);
557
558 found = dw_mci_exynos_get_best_clksmpl(candidates);
559 if (found >= 0) {
560 dw_mci_exynos_set_clksmpl(host, found);
561 priv->tuned_sample = found;
562 } else {
563 ret = -EIO;
564 dev_warn(&mmc->class_dev,
565 "There is no candidates value about clksmpl!\n");
566 }
567
568 return ret;
569 }
570
dw_mci_exynos_prepare_hs400_tuning(struct dw_mci * host,struct mmc_ios * ios)571 static int dw_mci_exynos_prepare_hs400_tuning(struct dw_mci *host,
572 struct mmc_ios *ios)
573 {
574 struct dw_mci_exynos_priv_data *priv = host->priv;
575
576 dw_mci_exynos_set_clksel_timing(host, priv->hs400_timing);
577 dw_mci_exynos_adjust_clock(host, (ios->clock) << 1);
578
579 return 0;
580 }
581
dw_mci_exynos_set_data_timeout(struct dw_mci * host,unsigned int timeout_ns)582 static void dw_mci_exynos_set_data_timeout(struct dw_mci *host,
583 unsigned int timeout_ns)
584 {
585 u32 clk_div, tmout;
586 u64 tmp;
587 unsigned int tmp2;
588
589 clk_div = (mci_readl(host, CLKDIV) & 0xFF) * 2;
590 if (clk_div == 0)
591 clk_div = 1;
592
593 tmp = DIV_ROUND_UP_ULL((u64)timeout_ns * host->bus_hz, NSEC_PER_SEC);
594 tmp = DIV_ROUND_UP_ULL(tmp, clk_div);
595
596 /* TMOUT[7:0] (RESPONSE_TIMEOUT) */
597 tmout = 0xFF; /* Set maximum */
598
599 /*
600 * Extended HW timer (max = 0x6FFFFF2):
601 * ((TMOUT[10:8] - 1) * 0xFFFFFF + TMOUT[31:11] * 8)
602 */
603 if (!tmp || tmp > 0x6FFFFF2)
604 tmout |= (0xFFFFFF << 8);
605 else {
606 /* TMOUT[10:8] */
607 tmp2 = (((unsigned int)tmp / 0xFFFFFF) + 1) & 0x7;
608 tmout |= tmp2 << 8;
609
610 /* TMOUT[31:11] */
611 tmp = tmp - ((tmp2 - 1) * 0xFFFFFF);
612 tmout |= (tmp & 0xFFFFF8) << 8;
613 }
614
615 mci_writel(host, TMOUT, tmout);
616 dev_dbg(host->dev, "timeout_ns: %u => TMOUT[31:8]: %#08x",
617 timeout_ns, tmout >> 8);
618 }
619
dw_mci_exynos_get_drto_clks(struct dw_mci * host)620 static u32 dw_mci_exynos_get_drto_clks(struct dw_mci *host)
621 {
622 u32 drto_clks;
623
624 drto_clks = mci_readl(host, TMOUT) >> 8;
625
626 return (((drto_clks & 0x7) - 1) * 0xFFFFFF) + ((drto_clks & 0xFFFFF8));
627 }
628
629 /* Common capabilities of Exynos4/Exynos5 SoC */
630 static unsigned long exynos_dwmmc_caps[4] = {
631 MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA,
632 0,
633 0,
634 0,
635 };
636
637 static const struct dw_mci_drv_data exynos_drv_data = {
638 .caps = exynos_dwmmc_caps,
639 .num_caps = ARRAY_SIZE(exynos_dwmmc_caps),
640 .common_caps = MMC_CAP_CMD23,
641 .init = dw_mci_exynos_priv_init,
642 .set_ios = dw_mci_exynos_set_ios,
643 .parse_dt = dw_mci_exynos_parse_dt,
644 .execute_tuning = dw_mci_exynos_execute_tuning,
645 .prepare_hs400_tuning = dw_mci_exynos_prepare_hs400_tuning,
646 };
647
648 static const struct dw_mci_drv_data artpec_drv_data = {
649 .common_caps = MMC_CAP_CMD23,
650 .init = dw_mci_exynos_priv_init,
651 .set_ios = dw_mci_exynos_set_ios,
652 .parse_dt = dw_mci_exynos_parse_dt,
653 .execute_tuning = dw_mci_exynos_execute_tuning,
654 .set_data_timeout = dw_mci_exynos_set_data_timeout,
655 .get_drto_clks = dw_mci_exynos_get_drto_clks,
656 };
657
658 static const struct of_device_id dw_mci_exynos_match[] = {
659 { .compatible = "samsung,exynos4412-dw-mshc",
660 .data = &exynos_drv_data, },
661 { .compatible = "samsung,exynos5250-dw-mshc",
662 .data = &exynos_drv_data, },
663 { .compatible = "samsung,exynos5420-dw-mshc",
664 .data = &exynos_drv_data, },
665 { .compatible = "samsung,exynos5420-dw-mshc-smu",
666 .data = &exynos_drv_data, },
667 { .compatible = "samsung,exynos7-dw-mshc",
668 .data = &exynos_drv_data, },
669 { .compatible = "samsung,exynos7-dw-mshc-smu",
670 .data = &exynos_drv_data, },
671 { .compatible = "samsung,exynos7870-dw-mshc",
672 .data = &exynos_drv_data, },
673 { .compatible = "samsung,exynos7870-dw-mshc-smu",
674 .data = &exynos_drv_data, },
675 { .compatible = "axis,artpec8-dw-mshc",
676 .data = &artpec_drv_data, },
677 {},
678 };
679 MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
680
dw_mci_exynos_probe(struct platform_device * pdev)681 static int dw_mci_exynos_probe(struct platform_device *pdev)
682 {
683 const struct dw_mci_drv_data *drv_data;
684 const struct of_device_id *match;
685 int ret;
686
687 match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
688 drv_data = match->data;
689
690 pm_runtime_get_noresume(&pdev->dev);
691 pm_runtime_set_active(&pdev->dev);
692 pm_runtime_enable(&pdev->dev);
693
694 ret = dw_mci_pltfm_register(pdev, drv_data);
695 if (ret) {
696 pm_runtime_disable(&pdev->dev);
697 pm_runtime_set_suspended(&pdev->dev);
698 pm_runtime_put_noidle(&pdev->dev);
699
700 return ret;
701 }
702
703 return 0;
704 }
705
dw_mci_exynos_remove(struct platform_device * pdev)706 static void dw_mci_exynos_remove(struct platform_device *pdev)
707 {
708 pm_runtime_disable(&pdev->dev);
709 pm_runtime_set_suspended(&pdev->dev);
710 pm_runtime_put_noidle(&pdev->dev);
711
712 dw_mci_pltfm_remove(pdev);
713 }
714
715 static const struct dev_pm_ops dw_mci_exynos_pmops = {
716 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend_noirq,
717 dw_mci_exynos_resume_noirq)
718 SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
719 dw_mci_exynos_runtime_resume,
720 NULL)
721 };
722
723 static struct platform_driver dw_mci_exynos_pltfm_driver = {
724 .probe = dw_mci_exynos_probe,
725 .remove_new = dw_mci_exynos_remove,
726 .driver = {
727 .name = "dwmmc_exynos",
728 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
729 .of_match_table = dw_mci_exynos_match,
730 .pm = &dw_mci_exynos_pmops,
731 },
732 };
733
734 module_platform_driver(dw_mci_exynos_pltfm_driver);
735
736 MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
737 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
738 MODULE_LICENSE("GPL v2");
739 MODULE_ALIAS("platform:dwmmc_exynos");
740