xref: /openbmc/linux/drivers/mmc/host/mtk-sd.c (revision fd5e9fccbd504c5179ab57ff695c610bca8809d6)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2014-2015, 2022 MediaTek Inc.
4  * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
5  */
6 
7 #include <linux/module.h>
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/iopoll.h>
13 #include <linux/ioport.h>
14 #include <linux/irq.h>
15 #include <linux/of.h>
16 #include <linux/of_gpio.h>
17 #include <linux/pinctrl/consumer.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/pm_wakeirq.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/reset.h>
27 
28 #include <linux/mmc/card.h>
29 #include <linux/mmc/core.h>
30 #include <linux/mmc/host.h>
31 #include <linux/mmc/mmc.h>
32 #include <linux/mmc/sd.h>
33 #include <linux/mmc/sdio.h>
34 #include <linux/mmc/slot-gpio.h>
35 
36 #include "cqhci.h"
37 
38 #define MAX_BD_NUM          1024
39 #define MSDC_NR_CLOCKS      3
40 
41 /*--------------------------------------------------------------------------*/
42 /* Common Definition                                                        */
43 /*--------------------------------------------------------------------------*/
44 #define MSDC_BUS_1BITS          0x0
45 #define MSDC_BUS_4BITS          0x1
46 #define MSDC_BUS_8BITS          0x2
47 
48 #define MSDC_BURST_64B          0x6
49 
50 /*--------------------------------------------------------------------------*/
51 /* Register Offset                                                          */
52 /*--------------------------------------------------------------------------*/
53 #define MSDC_CFG         0x0
54 #define MSDC_IOCON       0x04
55 #define MSDC_PS          0x08
56 #define MSDC_INT         0x0c
57 #define MSDC_INTEN       0x10
58 #define MSDC_FIFOCS      0x14
59 #define SDC_CFG          0x30
60 #define SDC_CMD          0x34
61 #define SDC_ARG          0x38
62 #define SDC_STS          0x3c
63 #define SDC_RESP0        0x40
64 #define SDC_RESP1        0x44
65 #define SDC_RESP2        0x48
66 #define SDC_RESP3        0x4c
67 #define SDC_BLK_NUM      0x50
68 #define SDC_ADV_CFG0     0x64
69 #define EMMC_IOCON       0x7c
70 #define SDC_ACMD_RESP    0x80
71 #define DMA_SA_H4BIT     0x8c
72 #define MSDC_DMA_SA      0x90
73 #define MSDC_DMA_CTRL    0x98
74 #define MSDC_DMA_CFG     0x9c
75 #define MSDC_PATCH_BIT   0xb0
76 #define MSDC_PATCH_BIT1  0xb4
77 #define MSDC_PATCH_BIT2  0xb8
78 #define MSDC_PAD_TUNE    0xec
79 #define MSDC_PAD_TUNE0   0xf0
80 #define PAD_DS_TUNE      0x188
81 #define PAD_CMD_TUNE     0x18c
82 #define EMMC51_CFG0	 0x204
83 #define EMMC50_CFG0      0x208
84 #define EMMC50_CFG1      0x20c
85 #define EMMC50_CFG3      0x220
86 #define SDC_FIFO_CFG     0x228
87 #define CQHCI_SETTING	 0x7fc
88 
89 /*--------------------------------------------------------------------------*/
90 /* Top Pad Register Offset                                                  */
91 /*--------------------------------------------------------------------------*/
92 #define EMMC_TOP_CONTROL	0x00
93 #define EMMC_TOP_CMD		0x04
94 #define EMMC50_PAD_DS_TUNE	0x0c
95 
96 /*--------------------------------------------------------------------------*/
97 /* Register Mask                                                            */
98 /*--------------------------------------------------------------------------*/
99 
100 /* MSDC_CFG mask */
101 #define MSDC_CFG_MODE           BIT(0)	/* RW */
102 #define MSDC_CFG_CKPDN          BIT(1)	/* RW */
103 #define MSDC_CFG_RST            BIT(2)	/* RW */
104 #define MSDC_CFG_PIO            BIT(3)	/* RW */
105 #define MSDC_CFG_CKDRVEN        BIT(4)	/* RW */
106 #define MSDC_CFG_BV18SDT        BIT(5)	/* RW */
107 #define MSDC_CFG_BV18PSS        BIT(6)	/* R  */
108 #define MSDC_CFG_CKSTB          BIT(7)	/* R  */
109 #define MSDC_CFG_CKDIV          GENMASK(15, 8)	/* RW */
110 #define MSDC_CFG_CKMOD          GENMASK(17, 16)	/* RW */
111 #define MSDC_CFG_HS400_CK_MODE  BIT(18)	/* RW */
112 #define MSDC_CFG_HS400_CK_MODE_EXTRA  BIT(22)	/* RW */
113 #define MSDC_CFG_CKDIV_EXTRA    GENMASK(19, 8)	/* RW */
114 #define MSDC_CFG_CKMOD_EXTRA    GENMASK(21, 20)	/* RW */
115 
116 /* MSDC_IOCON mask */
117 #define MSDC_IOCON_SDR104CKS    BIT(0)	/* RW */
118 #define MSDC_IOCON_RSPL         BIT(1)	/* RW */
119 #define MSDC_IOCON_DSPL         BIT(2)	/* RW */
120 #define MSDC_IOCON_DDLSEL       BIT(3)	/* RW */
121 #define MSDC_IOCON_DDR50CKD     BIT(4)	/* RW */
122 #define MSDC_IOCON_DSPLSEL      BIT(5)	/* RW */
123 #define MSDC_IOCON_W_DSPL       BIT(8)	/* RW */
124 #define MSDC_IOCON_D0SPL        BIT(16)	/* RW */
125 #define MSDC_IOCON_D1SPL        BIT(17)	/* RW */
126 #define MSDC_IOCON_D2SPL        BIT(18)	/* RW */
127 #define MSDC_IOCON_D3SPL        BIT(19)	/* RW */
128 #define MSDC_IOCON_D4SPL        BIT(20)	/* RW */
129 #define MSDC_IOCON_D5SPL        BIT(21)	/* RW */
130 #define MSDC_IOCON_D6SPL        BIT(22)	/* RW */
131 #define MSDC_IOCON_D7SPL        BIT(23)	/* RW */
132 #define MSDC_IOCON_RISCSZ       GENMASK(25, 24)	/* RW */
133 
134 /* MSDC_PS mask */
135 #define MSDC_PS_CDEN            BIT(0)	/* RW */
136 #define MSDC_PS_CDSTS           BIT(1)	/* R  */
137 #define MSDC_PS_CDDEBOUNCE      GENMASK(15, 12)	/* RW */
138 #define MSDC_PS_DAT             GENMASK(23, 16)	/* R  */
139 #define MSDC_PS_DATA1           BIT(17)	/* R  */
140 #define MSDC_PS_CMD             BIT(24)	/* R  */
141 #define MSDC_PS_WP              BIT(31)	/* R  */
142 
143 /* MSDC_INT mask */
144 #define MSDC_INT_MMCIRQ         BIT(0)	/* W1C */
145 #define MSDC_INT_CDSC           BIT(1)	/* W1C */
146 #define MSDC_INT_ACMDRDY        BIT(3)	/* W1C */
147 #define MSDC_INT_ACMDTMO        BIT(4)	/* W1C */
148 #define MSDC_INT_ACMDCRCERR     BIT(5)	/* W1C */
149 #define MSDC_INT_DMAQ_EMPTY     BIT(6)	/* W1C */
150 #define MSDC_INT_SDIOIRQ        BIT(7)	/* W1C */
151 #define MSDC_INT_CMDRDY         BIT(8)	/* W1C */
152 #define MSDC_INT_CMDTMO         BIT(9)	/* W1C */
153 #define MSDC_INT_RSPCRCERR      BIT(10)	/* W1C */
154 #define MSDC_INT_CSTA           BIT(11)	/* R */
155 #define MSDC_INT_XFER_COMPL     BIT(12)	/* W1C */
156 #define MSDC_INT_DXFER_DONE     BIT(13)	/* W1C */
157 #define MSDC_INT_DATTMO         BIT(14)	/* W1C */
158 #define MSDC_INT_DATCRCERR      BIT(15)	/* W1C */
159 #define MSDC_INT_ACMD19_DONE    BIT(16)	/* W1C */
160 #define MSDC_INT_DMA_BDCSERR    BIT(17)	/* W1C */
161 #define MSDC_INT_DMA_GPDCSERR   BIT(18)	/* W1C */
162 #define MSDC_INT_DMA_PROTECT    BIT(19)	/* W1C */
163 #define MSDC_INT_CMDQ           BIT(28)	/* W1C */
164 
165 /* MSDC_INTEN mask */
166 #define MSDC_INTEN_MMCIRQ       BIT(0)	/* RW */
167 #define MSDC_INTEN_CDSC         BIT(1)	/* RW */
168 #define MSDC_INTEN_ACMDRDY      BIT(3)	/* RW */
169 #define MSDC_INTEN_ACMDTMO      BIT(4)	/* RW */
170 #define MSDC_INTEN_ACMDCRCERR   BIT(5)	/* RW */
171 #define MSDC_INTEN_DMAQ_EMPTY   BIT(6)	/* RW */
172 #define MSDC_INTEN_SDIOIRQ      BIT(7)	/* RW */
173 #define MSDC_INTEN_CMDRDY       BIT(8)	/* RW */
174 #define MSDC_INTEN_CMDTMO       BIT(9)	/* RW */
175 #define MSDC_INTEN_RSPCRCERR    BIT(10)	/* RW */
176 #define MSDC_INTEN_CSTA         BIT(11)	/* RW */
177 #define MSDC_INTEN_XFER_COMPL   BIT(12)	/* RW */
178 #define MSDC_INTEN_DXFER_DONE   BIT(13)	/* RW */
179 #define MSDC_INTEN_DATTMO       BIT(14)	/* RW */
180 #define MSDC_INTEN_DATCRCERR    BIT(15)	/* RW */
181 #define MSDC_INTEN_ACMD19_DONE  BIT(16)	/* RW */
182 #define MSDC_INTEN_DMA_BDCSERR  BIT(17)	/* RW */
183 #define MSDC_INTEN_DMA_GPDCSERR BIT(18)	/* RW */
184 #define MSDC_INTEN_DMA_PROTECT  BIT(19)	/* RW */
185 
186 /* MSDC_FIFOCS mask */
187 #define MSDC_FIFOCS_RXCNT       GENMASK(7, 0)	/* R */
188 #define MSDC_FIFOCS_TXCNT       GENMASK(23, 16)	/* R */
189 #define MSDC_FIFOCS_CLR         BIT(31)	/* RW */
190 
191 /* SDC_CFG mask */
192 #define SDC_CFG_SDIOINTWKUP     BIT(0)	/* RW */
193 #define SDC_CFG_INSWKUP         BIT(1)	/* RW */
194 #define SDC_CFG_WRDTOC          GENMASK(14, 2)  /* RW */
195 #define SDC_CFG_BUSWIDTH        GENMASK(17, 16)	/* RW */
196 #define SDC_CFG_SDIO            BIT(19)	/* RW */
197 #define SDC_CFG_SDIOIDE         BIT(20)	/* RW */
198 #define SDC_CFG_INTATGAP        BIT(21)	/* RW */
199 #define SDC_CFG_DTOC            GENMASK(31, 24)	/* RW */
200 
201 /* SDC_STS mask */
202 #define SDC_STS_SDCBUSY         BIT(0)	/* RW */
203 #define SDC_STS_CMDBUSY         BIT(1)	/* RW */
204 #define SDC_STS_SWR_COMPL       BIT(31)	/* RW */
205 
206 #define SDC_DAT1_IRQ_TRIGGER	BIT(19)	/* RW */
207 /* SDC_ADV_CFG0 mask */
208 #define SDC_RX_ENHANCE_EN	BIT(20)	/* RW */
209 
210 /* DMA_SA_H4BIT mask */
211 #define DMA_ADDR_HIGH_4BIT      GENMASK(3, 0)	/* RW */
212 
213 /* MSDC_DMA_CTRL mask */
214 #define MSDC_DMA_CTRL_START     BIT(0)	/* W */
215 #define MSDC_DMA_CTRL_STOP      BIT(1)	/* W */
216 #define MSDC_DMA_CTRL_RESUME    BIT(2)	/* W */
217 #define MSDC_DMA_CTRL_MODE      BIT(8)	/* RW */
218 #define MSDC_DMA_CTRL_LASTBUF   BIT(10)	/* RW */
219 #define MSDC_DMA_CTRL_BRUSTSZ   GENMASK(14, 12)	/* RW */
220 
221 /* MSDC_DMA_CFG mask */
222 #define MSDC_DMA_CFG_STS        BIT(0)	/* R */
223 #define MSDC_DMA_CFG_DECSEN     BIT(1)	/* RW */
224 #define MSDC_DMA_CFG_AHBHPROT2  BIT(9)	/* RW */
225 #define MSDC_DMA_CFG_ACTIVEEN   BIT(13)	/* RW */
226 #define MSDC_DMA_CFG_CS12B16B   BIT(16)	/* RW */
227 
228 /* MSDC_PATCH_BIT mask */
229 #define MSDC_PATCH_BIT_ODDSUPP    BIT(1)	/* RW */
230 #define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7)
231 #define MSDC_CKGEN_MSDC_DLY_SEL   GENMASK(14, 10)
232 #define MSDC_PATCH_BIT_IODSSEL    BIT(16)	/* RW */
233 #define MSDC_PATCH_BIT_IOINTSEL   BIT(17)	/* RW */
234 #define MSDC_PATCH_BIT_BUSYDLY    GENMASK(21, 18)	/* RW */
235 #define MSDC_PATCH_BIT_WDOD       GENMASK(25, 22)	/* RW */
236 #define MSDC_PATCH_BIT_IDRTSEL    BIT(26)	/* RW */
237 #define MSDC_PATCH_BIT_CMDFSEL    BIT(27)	/* RW */
238 #define MSDC_PATCH_BIT_INTDLSEL   BIT(28)	/* RW */
239 #define MSDC_PATCH_BIT_SPCPUSH    BIT(29)	/* RW */
240 #define MSDC_PATCH_BIT_DECRCTMO   BIT(30)	/* RW */
241 
242 #define MSDC_PATCH_BIT1_CMDTA     GENMASK(5, 3)    /* RW */
243 #define MSDC_PB1_BUSY_CHECK_SEL   BIT(7)    /* RW */
244 #define MSDC_PATCH_BIT1_STOP_DLY  GENMASK(11, 8)    /* RW */
245 
246 #define MSDC_PATCH_BIT2_CFGRESP   BIT(15)   /* RW */
247 #define MSDC_PATCH_BIT2_CFGCRCSTS BIT(28)   /* RW */
248 #define MSDC_PB2_SUPPORT_64G      BIT(1)    /* RW */
249 #define MSDC_PB2_RESPWAIT         GENMASK(3, 2)   /* RW */
250 #define MSDC_PB2_RESPSTSENSEL     GENMASK(18, 16) /* RW */
251 #define MSDC_PB2_CRCSTSENSEL      GENMASK(31, 29) /* RW */
252 
253 #define MSDC_PAD_TUNE_DATWRDLY	  GENMASK(4, 0)		/* RW */
254 #define MSDC_PAD_TUNE_DATRRDLY	  GENMASK(12, 8)	/* RW */
255 #define MSDC_PAD_TUNE_CMDRDLY	  GENMASK(20, 16)	/* RW */
256 #define MSDC_PAD_TUNE_CMDRRDLY	  GENMASK(26, 22)	/* RW */
257 #define MSDC_PAD_TUNE_CLKTDLY	  GENMASK(31, 27)	/* RW */
258 #define MSDC_PAD_TUNE_RXDLYSEL	  BIT(15)   /* RW */
259 #define MSDC_PAD_TUNE_RD_SEL	  BIT(13)   /* RW */
260 #define MSDC_PAD_TUNE_CMD_SEL	  BIT(21)   /* RW */
261 
262 #define PAD_DS_TUNE_DLY_SEL       BIT(0)	  /* RW */
263 #define PAD_DS_TUNE_DLY2_SEL      BIT(1)	  /* RW */
264 #define PAD_DS_TUNE_DLY1	  GENMASK(6, 2)   /* RW */
265 #define PAD_DS_TUNE_DLY2	  GENMASK(11, 7)  /* RW */
266 #define PAD_DS_TUNE_DLY3	  GENMASK(16, 12) /* RW */
267 
268 #define PAD_CMD_TUNE_RX_DLY3	  GENMASK(5, 1)   /* RW */
269 
270 /* EMMC51_CFG0 mask */
271 #define CMDQ_RDAT_CNT		  GENMASK(21, 12) /* RW */
272 
273 #define EMMC50_CFG_PADCMD_LATCHCK BIT(0)   /* RW */
274 #define EMMC50_CFG_CRCSTS_EDGE    BIT(3)   /* RW */
275 #define EMMC50_CFG_CFCSTS_SEL     BIT(4)   /* RW */
276 #define EMMC50_CFG_CMD_RESP_SEL   BIT(9)   /* RW */
277 
278 /* EMMC50_CFG1 mask */
279 #define EMMC50_CFG1_DS_CFG        BIT(28)  /* RW */
280 
281 #define EMMC50_CFG3_OUTS_WR       GENMASK(4, 0)  /* RW */
282 
283 #define SDC_FIFO_CFG_WRVALIDSEL   BIT(24)  /* RW */
284 #define SDC_FIFO_CFG_RDVALIDSEL   BIT(25)  /* RW */
285 
286 /* CQHCI_SETTING */
287 #define CQHCI_RD_CMD_WND_SEL	  BIT(14) /* RW */
288 #define CQHCI_WR_CMD_WND_SEL	  BIT(15) /* RW */
289 
290 /* EMMC_TOP_CONTROL mask */
291 #define PAD_RXDLY_SEL           BIT(0)      /* RW */
292 #define DELAY_EN                BIT(1)      /* RW */
293 #define PAD_DAT_RD_RXDLY2       GENMASK(6, 2)     /* RW */
294 #define PAD_DAT_RD_RXDLY        GENMASK(11, 7)    /* RW */
295 #define PAD_DAT_RD_RXDLY2_SEL   BIT(12)     /* RW */
296 #define PAD_DAT_RD_RXDLY_SEL    BIT(13)     /* RW */
297 #define DATA_K_VALUE_SEL        BIT(14)     /* RW */
298 #define SDC_RX_ENH_EN           BIT(15)     /* TW */
299 
300 /* EMMC_TOP_CMD mask */
301 #define PAD_CMD_RXDLY2          GENMASK(4, 0)	/* RW */
302 #define PAD_CMD_RXDLY           GENMASK(9, 5)	/* RW */
303 #define PAD_CMD_RD_RXDLY2_SEL   BIT(10)		/* RW */
304 #define PAD_CMD_RD_RXDLY_SEL    BIT(11)		/* RW */
305 #define PAD_CMD_TX_DLY          GENMASK(16, 12)	/* RW */
306 
307 /* EMMC50_PAD_DS_TUNE mask */
308 #define PAD_DS_DLY_SEL		BIT(16)	/* RW */
309 #define PAD_DS_DLY2_SEL		BIT(15)	/* RW */
310 #define PAD_DS_DLY1		GENMASK(14, 10)	/* RW */
311 #define PAD_DS_DLY3		GENMASK(4, 0)	/* RW */
312 
313 #define REQ_CMD_EIO  BIT(0)
314 #define REQ_CMD_TMO  BIT(1)
315 #define REQ_DAT_ERR  BIT(2)
316 #define REQ_STOP_EIO BIT(3)
317 #define REQ_STOP_TMO BIT(4)
318 #define REQ_CMD_BUSY BIT(5)
319 
320 #define MSDC_PREPARE_FLAG BIT(0)
321 #define MSDC_ASYNC_FLAG BIT(1)
322 #define MSDC_MMAP_FLAG BIT(2)
323 
324 #define MTK_MMC_AUTOSUSPEND_DELAY	50
325 #define CMD_TIMEOUT         (HZ/10 * 5)	/* 100ms x5 */
326 #define DAT_TIMEOUT         (HZ    * 5)	/* 1000ms x5 */
327 
328 #define DEFAULT_DEBOUNCE	(8)	/* 8 cycles CD debounce */
329 
330 #define PAD_DELAY_MAX	32 /* PAD delay cells */
331 /*--------------------------------------------------------------------------*/
332 /* Descriptor Structure                                                     */
333 /*--------------------------------------------------------------------------*/
334 struct mt_gpdma_desc {
335 	u32 gpd_info;
336 #define GPDMA_DESC_HWO		BIT(0)
337 #define GPDMA_DESC_BDP		BIT(1)
338 #define GPDMA_DESC_CHECKSUM	GENMASK(15, 8)
339 #define GPDMA_DESC_INT		BIT(16)
340 #define GPDMA_DESC_NEXT_H4	GENMASK(27, 24)
341 #define GPDMA_DESC_PTR_H4	GENMASK(31, 28)
342 	u32 next;
343 	u32 ptr;
344 	u32 gpd_data_len;
345 #define GPDMA_DESC_BUFLEN	GENMASK(15, 0)
346 #define GPDMA_DESC_EXTLEN	GENMASK(23, 16)
347 	u32 arg;
348 	u32 blknum;
349 	u32 cmd;
350 };
351 
352 struct mt_bdma_desc {
353 	u32 bd_info;
354 #define BDMA_DESC_EOL		BIT(0)
355 #define BDMA_DESC_CHECKSUM	GENMASK(15, 8)
356 #define BDMA_DESC_BLKPAD	BIT(17)
357 #define BDMA_DESC_DWPAD		BIT(18)
358 #define BDMA_DESC_NEXT_H4	GENMASK(27, 24)
359 #define BDMA_DESC_PTR_H4	GENMASK(31, 28)
360 	u32 next;
361 	u32 ptr;
362 	u32 bd_data_len;
363 #define BDMA_DESC_BUFLEN	GENMASK(15, 0)
364 #define BDMA_DESC_BUFLEN_EXT	GENMASK(23, 0)
365 };
366 
367 struct msdc_dma {
368 	struct scatterlist *sg;	/* I/O scatter list */
369 	struct mt_gpdma_desc *gpd;		/* pointer to gpd array */
370 	struct mt_bdma_desc *bd;		/* pointer to bd array */
371 	dma_addr_t gpd_addr;	/* the physical address of gpd array */
372 	dma_addr_t bd_addr;	/* the physical address of bd array */
373 };
374 
375 struct msdc_save_para {
376 	u32 msdc_cfg;
377 	u32 iocon;
378 	u32 sdc_cfg;
379 	u32 pad_tune;
380 	u32 patch_bit0;
381 	u32 patch_bit1;
382 	u32 patch_bit2;
383 	u32 pad_ds_tune;
384 	u32 pad_cmd_tune;
385 	u32 emmc50_cfg0;
386 	u32 emmc50_cfg3;
387 	u32 sdc_fifo_cfg;
388 	u32 emmc_top_control;
389 	u32 emmc_top_cmd;
390 	u32 emmc50_pad_ds_tune;
391 };
392 
393 struct mtk_mmc_compatible {
394 	u8 clk_div_bits;
395 	bool recheck_sdio_irq;
396 	bool hs400_tune; /* only used for MT8173 */
397 	u32 pad_tune_reg;
398 	bool async_fifo;
399 	bool data_tune;
400 	bool busy_check;
401 	bool stop_clk_fix;
402 	bool enhance_rx;
403 	bool support_64g;
404 	bool use_internal_cd;
405 };
406 
407 struct msdc_tune_para {
408 	u32 iocon;
409 	u32 pad_tune;
410 	u32 pad_cmd_tune;
411 	u32 emmc_top_control;
412 	u32 emmc_top_cmd;
413 };
414 
415 struct msdc_delay_phase {
416 	u8 maxlen;
417 	u8 start;
418 	u8 final_phase;
419 };
420 
421 struct msdc_host {
422 	struct device *dev;
423 	const struct mtk_mmc_compatible *dev_comp;
424 	int cmd_rsp;
425 
426 	spinlock_t lock;
427 	struct mmc_request *mrq;
428 	struct mmc_command *cmd;
429 	struct mmc_data *data;
430 	int error;
431 
432 	void __iomem *base;		/* host base address */
433 	void __iomem *top_base;		/* host top register base address */
434 
435 	struct msdc_dma dma;	/* dma channel */
436 	u64 dma_mask;
437 
438 	u32 timeout_ns;		/* data timeout ns */
439 	u32 timeout_clks;	/* data timeout clks */
440 
441 	struct pinctrl *pinctrl;
442 	struct pinctrl_state *pins_default;
443 	struct pinctrl_state *pins_uhs;
444 	struct pinctrl_state *pins_eint;
445 	struct delayed_work req_timeout;
446 	int irq;		/* host interrupt */
447 	int eint_irq;		/* interrupt from sdio device for waking up system */
448 	struct reset_control *reset;
449 
450 	struct clk *src_clk;	/* msdc source clock */
451 	struct clk *h_clk;      /* msdc h_clk */
452 	struct clk *bus_clk;	/* bus clock which used to access register */
453 	struct clk *src_clk_cg; /* msdc source clock control gate */
454 	struct clk *sys_clk_cg;	/* msdc subsys clock control gate */
455 	struct clk *crypto_clk; /* msdc crypto clock control gate */
456 	struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
457 	u32 mclk;		/* mmc subsystem clock frequency */
458 	u32 src_clk_freq;	/* source clock frequency */
459 	unsigned char timing;
460 	bool vqmmc_enabled;
461 	u32 latch_ck;
462 	u32 hs400_ds_delay;
463 	u32 hs400_ds_dly3;
464 	u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
465 	u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
466 	bool hs400_cmd_resp_sel_rising;
467 				 /* cmd response sample selection for HS400 */
468 	bool hs400_mode;	/* current eMMC will run at hs400 mode */
469 	bool hs400_tuning;	/* hs400 mode online tuning */
470 	bool internal_cd;	/* Use internal card-detect logic */
471 	bool cqhci;		/* support eMMC hw cmdq */
472 	struct msdc_save_para save_para; /* used when gate HCLK */
473 	struct msdc_tune_para def_tune_para; /* default tune setting */
474 	struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
475 	struct cqhci_host *cq_host;
476 	u32 cq_ssc1_time;
477 };
478 
479 static const struct mtk_mmc_compatible mt2701_compat = {
480 	.clk_div_bits = 12,
481 	.recheck_sdio_irq = true,
482 	.hs400_tune = false,
483 	.pad_tune_reg = MSDC_PAD_TUNE0,
484 	.async_fifo = true,
485 	.data_tune = true,
486 	.busy_check = false,
487 	.stop_clk_fix = false,
488 	.enhance_rx = false,
489 	.support_64g = false,
490 };
491 
492 static const struct mtk_mmc_compatible mt2712_compat = {
493 	.clk_div_bits = 12,
494 	.recheck_sdio_irq = false,
495 	.hs400_tune = false,
496 	.pad_tune_reg = MSDC_PAD_TUNE0,
497 	.async_fifo = true,
498 	.data_tune = true,
499 	.busy_check = true,
500 	.stop_clk_fix = true,
501 	.enhance_rx = true,
502 	.support_64g = true,
503 };
504 
505 static const struct mtk_mmc_compatible mt6779_compat = {
506 	.clk_div_bits = 12,
507 	.recheck_sdio_irq = false,
508 	.hs400_tune = false,
509 	.pad_tune_reg = MSDC_PAD_TUNE0,
510 	.async_fifo = true,
511 	.data_tune = true,
512 	.busy_check = true,
513 	.stop_clk_fix = true,
514 	.enhance_rx = true,
515 	.support_64g = true,
516 };
517 
518 static const struct mtk_mmc_compatible mt6795_compat = {
519 	.clk_div_bits = 8,
520 	.recheck_sdio_irq = false,
521 	.hs400_tune = true,
522 	.pad_tune_reg = MSDC_PAD_TUNE,
523 	.async_fifo = false,
524 	.data_tune = false,
525 	.busy_check = false,
526 	.stop_clk_fix = false,
527 	.enhance_rx = false,
528 	.support_64g = false,
529 };
530 
531 static const struct mtk_mmc_compatible mt7620_compat = {
532 	.clk_div_bits = 8,
533 	.recheck_sdio_irq = true,
534 	.hs400_tune = false,
535 	.pad_tune_reg = MSDC_PAD_TUNE,
536 	.async_fifo = false,
537 	.data_tune = false,
538 	.busy_check = false,
539 	.stop_clk_fix = false,
540 	.enhance_rx = false,
541 	.use_internal_cd = true,
542 };
543 
544 static const struct mtk_mmc_compatible mt7622_compat = {
545 	.clk_div_bits = 12,
546 	.recheck_sdio_irq = true,
547 	.hs400_tune = false,
548 	.pad_tune_reg = MSDC_PAD_TUNE0,
549 	.async_fifo = true,
550 	.data_tune = true,
551 	.busy_check = true,
552 	.stop_clk_fix = true,
553 	.enhance_rx = true,
554 	.support_64g = false,
555 };
556 
557 static const struct mtk_mmc_compatible mt7986_compat = {
558 	.clk_div_bits = 12,
559 	.recheck_sdio_irq = true,
560 	.hs400_tune = false,
561 	.pad_tune_reg = MSDC_PAD_TUNE0,
562 	.async_fifo = true,
563 	.data_tune = true,
564 	.busy_check = true,
565 	.stop_clk_fix = true,
566 	.enhance_rx = true,
567 	.support_64g = true,
568 };
569 
570 static const struct mtk_mmc_compatible mt8135_compat = {
571 	.clk_div_bits = 8,
572 	.recheck_sdio_irq = true,
573 	.hs400_tune = false,
574 	.pad_tune_reg = MSDC_PAD_TUNE,
575 	.async_fifo = false,
576 	.data_tune = false,
577 	.busy_check = false,
578 	.stop_clk_fix = false,
579 	.enhance_rx = false,
580 	.support_64g = false,
581 };
582 
583 static const struct mtk_mmc_compatible mt8173_compat = {
584 	.clk_div_bits = 8,
585 	.recheck_sdio_irq = true,
586 	.hs400_tune = true,
587 	.pad_tune_reg = MSDC_PAD_TUNE,
588 	.async_fifo = false,
589 	.data_tune = false,
590 	.busy_check = false,
591 	.stop_clk_fix = false,
592 	.enhance_rx = false,
593 	.support_64g = false,
594 };
595 
596 static const struct mtk_mmc_compatible mt8183_compat = {
597 	.clk_div_bits = 12,
598 	.recheck_sdio_irq = false,
599 	.hs400_tune = false,
600 	.pad_tune_reg = MSDC_PAD_TUNE0,
601 	.async_fifo = true,
602 	.data_tune = true,
603 	.busy_check = true,
604 	.stop_clk_fix = true,
605 	.enhance_rx = true,
606 	.support_64g = true,
607 };
608 
609 static const struct mtk_mmc_compatible mt8516_compat = {
610 	.clk_div_bits = 12,
611 	.recheck_sdio_irq = true,
612 	.hs400_tune = false,
613 	.pad_tune_reg = MSDC_PAD_TUNE0,
614 	.async_fifo = true,
615 	.data_tune = true,
616 	.busy_check = true,
617 	.stop_clk_fix = true,
618 };
619 
620 static const struct of_device_id msdc_of_ids[] = {
621 	{ .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
622 	{ .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
623 	{ .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
624 	{ .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat},
625 	{ .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
626 	{ .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
627 	{ .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
628 	{ .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
629 	{ .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
630 	{ .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
631 	{ .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
632 
633 	{}
634 };
635 MODULE_DEVICE_TABLE(of, msdc_of_ids);
636 
sdr_set_bits(void __iomem * reg,u32 bs)637 static void sdr_set_bits(void __iomem *reg, u32 bs)
638 {
639 	u32 val = readl(reg);
640 
641 	val |= bs;
642 	writel(val, reg);
643 }
644 
sdr_clr_bits(void __iomem * reg,u32 bs)645 static void sdr_clr_bits(void __iomem *reg, u32 bs)
646 {
647 	u32 val = readl(reg);
648 
649 	val &= ~bs;
650 	writel(val, reg);
651 }
652 
sdr_set_field(void __iomem * reg,u32 field,u32 val)653 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
654 {
655 	unsigned int tv = readl(reg);
656 
657 	tv &= ~field;
658 	tv |= ((val) << (ffs((unsigned int)field) - 1));
659 	writel(tv, reg);
660 }
661 
sdr_get_field(void __iomem * reg,u32 field,u32 * val)662 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
663 {
664 	unsigned int tv = readl(reg);
665 
666 	*val = ((tv & field) >> (ffs((unsigned int)field) - 1));
667 }
668 
msdc_reset_hw(struct msdc_host * host)669 static void msdc_reset_hw(struct msdc_host *host)
670 {
671 	u32 val;
672 
673 	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
674 	readl_poll_timeout_atomic(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0);
675 
676 	sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
677 	readl_poll_timeout_atomic(host->base + MSDC_FIFOCS, val,
678 				  !(val & MSDC_FIFOCS_CLR), 0, 0);
679 
680 	val = readl(host->base + MSDC_INT);
681 	writel(val, host->base + MSDC_INT);
682 }
683 
684 static void msdc_cmd_next(struct msdc_host *host,
685 		struct mmc_request *mrq, struct mmc_command *cmd);
686 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb);
687 
688 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
689 			MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
690 			MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
691 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
692 			MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
693 			MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
694 
msdc_dma_calcs(u8 * buf,u32 len)695 static u8 msdc_dma_calcs(u8 *buf, u32 len)
696 {
697 	u32 i, sum = 0;
698 
699 	for (i = 0; i < len; i++)
700 		sum += buf[i];
701 	return 0xff - (u8) sum;
702 }
703 
msdc_dma_setup(struct msdc_host * host,struct msdc_dma * dma,struct mmc_data * data)704 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
705 		struct mmc_data *data)
706 {
707 	unsigned int j, dma_len;
708 	dma_addr_t dma_address;
709 	u32 dma_ctrl;
710 	struct scatterlist *sg;
711 	struct mt_gpdma_desc *gpd;
712 	struct mt_bdma_desc *bd;
713 
714 	sg = data->sg;
715 
716 	gpd = dma->gpd;
717 	bd = dma->bd;
718 
719 	/* modify gpd */
720 	gpd->gpd_info |= GPDMA_DESC_HWO;
721 	gpd->gpd_info |= GPDMA_DESC_BDP;
722 	/* need to clear first. use these bits to calc checksum */
723 	gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
724 	gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
725 
726 	/* modify bd */
727 	for_each_sg(data->sg, sg, data->sg_count, j) {
728 		dma_address = sg_dma_address(sg);
729 		dma_len = sg_dma_len(sg);
730 
731 		/* init bd */
732 		bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
733 		bd[j].bd_info &= ~BDMA_DESC_DWPAD;
734 		bd[j].ptr = lower_32_bits(dma_address);
735 		if (host->dev_comp->support_64g) {
736 			bd[j].bd_info &= ~BDMA_DESC_PTR_H4;
737 			bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf)
738 					 << 28;
739 		}
740 
741 		if (host->dev_comp->support_64g) {
742 			bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT;
743 			bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT);
744 		} else {
745 			bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
746 			bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
747 		}
748 
749 		if (j == data->sg_count - 1) /* the last bd */
750 			bd[j].bd_info |= BDMA_DESC_EOL;
751 		else
752 			bd[j].bd_info &= ~BDMA_DESC_EOL;
753 
754 		/* checksum need to clear first */
755 		bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
756 		bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
757 	}
758 
759 	sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
760 	dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
761 	dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
762 	dma_ctrl |= (MSDC_BURST_64B << 12 | BIT(8));
763 	writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
764 	if (host->dev_comp->support_64g)
765 		sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
766 			      upper_32_bits(dma->gpd_addr) & 0xf);
767 	writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
768 }
769 
msdc_prepare_data(struct msdc_host * host,struct mmc_data * data)770 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data)
771 {
772 	if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
773 		data->host_cookie |= MSDC_PREPARE_FLAG;
774 		data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
775 					    mmc_get_dma_dir(data));
776 	}
777 }
778 
msdc_unprepare_data(struct msdc_host * host,struct mmc_data * data)779 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data)
780 {
781 	if (data->host_cookie & MSDC_ASYNC_FLAG)
782 		return;
783 
784 	if (data->host_cookie & MSDC_PREPARE_FLAG) {
785 		dma_unmap_sg(host->dev, data->sg, data->sg_len,
786 			     mmc_get_dma_dir(data));
787 		data->host_cookie &= ~MSDC_PREPARE_FLAG;
788 	}
789 }
790 
msdc_timeout_cal(struct msdc_host * host,u64 ns,u64 clks)791 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks)
792 {
793 	struct mmc_host *mmc = mmc_from_priv(host);
794 	u64 timeout, clk_ns;
795 	u32 mode = 0;
796 
797 	if (mmc->actual_clock == 0) {
798 		timeout = 0;
799 	} else {
800 		clk_ns  = 1000000000ULL;
801 		do_div(clk_ns, mmc->actual_clock);
802 		timeout = ns + clk_ns - 1;
803 		do_div(timeout, clk_ns);
804 		timeout += clks;
805 		/* in 1048576 sclk cycle unit */
806 		timeout = DIV_ROUND_UP(timeout, BIT(20));
807 		if (host->dev_comp->clk_div_bits == 8)
808 			sdr_get_field(host->base + MSDC_CFG,
809 				      MSDC_CFG_CKMOD, &mode);
810 		else
811 			sdr_get_field(host->base + MSDC_CFG,
812 				      MSDC_CFG_CKMOD_EXTRA, &mode);
813 		/*DDR mode will double the clk cycles for data timeout */
814 		timeout = mode >= 2 ? timeout * 2 : timeout;
815 		timeout = timeout > 1 ? timeout - 1 : 0;
816 	}
817 	return timeout;
818 }
819 
820 /* clock control primitives */
msdc_set_timeout(struct msdc_host * host,u64 ns,u64 clks)821 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks)
822 {
823 	u64 timeout;
824 
825 	host->timeout_ns = ns;
826 	host->timeout_clks = clks;
827 
828 	timeout = msdc_timeout_cal(host, ns, clks);
829 	sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC,
830 		      (u32)(timeout > 255 ? 255 : timeout));
831 }
832 
msdc_set_busy_timeout(struct msdc_host * host,u64 ns,u64 clks)833 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
834 {
835 	u64 timeout;
836 
837 	timeout = msdc_timeout_cal(host, ns, clks);
838 	sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC,
839 		      (u32)(timeout > 8191 ? 8191 : timeout));
840 }
841 
msdc_gate_clock(struct msdc_host * host)842 static void msdc_gate_clock(struct msdc_host *host)
843 {
844 	clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
845 	clk_disable_unprepare(host->crypto_clk);
846 	clk_disable_unprepare(host->src_clk_cg);
847 	clk_disable_unprepare(host->src_clk);
848 	clk_disable_unprepare(host->bus_clk);
849 	clk_disable_unprepare(host->h_clk);
850 }
851 
msdc_ungate_clock(struct msdc_host * host)852 static int msdc_ungate_clock(struct msdc_host *host)
853 {
854 	u32 val;
855 	int ret;
856 
857 	clk_prepare_enable(host->h_clk);
858 	clk_prepare_enable(host->bus_clk);
859 	clk_prepare_enable(host->src_clk);
860 	clk_prepare_enable(host->src_clk_cg);
861 	clk_prepare_enable(host->crypto_clk);
862 	ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
863 	if (ret) {
864 		dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
865 		return ret;
866 	}
867 
868 	return readl_poll_timeout(host->base + MSDC_CFG, val,
869 				  (val & MSDC_CFG_CKSTB), 1, 20000);
870 }
871 
msdc_set_mclk(struct msdc_host * host,unsigned char timing,u32 hz)872 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
873 {
874 	struct mmc_host *mmc = mmc_from_priv(host);
875 	u32 mode;
876 	u32 flags;
877 	u32 div;
878 	u32 sclk;
879 	u32 tune_reg = host->dev_comp->pad_tune_reg;
880 	u32 val;
881 
882 	if (!hz) {
883 		dev_dbg(host->dev, "set mclk to 0\n");
884 		host->mclk = 0;
885 		mmc->actual_clock = 0;
886 		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
887 		return;
888 	}
889 
890 	flags = readl(host->base + MSDC_INTEN);
891 	sdr_clr_bits(host->base + MSDC_INTEN, flags);
892 	if (host->dev_comp->clk_div_bits == 8)
893 		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
894 	else
895 		sdr_clr_bits(host->base + MSDC_CFG,
896 			     MSDC_CFG_HS400_CK_MODE_EXTRA);
897 	if (timing == MMC_TIMING_UHS_DDR50 ||
898 	    timing == MMC_TIMING_MMC_DDR52 ||
899 	    timing == MMC_TIMING_MMC_HS400) {
900 		if (timing == MMC_TIMING_MMC_HS400)
901 			mode = 0x3;
902 		else
903 			mode = 0x2; /* ddr mode and use divisor */
904 
905 		if (hz >= (host->src_clk_freq >> 2)) {
906 			div = 0; /* mean div = 1/4 */
907 			sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
908 		} else {
909 			div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
910 			sclk = (host->src_clk_freq >> 2) / div;
911 			div = (div >> 1);
912 		}
913 
914 		if (timing == MMC_TIMING_MMC_HS400 &&
915 		    hz >= (host->src_clk_freq >> 1)) {
916 			if (host->dev_comp->clk_div_bits == 8)
917 				sdr_set_bits(host->base + MSDC_CFG,
918 					     MSDC_CFG_HS400_CK_MODE);
919 			else
920 				sdr_set_bits(host->base + MSDC_CFG,
921 					     MSDC_CFG_HS400_CK_MODE_EXTRA);
922 			sclk = host->src_clk_freq >> 1;
923 			div = 0; /* div is ignore when bit18 is set */
924 		}
925 	} else if (hz >= host->src_clk_freq) {
926 		mode = 0x1; /* no divisor */
927 		div = 0;
928 		sclk = host->src_clk_freq;
929 	} else {
930 		mode = 0x0; /* use divisor */
931 		if (hz >= (host->src_clk_freq >> 1)) {
932 			div = 0; /* mean div = 1/2 */
933 			sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
934 		} else {
935 			div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
936 			sclk = (host->src_clk_freq >> 2) / div;
937 		}
938 	}
939 	sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
940 
941 	clk_disable_unprepare(host->src_clk_cg);
942 	if (host->dev_comp->clk_div_bits == 8)
943 		sdr_set_field(host->base + MSDC_CFG,
944 			      MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
945 			      (mode << 8) | div);
946 	else
947 		sdr_set_field(host->base + MSDC_CFG,
948 			      MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
949 			      (mode << 12) | div);
950 
951 	clk_prepare_enable(host->src_clk_cg);
952 	readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0);
953 	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
954 	mmc->actual_clock = sclk;
955 	host->mclk = hz;
956 	host->timing = timing;
957 	/* need because clk changed. */
958 	msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
959 	sdr_set_bits(host->base + MSDC_INTEN, flags);
960 
961 	/*
962 	 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
963 	 * tune result of hs200/200Mhz is not suitable for 50Mhz
964 	 */
965 	if (mmc->actual_clock <= 52000000) {
966 		writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
967 		if (host->top_base) {
968 			writel(host->def_tune_para.emmc_top_control,
969 			       host->top_base + EMMC_TOP_CONTROL);
970 			writel(host->def_tune_para.emmc_top_cmd,
971 			       host->top_base + EMMC_TOP_CMD);
972 		} else {
973 			writel(host->def_tune_para.pad_tune,
974 			       host->base + tune_reg);
975 		}
976 	} else {
977 		writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
978 		writel(host->saved_tune_para.pad_cmd_tune,
979 		       host->base + PAD_CMD_TUNE);
980 		if (host->top_base) {
981 			writel(host->saved_tune_para.emmc_top_control,
982 			       host->top_base + EMMC_TOP_CONTROL);
983 			writel(host->saved_tune_para.emmc_top_cmd,
984 			       host->top_base + EMMC_TOP_CMD);
985 		} else {
986 			writel(host->saved_tune_para.pad_tune,
987 			       host->base + tune_reg);
988 		}
989 	}
990 
991 	if (timing == MMC_TIMING_MMC_HS400 &&
992 	    host->dev_comp->hs400_tune)
993 		sdr_set_field(host->base + tune_reg,
994 			      MSDC_PAD_TUNE_CMDRRDLY,
995 			      host->hs400_cmd_int_delay);
996 	dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock,
997 		timing);
998 }
999 
msdc_cmd_find_resp(struct msdc_host * host,struct mmc_command * cmd)1000 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
1001 		struct mmc_command *cmd)
1002 {
1003 	u32 resp;
1004 
1005 	switch (mmc_resp_type(cmd)) {
1006 		/* Actually, R1, R5, R6, R7 are the same */
1007 	case MMC_RSP_R1:
1008 		resp = 0x1;
1009 		break;
1010 	case MMC_RSP_R1B:
1011 		resp = 0x7;
1012 		break;
1013 	case MMC_RSP_R2:
1014 		resp = 0x2;
1015 		break;
1016 	case MMC_RSP_R3:
1017 		resp = 0x3;
1018 		break;
1019 	case MMC_RSP_NONE:
1020 	default:
1021 		resp = 0x0;
1022 		break;
1023 	}
1024 
1025 	return resp;
1026 }
1027 
msdc_cmd_prepare_raw_cmd(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1028 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
1029 		struct mmc_request *mrq, struct mmc_command *cmd)
1030 {
1031 	struct mmc_host *mmc = mmc_from_priv(host);
1032 	/* rawcmd :
1033 	 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
1034 	 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
1035 	 */
1036 	u32 opcode = cmd->opcode;
1037 	u32 resp = msdc_cmd_find_resp(host, cmd);
1038 	u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
1039 
1040 	host->cmd_rsp = resp;
1041 
1042 	if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
1043 	    opcode == MMC_STOP_TRANSMISSION)
1044 		rawcmd |= BIT(14);
1045 	else if (opcode == SD_SWITCH_VOLTAGE)
1046 		rawcmd |= BIT(30);
1047 	else if (opcode == SD_APP_SEND_SCR ||
1048 		 opcode == SD_APP_SEND_NUM_WR_BLKS ||
1049 		 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1050 		 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1051 		 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
1052 		rawcmd |= BIT(11);
1053 
1054 	if (cmd->data) {
1055 		struct mmc_data *data = cmd->data;
1056 
1057 		if (mmc_op_multi(opcode)) {
1058 			if (mmc_card_mmc(mmc->card) && mrq->sbc &&
1059 			    !(mrq->sbc->arg & 0xFFFF0000))
1060 				rawcmd |= BIT(29); /* AutoCMD23 */
1061 		}
1062 
1063 		rawcmd |= ((data->blksz & 0xFFF) << 16);
1064 		if (data->flags & MMC_DATA_WRITE)
1065 			rawcmd |= BIT(13);
1066 		if (data->blocks > 1)
1067 			rawcmd |= BIT(12);
1068 		else
1069 			rawcmd |= BIT(11);
1070 		/* Always use dma mode */
1071 		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
1072 
1073 		if (host->timeout_ns != data->timeout_ns ||
1074 		    host->timeout_clks != data->timeout_clks)
1075 			msdc_set_timeout(host, data->timeout_ns,
1076 					data->timeout_clks);
1077 
1078 		writel(data->blocks, host->base + SDC_BLK_NUM);
1079 	}
1080 	return rawcmd;
1081 }
1082 
msdc_start_data(struct msdc_host * host,struct mmc_command * cmd,struct mmc_data * data)1083 static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd,
1084 		struct mmc_data *data)
1085 {
1086 	bool read;
1087 
1088 	WARN_ON(host->data);
1089 	host->data = data;
1090 	read = data->flags & MMC_DATA_READ;
1091 
1092 	mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1093 	msdc_dma_setup(host, &host->dma, data);
1094 	sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
1095 	sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
1096 	dev_dbg(host->dev, "DMA start\n");
1097 	dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
1098 			__func__, cmd->opcode, data->blocks, read);
1099 }
1100 
msdc_auto_cmd_done(struct msdc_host * host,int events,struct mmc_command * cmd)1101 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
1102 		struct mmc_command *cmd)
1103 {
1104 	u32 *rsp = cmd->resp;
1105 
1106 	rsp[0] = readl(host->base + SDC_ACMD_RESP);
1107 
1108 	if (events & MSDC_INT_ACMDRDY) {
1109 		cmd->error = 0;
1110 	} else {
1111 		msdc_reset_hw(host);
1112 		if (events & MSDC_INT_ACMDCRCERR) {
1113 			cmd->error = -EILSEQ;
1114 			host->error |= REQ_STOP_EIO;
1115 		} else if (events & MSDC_INT_ACMDTMO) {
1116 			cmd->error = -ETIMEDOUT;
1117 			host->error |= REQ_STOP_TMO;
1118 		}
1119 		dev_err(host->dev,
1120 			"%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
1121 			__func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
1122 	}
1123 	return cmd->error;
1124 }
1125 
1126 /*
1127  * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost
1128  *
1129  * Host controller may lost interrupt in some special case.
1130  * Add SDIO irq recheck mechanism to make sure all interrupts
1131  * can be processed immediately
1132  */
msdc_recheck_sdio_irq(struct msdc_host * host)1133 static void msdc_recheck_sdio_irq(struct msdc_host *host)
1134 {
1135 	struct mmc_host *mmc = mmc_from_priv(host);
1136 	u32 reg_int, reg_inten, reg_ps;
1137 
1138 	if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1139 		reg_inten = readl(host->base + MSDC_INTEN);
1140 		if (reg_inten & MSDC_INTEN_SDIOIRQ) {
1141 			reg_int = readl(host->base + MSDC_INT);
1142 			reg_ps = readl(host->base + MSDC_PS);
1143 			if (!(reg_int & MSDC_INT_SDIOIRQ ||
1144 			      reg_ps & MSDC_PS_DATA1)) {
1145 				__msdc_enable_sdio_irq(host, 0);
1146 				sdio_signal_irq(mmc);
1147 			}
1148 		}
1149 	}
1150 }
1151 
msdc_track_cmd_data(struct msdc_host * host,struct mmc_command * cmd)1152 static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd)
1153 {
1154 	if (host->error)
1155 		dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
1156 			__func__, cmd->opcode, cmd->arg, host->error);
1157 }
1158 
msdc_request_done(struct msdc_host * host,struct mmc_request * mrq)1159 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
1160 {
1161 	unsigned long flags;
1162 
1163 	/*
1164 	 * No need check the return value of cancel_delayed_work, as only ONE
1165 	 * path will go here!
1166 	 */
1167 	cancel_delayed_work(&host->req_timeout);
1168 
1169 	spin_lock_irqsave(&host->lock, flags);
1170 	host->mrq = NULL;
1171 	spin_unlock_irqrestore(&host->lock, flags);
1172 
1173 	msdc_track_cmd_data(host, mrq->cmd);
1174 	if (mrq->data)
1175 		msdc_unprepare_data(host, mrq->data);
1176 	if (host->error)
1177 		msdc_reset_hw(host);
1178 	mmc_request_done(mmc_from_priv(host), mrq);
1179 	if (host->dev_comp->recheck_sdio_irq)
1180 		msdc_recheck_sdio_irq(host);
1181 }
1182 
1183 /* returns true if command is fully handled; returns false otherwise */
msdc_cmd_done(struct msdc_host * host,int events,struct mmc_request * mrq,struct mmc_command * cmd)1184 static bool msdc_cmd_done(struct msdc_host *host, int events,
1185 			  struct mmc_request *mrq, struct mmc_command *cmd)
1186 {
1187 	bool done = false;
1188 	bool sbc_error;
1189 	unsigned long flags;
1190 	u32 *rsp;
1191 
1192 	if (mrq->sbc && cmd == mrq->cmd &&
1193 	    (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
1194 				   | MSDC_INT_ACMDTMO)))
1195 		msdc_auto_cmd_done(host, events, mrq->sbc);
1196 
1197 	sbc_error = mrq->sbc && mrq->sbc->error;
1198 
1199 	if (!sbc_error && !(events & (MSDC_INT_CMDRDY
1200 					| MSDC_INT_RSPCRCERR
1201 					| MSDC_INT_CMDTMO)))
1202 		return done;
1203 
1204 	spin_lock_irqsave(&host->lock, flags);
1205 	done = !host->cmd;
1206 	host->cmd = NULL;
1207 	spin_unlock_irqrestore(&host->lock, flags);
1208 
1209 	if (done)
1210 		return true;
1211 	rsp = cmd->resp;
1212 
1213 	sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1214 
1215 	if (cmd->flags & MMC_RSP_PRESENT) {
1216 		if (cmd->flags & MMC_RSP_136) {
1217 			rsp[0] = readl(host->base + SDC_RESP3);
1218 			rsp[1] = readl(host->base + SDC_RESP2);
1219 			rsp[2] = readl(host->base + SDC_RESP1);
1220 			rsp[3] = readl(host->base + SDC_RESP0);
1221 		} else {
1222 			rsp[0] = readl(host->base + SDC_RESP0);
1223 		}
1224 	}
1225 
1226 	if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
1227 		if ((events & MSDC_INT_CMDTMO && !host->hs400_tuning) ||
1228 		    (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning))
1229 			/*
1230 			 * should not clear fifo/interrupt as the tune data
1231 			 * may have already come when cmd19/cmd21 gets response
1232 			 * CRC error.
1233 			 */
1234 			msdc_reset_hw(host);
1235 		if (events & MSDC_INT_RSPCRCERR) {
1236 			cmd->error = -EILSEQ;
1237 			host->error |= REQ_CMD_EIO;
1238 		} else if (events & MSDC_INT_CMDTMO) {
1239 			cmd->error = -ETIMEDOUT;
1240 			host->error |= REQ_CMD_TMO;
1241 		}
1242 	}
1243 	if (cmd->error)
1244 		dev_dbg(host->dev,
1245 				"%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
1246 				__func__, cmd->opcode, cmd->arg, rsp[0],
1247 				cmd->error);
1248 
1249 	msdc_cmd_next(host, mrq, cmd);
1250 	return true;
1251 }
1252 
1253 /* It is the core layer's responsibility to ensure card status
1254  * is correct before issue a request. but host design do below
1255  * checks recommended.
1256  */
msdc_cmd_is_ready(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1257 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
1258 		struct mmc_request *mrq, struct mmc_command *cmd)
1259 {
1260 	u32 val;
1261 	int ret;
1262 
1263 	/* The max busy time we can endure is 20ms */
1264 	ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1265 					!(val & SDC_STS_CMDBUSY), 1, 20000);
1266 	if (ret) {
1267 		dev_err(host->dev, "CMD bus busy detected\n");
1268 		host->error |= REQ_CMD_BUSY;
1269 		msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1270 		return false;
1271 	}
1272 
1273 	if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
1274 		/* R1B or with data, should check SDCBUSY */
1275 		ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1276 						!(val & SDC_STS_SDCBUSY), 1, 20000);
1277 		if (ret) {
1278 			dev_err(host->dev, "Controller busy detected\n");
1279 			host->error |= REQ_CMD_BUSY;
1280 			msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1281 			return false;
1282 		}
1283 	}
1284 	return true;
1285 }
1286 
msdc_start_command(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1287 static void msdc_start_command(struct msdc_host *host,
1288 		struct mmc_request *mrq, struct mmc_command *cmd)
1289 {
1290 	u32 rawcmd;
1291 	unsigned long flags;
1292 
1293 	WARN_ON(host->cmd);
1294 	host->cmd = cmd;
1295 
1296 	mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1297 	if (!msdc_cmd_is_ready(host, mrq, cmd))
1298 		return;
1299 
1300 	if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1301 	    readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1302 		dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
1303 		msdc_reset_hw(host);
1304 	}
1305 
1306 	cmd->error = 0;
1307 	rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
1308 
1309 	spin_lock_irqsave(&host->lock, flags);
1310 	sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1311 	spin_unlock_irqrestore(&host->lock, flags);
1312 
1313 	writel(cmd->arg, host->base + SDC_ARG);
1314 	writel(rawcmd, host->base + SDC_CMD);
1315 }
1316 
msdc_cmd_next(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1317 static void msdc_cmd_next(struct msdc_host *host,
1318 		struct mmc_request *mrq, struct mmc_command *cmd)
1319 {
1320 	if ((cmd->error && !host->hs400_tuning &&
1321 	     !(cmd->error == -EILSEQ &&
1322 	     mmc_op_tuning(cmd->opcode))) ||
1323 	    (mrq->sbc && mrq->sbc->error))
1324 		msdc_request_done(host, mrq);
1325 	else if (cmd == mrq->sbc)
1326 		msdc_start_command(host, mrq, mrq->cmd);
1327 	else if (!cmd->data)
1328 		msdc_request_done(host, mrq);
1329 	else
1330 		msdc_start_data(host, cmd, cmd->data);
1331 }
1332 
msdc_ops_request(struct mmc_host * mmc,struct mmc_request * mrq)1333 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1334 {
1335 	struct msdc_host *host = mmc_priv(mmc);
1336 
1337 	host->error = 0;
1338 	WARN_ON(host->mrq);
1339 	host->mrq = mrq;
1340 
1341 	if (mrq->data)
1342 		msdc_prepare_data(host, mrq->data);
1343 
1344 	/* if SBC is required, we have HW option and SW option.
1345 	 * if HW option is enabled, and SBC does not have "special" flags,
1346 	 * use HW option,  otherwise use SW option
1347 	 */
1348 	if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
1349 	    (mrq->sbc->arg & 0xFFFF0000)))
1350 		msdc_start_command(host, mrq, mrq->sbc);
1351 	else
1352 		msdc_start_command(host, mrq, mrq->cmd);
1353 }
1354 
msdc_pre_req(struct mmc_host * mmc,struct mmc_request * mrq)1355 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1356 {
1357 	struct msdc_host *host = mmc_priv(mmc);
1358 	struct mmc_data *data = mrq->data;
1359 
1360 	if (!data)
1361 		return;
1362 
1363 	msdc_prepare_data(host, data);
1364 	data->host_cookie |= MSDC_ASYNC_FLAG;
1365 }
1366 
msdc_post_req(struct mmc_host * mmc,struct mmc_request * mrq,int err)1367 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1368 		int err)
1369 {
1370 	struct msdc_host *host = mmc_priv(mmc);
1371 	struct mmc_data *data = mrq->data;
1372 
1373 	if (!data)
1374 		return;
1375 
1376 	if (data->host_cookie) {
1377 		data->host_cookie &= ~MSDC_ASYNC_FLAG;
1378 		msdc_unprepare_data(host, data);
1379 	}
1380 }
1381 
msdc_data_xfer_next(struct msdc_host * host,struct mmc_request * mrq)1382 static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq)
1383 {
1384 	if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
1385 	    !mrq->sbc)
1386 		msdc_start_command(host, mrq, mrq->stop);
1387 	else
1388 		msdc_request_done(host, mrq);
1389 }
1390 
msdc_data_xfer_done(struct msdc_host * host,u32 events,struct mmc_request * mrq,struct mmc_data * data)1391 static void msdc_data_xfer_done(struct msdc_host *host, u32 events,
1392 				struct mmc_request *mrq, struct mmc_data *data)
1393 {
1394 	struct mmc_command *stop;
1395 	unsigned long flags;
1396 	bool done;
1397 	unsigned int check_data = events &
1398 	    (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
1399 	     | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
1400 	     | MSDC_INT_DMA_PROTECT);
1401 	u32 val;
1402 	int ret;
1403 
1404 	spin_lock_irqsave(&host->lock, flags);
1405 	done = !host->data;
1406 	if (check_data)
1407 		host->data = NULL;
1408 	spin_unlock_irqrestore(&host->lock, flags);
1409 
1410 	if (done)
1411 		return;
1412 	stop = data->stop;
1413 
1414 	if (check_data || (stop && stop->error)) {
1415 		dev_dbg(host->dev, "DMA status: 0x%8X\n",
1416 				readl(host->base + MSDC_DMA_CFG));
1417 		sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1418 				1);
1419 
1420 		ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val,
1421 						!(val & MSDC_DMA_CTRL_STOP), 1, 20000);
1422 		if (ret)
1423 			dev_dbg(host->dev, "DMA stop timed out\n");
1424 
1425 		ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val,
1426 						!(val & MSDC_DMA_CFG_STS), 1, 20000);
1427 		if (ret)
1428 			dev_dbg(host->dev, "DMA inactive timed out\n");
1429 
1430 		sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1431 		dev_dbg(host->dev, "DMA stop\n");
1432 
1433 		if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
1434 			data->bytes_xfered = data->blocks * data->blksz;
1435 		} else {
1436 			dev_dbg(host->dev, "interrupt events: %x\n", events);
1437 			msdc_reset_hw(host);
1438 			host->error |= REQ_DAT_ERR;
1439 			data->bytes_xfered = 0;
1440 
1441 			if (events & MSDC_INT_DATTMO)
1442 				data->error = -ETIMEDOUT;
1443 			else if (events & MSDC_INT_DATCRCERR)
1444 				data->error = -EILSEQ;
1445 
1446 			dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1447 				__func__, mrq->cmd->opcode, data->blocks);
1448 			dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1449 				(int)data->error, data->bytes_xfered);
1450 		}
1451 
1452 		msdc_data_xfer_next(host, mrq);
1453 	}
1454 }
1455 
msdc_set_buswidth(struct msdc_host * host,u32 width)1456 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1457 {
1458 	u32 val = readl(host->base + SDC_CFG);
1459 
1460 	val &= ~SDC_CFG_BUSWIDTH;
1461 
1462 	switch (width) {
1463 	default:
1464 	case MMC_BUS_WIDTH_1:
1465 		val |= (MSDC_BUS_1BITS << 16);
1466 		break;
1467 	case MMC_BUS_WIDTH_4:
1468 		val |= (MSDC_BUS_4BITS << 16);
1469 		break;
1470 	case MMC_BUS_WIDTH_8:
1471 		val |= (MSDC_BUS_8BITS << 16);
1472 		break;
1473 	}
1474 
1475 	writel(val, host->base + SDC_CFG);
1476 	dev_dbg(host->dev, "Bus Width = %d", width);
1477 }
1478 
msdc_ops_switch_volt(struct mmc_host * mmc,struct mmc_ios * ios)1479 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1480 {
1481 	struct msdc_host *host = mmc_priv(mmc);
1482 	int ret;
1483 
1484 	if (!IS_ERR(mmc->supply.vqmmc)) {
1485 		if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
1486 		    ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
1487 			dev_err(host->dev, "Unsupported signal voltage!\n");
1488 			return -EINVAL;
1489 		}
1490 
1491 		ret = mmc_regulator_set_vqmmc(mmc, ios);
1492 		if (ret < 0) {
1493 			dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1494 				ret, ios->signal_voltage);
1495 			return ret;
1496 		}
1497 
1498 		/* Apply different pinctrl settings for different signal voltage */
1499 		if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1500 			pinctrl_select_state(host->pinctrl, host->pins_uhs);
1501 		else
1502 			pinctrl_select_state(host->pinctrl, host->pins_default);
1503 	}
1504 	return 0;
1505 }
1506 
msdc_card_busy(struct mmc_host * mmc)1507 static int msdc_card_busy(struct mmc_host *mmc)
1508 {
1509 	struct msdc_host *host = mmc_priv(mmc);
1510 	u32 status = readl(host->base + MSDC_PS);
1511 
1512 	/* only check if data0 is low */
1513 	return !(status & BIT(16));
1514 }
1515 
msdc_request_timeout(struct work_struct * work)1516 static void msdc_request_timeout(struct work_struct *work)
1517 {
1518 	struct msdc_host *host = container_of(work, struct msdc_host,
1519 			req_timeout.work);
1520 
1521 	/* simulate HW timeout status */
1522 	dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1523 	if (host->mrq) {
1524 		dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1525 				host->mrq, host->mrq->cmd->opcode);
1526 		if (host->cmd) {
1527 			dev_err(host->dev, "%s: aborting cmd=%d\n",
1528 					__func__, host->cmd->opcode);
1529 			msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1530 					host->cmd);
1531 		} else if (host->data) {
1532 			dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1533 					__func__, host->mrq->cmd->opcode,
1534 					host->data->blocks);
1535 			msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1536 					host->data);
1537 		}
1538 	}
1539 }
1540 
__msdc_enable_sdio_irq(struct msdc_host * host,int enb)1541 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb)
1542 {
1543 	if (enb) {
1544 		sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1545 		sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1546 		if (host->dev_comp->recheck_sdio_irq)
1547 			msdc_recheck_sdio_irq(host);
1548 	} else {
1549 		sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1550 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1551 	}
1552 }
1553 
msdc_enable_sdio_irq(struct mmc_host * mmc,int enb)1554 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb)
1555 {
1556 	struct msdc_host *host = mmc_priv(mmc);
1557 	unsigned long flags;
1558 	int ret;
1559 
1560 	spin_lock_irqsave(&host->lock, flags);
1561 	__msdc_enable_sdio_irq(host, enb);
1562 	spin_unlock_irqrestore(&host->lock, flags);
1563 
1564 	if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) {
1565 		if (enb) {
1566 			/*
1567 			 * In dev_pm_set_dedicated_wake_irq_reverse(), eint pin will be set to
1568 			 * GPIO mode. We need to restore it to SDIO DAT1 mode after that.
1569 			 * Since the current pinstate is pins_uhs, to ensure pinctrl select take
1570 			 * affect successfully, we change the pinstate to pins_eint firstly.
1571 			 */
1572 			pinctrl_select_state(host->pinctrl, host->pins_eint);
1573 			ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq);
1574 
1575 			if (ret) {
1576 				dev_err(host->dev, "Failed to register SDIO wakeup irq!\n");
1577 				host->pins_eint = NULL;
1578 				pm_runtime_get_noresume(host->dev);
1579 			} else {
1580 				dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq);
1581 			}
1582 
1583 			pinctrl_select_state(host->pinctrl, host->pins_uhs);
1584 		} else {
1585 			dev_pm_clear_wake_irq(host->dev);
1586 		}
1587 	} else {
1588 		if (enb) {
1589 			/* Ensure host->pins_eint is NULL */
1590 			host->pins_eint = NULL;
1591 			pm_runtime_get_noresume(host->dev);
1592 		} else {
1593 			pm_runtime_put_noidle(host->dev);
1594 		}
1595 	}
1596 }
1597 
msdc_cmdq_irq(struct msdc_host * host,u32 intsts)1598 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts)
1599 {
1600 	struct mmc_host *mmc = mmc_from_priv(host);
1601 	int cmd_err = 0, dat_err = 0;
1602 
1603 	if (intsts & MSDC_INT_RSPCRCERR) {
1604 		cmd_err = -EILSEQ;
1605 		dev_err(host->dev, "%s: CMD CRC ERR", __func__);
1606 	} else if (intsts & MSDC_INT_CMDTMO) {
1607 		cmd_err = -ETIMEDOUT;
1608 		dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__);
1609 	}
1610 
1611 	if (intsts & MSDC_INT_DATCRCERR) {
1612 		dat_err = -EILSEQ;
1613 		dev_err(host->dev, "%s: DATA CRC ERR", __func__);
1614 	} else if (intsts & MSDC_INT_DATTMO) {
1615 		dat_err = -ETIMEDOUT;
1616 		dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__);
1617 	}
1618 
1619 	if (cmd_err || dat_err) {
1620 		dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x",
1621 			cmd_err, dat_err, intsts);
1622 	}
1623 
1624 	return cqhci_irq(mmc, 0, cmd_err, dat_err);
1625 }
1626 
msdc_irq(int irq,void * dev_id)1627 static irqreturn_t msdc_irq(int irq, void *dev_id)
1628 {
1629 	struct msdc_host *host = (struct msdc_host *) dev_id;
1630 	struct mmc_host *mmc = mmc_from_priv(host);
1631 
1632 	while (true) {
1633 		struct mmc_request *mrq;
1634 		struct mmc_command *cmd;
1635 		struct mmc_data *data;
1636 		u32 events, event_mask;
1637 
1638 		spin_lock(&host->lock);
1639 		events = readl(host->base + MSDC_INT);
1640 		event_mask = readl(host->base + MSDC_INTEN);
1641 		if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1642 			__msdc_enable_sdio_irq(host, 0);
1643 		/* clear interrupts */
1644 		writel(events & event_mask, host->base + MSDC_INT);
1645 
1646 		mrq = host->mrq;
1647 		cmd = host->cmd;
1648 		data = host->data;
1649 		spin_unlock(&host->lock);
1650 
1651 		if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1652 			sdio_signal_irq(mmc);
1653 
1654 		if ((events & event_mask) & MSDC_INT_CDSC) {
1655 			if (host->internal_cd)
1656 				mmc_detect_change(mmc, msecs_to_jiffies(20));
1657 			events &= ~MSDC_INT_CDSC;
1658 		}
1659 
1660 		if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ)))
1661 			break;
1662 
1663 		if ((mmc->caps2 & MMC_CAP2_CQE) &&
1664 		    (events & MSDC_INT_CMDQ)) {
1665 			msdc_cmdq_irq(host, events);
1666 			/* clear interrupts */
1667 			writel(events, host->base + MSDC_INT);
1668 			return IRQ_HANDLED;
1669 		}
1670 
1671 		if (!mrq) {
1672 			dev_err(host->dev,
1673 				"%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1674 				__func__, events, event_mask);
1675 			WARN_ON(1);
1676 			break;
1677 		}
1678 
1679 		dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1680 
1681 		if (cmd)
1682 			msdc_cmd_done(host, events, mrq, cmd);
1683 		else if (data)
1684 			msdc_data_xfer_done(host, events, mrq, data);
1685 	}
1686 
1687 	return IRQ_HANDLED;
1688 }
1689 
msdc_init_hw(struct msdc_host * host)1690 static void msdc_init_hw(struct msdc_host *host)
1691 {
1692 	u32 val;
1693 	u32 tune_reg = host->dev_comp->pad_tune_reg;
1694 	struct mmc_host *mmc = mmc_from_priv(host);
1695 
1696 	if (host->reset) {
1697 		reset_control_assert(host->reset);
1698 		usleep_range(10, 50);
1699 		reset_control_deassert(host->reset);
1700 	}
1701 
1702 	/* Configure to MMC/SD mode, clock free running */
1703 	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1704 
1705 	/* Reset */
1706 	msdc_reset_hw(host);
1707 
1708 	/* Disable and clear all interrupts */
1709 	writel(0, host->base + MSDC_INTEN);
1710 	val = readl(host->base + MSDC_INT);
1711 	writel(val, host->base + MSDC_INT);
1712 
1713 	/* Configure card detection */
1714 	if (host->internal_cd) {
1715 		sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1716 			      DEFAULT_DEBOUNCE);
1717 		sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1718 		sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1719 		sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1720 	} else {
1721 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1722 		sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1723 		sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1724 	}
1725 
1726 	if (host->top_base) {
1727 		writel(0, host->top_base + EMMC_TOP_CONTROL);
1728 		writel(0, host->top_base + EMMC_TOP_CMD);
1729 	} else {
1730 		writel(0, host->base + tune_reg);
1731 	}
1732 	writel(0, host->base + MSDC_IOCON);
1733 	sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1734 	writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1735 	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1736 	writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
1737 	sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1738 
1739 	if (host->dev_comp->stop_clk_fix) {
1740 		sdr_set_field(host->base + MSDC_PATCH_BIT1,
1741 			      MSDC_PATCH_BIT1_STOP_DLY, 3);
1742 		sdr_clr_bits(host->base + SDC_FIFO_CFG,
1743 			     SDC_FIFO_CFG_WRVALIDSEL);
1744 		sdr_clr_bits(host->base + SDC_FIFO_CFG,
1745 			     SDC_FIFO_CFG_RDVALIDSEL);
1746 	}
1747 
1748 	if (host->dev_comp->busy_check)
1749 		sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7));
1750 
1751 	if (host->dev_comp->async_fifo) {
1752 		sdr_set_field(host->base + MSDC_PATCH_BIT2,
1753 			      MSDC_PB2_RESPWAIT, 3);
1754 		if (host->dev_comp->enhance_rx) {
1755 			if (host->top_base)
1756 				sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1757 					     SDC_RX_ENH_EN);
1758 			else
1759 				sdr_set_bits(host->base + SDC_ADV_CFG0,
1760 					     SDC_RX_ENHANCE_EN);
1761 		} else {
1762 			sdr_set_field(host->base + MSDC_PATCH_BIT2,
1763 				      MSDC_PB2_RESPSTSENSEL, 2);
1764 			sdr_set_field(host->base + MSDC_PATCH_BIT2,
1765 				      MSDC_PB2_CRCSTSENSEL, 2);
1766 		}
1767 		/* use async fifo, then no need tune internal delay */
1768 		sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
1769 			     MSDC_PATCH_BIT2_CFGRESP);
1770 		sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1771 			     MSDC_PATCH_BIT2_CFGCRCSTS);
1772 	}
1773 
1774 	if (host->dev_comp->support_64g)
1775 		sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1776 			     MSDC_PB2_SUPPORT_64G);
1777 	if (host->dev_comp->data_tune) {
1778 		if (host->top_base) {
1779 			sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1780 				     PAD_DAT_RD_RXDLY_SEL);
1781 			sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
1782 				     DATA_K_VALUE_SEL);
1783 			sdr_set_bits(host->top_base + EMMC_TOP_CMD,
1784 				     PAD_CMD_RD_RXDLY_SEL);
1785 		} else {
1786 			sdr_set_bits(host->base + tune_reg,
1787 				     MSDC_PAD_TUNE_RD_SEL |
1788 				     MSDC_PAD_TUNE_CMD_SEL);
1789 		}
1790 	} else {
1791 		/* choose clock tune */
1792 		if (host->top_base)
1793 			sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1794 				     PAD_RXDLY_SEL);
1795 		else
1796 			sdr_set_bits(host->base + tune_reg,
1797 				     MSDC_PAD_TUNE_RXDLYSEL);
1798 	}
1799 
1800 	if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
1801 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1802 		sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1803 		sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1804 	} else {
1805 		/* Configure to enable SDIO mode, otherwise SDIO CMD5 fails */
1806 		sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1807 
1808 		/* Config SDIO device detect interrupt function */
1809 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1810 		sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1811 	}
1812 
1813 	/* Configure to default data timeout */
1814 	sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1815 
1816 	host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1817 	host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1818 	if (host->top_base) {
1819 		host->def_tune_para.emmc_top_control =
1820 			readl(host->top_base + EMMC_TOP_CONTROL);
1821 		host->def_tune_para.emmc_top_cmd =
1822 			readl(host->top_base + EMMC_TOP_CMD);
1823 		host->saved_tune_para.emmc_top_control =
1824 			readl(host->top_base + EMMC_TOP_CONTROL);
1825 		host->saved_tune_para.emmc_top_cmd =
1826 			readl(host->top_base + EMMC_TOP_CMD);
1827 	} else {
1828 		host->def_tune_para.pad_tune = readl(host->base + tune_reg);
1829 		host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1830 	}
1831 	dev_dbg(host->dev, "init hardware done!");
1832 }
1833 
msdc_deinit_hw(struct msdc_host * host)1834 static void msdc_deinit_hw(struct msdc_host *host)
1835 {
1836 	u32 val;
1837 
1838 	if (host->internal_cd) {
1839 		/* Disabled card-detect */
1840 		sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1841 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1842 	}
1843 
1844 	/* Disable and clear all interrupts */
1845 	writel(0, host->base + MSDC_INTEN);
1846 
1847 	val = readl(host->base + MSDC_INT);
1848 	writel(val, host->base + MSDC_INT);
1849 }
1850 
1851 /* init gpd and bd list in msdc_drv_probe */
msdc_init_gpd_bd(struct msdc_host * host,struct msdc_dma * dma)1852 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1853 {
1854 	struct mt_gpdma_desc *gpd = dma->gpd;
1855 	struct mt_bdma_desc *bd = dma->bd;
1856 	dma_addr_t dma_addr;
1857 	int i;
1858 
1859 	memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
1860 
1861 	dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc);
1862 	gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1863 	/* gpd->next is must set for desc DMA
1864 	 * That's why must alloc 2 gpd structure.
1865 	 */
1866 	gpd->next = lower_32_bits(dma_addr);
1867 	if (host->dev_comp->support_64g)
1868 		gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1869 
1870 	dma_addr = dma->bd_addr;
1871 	gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */
1872 	if (host->dev_comp->support_64g)
1873 		gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28;
1874 
1875 	memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1876 	for (i = 0; i < (MAX_BD_NUM - 1); i++) {
1877 		dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1);
1878 		bd[i].next = lower_32_bits(dma_addr);
1879 		if (host->dev_comp->support_64g)
1880 			bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1881 	}
1882 }
1883 
msdc_ops_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)1884 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1885 {
1886 	struct msdc_host *host = mmc_priv(mmc);
1887 	int ret;
1888 
1889 	msdc_set_buswidth(host, ios->bus_width);
1890 
1891 	/* Suspend/Resume will do power off/on */
1892 	switch (ios->power_mode) {
1893 	case MMC_POWER_UP:
1894 		if (!IS_ERR(mmc->supply.vmmc)) {
1895 			msdc_init_hw(host);
1896 			ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1897 					ios->vdd);
1898 			if (ret) {
1899 				dev_err(host->dev, "Failed to set vmmc power!\n");
1900 				return;
1901 			}
1902 		}
1903 		break;
1904 	case MMC_POWER_ON:
1905 		if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1906 			ret = regulator_enable(mmc->supply.vqmmc);
1907 			if (ret)
1908 				dev_err(host->dev, "Failed to set vqmmc power!\n");
1909 			else
1910 				host->vqmmc_enabled = true;
1911 		}
1912 		break;
1913 	case MMC_POWER_OFF:
1914 		if (!IS_ERR(mmc->supply.vmmc))
1915 			mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1916 
1917 		if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1918 			regulator_disable(mmc->supply.vqmmc);
1919 			host->vqmmc_enabled = false;
1920 		}
1921 		break;
1922 	default:
1923 		break;
1924 	}
1925 
1926 	if (host->mclk != ios->clock || host->timing != ios->timing)
1927 		msdc_set_mclk(host, ios->timing, ios->clock);
1928 }
1929 
test_delay_bit(u32 delay,u32 bit)1930 static u32 test_delay_bit(u32 delay, u32 bit)
1931 {
1932 	bit %= PAD_DELAY_MAX;
1933 	return delay & BIT(bit);
1934 }
1935 
get_delay_len(u32 delay,u32 start_bit)1936 static int get_delay_len(u32 delay, u32 start_bit)
1937 {
1938 	int i;
1939 
1940 	for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
1941 		if (test_delay_bit(delay, start_bit + i) == 0)
1942 			return i;
1943 	}
1944 	return PAD_DELAY_MAX - start_bit;
1945 }
1946 
get_best_delay(struct msdc_host * host,u32 delay)1947 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
1948 {
1949 	int start = 0, len = 0;
1950 	int start_final = 0, len_final = 0;
1951 	u8 final_phase = 0xff;
1952 	struct msdc_delay_phase delay_phase = { 0, };
1953 
1954 	if (delay == 0) {
1955 		dev_err(host->dev, "phase error: [map:%x]\n", delay);
1956 		delay_phase.final_phase = final_phase;
1957 		return delay_phase;
1958 	}
1959 
1960 	while (start < PAD_DELAY_MAX) {
1961 		len = get_delay_len(delay, start);
1962 		if (len_final < len) {
1963 			start_final = start;
1964 			len_final = len;
1965 		}
1966 		start += len ? len : 1;
1967 		if (len >= 12 && start_final < 4)
1968 			break;
1969 	}
1970 
1971 	/* The rule is that to find the smallest delay cell */
1972 	if (start_final == 0)
1973 		final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
1974 	else
1975 		final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
1976 	dev_dbg(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
1977 		delay, len_final, final_phase);
1978 
1979 	delay_phase.maxlen = len_final;
1980 	delay_phase.start = start_final;
1981 	delay_phase.final_phase = final_phase;
1982 	return delay_phase;
1983 }
1984 
msdc_set_cmd_delay(struct msdc_host * host,u32 value)1985 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
1986 {
1987 	u32 tune_reg = host->dev_comp->pad_tune_reg;
1988 
1989 	if (host->top_base)
1990 		sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
1991 			      value);
1992 	else
1993 		sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
1994 			      value);
1995 }
1996 
msdc_set_data_delay(struct msdc_host * host,u32 value)1997 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
1998 {
1999 	u32 tune_reg = host->dev_comp->pad_tune_reg;
2000 
2001 	if (host->top_base)
2002 		sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2003 			      PAD_DAT_RD_RXDLY, value);
2004 	else
2005 		sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
2006 			      value);
2007 }
2008 
msdc_tune_response(struct mmc_host * mmc,u32 opcode)2009 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
2010 {
2011 	struct msdc_host *host = mmc_priv(mmc);
2012 	u32 rise_delay = 0, fall_delay = 0;
2013 	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2014 	struct msdc_delay_phase internal_delay_phase;
2015 	u8 final_delay, final_maxlen;
2016 	u32 internal_delay = 0;
2017 	u32 tune_reg = host->dev_comp->pad_tune_reg;
2018 	int cmd_err;
2019 	int i, j;
2020 
2021 	if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2022 	    mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2023 		sdr_set_field(host->base + tune_reg,
2024 			      MSDC_PAD_TUNE_CMDRRDLY,
2025 			      host->hs200_cmd_int_delay);
2026 
2027 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2028 	for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2029 		msdc_set_cmd_delay(host, i);
2030 		/*
2031 		 * Using the same parameters, it may sometimes pass the test,
2032 		 * but sometimes it may fail. To make sure the parameters are
2033 		 * more stable, we test each set of parameters 3 times.
2034 		 */
2035 		for (j = 0; j < 3; j++) {
2036 			mmc_send_tuning(mmc, opcode, &cmd_err);
2037 			if (!cmd_err) {
2038 				rise_delay |= BIT(i);
2039 			} else {
2040 				rise_delay &= ~BIT(i);
2041 				break;
2042 			}
2043 		}
2044 	}
2045 	final_rise_delay = get_best_delay(host, rise_delay);
2046 	/* if rising edge has enough margin, then do not scan falling edge */
2047 	if (final_rise_delay.maxlen >= 12 ||
2048 	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2049 		goto skip_fall;
2050 
2051 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2052 	for (i = 0; i < PAD_DELAY_MAX; i++) {
2053 		msdc_set_cmd_delay(host, i);
2054 		/*
2055 		 * Using the same parameters, it may sometimes pass the test,
2056 		 * but sometimes it may fail. To make sure the parameters are
2057 		 * more stable, we test each set of parameters 3 times.
2058 		 */
2059 		for (j = 0; j < 3; j++) {
2060 			mmc_send_tuning(mmc, opcode, &cmd_err);
2061 			if (!cmd_err) {
2062 				fall_delay |= BIT(i);
2063 			} else {
2064 				fall_delay &= ~BIT(i);
2065 				break;
2066 			}
2067 		}
2068 	}
2069 	final_fall_delay = get_best_delay(host, fall_delay);
2070 
2071 skip_fall:
2072 	final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2073 	if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4)
2074 		final_maxlen = final_fall_delay.maxlen;
2075 	if (final_maxlen == final_rise_delay.maxlen) {
2076 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2077 		final_delay = final_rise_delay.final_phase;
2078 	} else {
2079 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2080 		final_delay = final_fall_delay.final_phase;
2081 	}
2082 	msdc_set_cmd_delay(host, final_delay);
2083 
2084 	if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
2085 		goto skip_internal;
2086 
2087 	for (i = 0; i < PAD_DELAY_MAX; i++) {
2088 		sdr_set_field(host->base + tune_reg,
2089 			      MSDC_PAD_TUNE_CMDRRDLY, i);
2090 		mmc_send_tuning(mmc, opcode, &cmd_err);
2091 		if (!cmd_err)
2092 			internal_delay |= BIT(i);
2093 	}
2094 	dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
2095 	internal_delay_phase = get_best_delay(host, internal_delay);
2096 	sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
2097 		      internal_delay_phase.final_phase);
2098 skip_internal:
2099 	dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2100 	return final_delay == 0xff ? -EIO : 0;
2101 }
2102 
hs400_tune_response(struct mmc_host * mmc,u32 opcode)2103 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
2104 {
2105 	struct msdc_host *host = mmc_priv(mmc);
2106 	u32 cmd_delay = 0;
2107 	struct msdc_delay_phase final_cmd_delay = { 0,};
2108 	u8 final_delay;
2109 	int cmd_err;
2110 	int i, j;
2111 
2112 	/* select EMMC50 PAD CMD tune */
2113 	sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
2114 	sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
2115 
2116 	if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2117 	    mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2118 		sdr_set_field(host->base + MSDC_PAD_TUNE,
2119 			      MSDC_PAD_TUNE_CMDRRDLY,
2120 			      host->hs200_cmd_int_delay);
2121 
2122 	if (host->hs400_cmd_resp_sel_rising)
2123 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2124 	else
2125 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2126 	for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2127 		sdr_set_field(host->base + PAD_CMD_TUNE,
2128 			      PAD_CMD_TUNE_RX_DLY3, i);
2129 		/*
2130 		 * Using the same parameters, it may sometimes pass the test,
2131 		 * but sometimes it may fail. To make sure the parameters are
2132 		 * more stable, we test each set of parameters 3 times.
2133 		 */
2134 		for (j = 0; j < 3; j++) {
2135 			mmc_send_tuning(mmc, opcode, &cmd_err);
2136 			if (!cmd_err) {
2137 				cmd_delay |= BIT(i);
2138 			} else {
2139 				cmd_delay &= ~BIT(i);
2140 				break;
2141 			}
2142 		}
2143 	}
2144 	final_cmd_delay = get_best_delay(host, cmd_delay);
2145 	sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
2146 		      final_cmd_delay.final_phase);
2147 	final_delay = final_cmd_delay.final_phase;
2148 
2149 	dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2150 	return final_delay == 0xff ? -EIO : 0;
2151 }
2152 
msdc_tune_data(struct mmc_host * mmc,u32 opcode)2153 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
2154 {
2155 	struct msdc_host *host = mmc_priv(mmc);
2156 	u32 rise_delay = 0, fall_delay = 0;
2157 	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2158 	u8 final_delay, final_maxlen;
2159 	int i, ret;
2160 
2161 	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2162 		      host->latch_ck);
2163 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2164 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2165 	for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2166 		msdc_set_data_delay(host, i);
2167 		ret = mmc_send_tuning(mmc, opcode, NULL);
2168 		if (!ret)
2169 			rise_delay |= BIT(i);
2170 	}
2171 	final_rise_delay = get_best_delay(host, rise_delay);
2172 	/* if rising edge has enough margin, then do not scan falling edge */
2173 	if (final_rise_delay.maxlen >= 12 ||
2174 	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2175 		goto skip_fall;
2176 
2177 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2178 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2179 	for (i = 0; i < PAD_DELAY_MAX; i++) {
2180 		msdc_set_data_delay(host, i);
2181 		ret = mmc_send_tuning(mmc, opcode, NULL);
2182 		if (!ret)
2183 			fall_delay |= BIT(i);
2184 	}
2185 	final_fall_delay = get_best_delay(host, fall_delay);
2186 
2187 skip_fall:
2188 	final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2189 	if (final_maxlen == final_rise_delay.maxlen) {
2190 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2191 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2192 		final_delay = final_rise_delay.final_phase;
2193 	} else {
2194 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2195 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2196 		final_delay = final_fall_delay.final_phase;
2197 	}
2198 	msdc_set_data_delay(host, final_delay);
2199 
2200 	dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
2201 	return final_delay == 0xff ? -EIO : 0;
2202 }
2203 
2204 /*
2205  * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
2206  * together, which can save the tuning time.
2207  */
msdc_tune_together(struct mmc_host * mmc,u32 opcode)2208 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
2209 {
2210 	struct msdc_host *host = mmc_priv(mmc);
2211 	u32 rise_delay = 0, fall_delay = 0;
2212 	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2213 	u8 final_delay, final_maxlen;
2214 	int i, ret;
2215 
2216 	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2217 		      host->latch_ck);
2218 
2219 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2220 	sdr_clr_bits(host->base + MSDC_IOCON,
2221 		     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2222 	for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2223 		msdc_set_cmd_delay(host, i);
2224 		msdc_set_data_delay(host, i);
2225 		ret = mmc_send_tuning(mmc, opcode, NULL);
2226 		if (!ret)
2227 			rise_delay |= BIT(i);
2228 	}
2229 	final_rise_delay = get_best_delay(host, rise_delay);
2230 	/* if rising edge has enough margin, then do not scan falling edge */
2231 	if (final_rise_delay.maxlen >= 12 ||
2232 	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2233 		goto skip_fall;
2234 
2235 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2236 	sdr_set_bits(host->base + MSDC_IOCON,
2237 		     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2238 	for (i = 0; i < PAD_DELAY_MAX; i++) {
2239 		msdc_set_cmd_delay(host, i);
2240 		msdc_set_data_delay(host, i);
2241 		ret = mmc_send_tuning(mmc, opcode, NULL);
2242 		if (!ret)
2243 			fall_delay |= BIT(i);
2244 	}
2245 	final_fall_delay = get_best_delay(host, fall_delay);
2246 
2247 skip_fall:
2248 	final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2249 	if (final_maxlen == final_rise_delay.maxlen) {
2250 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2251 		sdr_clr_bits(host->base + MSDC_IOCON,
2252 			     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2253 		final_delay = final_rise_delay.final_phase;
2254 	} else {
2255 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2256 		sdr_set_bits(host->base + MSDC_IOCON,
2257 			     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2258 		final_delay = final_fall_delay.final_phase;
2259 	}
2260 
2261 	msdc_set_cmd_delay(host, final_delay);
2262 	msdc_set_data_delay(host, final_delay);
2263 
2264 	dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
2265 	return final_delay == 0xff ? -EIO : 0;
2266 }
2267 
msdc_execute_tuning(struct mmc_host * mmc,u32 opcode)2268 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
2269 {
2270 	struct msdc_host *host = mmc_priv(mmc);
2271 	int ret;
2272 	u32 tune_reg = host->dev_comp->pad_tune_reg;
2273 
2274 	if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
2275 		ret = msdc_tune_together(mmc, opcode);
2276 		if (host->hs400_mode) {
2277 			sdr_clr_bits(host->base + MSDC_IOCON,
2278 				     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2279 			msdc_set_data_delay(host, 0);
2280 		}
2281 		goto tune_done;
2282 	}
2283 	if (host->hs400_mode &&
2284 	    host->dev_comp->hs400_tune)
2285 		ret = hs400_tune_response(mmc, opcode);
2286 	else
2287 		ret = msdc_tune_response(mmc, opcode);
2288 	if (ret == -EIO) {
2289 		dev_err(host->dev, "Tune response fail!\n");
2290 		return ret;
2291 	}
2292 	if (host->hs400_mode == false) {
2293 		ret = msdc_tune_data(mmc, opcode);
2294 		if (ret == -EIO)
2295 			dev_err(host->dev, "Tune data fail!\n");
2296 	}
2297 
2298 tune_done:
2299 	host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2300 	host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2301 	host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2302 	if (host->top_base) {
2303 		host->saved_tune_para.emmc_top_control = readl(host->top_base +
2304 				EMMC_TOP_CONTROL);
2305 		host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
2306 				EMMC_TOP_CMD);
2307 	}
2308 	return ret;
2309 }
2310 
msdc_prepare_hs400_tuning(struct mmc_host * mmc,struct mmc_ios * ios)2311 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2312 {
2313 	struct msdc_host *host = mmc_priv(mmc);
2314 
2315 	host->hs400_mode = true;
2316 
2317 	if (host->top_base) {
2318 		if (host->hs400_ds_dly3)
2319 			sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2320 				      PAD_DS_DLY3, host->hs400_ds_dly3);
2321 		if (host->hs400_ds_delay)
2322 			writel(host->hs400_ds_delay,
2323 			       host->top_base + EMMC50_PAD_DS_TUNE);
2324 	} else {
2325 		if (host->hs400_ds_dly3)
2326 			sdr_set_field(host->base + PAD_DS_TUNE,
2327 				      PAD_DS_TUNE_DLY3, host->hs400_ds_dly3);
2328 		if (host->hs400_ds_delay)
2329 			writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
2330 	}
2331 	/* hs400 mode must set it to 0 */
2332 	sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
2333 	/* to improve read performance, set outstanding to 2 */
2334 	sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
2335 
2336 	return 0;
2337 }
2338 
msdc_execute_hs400_tuning(struct mmc_host * mmc,struct mmc_card * card)2339 static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card)
2340 {
2341 	struct msdc_host *host = mmc_priv(mmc);
2342 	struct msdc_delay_phase dly1_delay;
2343 	u32 val, result_dly1 = 0;
2344 	u8 *ext_csd;
2345 	int i, ret;
2346 
2347 	if (host->top_base) {
2348 		sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE,
2349 			     PAD_DS_DLY_SEL);
2350 		sdr_clr_bits(host->top_base + EMMC50_PAD_DS_TUNE,
2351 			     PAD_DS_DLY2_SEL);
2352 	} else {
2353 		sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL);
2354 		sdr_clr_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY2_SEL);
2355 	}
2356 
2357 	host->hs400_tuning = true;
2358 	for (i = 0; i < PAD_DELAY_MAX; i++) {
2359 		if (host->top_base)
2360 			sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2361 				      PAD_DS_DLY1, i);
2362 		else
2363 			sdr_set_field(host->base + PAD_DS_TUNE,
2364 				      PAD_DS_TUNE_DLY1, i);
2365 		ret = mmc_get_ext_csd(card, &ext_csd);
2366 		if (!ret) {
2367 			result_dly1 |= BIT(i);
2368 			kfree(ext_csd);
2369 		}
2370 	}
2371 	host->hs400_tuning = false;
2372 
2373 	dly1_delay = get_best_delay(host, result_dly1);
2374 	if (dly1_delay.maxlen == 0) {
2375 		dev_err(host->dev, "Failed to get DLY1 delay!\n");
2376 		goto fail;
2377 	}
2378 	if (host->top_base)
2379 		sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2380 			      PAD_DS_DLY1, dly1_delay.final_phase);
2381 	else
2382 		sdr_set_field(host->base + PAD_DS_TUNE,
2383 			      PAD_DS_TUNE_DLY1, dly1_delay.final_phase);
2384 
2385 	if (host->top_base)
2386 		val = readl(host->top_base + EMMC50_PAD_DS_TUNE);
2387 	else
2388 		val = readl(host->base + PAD_DS_TUNE);
2389 
2390 	dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val);
2391 
2392 	return 0;
2393 
2394 fail:
2395 	dev_err(host->dev, "Failed to tuning DS pin delay!\n");
2396 	return -EIO;
2397 }
2398 
msdc_hw_reset(struct mmc_host * mmc)2399 static void msdc_hw_reset(struct mmc_host *mmc)
2400 {
2401 	struct msdc_host *host = mmc_priv(mmc);
2402 
2403 	sdr_set_bits(host->base + EMMC_IOCON, 1);
2404 	udelay(10); /* 10us is enough */
2405 	sdr_clr_bits(host->base + EMMC_IOCON, 1);
2406 }
2407 
msdc_ack_sdio_irq(struct mmc_host * mmc)2408 static void msdc_ack_sdio_irq(struct mmc_host *mmc)
2409 {
2410 	unsigned long flags;
2411 	struct msdc_host *host = mmc_priv(mmc);
2412 
2413 	spin_lock_irqsave(&host->lock, flags);
2414 	__msdc_enable_sdio_irq(host, 1);
2415 	spin_unlock_irqrestore(&host->lock, flags);
2416 }
2417 
msdc_get_cd(struct mmc_host * mmc)2418 static int msdc_get_cd(struct mmc_host *mmc)
2419 {
2420 	struct msdc_host *host = mmc_priv(mmc);
2421 	int val;
2422 
2423 	if (mmc->caps & MMC_CAP_NONREMOVABLE)
2424 		return 1;
2425 
2426 	if (!host->internal_cd)
2427 		return mmc_gpio_get_cd(mmc);
2428 
2429 	val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
2430 	if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)
2431 		return !!val;
2432 	else
2433 		return !val;
2434 }
2435 
msdc_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)2436 static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc,
2437 				       struct mmc_ios *ios)
2438 {
2439 	struct msdc_host *host = mmc_priv(mmc);
2440 
2441 	if (ios->enhanced_strobe) {
2442 		msdc_prepare_hs400_tuning(mmc, ios);
2443 		sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1);
2444 		sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1);
2445 		sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1);
2446 
2447 		sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2448 		sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2449 		sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT);
2450 	} else {
2451 		sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0);
2452 		sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0);
2453 		sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0);
2454 
2455 		sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2456 		sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2457 		sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4);
2458 	}
2459 }
2460 
msdc_cqe_cit_cal(struct msdc_host * host,u64 timer_ns)2461 static void msdc_cqe_cit_cal(struct msdc_host *host, u64 timer_ns)
2462 {
2463 	struct mmc_host *mmc = mmc_from_priv(host);
2464 	struct cqhci_host *cq_host = mmc->cqe_private;
2465 	u8 itcfmul;
2466 	u64 hclk_freq, value;
2467 
2468 	/*
2469 	 * On MediaTek SoCs the MSDC controller's CQE uses msdc_hclk as ITCFVAL
2470 	 * so we multiply/divide the HCLK frequency by ITCFMUL to calculate the
2471 	 * Send Status Command Idle Timer (CIT) value.
2472 	 */
2473 	hclk_freq = (u64)clk_get_rate(host->h_clk);
2474 	itcfmul = CQHCI_ITCFMUL(cqhci_readl(cq_host, CQHCI_CAP));
2475 	switch (itcfmul) {
2476 	case 0x0:
2477 		do_div(hclk_freq, 1000);
2478 		break;
2479 	case 0x1:
2480 		do_div(hclk_freq, 100);
2481 		break;
2482 	case 0x2:
2483 		do_div(hclk_freq, 10);
2484 		break;
2485 	case 0x3:
2486 		break;
2487 	case 0x4:
2488 		hclk_freq = hclk_freq * 10;
2489 		break;
2490 	default:
2491 		host->cq_ssc1_time = 0x40;
2492 		return;
2493 	}
2494 
2495 	value = hclk_freq * timer_ns;
2496 	do_div(value, 1000000000);
2497 	host->cq_ssc1_time = value;
2498 }
2499 
msdc_cqe_enable(struct mmc_host * mmc)2500 static void msdc_cqe_enable(struct mmc_host *mmc)
2501 {
2502 	struct msdc_host *host = mmc_priv(mmc);
2503 	struct cqhci_host *cq_host = mmc->cqe_private;
2504 
2505 	/* enable cmdq irq */
2506 	writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
2507 	/* enable busy check */
2508 	sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2509 	/* default write data / busy timeout 20s */
2510 	msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
2511 	/* default read data timeout 1s */
2512 	msdc_set_timeout(host, 1000000000ULL, 0);
2513 
2514 	/* Set the send status command idle timer */
2515 	cqhci_writel(cq_host, host->cq_ssc1_time, CQHCI_SSC1);
2516 }
2517 
msdc_cqe_disable(struct mmc_host * mmc,bool recovery)2518 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery)
2519 {
2520 	struct msdc_host *host = mmc_priv(mmc);
2521 	unsigned int val = 0;
2522 
2523 	/* disable cmdq irq */
2524 	sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);
2525 	/* disable busy check */
2526 	sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2527 
2528 	val = readl(host->base + MSDC_INT);
2529 	writel(val, host->base + MSDC_INT);
2530 
2531 	if (recovery) {
2532 		sdr_set_field(host->base + MSDC_DMA_CTRL,
2533 			      MSDC_DMA_CTRL_STOP, 1);
2534 		if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val,
2535 			!(val & MSDC_DMA_CTRL_STOP), 1, 3000)))
2536 			return;
2537 		if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val,
2538 			!(val & MSDC_DMA_CFG_STS), 1, 3000)))
2539 			return;
2540 		msdc_reset_hw(host);
2541 	}
2542 }
2543 
msdc_cqe_pre_enable(struct mmc_host * mmc)2544 static void msdc_cqe_pre_enable(struct mmc_host *mmc)
2545 {
2546 	struct cqhci_host *cq_host = mmc->cqe_private;
2547 	u32 reg;
2548 
2549 	reg = cqhci_readl(cq_host, CQHCI_CFG);
2550 	reg |= CQHCI_ENABLE;
2551 	cqhci_writel(cq_host, reg, CQHCI_CFG);
2552 }
2553 
msdc_cqe_post_disable(struct mmc_host * mmc)2554 static void msdc_cqe_post_disable(struct mmc_host *mmc)
2555 {
2556 	struct cqhci_host *cq_host = mmc->cqe_private;
2557 	u32 reg;
2558 
2559 	reg = cqhci_readl(cq_host, CQHCI_CFG);
2560 	reg &= ~CQHCI_ENABLE;
2561 	cqhci_writel(cq_host, reg, CQHCI_CFG);
2562 }
2563 
2564 static const struct mmc_host_ops mt_msdc_ops = {
2565 	.post_req = msdc_post_req,
2566 	.pre_req = msdc_pre_req,
2567 	.request = msdc_ops_request,
2568 	.set_ios = msdc_ops_set_ios,
2569 	.get_ro = mmc_gpio_get_ro,
2570 	.get_cd = msdc_get_cd,
2571 	.hs400_enhanced_strobe = msdc_hs400_enhanced_strobe,
2572 	.enable_sdio_irq = msdc_enable_sdio_irq,
2573 	.ack_sdio_irq = msdc_ack_sdio_irq,
2574 	.start_signal_voltage_switch = msdc_ops_switch_volt,
2575 	.card_busy = msdc_card_busy,
2576 	.execute_tuning = msdc_execute_tuning,
2577 	.prepare_hs400_tuning = msdc_prepare_hs400_tuning,
2578 	.execute_hs400_tuning = msdc_execute_hs400_tuning,
2579 	.card_hw_reset = msdc_hw_reset,
2580 };
2581 
2582 static const struct cqhci_host_ops msdc_cmdq_ops = {
2583 	.enable         = msdc_cqe_enable,
2584 	.disable        = msdc_cqe_disable,
2585 	.pre_enable = msdc_cqe_pre_enable,
2586 	.post_disable = msdc_cqe_post_disable,
2587 };
2588 
msdc_of_property_parse(struct platform_device * pdev,struct msdc_host * host)2589 static void msdc_of_property_parse(struct platform_device *pdev,
2590 				   struct msdc_host *host)
2591 {
2592 	of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
2593 			     &host->latch_ck);
2594 
2595 	of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
2596 			     &host->hs400_ds_delay);
2597 
2598 	of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3",
2599 			     &host->hs400_ds_dly3);
2600 
2601 	of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay",
2602 			     &host->hs200_cmd_int_delay);
2603 
2604 	of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay",
2605 			     &host->hs400_cmd_int_delay);
2606 
2607 	if (of_property_read_bool(pdev->dev.of_node,
2608 				  "mediatek,hs400-cmd-resp-sel-rising"))
2609 		host->hs400_cmd_resp_sel_rising = true;
2610 	else
2611 		host->hs400_cmd_resp_sel_rising = false;
2612 
2613 	if (of_property_read_bool(pdev->dev.of_node,
2614 				  "supports-cqe"))
2615 		host->cqhci = true;
2616 	else
2617 		host->cqhci = false;
2618 }
2619 
msdc_of_clock_parse(struct platform_device * pdev,struct msdc_host * host)2620 static int msdc_of_clock_parse(struct platform_device *pdev,
2621 			       struct msdc_host *host)
2622 {
2623 	int ret;
2624 
2625 	host->src_clk = devm_clk_get(&pdev->dev, "source");
2626 	if (IS_ERR(host->src_clk))
2627 		return PTR_ERR(host->src_clk);
2628 
2629 	host->h_clk = devm_clk_get(&pdev->dev, "hclk");
2630 	if (IS_ERR(host->h_clk))
2631 		return PTR_ERR(host->h_clk);
2632 
2633 	host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk");
2634 	if (IS_ERR(host->bus_clk))
2635 		host->bus_clk = NULL;
2636 
2637 	/*source clock control gate is optional clock*/
2638 	host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg");
2639 	if (IS_ERR(host->src_clk_cg))
2640 		return PTR_ERR(host->src_clk_cg);
2641 
2642 	/*
2643 	 * Fallback for legacy device-trees: src_clk and HCLK use the same
2644 	 * bit to control gating but they are parented to a different mux,
2645 	 * hence if our intention is to gate only the source, required
2646 	 * during a clk mode switch to avoid hw hangs, we need to gate
2647 	 * its parent (specified as a different clock only on new DTs).
2648 	 */
2649 	if (!host->src_clk_cg) {
2650 		host->src_clk_cg = clk_get_parent(host->src_clk);
2651 		if (IS_ERR(host->src_clk_cg))
2652 			return PTR_ERR(host->src_clk_cg);
2653 	}
2654 
2655 	/* If present, always enable for this clock gate */
2656 	host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg");
2657 	if (IS_ERR(host->sys_clk_cg))
2658 		host->sys_clk_cg = NULL;
2659 
2660 	host->bulk_clks[0].id = "pclk_cg";
2661 	host->bulk_clks[1].id = "axi_cg";
2662 	host->bulk_clks[2].id = "ahb_cg";
2663 	ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS,
2664 					 host->bulk_clks);
2665 	if (ret) {
2666 		dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n");
2667 		return ret;
2668 	}
2669 
2670 	return 0;
2671 }
2672 
msdc_drv_probe(struct platform_device * pdev)2673 static int msdc_drv_probe(struct platform_device *pdev)
2674 {
2675 	struct mmc_host *mmc;
2676 	struct msdc_host *host;
2677 	struct resource *res;
2678 	int ret;
2679 
2680 	if (!pdev->dev.of_node) {
2681 		dev_err(&pdev->dev, "No DT found\n");
2682 		return -EINVAL;
2683 	}
2684 
2685 	/* Allocate MMC host for this device */
2686 	mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(struct msdc_host));
2687 	if (!mmc)
2688 		return -ENOMEM;
2689 
2690 	host = mmc_priv(mmc);
2691 	ret = mmc_of_parse(mmc);
2692 	if (ret)
2693 		return ret;
2694 
2695 	host->base = devm_platform_ioremap_resource(pdev, 0);
2696 	if (IS_ERR(host->base))
2697 		return PTR_ERR(host->base);
2698 
2699 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2700 	if (res) {
2701 		host->top_base = devm_ioremap_resource(&pdev->dev, res);
2702 		if (IS_ERR(host->top_base))
2703 			host->top_base = NULL;
2704 	}
2705 
2706 	ret = mmc_regulator_get_supply(mmc);
2707 	if (ret)
2708 		return ret;
2709 
2710 	ret = msdc_of_clock_parse(pdev, host);
2711 	if (ret)
2712 		return ret;
2713 
2714 	host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
2715 								"hrst");
2716 	if (IS_ERR(host->reset))
2717 		return PTR_ERR(host->reset);
2718 
2719 	/* only eMMC has crypto property */
2720 	if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) {
2721 		host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto");
2722 		if (IS_ERR(host->crypto_clk))
2723 			return PTR_ERR(host->crypto_clk);
2724 		else if (host->crypto_clk)
2725 			mmc->caps2 |= MMC_CAP2_CRYPTO;
2726 	}
2727 
2728 	host->irq = platform_get_irq(pdev, 0);
2729 	if (host->irq < 0)
2730 		return host->irq;
2731 
2732 	host->pinctrl = devm_pinctrl_get(&pdev->dev);
2733 	if (IS_ERR(host->pinctrl))
2734 		return dev_err_probe(&pdev->dev, PTR_ERR(host->pinctrl),
2735 				     "Cannot find pinctrl");
2736 
2737 	host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
2738 	if (IS_ERR(host->pins_default)) {
2739 		dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
2740 		return PTR_ERR(host->pins_default);
2741 	}
2742 
2743 	host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
2744 	if (IS_ERR(host->pins_uhs)) {
2745 		dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
2746 		return PTR_ERR(host->pins_uhs);
2747 	}
2748 
2749 	/* Support for SDIO eint irq ? */
2750 	if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) {
2751 		host->eint_irq = platform_get_irq_byname_optional(pdev, "sdio_wakeup");
2752 		if (host->eint_irq > 0) {
2753 			host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint");
2754 			if (IS_ERR(host->pins_eint)) {
2755 				dev_err(&pdev->dev, "Cannot find pinctrl eint!\n");
2756 				host->pins_eint = NULL;
2757 			} else {
2758 				device_init_wakeup(&pdev->dev, true);
2759 			}
2760 		}
2761 	}
2762 
2763 	msdc_of_property_parse(pdev, host);
2764 
2765 	host->dev = &pdev->dev;
2766 	host->dev_comp = of_device_get_match_data(&pdev->dev);
2767 	host->src_clk_freq = clk_get_rate(host->src_clk);
2768 	/* Set host parameters to mmc */
2769 	mmc->ops = &mt_msdc_ops;
2770 	if (host->dev_comp->clk_div_bits == 8)
2771 		mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
2772 	else
2773 		mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
2774 
2775 	if (!(mmc->caps & MMC_CAP_NONREMOVABLE) &&
2776 	    !mmc_can_gpio_cd(mmc) &&
2777 	    host->dev_comp->use_internal_cd) {
2778 		/*
2779 		 * Is removable but no GPIO declared, so
2780 		 * use internal functionality.
2781 		 */
2782 		host->internal_cd = true;
2783 	}
2784 
2785 	if (mmc->caps & MMC_CAP_SDIO_IRQ)
2786 		mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2787 
2788 	mmc->caps |= MMC_CAP_CMD23;
2789 	if (host->cqhci)
2790 		mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
2791 	/* MMC core transfer sizes tunable parameters */
2792 	mmc->max_segs = MAX_BD_NUM;
2793 	if (host->dev_comp->support_64g)
2794 		mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT;
2795 	else
2796 		mmc->max_seg_size = BDMA_DESC_BUFLEN;
2797 	mmc->max_blk_size = 2048;
2798 	mmc->max_req_size = 512 * 1024;
2799 	mmc->max_blk_count = mmc->max_req_size / 512;
2800 	if (host->dev_comp->support_64g)
2801 		host->dma_mask = DMA_BIT_MASK(36);
2802 	else
2803 		host->dma_mask = DMA_BIT_MASK(32);
2804 	mmc_dev(mmc)->dma_mask = &host->dma_mask;
2805 
2806 	host->timeout_clks = 3 * 1048576;
2807 	host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2808 				2 * sizeof(struct mt_gpdma_desc),
2809 				&host->dma.gpd_addr, GFP_KERNEL);
2810 	host->dma.bd = dma_alloc_coherent(&pdev->dev,
2811 				MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2812 				&host->dma.bd_addr, GFP_KERNEL);
2813 	if (!host->dma.gpd || !host->dma.bd) {
2814 		ret = -ENOMEM;
2815 		goto release_mem;
2816 	}
2817 	msdc_init_gpd_bd(host, &host->dma);
2818 	INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
2819 	spin_lock_init(&host->lock);
2820 
2821 	platform_set_drvdata(pdev, mmc);
2822 	ret = msdc_ungate_clock(host);
2823 	if (ret) {
2824 		dev_err(&pdev->dev, "Cannot ungate clocks!\n");
2825 		goto release_clk;
2826 	}
2827 	msdc_init_hw(host);
2828 
2829 	if (mmc->caps2 & MMC_CAP2_CQE) {
2830 		host->cq_host = devm_kzalloc(mmc->parent,
2831 					     sizeof(*host->cq_host),
2832 					     GFP_KERNEL);
2833 		if (!host->cq_host) {
2834 			ret = -ENOMEM;
2835 			goto release;
2836 		}
2837 		host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
2838 		host->cq_host->mmio = host->base + 0x800;
2839 		host->cq_host->ops = &msdc_cmdq_ops;
2840 		ret = cqhci_init(host->cq_host, mmc, true);
2841 		if (ret)
2842 			goto release;
2843 		mmc->max_segs = 128;
2844 		/* cqhci 16bit length */
2845 		/* 0 size, means 65536 so we don't have to -1 here */
2846 		mmc->max_seg_size = 64 * 1024;
2847 		/* Reduce CIT to 0x40 that corresponds to 2.35us */
2848 		msdc_cqe_cit_cal(host, 2350);
2849 	}
2850 
2851 	ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
2852 			       IRQF_TRIGGER_NONE, pdev->name, host);
2853 	if (ret)
2854 		goto release;
2855 
2856 	pm_runtime_set_active(host->dev);
2857 	pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
2858 	pm_runtime_use_autosuspend(host->dev);
2859 	pm_runtime_enable(host->dev);
2860 	ret = mmc_add_host(mmc);
2861 
2862 	if (ret)
2863 		goto end;
2864 
2865 	return 0;
2866 end:
2867 	pm_runtime_disable(host->dev);
2868 release:
2869 	msdc_deinit_hw(host);
2870 release_clk:
2871 	msdc_gate_clock(host);
2872 	platform_set_drvdata(pdev, NULL);
2873 release_mem:
2874 	device_init_wakeup(&pdev->dev, false);
2875 	if (host->dma.gpd)
2876 		dma_free_coherent(&pdev->dev,
2877 			2 * sizeof(struct mt_gpdma_desc),
2878 			host->dma.gpd, host->dma.gpd_addr);
2879 	if (host->dma.bd)
2880 		dma_free_coherent(&pdev->dev,
2881 				  MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2882 				  host->dma.bd, host->dma.bd_addr);
2883 	return ret;
2884 }
2885 
msdc_drv_remove(struct platform_device * pdev)2886 static void msdc_drv_remove(struct platform_device *pdev)
2887 {
2888 	struct mmc_host *mmc;
2889 	struct msdc_host *host;
2890 
2891 	mmc = platform_get_drvdata(pdev);
2892 	host = mmc_priv(mmc);
2893 
2894 	pm_runtime_get_sync(host->dev);
2895 
2896 	platform_set_drvdata(pdev, NULL);
2897 	mmc_remove_host(mmc);
2898 	msdc_deinit_hw(host);
2899 	msdc_gate_clock(host);
2900 
2901 	pm_runtime_disable(host->dev);
2902 	pm_runtime_put_noidle(host->dev);
2903 	dma_free_coherent(&pdev->dev,
2904 			2 * sizeof(struct mt_gpdma_desc),
2905 			host->dma.gpd, host->dma.gpd_addr);
2906 	dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2907 			  host->dma.bd, host->dma.bd_addr);
2908 	device_init_wakeup(&pdev->dev, false);
2909 }
2910 
msdc_save_reg(struct msdc_host * host)2911 static void msdc_save_reg(struct msdc_host *host)
2912 {
2913 	u32 tune_reg = host->dev_comp->pad_tune_reg;
2914 
2915 	host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
2916 	host->save_para.iocon = readl(host->base + MSDC_IOCON);
2917 	host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
2918 	host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
2919 	host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
2920 	host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
2921 	host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
2922 	host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2923 	host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
2924 	host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
2925 	host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
2926 	if (host->top_base) {
2927 		host->save_para.emmc_top_control =
2928 			readl(host->top_base + EMMC_TOP_CONTROL);
2929 		host->save_para.emmc_top_cmd =
2930 			readl(host->top_base + EMMC_TOP_CMD);
2931 		host->save_para.emmc50_pad_ds_tune =
2932 			readl(host->top_base + EMMC50_PAD_DS_TUNE);
2933 	} else {
2934 		host->save_para.pad_tune = readl(host->base + tune_reg);
2935 	}
2936 }
2937 
msdc_restore_reg(struct msdc_host * host)2938 static void msdc_restore_reg(struct msdc_host *host)
2939 {
2940 	struct mmc_host *mmc = mmc_from_priv(host);
2941 	u32 tune_reg = host->dev_comp->pad_tune_reg;
2942 
2943 	writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
2944 	writel(host->save_para.iocon, host->base + MSDC_IOCON);
2945 	writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
2946 	writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
2947 	writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
2948 	writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
2949 	writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
2950 	writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
2951 	writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
2952 	writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
2953 	writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
2954 	if (host->top_base) {
2955 		writel(host->save_para.emmc_top_control,
2956 		       host->top_base + EMMC_TOP_CONTROL);
2957 		writel(host->save_para.emmc_top_cmd,
2958 		       host->top_base + EMMC_TOP_CMD);
2959 		writel(host->save_para.emmc50_pad_ds_tune,
2960 		       host->top_base + EMMC50_PAD_DS_TUNE);
2961 	} else {
2962 		writel(host->save_para.pad_tune, host->base + tune_reg);
2963 	}
2964 
2965 	if (sdio_irq_claimed(mmc))
2966 		__msdc_enable_sdio_irq(host, 1);
2967 }
2968 
msdc_runtime_suspend(struct device * dev)2969 static int __maybe_unused msdc_runtime_suspend(struct device *dev)
2970 {
2971 	struct mmc_host *mmc = dev_get_drvdata(dev);
2972 	struct msdc_host *host = mmc_priv(mmc);
2973 
2974 	msdc_save_reg(host);
2975 
2976 	if (sdio_irq_claimed(mmc)) {
2977 		if (host->pins_eint) {
2978 			disable_irq(host->irq);
2979 			pinctrl_select_state(host->pinctrl, host->pins_eint);
2980 		}
2981 
2982 		__msdc_enable_sdio_irq(host, 0);
2983 	}
2984 	msdc_gate_clock(host);
2985 	return 0;
2986 }
2987 
msdc_runtime_resume(struct device * dev)2988 static int __maybe_unused msdc_runtime_resume(struct device *dev)
2989 {
2990 	struct mmc_host *mmc = dev_get_drvdata(dev);
2991 	struct msdc_host *host = mmc_priv(mmc);
2992 	int ret;
2993 
2994 	ret = msdc_ungate_clock(host);
2995 	if (ret)
2996 		return ret;
2997 
2998 	msdc_restore_reg(host);
2999 
3000 	if (sdio_irq_claimed(mmc) && host->pins_eint) {
3001 		pinctrl_select_state(host->pinctrl, host->pins_uhs);
3002 		enable_irq(host->irq);
3003 	}
3004 	return 0;
3005 }
3006 
msdc_suspend(struct device * dev)3007 static int __maybe_unused msdc_suspend(struct device *dev)
3008 {
3009 	struct mmc_host *mmc = dev_get_drvdata(dev);
3010 	struct msdc_host *host = mmc_priv(mmc);
3011 	int ret;
3012 	u32 val;
3013 
3014 	if (mmc->caps2 & MMC_CAP2_CQE) {
3015 		ret = cqhci_suspend(mmc);
3016 		if (ret)
3017 			return ret;
3018 		val = readl(host->base + MSDC_INT);
3019 		writel(val, host->base + MSDC_INT);
3020 	}
3021 
3022 	/*
3023 	 * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will
3024 	 * not be marked as 1, pm_runtime_force_resume() will go out directly.
3025 	 */
3026 	if (sdio_irq_claimed(mmc) && host->pins_eint)
3027 		pm_runtime_get_noresume(dev);
3028 
3029 	return pm_runtime_force_suspend(dev);
3030 }
3031 
msdc_resume(struct device * dev)3032 static int __maybe_unused msdc_resume(struct device *dev)
3033 {
3034 	struct mmc_host *mmc = dev_get_drvdata(dev);
3035 	struct msdc_host *host = mmc_priv(mmc);
3036 
3037 	if (sdio_irq_claimed(mmc) && host->pins_eint)
3038 		pm_runtime_put_noidle(dev);
3039 
3040 	return pm_runtime_force_resume(dev);
3041 }
3042 
3043 static const struct dev_pm_ops msdc_dev_pm_ops = {
3044 	SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume)
3045 	SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
3046 };
3047 
3048 static struct platform_driver mt_msdc_driver = {
3049 	.probe = msdc_drv_probe,
3050 	.remove_new = msdc_drv_remove,
3051 	.driver = {
3052 		.name = "mtk-msdc",
3053 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
3054 		.of_match_table = msdc_of_ids,
3055 		.pm = &msdc_dev_pm_ops,
3056 	},
3057 };
3058 
3059 module_platform_driver(mt_msdc_driver);
3060 MODULE_LICENSE("GPL v2");
3061 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");
3062