1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #include <linux/devcoredump.h>
6
7 #include "cam.h"
8 #include "chan.h"
9 #include "debug.h"
10 #include "fw.h"
11 #include "mac.h"
12 #include "ps.h"
13 #include "reg.h"
14 #include "ser.h"
15 #include "util.h"
16
17 #define SER_RECFG_TIMEOUT 1000
18
19 enum ser_evt {
20 SER_EV_NONE,
21 SER_EV_STATE_IN,
22 SER_EV_STATE_OUT,
23 SER_EV_L1_RESET_PREPARE, /* pre-M0 */
24 SER_EV_L1_RESET, /* M1 */
25 SER_EV_DO_RECOVERY, /* M3 */
26 SER_EV_MAC_RESET_DONE, /* M5 */
27 SER_EV_L2_RESET,
28 SER_EV_L2_RECFG_DONE,
29 SER_EV_L2_RECFG_TIMEOUT,
30 SER_EV_M1_TIMEOUT,
31 SER_EV_M3_TIMEOUT,
32 SER_EV_FW_M5_TIMEOUT,
33 SER_EV_L0_RESET,
34 SER_EV_MAXX
35 };
36
37 enum ser_state {
38 SER_IDLE_ST,
39 SER_L1_RESET_PRE_ST,
40 SER_RESET_TRX_ST,
41 SER_DO_HCI_ST,
42 SER_L2_RESET_ST,
43 SER_ST_MAX_ST
44 };
45
46 struct ser_msg {
47 struct list_head list;
48 u8 event;
49 };
50
51 struct state_ent {
52 u8 state;
53 char *name;
54 void (*st_func)(struct rtw89_ser *ser, u8 event);
55 };
56
57 struct event_ent {
58 u8 event;
59 char *name;
60 };
61
ser_ev_name(struct rtw89_ser * ser,u8 event)62 static char *ser_ev_name(struct rtw89_ser *ser, u8 event)
63 {
64 if (event < SER_EV_MAXX)
65 return ser->ev_tbl[event].name;
66
67 return "err_ev_name";
68 }
69
ser_st_name(struct rtw89_ser * ser)70 static char *ser_st_name(struct rtw89_ser *ser)
71 {
72 if (ser->state < SER_ST_MAX_ST)
73 return ser->st_tbl[ser->state].name;
74
75 return "err_st_name";
76 }
77
78 #define RTW89_DEF_SER_CD_TYPE(_name, _type, _size) \
79 struct ser_cd_ ## _name { \
80 u32 type; \
81 u32 type_size; \
82 u64 padding; \
83 u8 data[_size]; \
84 } __packed; \
85 static void ser_cd_ ## _name ## _init(struct ser_cd_ ## _name *p) \
86 { \
87 p->type = _type; \
88 p->type_size = sizeof(p->data); \
89 p->padding = 0x0123456789abcdef; \
90 }
91
92 enum rtw89_ser_cd_type {
93 RTW89_SER_CD_FW_RSVD_PLE = 0,
94 RTW89_SER_CD_FW_BACKTRACE = 1,
95 };
96
97 RTW89_DEF_SER_CD_TYPE(fw_rsvd_ple,
98 RTW89_SER_CD_FW_RSVD_PLE,
99 RTW89_FW_RSVD_PLE_SIZE);
100
101 RTW89_DEF_SER_CD_TYPE(fw_backtrace,
102 RTW89_SER_CD_FW_BACKTRACE,
103 RTW89_FW_BACKTRACE_MAX_SIZE);
104
105 struct rtw89_ser_cd_buffer {
106 struct ser_cd_fw_rsvd_ple fwple;
107 struct ser_cd_fw_backtrace fwbt;
108 } __packed;
109
rtw89_ser_cd_prep(struct rtw89_dev * rtwdev)110 static struct rtw89_ser_cd_buffer *rtw89_ser_cd_prep(struct rtw89_dev *rtwdev)
111 {
112 struct rtw89_ser_cd_buffer *buf;
113
114 buf = vzalloc(sizeof(*buf));
115 if (!buf)
116 return NULL;
117
118 ser_cd_fw_rsvd_ple_init(&buf->fwple);
119 ser_cd_fw_backtrace_init(&buf->fwbt);
120
121 return buf;
122 }
123
rtw89_ser_cd_send(struct rtw89_dev * rtwdev,struct rtw89_ser_cd_buffer * buf)124 static void rtw89_ser_cd_send(struct rtw89_dev *rtwdev,
125 struct rtw89_ser_cd_buffer *buf)
126 {
127 rtw89_debug(rtwdev, RTW89_DBG_SER, "SER sends core dump\n");
128
129 /* After calling dev_coredump, buf's lifetime is supposed to be
130 * handled by the device coredump framework. Note that a new dump
131 * will be discarded if a previous one hasn't been released by
132 * framework yet.
133 */
134 dev_coredumpv(rtwdev->dev, buf, sizeof(*buf), GFP_KERNEL);
135 }
136
rtw89_ser_cd_free(struct rtw89_dev * rtwdev,struct rtw89_ser_cd_buffer * buf,bool free_self)137 static void rtw89_ser_cd_free(struct rtw89_dev *rtwdev,
138 struct rtw89_ser_cd_buffer *buf, bool free_self)
139 {
140 if (!free_self)
141 return;
142
143 rtw89_debug(rtwdev, RTW89_DBG_SER, "SER frees core dump by self\n");
144
145 /* When some problems happen during filling data of core dump,
146 * we won't send it to device coredump framework. Instead, we
147 * free buf by ourselves.
148 */
149 vfree(buf);
150 }
151
ser_state_run(struct rtw89_ser * ser,u8 evt)152 static void ser_state_run(struct rtw89_ser *ser, u8 evt)
153 {
154 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
155
156 rtw89_debug(rtwdev, RTW89_DBG_SER, "ser: %s receive %s\n",
157 ser_st_name(ser), ser_ev_name(ser, evt));
158
159 wiphy_lock(rtwdev->hw->wiphy);
160 mutex_lock(&rtwdev->mutex);
161 rtw89_leave_lps(rtwdev);
162 mutex_unlock(&rtwdev->mutex);
163 wiphy_unlock(rtwdev->hw->wiphy);
164
165 ser->st_tbl[ser->state].st_func(ser, evt);
166 }
167
ser_state_goto(struct rtw89_ser * ser,u8 new_state)168 static void ser_state_goto(struct rtw89_ser *ser, u8 new_state)
169 {
170 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
171
172 if (ser->state == new_state || new_state >= SER_ST_MAX_ST)
173 return;
174 ser_state_run(ser, SER_EV_STATE_OUT);
175
176 rtw89_debug(rtwdev, RTW89_DBG_SER, "ser: %s goto -> %s\n",
177 ser_st_name(ser), ser->st_tbl[new_state].name);
178
179 ser->state = new_state;
180 ser_state_run(ser, SER_EV_STATE_IN);
181 }
182
__rtw89_ser_dequeue_msg(struct rtw89_ser * ser)183 static struct ser_msg *__rtw89_ser_dequeue_msg(struct rtw89_ser *ser)
184 {
185 struct ser_msg *msg;
186
187 spin_lock_irq(&ser->msg_q_lock);
188 msg = list_first_entry_or_null(&ser->msg_q, struct ser_msg, list);
189 if (msg)
190 list_del(&msg->list);
191 spin_unlock_irq(&ser->msg_q_lock);
192
193 return msg;
194 }
195
rtw89_ser_hdl_work(struct work_struct * work)196 static void rtw89_ser_hdl_work(struct work_struct *work)
197 {
198 struct ser_msg *msg;
199 struct rtw89_ser *ser = container_of(work, struct rtw89_ser,
200 ser_hdl_work);
201
202 while ((msg = __rtw89_ser_dequeue_msg(ser))) {
203 ser_state_run(ser, msg->event);
204 kfree(msg);
205 }
206 }
207
ser_send_msg(struct rtw89_ser * ser,u8 event)208 static int ser_send_msg(struct rtw89_ser *ser, u8 event)
209 {
210 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
211 struct ser_msg *msg = NULL;
212
213 if (test_bit(RTW89_SER_DRV_STOP_RUN, ser->flags))
214 return -EIO;
215
216 msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
217 if (!msg)
218 return -ENOMEM;
219
220 msg->event = event;
221
222 spin_lock_irq(&ser->msg_q_lock);
223 list_add(&msg->list, &ser->msg_q);
224 spin_unlock_irq(&ser->msg_q_lock);
225
226 ieee80211_queue_work(rtwdev->hw, &ser->ser_hdl_work);
227 return 0;
228 }
229
rtw89_ser_alarm_work(struct work_struct * work)230 static void rtw89_ser_alarm_work(struct work_struct *work)
231 {
232 struct rtw89_ser *ser = container_of(work, struct rtw89_ser,
233 ser_alarm_work.work);
234
235 ser_send_msg(ser, ser->alarm_event);
236 ser->alarm_event = SER_EV_NONE;
237 }
238
ser_set_alarm(struct rtw89_ser * ser,u32 ms,u8 event)239 static void ser_set_alarm(struct rtw89_ser *ser, u32 ms, u8 event)
240 {
241 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
242
243 if (test_bit(RTW89_SER_DRV_STOP_RUN, ser->flags))
244 return;
245
246 ser->alarm_event = event;
247 ieee80211_queue_delayed_work(rtwdev->hw, &ser->ser_alarm_work,
248 msecs_to_jiffies(ms));
249 }
250
ser_del_alarm(struct rtw89_ser * ser)251 static void ser_del_alarm(struct rtw89_ser *ser)
252 {
253 cancel_delayed_work(&ser->ser_alarm_work);
254 ser->alarm_event = SER_EV_NONE;
255 }
256
257 /* driver function */
drv_stop_tx(struct rtw89_ser * ser)258 static void drv_stop_tx(struct rtw89_ser *ser)
259 {
260 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
261
262 ieee80211_stop_queues(rtwdev->hw);
263 set_bit(RTW89_SER_DRV_STOP_TX, ser->flags);
264 }
265
drv_stop_rx(struct rtw89_ser * ser)266 static void drv_stop_rx(struct rtw89_ser *ser)
267 {
268 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
269
270 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags);
271 set_bit(RTW89_SER_DRV_STOP_RX, ser->flags);
272 }
273
drv_trx_reset(struct rtw89_ser * ser)274 static void drv_trx_reset(struct rtw89_ser *ser)
275 {
276 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
277
278 rtw89_hci_reset(rtwdev);
279 }
280
drv_resume_tx(struct rtw89_ser * ser)281 static void drv_resume_tx(struct rtw89_ser *ser)
282 {
283 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
284
285 if (!test_bit(RTW89_SER_DRV_STOP_TX, ser->flags))
286 return;
287
288 ieee80211_wake_queues(rtwdev->hw);
289 clear_bit(RTW89_SER_DRV_STOP_TX, ser->flags);
290 }
291
drv_resume_rx(struct rtw89_ser * ser)292 static void drv_resume_rx(struct rtw89_ser *ser)
293 {
294 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
295
296 if (!test_bit(RTW89_SER_DRV_STOP_RX, ser->flags))
297 return;
298
299 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags);
300 clear_bit(RTW89_SER_DRV_STOP_RX, ser->flags);
301 }
302
ser_reset_vif(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)303 static void ser_reset_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
304 {
305 rtw89_core_release_bit_map(rtwdev->hw_port, rtwvif->port);
306 rtwvif->net_type = RTW89_NET_TYPE_NO_LINK;
307 rtwvif->trigger = false;
308 rtwvif->tdls_peer = 0;
309 }
310
ser_sta_deinit_cam_iter(void * data,struct ieee80211_sta * sta)311 static void ser_sta_deinit_cam_iter(void *data, struct ieee80211_sta *sta)
312 {
313 struct rtw89_vif *target_rtwvif = (struct rtw89_vif *)data;
314 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
315 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
316 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
317
318 if (rtwvif != target_rtwvif)
319 return;
320
321 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls)
322 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta->addr_cam);
323 if (sta->tdls)
324 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta->bssid_cam);
325
326 INIT_LIST_HEAD(&rtwsta->ba_cam_list);
327 }
328
ser_deinit_cam(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)329 static void ser_deinit_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
330 {
331 ieee80211_iterate_stations_atomic(rtwdev->hw,
332 ser_sta_deinit_cam_iter,
333 rtwvif);
334
335 rtw89_cam_deinit(rtwdev, rtwvif);
336
337 bitmap_zero(rtwdev->cam_info.ba_cam_map, RTW89_MAX_BA_CAM_NUM);
338 }
339
ser_reset_mac_binding(struct rtw89_dev * rtwdev)340 static void ser_reset_mac_binding(struct rtw89_dev *rtwdev)
341 {
342 struct rtw89_vif *rtwvif;
343
344 rtw89_cam_reset_keys(rtwdev);
345 rtw89_for_each_rtwvif(rtwdev, rtwvif)
346 ser_deinit_cam(rtwdev, rtwvif);
347
348 rtw89_core_release_all_bits_map(rtwdev->mac_id_map, RTW89_MAX_MAC_ID_NUM);
349 rtw89_for_each_rtwvif(rtwdev, rtwvif)
350 ser_reset_vif(rtwdev, rtwvif);
351
352 rtwdev->total_sta_assoc = 0;
353 }
354
355 /* hal function */
hal_enable_dma(struct rtw89_ser * ser)356 static int hal_enable_dma(struct rtw89_ser *ser)
357 {
358 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
359 int ret;
360
361 if (!test_bit(RTW89_SER_HAL_STOP_DMA, ser->flags))
362 return 0;
363
364 if (!rtwdev->hci.ops->mac_lv1_rcvy)
365 return -EIO;
366
367 ret = rtwdev->hci.ops->mac_lv1_rcvy(rtwdev, RTW89_LV1_RCVY_STEP_2);
368 if (!ret)
369 clear_bit(RTW89_SER_HAL_STOP_DMA, ser->flags);
370
371 return ret;
372 }
373
hal_stop_dma(struct rtw89_ser * ser)374 static int hal_stop_dma(struct rtw89_ser *ser)
375 {
376 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
377 int ret;
378
379 if (!rtwdev->hci.ops->mac_lv1_rcvy)
380 return -EIO;
381
382 ret = rtwdev->hci.ops->mac_lv1_rcvy(rtwdev, RTW89_LV1_RCVY_STEP_1);
383 if (!ret)
384 set_bit(RTW89_SER_HAL_STOP_DMA, ser->flags);
385
386 return ret;
387 }
388
hal_send_post_m0_event(struct rtw89_ser * ser)389 static void hal_send_post_m0_event(struct rtw89_ser *ser)
390 {
391 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
392
393 rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L1_RESET_START_DMAC);
394 }
395
hal_send_m2_event(struct rtw89_ser * ser)396 static void hal_send_m2_event(struct rtw89_ser *ser)
397 {
398 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
399
400 rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L1_DISABLE_EN);
401 }
402
hal_send_m4_event(struct rtw89_ser * ser)403 static void hal_send_m4_event(struct rtw89_ser *ser)
404 {
405 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
406
407 rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L1_RCVY_EN);
408 }
409
410 /* state handler */
ser_idle_st_hdl(struct rtw89_ser * ser,u8 evt)411 static void ser_idle_st_hdl(struct rtw89_ser *ser, u8 evt)
412 {
413 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
414
415 switch (evt) {
416 case SER_EV_STATE_IN:
417 rtw89_hci_recovery_complete(rtwdev);
418 clear_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags);
419 clear_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags);
420 break;
421 case SER_EV_L1_RESET_PREPARE:
422 ser_state_goto(ser, SER_L1_RESET_PRE_ST);
423 break;
424 case SER_EV_L1_RESET:
425 ser_state_goto(ser, SER_RESET_TRX_ST);
426 break;
427 case SER_EV_L2_RESET:
428 ser_state_goto(ser, SER_L2_RESET_ST);
429 break;
430 case SER_EV_STATE_OUT:
431 set_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags);
432 rtw89_hci_recovery_start(rtwdev);
433 break;
434 default:
435 break;
436 }
437 }
438
ser_l1_reset_pre_st_hdl(struct rtw89_ser * ser,u8 evt)439 static void ser_l1_reset_pre_st_hdl(struct rtw89_ser *ser, u8 evt)
440 {
441 switch (evt) {
442 case SER_EV_STATE_IN:
443 ser->prehandle_l1 = true;
444 hal_send_post_m0_event(ser);
445 ser_set_alarm(ser, 1000, SER_EV_M1_TIMEOUT);
446 break;
447 case SER_EV_L1_RESET:
448 ser_state_goto(ser, SER_RESET_TRX_ST);
449 break;
450 case SER_EV_M1_TIMEOUT:
451 ser_state_goto(ser, SER_L2_RESET_ST);
452 break;
453 case SER_EV_STATE_OUT:
454 ser_del_alarm(ser);
455 break;
456 default:
457 break;
458 }
459 }
460
ser_reset_trx_st_hdl(struct rtw89_ser * ser,u8 evt)461 static void ser_reset_trx_st_hdl(struct rtw89_ser *ser, u8 evt)
462 {
463 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
464
465 switch (evt) {
466 case SER_EV_STATE_IN:
467 cancel_delayed_work_sync(&rtwdev->track_work);
468 drv_stop_tx(ser);
469
470 if (hal_stop_dma(ser)) {
471 ser_state_goto(ser, SER_L2_RESET_ST);
472 break;
473 }
474
475 drv_stop_rx(ser);
476 drv_trx_reset(ser);
477
478 /* wait m3 */
479 hal_send_m2_event(ser);
480
481 /* set alarm to prevent FW response timeout */
482 ser_set_alarm(ser, 1000, SER_EV_M3_TIMEOUT);
483 break;
484
485 case SER_EV_DO_RECOVERY:
486 ser_state_goto(ser, SER_DO_HCI_ST);
487 break;
488
489 case SER_EV_M3_TIMEOUT:
490 ser_state_goto(ser, SER_L2_RESET_ST);
491 break;
492
493 case SER_EV_STATE_OUT:
494 ser_del_alarm(ser);
495 hal_enable_dma(ser);
496 drv_resume_rx(ser);
497 drv_resume_tx(ser);
498 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work,
499 RTW89_TRACK_WORK_PERIOD);
500 break;
501
502 default:
503 break;
504 }
505 }
506
ser_do_hci_st_hdl(struct rtw89_ser * ser,u8 evt)507 static void ser_do_hci_st_hdl(struct rtw89_ser *ser, u8 evt)
508 {
509 switch (evt) {
510 case SER_EV_STATE_IN:
511 /* wait m5 */
512 hal_send_m4_event(ser);
513
514 /* prevent FW response timeout */
515 ser_set_alarm(ser, 1000, SER_EV_FW_M5_TIMEOUT);
516 break;
517
518 case SER_EV_FW_M5_TIMEOUT:
519 ser_state_goto(ser, SER_L2_RESET_ST);
520 break;
521
522 case SER_EV_MAC_RESET_DONE:
523 ser_state_goto(ser, SER_IDLE_ST);
524 break;
525
526 case SER_EV_STATE_OUT:
527 ser_del_alarm(ser);
528 break;
529
530 default:
531 break;
532 }
533 }
534
ser_mac_mem_dump(struct rtw89_dev * rtwdev,u8 * buf,u8 sel,u32 start_addr,u32 len)535 static void ser_mac_mem_dump(struct rtw89_dev *rtwdev, u8 *buf,
536 u8 sel, u32 start_addr, u32 len)
537 {
538 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
539 u32 filter_model_addr = mac->filter_model_addr;
540 u32 indir_access_addr = mac->indir_access_addr;
541 u32 *ptr = (u32 *)buf;
542 u32 base_addr, start_page, residue;
543 u32 cnt = 0;
544 u32 i;
545
546 start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE;
547 residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE;
548 base_addr = mac->mem_base_addrs[sel];
549 base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE;
550
551 while (cnt < len) {
552 rtw89_write32(rtwdev, filter_model_addr, base_addr);
553
554 for (i = indir_access_addr + residue;
555 i < indir_access_addr + MAC_MEM_DUMP_PAGE_SIZE;
556 i += 4, ptr++) {
557 *ptr = rtw89_read32(rtwdev, i);
558 cnt += 4;
559 if (cnt >= len)
560 break;
561 }
562
563 residue = 0;
564 base_addr += MAC_MEM_DUMP_PAGE_SIZE;
565 }
566 }
567
rtw89_ser_fw_rsvd_ple_dump(struct rtw89_dev * rtwdev,u8 * buf)568 static void rtw89_ser_fw_rsvd_ple_dump(struct rtw89_dev *rtwdev, u8 *buf)
569 {
570 u32 start_addr = rtwdev->chip->rsvd_ple_ofst;
571
572 rtw89_debug(rtwdev, RTW89_DBG_SER,
573 "dump mem for fw rsvd payload engine (start addr: 0x%x)\n",
574 start_addr);
575 ser_mac_mem_dump(rtwdev, buf, RTW89_MAC_MEM_SHARED_BUF, start_addr,
576 RTW89_FW_RSVD_PLE_SIZE);
577 }
578
579 struct __fw_backtrace_entry {
580 u32 wcpu_addr;
581 u32 size;
582 u32 key;
583 } __packed;
584
585 struct __fw_backtrace_info {
586 u32 ra;
587 u32 sp;
588 } __packed;
589
590 static_assert(RTW89_FW_BACKTRACE_INFO_SIZE ==
591 sizeof(struct __fw_backtrace_info));
592
rtw89_ser_fw_backtrace_dump(struct rtw89_dev * rtwdev,u8 * buf,const struct __fw_backtrace_entry * ent)593 static int rtw89_ser_fw_backtrace_dump(struct rtw89_dev *rtwdev, u8 *buf,
594 const struct __fw_backtrace_entry *ent)
595 {
596 struct __fw_backtrace_info *ptr = (struct __fw_backtrace_info *)buf;
597 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
598 u32 filter_model_addr = mac->filter_model_addr;
599 u32 indir_access_addr = mac->indir_access_addr;
600 u32 fwbt_addr = ent->wcpu_addr & RTW89_WCPU_BASE_MASK;
601 u32 fwbt_size = ent->size;
602 u32 fwbt_key = ent->key;
603 u32 i;
604
605 if (fwbt_addr == 0) {
606 rtw89_warn(rtwdev, "FW backtrace invalid address: 0x%x\n",
607 fwbt_addr);
608 return -EINVAL;
609 }
610
611 if (fwbt_key != RTW89_FW_BACKTRACE_KEY) {
612 rtw89_warn(rtwdev, "FW backtrace invalid key: 0x%x\n",
613 fwbt_key);
614 return -EINVAL;
615 }
616
617 if (fwbt_size == 0 || !RTW89_VALID_FW_BACKTRACE_SIZE(fwbt_size) ||
618 fwbt_size > RTW89_FW_BACKTRACE_MAX_SIZE) {
619 rtw89_warn(rtwdev, "FW backtrace invalid size: 0x%x\n",
620 fwbt_size);
621 return -EINVAL;
622 }
623
624 rtw89_debug(rtwdev, RTW89_DBG_SER, "dump fw backtrace start\n");
625 rtw89_write32(rtwdev, filter_model_addr, fwbt_addr);
626
627 for (i = indir_access_addr;
628 i < indir_access_addr + fwbt_size;
629 i += RTW89_FW_BACKTRACE_INFO_SIZE, ptr++) {
630 *ptr = (struct __fw_backtrace_info){
631 .ra = rtw89_read32(rtwdev, i),
632 .sp = rtw89_read32(rtwdev, i + 4),
633 };
634 rtw89_debug(rtwdev, RTW89_DBG_SER,
635 "next sp: 0x%x, next ra: 0x%x\n",
636 ptr->sp, ptr->ra);
637 }
638
639 rtw89_debug(rtwdev, RTW89_DBG_SER, "dump fw backtrace end\n");
640 return 0;
641 }
642
ser_l2_reset_st_pre_hdl(struct rtw89_ser * ser)643 static void ser_l2_reset_st_pre_hdl(struct rtw89_ser *ser)
644 {
645 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
646 struct rtw89_ser_cd_buffer *buf;
647 struct __fw_backtrace_entry fwbt_ent;
648 int ret = 0;
649
650 buf = rtw89_ser_cd_prep(rtwdev);
651 if (!buf) {
652 ret = -ENOMEM;
653 goto bottom;
654 }
655
656 rtw89_ser_fw_rsvd_ple_dump(rtwdev, buf->fwple.data);
657
658 fwbt_ent = *(struct __fw_backtrace_entry *)buf->fwple.data;
659 ret = rtw89_ser_fw_backtrace_dump(rtwdev, buf->fwbt.data, &fwbt_ent);
660 if (ret)
661 goto bottom;
662
663 rtw89_ser_cd_send(rtwdev, buf);
664
665 bottom:
666 rtw89_ser_cd_free(rtwdev, buf, !!ret);
667
668 ser_reset_mac_binding(rtwdev);
669 rtw89_core_stop(rtwdev);
670 rtw89_entity_init(rtwdev);
671 rtw89_fw_release_general_pkt_list(rtwdev, false);
672 INIT_LIST_HEAD(&rtwdev->rtwvifs_list);
673 }
674
ser_l2_reset_st_hdl(struct rtw89_ser * ser,u8 evt)675 static void ser_l2_reset_st_hdl(struct rtw89_ser *ser, u8 evt)
676 {
677 struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
678
679 switch (evt) {
680 case SER_EV_STATE_IN:
681 wiphy_lock(rtwdev->hw->wiphy);
682 mutex_lock(&rtwdev->mutex);
683 ser_l2_reset_st_pre_hdl(ser);
684 mutex_unlock(&rtwdev->mutex);
685 wiphy_unlock(rtwdev->hw->wiphy);
686
687 ieee80211_restart_hw(rtwdev->hw);
688 ser_set_alarm(ser, SER_RECFG_TIMEOUT, SER_EV_L2_RECFG_TIMEOUT);
689 break;
690
691 case SER_EV_L2_RECFG_TIMEOUT:
692 rtw89_info(rtwdev, "Err: ser L2 re-config timeout\n");
693 fallthrough;
694 case SER_EV_L2_RECFG_DONE:
695 ser_state_goto(ser, SER_IDLE_ST);
696 break;
697
698 case SER_EV_STATE_OUT:
699 ser_del_alarm(ser);
700 break;
701
702 default:
703 break;
704 }
705 }
706
707 static const struct event_ent ser_ev_tbl[] = {
708 {SER_EV_NONE, "SER_EV_NONE"},
709 {SER_EV_STATE_IN, "SER_EV_STATE_IN"},
710 {SER_EV_STATE_OUT, "SER_EV_STATE_OUT"},
711 {SER_EV_L1_RESET_PREPARE, "SER_EV_L1_RESET_PREPARE pre-m0"},
712 {SER_EV_L1_RESET, "SER_EV_L1_RESET m1"},
713 {SER_EV_DO_RECOVERY, "SER_EV_DO_RECOVERY m3"},
714 {SER_EV_MAC_RESET_DONE, "SER_EV_MAC_RESET_DONE m5"},
715 {SER_EV_L2_RESET, "SER_EV_L2_RESET"},
716 {SER_EV_L2_RECFG_DONE, "SER_EV_L2_RECFG_DONE"},
717 {SER_EV_L2_RECFG_TIMEOUT, "SER_EV_L2_RECFG_TIMEOUT"},
718 {SER_EV_M1_TIMEOUT, "SER_EV_M1_TIMEOUT"},
719 {SER_EV_M3_TIMEOUT, "SER_EV_M3_TIMEOUT"},
720 {SER_EV_FW_M5_TIMEOUT, "SER_EV_FW_M5_TIMEOUT"},
721 {SER_EV_L0_RESET, "SER_EV_L0_RESET"},
722 {SER_EV_MAXX, "SER_EV_MAX"}
723 };
724
725 static const struct state_ent ser_st_tbl[] = {
726 {SER_IDLE_ST, "SER_IDLE_ST", ser_idle_st_hdl},
727 {SER_L1_RESET_PRE_ST, "SER_L1_RESET_PRE_ST", ser_l1_reset_pre_st_hdl},
728 {SER_RESET_TRX_ST, "SER_RESET_TRX_ST", ser_reset_trx_st_hdl},
729 {SER_DO_HCI_ST, "SER_DO_HCI_ST", ser_do_hci_st_hdl},
730 {SER_L2_RESET_ST, "SER_L2_RESET_ST", ser_l2_reset_st_hdl}
731 };
732
rtw89_ser_init(struct rtw89_dev * rtwdev)733 int rtw89_ser_init(struct rtw89_dev *rtwdev)
734 {
735 struct rtw89_ser *ser = &rtwdev->ser;
736
737 memset(ser, 0, sizeof(*ser));
738 INIT_LIST_HEAD(&ser->msg_q);
739 ser->state = SER_IDLE_ST;
740 ser->st_tbl = ser_st_tbl;
741 ser->ev_tbl = ser_ev_tbl;
742
743 bitmap_zero(ser->flags, RTW89_NUM_OF_SER_FLAGS);
744 spin_lock_init(&ser->msg_q_lock);
745 INIT_WORK(&ser->ser_hdl_work, rtw89_ser_hdl_work);
746 INIT_DELAYED_WORK(&ser->ser_alarm_work, rtw89_ser_alarm_work);
747 return 0;
748 }
749
rtw89_ser_deinit(struct rtw89_dev * rtwdev)750 int rtw89_ser_deinit(struct rtw89_dev *rtwdev)
751 {
752 struct rtw89_ser *ser = (struct rtw89_ser *)&rtwdev->ser;
753
754 set_bit(RTW89_SER_DRV_STOP_RUN, ser->flags);
755 cancel_delayed_work_sync(&ser->ser_alarm_work);
756 cancel_work_sync(&ser->ser_hdl_work);
757 clear_bit(RTW89_SER_DRV_STOP_RUN, ser->flags);
758 return 0;
759 }
760
rtw89_ser_recfg_done(struct rtw89_dev * rtwdev)761 void rtw89_ser_recfg_done(struct rtw89_dev *rtwdev)
762 {
763 ser_send_msg(&rtwdev->ser, SER_EV_L2_RECFG_DONE);
764 }
765
rtw89_ser_notify(struct rtw89_dev * rtwdev,u32 err)766 int rtw89_ser_notify(struct rtw89_dev *rtwdev, u32 err)
767 {
768 u8 event = SER_EV_NONE;
769
770 rtw89_info(rtwdev, "SER catches error: 0x%x\n", err);
771
772 switch (err) {
773 case MAC_AX_ERR_L1_PREERR_DMAC: /* pre-M0 */
774 event = SER_EV_L1_RESET_PREPARE;
775 break;
776 case MAC_AX_ERR_L1_ERR_DMAC:
777 case MAC_AX_ERR_L0_PROMOTE_TO_L1:
778 event = SER_EV_L1_RESET; /* M1 */
779 break;
780 case MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE:
781 event = SER_EV_DO_RECOVERY; /* M3 */
782 break;
783 case MAC_AX_ERR_L1_RESET_RECOVERY_DONE:
784 event = SER_EV_MAC_RESET_DONE; /* M5 */
785 break;
786 case MAC_AX_ERR_L0_ERR_CMAC0:
787 case MAC_AX_ERR_L0_ERR_CMAC1:
788 case MAC_AX_ERR_L0_RESET_DONE:
789 event = SER_EV_L0_RESET;
790 break;
791 default:
792 if (err == MAC_AX_ERR_L1_PROMOTE_TO_L2 ||
793 (err >= MAC_AX_ERR_L2_ERR_AH_DMA &&
794 err <= MAC_AX_GET_ERR_MAX))
795 event = SER_EV_L2_RESET;
796 break;
797 }
798
799 if (event == SER_EV_NONE) {
800 rtw89_warn(rtwdev, "SER cannot recognize error: 0x%x\n", err);
801 return -EINVAL;
802 }
803
804 ser_send_msg(&rtwdev->ser, event);
805 return 0;
806 }
807 EXPORT_SYMBOL(rtw89_ser_notify);
808