1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
3
4 #include "wifi.h"
5 #include "core.h"
6 #include "pci.h"
7 #include "base.h"
8 #include "ps.h"
9 #include "efuse.h"
10 #include <linux/interrupt.h>
11 #include <linux/export.h>
12 #include <linux/module.h>
13
14 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
15 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
16 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
17 MODULE_LICENSE("GPL");
18 MODULE_DESCRIPTION("PCI basic driver for rtlwifi");
19
20 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
21 INTEL_VENDOR_ID,
22 ATI_VENDOR_ID,
23 AMD_VENDOR_ID,
24 SIS_VENDOR_ID
25 };
26
27 static const u8 ac_to_hwq[] = {
28 VO_QUEUE,
29 VI_QUEUE,
30 BE_QUEUE,
31 BK_QUEUE
32 };
33
_rtl_mac_to_hwqueue(struct ieee80211_hw * hw,struct sk_buff * skb)34 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, struct sk_buff *skb)
35 {
36 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
37 __le16 fc = rtl_get_fc(skb);
38 u8 queue_index = skb_get_queue_mapping(skb);
39 struct ieee80211_hdr *hdr;
40
41 if (unlikely(ieee80211_is_beacon(fc)))
42 return BEACON_QUEUE;
43 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
44 return MGNT_QUEUE;
45 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
46 if (ieee80211_is_nullfunc(fc))
47 return HIGH_QUEUE;
48 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
49 hdr = rtl_get_hdr(skb);
50
51 if (is_multicast_ether_addr(hdr->addr1) ||
52 is_broadcast_ether_addr(hdr->addr1))
53 return HIGH_QUEUE;
54 }
55
56 return ac_to_hwq[queue_index];
57 }
58
59 /* Update PCI dependent default settings*/
_rtl_pci_update_default_setting(struct ieee80211_hw * hw)60 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
61 {
62 struct rtl_priv *rtlpriv = rtl_priv(hw);
63 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
64 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
65 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
66 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
67 u8 init_aspm;
68
69 ppsc->reg_rfps_level = 0;
70 ppsc->support_aspm = false;
71
72 /*Update PCI ASPM setting */
73 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
74 switch (rtlpci->const_pci_aspm) {
75 case 0:
76 /*No ASPM */
77 break;
78
79 case 1:
80 /*ASPM dynamically enabled/disable. */
81 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
82 break;
83
84 case 2:
85 /*ASPM with Clock Req dynamically enabled/disable. */
86 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
87 RT_RF_OFF_LEVL_CLK_REQ);
88 break;
89
90 case 3:
91 /* Always enable ASPM and Clock Req
92 * from initialization to halt.
93 */
94 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
95 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
96 RT_RF_OFF_LEVL_CLK_REQ);
97 break;
98
99 case 4:
100 /* Always enable ASPM without Clock Req
101 * from initialization to halt.
102 */
103 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
104 RT_RF_OFF_LEVL_CLK_REQ);
105 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
106 break;
107 }
108
109 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
110
111 /*Update Radio OFF setting */
112 switch (rtlpci->const_hwsw_rfoff_d3) {
113 case 1:
114 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
115 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
116 break;
117
118 case 2:
119 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
120 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
121 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
122 break;
123
124 case 3:
125 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
126 break;
127 }
128
129 /*Set HW definition to determine if it supports ASPM. */
130 switch (rtlpci->const_support_pciaspm) {
131 case 0:
132 /*Not support ASPM. */
133 ppsc->support_aspm = false;
134 break;
135 case 1:
136 /*Support ASPM. */
137 ppsc->support_aspm = true;
138 ppsc->support_backdoor = true;
139 break;
140 case 2:
141 /*ASPM value set by chipset. */
142 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
143 ppsc->support_aspm = true;
144 break;
145 default:
146 pr_err("switch case %#x not processed\n",
147 rtlpci->const_support_pciaspm);
148 break;
149 }
150
151 /* toshiba aspm issue, toshiba will set aspm selfly
152 * so we should not set aspm in driver
153 */
154 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
155 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
156 init_aspm == 0x43)
157 ppsc->support_aspm = false;
158
159 /* RTL8723BE found on some ASUSTek laptops, such as F441U and
160 * X555UQ with subsystem ID 11ad:1723 are known to output large
161 * amounts of PCIe AER errors during and after boot up, causing
162 * heavy lags, poor network throughput, and occasional lock-ups.
163 */
164 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8723BE &&
165 (rtlpci->pdev->subsystem_vendor == 0x11ad &&
166 rtlpci->pdev->subsystem_device == 0x1723))
167 ppsc->support_aspm = false;
168 }
169
_rtl_pci_platform_switch_device_pci_aspm(struct ieee80211_hw * hw,u8 value)170 static bool _rtl_pci_platform_switch_device_pci_aspm(
171 struct ieee80211_hw *hw,
172 u8 value)
173 {
174 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
175 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
176
177 value &= PCI_EXP_LNKCTL_ASPMC;
178
179 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
180 value |= PCI_EXP_LNKCTL_CCC;
181
182 pcie_capability_clear_and_set_word(rtlpci->pdev, PCI_EXP_LNKCTL,
183 PCI_EXP_LNKCTL_ASPMC | value,
184 value);
185
186 return false;
187 }
188
189 /* @value is PCI_EXP_LNKCTL_CLKREQ_EN or 0 to enable/disable clk request. */
_rtl_pci_switch_clk_req(struct ieee80211_hw * hw,u16 value)190 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u16 value)
191 {
192 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
193 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
194
195 value &= PCI_EXP_LNKCTL_CLKREQ_EN;
196
197 pcie_capability_clear_and_set_word(rtlpci->pdev, PCI_EXP_LNKCTL,
198 PCI_EXP_LNKCTL_CLKREQ_EN,
199 value);
200
201 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
202 udelay(100);
203 }
204
205 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
rtl_pci_disable_aspm(struct ieee80211_hw * hw)206 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
207 {
208 struct rtl_priv *rtlpriv = rtl_priv(hw);
209 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
210 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
211 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
212 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
213 /*Retrieve original configuration settings. */
214 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
215 u16 aspmlevel = 0;
216 u8 tmp_u1b = 0;
217
218 if (!ppsc->support_aspm)
219 return;
220
221 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
222 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
223 "PCI(Bridge) UNKNOWN\n");
224
225 return;
226 }
227
228 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
229 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
230 _rtl_pci_switch_clk_req(hw, 0x0);
231 }
232
233 /*for promising device will in L0 state after an I/O. */
234 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
235
236 /*Set corresponding value. */
237 aspmlevel |= BIT(0) | BIT(1);
238 linkctrl_reg &= ~aspmlevel;
239
240 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
241 }
242
243 /*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
244 *power saving We should follow the sequence to enable
245 *RTL8192SE first then enable Pci Bridge ASPM
246 *or the system will show bluescreen.
247 */
rtl_pci_enable_aspm(struct ieee80211_hw * hw)248 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
249 {
250 struct rtl_priv *rtlpriv = rtl_priv(hw);
251 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
252 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
253 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
254 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
255 u16 aspmlevel;
256 u8 u_device_aspmsetting;
257
258 if (!ppsc->support_aspm)
259 return;
260
261 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
262 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
263 "PCI(Bridge) UNKNOWN\n");
264 return;
265 }
266
267 /*Get ASPM level (with/without Clock Req) */
268 aspmlevel = rtlpci->const_devicepci_aspm_setting;
269 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
270
271 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
272 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
273
274 u_device_aspmsetting |= aspmlevel;
275
276 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
277
278 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
279 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
280 RT_RF_OFF_LEVL_CLK_REQ) ?
281 PCI_EXP_LNKCTL_CLKREQ_EN : 0);
282 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
283 }
284 udelay(100);
285 }
286
rtl_pci_get_amd_l1_patch(struct ieee80211_hw * hw)287 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
288 {
289 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
290
291 bool status = false;
292 u8 offset_e0;
293 unsigned int offset_e4;
294
295 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
296
297 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
298
299 if (offset_e0 == 0xA0) {
300 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
301 if (offset_e4 & BIT(23))
302 status = true;
303 }
304
305 return status;
306 }
307
rtl_pci_parse_configuration(struct pci_dev * pdev,struct ieee80211_hw * hw)308 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
309 struct ieee80211_hw *hw)
310 {
311 struct rtl_priv *rtlpriv = rtl_priv(hw);
312 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
313
314 u8 tmp;
315 u16 linkctrl_reg;
316
317 /*Link Control Register */
318 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
319 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
320
321 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
322 pcipriv->ndis_adapter.linkctrl_reg);
323
324 pci_read_config_byte(pdev, 0x98, &tmp);
325 tmp |= BIT(4);
326 pci_write_config_byte(pdev, 0x98, tmp);
327
328 tmp = 0x17;
329 pci_write_config_byte(pdev, 0x70f, tmp);
330 }
331
rtl_pci_init_aspm(struct ieee80211_hw * hw)332 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
333 {
334 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
335
336 _rtl_pci_update_default_setting(hw);
337
338 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
339 /*Always enable ASPM & Clock Req. */
340 rtl_pci_enable_aspm(hw);
341 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
342 }
343 }
344
_rtl_pci_io_handler_init(struct device * dev,struct ieee80211_hw * hw)345 static void _rtl_pci_io_handler_init(struct device *dev,
346 struct ieee80211_hw *hw)
347 {
348 struct rtl_priv *rtlpriv = rtl_priv(hw);
349
350 rtlpriv->io.dev = dev;
351
352 rtlpriv->io.write8_async = pci_write8_async;
353 rtlpriv->io.write16_async = pci_write16_async;
354 rtlpriv->io.write32_async = pci_write32_async;
355
356 rtlpriv->io.read8_sync = pci_read8_sync;
357 rtlpriv->io.read16_sync = pci_read16_sync;
358 rtlpriv->io.read32_sync = pci_read32_sync;
359 }
360
_rtl_update_earlymode_info(struct ieee80211_hw * hw,struct sk_buff * skb,struct rtl_tcb_desc * tcb_desc,u8 tid)361 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
362 struct sk_buff *skb,
363 struct rtl_tcb_desc *tcb_desc, u8 tid)
364 {
365 struct rtl_priv *rtlpriv = rtl_priv(hw);
366 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
367 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
368 struct sk_buff *next_skb;
369 u8 additionlen = FCS_LEN;
370
371 /* here open is 4, wep/tkip is 8, aes is 12*/
372 if (info->control.hw_key)
373 additionlen += info->control.hw_key->icv_len;
374
375 /* The most skb num is 6 */
376 tcb_desc->empkt_num = 0;
377 spin_lock_bh(&rtlpriv->locks.waitq_lock);
378 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
379 struct ieee80211_tx_info *next_info;
380
381 next_info = IEEE80211_SKB_CB(next_skb);
382 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
383 tcb_desc->empkt_len[tcb_desc->empkt_num] =
384 next_skb->len + additionlen;
385 tcb_desc->empkt_num++;
386 } else {
387 break;
388 }
389
390 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
391 next_skb))
392 break;
393
394 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
395 break;
396 }
397 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
398
399 return true;
400 }
401
402 /* just for early mode now */
_rtl_pci_tx_chk_waitq(struct ieee80211_hw * hw)403 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
404 {
405 struct rtl_priv *rtlpriv = rtl_priv(hw);
406 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
407 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
408 struct sk_buff *skb = NULL;
409 struct ieee80211_tx_info *info = NULL;
410 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
411 int tid;
412
413 if (!rtlpriv->rtlhal.earlymode_enable)
414 return;
415
416 /* we just use em for BE/BK/VI/VO */
417 for (tid = 7; tid >= 0; tid--) {
418 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
419 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
420
421 while (!mac->act_scanning &&
422 rtlpriv->psc.rfpwr_state == ERFON) {
423 struct rtl_tcb_desc tcb_desc;
424
425 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
426
427 spin_lock(&rtlpriv->locks.waitq_lock);
428 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
429 (ring->entries - skb_queue_len(&ring->queue) >
430 rtlhal->max_earlymode_num)) {
431 skb = skb_dequeue(&mac->skb_waitq[tid]);
432 } else {
433 spin_unlock(&rtlpriv->locks.waitq_lock);
434 break;
435 }
436 spin_unlock(&rtlpriv->locks.waitq_lock);
437
438 /* Some macaddr can't do early mode. like
439 * multicast/broadcast/no_qos data
440 */
441 info = IEEE80211_SKB_CB(skb);
442 if (info->flags & IEEE80211_TX_CTL_AMPDU)
443 _rtl_update_earlymode_info(hw, skb,
444 &tcb_desc, tid);
445
446 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
447 }
448 }
449 }
450
_rtl_pci_tx_isr(struct ieee80211_hw * hw,int prio)451 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
452 {
453 struct rtl_priv *rtlpriv = rtl_priv(hw);
454 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
455
456 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
457
458 while (skb_queue_len(&ring->queue)) {
459 struct sk_buff *skb;
460 struct ieee80211_tx_info *info;
461 __le16 fc;
462 u8 tid;
463 u8 *entry;
464
465 if (rtlpriv->use_new_trx_flow)
466 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
467 else
468 entry = (u8 *)(&ring->desc[ring->idx]);
469
470 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
471 return;
472 ring->idx = (ring->idx + 1) % ring->entries;
473
474 skb = __skb_dequeue(&ring->queue);
475 dma_unmap_single(&rtlpci->pdev->dev,
476 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
477 true, HW_DESC_TXBUFF_ADDR),
478 skb->len, DMA_TO_DEVICE);
479
480 /* remove early mode header */
481 if (rtlpriv->rtlhal.earlymode_enable)
482 skb_pull(skb, EM_HDR_LEN);
483
484 rtl_dbg(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
485 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
486 ring->idx,
487 skb_queue_len(&ring->queue),
488 *(u16 *)(skb->data + 22));
489
490 if (prio == TXCMD_QUEUE) {
491 dev_kfree_skb(skb);
492 goto tx_status_ok;
493 }
494
495 /* for sw LPS, just after NULL skb send out, we can
496 * sure AP knows we are sleeping, we should not let
497 * rf sleep
498 */
499 fc = rtl_get_fc(skb);
500 if (ieee80211_is_nullfunc(fc)) {
501 if (ieee80211_has_pm(fc)) {
502 rtlpriv->mac80211.offchan_delay = true;
503 rtlpriv->psc.state_inap = true;
504 } else {
505 rtlpriv->psc.state_inap = false;
506 }
507 }
508 if (ieee80211_is_action(fc)) {
509 struct ieee80211_mgmt *action_frame =
510 (struct ieee80211_mgmt *)skb->data;
511 if (action_frame->u.action.u.ht_smps.action ==
512 WLAN_HT_ACTION_SMPS) {
513 dev_kfree_skb(skb);
514 goto tx_status_ok;
515 }
516 }
517
518 /* update tid tx pkt num */
519 tid = rtl_get_tid(skb);
520 if (tid <= 7)
521 rtlpriv->link_info.tidtx_inperiod[tid]++;
522
523 info = IEEE80211_SKB_CB(skb);
524
525 if (likely(!ieee80211_is_nullfunc(fc))) {
526 ieee80211_tx_info_clear_status(info);
527 info->flags |= IEEE80211_TX_STAT_ACK;
528 /*info->status.rates[0].count = 1; */
529 ieee80211_tx_status_irqsafe(hw, skb);
530 } else {
531 rtl_tx_ackqueue(hw, skb);
532 }
533
534 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) {
535 rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG,
536 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n",
537 prio, ring->idx,
538 skb_queue_len(&ring->queue));
539
540 ieee80211_wake_queue(hw, skb_get_queue_mapping(skb));
541 }
542 tx_status_ok:
543 skb = NULL;
544 }
545
546 if (((rtlpriv->link_info.num_rx_inperiod +
547 rtlpriv->link_info.num_tx_inperiod) > 8) ||
548 rtlpriv->link_info.num_rx_inperiod > 2)
549 rtl_lps_leave(hw, false);
550 }
551
_rtl_pci_init_one_rxdesc(struct ieee80211_hw * hw,struct sk_buff * new_skb,u8 * entry,int rxring_idx,int desc_idx)552 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
553 struct sk_buff *new_skb, u8 *entry,
554 int rxring_idx, int desc_idx)
555 {
556 struct rtl_priv *rtlpriv = rtl_priv(hw);
557 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
558 u32 bufferaddress;
559 u8 tmp_one = 1;
560 struct sk_buff *skb;
561
562 if (likely(new_skb)) {
563 skb = new_skb;
564 goto remap;
565 }
566 skb = dev_alloc_skb(rtlpci->rxbuffersize);
567 if (!skb)
568 return 0;
569
570 remap:
571 /* just set skb->cb to mapping addr for pci_unmap_single use */
572 *((dma_addr_t *)skb->cb) =
573 dma_map_single(&rtlpci->pdev->dev, skb_tail_pointer(skb),
574 rtlpci->rxbuffersize, DMA_FROM_DEVICE);
575 bufferaddress = *((dma_addr_t *)skb->cb);
576 if (dma_mapping_error(&rtlpci->pdev->dev, bufferaddress))
577 return 0;
578 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
579 if (rtlpriv->use_new_trx_flow) {
580 /* skb->cb may be 64 bit address */
581 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
582 HW_DESC_RX_PREPARE,
583 (u8 *)(dma_addr_t *)skb->cb);
584 } else {
585 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
586 HW_DESC_RXBUFF_ADDR,
587 (u8 *)&bufferaddress);
588 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
589 HW_DESC_RXPKT_LEN,
590 (u8 *)&rtlpci->rxbuffersize);
591 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
592 HW_DESC_RXOWN,
593 (u8 *)&tmp_one);
594 }
595 return 1;
596 }
597
598 /* inorder to receive 8K AMSDU we have set skb to
599 * 9100bytes in init rx ring, but if this packet is
600 * not a AMSDU, this large packet will be sent to
601 * TCP/IP directly, this cause big packet ping fail
602 * like: "ping -s 65507", so here we will realloc skb
603 * based on the true size of packet, Mac80211
604 * Probably will do it better, but does not yet.
605 *
606 * Some platform will fail when alloc skb sometimes.
607 * in this condition, we will send the old skb to
608 * mac80211 directly, this will not cause any other
609 * issues, but only this packet will be lost by TCP/IP
610 */
_rtl_pci_rx_to_mac80211(struct ieee80211_hw * hw,struct sk_buff * skb,struct ieee80211_rx_status rx_status)611 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw,
612 struct sk_buff *skb,
613 struct ieee80211_rx_status rx_status)
614 {
615 if (unlikely(!rtl_action_proc(hw, skb, false))) {
616 dev_kfree_skb_any(skb);
617 } else {
618 struct sk_buff *uskb = NULL;
619
620 uskb = dev_alloc_skb(skb->len + 128);
621 if (likely(uskb)) {
622 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
623 sizeof(rx_status));
624 skb_put_data(uskb, skb->data, skb->len);
625 dev_kfree_skb_any(skb);
626 ieee80211_rx_irqsafe(hw, uskb);
627 } else {
628 ieee80211_rx_irqsafe(hw, skb);
629 }
630 }
631 }
632
633 /*hsisr interrupt handler*/
_rtl_pci_hs_interrupt(struct ieee80211_hw * hw)634 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw)
635 {
636 struct rtl_priv *rtlpriv = rtl_priv(hw);
637 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
638
639 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
640 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
641 rtlpci->sys_irq_mask);
642 }
643
_rtl_pci_rx_interrupt(struct ieee80211_hw * hw)644 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
645 {
646 struct rtl_priv *rtlpriv = rtl_priv(hw);
647 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
648 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE;
649 struct ieee80211_rx_status rx_status = { 0 };
650 unsigned int count = rtlpci->rxringcount;
651 u8 own;
652 u8 tmp_one;
653 bool unicast = false;
654 u8 hw_queue = 0;
655 unsigned int rx_remained_cnt = 0;
656 struct rtl_stats stats = {
657 .signal = 0,
658 .rate = 0,
659 };
660
661 /*RX NORMAL PKT */
662 while (count--) {
663 struct ieee80211_hdr *hdr;
664 __le16 fc;
665 u16 len;
666 /*rx buffer descriptor */
667 struct rtl_rx_buffer_desc *buffer_desc = NULL;
668 /*if use new trx flow, it means wifi info */
669 struct rtl_rx_desc *pdesc = NULL;
670 /*rx pkt */
671 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[
672 rtlpci->rx_ring[rxring_idx].idx];
673 struct sk_buff *new_skb;
674
675 if (rtlpriv->use_new_trx_flow) {
676 if (rx_remained_cnt == 0)
677 rx_remained_cnt =
678 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
679 hw_queue);
680 if (rx_remained_cnt == 0)
681 return;
682 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[
683 rtlpci->rx_ring[rxring_idx].idx];
684 pdesc = (struct rtl_rx_desc *)skb->data;
685 } else { /* rx descriptor */
686 pdesc = &rtlpci->rx_ring[rxring_idx].desc[
687 rtlpci->rx_ring[rxring_idx].idx];
688
689 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
690 false,
691 HW_DESC_OWN);
692 if (own) /* wait data to be filled by hardware */
693 return;
694 }
695
696 /* Reaching this point means: data is filled already
697 * AAAAAAttention !!!
698 * We can NOT access 'skb' before 'pci_unmap_single'
699 */
700 dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb),
701 rtlpci->rxbuffersize, DMA_FROM_DEVICE);
702
703 /* get a new skb - if fail, old one will be reused */
704 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
705 if (unlikely(!new_skb))
706 goto no_new;
707 memset(&rx_status, 0, sizeof(rx_status));
708 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
709 &rx_status, (u8 *)pdesc, skb);
710
711 if (rtlpriv->use_new_trx_flow)
712 rtlpriv->cfg->ops->rx_check_dma_ok(hw,
713 (u8 *)buffer_desc,
714 hw_queue);
715
716 len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false,
717 HW_DESC_RXPKT_LEN);
718
719 if (skb->end - skb->tail > len) {
720 skb_put(skb, len);
721 if (rtlpriv->use_new_trx_flow)
722 skb_reserve(skb, stats.rx_drvinfo_size +
723 stats.rx_bufshift + 24);
724 else
725 skb_reserve(skb, stats.rx_drvinfo_size +
726 stats.rx_bufshift);
727 } else {
728 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
729 "skb->end - skb->tail = %d, len is %d\n",
730 skb->end - skb->tail, len);
731 dev_kfree_skb_any(skb);
732 goto new_trx_end;
733 }
734 /* handle command packet here */
735 if (stats.packet_report_type == C2H_PACKET) {
736 rtl_c2hcmd_enqueue(hw, skb);
737 goto new_trx_end;
738 }
739
740 /* NOTICE This can not be use for mac80211,
741 * this is done in mac80211 code,
742 * if done here sec DHCP will fail
743 * skb_trim(skb, skb->len - 4);
744 */
745
746 hdr = rtl_get_hdr(skb);
747 fc = rtl_get_fc(skb);
748
749 if (!stats.crc && !stats.hwerror && (skb->len > FCS_LEN)) {
750 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
751 sizeof(rx_status));
752
753 if (is_broadcast_ether_addr(hdr->addr1)) {
754 ;/*TODO*/
755 } else if (is_multicast_ether_addr(hdr->addr1)) {
756 ;/*TODO*/
757 } else {
758 unicast = true;
759 rtlpriv->stats.rxbytesunicast += skb->len;
760 }
761 rtl_is_special_data(hw, skb, false, true);
762
763 if (ieee80211_is_data(fc)) {
764 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
765 if (unicast)
766 rtlpriv->link_info.num_rx_inperiod++;
767 }
768
769 rtl_collect_scan_list(hw, skb);
770
771 /* static bcn for roaming */
772 rtl_beacon_statistic(hw, skb);
773 rtl_p2p_info(hw, (void *)skb->data, skb->len);
774 /* for sw lps */
775 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
776 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
777 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP &&
778 rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G &&
779 (ieee80211_is_beacon(fc) ||
780 ieee80211_is_probe_resp(fc))) {
781 dev_kfree_skb_any(skb);
782 } else {
783 _rtl_pci_rx_to_mac80211(hw, skb, rx_status);
784 }
785 } else {
786 /* drop packets with errors or those too short */
787 dev_kfree_skb_any(skb);
788 }
789 new_trx_end:
790 if (rtlpriv->use_new_trx_flow) {
791 rtlpci->rx_ring[hw_queue].next_rx_rp += 1;
792 rtlpci->rx_ring[hw_queue].next_rx_rp %=
793 RTL_PCI_MAX_RX_COUNT;
794
795 rx_remained_cnt--;
796 rtl_write_word(rtlpriv, 0x3B4,
797 rtlpci->rx_ring[hw_queue].next_rx_rp);
798 }
799 if (((rtlpriv->link_info.num_rx_inperiod +
800 rtlpriv->link_info.num_tx_inperiod) > 8) ||
801 rtlpriv->link_info.num_rx_inperiod > 2)
802 rtl_lps_leave(hw, false);
803 skb = new_skb;
804 no_new:
805 if (rtlpriv->use_new_trx_flow) {
806 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc,
807 rxring_idx,
808 rtlpci->rx_ring[rxring_idx].idx);
809 } else {
810 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc,
811 rxring_idx,
812 rtlpci->rx_ring[rxring_idx].idx);
813 if (rtlpci->rx_ring[rxring_idx].idx ==
814 rtlpci->rxringcount - 1)
815 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc,
816 false,
817 HW_DESC_RXERO,
818 (u8 *)&tmp_one);
819 }
820 rtlpci->rx_ring[rxring_idx].idx =
821 (rtlpci->rx_ring[rxring_idx].idx + 1) %
822 rtlpci->rxringcount;
823 }
824 }
825
_rtl_pci_interrupt(int irq,void * dev_id)826 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
827 {
828 struct ieee80211_hw *hw = dev_id;
829 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
830 struct rtl_priv *rtlpriv = rtl_priv(hw);
831 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
832 unsigned long flags;
833 struct rtl_int intvec = {0};
834
835 irqreturn_t ret = IRQ_HANDLED;
836
837 if (rtlpci->irq_enabled == 0)
838 return ret;
839
840 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
841 rtlpriv->cfg->ops->disable_interrupt(hw);
842
843 /*read ISR: 4/8bytes */
844 rtlpriv->cfg->ops->interrupt_recognized(hw, &intvec);
845
846 /*Shared IRQ or HW disappeared */
847 if (!intvec.inta || intvec.inta == 0xffff)
848 goto done;
849
850 /*<1> beacon related */
851 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK])
852 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
853 "beacon ok interrupt!\n");
854
855 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDER]))
856 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
857 "beacon err interrupt!\n");
858
859 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BDOK])
860 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
861
862 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
863 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
864 "prepare beacon for interrupt!\n");
865 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
866 }
867
868 /*<2> Tx related */
869 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
870 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
871
872 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
873 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
874 "Manage ok interrupt!\n");
875 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
876 }
877
878 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
879 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
880 "HIGH_QUEUE ok interrupt!\n");
881 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
882 }
883
884 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
885 rtlpriv->link_info.num_tx_inperiod++;
886
887 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
888 "BK Tx OK interrupt!\n");
889 _rtl_pci_tx_isr(hw, BK_QUEUE);
890 }
891
892 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
893 rtlpriv->link_info.num_tx_inperiod++;
894
895 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
896 "BE TX OK interrupt!\n");
897 _rtl_pci_tx_isr(hw, BE_QUEUE);
898 }
899
900 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
901 rtlpriv->link_info.num_tx_inperiod++;
902
903 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
904 "VI TX OK interrupt!\n");
905 _rtl_pci_tx_isr(hw, VI_QUEUE);
906 }
907
908 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
909 rtlpriv->link_info.num_tx_inperiod++;
910
911 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
912 "Vo TX OK interrupt!\n");
913 _rtl_pci_tx_isr(hw, VO_QUEUE);
914 }
915
916 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
917 if (intvec.intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) {
918 rtlpriv->link_info.num_tx_inperiod++;
919
920 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
921 "H2C TX OK interrupt!\n");
922 _rtl_pci_tx_isr(hw, H2C_QUEUE);
923 }
924 }
925
926 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
927 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
928 rtlpriv->link_info.num_tx_inperiod++;
929
930 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
931 "CMD TX OK interrupt!\n");
932 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
933 }
934 }
935
936 /*<3> Rx related */
937 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
938 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
939 _rtl_pci_rx_interrupt(hw);
940 }
941
942 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
943 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
944 "rx descriptor unavailable!\n");
945 _rtl_pci_rx_interrupt(hw);
946 }
947
948 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
949 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
950 _rtl_pci_rx_interrupt(hw);
951 }
952
953 /*<4> fw related*/
954 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
955 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
956 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
957 "firmware interrupt!\n");
958 queue_delayed_work(rtlpriv->works.rtl_wq,
959 &rtlpriv->works.fwevt_wq, 0);
960 }
961 }
962
963 /*<5> hsisr related*/
964 /* Only 8188EE & 8723BE Supported.
965 * If Other ICs Come in, System will corrupt,
966 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR]
967 * are not initialized
968 */
969 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE ||
970 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
971 if (unlikely(intvec.inta &
972 rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
973 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
974 "hsisr interrupt!\n");
975 _rtl_pci_hs_interrupt(hw);
976 }
977 }
978
979 if (rtlpriv->rtlhal.earlymode_enable)
980 tasklet_schedule(&rtlpriv->works.irq_tasklet);
981
982 done:
983 rtlpriv->cfg->ops->enable_interrupt(hw);
984 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
985 return ret;
986 }
987
_rtl_pci_irq_tasklet(struct tasklet_struct * t)988 static void _rtl_pci_irq_tasklet(struct tasklet_struct *t)
989 {
990 struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t, works.irq_tasklet);
991 struct ieee80211_hw *hw = rtlpriv->hw;
992 _rtl_pci_tx_chk_waitq(hw);
993 }
994
_rtl_pci_prepare_bcn_tasklet(struct tasklet_struct * t)995 static void _rtl_pci_prepare_bcn_tasklet(struct tasklet_struct *t)
996 {
997 struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t,
998 works.irq_prepare_bcn_tasklet);
999 struct ieee80211_hw *hw = rtlpriv->hw;
1000 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1001 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1002 struct rtl8192_tx_ring *ring = NULL;
1003 struct ieee80211_hdr *hdr = NULL;
1004 struct ieee80211_tx_info *info = NULL;
1005 struct sk_buff *pskb = NULL;
1006 struct rtl_tx_desc *pdesc = NULL;
1007 struct rtl_tcb_desc tcb_desc;
1008 /*This is for new trx flow*/
1009 struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
1010 u8 temp_one = 1;
1011 u8 *entry;
1012
1013 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
1014 ring = &rtlpci->tx_ring[BEACON_QUEUE];
1015 pskb = __skb_dequeue(&ring->queue);
1016 if (rtlpriv->use_new_trx_flow)
1017 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1018 else
1019 entry = (u8 *)(&ring->desc[ring->idx]);
1020 if (pskb) {
1021 dma_unmap_single(&rtlpci->pdev->dev,
1022 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1023 true, HW_DESC_TXBUFF_ADDR),
1024 pskb->len, DMA_TO_DEVICE);
1025 kfree_skb(pskb);
1026 }
1027
1028 /*NB: the beacon data buffer must be 32-bit aligned. */
1029 pskb = ieee80211_beacon_get(hw, mac->vif, 0);
1030 if (!pskb)
1031 return;
1032 hdr = rtl_get_hdr(pskb);
1033 info = IEEE80211_SKB_CB(pskb);
1034 pdesc = &ring->desc[0];
1035 if (rtlpriv->use_new_trx_flow)
1036 pbuffer_desc = &ring->buffer_desc[0];
1037
1038 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1039 (u8 *)pbuffer_desc, info, NULL, pskb,
1040 BEACON_QUEUE, &tcb_desc);
1041
1042 __skb_queue_tail(&ring->queue, pskb);
1043
1044 if (rtlpriv->use_new_trx_flow) {
1045 temp_one = 4;
1046 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true,
1047 HW_DESC_OWN, (u8 *)&temp_one);
1048 } else {
1049 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN,
1050 &temp_one);
1051 }
1052 }
1053
_rtl_pci_init_trx_var(struct ieee80211_hw * hw)1054 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1055 {
1056 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1057 struct rtl_priv *rtlpriv = rtl_priv(hw);
1058 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1059 u8 i;
1060 u16 desc_num;
1061
1062 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
1063 desc_num = TX_DESC_NUM_92E;
1064 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE)
1065 desc_num = TX_DESC_NUM_8822B;
1066 else
1067 desc_num = RT_TXDESC_NUM;
1068
1069 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1070 rtlpci->txringcount[i] = desc_num;
1071
1072 /*we just alloc 2 desc for beacon queue,
1073 *because we just need first desc in hw beacon.
1074 */
1075 rtlpci->txringcount[BEACON_QUEUE] = 2;
1076
1077 /*BE queue need more descriptor for performance
1078 *consideration or, No more tx desc will happen,
1079 *and may cause mac80211 mem leakage.
1080 */
1081 if (!rtl_priv(hw)->use_new_trx_flow)
1082 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1083
1084 rtlpci->rxbuffersize = 9100; /*2048/1024; */
1085 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1086 }
1087
_rtl_pci_init_struct(struct ieee80211_hw * hw,struct pci_dev * pdev)1088 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1089 struct pci_dev *pdev)
1090 {
1091 struct rtl_priv *rtlpriv = rtl_priv(hw);
1092 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1093 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1094 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1095
1096 rtlpci->up_first_time = true;
1097 rtlpci->being_init_adapter = false;
1098
1099 rtlhal->hw = hw;
1100 rtlpci->pdev = pdev;
1101
1102 /*Tx/Rx related var */
1103 _rtl_pci_init_trx_var(hw);
1104
1105 /*IBSS*/
1106 mac->beacon_interval = 100;
1107
1108 /*AMPDU*/
1109 mac->min_space_cfg = 0;
1110 mac->max_mss_density = 0;
1111 /*set sane AMPDU defaults */
1112 mac->current_ampdu_density = 7;
1113 mac->current_ampdu_factor = 3;
1114
1115 /*Retry Limit*/
1116 mac->retry_short = 7;
1117 mac->retry_long = 7;
1118
1119 /*QOS*/
1120 rtlpci->acm_method = EACMWAY2_SW;
1121
1122 /*task */
1123 tasklet_setup(&rtlpriv->works.irq_tasklet, _rtl_pci_irq_tasklet);
1124 tasklet_setup(&rtlpriv->works.irq_prepare_bcn_tasklet,
1125 _rtl_pci_prepare_bcn_tasklet);
1126 INIT_WORK(&rtlpriv->works.lps_change_work,
1127 rtl_lps_change_work_callback);
1128 }
1129
_rtl_pci_init_tx_ring(struct ieee80211_hw * hw,unsigned int prio,unsigned int entries)1130 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1131 unsigned int prio, unsigned int entries)
1132 {
1133 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1134 struct rtl_priv *rtlpriv = rtl_priv(hw);
1135 struct rtl_tx_buffer_desc *buffer_desc;
1136 struct rtl_tx_desc *desc;
1137 dma_addr_t buffer_desc_dma, desc_dma;
1138 u32 nextdescaddress;
1139 int i;
1140
1141 /* alloc tx buffer desc for new trx flow*/
1142 if (rtlpriv->use_new_trx_flow) {
1143 buffer_desc =
1144 dma_alloc_coherent(&rtlpci->pdev->dev,
1145 sizeof(*buffer_desc) * entries,
1146 &buffer_desc_dma, GFP_KERNEL);
1147
1148 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) {
1149 pr_err("Cannot allocate TX ring (prio = %d)\n",
1150 prio);
1151 return -ENOMEM;
1152 }
1153
1154 rtlpci->tx_ring[prio].buffer_desc = buffer_desc;
1155 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma;
1156
1157 rtlpci->tx_ring[prio].cur_tx_rp = 0;
1158 rtlpci->tx_ring[prio].cur_tx_wp = 0;
1159 }
1160
1161 /* alloc dma for this ring */
1162 desc = dma_alloc_coherent(&rtlpci->pdev->dev, sizeof(*desc) * entries,
1163 &desc_dma, GFP_KERNEL);
1164
1165 if (!desc || (unsigned long)desc & 0xFF) {
1166 pr_err("Cannot allocate TX ring (prio = %d)\n", prio);
1167 return -ENOMEM;
1168 }
1169
1170 rtlpci->tx_ring[prio].desc = desc;
1171 rtlpci->tx_ring[prio].dma = desc_dma;
1172
1173 rtlpci->tx_ring[prio].idx = 0;
1174 rtlpci->tx_ring[prio].entries = entries;
1175 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1176
1177 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1178 prio, desc);
1179
1180 /* init every desc in this ring */
1181 if (!rtlpriv->use_new_trx_flow) {
1182 for (i = 0; i < entries; i++) {
1183 nextdescaddress = (u32)desc_dma +
1184 ((i + 1) % entries) *
1185 sizeof(*desc);
1186
1187 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i],
1188 true,
1189 HW_DESC_TX_NEXTDESC_ADDR,
1190 (u8 *)&nextdescaddress);
1191 }
1192 }
1193 return 0;
1194 }
1195
_rtl_pci_init_rx_ring(struct ieee80211_hw * hw,int rxring_idx)1196 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1197 {
1198 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1199 struct rtl_priv *rtlpriv = rtl_priv(hw);
1200 int i;
1201
1202 if (rtlpriv->use_new_trx_flow) {
1203 struct rtl_rx_buffer_desc *entry = NULL;
1204 /* alloc dma for this ring */
1205 rtlpci->rx_ring[rxring_idx].buffer_desc =
1206 dma_alloc_coherent(&rtlpci->pdev->dev,
1207 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
1208 rtlpci->rxringcount,
1209 &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL);
1210 if (!rtlpci->rx_ring[rxring_idx].buffer_desc ||
1211 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) {
1212 pr_err("Cannot allocate RX ring\n");
1213 return -ENOMEM;
1214 }
1215
1216 /* init every desc in this ring */
1217 rtlpci->rx_ring[rxring_idx].idx = 0;
1218 for (i = 0; i < rtlpci->rxringcount; i++) {
1219 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i];
1220 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1221 rxring_idx, i))
1222 return -ENOMEM;
1223 }
1224 } else {
1225 struct rtl_rx_desc *entry = NULL;
1226 u8 tmp_one = 1;
1227 /* alloc dma for this ring */
1228 rtlpci->rx_ring[rxring_idx].desc =
1229 dma_alloc_coherent(&rtlpci->pdev->dev,
1230 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1231 rtlpci->rxringcount,
1232 &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL);
1233 if (!rtlpci->rx_ring[rxring_idx].desc ||
1234 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) {
1235 pr_err("Cannot allocate RX ring\n");
1236 return -ENOMEM;
1237 }
1238
1239 /* init every desc in this ring */
1240 rtlpci->rx_ring[rxring_idx].idx = 0;
1241
1242 for (i = 0; i < rtlpci->rxringcount; i++) {
1243 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1244 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1245 rxring_idx, i))
1246 return -ENOMEM;
1247 }
1248
1249 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1250 HW_DESC_RXERO, &tmp_one);
1251 }
1252 return 0;
1253 }
1254
_rtl_pci_free_tx_ring(struct ieee80211_hw * hw,unsigned int prio)1255 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1256 unsigned int prio)
1257 {
1258 struct rtl_priv *rtlpriv = rtl_priv(hw);
1259 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1260 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1261
1262 /* free every desc in this ring */
1263 while (skb_queue_len(&ring->queue)) {
1264 u8 *entry;
1265 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1266
1267 if (rtlpriv->use_new_trx_flow)
1268 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1269 else
1270 entry = (u8 *)(&ring->desc[ring->idx]);
1271
1272 dma_unmap_single(&rtlpci->pdev->dev,
1273 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1274 true, HW_DESC_TXBUFF_ADDR),
1275 skb->len, DMA_TO_DEVICE);
1276 kfree_skb(skb);
1277 ring->idx = (ring->idx + 1) % ring->entries;
1278 }
1279
1280 /* free dma of this ring */
1281 dma_free_coherent(&rtlpci->pdev->dev,
1282 sizeof(*ring->desc) * ring->entries, ring->desc,
1283 ring->dma);
1284 ring->desc = NULL;
1285 if (rtlpriv->use_new_trx_flow) {
1286 dma_free_coherent(&rtlpci->pdev->dev,
1287 sizeof(*ring->buffer_desc) * ring->entries,
1288 ring->buffer_desc, ring->buffer_desc_dma);
1289 ring->buffer_desc = NULL;
1290 }
1291 }
1292
_rtl_pci_free_rx_ring(struct ieee80211_hw * hw,int rxring_idx)1293 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1294 {
1295 struct rtl_priv *rtlpriv = rtl_priv(hw);
1296 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1297 int i;
1298
1299 /* free every desc in this ring */
1300 for (i = 0; i < rtlpci->rxringcount; i++) {
1301 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i];
1302
1303 if (!skb)
1304 continue;
1305 dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb),
1306 rtlpci->rxbuffersize, DMA_FROM_DEVICE);
1307 kfree_skb(skb);
1308 }
1309
1310 /* free dma of this ring */
1311 if (rtlpriv->use_new_trx_flow) {
1312 dma_free_coherent(&rtlpci->pdev->dev,
1313 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
1314 rtlpci->rxringcount,
1315 rtlpci->rx_ring[rxring_idx].buffer_desc,
1316 rtlpci->rx_ring[rxring_idx].dma);
1317 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL;
1318 } else {
1319 dma_free_coherent(&rtlpci->pdev->dev,
1320 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1321 rtlpci->rxringcount,
1322 rtlpci->rx_ring[rxring_idx].desc,
1323 rtlpci->rx_ring[rxring_idx].dma);
1324 rtlpci->rx_ring[rxring_idx].desc = NULL;
1325 }
1326 }
1327
_rtl_pci_init_trx_ring(struct ieee80211_hw * hw)1328 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1329 {
1330 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1331 int ret;
1332 int i, rxring_idx;
1333
1334 /* rxring_idx 0:RX_MPDU_QUEUE
1335 * rxring_idx 1:RX_CMD_QUEUE
1336 */
1337 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1338 ret = _rtl_pci_init_rx_ring(hw, rxring_idx);
1339 if (ret)
1340 return ret;
1341 }
1342
1343 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1344 ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]);
1345 if (ret)
1346 goto err_free_rings;
1347 }
1348
1349 return 0;
1350
1351 err_free_rings:
1352 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1353 _rtl_pci_free_rx_ring(hw, rxring_idx);
1354
1355 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1356 if (rtlpci->tx_ring[i].desc ||
1357 rtlpci->tx_ring[i].buffer_desc)
1358 _rtl_pci_free_tx_ring(hw, i);
1359
1360 return 1;
1361 }
1362
_rtl_pci_deinit_trx_ring(struct ieee80211_hw * hw)1363 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1364 {
1365 u32 i, rxring_idx;
1366
1367 /*free rx rings */
1368 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1369 _rtl_pci_free_rx_ring(hw, rxring_idx);
1370
1371 /*free tx rings */
1372 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1373 _rtl_pci_free_tx_ring(hw, i);
1374
1375 return 0;
1376 }
1377
rtl_pci_reset_trx_ring(struct ieee80211_hw * hw)1378 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1379 {
1380 struct rtl_priv *rtlpriv = rtl_priv(hw);
1381 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1382 int i, rxring_idx;
1383 unsigned long flags;
1384 u8 tmp_one = 1;
1385 u32 bufferaddress;
1386 /* rxring_idx 0:RX_MPDU_QUEUE */
1387 /* rxring_idx 1:RX_CMD_QUEUE */
1388 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1389 /* force the rx_ring[RX_MPDU_QUEUE/
1390 * RX_CMD_QUEUE].idx to the first one
1391 *new trx flow, do nothing
1392 */
1393 if (!rtlpriv->use_new_trx_flow &&
1394 rtlpci->rx_ring[rxring_idx].desc) {
1395 struct rtl_rx_desc *entry = NULL;
1396
1397 rtlpci->rx_ring[rxring_idx].idx = 0;
1398 for (i = 0; i < rtlpci->rxringcount; i++) {
1399 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1400 bufferaddress =
1401 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1402 false, HW_DESC_RXBUFF_ADDR);
1403 memset((u8 *)entry, 0,
1404 sizeof(*rtlpci->rx_ring
1405 [rxring_idx].desc));/*clear one entry*/
1406 if (rtlpriv->use_new_trx_flow) {
1407 rtlpriv->cfg->ops->set_desc(hw,
1408 (u8 *)entry, false,
1409 HW_DESC_RX_PREPARE,
1410 (u8 *)&bufferaddress);
1411 } else {
1412 rtlpriv->cfg->ops->set_desc(hw,
1413 (u8 *)entry, false,
1414 HW_DESC_RXBUFF_ADDR,
1415 (u8 *)&bufferaddress);
1416 rtlpriv->cfg->ops->set_desc(hw,
1417 (u8 *)entry, false,
1418 HW_DESC_RXPKT_LEN,
1419 (u8 *)&rtlpci->rxbuffersize);
1420 rtlpriv->cfg->ops->set_desc(hw,
1421 (u8 *)entry, false,
1422 HW_DESC_RXOWN,
1423 (u8 *)&tmp_one);
1424 }
1425 }
1426 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1427 HW_DESC_RXERO, (u8 *)&tmp_one);
1428 }
1429 rtlpci->rx_ring[rxring_idx].idx = 0;
1430 }
1431
1432 /*after reset, release previous pending packet,
1433 *and force the tx idx to the first one
1434 */
1435 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1436 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1437 if (rtlpci->tx_ring[i].desc ||
1438 rtlpci->tx_ring[i].buffer_desc) {
1439 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1440
1441 while (skb_queue_len(&ring->queue)) {
1442 u8 *entry;
1443 struct sk_buff *skb =
1444 __skb_dequeue(&ring->queue);
1445 if (rtlpriv->use_new_trx_flow)
1446 entry = (u8 *)(&ring->buffer_desc
1447 [ring->idx]);
1448 else
1449 entry = (u8 *)(&ring->desc[ring->idx]);
1450
1451 dma_unmap_single(&rtlpci->pdev->dev,
1452 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1453 true, HW_DESC_TXBUFF_ADDR),
1454 skb->len, DMA_TO_DEVICE);
1455 dev_kfree_skb_irq(skb);
1456 ring->idx = (ring->idx + 1) % ring->entries;
1457 }
1458
1459 if (rtlpriv->use_new_trx_flow) {
1460 rtlpci->tx_ring[i].cur_tx_rp = 0;
1461 rtlpci->tx_ring[i].cur_tx_wp = 0;
1462 }
1463
1464 ring->idx = 0;
1465 ring->entries = rtlpci->txringcount[i];
1466 }
1467 }
1468 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1469
1470 return 0;
1471 }
1472
rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct sk_buff * skb)1473 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1474 struct ieee80211_sta *sta,
1475 struct sk_buff *skb)
1476 {
1477 struct rtl_priv *rtlpriv = rtl_priv(hw);
1478 struct rtl_sta_info *sta_entry = NULL;
1479 u8 tid = rtl_get_tid(skb);
1480 __le16 fc = rtl_get_fc(skb);
1481
1482 if (!sta)
1483 return false;
1484 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1485
1486 if (!rtlpriv->rtlhal.earlymode_enable)
1487 return false;
1488 if (ieee80211_is_nullfunc(fc))
1489 return false;
1490 if (ieee80211_is_qos_nullfunc(fc))
1491 return false;
1492 if (ieee80211_is_pspoll(fc))
1493 return false;
1494 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1495 return false;
1496 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1497 return false;
1498 if (tid > 7)
1499 return false;
1500
1501 /* maybe every tid should be checked */
1502 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1503 return false;
1504
1505 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1506 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1507 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1508
1509 return true;
1510 }
1511
rtl_pci_tx(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct sk_buff * skb,struct rtl_tcb_desc * ptcb_desc)1512 static int rtl_pci_tx(struct ieee80211_hw *hw,
1513 struct ieee80211_sta *sta,
1514 struct sk_buff *skb,
1515 struct rtl_tcb_desc *ptcb_desc)
1516 {
1517 struct rtl_priv *rtlpriv = rtl_priv(hw);
1518 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1519 struct rtl8192_tx_ring *ring;
1520 struct rtl_tx_desc *pdesc;
1521 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
1522 u16 idx;
1523 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1524 unsigned long flags;
1525 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1526 __le16 fc = rtl_get_fc(skb);
1527 u8 *pda_addr = hdr->addr1;
1528 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1529 u8 own;
1530 u8 temp_one = 1;
1531
1532 if (ieee80211_is_mgmt(fc))
1533 rtl_tx_mgmt_proc(hw, skb);
1534
1535 if (rtlpriv->psc.sw_ps_enabled) {
1536 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1537 !ieee80211_has_pm(fc))
1538 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1539 }
1540
1541 rtl_action_proc(hw, skb, true);
1542
1543 if (is_multicast_ether_addr(pda_addr))
1544 rtlpriv->stats.txbytesmulticast += skb->len;
1545 else if (is_broadcast_ether_addr(pda_addr))
1546 rtlpriv->stats.txbytesbroadcast += skb->len;
1547 else
1548 rtlpriv->stats.txbytesunicast += skb->len;
1549
1550 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1551 ring = &rtlpci->tx_ring[hw_queue];
1552 if (hw_queue != BEACON_QUEUE) {
1553 if (rtlpriv->use_new_trx_flow)
1554 idx = ring->cur_tx_wp;
1555 else
1556 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1557 ring->entries;
1558 } else {
1559 idx = 0;
1560 }
1561
1562 pdesc = &ring->desc[idx];
1563 if (rtlpriv->use_new_trx_flow) {
1564 ptx_bd_desc = &ring->buffer_desc[idx];
1565 } else {
1566 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
1567 true, HW_DESC_OWN);
1568
1569 if (own == 1 && hw_queue != BEACON_QUEUE) {
1570 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1571 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1572 hw_queue, ring->idx, idx,
1573 skb_queue_len(&ring->queue));
1574
1575 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1576 flags);
1577 return skb->len;
1578 }
1579 }
1580
1581 if (rtlpriv->cfg->ops->get_available_desc &&
1582 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) {
1583 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1584 "get_available_desc fail\n");
1585 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1586 return skb->len;
1587 }
1588
1589 if (ieee80211_is_data(fc))
1590 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1591
1592 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1593 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc);
1594
1595 __skb_queue_tail(&ring->queue, skb);
1596
1597 if (rtlpriv->use_new_trx_flow) {
1598 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1599 HW_DESC_OWN, &hw_queue);
1600 } else {
1601 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1602 HW_DESC_OWN, &temp_one);
1603 }
1604
1605 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1606 hw_queue != BEACON_QUEUE) {
1607 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
1608 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1609 hw_queue, ring->idx, idx,
1610 skb_queue_len(&ring->queue));
1611
1612 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1613 }
1614
1615 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1616
1617 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1618
1619 return 0;
1620 }
1621
rtl_pci_flush(struct ieee80211_hw * hw,u32 queues,bool drop)1622 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1623 {
1624 struct rtl_priv *rtlpriv = rtl_priv(hw);
1625 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1626 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1627 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1628 u16 i = 0;
1629 int queue_id;
1630 struct rtl8192_tx_ring *ring;
1631
1632 if (mac->skip_scan)
1633 return;
1634
1635 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1636 u32 queue_len;
1637
1638 if (((queues >> queue_id) & 0x1) == 0) {
1639 queue_id--;
1640 continue;
1641 }
1642 ring = &pcipriv->dev.tx_ring[queue_id];
1643 queue_len = skb_queue_len(&ring->queue);
1644 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1645 queue_id == TXCMD_QUEUE) {
1646 queue_id--;
1647 continue;
1648 } else {
1649 msleep(20);
1650 i++;
1651 }
1652
1653 /* we just wait 1s for all queues */
1654 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1655 is_hal_stop(rtlhal) || i >= 200)
1656 return;
1657 }
1658 }
1659
rtl_pci_deinit(struct ieee80211_hw * hw)1660 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1661 {
1662 struct rtl_priv *rtlpriv = rtl_priv(hw);
1663 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1664
1665 _rtl_pci_deinit_trx_ring(hw);
1666
1667 synchronize_irq(rtlpci->pdev->irq);
1668 tasklet_kill(&rtlpriv->works.irq_tasklet);
1669 cancel_work_sync(&rtlpriv->works.lps_change_work);
1670 }
1671
rtl_pci_init(struct ieee80211_hw * hw,struct pci_dev * pdev)1672 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1673 {
1674 int err;
1675
1676 _rtl_pci_init_struct(hw, pdev);
1677
1678 err = _rtl_pci_init_trx_ring(hw);
1679 if (err) {
1680 pr_err("tx ring initialization failed\n");
1681 return err;
1682 }
1683
1684 return 0;
1685 }
1686
rtl_pci_start(struct ieee80211_hw * hw)1687 static int rtl_pci_start(struct ieee80211_hw *hw)
1688 {
1689 struct rtl_priv *rtlpriv = rtl_priv(hw);
1690 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1691 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1692 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1693 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
1694 struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops;
1695
1696 int err;
1697
1698 rtl_pci_reset_trx_ring(hw);
1699
1700 rtlpci->driver_is_goingto_unload = false;
1701 if (rtlpriv->cfg->ops->get_btc_status &&
1702 rtlpriv->cfg->ops->get_btc_status()) {
1703 rtlpriv->btcoexist.btc_info.ap_num = 36;
1704 btc_ops->btc_init_variables(rtlpriv);
1705 btc_ops->btc_init_hal_vars(rtlpriv);
1706 } else if (btc_ops) {
1707 btc_ops->btc_init_variables_wifi_only(rtlpriv);
1708 }
1709
1710 err = rtlpriv->cfg->ops->hw_init(hw);
1711 if (err) {
1712 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1713 "Failed to config hardware!\n");
1714 kfree(rtlpriv->btcoexist.btc_context);
1715 kfree(rtlpriv->btcoexist.wifi_only_context);
1716 return err;
1717 }
1718 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
1719 &rtlmac->retry_long);
1720
1721 rtlpriv->cfg->ops->enable_interrupt(hw);
1722 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1723
1724 rtl_init_rx_config(hw);
1725
1726 /*should be after adapter start and interrupt enable. */
1727 set_hal_start(rtlhal);
1728
1729 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1730
1731 rtlpci->up_first_time = false;
1732
1733 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__);
1734 return 0;
1735 }
1736
rtl_pci_stop(struct ieee80211_hw * hw)1737 static void rtl_pci_stop(struct ieee80211_hw *hw)
1738 {
1739 struct rtl_priv *rtlpriv = rtl_priv(hw);
1740 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1741 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1742 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1743 unsigned long flags;
1744 u8 rf_timeout = 0;
1745
1746 if (rtlpriv->cfg->ops->get_btc_status())
1747 rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv);
1748
1749 if (rtlpriv->btcoexist.btc_ops)
1750 rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv);
1751
1752 /*should be before disable interrupt&adapter
1753 *and will do it immediately.
1754 */
1755 set_hal_stop(rtlhal);
1756
1757 rtlpci->driver_is_goingto_unload = true;
1758 rtlpriv->cfg->ops->disable_interrupt(hw);
1759 cancel_work_sync(&rtlpriv->works.lps_change_work);
1760
1761 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1762 while (ppsc->rfchange_inprogress) {
1763 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1764 if (rf_timeout > 100) {
1765 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1766 break;
1767 }
1768 mdelay(1);
1769 rf_timeout++;
1770 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1771 }
1772 ppsc->rfchange_inprogress = true;
1773 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1774
1775 rtlpriv->cfg->ops->hw_disable(hw);
1776 /* some things are not needed if firmware not available */
1777 if (!rtlpriv->max_fw_size)
1778 return;
1779 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1780
1781 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1782 ppsc->rfchange_inprogress = false;
1783 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1784
1785 rtl_pci_enable_aspm(hw);
1786 }
1787
_rtl_pci_find_adapter(struct pci_dev * pdev,struct ieee80211_hw * hw)1788 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1789 struct ieee80211_hw *hw)
1790 {
1791 struct rtl_priv *rtlpriv = rtl_priv(hw);
1792 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1793 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1794 struct pci_dev *bridge_pdev = pdev->bus->self;
1795 u16 venderid;
1796 u16 deviceid;
1797 u8 revisionid;
1798 u16 irqline;
1799 u8 tmp;
1800
1801 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1802 venderid = pdev->vendor;
1803 deviceid = pdev->device;
1804 pci_read_config_byte(pdev, 0x8, &revisionid);
1805 pci_read_config_word(pdev, 0x3C, &irqline);
1806
1807 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1808 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1809 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1810 * the correct driver is r8192e_pci, thus this routine should
1811 * return false.
1812 */
1813 if (deviceid == RTL_PCI_8192SE_DID &&
1814 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1815 return false;
1816
1817 if (deviceid == RTL_PCI_8192_DID ||
1818 deviceid == RTL_PCI_0044_DID ||
1819 deviceid == RTL_PCI_0047_DID ||
1820 deviceid == RTL_PCI_8192SE_DID ||
1821 deviceid == RTL_PCI_8174_DID ||
1822 deviceid == RTL_PCI_8173_DID ||
1823 deviceid == RTL_PCI_8172_DID ||
1824 deviceid == RTL_PCI_8171_DID) {
1825 switch (revisionid) {
1826 case RTL_PCI_REVISION_ID_8192PCIE:
1827 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1828 "8192 PCI-E is found - vid/did=%x/%x\n",
1829 venderid, deviceid);
1830 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1831 return false;
1832 case RTL_PCI_REVISION_ID_8192SE:
1833 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1834 "8192SE is found - vid/did=%x/%x\n",
1835 venderid, deviceid);
1836 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1837 break;
1838 default:
1839 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1840 "Err: Unknown device - vid/did=%x/%x\n",
1841 venderid, deviceid);
1842 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1843 break;
1844 }
1845 } else if (deviceid == RTL_PCI_8723AE_DID) {
1846 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1847 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1848 "8723AE PCI-E is found - vid/did=%x/%x\n",
1849 venderid, deviceid);
1850 } else if (deviceid == RTL_PCI_8192CET_DID ||
1851 deviceid == RTL_PCI_8192CE_DID ||
1852 deviceid == RTL_PCI_8191CE_DID ||
1853 deviceid == RTL_PCI_8188CE_DID) {
1854 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1855 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1856 "8192C PCI-E is found - vid/did=%x/%x\n",
1857 venderid, deviceid);
1858 } else if (deviceid == RTL_PCI_8192DE_DID ||
1859 deviceid == RTL_PCI_8192DE_DID2) {
1860 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1861 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1862 "8192D PCI-E is found - vid/did=%x/%x\n",
1863 venderid, deviceid);
1864 } else if (deviceid == RTL_PCI_8188EE_DID) {
1865 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
1866 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1867 "Find adapter, Hardware type is 8188EE\n");
1868 } else if (deviceid == RTL_PCI_8723BE_DID) {
1869 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE;
1870 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1871 "Find adapter, Hardware type is 8723BE\n");
1872 } else if (deviceid == RTL_PCI_8192EE_DID) {
1873 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE;
1874 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1875 "Find adapter, Hardware type is 8192EE\n");
1876 } else if (deviceid == RTL_PCI_8821AE_DID) {
1877 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE;
1878 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1879 "Find adapter, Hardware type is 8821AE\n");
1880 } else if (deviceid == RTL_PCI_8812AE_DID) {
1881 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE;
1882 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1883 "Find adapter, Hardware type is 8812AE\n");
1884 } else if (deviceid == RTL_PCI_8822BE_DID) {
1885 rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE;
1886 rtlhal->bandset = BAND_ON_BOTH;
1887 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1888 "Find adapter, Hardware type is 8822BE\n");
1889 } else {
1890 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1891 "Err: Unknown device - vid/did=%x/%x\n",
1892 venderid, deviceid);
1893
1894 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1895 }
1896
1897 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1898 if (revisionid == 0 || revisionid == 1) {
1899 if (revisionid == 0) {
1900 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1901 "Find 92DE MAC0\n");
1902 rtlhal->interfaceindex = 0;
1903 } else if (revisionid == 1) {
1904 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1905 "Find 92DE MAC1\n");
1906 rtlhal->interfaceindex = 1;
1907 }
1908 } else {
1909 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1910 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
1911 venderid, deviceid, revisionid);
1912 rtlhal->interfaceindex = 0;
1913 }
1914 }
1915
1916 switch (rtlhal->hw_type) {
1917 case HARDWARE_TYPE_RTL8192EE:
1918 case HARDWARE_TYPE_RTL8822BE:
1919 /* use new trx flow */
1920 rtlpriv->use_new_trx_flow = true;
1921 break;
1922
1923 default:
1924 rtlpriv->use_new_trx_flow = false;
1925 break;
1926 }
1927
1928 /*find bus info */
1929 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1930 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1931 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1932
1933 /*find bridge info */
1934 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1935 /* some ARM have no bridge_pdev and will crash here
1936 * so we should check if bridge_pdev is NULL
1937 */
1938 if (bridge_pdev) {
1939 /*find bridge info if available */
1940 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1941 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1942 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1943 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1944 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1945 "Pci Bridge Vendor is found index: %d\n",
1946 tmp);
1947 break;
1948 }
1949 }
1950 }
1951
1952 if (pcipriv->ndis_adapter.pcibridge_vendor !=
1953 PCI_BRIDGE_VENDOR_UNKNOWN) {
1954 pcipriv->ndis_adapter.pcibridge_busnum =
1955 bridge_pdev->bus->number;
1956 pcipriv->ndis_adapter.pcibridge_devnum =
1957 PCI_SLOT(bridge_pdev->devfn);
1958 pcipriv->ndis_adapter.pcibridge_funcnum =
1959 PCI_FUNC(bridge_pdev->devfn);
1960
1961 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1962 PCI_BRIDGE_VENDOR_AMD) {
1963 pcipriv->ndis_adapter.amd_l1_patch =
1964 rtl_pci_get_amd_l1_patch(hw);
1965 }
1966 }
1967
1968 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1969 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
1970 pcipriv->ndis_adapter.busnumber,
1971 pcipriv->ndis_adapter.devnumber,
1972 pcipriv->ndis_adapter.funcnumber,
1973 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
1974
1975 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1976 "pci_bridge busnumber:devnumber:funcnumber:vendor:amd %d:%d:%d:%x:%x\n",
1977 pcipriv->ndis_adapter.pcibridge_busnum,
1978 pcipriv->ndis_adapter.pcibridge_devnum,
1979 pcipriv->ndis_adapter.pcibridge_funcnum,
1980 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1981 pcipriv->ndis_adapter.amd_l1_patch);
1982
1983 rtl_pci_parse_configuration(pdev, hw);
1984
1985 return true;
1986 }
1987
rtl_pci_intr_mode_msi(struct ieee80211_hw * hw)1988 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
1989 {
1990 struct rtl_priv *rtlpriv = rtl_priv(hw);
1991 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1992 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
1993 int ret;
1994
1995 ret = pci_enable_msi(rtlpci->pdev);
1996 if (ret < 0)
1997 return ret;
1998
1999 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2000 IRQF_SHARED, KBUILD_MODNAME, hw);
2001 if (ret < 0) {
2002 pci_disable_msi(rtlpci->pdev);
2003 return ret;
2004 }
2005
2006 rtlpci->using_msi = true;
2007
2008 rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2009 "MSI Interrupt Mode!\n");
2010 return 0;
2011 }
2012
rtl_pci_intr_mode_legacy(struct ieee80211_hw * hw)2013 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
2014 {
2015 struct rtl_priv *rtlpriv = rtl_priv(hw);
2016 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2017 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2018 int ret;
2019
2020 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2021 IRQF_SHARED, KBUILD_MODNAME, hw);
2022 if (ret < 0)
2023 return ret;
2024
2025 rtlpci->using_msi = false;
2026 rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2027 "Pin-based Interrupt Mode!\n");
2028 return 0;
2029 }
2030
rtl_pci_intr_mode_decide(struct ieee80211_hw * hw)2031 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
2032 {
2033 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2034 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2035 int ret;
2036
2037 if (rtlpci->msi_support) {
2038 ret = rtl_pci_intr_mode_msi(hw);
2039 if (ret < 0)
2040 ret = rtl_pci_intr_mode_legacy(hw);
2041 } else {
2042 ret = rtl_pci_intr_mode_legacy(hw);
2043 }
2044 return ret;
2045 }
2046
platform_enable_dma64(struct pci_dev * pdev,bool dma64)2047 static void platform_enable_dma64(struct pci_dev *pdev, bool dma64)
2048 {
2049 u8 value;
2050
2051 pci_read_config_byte(pdev, 0x719, &value);
2052
2053 /* 0x719 Bit5 is DMA64 bit fetch. */
2054 if (dma64)
2055 value |= BIT(5);
2056 else
2057 value &= ~BIT(5);
2058
2059 pci_write_config_byte(pdev, 0x719, value);
2060 }
2061
rtl_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)2062 int rtl_pci_probe(struct pci_dev *pdev,
2063 const struct pci_device_id *id)
2064 {
2065 struct ieee80211_hw *hw = NULL;
2066
2067 struct rtl_priv *rtlpriv = NULL;
2068 struct rtl_pci_priv *pcipriv = NULL;
2069 struct rtl_pci *rtlpci;
2070 unsigned long pmem_start, pmem_len, pmem_flags;
2071 int err;
2072
2073 err = pci_enable_device(pdev);
2074 if (err) {
2075 WARN_ONCE(true, "%s : Cannot enable new PCI device\n",
2076 pci_name(pdev));
2077 return err;
2078 }
2079
2080 if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 &&
2081 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
2082 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
2083 WARN_ONCE(true,
2084 "Unable to obtain 64bit DMA for consistent allocations\n");
2085 err = -ENOMEM;
2086 goto fail1;
2087 }
2088
2089 platform_enable_dma64(pdev, true);
2090 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
2091 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) {
2092 WARN_ONCE(true,
2093 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n");
2094 err = -ENOMEM;
2095 goto fail1;
2096 }
2097
2098 platform_enable_dma64(pdev, false);
2099 }
2100
2101 pci_set_master(pdev);
2102
2103 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
2104 sizeof(struct rtl_priv), &rtl_ops);
2105 if (!hw) {
2106 WARN_ONCE(true,
2107 "%s : ieee80211 alloc failed\n", pci_name(pdev));
2108 err = -ENOMEM;
2109 goto fail1;
2110 }
2111
2112 SET_IEEE80211_DEV(hw, &pdev->dev);
2113 pci_set_drvdata(pdev, hw);
2114
2115 rtlpriv = hw->priv;
2116 rtlpriv->hw = hw;
2117 pcipriv = (void *)rtlpriv->priv;
2118 pcipriv->dev.pdev = pdev;
2119 init_completion(&rtlpriv->firmware_loading_complete);
2120 /*proximity init here*/
2121 rtlpriv->proximity.proxim_on = false;
2122
2123 pcipriv = (void *)rtlpriv->priv;
2124 pcipriv->dev.pdev = pdev;
2125
2126 /* init cfg & intf_ops */
2127 rtlpriv->rtlhal.interface = INTF_PCI;
2128 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
2129 rtlpriv->intf_ops = &rtl_pci_ops;
2130 rtl_efuse_ops_init(hw);
2131
2132 /* MEM map */
2133 err = pci_request_regions(pdev, KBUILD_MODNAME);
2134 if (err) {
2135 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n");
2136 goto fail1;
2137 }
2138
2139 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
2140 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
2141 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
2142
2143 /*shared mem start */
2144 rtlpriv->io.pci_mem_start =
2145 (unsigned long)pci_iomap(pdev,
2146 rtlpriv->cfg->bar_id, pmem_len);
2147 if (rtlpriv->io.pci_mem_start == 0) {
2148 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n");
2149 err = -ENOMEM;
2150 goto fail2;
2151 }
2152
2153 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2154 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
2155 pmem_start, pmem_len, pmem_flags,
2156 rtlpriv->io.pci_mem_start);
2157
2158 /* Disable Clk Request */
2159 pci_write_config_byte(pdev, 0x81, 0);
2160 /* leave D3 mode */
2161 pci_write_config_byte(pdev, 0x44, 0);
2162 pci_write_config_byte(pdev, 0x04, 0x06);
2163 pci_write_config_byte(pdev, 0x04, 0x07);
2164
2165 /* find adapter */
2166 if (!_rtl_pci_find_adapter(pdev, hw)) {
2167 err = -ENODEV;
2168 goto fail2;
2169 }
2170
2171 /* Init IO handler */
2172 _rtl_pci_io_handler_init(&pdev->dev, hw);
2173
2174 /*like read eeprom and so on */
2175 rtlpriv->cfg->ops->read_eeprom_info(hw);
2176
2177 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
2178 pr_err("Can't init_sw_vars\n");
2179 err = -ENODEV;
2180 goto fail2;
2181 }
2182 rtl_init_sw_leds(hw);
2183
2184 /*aspm */
2185 rtl_pci_init_aspm(hw);
2186
2187 /* Init mac80211 sw */
2188 err = rtl_init_core(hw);
2189 if (err) {
2190 pr_err("Can't allocate sw for mac80211\n");
2191 goto fail3;
2192 }
2193
2194 /* Init PCI sw */
2195 err = rtl_pci_init(hw, pdev);
2196 if (err) {
2197 pr_err("Failed to init PCI\n");
2198 goto fail4;
2199 }
2200
2201 err = ieee80211_register_hw(hw);
2202 if (err) {
2203 pr_err("Can't register mac80211 hw.\n");
2204 err = -ENODEV;
2205 goto fail5;
2206 }
2207 rtlpriv->mac80211.mac80211_registered = 1;
2208
2209 /* add for debug */
2210 rtl_debug_add_one(hw);
2211
2212 /*init rfkill */
2213 rtl_init_rfkill(hw); /* Init PCI sw */
2214
2215 rtlpci = rtl_pcidev(pcipriv);
2216 err = rtl_pci_intr_mode_decide(hw);
2217 if (err) {
2218 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2219 "%s: failed to register IRQ handler\n",
2220 wiphy_name(hw->wiphy));
2221 goto fail3;
2222 }
2223 rtlpci->irq_alloc = 1;
2224
2225 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2226 return 0;
2227
2228 fail5:
2229 rtl_pci_deinit(hw);
2230 fail4:
2231 rtl_deinit_core(hw);
2232 fail3:
2233 wait_for_completion(&rtlpriv->firmware_loading_complete);
2234 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2235
2236 fail2:
2237 if (rtlpriv->io.pci_mem_start != 0)
2238 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2239
2240 pci_release_regions(pdev);
2241
2242 fail1:
2243 if (hw)
2244 ieee80211_free_hw(hw);
2245 pci_disable_device(pdev);
2246
2247 return err;
2248 }
2249 EXPORT_SYMBOL(rtl_pci_probe);
2250
rtl_pci_disconnect(struct pci_dev * pdev)2251 void rtl_pci_disconnect(struct pci_dev *pdev)
2252 {
2253 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2254 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2255 struct rtl_priv *rtlpriv = rtl_priv(hw);
2256 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2257 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2258
2259 /* just in case driver is removed before firmware callback */
2260 wait_for_completion(&rtlpriv->firmware_loading_complete);
2261 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2262
2263 /* remove form debug */
2264 rtl_debug_remove_one(hw);
2265
2266 /*ieee80211_unregister_hw will call ops_stop */
2267 if (rtlmac->mac80211_registered == 1) {
2268 ieee80211_unregister_hw(hw);
2269 rtlmac->mac80211_registered = 0;
2270 } else {
2271 rtl_deinit_deferred_work(hw, false);
2272 rtlpriv->intf_ops->adapter_stop(hw);
2273 }
2274 rtlpriv->cfg->ops->disable_interrupt(hw);
2275
2276 /*deinit rfkill */
2277 rtl_deinit_rfkill(hw);
2278
2279 rtl_pci_deinit(hw);
2280 rtl_deinit_core(hw);
2281 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2282
2283 if (rtlpci->irq_alloc) {
2284 free_irq(rtlpci->pdev->irq, hw);
2285 rtlpci->irq_alloc = 0;
2286 }
2287
2288 if (rtlpci->using_msi)
2289 pci_disable_msi(rtlpci->pdev);
2290
2291 if (rtlpriv->io.pci_mem_start != 0) {
2292 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2293 pci_release_regions(pdev);
2294 }
2295
2296 pci_disable_device(pdev);
2297
2298 rtl_pci_disable_aspm(hw);
2299
2300 pci_set_drvdata(pdev, NULL);
2301
2302 ieee80211_free_hw(hw);
2303 }
2304 EXPORT_SYMBOL(rtl_pci_disconnect);
2305
2306 #ifdef CONFIG_PM_SLEEP
2307 /***************************************
2308 * kernel pci power state define:
2309 * PCI_D0 ((pci_power_t __force) 0)
2310 * PCI_D1 ((pci_power_t __force) 1)
2311 * PCI_D2 ((pci_power_t __force) 2)
2312 * PCI_D3hot ((pci_power_t __force) 3)
2313 * PCI_D3cold ((pci_power_t __force) 4)
2314 * PCI_UNKNOWN ((pci_power_t __force) 5)
2315
2316 * This function is called when system
2317 * goes into suspend state mac80211 will
2318 * call rtl_mac_stop() from the mac80211
2319 * suspend function first, So there is
2320 * no need to call hw_disable here.
2321 ****************************************/
rtl_pci_suspend(struct device * dev)2322 int rtl_pci_suspend(struct device *dev)
2323 {
2324 struct ieee80211_hw *hw = dev_get_drvdata(dev);
2325 struct rtl_priv *rtlpriv = rtl_priv(hw);
2326
2327 rtlpriv->cfg->ops->hw_suspend(hw);
2328 rtl_deinit_rfkill(hw);
2329
2330 return 0;
2331 }
2332 EXPORT_SYMBOL(rtl_pci_suspend);
2333
rtl_pci_resume(struct device * dev)2334 int rtl_pci_resume(struct device *dev)
2335 {
2336 struct ieee80211_hw *hw = dev_get_drvdata(dev);
2337 struct rtl_priv *rtlpriv = rtl_priv(hw);
2338
2339 rtlpriv->cfg->ops->hw_resume(hw);
2340 rtl_init_rfkill(hw);
2341 return 0;
2342 }
2343 EXPORT_SYMBOL(rtl_pci_resume);
2344 #endif /* CONFIG_PM_SLEEP */
2345
2346 const struct rtl_intf_ops rtl_pci_ops = {
2347 .read_efuse_byte = read_efuse_byte,
2348 .adapter_start = rtl_pci_start,
2349 .adapter_stop = rtl_pci_stop,
2350 .adapter_tx = rtl_pci_tx,
2351 .flush = rtl_pci_flush,
2352 .reset_trx_ring = rtl_pci_reset_trx_ring,
2353 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2354
2355 .disable_aspm = rtl_pci_disable_aspm,
2356 .enable_aspm = rtl_pci_enable_aspm,
2357 };
2358