1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * RTL8XXXU mac80211 USB driver
4 *
5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
6 *
7 * Portions, notably calibration code:
8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
9 *
10 * This driver was written as a replacement for the vendor provided
11 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
12 * their programming interface, I have started adding support for
13 * additional 8xxx chips like the 8192cu, 8188cus, etc.
14 */
15
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/sched.h>
19 #include <linux/errno.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/list.h>
24 #include <linux/usb.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/ethtool.h>
28 #include <linux/wireless.h>
29 #include <linux/firmware.h>
30 #include <linux/moduleparam.h>
31 #include <net/mac80211.h>
32 #include "rtl8xxxu.h"
33 #include "rtl8xxxu_regs.h"
34
35 #define DRIVER_NAME "rtl8xxxu"
36
37 int rtl8xxxu_debug;
38 static bool rtl8xxxu_ht40_2g;
39 static bool rtl8xxxu_dma_aggregation;
40 static int rtl8xxxu_dma_agg_timeout = -1;
41 static int rtl8xxxu_dma_agg_pages = -1;
42
43 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@gmail.com>");
44 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
45 MODULE_LICENSE("GPL");
46 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
47 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
48 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
49 MODULE_FIRMWARE("rtlwifi/rtl8188eufw.bin");
50 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
51 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
52 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
53 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
54 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
55 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
56 MODULE_FIRMWARE("rtlwifi/rtl8188fufw.bin");
57 MODULE_FIRMWARE("rtlwifi/rtl8710bufw_SMIC.bin");
58 MODULE_FIRMWARE("rtlwifi/rtl8710bufw_UMC.bin");
59 MODULE_FIRMWARE("rtlwifi/rtl8192fufw.bin");
60
61 module_param_named(debug, rtl8xxxu_debug, int, 0600);
62 MODULE_PARM_DESC(debug, "Set debug mask");
63 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
64 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
65 module_param_named(dma_aggregation, rtl8xxxu_dma_aggregation, bool, 0600);
66 MODULE_PARM_DESC(dma_aggregation, "Enable DMA packet aggregation");
67 module_param_named(dma_agg_timeout, rtl8xxxu_dma_agg_timeout, int, 0600);
68 MODULE_PARM_DESC(dma_agg_timeout, "Set DMA aggregation timeout (range 1-127)");
69 module_param_named(dma_agg_pages, rtl8xxxu_dma_agg_pages, int, 0600);
70 MODULE_PARM_DESC(dma_agg_pages, "Set DMA aggregation pages (range 1-127, 0 to disable)");
71
72 #define USB_VENDOR_ID_REALTEK 0x0bda
73 #define RTL8XXXU_RX_URBS 32
74 #define RTL8XXXU_RX_URB_PENDING_WATER 8
75 #define RTL8XXXU_TX_URBS 64
76 #define RTL8XXXU_TX_URB_LOW_WATER 25
77 #define RTL8XXXU_TX_URB_HIGH_WATER 32
78
79 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
80 struct rtl8xxxu_rx_urb *rx_urb);
81
82 static struct ieee80211_rate rtl8xxxu_rates[] = {
83 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
84 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
85 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
86 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
87 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
88 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
89 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
90 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
91 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
92 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
93 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
94 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
95 };
96
97 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
98 { .band = NL80211_BAND_2GHZ, .center_freq = 2412,
99 .hw_value = 1, .max_power = 30 },
100 { .band = NL80211_BAND_2GHZ, .center_freq = 2417,
101 .hw_value = 2, .max_power = 30 },
102 { .band = NL80211_BAND_2GHZ, .center_freq = 2422,
103 .hw_value = 3, .max_power = 30 },
104 { .band = NL80211_BAND_2GHZ, .center_freq = 2427,
105 .hw_value = 4, .max_power = 30 },
106 { .band = NL80211_BAND_2GHZ, .center_freq = 2432,
107 .hw_value = 5, .max_power = 30 },
108 { .band = NL80211_BAND_2GHZ, .center_freq = 2437,
109 .hw_value = 6, .max_power = 30 },
110 { .band = NL80211_BAND_2GHZ, .center_freq = 2442,
111 .hw_value = 7, .max_power = 30 },
112 { .band = NL80211_BAND_2GHZ, .center_freq = 2447,
113 .hw_value = 8, .max_power = 30 },
114 { .band = NL80211_BAND_2GHZ, .center_freq = 2452,
115 .hw_value = 9, .max_power = 30 },
116 { .band = NL80211_BAND_2GHZ, .center_freq = 2457,
117 .hw_value = 10, .max_power = 30 },
118 { .band = NL80211_BAND_2GHZ, .center_freq = 2462,
119 .hw_value = 11, .max_power = 30 },
120 { .band = NL80211_BAND_2GHZ, .center_freq = 2467,
121 .hw_value = 12, .max_power = 30 },
122 { .band = NL80211_BAND_2GHZ, .center_freq = 2472,
123 .hw_value = 13, .max_power = 30 },
124 { .band = NL80211_BAND_2GHZ, .center_freq = 2484,
125 .hw_value = 14, .max_power = 30 }
126 };
127
128 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
129 .channels = rtl8xxxu_channels_2g,
130 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
131 .bitrates = rtl8xxxu_rates,
132 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
133 };
134
135 const struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[] = {
136 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
137 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
138 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
139 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
140 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
141 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
142 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
143 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
144 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
145 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
146 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
147 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
148 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
149 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
150 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
151 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
152 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
153 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
154 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
155 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
156 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
157 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
158 };
159
160 static const struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
161 {0x800, 0x80040000}, {0x804, 0x00000003},
162 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
163 {0x810, 0x10001331}, {0x814, 0x020c3d10},
164 {0x818, 0x02200385}, {0x81c, 0x00000000},
165 {0x820, 0x01000100}, {0x824, 0x00390004},
166 {0x828, 0x00000000}, {0x82c, 0x00000000},
167 {0x830, 0x00000000}, {0x834, 0x00000000},
168 {0x838, 0x00000000}, {0x83c, 0x00000000},
169 {0x840, 0x00010000}, {0x844, 0x00000000},
170 {0x848, 0x00000000}, {0x84c, 0x00000000},
171 {0x850, 0x00000000}, {0x854, 0x00000000},
172 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
173 {0x860, 0x66f60110}, {0x864, 0x061f0130},
174 {0x868, 0x00000000}, {0x86c, 0x32323200},
175 {0x870, 0x07000760}, {0x874, 0x22004000},
176 {0x878, 0x00000808}, {0x87c, 0x00000000},
177 {0x880, 0xc0083070}, {0x884, 0x000004d5},
178 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
179 {0x890, 0x00000800}, {0x894, 0xfffffffe},
180 {0x898, 0x40302010}, {0x89c, 0x00706050},
181 {0x900, 0x00000000}, {0x904, 0x00000023},
182 {0x908, 0x00000000}, {0x90c, 0x81121111},
183 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
184 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
185 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
186 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
187 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
188 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
189 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
190 {0xa78, 0x00000900},
191 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
192 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
193 {0xc10, 0x08800000}, {0xc14, 0x40000100},
194 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
195 {0xc20, 0x00000000}, {0xc24, 0x00000000},
196 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
197 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
198 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
199 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
200 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
201 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
202 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
203 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
204 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
205 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
206 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
207 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
208 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
209 {0xc90, 0x00121820}, {0xc94, 0x00000000},
210 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
211 {0xca0, 0x00000000}, {0xca4, 0x00000080},
212 {0xca8, 0x00000000}, {0xcac, 0x00000000},
213 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
214 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
215 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
216 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
217 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
218 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
219 {0xce0, 0x00222222}, {0xce4, 0x00000000},
220 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
221 {0xd00, 0x00080740}, {0xd04, 0x00020401},
222 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
223 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
224 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
225 {0xd30, 0x00000000}, {0xd34, 0x80608000},
226 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
227 {0xd40, 0x00000000}, {0xd44, 0x00000000},
228 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
229 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
230 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
231 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
232 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
233 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
234 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
235 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
236 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
237 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
238 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
239 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
240 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
241 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
242 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
243 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
244 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
245 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
246 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
247 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
248 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
249 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
250 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
251 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
252 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
253 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
254 {0xf00, 0x00000300},
255 {0xffff, 0xffffffff},
256 };
257
258 static const struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
259 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
260 {0x800, 0x80040002}, {0x804, 0x00000003},
261 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
262 {0x810, 0x10000330}, {0x814, 0x020c3d10},
263 {0x818, 0x02200385}, {0x81c, 0x00000000},
264 {0x820, 0x01000100}, {0x824, 0x00390004},
265 {0x828, 0x01000100}, {0x82c, 0x00390004},
266 {0x830, 0x27272727}, {0x834, 0x27272727},
267 {0x838, 0x27272727}, {0x83c, 0x27272727},
268 {0x840, 0x00010000}, {0x844, 0x00010000},
269 {0x848, 0x27272727}, {0x84c, 0x27272727},
270 {0x850, 0x00000000}, {0x854, 0x00000000},
271 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
272 {0x860, 0x66e60230}, {0x864, 0x061f0130},
273 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
274 {0x870, 0x07000700}, {0x874, 0x22184000},
275 {0x878, 0x08080808}, {0x87c, 0x00000000},
276 {0x880, 0xc0083070}, {0x884, 0x000004d5},
277 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
278 {0x890, 0x00000800}, {0x894, 0xfffffffe},
279 {0x898, 0x40302010}, {0x89c, 0x00706050},
280 {0x900, 0x00000000}, {0x904, 0x00000023},
281 {0x908, 0x00000000}, {0x90c, 0x81121313},
282 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
283 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
284 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
285 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
286 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
287 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
288 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
289 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
290 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
291 {0xc10, 0x08800000}, {0xc14, 0x40000100},
292 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
293 {0xc20, 0x00000000}, {0xc24, 0x00000000},
294 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
295 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
296 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
297 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
298 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
299 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
300 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
301 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
302 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
303 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
304 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
305 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
306 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
307 {0xc90, 0x00121820}, {0xc94, 0x00000000},
308 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
309 {0xca0, 0x00000000}, {0xca4, 0x00000080},
310 {0xca8, 0x00000000}, {0xcac, 0x00000000},
311 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
312 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
313 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
314 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
315 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
316 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
317 {0xce0, 0x00222222}, {0xce4, 0x00000000},
318 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
319 {0xd00, 0x00080740}, {0xd04, 0x00020403},
320 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
321 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
322 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
323 {0xd30, 0x00000000}, {0xd34, 0x80608000},
324 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
325 {0xd40, 0x00000000}, {0xd44, 0x00000000},
326 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
327 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
328 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
329 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
330 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
331 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
332 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
333 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
334 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
335 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
336 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
337 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
338 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
339 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
340 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
341 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
342 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
343 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
344 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
345 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
346 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
347 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
348 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
349 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
350 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
351 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
352 {0xf00, 0x00000300},
353 {0xffff, 0xffffffff},
354 };
355
356 static const struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
357 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
358 {0x040, 0x000c0004}, {0x800, 0x80040000},
359 {0x804, 0x00000001}, {0x808, 0x0000fc00},
360 {0x80c, 0x0000000a}, {0x810, 0x10005388},
361 {0x814, 0x020c3d10}, {0x818, 0x02200385},
362 {0x81c, 0x00000000}, {0x820, 0x01000100},
363 {0x824, 0x00390204}, {0x828, 0x00000000},
364 {0x82c, 0x00000000}, {0x830, 0x00000000},
365 {0x834, 0x00000000}, {0x838, 0x00000000},
366 {0x83c, 0x00000000}, {0x840, 0x00010000},
367 {0x844, 0x00000000}, {0x848, 0x00000000},
368 {0x84c, 0x00000000}, {0x850, 0x00000000},
369 {0x854, 0x00000000}, {0x858, 0x569a569a},
370 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
371 {0x864, 0x061f0130}, {0x868, 0x00000000},
372 {0x86c, 0x20202000}, {0x870, 0x03000300},
373 {0x874, 0x22004000}, {0x878, 0x00000808},
374 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
375 {0x884, 0x000004d5}, {0x888, 0x00000000},
376 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
377 {0x894, 0xfffffffe}, {0x898, 0x40302010},
378 {0x89c, 0x00706050}, {0x900, 0x00000000},
379 {0x904, 0x00000023}, {0x908, 0x00000000},
380 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
381 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
382 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
383 {0xa14, 0x11144028}, {0xa18, 0x00881117},
384 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
385 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
386 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
387 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
388 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
389 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
390 {0xc14, 0x40000100}, {0xc18, 0x08800000},
391 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
392 {0xc24, 0x00000000}, {0xc28, 0x00000000},
393 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
394 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
395 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
396 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
397 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
398 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
399 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
400 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
401 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
402 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
403 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
404 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
405 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
406 {0xc94, 0x00000000}, {0xc98, 0x00121820},
407 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
408 {0xca4, 0x00000080}, {0xca8, 0x00000000},
409 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
410 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
411 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
412 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
413 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
414 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
415 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
416 {0xce4, 0x00000000}, {0xce8, 0x37644302},
417 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
418 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
419 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
420 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
421 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
422 {0xd34, 0x80608000}, {0xd38, 0x00000000},
423 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
424 {0xd44, 0x00000000}, {0xd48, 0x00000000},
425 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
426 {0xd54, 0x00000000}, {0xd58, 0x00000000},
427 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
428 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
429 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
430 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
431 {0xe00, 0x24242424}, {0xe04, 0x24242424},
432 {0xe08, 0x03902024}, {0xe10, 0x24242424},
433 {0xe14, 0x24242424}, {0xe18, 0x24242424},
434 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
435 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
436 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
437 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
438 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
439 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
440 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
441 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
442 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
443 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
444 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
445 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
446 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
447 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
448 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
449 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
450 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
451 {0xf00, 0x00000300},
452 {0xffff, 0xffffffff},
453 };
454
455 static const struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
456 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
457 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
458 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
459 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
460 {0xc78, 0x78080001}, {0xc78, 0x77090001},
461 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
462 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
463 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
464 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
465 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
466 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
467 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
468 {0xc78, 0x68180001}, {0xc78, 0x67190001},
469 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
470 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
471 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
472 {0xc78, 0x60200001}, {0xc78, 0x49210001},
473 {0xc78, 0x48220001}, {0xc78, 0x47230001},
474 {0xc78, 0x46240001}, {0xc78, 0x45250001},
475 {0xc78, 0x44260001}, {0xc78, 0x43270001},
476 {0xc78, 0x42280001}, {0xc78, 0x41290001},
477 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
478 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
479 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
480 {0xc78, 0x21300001}, {0xc78, 0x20310001},
481 {0xc78, 0x06320001}, {0xc78, 0x05330001},
482 {0xc78, 0x04340001}, {0xc78, 0x03350001},
483 {0xc78, 0x02360001}, {0xc78, 0x01370001},
484 {0xc78, 0x00380001}, {0xc78, 0x00390001},
485 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
486 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
487 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
488 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
489 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
490 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
491 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
492 {0xc78, 0x78480001}, {0xc78, 0x77490001},
493 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
494 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
495 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
496 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
497 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
498 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
499 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
500 {0xc78, 0x68580001}, {0xc78, 0x67590001},
501 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
502 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
503 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
504 {0xc78, 0x60600001}, {0xc78, 0x49610001},
505 {0xc78, 0x48620001}, {0xc78, 0x47630001},
506 {0xc78, 0x46640001}, {0xc78, 0x45650001},
507 {0xc78, 0x44660001}, {0xc78, 0x43670001},
508 {0xc78, 0x42680001}, {0xc78, 0x41690001},
509 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
510 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
511 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
512 {0xc78, 0x21700001}, {0xc78, 0x20710001},
513 {0xc78, 0x06720001}, {0xc78, 0x05730001},
514 {0xc78, 0x04740001}, {0xc78, 0x03750001},
515 {0xc78, 0x02760001}, {0xc78, 0x01770001},
516 {0xc78, 0x00780001}, {0xc78, 0x00790001},
517 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
518 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
519 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
520 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
521 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
522 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
523 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
524 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
525 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
526 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
527 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
528 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
529 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
530 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
531 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
532 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
533 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
534 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
535 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
536 {0xffff, 0xffffffff}
537 };
538
539 static const struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
540 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
541 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
542 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
543 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
544 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
545 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
546 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
547 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
548 {0xc78, 0x73100001}, {0xc78, 0x72110001},
549 {0xc78, 0x71120001}, {0xc78, 0x70130001},
550 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
551 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
552 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
553 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
554 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
555 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
556 {0xc78, 0x63200001}, {0xc78, 0x62210001},
557 {0xc78, 0x61220001}, {0xc78, 0x60230001},
558 {0xc78, 0x46240001}, {0xc78, 0x45250001},
559 {0xc78, 0x44260001}, {0xc78, 0x43270001},
560 {0xc78, 0x42280001}, {0xc78, 0x41290001},
561 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
562 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
563 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
564 {0xc78, 0x21300001}, {0xc78, 0x20310001},
565 {0xc78, 0x06320001}, {0xc78, 0x05330001},
566 {0xc78, 0x04340001}, {0xc78, 0x03350001},
567 {0xc78, 0x02360001}, {0xc78, 0x01370001},
568 {0xc78, 0x00380001}, {0xc78, 0x00390001},
569 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
570 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
571 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
572 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
573 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
574 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
575 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
576 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
577 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
578 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
579 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
580 {0xc78, 0x73500001}, {0xc78, 0x72510001},
581 {0xc78, 0x71520001}, {0xc78, 0x70530001},
582 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
583 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
584 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
585 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
586 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
587 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
588 {0xc78, 0x63600001}, {0xc78, 0x62610001},
589 {0xc78, 0x61620001}, {0xc78, 0x60630001},
590 {0xc78, 0x46640001}, {0xc78, 0x45650001},
591 {0xc78, 0x44660001}, {0xc78, 0x43670001},
592 {0xc78, 0x42680001}, {0xc78, 0x41690001},
593 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
594 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
595 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
596 {0xc78, 0x21700001}, {0xc78, 0x20710001},
597 {0xc78, 0x06720001}, {0xc78, 0x05730001},
598 {0xc78, 0x04740001}, {0xc78, 0x03750001},
599 {0xc78, 0x02760001}, {0xc78, 0x01770001},
600 {0xc78, 0x00780001}, {0xc78, 0x00790001},
601 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
602 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
603 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
604 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
605 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
606 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
607 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
608 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
609 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
610 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
611 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
612 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
613 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
614 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
615 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
616 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
617 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
618 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
619 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
620 {0xffff, 0xffffffff}
621 };
622
623 static const struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
624 { /* RF_A */
625 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
626 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
627 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
628 .hspiread = REG_HSPI_XA_READBACK,
629 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
630 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
631 },
632 { /* RF_B */
633 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
634 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
635 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
636 .hspiread = REG_HSPI_XB_READBACK,
637 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
638 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
639 },
640 };
641
642 const u32 rtl8xxxu_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
643 REG_OFDM0_XA_RX_IQ_IMBALANCE,
644 REG_OFDM0_XB_RX_IQ_IMBALANCE,
645 REG_OFDM0_ENERGY_CCA_THRES,
646 REG_OFDM0_AGC_RSSI_TABLE,
647 REG_OFDM0_XA_TX_IQ_IMBALANCE,
648 REG_OFDM0_XB_TX_IQ_IMBALANCE,
649 REG_OFDM0_XC_TX_AFE,
650 REG_OFDM0_XD_TX_AFE,
651 REG_OFDM0_RX_IQ_EXT_ANTA
652 };
653
rtl8xxxu_read8(struct rtl8xxxu_priv * priv,u16 addr)654 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
655 {
656 struct usb_device *udev = priv->udev;
657 int len;
658 u8 data;
659
660 if (priv->rtl_chip == RTL8710B && addr <= 0xff)
661 addr |= 0x8000;
662
663 mutex_lock(&priv->usb_buf_mutex);
664 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
665 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
666 addr, 0, &priv->usb_buf.val8, sizeof(u8),
667 RTW_USB_CONTROL_MSG_TIMEOUT);
668 data = priv->usb_buf.val8;
669 mutex_unlock(&priv->usb_buf_mutex);
670
671 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
672 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
673 __func__, addr, data, len);
674 return data;
675 }
676
rtl8xxxu_read16(struct rtl8xxxu_priv * priv,u16 addr)677 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
678 {
679 struct usb_device *udev = priv->udev;
680 int len;
681 u16 data;
682
683 if (priv->rtl_chip == RTL8710B && addr <= 0xff)
684 addr |= 0x8000;
685
686 mutex_lock(&priv->usb_buf_mutex);
687 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
688 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
689 addr, 0, &priv->usb_buf.val16, sizeof(u16),
690 RTW_USB_CONTROL_MSG_TIMEOUT);
691 data = le16_to_cpu(priv->usb_buf.val16);
692 mutex_unlock(&priv->usb_buf_mutex);
693
694 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
695 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
696 __func__, addr, data, len);
697 return data;
698 }
699
rtl8xxxu_read32(struct rtl8xxxu_priv * priv,u16 addr)700 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
701 {
702 struct usb_device *udev = priv->udev;
703 int len;
704 u32 data;
705
706 if (priv->rtl_chip == RTL8710B && addr <= 0xff)
707 addr |= 0x8000;
708
709 mutex_lock(&priv->usb_buf_mutex);
710 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
711 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
712 addr, 0, &priv->usb_buf.val32, sizeof(u32),
713 RTW_USB_CONTROL_MSG_TIMEOUT);
714 data = le32_to_cpu(priv->usb_buf.val32);
715 mutex_unlock(&priv->usb_buf_mutex);
716
717 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
718 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
719 __func__, addr, data, len);
720 return data;
721 }
722
rtl8xxxu_write8(struct rtl8xxxu_priv * priv,u16 addr,u8 val)723 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
724 {
725 struct usb_device *udev = priv->udev;
726 int ret;
727
728 if (priv->rtl_chip == RTL8710B && addr <= 0xff)
729 addr |= 0x8000;
730
731 mutex_lock(&priv->usb_buf_mutex);
732 priv->usb_buf.val8 = val;
733 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
734 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
735 addr, 0, &priv->usb_buf.val8, sizeof(u8),
736 RTW_USB_CONTROL_MSG_TIMEOUT);
737
738 mutex_unlock(&priv->usb_buf_mutex);
739
740 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
741 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
742 __func__, addr, val);
743 return ret;
744 }
745
rtl8xxxu_write16(struct rtl8xxxu_priv * priv,u16 addr,u16 val)746 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
747 {
748 struct usb_device *udev = priv->udev;
749 int ret;
750
751 if (priv->rtl_chip == RTL8710B && addr <= 0xff)
752 addr |= 0x8000;
753
754 mutex_lock(&priv->usb_buf_mutex);
755 priv->usb_buf.val16 = cpu_to_le16(val);
756 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
757 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
758 addr, 0, &priv->usb_buf.val16, sizeof(u16),
759 RTW_USB_CONTROL_MSG_TIMEOUT);
760 mutex_unlock(&priv->usb_buf_mutex);
761
762 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
763 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
764 __func__, addr, val);
765 return ret;
766 }
767
rtl8xxxu_write32(struct rtl8xxxu_priv * priv,u16 addr,u32 val)768 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
769 {
770 struct usb_device *udev = priv->udev;
771 int ret;
772
773 if (priv->rtl_chip == RTL8710B && addr <= 0xff)
774 addr |= 0x8000;
775
776 mutex_lock(&priv->usb_buf_mutex);
777 priv->usb_buf.val32 = cpu_to_le32(val);
778 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
779 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
780 addr, 0, &priv->usb_buf.val32, sizeof(u32),
781 RTW_USB_CONTROL_MSG_TIMEOUT);
782 mutex_unlock(&priv->usb_buf_mutex);
783
784 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
785 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
786 __func__, addr, val);
787 return ret;
788 }
789
rtl8xxxu_write8_set(struct rtl8xxxu_priv * priv,u16 addr,u8 bits)790 int rtl8xxxu_write8_set(struct rtl8xxxu_priv *priv, u16 addr, u8 bits)
791 {
792 u8 val8;
793
794 val8 = rtl8xxxu_read8(priv, addr);
795 val8 |= bits;
796 return rtl8xxxu_write8(priv, addr, val8);
797 }
798
rtl8xxxu_write8_clear(struct rtl8xxxu_priv * priv,u16 addr,u8 bits)799 int rtl8xxxu_write8_clear(struct rtl8xxxu_priv *priv, u16 addr, u8 bits)
800 {
801 u8 val8;
802
803 val8 = rtl8xxxu_read8(priv, addr);
804 val8 &= ~bits;
805 return rtl8xxxu_write8(priv, addr, val8);
806 }
807
rtl8xxxu_write16_set(struct rtl8xxxu_priv * priv,u16 addr,u16 bits)808 int rtl8xxxu_write16_set(struct rtl8xxxu_priv *priv, u16 addr, u16 bits)
809 {
810 u16 val16;
811
812 val16 = rtl8xxxu_read16(priv, addr);
813 val16 |= bits;
814 return rtl8xxxu_write16(priv, addr, val16);
815 }
816
rtl8xxxu_write16_clear(struct rtl8xxxu_priv * priv,u16 addr,u16 bits)817 int rtl8xxxu_write16_clear(struct rtl8xxxu_priv *priv, u16 addr, u16 bits)
818 {
819 u16 val16;
820
821 val16 = rtl8xxxu_read16(priv, addr);
822 val16 &= ~bits;
823 return rtl8xxxu_write16(priv, addr, val16);
824 }
825
rtl8xxxu_write32_set(struct rtl8xxxu_priv * priv,u16 addr,u32 bits)826 int rtl8xxxu_write32_set(struct rtl8xxxu_priv *priv, u16 addr, u32 bits)
827 {
828 u32 val32;
829
830 val32 = rtl8xxxu_read32(priv, addr);
831 val32 |= bits;
832 return rtl8xxxu_write32(priv, addr, val32);
833 }
834
rtl8xxxu_write32_clear(struct rtl8xxxu_priv * priv,u16 addr,u32 bits)835 int rtl8xxxu_write32_clear(struct rtl8xxxu_priv *priv, u16 addr, u32 bits)
836 {
837 u32 val32;
838
839 val32 = rtl8xxxu_read32(priv, addr);
840 val32 &= ~bits;
841 return rtl8xxxu_write32(priv, addr, val32);
842 }
843
rtl8xxxu_write32_mask(struct rtl8xxxu_priv * priv,u16 addr,u32 mask,u32 val)844 int rtl8xxxu_write32_mask(struct rtl8xxxu_priv *priv, u16 addr,
845 u32 mask, u32 val)
846 {
847 u32 orig, new, shift;
848
849 shift = __ffs(mask);
850
851 orig = rtl8xxxu_read32(priv, addr);
852 new = (orig & ~mask) | ((val << shift) & mask);
853 return rtl8xxxu_write32(priv, addr, new);
854 }
855
rtl8xxxu_write_rfreg_mask(struct rtl8xxxu_priv * priv,enum rtl8xxxu_rfpath path,u8 reg,u32 mask,u32 val)856 int rtl8xxxu_write_rfreg_mask(struct rtl8xxxu_priv *priv,
857 enum rtl8xxxu_rfpath path, u8 reg,
858 u32 mask, u32 val)
859 {
860 u32 orig, new, shift;
861
862 shift = __ffs(mask);
863
864 orig = rtl8xxxu_read_rfreg(priv, path, reg);
865 new = (orig & ~mask) | ((val << shift) & mask);
866 return rtl8xxxu_write_rfreg(priv, path, reg, new);
867 }
868
869 static int
rtl8xxxu_writeN(struct rtl8xxxu_priv * priv,u16 addr,u8 * buf,u16 len)870 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
871 {
872 struct usb_device *udev = priv->udev;
873 int blocksize = priv->fops->writeN_block_size;
874 int ret, i, count, remainder;
875
876 count = len / blocksize;
877 remainder = len % blocksize;
878
879 for (i = 0; i < count; i++) {
880 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
881 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
882 addr, 0, buf, blocksize,
883 RTW_USB_CONTROL_MSG_TIMEOUT);
884 if (ret != blocksize)
885 goto write_error;
886
887 addr += blocksize;
888 buf += blocksize;
889 }
890
891 if (remainder) {
892 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
893 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
894 addr, 0, buf, remainder,
895 RTW_USB_CONTROL_MSG_TIMEOUT);
896 if (ret != remainder)
897 goto write_error;
898 }
899
900 return len;
901
902 write_error:
903 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
904 dev_info(&udev->dev,
905 "%s: Failed to write block at addr: %04x size: %04x\n",
906 __func__, addr, blocksize);
907 return -EAGAIN;
908 }
909
rtl8xxxu_read_rfreg(struct rtl8xxxu_priv * priv,enum rtl8xxxu_rfpath path,u8 reg)910 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
911 enum rtl8xxxu_rfpath path, u8 reg)
912 {
913 u32 hssia, val32, retval;
914
915 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
916 if (path != RF_A)
917 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
918 else
919 val32 = hssia;
920
921 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
922 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
923 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
924 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
925 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
926
927 udelay(10);
928
929 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
930 udelay(100);
931
932 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
933 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
934 udelay(10);
935
936 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
937 if (val32 & FPGA0_HSSI_PARM1_PI)
938 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
939 else
940 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
941
942 retval &= 0xfffff;
943
944 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
945 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
946 __func__, reg, retval);
947 return retval;
948 }
949
950 /*
951 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
952 * have write issues in high temperature conditions. We may have to
953 * retry writing them.
954 */
rtl8xxxu_write_rfreg(struct rtl8xxxu_priv * priv,enum rtl8xxxu_rfpath path,u8 reg,u32 data)955 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
956 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
957 {
958 int ret, retval;
959 u32 dataaddr, val32;
960
961 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
962 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
963 __func__, reg, data);
964
965 data &= FPGA0_LSSI_PARM_DATA_MASK;
966 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
967
968 if (priv->rtl_chip == RTL8192E) {
969 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
970 val32 &= ~0x20000;
971 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
972 }
973
974 /* Use XB for path B */
975 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
976 if (ret != sizeof(dataaddr))
977 retval = -EIO;
978 else
979 retval = 0;
980
981 udelay(1);
982
983 if (priv->rtl_chip == RTL8192E) {
984 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
985 val32 |= 0x20000;
986 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
987 }
988
989 return retval;
990 }
991
992 static int
rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv * priv,struct h2c_cmd * h2c,int len)993 rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len)
994 {
995 struct device *dev = &priv->udev->dev;
996 int mbox_nr, retry, retval = 0;
997 int mbox_reg, mbox_ext_reg;
998 u8 val8;
999
1000 mutex_lock(&priv->h2c_mutex);
1001
1002 mbox_nr = priv->next_mbox;
1003 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1004 mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2);
1005
1006 /*
1007 * MBOX ready?
1008 */
1009 retry = 100;
1010 do {
1011 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1012 if (!(val8 & BIT(mbox_nr)))
1013 break;
1014 } while (retry--);
1015
1016 if (!retry) {
1017 dev_info(dev, "%s: Mailbox busy\n", __func__);
1018 retval = -EBUSY;
1019 goto error;
1020 }
1021
1022 /*
1023 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1024 */
1025 if (len > sizeof(u32)) {
1026 rtl8xxxu_write16(priv, mbox_ext_reg, le16_to_cpu(h2c->raw.ext));
1027 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1028 dev_info(dev, "H2C_EXT %04x\n",
1029 le16_to_cpu(h2c->raw.ext));
1030 }
1031 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1032 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1033 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1034
1035 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1036
1037 error:
1038 mutex_unlock(&priv->h2c_mutex);
1039 return retval;
1040 }
1041
1042 int
rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv * priv,struct h2c_cmd * h2c,int len)1043 rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len)
1044 {
1045 struct device *dev = &priv->udev->dev;
1046 int mbox_nr, retry, retval = 0;
1047 int mbox_reg, mbox_ext_reg;
1048 u8 val8;
1049
1050 mutex_lock(&priv->h2c_mutex);
1051
1052 mbox_nr = priv->next_mbox;
1053 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1054 mbox_ext_reg = REG_HMBOX_EXT0_8723B + (mbox_nr * 4);
1055
1056 /*
1057 * MBOX ready?
1058 */
1059 retry = 100;
1060 do {
1061 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1062 if (!(val8 & BIT(mbox_nr)))
1063 break;
1064 } while (retry--);
1065
1066 if (!retry) {
1067 dev_info(dev, "%s: Mailbox busy\n", __func__);
1068 retval = -EBUSY;
1069 goto error;
1070 }
1071
1072 /*
1073 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1074 */
1075 if (len > sizeof(u32)) {
1076 rtl8xxxu_write32(priv, mbox_ext_reg,
1077 le32_to_cpu(h2c->raw_wide.ext));
1078 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1079 dev_info(dev, "H2C_EXT %08x\n",
1080 le32_to_cpu(h2c->raw_wide.ext));
1081 }
1082 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1083 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1084 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1085
1086 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1087
1088 error:
1089 mutex_unlock(&priv->h2c_mutex);
1090 return retval;
1091 }
1092
rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv * priv)1093 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv)
1094 {
1095 u8 val8;
1096 u32 val32;
1097
1098 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1099 val8 |= BIT(0) | BIT(3);
1100 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1101
1102 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1103 val32 &= ~(BIT(4) | BIT(5));
1104 val32 |= BIT(3);
1105 if (priv->rf_paths == 2) {
1106 val32 &= ~(BIT(20) | BIT(21));
1107 val32 |= BIT(19);
1108 }
1109 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1110
1111 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1112 val32 &= ~OFDM_RF_PATH_TX_MASK;
1113 if (priv->tx_paths == 2)
1114 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1115 else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C)
1116 val32 |= OFDM_RF_PATH_TX_B;
1117 else
1118 val32 |= OFDM_RF_PATH_TX_A;
1119 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1120
1121 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1122 val32 &= ~FPGA_RF_MODE_JAPAN;
1123 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1124
1125 if (priv->rf_paths == 2)
1126 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1127 else
1128 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1129
1130 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1131 if (priv->rf_paths == 2)
1132 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1133
1134 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1135 }
1136
rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv * priv)1137 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv)
1138 {
1139 u8 sps0;
1140 u32 val32;
1141
1142 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1143
1144 /* RF RX code for preamble power saving */
1145 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1146 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1147 if (priv->rf_paths == 2)
1148 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1149 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1150
1151 /* Disable TX for four paths */
1152 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1153 val32 &= ~OFDM_RF_PATH_TX_MASK;
1154 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1155
1156 /* Enable power saving */
1157 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1158 val32 |= FPGA_RF_MODE_JAPAN;
1159 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1160
1161 /* AFE control register to power down bits [30:22] */
1162 if (priv->rf_paths == 2)
1163 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1164 else
1165 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1166
1167 /* Power down RF module */
1168 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1169 if (priv->rf_paths == 2)
1170 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1171
1172 sps0 &= ~(BIT(0) | BIT(3));
1173 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1174 }
1175
rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv * priv)1176 static void rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1177 {
1178 u8 val8;
1179
1180 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1181 val8 &= ~BIT(6);
1182 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1183
1184 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1185 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1186 val8 &= ~BIT(0);
1187 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1188 }
1189
rtl8xxxu_start_tx_beacon(struct rtl8xxxu_priv * priv)1190 static void rtl8xxxu_start_tx_beacon(struct rtl8xxxu_priv *priv)
1191 {
1192 u8 val8;
1193
1194 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1195 val8 |= EN_BCNQ_DL >> 16;
1196 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1197
1198 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x80);
1199 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1200 val8 &= 0xF0;
1201 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1202 }
1203
1204
1205 /*
1206 * The rtl8723a has 3 channel groups for it's efuse settings. It only
1207 * supports the 2.4GHz band, so channels 1 - 14:
1208 * group 0: channels 1 - 3
1209 * group 1: channels 4 - 9
1210 * group 2: channels 10 - 14
1211 *
1212 * Note: We index from 0 in the code
1213 */
rtl8xxxu_gen1_channel_to_group(int channel)1214 static int rtl8xxxu_gen1_channel_to_group(int channel)
1215 {
1216 int group;
1217
1218 if (channel < 4)
1219 group = 0;
1220 else if (channel < 10)
1221 group = 1;
1222 else
1223 group = 2;
1224
1225 return group;
1226 }
1227
1228 /*
1229 * Valid for rtl8723bu and rtl8192eu
1230 */
rtl8xxxu_gen2_channel_to_group(int channel)1231 int rtl8xxxu_gen2_channel_to_group(int channel)
1232 {
1233 int group;
1234
1235 if (channel < 3)
1236 group = 0;
1237 else if (channel < 6)
1238 group = 1;
1239 else if (channel < 9)
1240 group = 2;
1241 else if (channel < 12)
1242 group = 3;
1243 else
1244 group = 4;
1245
1246 return group;
1247 }
1248
rtl8xxxu_gen1_config_channel(struct ieee80211_hw * hw)1249 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw)
1250 {
1251 struct rtl8xxxu_priv *priv = hw->priv;
1252 u32 val32, rsr;
1253 u8 val8, opmode;
1254 bool ht = true;
1255 int sec_ch_above, channel;
1256 int i;
1257
1258 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1259 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1260 channel = hw->conf.chandef.chan->hw_value;
1261
1262 switch (hw->conf.chandef.width) {
1263 case NL80211_CHAN_WIDTH_20_NOHT:
1264 ht = false;
1265 fallthrough;
1266 case NL80211_CHAN_WIDTH_20:
1267 opmode |= BW_OPMODE_20MHZ;
1268 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1269
1270 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1271 val32 &= ~FPGA_RF_MODE;
1272 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1273
1274 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1275 val32 &= ~FPGA_RF_MODE;
1276 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1277
1278 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1279 val32 |= FPGA0_ANALOG2_20MHZ;
1280 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1281 break;
1282 case NL80211_CHAN_WIDTH_40:
1283 if (hw->conf.chandef.center_freq1 >
1284 hw->conf.chandef.chan->center_freq) {
1285 sec_ch_above = 1;
1286 channel += 2;
1287 } else {
1288 sec_ch_above = 0;
1289 channel -= 2;
1290 }
1291
1292 opmode &= ~BW_OPMODE_20MHZ;
1293 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1294 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1295 if (sec_ch_above)
1296 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1297 else
1298 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1299 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1300
1301 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1302 val32 |= FPGA_RF_MODE;
1303 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1304
1305 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1306 val32 |= FPGA_RF_MODE;
1307 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1308
1309 /*
1310 * Set Control channel to upper or lower. These settings
1311 * are required only for 40MHz
1312 */
1313 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1314 val32 &= ~CCK0_SIDEBAND;
1315 if (!sec_ch_above)
1316 val32 |= CCK0_SIDEBAND;
1317 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1318
1319 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1320 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1321 if (sec_ch_above)
1322 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1323 else
1324 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1325 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1326
1327 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1328 val32 &= ~FPGA0_ANALOG2_20MHZ;
1329 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1330
1331 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1332 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1333 if (sec_ch_above)
1334 val32 |= FPGA0_PS_UPPER_CHANNEL;
1335 else
1336 val32 |= FPGA0_PS_LOWER_CHANNEL;
1337 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1338 break;
1339
1340 default:
1341 break;
1342 }
1343
1344 for (i = RF_A; i < priv->rf_paths; i++) {
1345 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1346 val32 &= ~MODE_AG_CHANNEL_MASK;
1347 val32 |= channel;
1348 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1349 }
1350
1351 if (ht)
1352 val8 = 0x0e;
1353 else
1354 val8 = 0x0a;
1355
1356 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1357 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1358
1359 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1360 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1361
1362 for (i = RF_A; i < priv->rf_paths; i++) {
1363 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1364 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1365 val32 &= ~MODE_AG_CHANNEL_20MHZ;
1366 else
1367 val32 |= MODE_AG_CHANNEL_20MHZ;
1368 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1369 }
1370 }
1371
rtl8xxxu_gen2_config_channel(struct ieee80211_hw * hw)1372 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw)
1373 {
1374 struct rtl8xxxu_priv *priv = hw->priv;
1375 u32 val32;
1376 u8 val8, subchannel;
1377 u16 rf_mode_bw;
1378 bool ht = true;
1379 int sec_ch_above, channel;
1380 int i;
1381
1382 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
1383 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;
1384 channel = hw->conf.chandef.chan->hw_value;
1385
1386 /* Hack */
1387 subchannel = 0;
1388
1389 switch (hw->conf.chandef.width) {
1390 case NL80211_CHAN_WIDTH_20_NOHT:
1391 ht = false;
1392 fallthrough;
1393 case NL80211_CHAN_WIDTH_20:
1394 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;
1395 subchannel = 0;
1396
1397 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1398 val32 &= ~FPGA_RF_MODE;
1399 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1400
1401 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1402 val32 &= ~FPGA_RF_MODE;
1403 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1404
1405 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
1406 val32 &= ~(BIT(30) | BIT(31));
1407 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
1408
1409 break;
1410 case NL80211_CHAN_WIDTH_40:
1411 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;
1412
1413 if (hw->conf.chandef.center_freq1 >
1414 hw->conf.chandef.chan->center_freq) {
1415 sec_ch_above = 1;
1416 channel += 2;
1417 } else {
1418 sec_ch_above = 0;
1419 channel -= 2;
1420 }
1421
1422 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1423 val32 |= FPGA_RF_MODE;
1424 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1425
1426 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1427 val32 |= FPGA_RF_MODE;
1428 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1429
1430 /*
1431 * Set Control channel to upper or lower. These settings
1432 * are required only for 40MHz
1433 */
1434 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1435 val32 &= ~CCK0_SIDEBAND;
1436 if (!sec_ch_above)
1437 val32 |= CCK0_SIDEBAND;
1438 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1439
1440 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1441 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1442 if (sec_ch_above)
1443 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1444 else
1445 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1446 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1447
1448 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1449 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1450 if (sec_ch_above)
1451 val32 |= FPGA0_PS_UPPER_CHANNEL;
1452 else
1453 val32 |= FPGA0_PS_LOWER_CHANNEL;
1454 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1455 break;
1456 case NL80211_CHAN_WIDTH_80:
1457 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;
1458 break;
1459 default:
1460 break;
1461 }
1462
1463 for (i = RF_A; i < priv->rf_paths; i++) {
1464 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1465 val32 &= ~MODE_AG_CHANNEL_MASK;
1466 val32 |= channel;
1467 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1468 }
1469
1470 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);
1471 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
1472
1473 if (ht)
1474 val8 = 0x0e;
1475 else
1476 val8 = 0x0a;
1477
1478 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1479 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1480
1481 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1482 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1483
1484 for (i = RF_A; i < priv->rf_paths; i++) {
1485 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1486 val32 &= ~MODE_AG_BW_MASK;
1487 switch(hw->conf.chandef.width) {
1488 case NL80211_CHAN_WIDTH_80:
1489 val32 |= MODE_AG_BW_80MHZ_8723B;
1490 break;
1491 case NL80211_CHAN_WIDTH_40:
1492 val32 |= MODE_AG_BW_40MHZ_8723B;
1493 break;
1494 default:
1495 val32 |= MODE_AG_BW_20MHZ_8723B;
1496 break;
1497 }
1498 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1499 }
1500 }
1501
1502 void
rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv * priv,int channel,bool ht40)1503 rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1504 {
1505 struct rtl8xxxu_power_base *power_base = priv->power_base;
1506 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1507 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1508 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1509 u8 val8, base;
1510 int group, i;
1511
1512 group = rtl8xxxu_gen1_channel_to_group(channel);
1513
1514 cck[0] = priv->cck_tx_power_index_A[group];
1515 cck[1] = priv->cck_tx_power_index_B[group];
1516
1517 if (priv->hi_pa) {
1518 if (cck[0] > 0x20)
1519 cck[0] = 0x20;
1520 if (cck[1] > 0x20)
1521 cck[1] = 0x20;
1522 }
1523
1524 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1525 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1526
1527 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1528 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1529
1530 mcsbase[0] = ofdm[0];
1531 mcsbase[1] = ofdm[1];
1532 if (!ht40) {
1533 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1534 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1535 }
1536
1537 if (priv->tx_paths > 1) {
1538 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1539 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
1540 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1541 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
1542 }
1543
1544 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1545 dev_info(&priv->udev->dev,
1546 "%s: Setting TX power CCK A: %02x, "
1547 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1548 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1549
1550 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1551 if (cck[i] > RF6052_MAX_TX_PWR)
1552 cck[i] = RF6052_MAX_TX_PWR;
1553 if (ofdm[i] > RF6052_MAX_TX_PWR)
1554 ofdm[i] = RF6052_MAX_TX_PWR;
1555 }
1556
1557 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1558 val32 &= 0xffff00ff;
1559 val32 |= (cck[0] << 8);
1560 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1561
1562 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1563 val32 &= 0xff;
1564 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1565 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1566
1567 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1568 val32 &= 0xffffff00;
1569 val32 |= cck[1];
1570 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1571
1572 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1573 val32 &= 0xff;
1574 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1575 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1576
1577 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1578 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1579 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1580 ofdmbase[1] << 16 | ofdmbase[1] << 24;
1581
1582 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06,
1583 ofdm_a + power_base->reg_0e00);
1584 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06,
1585 ofdm_b + power_base->reg_0830);
1586
1587 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24,
1588 ofdm_a + power_base->reg_0e04);
1589 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24,
1590 ofdm_b + power_base->reg_0834);
1591
1592 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1593 mcsbase[0] << 16 | mcsbase[0] << 24;
1594 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1595 mcsbase[1] << 16 | mcsbase[1] << 24;
1596
1597 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00,
1598 mcs_a + power_base->reg_0e10);
1599 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00,
1600 mcs_b + power_base->reg_083c);
1601
1602 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04,
1603 mcs_a + power_base->reg_0e14);
1604 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04,
1605 mcs_b + power_base->reg_0848);
1606
1607 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08,
1608 mcs_a + power_base->reg_0e18);
1609 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08,
1610 mcs_b + power_base->reg_084c);
1611
1612 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12,
1613 mcs_a + power_base->reg_0e1c);
1614 val8 = u32_get_bits(mcs_a + power_base->reg_0e1c, 0xff000000);
1615 for (i = 0; i < 3; i++) {
1616 base = i != 2 ? 8 : 6;
1617 val8 = max_t(int, val8 - base, 0);
1618 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1619 }
1620
1621 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12,
1622 mcs_b + power_base->reg_0868);
1623 val8 = u32_get_bits(mcs_b + power_base->reg_0868, 0xff000000);
1624 for (i = 0; i < 3; i++) {
1625 base = i != 2 ? 8 : 6;
1626 val8 = max_t(int, val8 - base, 0);
1627 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1628 }
1629 }
1630
rtl8xxxu_set_linktype(struct rtl8xxxu_priv * priv,enum nl80211_iftype linktype)1631 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1632 enum nl80211_iftype linktype)
1633 {
1634 u8 val8;
1635
1636 val8 = rtl8xxxu_read8(priv, REG_MSR);
1637 val8 &= ~MSR_LINKTYPE_MASK;
1638
1639 switch (linktype) {
1640 case NL80211_IFTYPE_UNSPECIFIED:
1641 val8 |= MSR_LINKTYPE_NONE;
1642 break;
1643 case NL80211_IFTYPE_ADHOC:
1644 val8 |= MSR_LINKTYPE_ADHOC;
1645 break;
1646 case NL80211_IFTYPE_STATION:
1647 val8 |= MSR_LINKTYPE_STATION;
1648 break;
1649 case NL80211_IFTYPE_AP:
1650 val8 |= MSR_LINKTYPE_AP;
1651 break;
1652 default:
1653 goto out;
1654 }
1655
1656 rtl8xxxu_write8(priv, REG_MSR, val8);
1657 out:
1658 return;
1659 }
1660
1661 static void
rtl8xxxu_set_retry(struct rtl8xxxu_priv * priv,u16 short_retry,u16 long_retry)1662 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1663 {
1664 u16 val16;
1665
1666 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1667 RETRY_LIMIT_SHORT_MASK) |
1668 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1669 RETRY_LIMIT_LONG_MASK);
1670
1671 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1672 }
1673
1674 static void
rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv * priv,u16 cck,u16 ofdm)1675 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1676 {
1677 u16 val16;
1678
1679 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1680 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1681
1682 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1683 }
1684
rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv * priv)1685 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1686 {
1687 struct device *dev = &priv->udev->dev;
1688 char cut = 'A' + priv->chip_cut;
1689
1690 dev_info(dev,
1691 "RTL%s rev %c (%s) romver %d, %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
1692 priv->chip_name, cut, priv->chip_vendor, priv->rom_rev,
1693 priv->tx_paths, priv->rx_paths, priv->ep_tx_count,
1694 priv->has_wifi, priv->has_bluetooth, priv->has_gps,
1695 priv->hi_pa);
1696
1697 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1698 }
1699
rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv * priv,u32 vendor)1700 void rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv *priv, u32 vendor)
1701 {
1702 if (vendor) {
1703 strscpy(priv->chip_vendor, "UMC", sizeof(priv->chip_vendor));
1704 priv->vendor_umc = 1;
1705 } else {
1706 strscpy(priv->chip_vendor, "TSMC", sizeof(priv->chip_vendor));
1707 }
1708 }
1709
rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv * priv,u32 vendor)1710 void rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv *priv, u32 vendor)
1711 {
1712 switch (vendor) {
1713 case SYS_CFG_VENDOR_ID_TSMC:
1714 strscpy(priv->chip_vendor, "TSMC", sizeof(priv->chip_vendor));
1715 break;
1716 case SYS_CFG_VENDOR_ID_SMIC:
1717 strscpy(priv->chip_vendor, "SMIC", sizeof(priv->chip_vendor));
1718 priv->vendor_smic = 1;
1719 break;
1720 case SYS_CFG_VENDOR_ID_UMC:
1721 strscpy(priv->chip_vendor, "UMC", sizeof(priv->chip_vendor));
1722 priv->vendor_umc = 1;
1723 break;
1724 default:
1725 strscpy(priv->chip_vendor, "unknown", sizeof(priv->chip_vendor));
1726 }
1727 }
1728
rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv * priv)1729 void rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv *priv)
1730 {
1731 u16 val16;
1732
1733 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
1734
1735 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
1736 priv->ep_tx_high_queue = 1;
1737 priv->ep_tx_count++;
1738 }
1739
1740 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
1741 priv->ep_tx_normal_queue = 1;
1742 priv->ep_tx_count++;
1743 }
1744
1745 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
1746 priv->ep_tx_low_queue = 1;
1747 priv->ep_tx_count++;
1748 }
1749 }
1750
rtl8xxxu_config_endpoints_no_sie(struct rtl8xxxu_priv * priv)1751 int rtl8xxxu_config_endpoints_no_sie(struct rtl8xxxu_priv *priv)
1752 {
1753 struct device *dev = &priv->udev->dev;
1754
1755 switch (priv->nr_out_eps) {
1756 case 6:
1757 case 5:
1758 case 4:
1759 case 3:
1760 priv->ep_tx_low_queue = 1;
1761 priv->ep_tx_count++;
1762 fallthrough;
1763 case 2:
1764 priv->ep_tx_normal_queue = 1;
1765 priv->ep_tx_count++;
1766 fallthrough;
1767 case 1:
1768 priv->ep_tx_high_queue = 1;
1769 priv->ep_tx_count++;
1770 break;
1771 default:
1772 dev_info(dev, "Unsupported USB TX end-points\n");
1773 return -ENOTSUPP;
1774 }
1775
1776 return 0;
1777 }
1778
1779 int
rtl8xxxu_read_efuse8(struct rtl8xxxu_priv * priv,u16 offset,u8 * data)1780 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
1781 {
1782 int i;
1783 u8 val8;
1784 u32 val32;
1785
1786 /* Write Address */
1787 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
1788 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
1789 val8 &= 0xfc;
1790 val8 |= (offset >> 8) & 0x03;
1791 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
1792
1793 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
1794 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
1795
1796 /* Poll for data read */
1797 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1798 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
1799 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1800 if (val32 & BIT(31))
1801 break;
1802 }
1803
1804 if (i == RTL8XXXU_MAX_REG_POLL)
1805 return -EIO;
1806
1807 udelay(50);
1808 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1809
1810 *data = val32 & 0xff;
1811 return 0;
1812 }
1813
rtl8xxxu_read_efuse(struct rtl8xxxu_priv * priv)1814 int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
1815 {
1816 struct device *dev = &priv->udev->dev;
1817 int i, ret = 0;
1818 u8 val8, word_mask, header, extheader;
1819 u16 val16, efuse_addr, offset;
1820 u32 val32;
1821
1822 val16 = rtl8xxxu_read16(priv, REG_9346CR);
1823 if (val16 & EEPROM_ENABLE)
1824 priv->has_eeprom = 1;
1825 if (val16 & EEPROM_BOOT)
1826 priv->boot_eeprom = 1;
1827
1828 if (priv->is_multi_func) {
1829 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
1830 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
1831 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
1832 }
1833
1834 dev_dbg(dev, "Booting from %s\n",
1835 priv->boot_eeprom ? "EEPROM" : "EFUSE");
1836
1837 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
1838
1839 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
1840 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
1841 if (!(val16 & SYS_ISO_PWC_EV12V)) {
1842 val16 |= SYS_ISO_PWC_EV12V;
1843 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
1844 }
1845 /* Reset: 0x0000[28], default valid */
1846 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1847 if (!(val16 & SYS_FUNC_ELDR)) {
1848 val16 |= SYS_FUNC_ELDR;
1849 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1850 }
1851
1852 /*
1853 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
1854 */
1855 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
1856 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
1857 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
1858 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
1859 }
1860
1861 /* Default value is 0xff */
1862 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
1863
1864 efuse_addr = 0;
1865 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
1866 u16 map_addr;
1867
1868 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
1869 if (ret || header == 0xff)
1870 goto exit;
1871
1872 if ((header & 0x1f) == 0x0f) { /* extended header */
1873 offset = (header & 0xe0) >> 5;
1874
1875 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
1876 &extheader);
1877 if (ret)
1878 goto exit;
1879 /* All words disabled */
1880 if ((extheader & 0x0f) == 0x0f)
1881 continue;
1882
1883 offset |= ((extheader & 0xf0) >> 1);
1884 word_mask = extheader & 0x0f;
1885 } else {
1886 offset = (header >> 4) & 0x0f;
1887 word_mask = header & 0x0f;
1888 }
1889
1890 /* Get word enable value from PG header */
1891
1892 /* We have 8 bits to indicate validity */
1893 map_addr = offset * 8;
1894 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
1895 /* Check word enable condition in the section */
1896 if (word_mask & BIT(i)) {
1897 map_addr += 2;
1898 continue;
1899 }
1900
1901 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
1902 if (ret)
1903 goto exit;
1904 if (map_addr >= EFUSE_MAP_LEN - 1) {
1905 dev_warn(dev, "%s: Illegal map_addr (%04x), "
1906 "efuse corrupt!\n",
1907 __func__, map_addr);
1908 ret = -EINVAL;
1909 goto exit;
1910 }
1911 priv->efuse_wifi.raw[map_addr++] = val8;
1912
1913 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
1914 if (ret)
1915 goto exit;
1916 priv->efuse_wifi.raw[map_addr++] = val8;
1917 }
1918 }
1919
1920 exit:
1921 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
1922
1923 return ret;
1924 }
1925
rtl8xxxu_dump_efuse(struct rtl8xxxu_priv * priv)1926 static void rtl8xxxu_dump_efuse(struct rtl8xxxu_priv *priv)
1927 {
1928 dev_info(&priv->udev->dev,
1929 "Dumping efuse for RTL%s (0x%02x bytes):\n",
1930 priv->chip_name, EFUSE_MAP_LEN);
1931
1932 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
1933 priv->efuse_wifi.raw, EFUSE_MAP_LEN, true);
1934 }
1935
rtl8xxxu_reset_8051(struct rtl8xxxu_priv * priv)1936 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
1937 {
1938 u8 val8;
1939 u16 sys_func;
1940
1941 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
1942 val8 &= ~BIT(0);
1943 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
1944
1945 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1946 sys_func &= ~SYS_FUNC_CPU_ENABLE;
1947 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
1948
1949 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
1950 val8 |= BIT(0);
1951 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
1952
1953 sys_func |= SYS_FUNC_CPU_ENABLE;
1954 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
1955 }
1956
rtl8xxxu_start_firmware(struct rtl8xxxu_priv * priv)1957 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
1958 {
1959 struct device *dev = &priv->udev->dev;
1960 u16 reg_mcu_fw_dl;
1961 int ret = 0, i;
1962 u32 val32;
1963
1964 if (priv->rtl_chip == RTL8710B)
1965 reg_mcu_fw_dl = REG_8051FW_CTRL_V1_8710B;
1966 else
1967 reg_mcu_fw_dl = REG_MCU_FW_DL;
1968
1969 /* Poll checksum report */
1970 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
1971 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl);
1972 if (val32 & MCU_FW_DL_CSUM_REPORT)
1973 break;
1974 }
1975
1976 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
1977 dev_warn(dev, "Firmware checksum poll timed out\n");
1978 ret = -EAGAIN;
1979 goto exit;
1980 }
1981
1982 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl);
1983 val32 |= MCU_FW_DL_READY;
1984 val32 &= ~MCU_WINT_INIT_READY;
1985 rtl8xxxu_write32(priv, reg_mcu_fw_dl, val32);
1986
1987 /*
1988 * Reset the 8051 in order for the firmware to start running,
1989 * otherwise it won't come up on the 8192eu
1990 */
1991 priv->fops->reset_8051(priv);
1992
1993 /* Wait for firmware to become ready */
1994 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
1995 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl);
1996 if (val32 & MCU_WINT_INIT_READY)
1997 break;
1998
1999 udelay(100);
2000 }
2001
2002 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2003 dev_warn(dev, "Firmware failed to start\n");
2004 ret = -EAGAIN;
2005 goto exit;
2006 }
2007
2008 /*
2009 * Init H2C command
2010 */
2011 if (priv->fops->init_reg_hmtfr)
2012 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);
2013 exit:
2014 return ret;
2015 }
2016
rtl8xxxu_download_firmware(struct rtl8xxxu_priv * priv)2017 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2018 {
2019 int pages, remainder, i, ret;
2020 u16 reg_fw_start_address;
2021 u16 reg_mcu_fw_dl;
2022 u8 val8;
2023 u16 val16;
2024 u32 val32;
2025 u8 *fwptr;
2026
2027 if (priv->rtl_chip == RTL8192F)
2028 reg_fw_start_address = REG_FW_START_ADDRESS_8192F;
2029 else
2030 reg_fw_start_address = REG_FW_START_ADDRESS;
2031
2032 if (priv->rtl_chip == RTL8710B) {
2033 reg_mcu_fw_dl = REG_8051FW_CTRL_V1_8710B;
2034 } else {
2035 reg_mcu_fw_dl = REG_MCU_FW_DL;
2036
2037 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2038 val8 |= 4;
2039 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2040
2041 /* 8051 enable */
2042 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2043 val16 |= SYS_FUNC_CPU_ENABLE;
2044 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2045 }
2046
2047 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl);
2048 if (val8 & MCU_FW_RAM_SEL) {
2049 dev_info(&priv->udev->dev,
2050 "Firmware is already running, resetting the MCU.\n");
2051 rtl8xxxu_write8(priv, reg_mcu_fw_dl, 0x00);
2052 priv->fops->reset_8051(priv);
2053 }
2054
2055 /* MCU firmware download enable */
2056 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl);
2057 val8 |= MCU_FW_DL_ENABLE;
2058 rtl8xxxu_write8(priv, reg_mcu_fw_dl, val8);
2059
2060 /* 8051 reset */
2061 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl);
2062 val32 &= ~BIT(19);
2063 rtl8xxxu_write32(priv, reg_mcu_fw_dl, val32);
2064
2065 if (priv->rtl_chip == RTL8710B) {
2066 /* We must set 0x8090[8]=1 before download FW. */
2067 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 1);
2068 val8 |= BIT(0);
2069 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 1, val8);
2070 }
2071
2072 /* Reset firmware download checksum */
2073 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl);
2074 val8 |= MCU_FW_DL_CSUM_REPORT;
2075 rtl8xxxu_write8(priv, reg_mcu_fw_dl, val8);
2076
2077 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2078 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2079
2080 fwptr = priv->fw_data->data;
2081
2082 for (i = 0; i < pages; i++) {
2083 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 2) & 0xF8;
2084 val8 |= i;
2085 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 2, val8);
2086
2087 ret = rtl8xxxu_writeN(priv, reg_fw_start_address,
2088 fwptr, RTL_FW_PAGE_SIZE);
2089 if (ret != RTL_FW_PAGE_SIZE) {
2090 ret = -EAGAIN;
2091 goto fw_abort;
2092 }
2093
2094 fwptr += RTL_FW_PAGE_SIZE;
2095 }
2096
2097 if (remainder) {
2098 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 2) & 0xF8;
2099 val8 |= i;
2100 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 2, val8);
2101 ret = rtl8xxxu_writeN(priv, reg_fw_start_address,
2102 fwptr, remainder);
2103 if (ret != remainder) {
2104 ret = -EAGAIN;
2105 goto fw_abort;
2106 }
2107 }
2108
2109 ret = 0;
2110 fw_abort:
2111 /* MCU firmware download disable */
2112 val16 = rtl8xxxu_read16(priv, reg_mcu_fw_dl);
2113 val16 &= ~MCU_FW_DL_ENABLE;
2114 rtl8xxxu_write16(priv, reg_mcu_fw_dl, val16);
2115
2116 return ret;
2117 }
2118
rtl8xxxu_load_firmware(struct rtl8xxxu_priv * priv,const char * fw_name)2119 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, const char *fw_name)
2120 {
2121 struct device *dev = &priv->udev->dev;
2122 const struct firmware *fw;
2123 int ret = 0;
2124 u16 signature;
2125
2126 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2127 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2128 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2129 ret = -EAGAIN;
2130 goto exit;
2131 }
2132 if (!fw) {
2133 dev_warn(dev, "Firmware data not available\n");
2134 ret = -EINVAL;
2135 goto exit;
2136 }
2137
2138 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2139 if (!priv->fw_data) {
2140 ret = -ENOMEM;
2141 goto exit;
2142 }
2143 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2144
2145 signature = le16_to_cpu(priv->fw_data->signature);
2146 switch (signature & 0xfff0) {
2147 case 0x92e0:
2148 case 0x92c0:
2149 case 0x88e0:
2150 case 0x88c0:
2151 case 0x5300:
2152 case 0x2300:
2153 case 0x88f0:
2154 case 0x10b0:
2155 case 0x92f0:
2156 break;
2157 default:
2158 ret = -EINVAL;
2159 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2160 __func__, signature);
2161 }
2162
2163 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2164 le16_to_cpu(priv->fw_data->major_version),
2165 priv->fw_data->minor_version, signature);
2166
2167 exit:
2168 release_firmware(fw);
2169 return ret;
2170 }
2171
rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv * priv)2172 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2173 {
2174 u16 val16;
2175 int i = 100;
2176
2177 /* Inform 8051 to perform reset */
2178 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2179
2180 for (i = 100; i > 0; i--) {
2181 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2182
2183 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2184 dev_dbg(&priv->udev->dev,
2185 "%s: Firmware self reset success!\n", __func__);
2186 break;
2187 }
2188 udelay(50);
2189 }
2190
2191 if (!i) {
2192 /* Force firmware reset */
2193 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2194 val16 &= ~SYS_FUNC_CPU_ENABLE;
2195 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2196 }
2197 }
2198
2199 static int
rtl8xxxu_init_mac(struct rtl8xxxu_priv * priv)2200 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv)
2201 {
2202 const struct rtl8xxxu_reg8val *array = priv->fops->mactable;
2203 int i, ret;
2204 u16 reg;
2205 u8 val;
2206
2207 for (i = 0; ; i++) {
2208 reg = array[i].reg;
2209 val = array[i].val;
2210
2211 if (reg == 0xffff && val == 0xff)
2212 break;
2213
2214 ret = rtl8xxxu_write8(priv, reg, val);
2215 if (ret != 1) {
2216 dev_warn(&priv->udev->dev,
2217 "Failed to initialize MAC "
2218 "(reg: %04x, val %02x)\n", reg, val);
2219 return -EAGAIN;
2220 }
2221 }
2222
2223 switch (priv->rtl_chip) {
2224 case RTL8188C:
2225 case RTL8188R:
2226 case RTL8191C:
2227 case RTL8192C:
2228 case RTL8723A:
2229 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2230 break;
2231 case RTL8188E:
2232 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0707);
2233 break;
2234 default:
2235 break;
2236 }
2237
2238 return 0;
2239 }
2240
rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv * priv,const struct rtl8xxxu_reg32val * array)2241 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2242 const struct rtl8xxxu_reg32val *array)
2243 {
2244 int i, ret;
2245 u16 reg;
2246 u32 val;
2247
2248 for (i = 0; ; i++) {
2249 reg = array[i].reg;
2250 val = array[i].val;
2251
2252 if (reg == 0xffff && val == 0xffffffff)
2253 break;
2254
2255 ret = rtl8xxxu_write32(priv, reg, val);
2256 if (ret != sizeof(val)) {
2257 dev_warn(&priv->udev->dev,
2258 "Failed to initialize PHY\n");
2259 return -EAGAIN;
2260 }
2261 udelay(1);
2262 }
2263
2264 return 0;
2265 }
2266
rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv * priv)2267 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv)
2268 {
2269 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2270 u16 val16;
2271 u32 val32;
2272
2273 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2274 udelay(2);
2275 val8 |= AFE_PLL_320_ENABLE;
2276 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2277 udelay(2);
2278
2279 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2280 udelay(2);
2281
2282 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2283 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2284 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2285
2286 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2287 val32 &= ~AFE_XTAL_RF_GATE;
2288 if (priv->has_bluetooth)
2289 val32 &= ~AFE_XTAL_BT_GATE;
2290 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
2291
2292 /* 6. 0x1f[7:0] = 0x07 */
2293 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2294 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2295
2296 if (priv->hi_pa)
2297 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2298 else if (priv->tx_paths == 2)
2299 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
2300 else
2301 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2302
2303 if (priv->rtl_chip == RTL8188R && priv->hi_pa &&
2304 priv->vendor_umc && priv->chip_cut == 1)
2305 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
2306
2307 if (priv->hi_pa)
2308 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2309 else
2310 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
2311
2312 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2313 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2314 ldohci12 = 0x57;
2315 lpldo = 1;
2316 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2317 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
2318 }
2319
2320 /*
2321 * Most of this is black magic retrieved from the old rtl8723au driver
2322 */
rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv * priv)2323 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2324 {
2325 u32 val32;
2326
2327 priv->fops->init_phy_bb(priv);
2328
2329 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2330 /*
2331 * For 1T2R boards, patch the registers.
2332 *
2333 * It looks like 8191/2 1T2R boards use path B for TX
2334 */
2335 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2336 val32 &= ~(BIT(0) | BIT(1));
2337 val32 |= BIT(1);
2338 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2339
2340 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2341 val32 &= ~0x300033;
2342 val32 |= 0x200022;
2343 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2344
2345 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2346 val32 &= ~CCK0_AFE_RX_MASK;
2347 val32 &= 0x00ffffff;
2348 val32 |= 0x40000000;
2349 val32 |= CCK0_AFE_RX_ANT_B;
2350 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2351
2352 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2353 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2354 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2355 OFDM_RF_PATH_TX_B);
2356 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2357
2358 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2359 val32 &= ~(BIT(4) | BIT(5));
2360 val32 |= BIT(4);
2361 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2362
2363 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2364 val32 &= ~(BIT(27) | BIT(26));
2365 val32 |= BIT(27);
2366 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2367
2368 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2369 val32 &= ~(BIT(27) | BIT(26));
2370 val32 |= BIT(27);
2371 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2372
2373 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2374 val32 &= ~(BIT(27) | BIT(26));
2375 val32 |= BIT(27);
2376 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2377
2378 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2379 val32 &= ~(BIT(27) | BIT(26));
2380 val32 |= BIT(27);
2381 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2382
2383 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2384 val32 &= ~(BIT(27) | BIT(26));
2385 val32 |= BIT(27);
2386 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2387 }
2388
2389 if (priv->fops->set_crystal_cap)
2390 priv->fops->set_crystal_cap(priv, priv->default_crystal_cap);
2391
2392 if (priv->rtl_chip == RTL8192E)
2393 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb);
2394
2395 return 0;
2396 }
2397
rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv * priv,const struct rtl8xxxu_rfregval * array,enum rtl8xxxu_rfpath path)2398 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
2399 const struct rtl8xxxu_rfregval *array,
2400 enum rtl8xxxu_rfpath path)
2401 {
2402 int i, ret;
2403 u8 reg;
2404 u32 val;
2405
2406 for (i = 0; ; i++) {
2407 reg = array[i].reg;
2408 val = array[i].val;
2409
2410 if (reg == 0xff && val == 0xffffffff)
2411 break;
2412
2413 switch (reg) {
2414 case 0xfe:
2415 msleep(50);
2416 continue;
2417 case 0xfd:
2418 mdelay(5);
2419 continue;
2420 case 0xfc:
2421 mdelay(1);
2422 continue;
2423 case 0xfb:
2424 udelay(50);
2425 continue;
2426 case 0xfa:
2427 udelay(5);
2428 continue;
2429 case 0xf9:
2430 udelay(1);
2431 continue;
2432 }
2433
2434 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
2435 if (ret) {
2436 dev_warn(&priv->udev->dev,
2437 "Failed to initialize RF\n");
2438 return -EAGAIN;
2439 }
2440 udelay(1);
2441 }
2442
2443 return 0;
2444 }
2445
rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv * priv,const struct rtl8xxxu_rfregval * table,enum rtl8xxxu_rfpath path)2446 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
2447 const struct rtl8xxxu_rfregval *table,
2448 enum rtl8xxxu_rfpath path)
2449 {
2450 u32 val32;
2451 u16 val16, rfsi_rfenv;
2452 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
2453
2454 switch (path) {
2455 case RF_A:
2456 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
2457 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
2458 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
2459 break;
2460 case RF_B:
2461 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
2462 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
2463 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
2464 break;
2465 default:
2466 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
2467 __func__, path + 'A');
2468 return -EINVAL;
2469 }
2470 /* For path B, use XB */
2471 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
2472 rfsi_rfenv &= FPGA0_RF_RFENV;
2473
2474 /*
2475 * These two we might be able to optimize into one
2476 */
2477 val32 = rtl8xxxu_read32(priv, reg_int_oe);
2478 val32 |= BIT(20); /* 0x10 << 16 */
2479 rtl8xxxu_write32(priv, reg_int_oe, val32);
2480 udelay(1);
2481
2482 val32 = rtl8xxxu_read32(priv, reg_int_oe);
2483 val32 |= BIT(4);
2484 rtl8xxxu_write32(priv, reg_int_oe, val32);
2485 udelay(1);
2486
2487 /*
2488 * These two we might be able to optimize into one
2489 */
2490 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2491 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
2492 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2493 udelay(1);
2494
2495 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2496 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
2497 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2498 udelay(1);
2499
2500 rtl8xxxu_init_rf_regs(priv, table, path);
2501
2502 /* For path B, use XB */
2503 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
2504 val16 &= ~FPGA0_RF_RFENV;
2505 val16 |= rfsi_rfenv;
2506 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
2507
2508 return 0;
2509 }
2510
rtl8xxxu_llt_write(struct rtl8xxxu_priv * priv,u8 address,u8 data)2511 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
2512 {
2513 int ret = -EBUSY;
2514 int count = 0;
2515 u32 value;
2516
2517 value = LLT_OP_WRITE | address << 8 | data;
2518
2519 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
2520
2521 do {
2522 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
2523 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
2524 ret = 0;
2525 break;
2526 }
2527 } while (count++ < 20);
2528
2529 return ret;
2530 }
2531
rtl8xxxu_init_llt_table(struct rtl8xxxu_priv * priv)2532 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv)
2533 {
2534 int ret;
2535 int i, last_entry;
2536 u8 last_tx_page;
2537
2538 last_tx_page = priv->fops->total_page_num;
2539
2540 if (priv->fops->last_llt_entry)
2541 last_entry = priv->fops->last_llt_entry;
2542 else
2543 last_entry = 255;
2544
2545 for (i = 0; i < last_tx_page; i++) {
2546 ret = rtl8xxxu_llt_write(priv, i, i + 1);
2547 if (ret)
2548 goto exit;
2549 }
2550
2551 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
2552 if (ret)
2553 goto exit;
2554
2555 /* Mark remaining pages as a ring buffer */
2556 for (i = last_tx_page + 1; i < last_entry; i++) {
2557 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
2558 if (ret)
2559 goto exit;
2560 }
2561
2562 /* Let last entry point to the start entry of ring buffer */
2563 ret = rtl8xxxu_llt_write(priv, last_entry, last_tx_page + 1);
2564 if (ret)
2565 goto exit;
2566
2567 exit:
2568 return ret;
2569 }
2570
rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv * priv)2571 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv)
2572 {
2573 u32 val32;
2574 int ret = 0;
2575 int i;
2576
2577 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
2578 val32 |= AUTO_LLT_INIT_LLT;
2579 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
2580
2581 for (i = 500; i; i--) {
2582 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
2583 if (!(val32 & AUTO_LLT_INIT_LLT))
2584 break;
2585 usleep_range(2, 4);
2586 }
2587
2588 if (!i) {
2589 ret = -EBUSY;
2590 dev_warn(&priv->udev->dev, "LLT table init failed\n");
2591 }
2592
2593 return ret;
2594 }
2595
rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv * priv)2596 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
2597 {
2598 u16 val16, hi, lo;
2599 u16 hiq, mgq, bkq, beq, viq, voq;
2600 int hip, mgp, bkp, bep, vip, vop;
2601 int ret = 0;
2602 u32 val32;
2603
2604 switch (priv->ep_tx_count) {
2605 case 1:
2606 if (priv->ep_tx_high_queue) {
2607 hi = TRXDMA_QUEUE_HIGH;
2608 } else if (priv->ep_tx_low_queue) {
2609 hi = TRXDMA_QUEUE_LOW;
2610 } else if (priv->ep_tx_normal_queue) {
2611 hi = TRXDMA_QUEUE_NORMAL;
2612 } else {
2613 hi = 0;
2614 ret = -EINVAL;
2615 }
2616
2617 hiq = hi;
2618 mgq = hi;
2619 bkq = hi;
2620 beq = hi;
2621 viq = hi;
2622 voq = hi;
2623
2624 hip = 0;
2625 mgp = 0;
2626 bkp = 0;
2627 bep = 0;
2628 vip = 0;
2629 vop = 0;
2630 break;
2631 case 2:
2632 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
2633 hi = TRXDMA_QUEUE_HIGH;
2634 lo = TRXDMA_QUEUE_LOW;
2635 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
2636 hi = TRXDMA_QUEUE_NORMAL;
2637 lo = TRXDMA_QUEUE_LOW;
2638 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
2639 hi = TRXDMA_QUEUE_HIGH;
2640 lo = TRXDMA_QUEUE_NORMAL;
2641 } else {
2642 ret = -EINVAL;
2643 hi = 0;
2644 lo = 0;
2645 }
2646
2647 hiq = hi;
2648 mgq = hi;
2649 bkq = lo;
2650 beq = lo;
2651 viq = hi;
2652 voq = hi;
2653
2654 hip = 0;
2655 mgp = 0;
2656 bkp = 1;
2657 bep = 1;
2658 vip = 0;
2659 vop = 0;
2660 break;
2661 case 3:
2662 beq = TRXDMA_QUEUE_LOW;
2663 bkq = TRXDMA_QUEUE_LOW;
2664 viq = TRXDMA_QUEUE_NORMAL;
2665 voq = TRXDMA_QUEUE_HIGH;
2666 mgq = TRXDMA_QUEUE_HIGH;
2667 hiq = TRXDMA_QUEUE_HIGH;
2668
2669 hip = hiq ^ 3;
2670 mgp = mgq ^ 3;
2671 bkp = bkq ^ 3;
2672 bep = beq ^ 3;
2673 vip = viq ^ 3;
2674 vop = viq ^ 3;
2675 break;
2676 default:
2677 ret = -EINVAL;
2678 }
2679
2680 /*
2681 * None of the vendor drivers are configuring the beacon
2682 * queue here .... why?
2683 */
2684 if (!ret) {
2685 /* Only RTL8192F seems to do it like this. */
2686 if (priv->rtl_chip == RTL8192F) {
2687 val32 = rtl8xxxu_read32(priv, REG_TRXDMA_CTRL);
2688 val32 &= 0x7;
2689 val32 |= (voq << TRXDMA_CTRL_VOQ_SHIFT_8192F) |
2690 (viq << TRXDMA_CTRL_VIQ_SHIFT_8192F) |
2691 (beq << TRXDMA_CTRL_BEQ_SHIFT_8192F) |
2692 (bkq << TRXDMA_CTRL_BKQ_SHIFT_8192F) |
2693 (mgq << TRXDMA_CTRL_MGQ_SHIFT_8192F) |
2694 (hiq << TRXDMA_CTRL_HIQ_SHIFT_8192F);
2695 rtl8xxxu_write32(priv, REG_TRXDMA_CTRL, val32);
2696 } else {
2697 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
2698 val16 &= 0x7;
2699 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
2700 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
2701 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
2702 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
2703 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
2704 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
2705 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
2706 }
2707
2708 priv->pipe_out[TXDESC_QUEUE_VO] =
2709 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
2710 priv->pipe_out[TXDESC_QUEUE_VI] =
2711 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
2712 priv->pipe_out[TXDESC_QUEUE_BE] =
2713 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
2714 priv->pipe_out[TXDESC_QUEUE_BK] =
2715 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
2716 priv->pipe_out[TXDESC_QUEUE_BEACON] =
2717 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2718 priv->pipe_out[TXDESC_QUEUE_MGNT] =
2719 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
2720 priv->pipe_out[TXDESC_QUEUE_HIGH] =
2721 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
2722 priv->pipe_out[TXDESC_QUEUE_CMD] =
2723 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2724 }
2725
2726 return ret;
2727 }
2728
rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv * priv,bool iqk_ok,int result[][8],int candidate,bool tx_only)2729 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok,
2730 int result[][8], int candidate, bool tx_only)
2731 {
2732 u32 oldval, x, tx0_a, reg;
2733 int y, tx0_c;
2734 u32 val32;
2735
2736 if (!iqk_ok)
2737 return;
2738
2739 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2740 oldval = val32 >> 22;
2741
2742 x = result[candidate][0];
2743 if ((x & 0x00000200) != 0)
2744 x = x | 0xfffffc00;
2745 tx0_a = (x * oldval) >> 8;
2746
2747 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2748 val32 &= ~0x3ff;
2749 val32 |= tx0_a;
2750 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2751
2752 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2753 val32 &= ~BIT(31);
2754 if ((x * oldval >> 7) & 0x1)
2755 val32 |= BIT(31);
2756 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2757
2758 y = result[candidate][1];
2759 if ((y & 0x00000200) != 0)
2760 y = y | 0xfffffc00;
2761 tx0_c = (y * oldval) >> 8;
2762
2763 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
2764 val32 &= ~0xf0000000;
2765 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
2766 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
2767
2768 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2769 val32 &= ~0x003f0000;
2770 val32 |= ((tx0_c & 0x3f) << 16);
2771 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2772
2773 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2774 val32 &= ~BIT(29);
2775 if ((y * oldval >> 7) & 0x1)
2776 val32 |= BIT(29);
2777 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2778
2779 if (tx_only) {
2780 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2781 return;
2782 }
2783
2784 reg = result[candidate][2];
2785
2786 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2787 val32 &= ~0x3ff;
2788 val32 |= (reg & 0x3ff);
2789 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2790
2791 reg = result[candidate][3] & 0x3F;
2792
2793 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2794 val32 &= ~0xfc00;
2795 val32 |= ((reg << 10) & 0xfc00);
2796 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2797
2798 reg = (result[candidate][3] >> 6) & 0xF;
2799
2800 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
2801 val32 &= ~0xf0000000;
2802 val32 |= (reg << 28);
2803 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
2804 }
2805
rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv * priv,bool iqk_ok,int result[][8],int candidate,bool tx_only)2806 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok,
2807 int result[][8], int candidate, bool tx_only)
2808 {
2809 u32 oldval, x, tx1_a, reg;
2810 int y, tx1_c;
2811 u32 val32;
2812
2813 if (!iqk_ok)
2814 return;
2815
2816 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2817 oldval = val32 >> 22;
2818
2819 x = result[candidate][4];
2820 if ((x & 0x00000200) != 0)
2821 x = x | 0xfffffc00;
2822 tx1_a = (x * oldval) >> 8;
2823
2824 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2825 val32 &= ~0x3ff;
2826 val32 |= tx1_a;
2827 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2828
2829 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2830 val32 &= ~BIT(27);
2831 if ((x * oldval >> 7) & 0x1)
2832 val32 |= BIT(27);
2833 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2834
2835 y = result[candidate][5];
2836 if ((y & 0x00000200) != 0)
2837 y = y | 0xfffffc00;
2838 tx1_c = (y * oldval) >> 8;
2839
2840 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
2841 val32 &= ~0xf0000000;
2842 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
2843 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
2844
2845 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2846 val32 &= ~0x003f0000;
2847 val32 |= ((tx1_c & 0x3f) << 16);
2848 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2849
2850 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2851 val32 &= ~BIT(25);
2852 if ((y * oldval >> 7) & 0x1)
2853 val32 |= BIT(25);
2854 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2855
2856 if (tx_only) {
2857 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2858 return;
2859 }
2860
2861 reg = result[candidate][6];
2862
2863 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2864 val32 &= ~0x3ff;
2865 val32 |= (reg & 0x3ff);
2866 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2867
2868 reg = result[candidate][7] & 0x3f;
2869
2870 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2871 val32 &= ~0xfc00;
2872 val32 |= ((reg << 10) & 0xfc00);
2873 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2874
2875 reg = (result[candidate][7] >> 6) & 0xf;
2876
2877 if (priv->rtl_chip == RTL8192F) {
2878 rtl8xxxu_write32_mask(priv, REG_RXIQB_EXT, 0x000000f0, reg);
2879 } else {
2880 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_RSSI_TABLE);
2881 val32 &= ~0x0000f000;
2882 val32 |= (reg << 12);
2883 rtl8xxxu_write32(priv, REG_OFDM0_AGC_RSSI_TABLE, val32);
2884 }
2885 }
2886
2887 #define MAX_TOLERANCE 5
2888
rtl8xxxu_simularity_compare(struct rtl8xxxu_priv * priv,int result[][8],int c1,int c2)2889 bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
2890 int result[][8], int c1, int c2)
2891 {
2892 u32 i, j, diff, simubitmap, bound = 0;
2893 int candidate[2] = {-1, -1}; /* for path A and path B */
2894 bool retval = true;
2895
2896 if (priv->tx_paths > 1)
2897 bound = 8;
2898 else
2899 bound = 4;
2900
2901 simubitmap = 0;
2902
2903 for (i = 0; i < bound; i++) {
2904 diff = (result[c1][i] > result[c2][i]) ?
2905 (result[c1][i] - result[c2][i]) :
2906 (result[c2][i] - result[c1][i]);
2907 if (diff > MAX_TOLERANCE) {
2908 if ((i == 2 || i == 6) && !simubitmap) {
2909 if (result[c1][i] + result[c1][i + 1] == 0)
2910 candidate[(i / 4)] = c2;
2911 else if (result[c2][i] + result[c2][i + 1] == 0)
2912 candidate[(i / 4)] = c1;
2913 else
2914 simubitmap = simubitmap | (1 << i);
2915 } else {
2916 simubitmap = simubitmap | (1 << i);
2917 }
2918 }
2919 }
2920
2921 if (simubitmap == 0) {
2922 for (i = 0; i < (bound / 4); i++) {
2923 if (candidate[i] >= 0) {
2924 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2925 result[3][j] = result[candidate[i]][j];
2926 retval = false;
2927 }
2928 }
2929 return retval;
2930 } else if (!(simubitmap & 0x0f)) {
2931 /* path A OK */
2932 for (i = 0; i < 4; i++)
2933 result[3][i] = result[c1][i];
2934 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
2935 /* path B OK */
2936 for (i = 4; i < 8; i++)
2937 result[3][i] = result[c1][i];
2938 }
2939
2940 return false;
2941 }
2942
rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv * priv,int result[][8],int c1,int c2)2943 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv,
2944 int result[][8], int c1, int c2)
2945 {
2946 u32 i, j, diff, simubitmap, bound = 0;
2947 int candidate[2] = {-1, -1}; /* for path A and path B */
2948 int tmp1, tmp2;
2949 bool retval = true;
2950
2951 if (priv->tx_paths > 1)
2952 bound = 8;
2953 else
2954 bound = 4;
2955
2956 simubitmap = 0;
2957
2958 for (i = 0; i < bound; i++) {
2959 if (i & 1) {
2960 if ((result[c1][i] & 0x00000200))
2961 tmp1 = result[c1][i] | 0xfffffc00;
2962 else
2963 tmp1 = result[c1][i];
2964
2965 if ((result[c2][i]& 0x00000200))
2966 tmp2 = result[c2][i] | 0xfffffc00;
2967 else
2968 tmp2 = result[c2][i];
2969 } else {
2970 tmp1 = result[c1][i];
2971 tmp2 = result[c2][i];
2972 }
2973
2974 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
2975
2976 if (diff > MAX_TOLERANCE) {
2977 if ((i == 2 || i == 6) && !simubitmap) {
2978 if (result[c1][i] + result[c1][i + 1] == 0)
2979 candidate[(i / 4)] = c2;
2980 else if (result[c2][i] + result[c2][i + 1] == 0)
2981 candidate[(i / 4)] = c1;
2982 else
2983 simubitmap = simubitmap | (1 << i);
2984 } else {
2985 simubitmap = simubitmap | (1 << i);
2986 }
2987 }
2988 }
2989
2990 if (simubitmap == 0) {
2991 for (i = 0; i < (bound / 4); i++) {
2992 if (candidate[i] >= 0) {
2993 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2994 result[3][j] = result[candidate[i]][j];
2995 retval = false;
2996 }
2997 }
2998 return retval;
2999 } else {
3000 if (!(simubitmap & 0x03)) {
3001 /* path A TX OK */
3002 for (i = 0; i < 2; i++)
3003 result[3][i] = result[c1][i];
3004 }
3005
3006 if (!(simubitmap & 0x0c)) {
3007 /* path A RX OK */
3008 for (i = 2; i < 4; i++)
3009 result[3][i] = result[c1][i];
3010 }
3011
3012 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
3013 /* path B TX OK */
3014 for (i = 4; i < 6; i++)
3015 result[3][i] = result[c1][i];
3016 }
3017
3018 if (!(simubitmap & 0xc0) && priv->tx_paths > 1) {
3019 /* path B RX OK */
3020 for (i = 6; i < 8; i++)
3021 result[3][i] = result[c1][i];
3022 }
3023 }
3024
3025 return false;
3026 }
3027
3028 void
rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv * priv,const u32 * reg,u32 * backup)3029 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
3030 {
3031 int i;
3032
3033 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3034 backup[i] = rtl8xxxu_read8(priv, reg[i]);
3035
3036 backup[i] = rtl8xxxu_read32(priv, reg[i]);
3037 }
3038
rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv * priv,const u32 * reg,u32 * backup)3039 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
3040 const u32 *reg, u32 *backup)
3041 {
3042 int i;
3043
3044 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3045 rtl8xxxu_write8(priv, reg[i], backup[i]);
3046
3047 rtl8xxxu_write32(priv, reg[i], backup[i]);
3048 }
3049
rtl8xxxu_save_regs(struct rtl8xxxu_priv * priv,const u32 * regs,u32 * backup,int count)3050 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3051 u32 *backup, int count)
3052 {
3053 int i;
3054
3055 for (i = 0; i < count; i++)
3056 backup[i] = rtl8xxxu_read32(priv, regs[i]);
3057 }
3058
rtl8xxxu_restore_regs(struct rtl8xxxu_priv * priv,const u32 * regs,u32 * backup,int count)3059 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3060 u32 *backup, int count)
3061 {
3062 int i;
3063
3064 for (i = 0; i < count; i++)
3065 rtl8xxxu_write32(priv, regs[i], backup[i]);
3066 }
3067
3068
rtl8xxxu_path_adda_on(struct rtl8xxxu_priv * priv,const u32 * regs,bool path_a_on)3069 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3070 bool path_a_on)
3071 {
3072 u32 path_on;
3073 int i;
3074
3075 if (priv->tx_paths == 1) {
3076 path_on = priv->fops->adda_1t_path_on;
3077 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
3078 } else {
3079 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
3080 priv->fops->adda_2t_path_on_b;
3081
3082 rtl8xxxu_write32(priv, regs[0], path_on);
3083 }
3084
3085 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3086 rtl8xxxu_write32(priv, regs[i], path_on);
3087 }
3088
rtl8xxxu_mac_calibration(struct rtl8xxxu_priv * priv,const u32 * regs,u32 * backup)3089 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3090 const u32 *regs, u32 *backup)
3091 {
3092 int i = 0;
3093
3094 rtl8xxxu_write8(priv, regs[i], 0x3f);
3095
3096 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3097 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3098
3099 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3100 }
3101
rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv * priv)3102 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3103 {
3104 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3105 int result = 0;
3106
3107 /* path-A IQK setting */
3108 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3109 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3110 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3111
3112 val32 = (priv->rf_paths > 1) ? 0x28160202 :
3113 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3114 0x28160502;
3115 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3116
3117 /* path-B IQK setting */
3118 if (priv->rf_paths > 1) {
3119 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3120 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3121 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3122 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3123 }
3124
3125 /* LO calibration setting */
3126 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3127
3128 /* One shot, path A LOK & IQK */
3129 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3130 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3131
3132 mdelay(1);
3133
3134 /* Check failed */
3135 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3136 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3137 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3138 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3139
3140 if (!(reg_eac & BIT(28)) &&
3141 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3142 ((reg_e9c & 0x03ff0000) != 0x00420000))
3143 result |= 0x01;
3144 else /* If TX not OK, ignore RX */
3145 goto out;
3146
3147 /* If TX is OK, check whether RX is OK */
3148 if (!(reg_eac & BIT(27)) &&
3149 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3150 ((reg_eac & 0x03ff0000) != 0x00360000))
3151 result |= 0x02;
3152 else
3153 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3154 __func__);
3155 out:
3156 return result;
3157 }
3158
rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv * priv)3159 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3160 {
3161 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3162 int result = 0;
3163
3164 /* One shot, path B LOK & IQK */
3165 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3166 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3167
3168 mdelay(1);
3169
3170 /* Check failed */
3171 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3172 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3173 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3174 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3175 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3176
3177 if (!(reg_eac & BIT(31)) &&
3178 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3179 ((reg_ebc & 0x03ff0000) != 0x00420000))
3180 result |= 0x01;
3181 else
3182 goto out;
3183
3184 if (!(reg_eac & BIT(30)) &&
3185 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3186 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3187 result |= 0x02;
3188 else
3189 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3190 __func__);
3191 out:
3192 return result;
3193 }
3194
rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv * priv,int result[][8],int t)3195 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
3196 int result[][8], int t)
3197 {
3198 struct device *dev = &priv->udev->dev;
3199 u32 i, val32;
3200 int path_a_ok, path_b_ok;
3201 int retry = 2;
3202 static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
3203 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
3204 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
3205 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
3206 REG_TX_OFDM_BBON, REG_TX_TO_RX,
3207 REG_TX_TO_TX, REG_RX_CCK,
3208 REG_RX_OFDM, REG_RX_WAIT_RIFS,
3209 REG_RX_TO_RX, REG_STANDBY,
3210 REG_SLEEP, REG_PMPD_ANAEN
3211 };
3212 static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
3213 REG_TXPAUSE, REG_BEACON_CTRL,
3214 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
3215 };
3216 static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
3217 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
3218 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
3219 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
3220 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
3221 };
3222
3223 /*
3224 * Note: IQ calibration must be performed after loading
3225 * PHY_REG.txt , and radio_a, radio_b.txt
3226 */
3227
3228 if (t == 0) {
3229 /* Save ADDA parameters, turn Path A ADDA on */
3230 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
3231 RTL8XXXU_ADDA_REGS);
3232 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3233 rtl8xxxu_save_regs(priv, iqk_bb_regs,
3234 priv->bb_backup, RTL8XXXU_BB_REGS);
3235 }
3236
3237 rtl8xxxu_path_adda_on(priv, adda_regs, true);
3238
3239 if (t == 0) {
3240 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3241 if (val32 & FPGA0_HSSI_PARM1_PI)
3242 priv->pi_enabled = 1;
3243 }
3244
3245 if (!priv->pi_enabled) {
3246 /* Switch BB to PI mode to do IQ Calibration. */
3247 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
3248 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
3249 }
3250
3251 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3252 val32 &= ~FPGA_RF_MODE_CCK;
3253 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
3254
3255 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
3256 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
3257 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
3258
3259 if (!priv->no_pape) {
3260 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3261 val32 |= (FPGA0_RF_PAPE |
3262 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3263 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3264 }
3265
3266 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3267 val32 &= ~BIT(10);
3268 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
3269 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3270 val32 &= ~BIT(10);
3271 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
3272
3273 if (priv->tx_paths > 1) {
3274 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3275 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
3276 }
3277
3278 /* MAC settings */
3279 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
3280
3281 /* Page B init */
3282 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
3283
3284 if (priv->tx_paths > 1)
3285 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
3286
3287 /* IQ calibration setting */
3288 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3289 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3290 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3291
3292 for (i = 0; i < retry; i++) {
3293 path_a_ok = rtl8xxxu_iqk_path_a(priv);
3294 if (path_a_ok == 0x03) {
3295 val32 = rtl8xxxu_read32(priv,
3296 REG_TX_POWER_BEFORE_IQK_A);
3297 result[t][0] = (val32 >> 16) & 0x3ff;
3298 val32 = rtl8xxxu_read32(priv,
3299 REG_TX_POWER_AFTER_IQK_A);
3300 result[t][1] = (val32 >> 16) & 0x3ff;
3301 val32 = rtl8xxxu_read32(priv,
3302 REG_RX_POWER_BEFORE_IQK_A_2);
3303 result[t][2] = (val32 >> 16) & 0x3ff;
3304 val32 = rtl8xxxu_read32(priv,
3305 REG_RX_POWER_AFTER_IQK_A_2);
3306 result[t][3] = (val32 >> 16) & 0x3ff;
3307 break;
3308 } else if (i == (retry - 1) && path_a_ok == 0x01) {
3309 /* TX IQK OK */
3310 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
3311 __func__);
3312
3313 val32 = rtl8xxxu_read32(priv,
3314 REG_TX_POWER_BEFORE_IQK_A);
3315 result[t][0] = (val32 >> 16) & 0x3ff;
3316 val32 = rtl8xxxu_read32(priv,
3317 REG_TX_POWER_AFTER_IQK_A);
3318 result[t][1] = (val32 >> 16) & 0x3ff;
3319 }
3320 }
3321
3322 if (!path_a_ok)
3323 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
3324
3325 if (priv->tx_paths > 1) {
3326 /*
3327 * Path A into standby
3328 */
3329 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
3330 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3331 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3332
3333 /* Turn Path B ADDA on */
3334 rtl8xxxu_path_adda_on(priv, adda_regs, false);
3335
3336 for (i = 0; i < retry; i++) {
3337 path_b_ok = rtl8xxxu_iqk_path_b(priv);
3338 if (path_b_ok == 0x03) {
3339 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3340 result[t][4] = (val32 >> 16) & 0x3ff;
3341 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3342 result[t][5] = (val32 >> 16) & 0x3ff;
3343 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3344 result[t][6] = (val32 >> 16) & 0x3ff;
3345 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3346 result[t][7] = (val32 >> 16) & 0x3ff;
3347 break;
3348 } else if (i == (retry - 1) && path_b_ok == 0x01) {
3349 /* TX IQK OK */
3350 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3351 result[t][4] = (val32 >> 16) & 0x3ff;
3352 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3353 result[t][5] = (val32 >> 16) & 0x3ff;
3354 }
3355 }
3356
3357 if (!path_b_ok)
3358 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
3359 }
3360
3361 /* Back to BB mode, load original value */
3362 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
3363
3364 if (t) {
3365 if (!priv->pi_enabled) {
3366 /*
3367 * Switch back BB to SI mode after finishing
3368 * IQ Calibration
3369 */
3370 val32 = 0x01000000;
3371 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
3372 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
3373 }
3374
3375 /* Reload ADDA power saving parameters */
3376 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
3377 RTL8XXXU_ADDA_REGS);
3378
3379 /* Reload MAC parameters */
3380 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3381
3382 /* Reload BB parameters */
3383 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
3384 priv->bb_backup, RTL8XXXU_BB_REGS);
3385
3386 /* Restore RX initial gain */
3387 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
3388
3389 if (priv->tx_paths > 1) {
3390 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
3391 0x00032ed3);
3392 }
3393
3394 /* Load 0xe30 IQC default value */
3395 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
3396 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
3397 }
3398 }
3399
rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv * priv,u8 start)3400 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
3401 {
3402 struct h2c_cmd h2c;
3403
3404 memset(&h2c, 0, sizeof(struct h2c_cmd));
3405 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
3406 h2c.bt_wlan_calibration.data = start;
3407
3408 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
3409 }
3410
rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv * priv)3411 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
3412 {
3413 struct device *dev = &priv->udev->dev;
3414 int result[4][8]; /* last is final result */
3415 int i, candidate;
3416 bool path_a_ok, path_b_ok;
3417 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
3418 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3419 s32 reg_tmp = 0;
3420 bool simu;
3421
3422 memset(result, 0, sizeof(result));
3423 candidate = -1;
3424
3425 path_a_ok = false;
3426 path_b_ok = false;
3427
3428 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3429
3430 for (i = 0; i < 3; i++) {
3431 rtl8xxxu_phy_iqcalibrate(priv, result, i);
3432
3433 if (i == 1) {
3434 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
3435 if (simu) {
3436 candidate = 0;
3437 break;
3438 }
3439 }
3440
3441 if (i == 2) {
3442 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
3443 if (simu) {
3444 candidate = 0;
3445 break;
3446 }
3447
3448 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
3449 if (simu) {
3450 candidate = 1;
3451 } else {
3452 for (i = 0; i < 8; i++)
3453 reg_tmp += result[3][i];
3454
3455 if (reg_tmp)
3456 candidate = 3;
3457 else
3458 candidate = -1;
3459 }
3460 }
3461 }
3462
3463 for (i = 0; i < 4; i++) {
3464 reg_e94 = result[i][0];
3465 reg_e9c = result[i][1];
3466 reg_ea4 = result[i][2];
3467 reg_eac = result[i][3];
3468 reg_eb4 = result[i][4];
3469 reg_ebc = result[i][5];
3470 reg_ec4 = result[i][6];
3471 reg_ecc = result[i][7];
3472 }
3473
3474 if (candidate >= 0) {
3475 reg_e94 = result[candidate][0];
3476 priv->rege94 = reg_e94;
3477 reg_e9c = result[candidate][1];
3478 priv->rege9c = reg_e9c;
3479 reg_ea4 = result[candidate][2];
3480 reg_eac = result[candidate][3];
3481 reg_eb4 = result[candidate][4];
3482 priv->regeb4 = reg_eb4;
3483 reg_ebc = result[candidate][5];
3484 priv->regebc = reg_ebc;
3485 reg_ec4 = result[candidate][6];
3486 reg_ecc = result[candidate][7];
3487 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
3488 dev_dbg(dev,
3489 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n",
3490 __func__, reg_e94, reg_e9c,
3491 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
3492 path_a_ok = true;
3493 path_b_ok = true;
3494 } else {
3495 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
3496 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
3497 }
3498
3499 if (reg_e94 && candidate >= 0)
3500 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
3501 candidate, (reg_ea4 == 0));
3502
3503 if (priv->tx_paths > 1 && reg_eb4)
3504 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
3505 candidate, (reg_ec4 == 0));
3506
3507 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
3508 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
3509 }
3510
rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv * priv)3511 void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
3512 {
3513 u32 val32;
3514 u32 rf_amode, rf_bmode = 0, lstf;
3515
3516 /* Check continuous TX and Packet TX */
3517 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3518
3519 if (lstf & OFDM_LSTF_MASK) {
3520 /* Disable all continuous TX */
3521 val32 = lstf & ~OFDM_LSTF_MASK;
3522 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
3523
3524 /* Read original RF mode Path A */
3525 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
3526
3527 /* Set RF mode to standby Path A */
3528 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
3529 (rf_amode & 0x8ffff) | 0x10000);
3530
3531 /* Path-B */
3532 if (priv->tx_paths > 1) {
3533 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
3534 RF6052_REG_AC);
3535
3536 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3537 (rf_bmode & 0x8ffff) | 0x10000);
3538 }
3539 } else {
3540 /* Deal with Packet TX case */
3541 /* block all queues */
3542 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3543 }
3544
3545 /* Start LC calibration */
3546 if (priv->fops->has_s0s1)
3547 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
3548 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
3549 val32 |= 0x08000;
3550 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
3551
3552 msleep(100);
3553
3554 if (priv->fops->has_s0s1)
3555 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
3556
3557 /* Restore original parameters */
3558 if (lstf & OFDM_LSTF_MASK) {
3559 /* Path-A */
3560 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
3561 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
3562
3563 /* Path-B */
3564 if (priv->tx_paths > 1)
3565 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3566 rf_bmode);
3567 } else /* Deal with Packet TX case */
3568 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
3569 }
3570
rtl8xxxu_set_mac(struct rtl8xxxu_priv * priv)3571 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
3572 {
3573 int i;
3574 u16 reg;
3575
3576 reg = REG_MACID;
3577
3578 for (i = 0; i < ETH_ALEN; i++)
3579 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
3580
3581 return 0;
3582 }
3583
rtl8xxxu_set_bssid(struct rtl8xxxu_priv * priv,const u8 * bssid)3584 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
3585 {
3586 int i;
3587 u16 reg;
3588
3589 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
3590
3591 reg = REG_BSSID;
3592
3593 for (i = 0; i < ETH_ALEN; i++)
3594 rtl8xxxu_write8(priv, reg + i, bssid[i]);
3595
3596 return 0;
3597 }
3598
3599 static void
rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv * priv,u8 ampdu_factor)3600 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
3601 {
3602 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
3603 u8 max_agg = 0xf;
3604 int i;
3605
3606 ampdu_factor = 1 << (ampdu_factor + 2);
3607 if (ampdu_factor > max_agg)
3608 ampdu_factor = max_agg;
3609
3610 for (i = 0; i < 4; i++) {
3611 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
3612 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
3613
3614 if ((vals[i] & 0x0f) > ampdu_factor)
3615 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
3616
3617 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
3618 }
3619 }
3620
rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv * priv,u8 density)3621 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
3622 {
3623 u8 val8;
3624
3625 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
3626 val8 &= 0xf8;
3627 val8 |= density;
3628 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
3629 }
3630
rtl8xxxu_active_to_emu(struct rtl8xxxu_priv * priv)3631 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
3632 {
3633 u8 val8;
3634 int count, ret = 0;
3635
3636 /* Start of rtl8723AU_card_enable_flow */
3637 /* Act to Cardemu sequence*/
3638 /* Turn off RF */
3639 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
3640
3641 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
3642 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3643 val8 &= ~LEDCFG2_DPDT_SELECT;
3644 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3645
3646 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
3647 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3648 val8 |= BIT(1);
3649 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3650
3651 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3652 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3653 if ((val8 & BIT(1)) == 0)
3654 break;
3655 udelay(10);
3656 }
3657
3658 if (!count) {
3659 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
3660 __func__);
3661 ret = -EBUSY;
3662 goto exit;
3663 }
3664
3665 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
3666 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3667 val8 |= SYS_ISO_ANALOG_IPS;
3668 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3669
3670 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
3671 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3672 val8 &= ~LDOA15_ENABLE;
3673 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3674
3675 exit:
3676 return ret;
3677 }
3678
rtl8xxxu_active_to_lps(struct rtl8xxxu_priv * priv)3679 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
3680 {
3681 u8 val8;
3682 u8 val32;
3683 int count, ret = 0;
3684
3685 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3686
3687 /*
3688 * Poll - wait for RX packet to complete
3689 */
3690 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3691 val32 = rtl8xxxu_read32(priv, 0x5f8);
3692 if (!val32)
3693 break;
3694 udelay(10);
3695 }
3696
3697 if (!count) {
3698 dev_warn(&priv->udev->dev,
3699 "%s: RX poll timed out (0x05f8)\n", __func__);
3700 ret = -EBUSY;
3701 goto exit;
3702 }
3703
3704 /* Disable CCK and OFDM, clock gated */
3705 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3706 val8 &= ~SYS_FUNC_BBRSTB;
3707 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3708
3709 udelay(2);
3710
3711 /* Reset baseband */
3712 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3713 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
3714 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3715
3716 /* Reset MAC TRX */
3717 val8 = rtl8xxxu_read8(priv, REG_CR);
3718 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
3719 rtl8xxxu_write8(priv, REG_CR, val8);
3720
3721 /* Reset MAC TRX */
3722 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
3723 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
3724 rtl8xxxu_write8(priv, REG_CR + 1, val8);
3725
3726 /* Respond TX OK to scheduler */
3727 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
3728 val8 |= DUAL_TSF_TX_OK;
3729 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
3730
3731 exit:
3732 return ret;
3733 }
3734
rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv * priv)3735 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv)
3736 {
3737 u8 val8;
3738
3739 /* Clear suspend enable and power down enable*/
3740 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3741 val8 &= ~(BIT(3) | BIT(7));
3742 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3743
3744 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
3745 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3746 val8 &= ~BIT(0);
3747 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3748
3749 /* 0x04[12:11] = 11 enable WL suspend*/
3750 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3751 val8 &= ~(BIT(3) | BIT(4));
3752 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3753 }
3754
rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv * priv)3755 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
3756 {
3757 u8 val8;
3758
3759 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
3760 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
3761
3762 /* 0x04[12:11] = 01 enable WL suspend */
3763 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3764 val8 &= ~BIT(4);
3765 val8 |= BIT(3);
3766 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3767
3768 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3769 val8 |= BIT(7);
3770 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3771
3772 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
3773 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3774 val8 |= BIT(0);
3775 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3776
3777 return 0;
3778 }
3779
rtl8xxxu_flush_fifo(struct rtl8xxxu_priv * priv)3780 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv)
3781 {
3782 struct device *dev = &priv->udev->dev;
3783 u32 val32;
3784 int retry, retval;
3785
3786 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3787
3788 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
3789 val32 |= RXPKT_NUM_RW_RELEASE_EN;
3790 rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32);
3791
3792 retry = 100;
3793 retval = -EBUSY;
3794
3795 do {
3796 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
3797 if (val32 & RXPKT_NUM_RXDMA_IDLE) {
3798 retval = 0;
3799 break;
3800 }
3801 } while (retry--);
3802
3803 rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0);
3804 rtl8xxxu_write32(priv, REG_RQPN, 0x80000000);
3805 mdelay(2);
3806
3807 if (!retry)
3808 dev_warn(dev, "Failed to flush FIFO\n");
3809
3810 return retval;
3811 }
3812
rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv * priv)3813 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv)
3814 {
3815 /* Fix USB interface interference issue */
3816 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
3817 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
3818 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3819 /*
3820 * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits
3821 * 8 and 5, for which I have found no documentation.
3822 */
3823 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
3824
3825 /*
3826 * Solve too many protocol error on USB bus.
3827 * Can't do this for 8188/8192 UMC A cut parts
3828 */
3829 if (!(!priv->chip_cut && priv->vendor_umc)) {
3830 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
3831 rtl8xxxu_write8(priv, 0xfe41, 0x94);
3832 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3833
3834 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
3835 rtl8xxxu_write8(priv, 0xfe41, 0x19);
3836 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3837
3838 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
3839 rtl8xxxu_write8(priv, 0xfe41, 0x91);
3840 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3841
3842 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
3843 rtl8xxxu_write8(priv, 0xfe41, 0x81);
3844 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3845 }
3846 }
3847
rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv * priv)3848 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv)
3849 {
3850 u32 val32;
3851
3852 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
3853 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
3854 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
3855 }
3856
rtl8xxxu_power_off(struct rtl8xxxu_priv * priv)3857 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
3858 {
3859 u8 val8;
3860 u16 val16;
3861 u32 val32;
3862
3863 /*
3864 * Workaround for 8188RU LNA power leakage problem.
3865 */
3866 if (priv->rtl_chip == RTL8188R) {
3867 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3868 val32 |= BIT(1);
3869 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3870 }
3871
3872 rtl8xxxu_flush_fifo(priv);
3873
3874 rtl8xxxu_active_to_lps(priv);
3875
3876 /* Turn off RF */
3877 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
3878
3879 /* Reset Firmware if running in RAM */
3880 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
3881 rtl8xxxu_firmware_self_reset(priv);
3882
3883 /* Reset MCU */
3884 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3885 val16 &= ~SYS_FUNC_CPU_ENABLE;
3886 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3887
3888 /* Reset MCU ready status */
3889 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
3890
3891 rtl8xxxu_active_to_emu(priv);
3892 rtl8xxxu_emu_to_disabled(priv);
3893
3894 /* Reset MCU IO Wrapper */
3895 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3896 val8 &= ~BIT(0);
3897 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3898
3899 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3900 val8 |= BIT(0);
3901 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3902
3903 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
3904 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
3905 }
3906
rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv * priv,u8 arg1,u8 arg2,u8 arg3,u8 arg4,u8 arg5)3907 void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
3908 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)
3909 {
3910 struct h2c_cmd h2c;
3911
3912 memset(&h2c, 0, sizeof(struct h2c_cmd));
3913 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;
3914 h2c.b_type_dma.data1 = arg1;
3915 h2c.b_type_dma.data2 = arg2;
3916 h2c.b_type_dma.data3 = arg3;
3917 h2c.b_type_dma.data4 = arg4;
3918 h2c.b_type_dma.data5 = arg5;
3919 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));
3920 }
3921
rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv * priv)3922 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv)
3923 {
3924 u32 val32;
3925
3926 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
3927 val32 &= ~(BIT(22) | BIT(23));
3928 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
3929 }
3930
rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv * priv)3931 static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv)
3932 {
3933 struct rtl8xxxu_fileops *fops = priv->fops;
3934 u32 hq, lq, nq, eq, pubq;
3935 u32 val32;
3936
3937 hq = 0;
3938 lq = 0;
3939 nq = 0;
3940 eq = 0;
3941 pubq = 0;
3942
3943 if (priv->ep_tx_high_queue)
3944 hq = fops->page_num_hi;
3945 if (priv->ep_tx_low_queue)
3946 lq = fops->page_num_lo;
3947 if (priv->ep_tx_normal_queue)
3948 nq = fops->page_num_norm;
3949
3950 val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT);
3951 rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32);
3952
3953 pubq = fops->total_page_num - hq - lq - nq - 1;
3954
3955 val32 = RQPN_LOAD;
3956 val32 |= (hq << RQPN_HI_PQ_SHIFT);
3957 val32 |= (lq << RQPN_LO_PQ_SHIFT);
3958 val32 |= (pubq << RQPN_PUB_PQ_SHIFT);
3959
3960 rtl8xxxu_write32(priv, REG_RQPN, val32);
3961 }
3962
rtl8xxxu_init_burst(struct rtl8xxxu_priv * priv)3963 void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv)
3964 {
3965 u8 val8;
3966
3967 /*
3968 * For USB high speed set 512B packets
3969 */
3970 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);
3971 u8p_replace_bits(&val8, 1, RXDMA_PRO_DMA_BURST_SIZE);
3972 u8p_replace_bits(&val8, 3, RXDMA_PRO_DMA_BURST_CNT);
3973 val8 |= RXDMA_PRO_DMA_MODE;
3974 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8);
3975
3976 /*
3977 * Enable single packet AMPDU
3978 */
3979 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B);
3980 val8 |= HT_SINGLE_AMPDU_ENABLE;
3981 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
3982
3983 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, priv->fops->max_aggr_num);
3984 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B,
3985 priv->fops->ampdu_max_time);
3986 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
3987 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
3988 rtl8xxxu_write8(priv, REG_PIFS, 0x00);
3989 if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8710B ||
3990 priv->rtl_chip == RTL8192F) {
3991 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, FWHW_TXQ_CTRL_AMPDU_RETRY);
3992 rtl8xxxu_write32(priv, REG_FAST_EDCA_CTRL, 0x03086666);
3993 }
3994 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, priv->fops->ustime_tsf_edca);
3995 rtl8xxxu_write8(priv, REG_USTIME_EDCA, priv->fops->ustime_tsf_edca);
3996
3997 /* to prevent mac is reseted by bus. */
3998 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
3999 val8 |= RSV_CTRL_WLOCK_1C | RSV_CTRL_DIS_PRST;
4000 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
4001 }
4002
rtl8xxxu_acquire_macid(struct rtl8xxxu_priv * priv)4003 static u8 rtl8xxxu_acquire_macid(struct rtl8xxxu_priv *priv)
4004 {
4005 u8 macid;
4006
4007 macid = find_first_zero_bit(priv->mac_id_map, RTL8XXXU_MAX_MAC_ID_NUM);
4008 if (macid < RTL8XXXU_MAX_MAC_ID_NUM)
4009 set_bit(macid, priv->mac_id_map);
4010
4011 return macid;
4012 }
4013
rtl8xxxu_release_macid(struct rtl8xxxu_priv * priv,u8 macid)4014 static void rtl8xxxu_release_macid(struct rtl8xxxu_priv *priv, u8 macid)
4015 {
4016 clear_bit(macid, priv->mac_id_map);
4017 }
4018
rtl8xxxu_get_macid(struct rtl8xxxu_priv * priv,struct ieee80211_sta * sta)4019 static inline u8 rtl8xxxu_get_macid(struct rtl8xxxu_priv *priv,
4020 struct ieee80211_sta *sta)
4021 {
4022 struct rtl8xxxu_sta_info *sta_info;
4023
4024 if (!priv->vif || priv->vif->type == NL80211_IFTYPE_STATION || !sta)
4025 return 0;
4026
4027 sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;
4028 return sta_info->macid;
4029 }
4030
rtl8xxxu_init_device(struct ieee80211_hw * hw)4031 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
4032 {
4033 struct rtl8xxxu_priv *priv = hw->priv;
4034 struct device *dev = &priv->udev->dev;
4035 struct rtl8xxxu_fileops *fops = priv->fops;
4036 bool macpower;
4037 int ret;
4038 u8 val8;
4039 u16 val16;
4040 u32 val32;
4041
4042 /* Check if MAC is already powered on */
4043 val8 = rtl8xxxu_read8(priv, REG_CR);
4044 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
4045
4046 /*
4047 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
4048 * initialized. First MAC returns 0xea, second MAC returns 0x00
4049 */
4050 if (val8 == 0xea || !(val16 & SYS_CLK_MAC_CLK_ENABLE))
4051 macpower = false;
4052 else
4053 macpower = true;
4054
4055 if (fops->needs_full_init)
4056 macpower = false;
4057
4058 ret = fops->power_on(priv);
4059 if (ret < 0) {
4060 dev_warn(dev, "%s: Failed power on\n", __func__);
4061 goto exit;
4062 }
4063
4064 if (!macpower)
4065 rtl8xxxu_init_queue_reserved_page(priv);
4066
4067 ret = rtl8xxxu_init_queue_priority(priv);
4068 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
4069 if (ret)
4070 goto exit;
4071
4072 /*
4073 * Set RX page boundary
4074 */
4075 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, fops->trxff_boundary);
4076
4077 for (int retry = 5; retry >= 0 ; retry--) {
4078 ret = rtl8xxxu_download_firmware(priv);
4079 dev_dbg(dev, "%s: download_firmware %i\n", __func__, ret);
4080 if (ret != -EAGAIN)
4081 break;
4082 if (retry)
4083 dev_dbg(dev, "%s: retry firmware download\n", __func__);
4084 }
4085 if (ret)
4086 goto exit;
4087 ret = rtl8xxxu_start_firmware(priv);
4088 dev_dbg(dev, "%s: start_firmware %i\n", __func__, ret);
4089 if (ret)
4090 goto exit;
4091
4092 if (fops->phy_init_antenna_selection)
4093 fops->phy_init_antenna_selection(priv);
4094
4095 ret = rtl8xxxu_init_mac(priv);
4096
4097 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
4098 if (ret)
4099 goto exit;
4100
4101 ret = rtl8xxxu_init_phy_bb(priv);
4102 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
4103 if (ret)
4104 goto exit;
4105
4106 ret = fops->init_phy_rf(priv);
4107 if (ret)
4108 goto exit;
4109
4110 /* Mac APLL Setting */
4111 if (priv->rtl_chip == RTL8192F)
4112 rtl8xxxu_write16_set(priv, REG_AFE_CTRL4, BIT(4) | BIT(15));
4113
4114 /* RFSW Control - clear bit 14 ?? */
4115 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E &&
4116 priv->rtl_chip != RTL8188E && priv->rtl_chip != RTL8710B &&
4117 priv->rtl_chip != RTL8192F)
4118 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
4119
4120 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
4121 FPGA0_RF_ANTSWB |
4122 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB) << FPGA0_RF_BD_CTRL_SHIFT);
4123 if (!priv->no_pape) {
4124 val32 |= (FPGA0_RF_PAPE |
4125 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
4126 }
4127 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4128
4129 /* 0x860[6:5]= 00 - why? - this sets antenna B */
4130 if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188E &&
4131 priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192F)
4132 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210);
4133
4134 if (!macpower) {
4135 /*
4136 * Set TX buffer boundary
4137 */
4138 val8 = fops->total_page_num + 1;
4139
4140 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
4141 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
4142 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
4143 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
4144 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
4145 }
4146
4147 /*
4148 * The vendor drivers set PBP for all devices, except 8192e.
4149 * There is no explanation for this in any of the sources.
4150 */
4151 val8 = (fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) |
4152 (fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT);
4153 if (priv->rtl_chip != RTL8192E)
4154 rtl8xxxu_write8(priv, REG_PBP, val8);
4155
4156 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4157 if (!macpower) {
4158 ret = fops->llt_init(priv);
4159 if (ret) {
4160 dev_warn(dev, "%s: LLT table init failed\n", __func__);
4161 goto exit;
4162 }
4163
4164 /*
4165 * Chip specific quirks
4166 */
4167 fops->usb_quirks(priv);
4168
4169 /*
4170 * Enable TX report and TX report timer for 8723bu/8188eu/...
4171 */
4172 if (fops->has_tx_report) {
4173 /*
4174 * The RTL8188EU has two types of TX reports:
4175 * rpt_sel=1:
4176 * One report for one frame. We can use this for frames
4177 * with IEEE80211_TX_CTL_REQ_TX_STATUS.
4178 * rpt_sel=2:
4179 * One report for many frames transmitted over a period
4180 * of time. (This is what REG_TX_REPORT_TIME is for.) The
4181 * report includes the number of frames transmitted
4182 * successfully, and the number of unsuccessful
4183 * transmissions. We use this for software rate control.
4184 *
4185 * Bit 0 of REG_TX_REPORT_CTRL is required for both types.
4186 * Bit 1 (TX_REPORT_CTRL_TIMER_ENABLE) is required for
4187 * type 2.
4188 */
4189 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
4190 if (priv->rtl_chip == RTL8188E)
4191 val8 |= BIT(0);
4192 val8 |= TX_REPORT_CTRL_TIMER_ENABLE;
4193 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
4194 /* Set MAX RPT MACID */
4195 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02);
4196 /* TX report Timer. Unit: 32us */
4197 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0);
4198
4199 /* tmp ps ? */
4200 val8 = rtl8xxxu_read8(priv, 0xa3);
4201 val8 &= 0xf8;
4202 rtl8xxxu_write8(priv, 0xa3, val8);
4203 }
4204
4205 if (priv->rtl_chip == RTL8710B || priv->rtl_chip == RTL8192F)
4206 rtl8xxxu_write8(priv, REG_EARLY_MODE_CONTROL_8710B, 0);
4207 }
4208
4209 /*
4210 * Unit in 8 bytes.
4211 * Get Rx PHY status in order to report RSSI and others.
4212 */
4213 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
4214
4215 if (priv->rtl_chip == RTL8192E) {
4216 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
4217 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
4218 } else if (priv->rtl_chip == RTL8188F) {
4219 rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff);
4220 rtl8xxxu_write32(priv, REG_HISR1, 0xffffffff);
4221 } else if (priv->rtl_chip == RTL8188E) {
4222 rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff);
4223 val32 = IMR0_PSTIMEOUT | IMR0_TBDER | IMR0_CPWM | IMR0_CPWM2;
4224 rtl8xxxu_write32(priv, REG_HIMR0, val32);
4225 val32 = IMR1_TXERR | IMR1_RXERR | IMR1_TXFOVW | IMR1_RXFOVW;
4226 rtl8xxxu_write32(priv, REG_HIMR1, val32);
4227 val8 = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION);
4228 val8 |= USB_SPEC_INT_BULK_SELECT;
4229 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, val8);
4230 } else if (priv->rtl_chip == RTL8710B) {
4231 rtl8xxxu_write32(priv, REG_HIMR0_8710B, 0);
4232 } else if (priv->rtl_chip != RTL8192F) {
4233 /*
4234 * Enable all interrupts - not obvious USB needs to do this
4235 */
4236 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
4237 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
4238 }
4239
4240 rtl8xxxu_set_mac(priv);
4241 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
4242
4243 /*
4244 * Configure initial WMAC settings
4245 */
4246 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
4247 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
4248 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
4249 rtl8xxxu_write32(priv, REG_RCR, val32);
4250 priv->regrcr = val32;
4251
4252 if (fops->init_reg_rxfltmap) {
4253 /* Accept all data frames */
4254 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
4255
4256 /*
4257 * Since ADF is removed from RCR, ps-poll will not be indicate to driver,
4258 * RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll.
4259 */
4260 rtl8xxxu_write16(priv, REG_RXFLTMAP1, 0x400);
4261
4262 /* Accept all management frames */
4263 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
4264 } else {
4265 /*
4266 * Accept all multicast
4267 */
4268 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
4269 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
4270 }
4271
4272 /*
4273 * Init adaptive controls
4274 */
4275 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4276 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4277 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
4278 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4279
4280 /* CCK = 0x0a, OFDM = 0x10 */
4281 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
4282 rtl8xxxu_set_retry(priv, 0x30, 0x30);
4283 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
4284
4285 /*
4286 * Init EDCA
4287 */
4288 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
4289
4290 /* Set CCK SIFS */
4291 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
4292
4293 /* Set OFDM SIFS */
4294 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
4295
4296 /* TXOP */
4297 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
4298 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
4299 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
4300 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
4301
4302 /* Set data auto rate fallback retry count */
4303 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
4304 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
4305 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
4306 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
4307
4308 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
4309 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
4310 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
4311
4312 /* Set ACK timeout */
4313 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
4314
4315 /*
4316 * Initialize beacon parameters
4317 */
4318 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
4319 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
4320 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
4321 if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8710B &&
4322 priv->rtl_chip != RTL8192F)
4323 /* Firmware will control REG_DRVERLYINT when power saving is enable, */
4324 /* so don't set this register on STA mode. */
4325 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
4326 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
4327 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
4328
4329 /*
4330 * Initialize burst parameters
4331 */
4332 if (priv->fops->init_burst)
4333 priv->fops->init_burst(priv);
4334
4335 if (fops->init_aggregation)
4336 fops->init_aggregation(priv);
4337
4338 if (fops->init_reg_pkt_life_time) {
4339 rtl8xxxu_write16(priv, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
4340 rtl8xxxu_write16(priv, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
4341 }
4342
4343 /*
4344 * Enable CCK and OFDM block
4345 */
4346 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4347 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
4348 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4349
4350 /*
4351 * Invalidate all CAM entries - bit 30 is undocumented
4352 */
4353 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
4354
4355 /*
4356 * Start out with default power levels for channel 6, 20MHz
4357 */
4358 fops->set_tx_power(priv, 1, false);
4359
4360 /* Let the 8051 take control of antenna setting */
4361 if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188F &&
4362 priv->rtl_chip != RTL8710B) {
4363 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4364 val8 |= LEDCFG2_DPDT_SELECT;
4365 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4366 }
4367
4368 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
4369
4370 /* Disable BAR - not sure if this has any effect on USB */
4371 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
4372
4373 if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8188E &&
4374 priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192F)
4375 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
4376
4377 if (fops->init_statistics)
4378 fops->init_statistics(priv);
4379
4380 if (priv->rtl_chip == RTL8192E) {
4381 /*
4382 * 0x4c6[3] 1: RTS BW = Data BW
4383 * 0: RTS BW depends on CCA / secondary CCA result.
4384 */
4385 val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL);
4386 val8 &= ~BIT(3);
4387 rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8);
4388 /*
4389 * Reset USB mode switch setting
4390 */
4391 rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00);
4392 } else if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8188E ||
4393 priv->rtl_chip == RTL8192F) {
4394 /*
4395 * Init GPIO settings for 8188f, 8188e, 8192f
4396 */
4397 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
4398 val8 &= ~GPIO_MUXCFG_IO_SEL_ENBT;
4399 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
4400 }
4401
4402 if (priv->rtl_chip == RTL8188F)
4403 /* CCK PD */
4404 rtl8xxxu_write8(priv, REG_CCK_PD_THRESH, CCK_PD_TYPE1_LV1_TH);
4405
4406 fops->phy_lc_calibrate(priv);
4407
4408 fops->phy_iq_calibrate(priv);
4409
4410 /*
4411 * This should enable thermal meter
4412 */
4413 if (fops->gen2_thermal_meter) {
4414 if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8710B) {
4415 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B);
4416 val32 |= 0x30000;
4417 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B, val32);
4418 } else {
4419 rtl8xxxu_write_rfreg(priv,
4420 RF_A, RF6052_REG_T_METER_8723B, 0x37cf8);
4421 }
4422 } else {
4423 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
4424 }
4425
4426 /* Set NAV_UPPER to 30000us */
4427 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
4428 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
4429
4430 if (priv->rtl_chip == RTL8723A) {
4431 /*
4432 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
4433 * but we need to find root cause.
4434 * This is 8723au only.
4435 */
4436 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4437 if ((val32 & 0xff000000) != 0x83000000) {
4438 val32 |= FPGA_RF_MODE_CCK;
4439 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4440 }
4441 } else if (priv->rtl_chip == RTL8192E || priv->rtl_chip == RTL8188E) {
4442 rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00);
4443 }
4444
4445 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
4446 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
4447 /* ack for xmit mgmt frames. */
4448 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
4449
4450 if (priv->rtl_chip == RTL8192E) {
4451 /*
4452 * Fix LDPC rx hang issue.
4453 */
4454 val32 = rtl8xxxu_read32(priv, REG_AFE_MISC);
4455 rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75);
4456 val32 &= 0xfff00fff;
4457 val32 |= 0x0007e000;
4458 rtl8xxxu_write32(priv, REG_AFE_MISC, val32);
4459
4460 /*
4461 * 0x824[9] = 0x82C[9] = 0xA80[7] those registers setting
4462 * should be equal or CCK RSSI report may be incorrect
4463 */
4464 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
4465 priv->cck_agc_report_type =
4466 u32_get_bits(val32, FPGA0_HSSI_PARM2_CCK_HIGH_PWR);
4467
4468 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_HSSI_PARM2);
4469 if (priv->cck_agc_report_type !=
4470 u32_get_bits(val32, FPGA0_HSSI_PARM2_CCK_HIGH_PWR)) {
4471 if (priv->cck_agc_report_type)
4472 val32 |= FPGA0_HSSI_PARM2_CCK_HIGH_PWR;
4473 else
4474 val32 &= ~FPGA0_HSSI_PARM2_CCK_HIGH_PWR;
4475 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM2, val32);
4476 }
4477
4478 val32 = rtl8xxxu_read32(priv, REG_AGC_RPT);
4479 if (priv->cck_agc_report_type)
4480 val32 |= AGC_RPT_CCK;
4481 else
4482 val32 &= ~AGC_RPT_CCK;
4483 rtl8xxxu_write32(priv, REG_AGC_RPT, val32);
4484 }
4485
4486 if (priv->rtl_chip == RTL8710B) {
4487 /*
4488 * 0x76D[5:4] is Port0,Port1 Enable Bit.
4489 * This is only for 8710B, 2b'00 for MP and 2b'11 for Normal Driver
4490 */
4491 val8 = rtl8xxxu_read8(priv, REG_PORT_CONTROL_8710B);
4492 val8 |= BIT(5) | BIT(4);
4493 rtl8xxxu_write8(priv, REG_PORT_CONTROL_8710B, val8);
4494
4495 /* Set 0x5c[8] and [2:0] = 1, LDO mode */
4496 val32 = rtl8xxxu_read32(priv, REG_WL_RF_PSS_8710B);
4497 val32 |= 0x107;
4498 rtl8xxxu_write32(priv, REG_WL_RF_PSS_8710B, val32);
4499 }
4500
4501 val32 = rtl8xxxu_read32(priv, 0xa9c);
4502 priv->cck_new_agc = u32_get_bits(val32, BIT(17));
4503
4504 /* Initialise the center frequency offset tracking */
4505 if (priv->fops->set_crystal_cap) {
4506 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING);
4507 priv->cfo_tracking.atc_status = val32 & CFO_TRACKING_ATC_STATUS;
4508 priv->cfo_tracking.adjust = true;
4509 priv->cfo_tracking.crystal_cap = priv->default_crystal_cap;
4510 }
4511
4512 if (priv->rtl_chip == RTL8188E)
4513 rtl8188e_ra_info_init_all(&priv->ra_info);
4514
4515 set_bit(RTL8XXXU_BC_MC_MACID, priv->mac_id_map);
4516
4517 exit:
4518 return ret;
4519 }
4520
rtl8xxxu_cam_write(struct rtl8xxxu_priv * priv,struct ieee80211_key_conf * key,const u8 * mac)4521 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
4522 struct ieee80211_key_conf *key, const u8 *mac)
4523 {
4524 u32 cmd, val32, addr, ctrl;
4525 int j, i, tmp_debug;
4526
4527 tmp_debug = rtl8xxxu_debug;
4528 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
4529 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
4530
4531 /*
4532 * This is a bit of a hack - the lower bits of the cipher
4533 * suite selector happens to match the cipher index in the CAM
4534 */
4535 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
4536 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
4537
4538 for (j = 5; j >= 0; j--) {
4539 switch (j) {
4540 case 0:
4541 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
4542 break;
4543 case 1:
4544 val32 = mac[2] | (mac[3] << 8) |
4545 (mac[4] << 16) | (mac[5] << 24);
4546 break;
4547 default:
4548 i = (j - 2) << 2;
4549 val32 = key->key[i] | (key->key[i + 1] << 8) |
4550 key->key[i + 2] << 16 | key->key[i + 3] << 24;
4551 break;
4552 }
4553
4554 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
4555 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
4556 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
4557 udelay(100);
4558 }
4559
4560 rtl8xxxu_debug = tmp_debug;
4561 }
4562
4563 static
rtl8xxxu_get_antenna(struct ieee80211_hw * hw,u32 * tx_ant,u32 * rx_ant)4564 int rtl8xxxu_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
4565 {
4566 struct rtl8xxxu_priv *priv = hw->priv;
4567
4568 *tx_ant = BIT(priv->tx_paths) - 1;
4569 *rx_ant = BIT(priv->rx_paths) - 1;
4570
4571 return 0;
4572 }
4573
rtl8xxxu_set_tim(struct ieee80211_hw * hw,struct ieee80211_sta * sta,bool set)4574 static int rtl8xxxu_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
4575 bool set)
4576 {
4577 struct rtl8xxxu_priv *priv = hw->priv;
4578
4579 schedule_work(&priv->update_beacon_work);
4580
4581 return 0;
4582 }
4583
rtl8xxxu_sw_scan_start(struct ieee80211_hw * hw,struct ieee80211_vif * vif,const u8 * mac)4584 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
4585 struct ieee80211_vif *vif, const u8 *mac)
4586 {
4587 struct rtl8xxxu_priv *priv = hw->priv;
4588 u8 val8;
4589
4590 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4591 val8 |= BEACON_DISABLE_TSF_UPDATE;
4592 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4593 }
4594
rtl8xxxu_sw_scan_complete(struct ieee80211_hw * hw,struct ieee80211_vif * vif)4595 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
4596 struct ieee80211_vif *vif)
4597 {
4598 struct rtl8xxxu_priv *priv = hw->priv;
4599 u8 val8;
4600
4601 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4602 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
4603 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4604 }
4605
rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv * priv,u32 ramask,u8 rateid,int sgi,int txbw_40mhz,u8 macid)4606 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
4607 u32 ramask, u8 rateid, int sgi, int txbw_40mhz,
4608 u8 macid)
4609 {
4610 struct h2c_cmd h2c;
4611
4612 memset(&h2c, 0, sizeof(struct h2c_cmd));
4613
4614 h2c.ramask.cmd = H2C_SET_RATE_MASK;
4615 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
4616 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
4617
4618 h2c.ramask.arg = 0x80;
4619 if (sgi)
4620 h2c.ramask.arg |= 0x20;
4621
4622 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
4623 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
4624 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
4625 }
4626
rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv * priv,u32 ramask,u8 rateid,int sgi,int txbw_40mhz,u8 macid)4627 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,
4628 u32 ramask, u8 rateid, int sgi, int txbw_40mhz,
4629 u8 macid)
4630 {
4631 struct h2c_cmd h2c;
4632 u8 bw;
4633
4634 if (txbw_40mhz)
4635 bw = RTL8XXXU_CHANNEL_WIDTH_40;
4636 else
4637 bw = RTL8XXXU_CHANNEL_WIDTH_20;
4638
4639 memset(&h2c, 0, sizeof(struct h2c_cmd));
4640
4641 h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID;
4642 h2c.b_macid_cfg.ramask0 = ramask & 0xff;
4643 h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff;
4644 h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff;
4645 h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff;
4646 h2c.b_macid_cfg.macid = macid;
4647
4648 h2c.b_macid_cfg.data1 = rateid;
4649 if (sgi)
4650 h2c.b_macid_cfg.data1 |= BIT(7);
4651
4652 h2c.b_macid_cfg.data2 = bw;
4653
4654 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, rateid %02x, sgi %d, size %zi\n",
4655 __func__, ramask, rateid, sgi, sizeof(h2c.b_macid_cfg));
4656 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg));
4657 }
4658
rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv * priv,u8 macid,u8 role,bool connect)4659 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv,
4660 u8 macid, u8 role, bool connect)
4661 {
4662 struct h2c_cmd h2c;
4663
4664 memset(&h2c, 0, sizeof(struct h2c_cmd));
4665
4666 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
4667
4668 if (connect)
4669 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
4670 else
4671 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
4672
4673 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
4674 }
4675
rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv * priv,u8 macid,u8 role,bool connect)4676 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv,
4677 u8 macid, u8 role, bool connect)
4678 {
4679 /*
4680 * The firmware turns on the rate control when it knows it's
4681 * connected to a network.
4682 */
4683 struct h2c_cmd h2c;
4684
4685 memset(&h2c, 0, sizeof(struct h2c_cmd));
4686
4687 h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT;
4688 if (connect)
4689 h2c.media_status_rpt.parm |= BIT(0);
4690 else
4691 h2c.media_status_rpt.parm &= ~BIT(0);
4692
4693 h2c.media_status_rpt.parm |= ((role << 4) & 0xf0);
4694 h2c.media_status_rpt.macid = macid;
4695
4696 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt));
4697 }
4698
rtl8xxxu_gen1_report_rssi(struct rtl8xxxu_priv * priv,u8 macid,u8 rssi)4699 void rtl8xxxu_gen1_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi)
4700 {
4701 struct h2c_cmd h2c;
4702 const int h2c_size = 4;
4703
4704 memset(&h2c, 0, sizeof(struct h2c_cmd));
4705
4706 h2c.rssi_report.cmd = H2C_SET_RSSI;
4707 h2c.rssi_report.macid = macid;
4708 h2c.rssi_report.rssi = rssi;
4709
4710 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, h2c_size);
4711 }
4712
rtl8xxxu_gen2_report_rssi(struct rtl8xxxu_priv * priv,u8 macid,u8 rssi)4713 void rtl8xxxu_gen2_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi)
4714 {
4715 struct h2c_cmd h2c;
4716 int h2c_size = sizeof(h2c.rssi_report);
4717
4718 if (priv->rtl_chip == RTL8723B)
4719 h2c_size = 4;
4720
4721 memset(&h2c, 0, sizeof(struct h2c_cmd));
4722
4723 h2c.rssi_report.cmd = H2C_8723B_RSSI_SETTING;
4724 h2c.rssi_report.macid = macid;
4725 h2c.rssi_report.rssi = rssi;
4726
4727 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, h2c_size);
4728 }
4729
rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv * priv)4730 void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv)
4731 {
4732 u8 agg_ctrl, usb_spec, page_thresh, timeout;
4733
4734 usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION);
4735 usb_spec &= ~USB_SPEC_USB_AGG_ENABLE;
4736 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec);
4737
4738 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
4739 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
4740
4741 if (!rtl8xxxu_dma_aggregation) {
4742 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
4743 return;
4744 }
4745
4746 agg_ctrl |= TRXDMA_CTRL_RXDMA_AGG_EN;
4747 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
4748
4749 /*
4750 * The number of packets we can take looks to be buffer size / 512
4751 * which matches the 512 byte rounding we have to do when de-muxing
4752 * the packets.
4753 *
4754 * Sample numbers from the vendor driver:
4755 * USB High-Speed mode values:
4756 * RxAggBlockCount = 8 : 512 byte unit
4757 * RxAggBlockTimeout = 6
4758 * RxAggPageCount = 48 : 128 byte unit
4759 * RxAggPageTimeout = 4 or 6 (absolute time 34ms/(2^6))
4760 */
4761
4762 page_thresh = (priv->fops->rx_agg_buf_size / 512);
4763 if (rtl8xxxu_dma_agg_pages >= 0) {
4764 if (rtl8xxxu_dma_agg_pages <= page_thresh)
4765 timeout = page_thresh;
4766 else if (rtl8xxxu_dma_agg_pages <= 6)
4767 dev_err(&priv->udev->dev,
4768 "%s: dma_agg_pages=%i too small, minimum is 6\n",
4769 __func__, rtl8xxxu_dma_agg_pages);
4770 else
4771 dev_err(&priv->udev->dev,
4772 "%s: dma_agg_pages=%i larger than limit %i\n",
4773 __func__, rtl8xxxu_dma_agg_pages, page_thresh);
4774 }
4775 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH, page_thresh);
4776 /*
4777 * REG_RXDMA_AGG_PG_TH + 1 seems to be the timeout register on
4778 * gen2 chips and rtl8188eu. The rtl8723au seems unhappy if we
4779 * don't set it, so better set both.
4780 */
4781 timeout = 4;
4782
4783 if (rtl8xxxu_dma_agg_timeout >= 0) {
4784 if (rtl8xxxu_dma_agg_timeout <= 127)
4785 timeout = rtl8xxxu_dma_agg_timeout;
4786 else
4787 dev_err(&priv->udev->dev,
4788 "%s: Invalid dma_agg_timeout: %i\n",
4789 __func__, rtl8xxxu_dma_agg_timeout);
4790 }
4791
4792 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH + 1, timeout);
4793 rtl8xxxu_write8(priv, REG_USB_DMA_AGG_TO, timeout);
4794 priv->rx_buf_aggregation = 1;
4795 }
4796
4797 static const struct ieee80211_rate rtl8xxxu_legacy_ratetable[] = {
4798 {.bitrate = 10, .hw_value = 0x00,},
4799 {.bitrate = 20, .hw_value = 0x01,},
4800 {.bitrate = 55, .hw_value = 0x02,},
4801 {.bitrate = 110, .hw_value = 0x03,},
4802 {.bitrate = 60, .hw_value = 0x04,},
4803 {.bitrate = 90, .hw_value = 0x05,},
4804 {.bitrate = 120, .hw_value = 0x06,},
4805 {.bitrate = 180, .hw_value = 0x07,},
4806 {.bitrate = 240, .hw_value = 0x08,},
4807 {.bitrate = 360, .hw_value = 0x09,},
4808 {.bitrate = 480, .hw_value = 0x0a,},
4809 {.bitrate = 540, .hw_value = 0x0b,},
4810 };
4811
rtl8xxxu_desc_to_mcsrate(u16 rate,u8 * mcs,u8 * nss)4812 static void rtl8xxxu_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss)
4813 {
4814 if (rate <= DESC_RATE_54M)
4815 return;
4816
4817 if (rate >= DESC_RATE_MCS0 && rate <= DESC_RATE_MCS15) {
4818 if (rate < DESC_RATE_MCS8)
4819 *nss = 1;
4820 else
4821 *nss = 2;
4822 *mcs = rate - DESC_RATE_MCS0;
4823 }
4824 }
4825
rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv * priv,u32 rate_cfg)4826 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
4827 {
4828 struct ieee80211_hw *hw = priv->hw;
4829 u32 val32;
4830 u8 rate_idx = 0;
4831
4832 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
4833
4834 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4835 if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ)
4836 val32 &= RESPONSE_RATE_RRSR_INIT_5G;
4837 else
4838 val32 &= RESPONSE_RATE_RRSR_INIT_2G;
4839 val32 |= rate_cfg;
4840 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4841
4842 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
4843
4844 while (rate_cfg) {
4845 rate_cfg = (rate_cfg >> 1);
4846 rate_idx++;
4847 }
4848 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
4849 }
4850
4851 static u16
rtl8xxxu_wireless_mode(struct ieee80211_hw * hw,struct ieee80211_sta * sta)4852 rtl8xxxu_wireless_mode(struct ieee80211_hw *hw, struct ieee80211_sta *sta)
4853 {
4854 u16 network_type = WIRELESS_MODE_UNKNOWN;
4855
4856 if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ) {
4857 if (sta->deflink.vht_cap.vht_supported)
4858 network_type = WIRELESS_MODE_AC;
4859 else if (sta->deflink.ht_cap.ht_supported)
4860 network_type = WIRELESS_MODE_N_5G;
4861
4862 network_type |= WIRELESS_MODE_A;
4863 } else {
4864 if (sta->deflink.vht_cap.vht_supported)
4865 network_type = WIRELESS_MODE_AC;
4866 else if (sta->deflink.ht_cap.ht_supported)
4867 network_type = WIRELESS_MODE_N_24G;
4868
4869 if (sta->deflink.supp_rates[0] <= 0xf)
4870 network_type |= WIRELESS_MODE_B;
4871 else if (sta->deflink.supp_rates[0] & 0xf)
4872 network_type |= (WIRELESS_MODE_B | WIRELESS_MODE_G);
4873 else
4874 network_type |= WIRELESS_MODE_G;
4875 }
4876
4877 return network_type;
4878 }
4879
rtl8xxxu_set_aifs(struct rtl8xxxu_priv * priv,u8 slot_time)4880 static void rtl8xxxu_set_aifs(struct rtl8xxxu_priv *priv, u8 slot_time)
4881 {
4882 u32 reg_edca_param[IEEE80211_NUM_ACS] = {
4883 [IEEE80211_AC_VO] = REG_EDCA_VO_PARAM,
4884 [IEEE80211_AC_VI] = REG_EDCA_VI_PARAM,
4885 [IEEE80211_AC_BE] = REG_EDCA_BE_PARAM,
4886 [IEEE80211_AC_BK] = REG_EDCA_BK_PARAM,
4887 };
4888 u32 val32;
4889 u16 wireless_mode = 0;
4890 u8 aifs, aifsn, sifs;
4891 int i;
4892
4893 if (priv->vif) {
4894 struct ieee80211_sta *sta;
4895
4896 rcu_read_lock();
4897 sta = ieee80211_find_sta(priv->vif, priv->vif->bss_conf.bssid);
4898 if (sta)
4899 wireless_mode = rtl8xxxu_wireless_mode(priv->hw, sta);
4900 rcu_read_unlock();
4901 }
4902
4903 if (priv->hw->conf.chandef.chan->band == NL80211_BAND_5GHZ ||
4904 (wireless_mode & WIRELESS_MODE_N_24G))
4905 sifs = 16;
4906 else
4907 sifs = 10;
4908
4909 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
4910 val32 = rtl8xxxu_read32(priv, reg_edca_param[i]);
4911
4912 /* It was set in conf_tx. */
4913 aifsn = val32 & 0xff;
4914
4915 /* aifsn not set yet or already fixed */
4916 if (aifsn < 2 || aifsn > 15)
4917 continue;
4918
4919 aifs = aifsn * slot_time + sifs;
4920
4921 val32 &= ~0xff;
4922 val32 |= aifs;
4923 rtl8xxxu_write32(priv, reg_edca_param[i], val32);
4924 }
4925 }
4926
rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report * rarpt,u8 rate,u8 sgi,u8 bw)4927 void rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report *rarpt,
4928 u8 rate, u8 sgi, u8 bw)
4929 {
4930 u8 mcs, nss;
4931
4932 rarpt->txrate.flags = 0;
4933
4934 if (rate <= DESC_RATE_54M) {
4935 rarpt->txrate.legacy = rtl8xxxu_legacy_ratetable[rate].bitrate;
4936 } else {
4937 rtl8xxxu_desc_to_mcsrate(rate, &mcs, &nss);
4938 rarpt->txrate.flags |= RATE_INFO_FLAGS_MCS;
4939
4940 rarpt->txrate.mcs = mcs;
4941 rarpt->txrate.nss = nss;
4942
4943 if (sgi)
4944 rarpt->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
4945
4946 rarpt->txrate.bw = bw;
4947 }
4948
4949 rarpt->bit_rate = cfg80211_calculate_bitrate(&rarpt->txrate);
4950 rarpt->desc_rate = rate;
4951 }
4952
4953 static void
rtl8xxxu_bss_info_changed(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_bss_conf * bss_conf,u64 changed)4954 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4955 struct ieee80211_bss_conf *bss_conf, u64 changed)
4956 {
4957 struct rtl8xxxu_priv *priv = hw->priv;
4958 struct device *dev = &priv->udev->dev;
4959 struct ieee80211_sta *sta;
4960 struct rtl8xxxu_ra_report *rarpt;
4961 u32 val32;
4962 u8 val8;
4963
4964 rarpt = &priv->ra_report;
4965
4966 if (changed & BSS_CHANGED_ASSOC) {
4967 dev_dbg(dev, "Changed ASSOC: %i!\n", vif->cfg.assoc);
4968
4969 rtl8xxxu_set_linktype(priv, vif->type);
4970
4971 if (vif->cfg.assoc) {
4972 u32 ramask;
4973 int sgi = 0;
4974 u8 highest_rate;
4975 u8 bw;
4976
4977 rcu_read_lock();
4978 sta = ieee80211_find_sta(vif, bss_conf->bssid);
4979 if (!sta) {
4980 dev_info(dev, "%s: ASSOC no sta found\n",
4981 __func__);
4982 rcu_read_unlock();
4983 goto error;
4984 }
4985
4986 if (sta->deflink.ht_cap.ht_supported)
4987 dev_info(dev, "%s: HT supported\n", __func__);
4988 if (sta->deflink.vht_cap.vht_supported)
4989 dev_info(dev, "%s: VHT supported\n", __func__);
4990
4991 /* TODO: Set bits 28-31 for rate adaptive id */
4992 ramask = (sta->deflink.supp_rates[0] & 0xfff) |
4993 sta->deflink.ht_cap.mcs.rx_mask[0] << 12 |
4994 sta->deflink.ht_cap.mcs.rx_mask[1] << 20;
4995 if (sta->deflink.ht_cap.cap &
4996 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
4997 sgi = 1;
4998
4999 highest_rate = fls(ramask) - 1;
5000 if (rtl8xxxu_ht40_2g &&
5001 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40))
5002 bw = RATE_INFO_BW_40;
5003 else
5004 bw = RATE_INFO_BW_20;
5005 rcu_read_unlock();
5006
5007 rtl8xxxu_update_ra_report(rarpt, highest_rate, sgi, bw);
5008
5009 priv->vif = vif;
5010 priv->rssi_level = RTL8XXXU_RATR_STA_INIT;
5011
5012 priv->fops->update_rate_mask(priv, ramask, 0, sgi,
5013 bw == RATE_INFO_BW_40, 0);
5014
5015 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
5016
5017 rtl8xxxu_stop_tx_beacon(priv);
5018
5019 /* joinbss sequence */
5020 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
5021 0xc000 | vif->cfg.aid);
5022
5023 priv->fops->report_connect(priv, 0, H2C_MACID_ROLE_AP, true);
5024 } else {
5025 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5026 val8 |= BEACON_DISABLE_TSF_UPDATE;
5027 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5028
5029 priv->fops->report_connect(priv, 0, H2C_MACID_ROLE_AP, false);
5030 }
5031 }
5032
5033 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
5034 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
5035 bss_conf->use_short_preamble);
5036 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
5037 if (bss_conf->use_short_preamble)
5038 val32 |= RSR_ACK_SHORT_PREAMBLE;
5039 else
5040 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
5041 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
5042 }
5043
5044 if (changed & BSS_CHANGED_ERP_SLOT) {
5045 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
5046 bss_conf->use_short_slot);
5047
5048 if (bss_conf->use_short_slot)
5049 val8 = 9;
5050 else
5051 val8 = 20;
5052 rtl8xxxu_write8(priv, REG_SLOT, val8);
5053
5054 rtl8xxxu_set_aifs(priv, val8);
5055 }
5056
5057 if (changed & BSS_CHANGED_BSSID) {
5058 dev_dbg(dev, "Changed BSSID!\n");
5059 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
5060 }
5061
5062 if (changed & BSS_CHANGED_BASIC_RATES) {
5063 dev_dbg(dev, "Changed BASIC_RATES!\n");
5064 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
5065 }
5066
5067 if (changed & BSS_CHANGED_BEACON_ENABLED) {
5068 if (bss_conf->enable_beacon)
5069 rtl8xxxu_start_tx_beacon(priv);
5070 else
5071 rtl8xxxu_stop_tx_beacon(priv);
5072 }
5073
5074 if (changed & BSS_CHANGED_BEACON)
5075 schedule_work(&priv->update_beacon_work);
5076
5077 error:
5078 return;
5079 }
5080
rtl8xxxu_start_ap(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_bss_conf * link_conf)5081 static int rtl8xxxu_start_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5082 struct ieee80211_bss_conf *link_conf)
5083 {
5084 struct rtl8xxxu_priv *priv = hw->priv;
5085 struct device *dev = &priv->udev->dev;
5086
5087 dev_dbg(dev, "Start AP mode\n");
5088 rtl8xxxu_set_bssid(priv, vif->bss_conf.bssid);
5089 rtl8xxxu_write16(priv, REG_BCN_INTERVAL, vif->bss_conf.beacon_int);
5090 priv->fops->report_connect(priv, RTL8XXXU_BC_MC_MACID, 0, true);
5091
5092 return 0;
5093 }
5094
rtl8xxxu_80211_to_rtl_queue(u32 queue)5095 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
5096 {
5097 u32 rtlqueue;
5098
5099 switch (queue) {
5100 case IEEE80211_AC_VO:
5101 rtlqueue = TXDESC_QUEUE_VO;
5102 break;
5103 case IEEE80211_AC_VI:
5104 rtlqueue = TXDESC_QUEUE_VI;
5105 break;
5106 case IEEE80211_AC_BE:
5107 rtlqueue = TXDESC_QUEUE_BE;
5108 break;
5109 case IEEE80211_AC_BK:
5110 rtlqueue = TXDESC_QUEUE_BK;
5111 break;
5112 default:
5113 rtlqueue = TXDESC_QUEUE_BE;
5114 }
5115
5116 return rtlqueue;
5117 }
5118
rtl8xxxu_queue_select(struct ieee80211_hdr * hdr,struct sk_buff * skb)5119 static u32 rtl8xxxu_queue_select(struct ieee80211_hdr *hdr, struct sk_buff *skb)
5120 {
5121 u32 queue;
5122
5123 if (unlikely(ieee80211_is_beacon(hdr->frame_control)))
5124 queue = TXDESC_QUEUE_BEACON;
5125 else if (ieee80211_is_mgmt(hdr->frame_control))
5126 queue = TXDESC_QUEUE_MGNT;
5127 else
5128 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
5129
5130 return queue;
5131 }
5132
5133 /*
5134 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor
5135 * format. The descriptor checksum is still only calculated over the
5136 * initial 32 bytes of the descriptor!
5137 */
rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 * tx_desc)5138 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc)
5139 {
5140 __le16 *ptr = (__le16 *)tx_desc;
5141 u16 csum = 0;
5142 int i;
5143
5144 /*
5145 * Clear csum field before calculation, as the csum field is
5146 * in the middle of the struct.
5147 */
5148 tx_desc->csum = cpu_to_le16(0);
5149
5150 for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++)
5151 csum = csum ^ le16_to_cpu(ptr[i]);
5152
5153 tx_desc->csum |= cpu_to_le16(csum);
5154 }
5155
rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv * priv)5156 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
5157 {
5158 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
5159 unsigned long flags;
5160
5161 spin_lock_irqsave(&priv->tx_urb_lock, flags);
5162 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
5163 list_del(&tx_urb->list);
5164 priv->tx_urb_free_count--;
5165 usb_free_urb(&tx_urb->urb);
5166 }
5167 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5168 }
5169
5170 static struct rtl8xxxu_tx_urb *
rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv * priv)5171 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
5172 {
5173 struct rtl8xxxu_tx_urb *tx_urb;
5174 unsigned long flags;
5175
5176 spin_lock_irqsave(&priv->tx_urb_lock, flags);
5177 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
5178 struct rtl8xxxu_tx_urb, list);
5179 if (tx_urb) {
5180 list_del(&tx_urb->list);
5181 priv->tx_urb_free_count--;
5182 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
5183 !priv->tx_stopped) {
5184 priv->tx_stopped = true;
5185 ieee80211_stop_queues(priv->hw);
5186 }
5187 }
5188
5189 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5190
5191 return tx_urb;
5192 }
5193
rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv * priv,struct rtl8xxxu_tx_urb * tx_urb)5194 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
5195 struct rtl8xxxu_tx_urb *tx_urb)
5196 {
5197 unsigned long flags;
5198
5199 INIT_LIST_HEAD(&tx_urb->list);
5200
5201 spin_lock_irqsave(&priv->tx_urb_lock, flags);
5202
5203 list_add(&tx_urb->list, &priv->tx_urb_free_list);
5204 priv->tx_urb_free_count++;
5205 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
5206 priv->tx_stopped) {
5207 priv->tx_stopped = false;
5208 ieee80211_wake_queues(priv->hw);
5209 }
5210
5211 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5212 }
5213
rtl8xxxu_tx_complete(struct urb * urb)5214 static void rtl8xxxu_tx_complete(struct urb *urb)
5215 {
5216 struct sk_buff *skb = (struct sk_buff *)urb->context;
5217 struct ieee80211_tx_info *tx_info;
5218 struct ieee80211_hw *hw;
5219 struct rtl8xxxu_priv *priv;
5220 struct rtl8xxxu_tx_urb *tx_urb =
5221 container_of(urb, struct rtl8xxxu_tx_urb, urb);
5222
5223 tx_info = IEEE80211_SKB_CB(skb);
5224 hw = tx_info->rate_driver_data[0];
5225 priv = hw->priv;
5226
5227 skb_pull(skb, priv->fops->tx_desc_size);
5228
5229 ieee80211_tx_info_clear_status(tx_info);
5230 tx_info->status.rates[0].idx = -1;
5231 tx_info->status.rates[0].count = 0;
5232
5233 if (!urb->status)
5234 tx_info->flags |= IEEE80211_TX_STAT_ACK;
5235
5236 ieee80211_tx_status_irqsafe(hw, skb);
5237
5238 rtl8xxxu_free_tx_urb(priv, tx_urb);
5239 }
5240
rtl8xxxu_dump_action(struct device * dev,struct ieee80211_hdr * hdr)5241 static void rtl8xxxu_dump_action(struct device *dev,
5242 struct ieee80211_hdr *hdr)
5243 {
5244 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
5245 u16 cap, timeout;
5246
5247 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
5248 return;
5249
5250 switch (mgmt->u.action.u.addba_resp.action_code) {
5251 case WLAN_ACTION_ADDBA_RESP:
5252 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
5253 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
5254 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
5255 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
5256 "status %02x\n",
5257 timeout,
5258 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
5259 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
5260 (cap >> 1) & 0x1,
5261 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
5262 break;
5263 case WLAN_ACTION_ADDBA_REQ:
5264 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
5265 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
5266 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
5267 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
5268 timeout,
5269 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
5270 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
5271 (cap >> 1) & 0x1);
5272 break;
5273 default:
5274 dev_info(dev, "action frame %02x\n",
5275 mgmt->u.action.u.addba_resp.action_code);
5276 break;
5277 }
5278 }
5279
5280 /*
5281 * Fill in v1 (gen1) specific TX descriptor bits.
5282 * This format is used on 8188cu/8192cu/8723au
5283 */
5284 void
rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw * hw,struct ieee80211_hdr * hdr,struct ieee80211_tx_info * tx_info,struct rtl8xxxu_txdesc32 * tx_desc,bool sgi,bool short_preamble,bool ampdu_enable,u32 rts_rate,u8 macid)5285 rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
5286 struct ieee80211_tx_info *tx_info,
5287 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi,
5288 bool short_preamble, bool ampdu_enable, u32 rts_rate,
5289 u8 macid)
5290 {
5291 struct rtl8xxxu_priv *priv = hw->priv;
5292 struct device *dev = &priv->udev->dev;
5293 u8 *qc = ieee80211_get_qos_ctl(hdr);
5294 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
5295 u32 rate = 0;
5296 u16 seq_number;
5297
5298 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
5299 dev_info(dev, "%s: TX rate: %d, pkt size %u\n",
5300 __func__, rate, le16_to_cpu(tx_desc->pkt_size));
5301
5302 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
5303
5304 tx_desc->txdw5 = cpu_to_le32(rate);
5305
5306 if (ieee80211_is_data(hdr->frame_control))
5307 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
5308
5309 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT);
5310
5311 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational))
5312 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE);
5313 else
5314 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK);
5315
5316 if (ieee80211_is_mgmt(hdr->frame_control)) {
5317 tx_desc->txdw5 = cpu_to_le32(rate);
5318 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
5319 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT);
5320 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);
5321 }
5322
5323 if (ieee80211_is_data_qos(hdr->frame_control))
5324 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);
5325
5326 if (short_preamble)
5327 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);
5328
5329 if (sgi)
5330 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI);
5331
5332 /*
5333 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled
5334 */
5335 tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT);
5336 if (ampdu_enable || tx_info->control.use_rts) {
5337 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);
5338 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
5339 } else if (tx_info->control.use_cts_prot) {
5340 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE);
5341 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
5342 }
5343 }
5344
5345 /*
5346 * Fill in v2 (gen2) specific TX descriptor bits.
5347 * This format is used on 8192eu/8723bu
5348 */
5349 void
rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw * hw,struct ieee80211_hdr * hdr,struct ieee80211_tx_info * tx_info,struct rtl8xxxu_txdesc32 * tx_desc32,bool sgi,bool short_preamble,bool ampdu_enable,u32 rts_rate,u8 macid)5350 rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
5351 struct ieee80211_tx_info *tx_info,
5352 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi,
5353 bool short_preamble, bool ampdu_enable, u32 rts_rate,
5354 u8 macid)
5355 {
5356 struct rtl8xxxu_priv *priv = hw->priv;
5357 struct device *dev = &priv->udev->dev;
5358 struct rtl8xxxu_txdesc40 *tx_desc40;
5359 u8 *qc = ieee80211_get_qos_ctl(hdr);
5360 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
5361 u32 rate = 0;
5362 u16 seq_number;
5363
5364 tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc32;
5365
5366 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
5367 dev_info(dev, "%s: TX rate: %d, pkt size %u\n",
5368 __func__, rate, le16_to_cpu(tx_desc40->pkt_size));
5369
5370 tx_desc40->txdw1 |= cpu_to_le32(macid << TXDESC40_MACID_SHIFT);
5371
5372 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
5373
5374 tx_desc40->txdw4 = cpu_to_le32(rate);
5375 if (ieee80211_is_data(hdr->frame_control)) {
5376 tx_desc40->txdw4 |= cpu_to_le32(0x1f <<
5377 TXDESC40_DATA_RATE_FB_SHIFT);
5378 }
5379
5380 tx_desc40->txdw9 = cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT);
5381
5382 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational))
5383 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE);
5384 else
5385 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK);
5386
5387 if (ieee80211_is_mgmt(hdr->frame_control)) {
5388 tx_desc40->txdw4 = cpu_to_le32(rate);
5389 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_USE_DRIVER_RATE);
5390 tx_desc40->txdw4 |=
5391 cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT);
5392 tx_desc40->txdw4 |= cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE);
5393 }
5394
5395 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)
5396 tx_desc40->txdw8 |= cpu_to_le32(TXDESC40_HW_SEQ_ENABLE);
5397
5398 if (short_preamble)
5399 tx_desc40->txdw5 |= cpu_to_le32(TXDESC40_SHORT_PREAMBLE);
5400
5401 tx_desc40->txdw4 |= cpu_to_le32(rts_rate << TXDESC40_RTS_RATE_SHIFT);
5402
5403 /*
5404 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled
5405 */
5406 if (ampdu_enable || tx_info->control.use_rts) {
5407 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE);
5408 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE);
5409 } else if (tx_info->control.use_cts_prot) {
5410 /*
5411 * For some reason the vendor driver doesn't set
5412 * TXDESC40_HW_RTS_ENABLE for CTS to SELF
5413 */
5414 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_CTS_SELF_ENABLE);
5415 }
5416 }
5417
5418 /*
5419 * Fill in v3 (gen1) specific TX descriptor bits.
5420 * This format is a hybrid between the v1 and v2 formats, only seen
5421 * on 8188eu devices so far.
5422 */
5423 void
rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw * hw,struct ieee80211_hdr * hdr,struct ieee80211_tx_info * tx_info,struct rtl8xxxu_txdesc32 * tx_desc,bool sgi,bool short_preamble,bool ampdu_enable,u32 rts_rate,u8 macid)5424 rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
5425 struct ieee80211_tx_info *tx_info,
5426 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi,
5427 bool short_preamble, bool ampdu_enable, u32 rts_rate,
5428 u8 macid)
5429 {
5430 struct rtl8xxxu_priv *priv = hw->priv;
5431 struct device *dev = &priv->udev->dev;
5432 struct rtl8xxxu_ra_info *ra = &priv->ra_info;
5433 u8 *qc = ieee80211_get_qos_ctl(hdr);
5434 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
5435 u32 rate = 0;
5436 u16 seq_number;
5437
5438 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
5439
5440 if (ieee80211_is_data(hdr->frame_control)) {
5441 rate = ra->decision_rate;
5442 tx_desc->txdw5 = cpu_to_le32(rate);
5443 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
5444 tx_desc->txdw4 |= le32_encode_bits(ra->pt_stage, TXDESC32_PT_STAGE_MASK);
5445 /* Data/RTS rate FB limit */
5446 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
5447 }
5448
5449 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
5450 dev_info(dev, "%s: TX rate: %d, pkt size %d\n",
5451 __func__, rate, le16_to_cpu(tx_desc->pkt_size));
5452
5453 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT);
5454
5455 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational))
5456 tx_desc->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE);
5457 else
5458 tx_desc->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK);
5459
5460 if (ieee80211_is_mgmt(hdr->frame_control)) {
5461 tx_desc->txdw5 = cpu_to_le32(rate);
5462 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
5463 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT);
5464 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);
5465 }
5466
5467 if (ieee80211_is_data_qos(hdr->frame_control)) {
5468 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);
5469
5470 if (conf_is_ht40(&hw->conf)) {
5471 tx_desc->txdw4 |= cpu_to_le32(TXDESC_DATA_BW);
5472
5473 if (conf_is_ht40_minus(&hw->conf))
5474 tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_UPPER);
5475 else
5476 tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_LOWER);
5477 }
5478 }
5479
5480 if (short_preamble)
5481 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);
5482
5483 if (sgi && ra->rate_sgi)
5484 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI);
5485
5486 /*
5487 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled
5488 */
5489 tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT);
5490 if (ampdu_enable || tx_info->control.use_rts) {
5491 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);
5492 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
5493 } else if (tx_info->control.use_cts_prot) {
5494 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE);
5495 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
5496 }
5497
5498 tx_desc->txdw2 |= cpu_to_le32(TXDESC_ANTENNA_SELECT_A |
5499 TXDESC_ANTENNA_SELECT_B);
5500 tx_desc->txdw7 |= cpu_to_le16(TXDESC_ANTENNA_SELECT_C >> 16);
5501 }
5502
rtl8xxxu_tx(struct ieee80211_hw * hw,struct ieee80211_tx_control * control,struct sk_buff * skb)5503 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
5504 struct ieee80211_tx_control *control,
5505 struct sk_buff *skb)
5506 {
5507 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
5508 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
5509 struct rtl8xxxu_priv *priv = hw->priv;
5510 struct rtl8xxxu_txdesc32 *tx_desc;
5511 struct rtl8xxxu_tx_urb *tx_urb;
5512 struct ieee80211_sta *sta = NULL;
5513 struct ieee80211_vif *vif = tx_info->control.vif;
5514 struct device *dev = &priv->udev->dev;
5515 u32 queue, rts_rate;
5516 u16 pktlen = skb->len;
5517 int tx_desc_size = priv->fops->tx_desc_size;
5518 u8 macid;
5519 int ret;
5520 bool ampdu_enable, sgi = false, short_preamble = false;
5521
5522 if (skb_headroom(skb) < tx_desc_size) {
5523 dev_warn(dev,
5524 "%s: Not enough headroom (%i) for tx descriptor\n",
5525 __func__, skb_headroom(skb));
5526 goto error;
5527 }
5528
5529 if (unlikely(skb->len > (65535 - tx_desc_size))) {
5530 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
5531 __func__, skb->len);
5532 goto error;
5533 }
5534
5535 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
5536 if (!tx_urb) {
5537 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
5538 goto error;
5539 }
5540
5541 if (ieee80211_is_action(hdr->frame_control))
5542 rtl8xxxu_dump_action(dev, hdr);
5543
5544 tx_info->rate_driver_data[0] = hw;
5545
5546 if (control && control->sta)
5547 sta = control->sta;
5548
5549 queue = rtl8xxxu_queue_select(hdr, skb);
5550
5551 tx_desc = skb_push(skb, tx_desc_size);
5552
5553 memset(tx_desc, 0, tx_desc_size);
5554 tx_desc->pkt_size = cpu_to_le16(pktlen);
5555 tx_desc->pkt_offset = tx_desc_size;
5556
5557 /* These bits mean different things to the RTL8192F. */
5558 if (priv->rtl_chip != RTL8192F)
5559 tx_desc->txdw0 =
5560 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
5561 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
5562 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
5563 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
5564
5565 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
5566
5567 if (tx_info->control.hw_key) {
5568 switch (tx_info->control.hw_key->cipher) {
5569 case WLAN_CIPHER_SUITE_WEP40:
5570 case WLAN_CIPHER_SUITE_WEP104:
5571 case WLAN_CIPHER_SUITE_TKIP:
5572 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
5573 break;
5574 case WLAN_CIPHER_SUITE_CCMP:
5575 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
5576 break;
5577 default:
5578 break;
5579 }
5580 }
5581
5582 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
5583 ampdu_enable = false;
5584 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
5585 if (sta->deflink.ht_cap.ht_supported) {
5586 u32 ampdu, val32;
5587 u8 *qc = ieee80211_get_qos_ctl(hdr);
5588 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
5589
5590 ampdu = (u32)sta->deflink.ht_cap.ampdu_density;
5591 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
5592 tx_desc->txdw2 |= cpu_to_le32(val32);
5593
5594 ampdu_enable = true;
5595
5596 if (!test_bit(tid, priv->tx_aggr_started) &&
5597 !(skb->protocol == cpu_to_be16(ETH_P_PAE)))
5598 if (!ieee80211_start_tx_ba_session(sta, tid, 0))
5599 set_bit(tid, priv->tx_aggr_started);
5600 }
5601 }
5602
5603 if (ieee80211_is_data_qos(hdr->frame_control) &&
5604 sta && sta->deflink.ht_cap.cap &
5605 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
5606 sgi = true;
5607
5608 if (sta && vif && vif->bss_conf.use_short_preamble)
5609 short_preamble = true;
5610
5611 if (skb->len > hw->wiphy->rts_threshold)
5612 tx_info->control.use_rts = true;
5613
5614 if (sta && vif && vif->bss_conf.use_cts_prot)
5615 tx_info->control.use_cts_prot = true;
5616
5617 if (ampdu_enable || tx_info->control.use_rts ||
5618 tx_info->control.use_cts_prot)
5619 rts_rate = DESC_RATE_24M;
5620 else
5621 rts_rate = 0;
5622
5623 macid = rtl8xxxu_get_macid(priv, sta);
5624 priv->fops->fill_txdesc(hw, hdr, tx_info, tx_desc, sgi, short_preamble,
5625 ampdu_enable, rts_rate, macid);
5626
5627 rtl8xxxu_calc_tx_desc_csum(tx_desc);
5628
5629 /* avoid zero checksum make tx hang */
5630 if (priv->rtl_chip == RTL8710B || priv->rtl_chip == RTL8192F)
5631 tx_desc->csum = ~tx_desc->csum;
5632
5633 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
5634 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
5635
5636 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
5637 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
5638 if (ret) {
5639 usb_unanchor_urb(&tx_urb->urb);
5640 rtl8xxxu_free_tx_urb(priv, tx_urb);
5641 goto error;
5642 }
5643 return;
5644 error:
5645 dev_kfree_skb(skb);
5646 }
5647
rtl8xxxu_send_beacon_frame(struct ieee80211_hw * hw,struct ieee80211_vif * vif)5648 static void rtl8xxxu_send_beacon_frame(struct ieee80211_hw *hw,
5649 struct ieee80211_vif *vif)
5650 {
5651 struct rtl8xxxu_priv *priv = hw->priv;
5652 struct sk_buff *skb = ieee80211_beacon_get(hw, vif, 0);
5653 struct device *dev = &priv->udev->dev;
5654 int retry;
5655 u8 val8;
5656
5657 /* BCN_VALID, write 1 to clear, cleared by SW */
5658 val8 = rtl8xxxu_read8(priv, REG_TDECTRL + 2);
5659 val8 |= BIT_BCN_VALID >> 16;
5660 rtl8xxxu_write8(priv, REG_TDECTRL + 2, val8);
5661
5662 /* SW_BCN_SEL - Port0 */
5663 val8 = rtl8xxxu_read8(priv, REG_DWBCN1_CTRL_8723B + 2);
5664 val8 &= ~(BIT_SW_BCN_SEL >> 16);
5665 rtl8xxxu_write8(priv, REG_DWBCN1_CTRL_8723B + 2, val8);
5666
5667 if (skb)
5668 rtl8xxxu_tx(hw, NULL, skb);
5669
5670 retry = 100;
5671 do {
5672 val8 = rtl8xxxu_read8(priv, REG_TDECTRL + 2);
5673 if (val8 & (BIT_BCN_VALID >> 16))
5674 break;
5675 usleep_range(10, 20);
5676 } while (--retry);
5677
5678 if (!retry)
5679 dev_err(dev, "%s: Failed to read beacon valid bit\n", __func__);
5680 }
5681
rtl8xxxu_update_beacon_work_callback(struct work_struct * work)5682 static void rtl8xxxu_update_beacon_work_callback(struct work_struct *work)
5683 {
5684 struct rtl8xxxu_priv *priv =
5685 container_of(work, struct rtl8xxxu_priv, update_beacon_work);
5686 struct ieee80211_hw *hw = priv->hw;
5687 struct ieee80211_vif *vif = priv->vif;
5688
5689 if (!vif) {
5690 WARN_ONCE(true, "no vif to update beacon\n");
5691 return;
5692 }
5693
5694 rtl8xxxu_send_beacon_frame(hw, vif);
5695 }
5696
rtl8723au_rx_parse_phystats(struct rtl8xxxu_priv * priv,struct ieee80211_rx_status * rx_status,struct rtl8723au_phy_stats * phy_stats,u32 rxmcs,struct ieee80211_hdr * hdr,bool crc_icv_err)5697 void rtl8723au_rx_parse_phystats(struct rtl8xxxu_priv *priv,
5698 struct ieee80211_rx_status *rx_status,
5699 struct rtl8723au_phy_stats *phy_stats,
5700 u32 rxmcs, struct ieee80211_hdr *hdr,
5701 bool crc_icv_err)
5702 {
5703 if (phy_stats->sgi_en)
5704 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
5705
5706 if (rxmcs < DESC_RATE_6M) {
5707 /*
5708 * Handle PHY stats for CCK rates
5709 */
5710 rx_status->signal = priv->fops->cck_rssi(priv, phy_stats);
5711 } else {
5712 bool parse_cfo = priv->fops->set_crystal_cap &&
5713 priv->vif &&
5714 priv->vif->type == NL80211_IFTYPE_STATION &&
5715 priv->vif->cfg.assoc &&
5716 !crc_icv_err &&
5717 !ieee80211_is_ctl(hdr->frame_control) &&
5718 ether_addr_equal(priv->vif->bss_conf.bssid, hdr->addr2);
5719
5720 if (parse_cfo) {
5721 priv->cfo_tracking.cfo_tail[0] = phy_stats->path_cfotail[0];
5722 priv->cfo_tracking.cfo_tail[1] = phy_stats->path_cfotail[1];
5723
5724 priv->cfo_tracking.packet_count++;
5725 }
5726
5727 rx_status->signal =
5728 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
5729 }
5730 }
5731
jaguar2_rx_parse_phystats_type0(struct rtl8xxxu_priv * priv,struct ieee80211_rx_status * rx_status,struct jaguar2_phy_stats_type0 * phy_stats0,u32 rxmcs,struct ieee80211_hdr * hdr,bool crc_icv_err)5732 static void jaguar2_rx_parse_phystats_type0(struct rtl8xxxu_priv *priv,
5733 struct ieee80211_rx_status *rx_status,
5734 struct jaguar2_phy_stats_type0 *phy_stats0,
5735 u32 rxmcs, struct ieee80211_hdr *hdr,
5736 bool crc_icv_err)
5737 {
5738 s8 rx_power = phy_stats0->pwdb - 110;
5739
5740 if (!priv->cck_new_agc)
5741 rx_power = priv->fops->cck_rssi(priv, (struct rtl8723au_phy_stats *)phy_stats0);
5742
5743 rx_status->signal = rx_power;
5744 }
5745
jaguar2_rx_parse_phystats_type1(struct rtl8xxxu_priv * priv,struct ieee80211_rx_status * rx_status,struct jaguar2_phy_stats_type1 * phy_stats1,u32 rxmcs,struct ieee80211_hdr * hdr,bool crc_icv_err)5746 static void jaguar2_rx_parse_phystats_type1(struct rtl8xxxu_priv *priv,
5747 struct ieee80211_rx_status *rx_status,
5748 struct jaguar2_phy_stats_type1 *phy_stats1,
5749 u32 rxmcs, struct ieee80211_hdr *hdr,
5750 bool crc_icv_err)
5751 {
5752 bool parse_cfo = priv->fops->set_crystal_cap &&
5753 priv->vif &&
5754 priv->vif->type == NL80211_IFTYPE_STATION &&
5755 priv->vif->cfg.assoc &&
5756 !crc_icv_err &&
5757 !ieee80211_is_ctl(hdr->frame_control) &&
5758 ether_addr_equal(priv->vif->bss_conf.bssid, hdr->addr2);
5759 u8 pwdb_max = 0;
5760 int rx_path;
5761
5762 if (parse_cfo) {
5763 /* Only path-A and path-B have CFO tail and short CFO */
5764 priv->cfo_tracking.cfo_tail[RF_A] = phy_stats1->cfo_tail[RF_A];
5765 priv->cfo_tracking.cfo_tail[RF_B] = phy_stats1->cfo_tail[RF_B];
5766
5767 priv->cfo_tracking.packet_count++;
5768 }
5769
5770 for (rx_path = 0; rx_path < priv->rx_paths; rx_path++)
5771 pwdb_max = max(pwdb_max, phy_stats1->pwdb[rx_path]);
5772
5773 rx_status->signal = pwdb_max - 110;
5774 }
5775
jaguar2_rx_parse_phystats_type2(struct rtl8xxxu_priv * priv,struct ieee80211_rx_status * rx_status,struct jaguar2_phy_stats_type2 * phy_stats2,u32 rxmcs,struct ieee80211_hdr * hdr,bool crc_icv_err)5776 static void jaguar2_rx_parse_phystats_type2(struct rtl8xxxu_priv *priv,
5777 struct ieee80211_rx_status *rx_status,
5778 struct jaguar2_phy_stats_type2 *phy_stats2,
5779 u32 rxmcs, struct ieee80211_hdr *hdr,
5780 bool crc_icv_err)
5781 {
5782 u8 pwdb_max = 0;
5783 int rx_path;
5784
5785 for (rx_path = 0; rx_path < priv->rx_paths; rx_path++)
5786 pwdb_max = max(pwdb_max, phy_stats2->pwdb[rx_path]);
5787
5788 rx_status->signal = pwdb_max - 110;
5789 }
5790
jaguar2_rx_parse_phystats(struct rtl8xxxu_priv * priv,struct ieee80211_rx_status * rx_status,struct rtl8723au_phy_stats * phy_stats,u32 rxmcs,struct ieee80211_hdr * hdr,bool crc_icv_err)5791 void jaguar2_rx_parse_phystats(struct rtl8xxxu_priv *priv,
5792 struct ieee80211_rx_status *rx_status,
5793 struct rtl8723au_phy_stats *phy_stats,
5794 u32 rxmcs, struct ieee80211_hdr *hdr,
5795 bool crc_icv_err)
5796 {
5797 struct jaguar2_phy_stats_type0 *phy_stats0 = (struct jaguar2_phy_stats_type0 *)phy_stats;
5798 struct jaguar2_phy_stats_type1 *phy_stats1 = (struct jaguar2_phy_stats_type1 *)phy_stats;
5799 struct jaguar2_phy_stats_type2 *phy_stats2 = (struct jaguar2_phy_stats_type2 *)phy_stats;
5800
5801 switch (phy_stats0->page_num) {
5802 case 0:
5803 /* CCK */
5804 jaguar2_rx_parse_phystats_type0(priv, rx_status, phy_stats0,
5805 rxmcs, hdr, crc_icv_err);
5806 break;
5807 case 1:
5808 /* OFDM */
5809 jaguar2_rx_parse_phystats_type1(priv, rx_status, phy_stats1,
5810 rxmcs, hdr, crc_icv_err);
5811 break;
5812 case 2:
5813 /* Also OFDM but different (how?) */
5814 jaguar2_rx_parse_phystats_type2(priv, rx_status, phy_stats2,
5815 rxmcs, hdr, crc_icv_err);
5816 break;
5817 default:
5818 return;
5819 }
5820 }
5821
rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv * priv)5822 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
5823 {
5824 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5825 unsigned long flags;
5826
5827 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5828
5829 list_for_each_entry_safe(rx_urb, tmp,
5830 &priv->rx_urb_pending_list, list) {
5831 list_del(&rx_urb->list);
5832 priv->rx_urb_pending_count--;
5833 usb_free_urb(&rx_urb->urb);
5834 }
5835
5836 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5837 }
5838
rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv * priv,struct rtl8xxxu_rx_urb * rx_urb)5839 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
5840 struct rtl8xxxu_rx_urb *rx_urb)
5841 {
5842 struct sk_buff *skb;
5843 unsigned long flags;
5844 int pending = 0;
5845
5846 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5847
5848 if (!priv->shutdown) {
5849 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
5850 priv->rx_urb_pending_count++;
5851 pending = priv->rx_urb_pending_count;
5852 } else {
5853 skb = (struct sk_buff *)rx_urb->urb.context;
5854 dev_kfree_skb_irq(skb);
5855 usb_free_urb(&rx_urb->urb);
5856 }
5857
5858 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5859
5860 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
5861 schedule_work(&priv->rx_urb_wq);
5862 }
5863
rtl8xxxu_rx_urb_work(struct work_struct * work)5864 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
5865 {
5866 struct rtl8xxxu_priv *priv;
5867 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5868 struct list_head local;
5869 struct sk_buff *skb;
5870 unsigned long flags;
5871 int ret;
5872
5873 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
5874 INIT_LIST_HEAD(&local);
5875
5876 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5877
5878 list_splice_init(&priv->rx_urb_pending_list, &local);
5879 priv->rx_urb_pending_count = 0;
5880
5881 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5882
5883 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
5884 list_del_init(&rx_urb->list);
5885 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5886 /*
5887 * If out of memory or temporary error, put it back on the
5888 * queue and try again. Otherwise the device is dead/gone
5889 * and we should drop it.
5890 */
5891 switch (ret) {
5892 case 0:
5893 break;
5894 case -ENOMEM:
5895 case -EAGAIN:
5896 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5897 break;
5898 default:
5899 dev_warn(&priv->udev->dev,
5900 "failed to requeue urb with error %i\n", ret);
5901 skb = (struct sk_buff *)rx_urb->urb.context;
5902 dev_kfree_skb(skb);
5903 usb_free_urb(&rx_urb->urb);
5904 }
5905 }
5906 }
5907
5908 /*
5909 * The RTL8723BU/RTL8192EU vendor driver use coexistence table type
5910 * 0-7 to represent writing different combinations of register values
5911 * to REG_BT_COEX_TABLEs. It's for different kinds of coexistence use
5912 * cases which Realtek doesn't provide detail for these settings. Keep
5913 * this aligned with vendor driver for easier maintenance.
5914 */
5915 static
rtl8723bu_set_coex_with_type(struct rtl8xxxu_priv * priv,u8 type)5916 void rtl8723bu_set_coex_with_type(struct rtl8xxxu_priv *priv, u8 type)
5917 {
5918 switch (type) {
5919 case 0:
5920 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
5921 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555);
5922 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5923 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5924 break;
5925 case 1:
5926 case 3:
5927 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
5928 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a);
5929 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5930 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5931 break;
5932 case 2:
5933 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a);
5934 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a);
5935 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5936 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5937 break;
5938 case 4:
5939 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a);
5940 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaa5a5a);
5941 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5942 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5943 break;
5944 case 5:
5945 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a);
5946 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaa5a5a5a);
5947 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5948 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5949 break;
5950 case 6:
5951 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
5952 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa);
5953 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5954 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5955 break;
5956 case 7:
5957 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0xaaaaaaaa);
5958 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa);
5959 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5960 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5961 break;
5962 default:
5963 break;
5964 }
5965 }
5966
5967 static
rtl8723bu_update_bt_link_info(struct rtl8xxxu_priv * priv,u8 bt_info)5968 void rtl8723bu_update_bt_link_info(struct rtl8xxxu_priv *priv, u8 bt_info)
5969 {
5970 struct rtl8xxxu_btcoex *btcoex = &priv->bt_coex;
5971
5972 if (bt_info & BT_INFO_8723B_1ANT_B_INQ_PAGE)
5973 btcoex->c2h_bt_inquiry = true;
5974 else
5975 btcoex->c2h_bt_inquiry = false;
5976
5977 if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION)) {
5978 btcoex->bt_status = BT_8723B_1ANT_STATUS_NON_CONNECTED_IDLE;
5979 btcoex->has_sco = false;
5980 btcoex->has_hid = false;
5981 btcoex->has_pan = false;
5982 btcoex->has_a2dp = false;
5983 } else {
5984 if ((bt_info & 0x1f) == BT_INFO_8723B_1ANT_B_CONNECTION)
5985 btcoex->bt_status = BT_8723B_1ANT_STATUS_CONNECTED_IDLE;
5986 else if ((bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) ||
5987 (bt_info & BT_INFO_8723B_1ANT_B_SCO_BUSY))
5988 btcoex->bt_status = BT_8723B_1ANT_STATUS_SCO_BUSY;
5989 else if (bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY)
5990 btcoex->bt_status = BT_8723B_1ANT_STATUS_ACL_BUSY;
5991 else
5992 btcoex->bt_status = BT_8723B_1ANT_STATUS_MAX;
5993
5994 if (bt_info & BT_INFO_8723B_1ANT_B_FTP)
5995 btcoex->has_pan = true;
5996 else
5997 btcoex->has_pan = false;
5998
5999 if (bt_info & BT_INFO_8723B_1ANT_B_A2DP)
6000 btcoex->has_a2dp = true;
6001 else
6002 btcoex->has_a2dp = false;
6003
6004 if (bt_info & BT_INFO_8723B_1ANT_B_HID)
6005 btcoex->has_hid = true;
6006 else
6007 btcoex->has_hid = false;
6008
6009 if (bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO)
6010 btcoex->has_sco = true;
6011 else
6012 btcoex->has_sco = false;
6013 }
6014
6015 if (!btcoex->has_a2dp && !btcoex->has_sco &&
6016 !btcoex->has_pan && btcoex->has_hid)
6017 btcoex->hid_only = true;
6018 else
6019 btcoex->hid_only = false;
6020
6021 if (!btcoex->has_sco && !btcoex->has_pan &&
6022 !btcoex->has_hid && btcoex->has_a2dp)
6023 btcoex->has_a2dp = true;
6024 else
6025 btcoex->has_a2dp = false;
6026
6027 if (btcoex->bt_status == BT_8723B_1ANT_STATUS_SCO_BUSY ||
6028 btcoex->bt_status == BT_8723B_1ANT_STATUS_ACL_BUSY)
6029 btcoex->bt_busy = true;
6030 else
6031 btcoex->bt_busy = false;
6032 }
6033
6034 static
rtl8723bu_handle_bt_inquiry(struct rtl8xxxu_priv * priv)6035 void rtl8723bu_handle_bt_inquiry(struct rtl8xxxu_priv *priv)
6036 {
6037 struct ieee80211_vif *vif;
6038 struct rtl8xxxu_btcoex *btcoex;
6039 bool wifi_connected;
6040
6041 vif = priv->vif;
6042 btcoex = &priv->bt_coex;
6043 wifi_connected = (vif && vif->cfg.assoc);
6044
6045 if (!wifi_connected) {
6046 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0);
6047 rtl8723bu_set_coex_with_type(priv, 0);
6048 } else if (btcoex->has_sco || btcoex->has_hid || btcoex->has_a2dp) {
6049 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 0x3, 0x11, 0x11);
6050 rtl8723bu_set_coex_with_type(priv, 4);
6051 } else if (btcoex->has_pan) {
6052 rtl8723bu_set_ps_tdma(priv, 0x61, 0x3f, 0x3, 0x11, 0x11);
6053 rtl8723bu_set_coex_with_type(priv, 4);
6054 } else {
6055 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0);
6056 rtl8723bu_set_coex_with_type(priv, 7);
6057 }
6058 }
6059
6060 static
rtl8723bu_handle_bt_info(struct rtl8xxxu_priv * priv)6061 void rtl8723bu_handle_bt_info(struct rtl8xxxu_priv *priv)
6062 {
6063 struct ieee80211_vif *vif;
6064 struct rtl8xxxu_btcoex *btcoex;
6065 bool wifi_connected;
6066
6067 vif = priv->vif;
6068 btcoex = &priv->bt_coex;
6069 wifi_connected = (vif && vif->cfg.assoc);
6070
6071 if (wifi_connected) {
6072 u32 val32 = 0;
6073 u32 high_prio_tx = 0, high_prio_rx = 0;
6074
6075 val32 = rtl8xxxu_read32(priv, 0x770);
6076 high_prio_tx = val32 & 0x0000ffff;
6077 high_prio_rx = (val32 & 0xffff0000) >> 16;
6078
6079 if (btcoex->bt_busy) {
6080 if (btcoex->hid_only) {
6081 rtl8723bu_set_ps_tdma(priv, 0x61, 0x20,
6082 0x3, 0x11, 0x11);
6083 rtl8723bu_set_coex_with_type(priv, 5);
6084 } else if (btcoex->a2dp_only) {
6085 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35,
6086 0x3, 0x11, 0x11);
6087 rtl8723bu_set_coex_with_type(priv, 4);
6088 } else if ((btcoex->has_a2dp && btcoex->has_pan) ||
6089 (btcoex->has_hid && btcoex->has_a2dp &&
6090 btcoex->has_pan)) {
6091 rtl8723bu_set_ps_tdma(priv, 0x51, 0x21,
6092 0x3, 0x10, 0x10);
6093 rtl8723bu_set_coex_with_type(priv, 4);
6094 } else if (btcoex->has_hid && btcoex->has_a2dp) {
6095 rtl8723bu_set_ps_tdma(priv, 0x51, 0x21,
6096 0x3, 0x10, 0x10);
6097 rtl8723bu_set_coex_with_type(priv, 3);
6098 } else {
6099 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35,
6100 0x3, 0x11, 0x11);
6101 rtl8723bu_set_coex_with_type(priv, 4);
6102 }
6103 } else {
6104 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0);
6105 if (high_prio_tx + high_prio_rx <= 60)
6106 rtl8723bu_set_coex_with_type(priv, 2);
6107 else
6108 rtl8723bu_set_coex_with_type(priv, 7);
6109 }
6110 } else {
6111 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0);
6112 rtl8723bu_set_coex_with_type(priv, 0);
6113 }
6114 }
6115
rtl8xxxu_c2hcmd_callback(struct work_struct * work)6116 static void rtl8xxxu_c2hcmd_callback(struct work_struct *work)
6117 {
6118 struct rtl8xxxu_priv *priv;
6119 struct rtl8723bu_c2h *c2h;
6120 struct sk_buff *skb = NULL;
6121 u8 bt_info = 0;
6122 struct rtl8xxxu_btcoex *btcoex;
6123 struct rtl8xxxu_ra_report *rarpt;
6124 u8 bw;
6125
6126 priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work);
6127 btcoex = &priv->bt_coex;
6128 rarpt = &priv->ra_report;
6129
6130 while (!skb_queue_empty(&priv->c2hcmd_queue)) {
6131 skb = skb_dequeue(&priv->c2hcmd_queue);
6132
6133 c2h = (struct rtl8723bu_c2h *)skb->data;
6134
6135 switch (c2h->id) {
6136 case C2H_8723B_BT_INFO:
6137 bt_info = c2h->bt_info.bt_info;
6138
6139 rtl8723bu_update_bt_link_info(priv, bt_info);
6140 if (btcoex->c2h_bt_inquiry) {
6141 rtl8723bu_handle_bt_inquiry(priv);
6142 break;
6143 }
6144 rtl8723bu_handle_bt_info(priv);
6145 break;
6146 case C2H_8723B_RA_REPORT:
6147 bw = rarpt->txrate.bw;
6148
6149 if (skb->len >= offsetofend(typeof(*c2h), ra_report.bw)) {
6150 if (c2h->ra_report.bw == RTL8XXXU_CHANNEL_WIDTH_40)
6151 bw = RATE_INFO_BW_40;
6152 else
6153 bw = RATE_INFO_BW_20;
6154 }
6155
6156 rtl8xxxu_update_ra_report(rarpt, c2h->ra_report.rate,
6157 c2h->ra_report.sgi, bw);
6158 break;
6159 default:
6160 break;
6161 }
6162
6163 dev_kfree_skb(skb);
6164 }
6165 }
6166
rtl8723bu_handle_c2h(struct rtl8xxxu_priv * priv,struct sk_buff * skb)6167 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv,
6168 struct sk_buff *skb)
6169 {
6170 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data;
6171 struct device *dev = &priv->udev->dev;
6172 int len;
6173
6174 len = skb->len - 2;
6175
6176 dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n",
6177 c2h->id, c2h->seq, len, c2h->bt_info.response_source);
6178
6179 switch(c2h->id) {
6180 case C2H_8723B_BT_INFO:
6181 if (c2h->bt_info.response_source >
6182 BT_INFO_SRC_8723B_BT_ACTIVE_SEND)
6183 dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n");
6184 else
6185 dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n");
6186
6187 if (c2h->bt_info.bt_has_reset)
6188 dev_dbg(dev, "BT has been reset\n");
6189 if (c2h->bt_info.tx_rx_mask)
6190 dev_dbg(dev, "BT TRx mask\n");
6191
6192 break;
6193 case C2H_8723B_BT_MP_INFO:
6194 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n",
6195 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status);
6196 break;
6197 case C2H_8723B_RA_REPORT:
6198 dev_dbg(dev,
6199 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n",
6200 c2h->ra_report.rate, c2h->ra_report.sgi,
6201 c2h->ra_report.macid, c2h->ra_report.noisy_state);
6202 break;
6203 default:
6204 dev_info(dev, "Unhandled C2H event %02x seq %02x\n",
6205 c2h->id, c2h->seq);
6206 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE,
6207 16, 1, c2h->raw.payload, len, false);
6208 break;
6209 }
6210
6211 skb_queue_tail(&priv->c2hcmd_queue, skb);
6212
6213 schedule_work(&priv->c2hcmd_work);
6214 }
6215
rtl8188e_c2hcmd_callback(struct work_struct * work)6216 static void rtl8188e_c2hcmd_callback(struct work_struct *work)
6217 {
6218 struct rtl8xxxu_priv *priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work);
6219 struct device *dev = &priv->udev->dev;
6220 struct sk_buff *skb = NULL;
6221 struct rtl8xxxu_rxdesc16 *rx_desc;
6222
6223 while (!skb_queue_empty(&priv->c2hcmd_queue)) {
6224 skb = skb_dequeue(&priv->c2hcmd_queue);
6225
6226 rx_desc = (struct rtl8xxxu_rxdesc16 *)(skb->data - sizeof(struct rtl8xxxu_rxdesc16));
6227
6228 switch (rx_desc->rpt_sel) {
6229 case 1:
6230 dev_dbg(dev, "C2H TX report type 1\n");
6231
6232 break;
6233 case 2:
6234 dev_dbg(dev, "C2H TX report type 2\n");
6235
6236 rtl8188e_handle_ra_tx_report2(priv, skb);
6237
6238 break;
6239 case 3:
6240 dev_dbg(dev, "C2H USB interrupt report\n");
6241
6242 break;
6243 default:
6244 dev_warn(dev, "%s: rpt_sel should not be %d\n",
6245 __func__, rx_desc->rpt_sel);
6246
6247 break;
6248 }
6249
6250 dev_kfree_skb(skb);
6251 }
6252 }
6253
rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv * priv,struct sk_buff * skb)6254 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb)
6255 {
6256 struct ieee80211_hw *hw = priv->hw;
6257 struct ieee80211_rx_status *rx_status;
6258 struct rtl8xxxu_rxdesc16 *rx_desc;
6259 struct rtl8723au_phy_stats *phy_stats;
6260 struct sk_buff *next_skb = NULL;
6261 __le32 *_rx_desc_le;
6262 u32 *_rx_desc;
6263 int drvinfo_sz, desc_shift;
6264 int i, pkt_cnt, pkt_len, urb_len, pkt_offset;
6265
6266 urb_len = skb->len;
6267 pkt_cnt = 0;
6268
6269 if (urb_len < sizeof(struct rtl8xxxu_rxdesc16)) {
6270 kfree_skb(skb);
6271 return RX_TYPE_ERROR;
6272 }
6273
6274 do {
6275 rx_desc = (struct rtl8xxxu_rxdesc16 *)skb->data;
6276 _rx_desc_le = (__le32 *)skb->data;
6277 _rx_desc = (u32 *)skb->data;
6278
6279 for (i = 0;
6280 i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++)
6281 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
6282
6283 /*
6284 * Only read pkt_cnt from the header if we're parsing the
6285 * first packet
6286 */
6287 if (!pkt_cnt)
6288 pkt_cnt = rx_desc->pkt_cnt;
6289 pkt_len = rx_desc->pktlen;
6290
6291 drvinfo_sz = rx_desc->drvinfo_sz * 8;
6292 desc_shift = rx_desc->shift;
6293 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift +
6294 sizeof(struct rtl8xxxu_rxdesc16), 128);
6295
6296 /*
6297 * Only clone the skb if there's enough data at the end to
6298 * at least cover the rx descriptor
6299 */
6300 if (pkt_cnt > 1 &&
6301 urb_len >= (pkt_offset + sizeof(struct rtl8xxxu_rxdesc16)))
6302 next_skb = skb_clone(skb, GFP_ATOMIC);
6303
6304 rx_status = IEEE80211_SKB_RXCB(skb);
6305 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
6306
6307 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16));
6308
6309 if (rx_desc->rpt_sel) {
6310 skb_queue_tail(&priv->c2hcmd_queue, skb);
6311 schedule_work(&priv->c2hcmd_work);
6312 } else {
6313 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
6314
6315 skb_pull(skb, drvinfo_sz + desc_shift);
6316
6317 skb_trim(skb, pkt_len);
6318
6319 if (rx_desc->phy_stats)
6320 priv->fops->parse_phystats(
6321 priv, rx_status, phy_stats,
6322 rx_desc->rxmcs,
6323 (struct ieee80211_hdr *)skb->data,
6324 rx_desc->crc32 || rx_desc->icverr);
6325
6326 rx_status->mactime = rx_desc->tsfl;
6327 rx_status->flag |= RX_FLAG_MACTIME_START;
6328
6329 if (!rx_desc->swdec &&
6330 rx_desc->security != RX_DESC_ENC_NONE)
6331 rx_status->flag |= RX_FLAG_DECRYPTED;
6332 if (rx_desc->crc32)
6333 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
6334 if (rx_desc->bw)
6335 rx_status->bw = RATE_INFO_BW_40;
6336
6337 if (rx_desc->rxht) {
6338 rx_status->encoding = RX_ENC_HT;
6339 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
6340 } else {
6341 rx_status->rate_idx = rx_desc->rxmcs;
6342 }
6343
6344 rx_status->freq = hw->conf.chandef.chan->center_freq;
6345 rx_status->band = hw->conf.chandef.chan->band;
6346
6347 ieee80211_rx_irqsafe(hw, skb);
6348 }
6349
6350 skb = next_skb;
6351 if (skb)
6352 skb_pull(next_skb, pkt_offset);
6353
6354 pkt_cnt--;
6355 urb_len -= pkt_offset;
6356 next_skb = NULL;
6357 } while (skb && pkt_cnt > 0 &&
6358 urb_len >= sizeof(struct rtl8xxxu_rxdesc16));
6359
6360 return RX_TYPE_DATA_PKT;
6361 }
6362
rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv * priv,struct sk_buff * skb)6363 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb)
6364 {
6365 struct ieee80211_hw *hw = priv->hw;
6366 struct ieee80211_rx_status *rx_status;
6367 struct rtl8xxxu_rxdesc24 *rx_desc;
6368 struct rtl8723au_phy_stats *phy_stats;
6369 struct sk_buff *next_skb = NULL;
6370 __le32 *_rx_desc_le;
6371 u32 *_rx_desc;
6372 int drvinfo_sz, desc_shift;
6373 int i, pkt_len, urb_len, pkt_offset;
6374
6375 urb_len = skb->len;
6376
6377 if (urb_len < sizeof(struct rtl8xxxu_rxdesc24)) {
6378 kfree_skb(skb);
6379 return RX_TYPE_ERROR;
6380 }
6381
6382 do {
6383 rx_desc = (struct rtl8xxxu_rxdesc24 *)skb->data;
6384 _rx_desc_le = (__le32 *)skb->data;
6385 _rx_desc = (u32 *)skb->data;
6386
6387 for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++)
6388 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
6389
6390 pkt_len = rx_desc->pktlen;
6391
6392 drvinfo_sz = rx_desc->drvinfo_sz * 8;
6393 desc_shift = rx_desc->shift;
6394 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift +
6395 sizeof(struct rtl8xxxu_rxdesc24), 8);
6396
6397 /*
6398 * Only clone the skb if there's enough data at the end to
6399 * at least cover the rx descriptor
6400 */
6401 if (urb_len >= (pkt_offset + sizeof(struct rtl8xxxu_rxdesc24)))
6402 next_skb = skb_clone(skb, GFP_ATOMIC);
6403
6404 rx_status = IEEE80211_SKB_RXCB(skb);
6405 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
6406
6407 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24));
6408
6409 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
6410
6411 skb_pull(skb, drvinfo_sz + desc_shift);
6412
6413 skb_trim(skb, pkt_len);
6414
6415 if (rx_desc->rpt_sel) {
6416 struct device *dev = &priv->udev->dev;
6417 dev_dbg(dev, "%s: C2H packet\n", __func__);
6418 rtl8723bu_handle_c2h(priv, skb);
6419 } else {
6420 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
6421
6422 if (rx_desc->phy_stats)
6423 priv->fops->parse_phystats(priv, rx_status, phy_stats,
6424 rx_desc->rxmcs, hdr,
6425 rx_desc->crc32 || rx_desc->icverr);
6426
6427 rx_status->mactime = rx_desc->tsfl;
6428 rx_status->flag |= RX_FLAG_MACTIME_START;
6429
6430 if (!rx_desc->swdec &&
6431 rx_desc->security != RX_DESC_ENC_NONE)
6432 rx_status->flag |= RX_FLAG_DECRYPTED;
6433 if (rx_desc->crc32)
6434 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
6435 if (rx_desc->bw)
6436 rx_status->bw = RATE_INFO_BW_40;
6437
6438 if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
6439 rx_status->encoding = RX_ENC_HT;
6440 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
6441 } else {
6442 rx_status->rate_idx = rx_desc->rxmcs;
6443 }
6444
6445 rx_status->freq = hw->conf.chandef.chan->center_freq;
6446 rx_status->band = hw->conf.chandef.chan->band;
6447
6448 ieee80211_rx_irqsafe(hw, skb);
6449 }
6450
6451 skb = next_skb;
6452 if (skb)
6453 skb_pull(next_skb, pkt_offset);
6454
6455 urb_len -= pkt_offset;
6456 next_skb = NULL;
6457 } while (skb && urb_len >= sizeof(struct rtl8xxxu_rxdesc24));
6458
6459 return RX_TYPE_DATA_PKT;
6460 }
6461
rtl8xxxu_rx_complete(struct urb * urb)6462 static void rtl8xxxu_rx_complete(struct urb *urb)
6463 {
6464 struct rtl8xxxu_rx_urb *rx_urb =
6465 container_of(urb, struct rtl8xxxu_rx_urb, urb);
6466 struct ieee80211_hw *hw = rx_urb->hw;
6467 struct rtl8xxxu_priv *priv = hw->priv;
6468 struct sk_buff *skb = (struct sk_buff *)urb->context;
6469 struct device *dev = &priv->udev->dev;
6470
6471 skb_put(skb, urb->actual_length);
6472
6473 if (urb->status == 0) {
6474 priv->fops->parse_rx_desc(priv, skb);
6475
6476 skb = NULL;
6477 rx_urb->urb.context = NULL;
6478 rtl8xxxu_queue_rx_urb(priv, rx_urb);
6479 } else {
6480 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
6481 goto cleanup;
6482 }
6483 return;
6484
6485 cleanup:
6486 usb_free_urb(urb);
6487 dev_kfree_skb(skb);
6488 }
6489
rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv * priv,struct rtl8xxxu_rx_urb * rx_urb)6490 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
6491 struct rtl8xxxu_rx_urb *rx_urb)
6492 {
6493 struct rtl8xxxu_fileops *fops = priv->fops;
6494 struct sk_buff *skb;
6495 int skb_size;
6496 int ret, rx_desc_sz;
6497
6498 rx_desc_sz = fops->rx_desc_size;
6499
6500 if (priv->rx_buf_aggregation && fops->rx_agg_buf_size) {
6501 skb_size = fops->rx_agg_buf_size;
6502 skb_size += (rx_desc_sz + sizeof(struct rtl8723au_phy_stats));
6503 } else {
6504 skb_size = IEEE80211_MAX_FRAME_LEN;
6505 }
6506
6507 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
6508 if (!skb)
6509 return -ENOMEM;
6510
6511 memset(skb->data, 0, rx_desc_sz);
6512 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
6513 skb_size, rtl8xxxu_rx_complete, skb);
6514 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
6515 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
6516 if (ret)
6517 usb_unanchor_urb(&rx_urb->urb);
6518 return ret;
6519 }
6520
rtl8xxxu_int_complete(struct urb * urb)6521 static void rtl8xxxu_int_complete(struct urb *urb)
6522 {
6523 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
6524 struct device *dev = &priv->udev->dev;
6525 int ret;
6526
6527 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_INTERRUPT)
6528 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
6529 if (urb->status == 0) {
6530 usb_anchor_urb(urb, &priv->int_anchor);
6531 ret = usb_submit_urb(urb, GFP_ATOMIC);
6532 if (ret)
6533 usb_unanchor_urb(urb);
6534 } else {
6535 dev_dbg(dev, "%s: Error %i\n", __func__, urb->status);
6536 }
6537 }
6538
6539
rtl8xxxu_submit_int_urb(struct ieee80211_hw * hw)6540 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
6541 {
6542 struct rtl8xxxu_priv *priv = hw->priv;
6543 struct urb *urb;
6544 u32 val32;
6545 int ret;
6546
6547 urb = usb_alloc_urb(0, GFP_KERNEL);
6548 if (!urb)
6549 return -ENOMEM;
6550
6551 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
6552 priv->int_buf, USB_INTR_CONTENT_LENGTH,
6553 rtl8xxxu_int_complete, priv, 1);
6554 usb_anchor_urb(urb, &priv->int_anchor);
6555 ret = usb_submit_urb(urb, GFP_KERNEL);
6556 if (ret) {
6557 usb_unanchor_urb(urb);
6558 goto error;
6559 }
6560
6561 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
6562 val32 |= USB_HIMR_CPWM;
6563 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
6564
6565 error:
6566 usb_free_urb(urb);
6567 return ret;
6568 }
6569
rtl8xxxu_add_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)6570 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
6571 struct ieee80211_vif *vif)
6572 {
6573 struct rtl8xxxu_priv *priv = hw->priv;
6574 int ret;
6575 u8 val8;
6576
6577 if (!priv->vif)
6578 priv->vif = vif;
6579 else
6580 return -EOPNOTSUPP;
6581
6582 switch (vif->type) {
6583 case NL80211_IFTYPE_STATION:
6584 rtl8xxxu_stop_tx_beacon(priv);
6585
6586 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6587 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
6588 BEACON_DISABLE_TSF_UPDATE;
6589 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6590 ret = 0;
6591 break;
6592 case NL80211_IFTYPE_AP:
6593 rtl8xxxu_write8(priv, REG_BEACON_CTRL,
6594 BEACON_DISABLE_TSF_UPDATE | BEACON_CTRL_MBSSID);
6595 rtl8xxxu_write8(priv, REG_ATIMWND, 0x0c); /* 12ms */
6596 rtl8xxxu_write16(priv, REG_TSFTR_SYN_OFFSET, 0x7fff); /* ~32ms */
6597 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, DUAL_TSF_RESET_TSF0);
6598
6599 /* enable BCN0 function */
6600 rtl8xxxu_write8(priv, REG_BEACON_CTRL,
6601 BEACON_DISABLE_TSF_UPDATE |
6602 BEACON_FUNCTION_ENABLE | BEACON_CTRL_MBSSID |
6603 BEACON_CTRL_TX_BEACON_RPT);
6604
6605 /* select BCN on port 0 */
6606 val8 = rtl8xxxu_read8(priv, REG_CCK_CHECK);
6607 val8 &= ~BIT_BCN_PORT_SEL;
6608 rtl8xxxu_write8(priv, REG_CCK_CHECK, val8);
6609
6610 ret = 0;
6611 break;
6612 default:
6613 ret = -EOPNOTSUPP;
6614 }
6615
6616 rtl8xxxu_set_linktype(priv, vif->type);
6617 ether_addr_copy(priv->mac_addr, vif->addr);
6618 rtl8xxxu_set_mac(priv);
6619
6620 return ret;
6621 }
6622
rtl8xxxu_remove_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)6623 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
6624 struct ieee80211_vif *vif)
6625 {
6626 struct rtl8xxxu_priv *priv = hw->priv;
6627
6628 dev_dbg(&priv->udev->dev, "%s\n", __func__);
6629
6630 if (priv->vif)
6631 priv->vif = NULL;
6632 }
6633
rtl8xxxu_config(struct ieee80211_hw * hw,u32 changed)6634 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
6635 {
6636 struct rtl8xxxu_priv *priv = hw->priv;
6637 struct device *dev = &priv->udev->dev;
6638 int ret = 0, channel;
6639 bool ht40;
6640
6641 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
6642 dev_info(dev,
6643 "%s: channel: %i (changed %08x chandef.width %02x)\n",
6644 __func__, hw->conf.chandef.chan->hw_value,
6645 changed, hw->conf.chandef.width);
6646
6647 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
6648 switch (hw->conf.chandef.width) {
6649 case NL80211_CHAN_WIDTH_20_NOHT:
6650 case NL80211_CHAN_WIDTH_20:
6651 ht40 = false;
6652 break;
6653 case NL80211_CHAN_WIDTH_40:
6654 ht40 = true;
6655 break;
6656 default:
6657 ret = -ENOTSUPP;
6658 goto exit;
6659 }
6660
6661 channel = hw->conf.chandef.chan->hw_value;
6662
6663 priv->fops->set_tx_power(priv, channel, ht40);
6664
6665 priv->fops->config_channel(hw);
6666 }
6667
6668 exit:
6669 return ret;
6670 }
6671
rtl8xxxu_conf_tx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,unsigned int link_id,u16 queue,const struct ieee80211_tx_queue_params * param)6672 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
6673 struct ieee80211_vif *vif,
6674 unsigned int link_id, u16 queue,
6675 const struct ieee80211_tx_queue_params *param)
6676 {
6677 struct rtl8xxxu_priv *priv = hw->priv;
6678 struct device *dev = &priv->udev->dev;
6679 u32 val32;
6680 u8 aifs, acm_ctrl, acm_bit;
6681
6682 aifs = param->aifs;
6683
6684 val32 = aifs |
6685 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
6686 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
6687 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
6688
6689 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
6690 dev_dbg(dev,
6691 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
6692 __func__, queue, val32, param->acm, acm_ctrl);
6693
6694 switch (queue) {
6695 case IEEE80211_AC_VO:
6696 acm_bit = ACM_HW_CTRL_VO;
6697 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
6698 break;
6699 case IEEE80211_AC_VI:
6700 acm_bit = ACM_HW_CTRL_VI;
6701 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
6702 break;
6703 case IEEE80211_AC_BE:
6704 acm_bit = ACM_HW_CTRL_BE;
6705 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
6706 break;
6707 case IEEE80211_AC_BK:
6708 acm_bit = ACM_HW_CTRL_BK;
6709 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
6710 break;
6711 default:
6712 acm_bit = 0;
6713 break;
6714 }
6715
6716 if (param->acm)
6717 acm_ctrl |= acm_bit;
6718 else
6719 acm_ctrl &= ~acm_bit;
6720 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
6721
6722 return 0;
6723 }
6724
rtl8xxxu_configure_filter(struct ieee80211_hw * hw,unsigned int changed_flags,unsigned int * total_flags,u64 multicast)6725 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
6726 unsigned int changed_flags,
6727 unsigned int *total_flags, u64 multicast)
6728 {
6729 struct rtl8xxxu_priv *priv = hw->priv;
6730 u32 rcr = priv->regrcr;
6731
6732 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
6733 __func__, changed_flags, *total_flags);
6734
6735 /*
6736 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
6737 */
6738
6739 if (*total_flags & FIF_FCSFAIL)
6740 rcr |= RCR_ACCEPT_CRC32;
6741 else
6742 rcr &= ~RCR_ACCEPT_CRC32;
6743
6744 /*
6745 * FIF_PLCPFAIL not supported?
6746 */
6747
6748 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
6749 rcr &= ~(RCR_CHECK_BSSID_BEACON | RCR_CHECK_BSSID_MATCH);
6750 else
6751 rcr |= RCR_CHECK_BSSID_BEACON | RCR_CHECK_BSSID_MATCH;
6752
6753 if (priv->vif && priv->vif->type == NL80211_IFTYPE_AP)
6754 rcr &= ~RCR_CHECK_BSSID_MATCH;
6755
6756 if (*total_flags & FIF_CONTROL)
6757 rcr |= RCR_ACCEPT_CTRL_FRAME;
6758 else
6759 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
6760
6761 if (*total_flags & FIF_OTHER_BSS)
6762 rcr |= RCR_ACCEPT_AP;
6763 else
6764 rcr &= ~RCR_ACCEPT_AP;
6765
6766 if (*total_flags & FIF_PSPOLL)
6767 rcr |= RCR_ACCEPT_PM;
6768 else
6769 rcr &= ~RCR_ACCEPT_PM;
6770
6771 /*
6772 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
6773 */
6774
6775 rtl8xxxu_write32(priv, REG_RCR, rcr);
6776 priv->regrcr = rcr;
6777
6778 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
6779 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
6780 FIF_PROBE_REQ);
6781 }
6782
rtl8xxxu_set_rts_threshold(struct ieee80211_hw * hw,u32 rts)6783 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
6784 {
6785 if (rts > 2347 && rts != (u32)-1)
6786 return -EINVAL;
6787
6788 return 0;
6789 }
6790
rtl8xxxu_set_key(struct ieee80211_hw * hw,enum set_key_cmd cmd,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ieee80211_key_conf * key)6791 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
6792 struct ieee80211_vif *vif,
6793 struct ieee80211_sta *sta,
6794 struct ieee80211_key_conf *key)
6795 {
6796 struct rtl8xxxu_priv *priv = hw->priv;
6797 struct device *dev = &priv->udev->dev;
6798 u8 mac_addr[ETH_ALEN];
6799 u8 val8;
6800 u16 val16;
6801 u32 val32;
6802 int retval = -EOPNOTSUPP;
6803
6804 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
6805 __func__, cmd, key->cipher, key->keyidx);
6806
6807 if (vif->type != NL80211_IFTYPE_STATION)
6808 return -EOPNOTSUPP;
6809
6810 if (key->keyidx > 3)
6811 return -EOPNOTSUPP;
6812
6813 switch (key->cipher) {
6814 case WLAN_CIPHER_SUITE_WEP40:
6815 case WLAN_CIPHER_SUITE_WEP104:
6816
6817 break;
6818 case WLAN_CIPHER_SUITE_CCMP:
6819 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
6820 break;
6821 case WLAN_CIPHER_SUITE_TKIP:
6822 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
6823 break;
6824 default:
6825 return -EOPNOTSUPP;
6826 }
6827
6828 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
6829 dev_dbg(dev, "%s: pairwise key\n", __func__);
6830 ether_addr_copy(mac_addr, sta->addr);
6831 } else {
6832 dev_dbg(dev, "%s: group key\n", __func__);
6833 eth_broadcast_addr(mac_addr);
6834 }
6835
6836 val16 = rtl8xxxu_read16(priv, REG_CR);
6837 val16 |= CR_SECURITY_ENABLE;
6838 rtl8xxxu_write16(priv, REG_CR, val16);
6839
6840 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
6841 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
6842 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
6843 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
6844
6845 switch (cmd) {
6846 case SET_KEY:
6847 key->hw_key_idx = key->keyidx;
6848 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
6849 rtl8xxxu_cam_write(priv, key, mac_addr);
6850 retval = 0;
6851 break;
6852 case DISABLE_KEY:
6853 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
6854 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
6855 key->keyidx << CAM_CMD_KEY_SHIFT;
6856 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
6857 retval = 0;
6858 break;
6859 default:
6860 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
6861 }
6862
6863 return retval;
6864 }
6865
6866 static int
rtl8xxxu_ampdu_action(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_ampdu_params * params)6867 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6868 struct ieee80211_ampdu_params *params)
6869 {
6870 struct rtl8xxxu_priv *priv = hw->priv;
6871 struct device *dev = &priv->udev->dev;
6872 u8 ampdu_factor, ampdu_density;
6873 struct ieee80211_sta *sta = params->sta;
6874 u16 tid = params->tid;
6875 enum ieee80211_ampdu_mlme_action action = params->action;
6876
6877 switch (action) {
6878 case IEEE80211_AMPDU_TX_START:
6879 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
6880 ampdu_factor = sta->deflink.ht_cap.ampdu_factor;
6881 ampdu_density = sta->deflink.ht_cap.ampdu_density;
6882 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
6883 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
6884 dev_dbg(dev,
6885 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
6886 ampdu_factor, ampdu_density);
6887 return IEEE80211_AMPDU_TX_START_IMMEDIATE;
6888 case IEEE80211_AMPDU_TX_STOP_CONT:
6889 case IEEE80211_AMPDU_TX_STOP_FLUSH:
6890 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
6891 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP\n", __func__);
6892 rtl8xxxu_set_ampdu_factor(priv, 0);
6893 rtl8xxxu_set_ampdu_min_space(priv, 0);
6894 clear_bit(tid, priv->tx_aggr_started);
6895 clear_bit(tid, priv->tid_tx_operational);
6896 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6897 break;
6898 case IEEE80211_AMPDU_TX_OPERATIONAL:
6899 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_OPERATIONAL\n", __func__);
6900 set_bit(tid, priv->tid_tx_operational);
6901 break;
6902 case IEEE80211_AMPDU_RX_START:
6903 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
6904 break;
6905 case IEEE80211_AMPDU_RX_STOP:
6906 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
6907 break;
6908 default:
6909 break;
6910 }
6911 return 0;
6912 }
6913
6914 static void
rtl8xxxu_sta_statistics(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct station_info * sinfo)6915 rtl8xxxu_sta_statistics(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6916 struct ieee80211_sta *sta, struct station_info *sinfo)
6917 {
6918 struct rtl8xxxu_priv *priv = hw->priv;
6919
6920 sinfo->txrate = priv->ra_report.txrate;
6921 sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
6922 }
6923
rtl8xxxu_signal_to_snr(int signal)6924 static u8 rtl8xxxu_signal_to_snr(int signal)
6925 {
6926 if (signal < RTL8XXXU_NOISE_FLOOR_MIN)
6927 signal = RTL8XXXU_NOISE_FLOOR_MIN;
6928 else if (signal > 0)
6929 signal = 0;
6930 return (u8)(signal - RTL8XXXU_NOISE_FLOOR_MIN);
6931 }
6932
rtl8xxxu_refresh_rate_mask(struct rtl8xxxu_priv * priv,int signal,struct ieee80211_sta * sta,bool force)6933 static void rtl8xxxu_refresh_rate_mask(struct rtl8xxxu_priv *priv,
6934 int signal, struct ieee80211_sta *sta,
6935 bool force)
6936 {
6937 struct ieee80211_hw *hw = priv->hw;
6938 u16 wireless_mode;
6939 u8 rssi_level, ratr_idx;
6940 u8 txbw_40mhz;
6941 u8 snr, snr_thresh_high, snr_thresh_low;
6942 u8 go_up_gap = 5;
6943 u8 macid = rtl8xxxu_get_macid(priv, sta);
6944
6945 rssi_level = priv->rssi_level;
6946 snr = rtl8xxxu_signal_to_snr(signal);
6947 snr_thresh_high = RTL8XXXU_SNR_THRESH_HIGH;
6948 snr_thresh_low = RTL8XXXU_SNR_THRESH_LOW;
6949 txbw_40mhz = (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) ? 1 : 0;
6950
6951 switch (rssi_level) {
6952 case RTL8XXXU_RATR_STA_MID:
6953 snr_thresh_high += go_up_gap;
6954 break;
6955 case RTL8XXXU_RATR_STA_LOW:
6956 snr_thresh_high += go_up_gap;
6957 snr_thresh_low += go_up_gap;
6958 break;
6959 default:
6960 break;
6961 }
6962
6963 if (snr > snr_thresh_high)
6964 rssi_level = RTL8XXXU_RATR_STA_HIGH;
6965 else if (snr > snr_thresh_low)
6966 rssi_level = RTL8XXXU_RATR_STA_MID;
6967 else
6968 rssi_level = RTL8XXXU_RATR_STA_LOW;
6969
6970 if (rssi_level != priv->rssi_level || force) {
6971 int sgi = 0;
6972 u32 rate_bitmap = 0;
6973
6974 rcu_read_lock();
6975 rate_bitmap = (sta->deflink.supp_rates[0] & 0xfff) |
6976 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12) |
6977 (sta->deflink.ht_cap.mcs.rx_mask[1] << 20);
6978 if (sta->deflink.ht_cap.cap &
6979 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
6980 sgi = 1;
6981 rcu_read_unlock();
6982
6983 wireless_mode = rtl8xxxu_wireless_mode(hw, sta);
6984 switch (wireless_mode) {
6985 case WIRELESS_MODE_B:
6986 ratr_idx = RATEID_IDX_B;
6987 if (rate_bitmap & 0x0000000c)
6988 rate_bitmap &= 0x0000000d;
6989 else
6990 rate_bitmap &= 0x0000000f;
6991 break;
6992 case WIRELESS_MODE_A:
6993 case WIRELESS_MODE_G:
6994 ratr_idx = RATEID_IDX_G;
6995 if (rssi_level == RTL8XXXU_RATR_STA_HIGH)
6996 rate_bitmap &= 0x00000f00;
6997 else
6998 rate_bitmap &= 0x00000ff0;
6999 break;
7000 case (WIRELESS_MODE_B | WIRELESS_MODE_G):
7001 ratr_idx = RATEID_IDX_BG;
7002 if (rssi_level == RTL8XXXU_RATR_STA_HIGH)
7003 rate_bitmap &= 0x00000f00;
7004 else if (rssi_level == RTL8XXXU_RATR_STA_MID)
7005 rate_bitmap &= 0x00000ff0;
7006 else
7007 rate_bitmap &= 0x00000ff5;
7008 break;
7009 case WIRELESS_MODE_N_24G:
7010 case WIRELESS_MODE_N_5G:
7011 case (WIRELESS_MODE_G | WIRELESS_MODE_N_24G):
7012 case (WIRELESS_MODE_A | WIRELESS_MODE_N_5G):
7013 if (priv->tx_paths == 2 && priv->rx_paths == 2)
7014 ratr_idx = RATEID_IDX_GN_N2SS;
7015 else
7016 ratr_idx = RATEID_IDX_GN_N1SS;
7017 break;
7018 case (WIRELESS_MODE_B | WIRELESS_MODE_G | WIRELESS_MODE_N_24G):
7019 case (WIRELESS_MODE_B | WIRELESS_MODE_N_24G):
7020 if (txbw_40mhz) {
7021 if (priv->tx_paths == 2 && priv->rx_paths == 2)
7022 ratr_idx = RATEID_IDX_BGN_40M_2SS;
7023 else
7024 ratr_idx = RATEID_IDX_BGN_40M_1SS;
7025 } else {
7026 if (priv->tx_paths == 2 && priv->rx_paths == 2)
7027 ratr_idx = RATEID_IDX_BGN_20M_2SS_BN;
7028 else
7029 ratr_idx = RATEID_IDX_BGN_20M_1SS_BN;
7030 }
7031
7032 if (priv->tx_paths == 2 && priv->rx_paths == 2) {
7033 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) {
7034 rate_bitmap &= 0x0f8f0000;
7035 } else if (rssi_level == RTL8XXXU_RATR_STA_MID) {
7036 rate_bitmap &= 0x0f8ff000;
7037 } else {
7038 if (txbw_40mhz)
7039 rate_bitmap &= 0x0f8ff015;
7040 else
7041 rate_bitmap &= 0x0f8ff005;
7042 }
7043 } else {
7044 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) {
7045 rate_bitmap &= 0x000f0000;
7046 } else if (rssi_level == RTL8XXXU_RATR_STA_MID) {
7047 rate_bitmap &= 0x000ff000;
7048 } else {
7049 if (txbw_40mhz)
7050 rate_bitmap &= 0x000ff015;
7051 else
7052 rate_bitmap &= 0x000ff005;
7053 }
7054 }
7055 break;
7056 default:
7057 ratr_idx = RATEID_IDX_BGN_40M_2SS;
7058 rate_bitmap &= 0x0fffffff;
7059 break;
7060 }
7061
7062 priv->rssi_level = rssi_level;
7063 priv->fops->update_rate_mask(priv, rate_bitmap, ratr_idx, sgi, txbw_40mhz, macid);
7064 }
7065 }
7066
rtl8xxxu_set_atc_status(struct rtl8xxxu_priv * priv,bool atc_status)7067 static void rtl8xxxu_set_atc_status(struct rtl8xxxu_priv *priv, bool atc_status)
7068 {
7069 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking;
7070 u32 val32;
7071
7072 if (atc_status == cfo->atc_status)
7073 return;
7074
7075 cfo->atc_status = atc_status;
7076
7077 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING);
7078 if (atc_status)
7079 val32 |= CFO_TRACKING_ATC_STATUS;
7080 else
7081 val32 &= ~CFO_TRACKING_ATC_STATUS;
7082 rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32);
7083 }
7084
7085 /* Central frequency offset correction */
rtl8xxxu_track_cfo(struct rtl8xxxu_priv * priv)7086 static void rtl8xxxu_track_cfo(struct rtl8xxxu_priv *priv)
7087 {
7088 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking;
7089 int cfo_khz_a, cfo_khz_b, cfo_average;
7090 int crystal_cap;
7091
7092 if (!priv->vif || !priv->vif->cfg.assoc) {
7093 /* Reset */
7094 cfo->adjust = true;
7095
7096 if (cfo->crystal_cap > priv->default_crystal_cap)
7097 priv->fops->set_crystal_cap(priv, cfo->crystal_cap - 1);
7098 else if (cfo->crystal_cap < priv->default_crystal_cap)
7099 priv->fops->set_crystal_cap(priv, cfo->crystal_cap + 1);
7100
7101 rtl8xxxu_set_atc_status(priv, true);
7102
7103 return;
7104 }
7105
7106 if (cfo->packet_count == cfo->packet_count_pre)
7107 /* No new information. */
7108 return;
7109
7110 cfo->packet_count_pre = cfo->packet_count;
7111
7112 /* CFO_tail[1:0] is S(8,7), (num_subcarrier>>7) x 312.5K = CFO value(K Hz) */
7113 cfo_khz_a = (int)((cfo->cfo_tail[0] * 3125) / 10) >> 7;
7114 cfo_khz_b = (int)((cfo->cfo_tail[1] * 3125) / 10) >> 7;
7115
7116 if (priv->tx_paths == 1)
7117 cfo_average = cfo_khz_a;
7118 else
7119 cfo_average = (cfo_khz_a + cfo_khz_b) / 2;
7120
7121 dev_dbg(&priv->udev->dev, "cfo_average: %d\n", cfo_average);
7122
7123 if (cfo->adjust) {
7124 if (abs(cfo_average) < CFO_TH_XTAL_LOW)
7125 cfo->adjust = false;
7126 } else {
7127 if (abs(cfo_average) > CFO_TH_XTAL_HIGH)
7128 cfo->adjust = true;
7129 }
7130
7131 /*
7132 * TODO: We should return here only if bluetooth is enabled.
7133 * See the vendor drivers for how to determine that.
7134 */
7135 if (priv->has_bluetooth)
7136 return;
7137
7138 if (!cfo->adjust)
7139 return;
7140
7141 crystal_cap = cfo->crystal_cap;
7142
7143 if (cfo_average > CFO_TH_XTAL_LOW)
7144 crystal_cap++;
7145 else if (cfo_average < -CFO_TH_XTAL_LOW)
7146 crystal_cap--;
7147
7148 crystal_cap = clamp(crystal_cap, 0, 0x3f);
7149
7150 priv->fops->set_crystal_cap(priv, crystal_cap);
7151
7152 rtl8xxxu_set_atc_status(priv, abs(cfo_average) >= CFO_TH_ATC);
7153 }
7154
rtl8xxxu_watchdog_callback(struct work_struct * work)7155 static void rtl8xxxu_watchdog_callback(struct work_struct *work)
7156 {
7157 struct ieee80211_vif *vif;
7158 struct rtl8xxxu_priv *priv;
7159
7160 priv = container_of(work, struct rtl8xxxu_priv, ra_watchdog.work);
7161 vif = priv->vif;
7162
7163 if (vif && vif->type == NL80211_IFTYPE_STATION) {
7164 int signal;
7165 struct ieee80211_sta *sta;
7166
7167 rcu_read_lock();
7168 sta = ieee80211_find_sta(vif, vif->bss_conf.bssid);
7169 if (!sta) {
7170 struct device *dev = &priv->udev->dev;
7171
7172 dev_dbg(dev, "%s: no sta found\n", __func__);
7173 rcu_read_unlock();
7174 goto out;
7175 }
7176 rcu_read_unlock();
7177
7178 signal = ieee80211_ave_rssi(vif);
7179
7180 priv->fops->report_rssi(priv, 0,
7181 rtl8xxxu_signal_to_snr(signal));
7182
7183 if (priv->fops->set_crystal_cap)
7184 rtl8xxxu_track_cfo(priv);
7185
7186 rtl8xxxu_refresh_rate_mask(priv, signal, sta, false);
7187 }
7188
7189 out:
7190 schedule_delayed_work(&priv->ra_watchdog, 2 * HZ);
7191 }
7192
rtl8xxxu_start(struct ieee80211_hw * hw)7193 static int rtl8xxxu_start(struct ieee80211_hw *hw)
7194 {
7195 struct rtl8xxxu_priv *priv = hw->priv;
7196 struct rtl8xxxu_rx_urb *rx_urb;
7197 struct rtl8xxxu_tx_urb *tx_urb;
7198 struct sk_buff *skb;
7199 unsigned long flags;
7200 int ret, i;
7201
7202 ret = 0;
7203
7204 init_usb_anchor(&priv->rx_anchor);
7205 init_usb_anchor(&priv->tx_anchor);
7206 init_usb_anchor(&priv->int_anchor);
7207
7208 priv->fops->enable_rf(priv);
7209 if (priv->usb_interrupts) {
7210 ret = rtl8xxxu_submit_int_urb(hw);
7211 if (ret)
7212 goto exit;
7213 }
7214
7215 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
7216 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
7217 if (!tx_urb) {
7218 if (!i)
7219 ret = -ENOMEM;
7220
7221 goto error_out;
7222 }
7223 usb_init_urb(&tx_urb->urb);
7224 INIT_LIST_HEAD(&tx_urb->list);
7225 tx_urb->hw = hw;
7226 list_add(&tx_urb->list, &priv->tx_urb_free_list);
7227 priv->tx_urb_free_count++;
7228 }
7229
7230 priv->tx_stopped = false;
7231
7232 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7233 priv->shutdown = false;
7234 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7235
7236 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
7237 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
7238 if (!rx_urb) {
7239 if (!i)
7240 ret = -ENOMEM;
7241
7242 goto error_out;
7243 }
7244 usb_init_urb(&rx_urb->urb);
7245 INIT_LIST_HEAD(&rx_urb->list);
7246 rx_urb->hw = hw;
7247
7248 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
7249 if (ret) {
7250 if (ret != -ENOMEM) {
7251 skb = (struct sk_buff *)rx_urb->urb.context;
7252 dev_kfree_skb(skb);
7253 }
7254 rtl8xxxu_queue_rx_urb(priv, rx_urb);
7255 }
7256 }
7257
7258 schedule_delayed_work(&priv->ra_watchdog, 2 * HZ);
7259 exit:
7260 /*
7261 * Accept all data and mgmt frames
7262 */
7263 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
7264 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
7265
7266 rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1,
7267 OFDM0_X_AGC_CORE1_IGI_MASK, 0x1e);
7268
7269 return ret;
7270
7271 error_out:
7272 rtl8xxxu_free_tx_resources(priv);
7273 /*
7274 * Disable all data and mgmt frames
7275 */
7276 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7277 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7278
7279 return ret;
7280 }
7281
rtl8xxxu_stop(struct ieee80211_hw * hw)7282 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
7283 {
7284 struct rtl8xxxu_priv *priv = hw->priv;
7285 unsigned long flags;
7286
7287 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
7288
7289 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7290 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7291
7292 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7293 priv->shutdown = true;
7294 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7295
7296 usb_kill_anchored_urbs(&priv->rx_anchor);
7297 usb_kill_anchored_urbs(&priv->tx_anchor);
7298 if (priv->usb_interrupts)
7299 usb_kill_anchored_urbs(&priv->int_anchor);
7300
7301 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
7302
7303 priv->fops->disable_rf(priv);
7304
7305 /*
7306 * Disable interrupts
7307 */
7308 if (priv->usb_interrupts)
7309 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
7310
7311 cancel_work_sync(&priv->c2hcmd_work);
7312 cancel_delayed_work_sync(&priv->ra_watchdog);
7313
7314 rtl8xxxu_free_rx_resources(priv);
7315 rtl8xxxu_free_tx_resources(priv);
7316 }
7317
rtl8xxxu_sta_add(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)7318 static int rtl8xxxu_sta_add(struct ieee80211_hw *hw,
7319 struct ieee80211_vif *vif,
7320 struct ieee80211_sta *sta)
7321 {
7322 struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;
7323 struct rtl8xxxu_priv *priv = hw->priv;
7324
7325 if (vif->type == NL80211_IFTYPE_AP) {
7326 sta_info->macid = rtl8xxxu_acquire_macid(priv);
7327 if (sta_info->macid >= RTL8XXXU_MAX_MAC_ID_NUM)
7328 return -ENOSPC;
7329
7330 rtl8xxxu_refresh_rate_mask(priv, 0, sta, true);
7331 priv->fops->report_connect(priv, sta_info->macid, H2C_MACID_ROLE_STA, true);
7332 }
7333
7334 return 0;
7335 }
7336
rtl8xxxu_sta_remove(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)7337 static int rtl8xxxu_sta_remove(struct ieee80211_hw *hw,
7338 struct ieee80211_vif *vif,
7339 struct ieee80211_sta *sta)
7340 {
7341 struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;
7342 struct rtl8xxxu_priv *priv = hw->priv;
7343
7344 if (vif->type == NL80211_IFTYPE_AP)
7345 rtl8xxxu_release_macid(priv, sta_info->macid);
7346
7347 return 0;
7348 }
7349
7350 static const struct ieee80211_ops rtl8xxxu_ops = {
7351 .tx = rtl8xxxu_tx,
7352 .wake_tx_queue = ieee80211_handle_wake_tx_queue,
7353 .add_interface = rtl8xxxu_add_interface,
7354 .remove_interface = rtl8xxxu_remove_interface,
7355 .config = rtl8xxxu_config,
7356 .conf_tx = rtl8xxxu_conf_tx,
7357 .bss_info_changed = rtl8xxxu_bss_info_changed,
7358 .start_ap = rtl8xxxu_start_ap,
7359 .configure_filter = rtl8xxxu_configure_filter,
7360 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
7361 .start = rtl8xxxu_start,
7362 .stop = rtl8xxxu_stop,
7363 .sw_scan_start = rtl8xxxu_sw_scan_start,
7364 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
7365 .set_key = rtl8xxxu_set_key,
7366 .ampdu_action = rtl8xxxu_ampdu_action,
7367 .sta_statistics = rtl8xxxu_sta_statistics,
7368 .get_antenna = rtl8xxxu_get_antenna,
7369 .set_tim = rtl8xxxu_set_tim,
7370 .sta_add = rtl8xxxu_sta_add,
7371 .sta_remove = rtl8xxxu_sta_remove,
7372 };
7373
rtl8xxxu_parse_usb(struct rtl8xxxu_priv * priv,struct usb_interface * interface)7374 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
7375 struct usb_interface *interface)
7376 {
7377 struct usb_interface_descriptor *interface_desc;
7378 struct usb_host_interface *host_interface;
7379 struct usb_endpoint_descriptor *endpoint;
7380 struct device *dev = &priv->udev->dev;
7381 int i, j = 0, endpoints;
7382 u8 dir, xtype, num;
7383 int ret = 0;
7384
7385 host_interface = interface->cur_altsetting;
7386 interface_desc = &host_interface->desc;
7387 endpoints = interface_desc->bNumEndpoints;
7388
7389 for (i = 0; i < endpoints; i++) {
7390 endpoint = &host_interface->endpoint[i].desc;
7391
7392 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
7393 num = usb_endpoint_num(endpoint);
7394 xtype = usb_endpoint_type(endpoint);
7395 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7396 dev_dbg(dev,
7397 "%s: endpoint: dir %02x, # %02x, type %02x\n",
7398 __func__, dir, num, xtype);
7399 if (usb_endpoint_dir_in(endpoint) &&
7400 usb_endpoint_xfer_bulk(endpoint)) {
7401 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7402 dev_dbg(dev, "%s: in endpoint num %i\n",
7403 __func__, num);
7404
7405 if (priv->pipe_in) {
7406 dev_warn(dev,
7407 "%s: Too many IN pipes\n", __func__);
7408 ret = -EINVAL;
7409 goto exit;
7410 }
7411
7412 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
7413 }
7414
7415 if (usb_endpoint_dir_in(endpoint) &&
7416 usb_endpoint_xfer_int(endpoint)) {
7417 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7418 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
7419 __func__, num);
7420
7421 if (priv->pipe_interrupt) {
7422 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
7423 __func__);
7424 ret = -EINVAL;
7425 goto exit;
7426 }
7427
7428 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
7429 }
7430
7431 if (usb_endpoint_dir_out(endpoint) &&
7432 usb_endpoint_xfer_bulk(endpoint)) {
7433 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7434 dev_dbg(dev, "%s: out endpoint num %i\n",
7435 __func__, num);
7436 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
7437 dev_warn(dev,
7438 "%s: Too many OUT pipes\n", __func__);
7439 ret = -EINVAL;
7440 goto exit;
7441 }
7442 priv->out_ep[j++] = num;
7443 }
7444 }
7445 exit:
7446 priv->nr_out_eps = j;
7447 return ret;
7448 }
7449
rtl8xxxu_init_led(struct rtl8xxxu_priv * priv)7450 static void rtl8xxxu_init_led(struct rtl8xxxu_priv *priv)
7451 {
7452 struct led_classdev *led = &priv->led_cdev;
7453
7454 if (!priv->fops->led_classdev_brightness_set)
7455 return;
7456
7457 led->brightness_set_blocking = priv->fops->led_classdev_brightness_set;
7458
7459 snprintf(priv->led_name, sizeof(priv->led_name),
7460 "rtl8xxxu-usb%s", dev_name(&priv->udev->dev));
7461 led->name = priv->led_name;
7462 led->max_brightness = RTL8XXXU_HW_LED_CONTROL;
7463
7464 if (led_classdev_register(&priv->udev->dev, led))
7465 return;
7466
7467 priv->led_registered = true;
7468
7469 led->brightness = led->max_brightness;
7470 priv->fops->led_classdev_brightness_set(led, led->brightness);
7471 }
7472
rtl8xxxu_deinit_led(struct rtl8xxxu_priv * priv)7473 static void rtl8xxxu_deinit_led(struct rtl8xxxu_priv *priv)
7474 {
7475 struct led_classdev *led = &priv->led_cdev;
7476
7477 if (!priv->led_registered)
7478 return;
7479
7480 priv->fops->led_classdev_brightness_set(led, LED_OFF);
7481 led_classdev_unregister(led);
7482 }
7483
rtl8xxxu_probe(struct usb_interface * interface,const struct usb_device_id * id)7484 static int rtl8xxxu_probe(struct usb_interface *interface,
7485 const struct usb_device_id *id)
7486 {
7487 struct rtl8xxxu_priv *priv;
7488 struct ieee80211_hw *hw;
7489 struct usb_device *udev;
7490 struct ieee80211_supported_band *sband;
7491 int ret;
7492 int untested = 1;
7493
7494 udev = usb_get_dev(interface_to_usbdev(interface));
7495
7496 switch (id->idVendor) {
7497 case USB_VENDOR_ID_REALTEK:
7498 switch(id->idProduct) {
7499 case 0x1724:
7500 case 0x8176:
7501 case 0x8178:
7502 case 0x817f:
7503 case 0x818b:
7504 case 0xf179:
7505 case 0x8179:
7506 case 0xb711:
7507 case 0xf192:
7508 untested = 0;
7509 break;
7510 }
7511 break;
7512 case 0x7392:
7513 if (id->idProduct == 0x7811 || id->idProduct == 0xa611 || id->idProduct == 0xb811)
7514 untested = 0;
7515 break;
7516 case 0x050d:
7517 if (id->idProduct == 0x1004)
7518 untested = 0;
7519 break;
7520 case 0x20f4:
7521 if (id->idProduct == 0x648b)
7522 untested = 0;
7523 break;
7524 case 0x2001:
7525 if (id->idProduct == 0x3308)
7526 untested = 0;
7527 break;
7528 case 0x2357:
7529 if (id->idProduct == 0x0109)
7530 untested = 0;
7531 break;
7532 case 0x0b05:
7533 if (id->idProduct == 0x18f1)
7534 untested = 0;
7535 break;
7536 default:
7537 break;
7538 }
7539
7540 if (untested) {
7541 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
7542 dev_info(&udev->dev,
7543 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
7544 id->idVendor, id->idProduct);
7545 dev_info(&udev->dev,
7546 "Please report results to Jes.Sorensen@gmail.com\n");
7547 }
7548
7549 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
7550 if (!hw) {
7551 ret = -ENOMEM;
7552 goto err_put_dev;
7553 }
7554
7555 priv = hw->priv;
7556 priv->hw = hw;
7557 priv->udev = udev;
7558 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
7559 mutex_init(&priv->usb_buf_mutex);
7560 mutex_init(&priv->syson_indirect_access_mutex);
7561 mutex_init(&priv->h2c_mutex);
7562 INIT_LIST_HEAD(&priv->tx_urb_free_list);
7563 spin_lock_init(&priv->tx_urb_lock);
7564 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
7565 spin_lock_init(&priv->rx_urb_lock);
7566 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
7567 INIT_DELAYED_WORK(&priv->ra_watchdog, rtl8xxxu_watchdog_callback);
7568 INIT_WORK(&priv->update_beacon_work, rtl8xxxu_update_beacon_work_callback);
7569 skb_queue_head_init(&priv->c2hcmd_queue);
7570
7571 usb_set_intfdata(interface, hw);
7572
7573 ret = rtl8xxxu_parse_usb(priv, interface);
7574 if (ret)
7575 goto err_set_intfdata;
7576
7577 ret = priv->fops->identify_chip(priv);
7578 if (ret) {
7579 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
7580 goto err_set_intfdata;
7581 }
7582
7583 hw->wiphy->available_antennas_tx = BIT(priv->tx_paths) - 1;
7584 hw->wiphy->available_antennas_rx = BIT(priv->rx_paths) - 1;
7585
7586 if (priv->rtl_chip == RTL8188E)
7587 INIT_WORK(&priv->c2hcmd_work, rtl8188e_c2hcmd_callback);
7588 else
7589 INIT_WORK(&priv->c2hcmd_work, rtl8xxxu_c2hcmd_callback);
7590
7591 ret = priv->fops->read_efuse(priv);
7592 if (ret) {
7593 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
7594 goto err_set_intfdata;
7595 }
7596
7597 ret = priv->fops->parse_efuse(priv);
7598 if (ret) {
7599 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
7600 goto err_set_intfdata;
7601 }
7602
7603 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE)
7604 rtl8xxxu_dump_efuse(priv);
7605
7606 rtl8xxxu_print_chipinfo(priv);
7607
7608 ret = priv->fops->load_firmware(priv);
7609 if (ret) {
7610 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
7611 goto err_set_intfdata;
7612 }
7613
7614 ret = rtl8xxxu_init_device(hw);
7615 if (ret)
7616 goto err_set_intfdata;
7617
7618 hw->wiphy->max_scan_ssids = 1;
7619 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
7620 if (priv->fops->max_macid_num)
7621 hw->wiphy->max_ap_assoc_sta = priv->fops->max_macid_num - 1;
7622 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
7623 if (priv->fops->supports_ap)
7624 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
7625 hw->queues = 4;
7626
7627 sband = &rtl8xxxu_supported_band;
7628 sband->ht_cap.ht_supported = true;
7629 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
7630 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
7631 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
7632 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
7633 sband->ht_cap.mcs.rx_mask[0] = 0xff;
7634 sband->ht_cap.mcs.rx_mask[4] = 0x01;
7635 if (priv->rf_paths > 1) {
7636 sband->ht_cap.mcs.rx_mask[1] = 0xff;
7637 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
7638 }
7639 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
7640 /*
7641 * Some APs will negotiate HT20_40 in a noisy environment leading
7642 * to miserable performance. Rather than defaulting to this, only
7643 * enable it if explicitly requested at module load time.
7644 */
7645 if (rtl8xxxu_ht40_2g) {
7646 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
7647 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
7648 }
7649 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
7650
7651 hw->wiphy->rts_threshold = 2347;
7652
7653 SET_IEEE80211_DEV(priv->hw, &interface->dev);
7654 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
7655
7656 hw->extra_tx_headroom = priv->fops->tx_desc_size;
7657 ieee80211_hw_set(hw, SIGNAL_DBM);
7658
7659 /*
7660 * The firmware handles rate control, except for RTL8188EU,
7661 * where we handle the rate control in the driver.
7662 */
7663 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
7664 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
7665 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
7666 ieee80211_hw_set(hw, MFP_CAPABLE);
7667
7668 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
7669
7670 ret = ieee80211_register_hw(priv->hw);
7671 if (ret) {
7672 dev_err(&udev->dev, "%s: Failed to register: %i\n",
7673 __func__, ret);
7674 goto err_set_intfdata;
7675 }
7676
7677 rtl8xxxu_init_led(priv);
7678
7679 return 0;
7680
7681 err_set_intfdata:
7682 usb_set_intfdata(interface, NULL);
7683
7684 kfree(priv->fw_data);
7685 mutex_destroy(&priv->usb_buf_mutex);
7686 mutex_destroy(&priv->syson_indirect_access_mutex);
7687 mutex_destroy(&priv->h2c_mutex);
7688
7689 ieee80211_free_hw(hw);
7690 err_put_dev:
7691 usb_put_dev(udev);
7692
7693 return ret;
7694 }
7695
rtl8xxxu_disconnect(struct usb_interface * interface)7696 static void rtl8xxxu_disconnect(struct usb_interface *interface)
7697 {
7698 struct rtl8xxxu_priv *priv;
7699 struct ieee80211_hw *hw;
7700
7701 hw = usb_get_intfdata(interface);
7702 priv = hw->priv;
7703
7704 rtl8xxxu_deinit_led(priv);
7705
7706 ieee80211_unregister_hw(hw);
7707
7708 priv->fops->power_off(priv);
7709
7710 usb_set_intfdata(interface, NULL);
7711
7712 dev_info(&priv->udev->dev, "disconnecting\n");
7713
7714 kfree(priv->fw_data);
7715 mutex_destroy(&priv->usb_buf_mutex);
7716 mutex_destroy(&priv->syson_indirect_access_mutex);
7717 mutex_destroy(&priv->h2c_mutex);
7718
7719 if (priv->udev->state != USB_STATE_NOTATTACHED) {
7720 dev_info(&priv->udev->dev,
7721 "Device still attached, trying to reset\n");
7722 usb_reset_device(priv->udev);
7723 }
7724 usb_put_dev(priv->udev);
7725 ieee80211_free_hw(hw);
7726 }
7727
7728 static const struct usb_device_id dev_table[] = {
7729 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
7730 .driver_info = (unsigned long)&rtl8723au_fops},
7731 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
7732 .driver_info = (unsigned long)&rtl8723au_fops},
7733 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
7734 .driver_info = (unsigned long)&rtl8723au_fops},
7735 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
7736 .driver_info = (unsigned long)&rtl8192eu_fops},
7737 /* TP-Link TL-WN822N v4 */
7738 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0108, 0xff, 0xff, 0xff),
7739 .driver_info = (unsigned long)&rtl8192eu_fops},
7740 /* D-Link DWA-131 rev E1, tested by David Patiño */
7741 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3319, 0xff, 0xff, 0xff),
7742 .driver_info = (unsigned long)&rtl8192eu_fops},
7743 /* Tested by Myckel Habets */
7744 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0109, 0xff, 0xff, 0xff),
7745 .driver_info = (unsigned long)&rtl8192eu_fops},
7746 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
7747 .driver_info = (unsigned long)&rtl8723bu_fops},
7748 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xa611, 0xff, 0xff, 0xff),
7749 .driver_info = (unsigned long)&rtl8723bu_fops},
7750 /* RTL8188FU */
7751 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf179, 0xff, 0xff, 0xff),
7752 .driver_info = (unsigned long)&rtl8188fu_fops},
7753 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8179, 0xff, 0xff, 0xff),
7754 .driver_info = (unsigned long)&rtl8188eu_fops},
7755 /* Tested by Hans de Goede - rtl8188etv */
7756 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0179, 0xff, 0xff, 0xff),
7757 .driver_info = (unsigned long)&rtl8188eu_fops},
7758 /* Sitecom rtl8188eus */
7759 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0076, 0xff, 0xff, 0xff),
7760 .driver_info = (unsigned long)&rtl8188eu_fops},
7761 /* D-Link USB-GO-N150 */
7762 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3311, 0xff, 0xff, 0xff),
7763 .driver_info = (unsigned long)&rtl8188eu_fops},
7764 /* D-Link DWA-125 REV D1 */
7765 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330f, 0xff, 0xff, 0xff),
7766 .driver_info = (unsigned long)&rtl8188eu_fops},
7767 /* D-Link DWA-123 REV D1 */
7768 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3310, 0xff, 0xff, 0xff),
7769 .driver_info = (unsigned long)&rtl8188eu_fops},
7770 /* D-Link DWA-121 rev B1 */
7771 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x331b, 0xff, 0xff, 0xff),
7772 .driver_info = (unsigned long)&rtl8188eu_fops},
7773 /* Abocom - Abocom */
7774 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8179, 0xff, 0xff, 0xff),
7775 .driver_info = (unsigned long)&rtl8188eu_fops},
7776 /* Elecom WDC-150SU2M */
7777 {USB_DEVICE_AND_INTERFACE_INFO(0x056e, 0x4008, 0xff, 0xff, 0xff),
7778 .driver_info = (unsigned long)&rtl8188eu_fops},
7779 /* TP-Link TL-WN722N v2 */
7780 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x010c, 0xff, 0xff, 0xff),
7781 .driver_info = (unsigned long)&rtl8188eu_fops},
7782 /* TP-Link TL-WN727N v5.21 */
7783 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0111, 0xff, 0xff, 0xff),
7784 .driver_info = (unsigned long)&rtl8188eu_fops},
7785 /* MERCUSYS MW150US v2 */
7786 {USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0102, 0xff, 0xff, 0xff),
7787 .driver_info = (unsigned long)&rtl8188eu_fops},
7788 /* ASUS USB-N10 Nano B1 */
7789 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x18f0, 0xff, 0xff, 0xff),
7790 .driver_info = (unsigned long)&rtl8188eu_fops},
7791 /* Edimax EW-7811Un V2 */
7792 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xb811, 0xff, 0xff, 0xff),
7793 .driver_info = (unsigned long)&rtl8188eu_fops},
7794 /* Rosewill USB-N150 Nano */
7795 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xffef, 0xff, 0xff, 0xff),
7796 .driver_info = (unsigned long)&rtl8188eu_fops},
7797 /* RTL8710BU aka RTL8188GU (not to be confused with RTL8188GTVU) */
7798 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb711, 0xff, 0xff, 0xff),
7799 .driver_info = (unsigned long)&rtl8710bu_fops},
7800 /* TOTOLINK N150UA V5 / N150UA-B */
7801 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2005, 0xff, 0xff, 0xff),
7802 .driver_info = (unsigned long)&rtl8710bu_fops},
7803 /* Comfast CF-826F */
7804 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf192, 0xff, 0xff, 0xff),
7805 .driver_info = (unsigned long)&rtl8192fu_fops},
7806 /* Asus USB-N13 rev C1 */
7807 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x18f1, 0xff, 0xff, 0xff),
7808 .driver_info = (unsigned long)&rtl8192fu_fops},
7809 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xb722, 0xff, 0xff, 0xff),
7810 .driver_info = (unsigned long)&rtl8192fu_fops},
7811 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x318b, 0xff, 0xff, 0xff),
7812 .driver_info = (unsigned long)&rtl8192fu_fops},
7813 #ifdef CONFIG_RTL8XXXU_UNTESTED
7814 /* Still supported by rtlwifi */
7815 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
7816 .driver_info = (unsigned long)&rtl8192cu_fops},
7817 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
7818 .driver_info = (unsigned long)&rtl8192cu_fops},
7819 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
7820 .driver_info = (unsigned long)&rtl8192cu_fops},
7821 /* Tested by Larry Finger */
7822 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
7823 .driver_info = (unsigned long)&rtl8192cu_fops},
7824 /* Tested by Andrea Merello */
7825 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
7826 .driver_info = (unsigned long)&rtl8192cu_fops},
7827 /* Tested by Jocelyn Mayer */
7828 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
7829 .driver_info = (unsigned long)&rtl8192cu_fops},
7830 /* Tested by Stefano Bravi */
7831 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
7832 .driver_info = (unsigned long)&rtl8192cu_fops},
7833 /* Currently untested 8188 series devices */
7834 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x018a, 0xff, 0xff, 0xff),
7835 .driver_info = (unsigned long)&rtl8192cu_fops},
7836 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
7837 .driver_info = (unsigned long)&rtl8192cu_fops},
7838 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
7839 .driver_info = (unsigned long)&rtl8192cu_fops},
7840 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
7841 .driver_info = (unsigned long)&rtl8192cu_fops},
7842 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
7843 .driver_info = (unsigned long)&rtl8192cu_fops},
7844 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
7845 .driver_info = (unsigned long)&rtl8192cu_fops},
7846 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
7847 .driver_info = (unsigned long)&rtl8192cu_fops},
7848 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
7849 .driver_info = (unsigned long)&rtl8192cu_fops},
7850 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
7851 .driver_info = (unsigned long)&rtl8192cu_fops},
7852 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
7853 .driver_info = (unsigned long)&rtl8192cu_fops},
7854 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
7855 .driver_info = (unsigned long)&rtl8192cu_fops},
7856 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
7857 .driver_info = (unsigned long)&rtl8192cu_fops},
7858 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
7859 .driver_info = (unsigned long)&rtl8192cu_fops},
7860 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
7861 .driver_info = (unsigned long)&rtl8192cu_fops},
7862 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
7863 .driver_info = (unsigned long)&rtl8192cu_fops},
7864 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
7865 .driver_info = (unsigned long)&rtl8192cu_fops},
7866 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
7867 .driver_info = (unsigned long)&rtl8192cu_fops},
7868 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
7869 .driver_info = (unsigned long)&rtl8192cu_fops},
7870 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
7871 .driver_info = (unsigned long)&rtl8192cu_fops},
7872 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
7873 .driver_info = (unsigned long)&rtl8192cu_fops},
7874 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
7875 .driver_info = (unsigned long)&rtl8192cu_fops},
7876 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
7877 .driver_info = (unsigned long)&rtl8192cu_fops},
7878 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
7879 .driver_info = (unsigned long)&rtl8192cu_fops},
7880 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
7881 .driver_info = (unsigned long)&rtl8192cu_fops},
7882 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
7883 .driver_info = (unsigned long)&rtl8192cu_fops},
7884 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
7885 .driver_info = (unsigned long)&rtl8192cu_fops},
7886 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
7887 .driver_info = (unsigned long)&rtl8192cu_fops},
7888 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
7889 .driver_info = (unsigned long)&rtl8192cu_fops},
7890 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
7891 .driver_info = (unsigned long)&rtl8192cu_fops},
7892 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
7893 .driver_info = (unsigned long)&rtl8192cu_fops},
7894 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
7895 .driver_info = (unsigned long)&rtl8192cu_fops},
7896 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
7897 .driver_info = (unsigned long)&rtl8192cu_fops},
7898 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
7899 .driver_info = (unsigned long)&rtl8192cu_fops},
7900 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
7901 .driver_info = (unsigned long)&rtl8192cu_fops},
7902 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
7903 .driver_info = (unsigned long)&rtl8192cu_fops},
7904 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
7905 .driver_info = (unsigned long)&rtl8192cu_fops},
7906 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
7907 .driver_info = (unsigned long)&rtl8192cu_fops},
7908 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
7909 .driver_info = (unsigned long)&rtl8192cu_fops},
7910 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
7911 .driver_info = (unsigned long)&rtl8192cu_fops},
7912 /* Currently untested 8192 series devices */
7913 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
7914 .driver_info = (unsigned long)&rtl8192cu_fops},
7915 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
7916 .driver_info = (unsigned long)&rtl8192cu_fops},
7917 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
7918 .driver_info = (unsigned long)&rtl8192cu_fops},
7919 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
7920 .driver_info = (unsigned long)&rtl8192cu_fops},
7921 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
7922 .driver_info = (unsigned long)&rtl8192cu_fops},
7923 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
7924 .driver_info = (unsigned long)&rtl8192cu_fops},
7925 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
7926 .driver_info = (unsigned long)&rtl8192cu_fops},
7927 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
7928 .driver_info = (unsigned long)&rtl8192cu_fops},
7929 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
7930 .driver_info = (unsigned long)&rtl8192cu_fops},
7931 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
7932 .driver_info = (unsigned long)&rtl8192cu_fops},
7933 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
7934 .driver_info = (unsigned long)&rtl8192cu_fops},
7935 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
7936 .driver_info = (unsigned long)&rtl8192cu_fops},
7937 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
7938 .driver_info = (unsigned long)&rtl8192cu_fops},
7939 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
7940 .driver_info = (unsigned long)&rtl8192cu_fops},
7941 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
7942 .driver_info = (unsigned long)&rtl8192cu_fops},
7943 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
7944 .driver_info = (unsigned long)&rtl8192cu_fops},
7945 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
7946 .driver_info = (unsigned long)&rtl8192cu_fops},
7947 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
7948 .driver_info = (unsigned long)&rtl8192cu_fops},
7949 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
7950 .driver_info = (unsigned long)&rtl8192cu_fops},
7951 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
7952 .driver_info = (unsigned long)&rtl8192cu_fops},
7953 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
7954 .driver_info = (unsigned long)&rtl8192cu_fops},
7955 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
7956 .driver_info = (unsigned long)&rtl8192cu_fops},
7957 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
7958 .driver_info = (unsigned long)&rtl8192cu_fops},
7959 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
7960 .driver_info = (unsigned long)&rtl8192cu_fops},
7961 /* found in rtl8192eu vendor driver */
7962 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0107, 0xff, 0xff, 0xff),
7963 .driver_info = (unsigned long)&rtl8192eu_fops},
7964 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab33, 0xff, 0xff, 0xff),
7965 .driver_info = (unsigned long)&rtl8192eu_fops},
7966 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818c, 0xff, 0xff, 0xff),
7967 .driver_info = (unsigned long)&rtl8192eu_fops},
7968 /* D-Link DWA-131 rev C1 */
7969 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3312, 0xff, 0xff, 0xff),
7970 .driver_info = (unsigned long)&rtl8192eu_fops},
7971 /* TP-Link TL-WN8200ND V2 */
7972 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0126, 0xff, 0xff, 0xff),
7973 .driver_info = (unsigned long)&rtl8192eu_fops},
7974 /* Mercusys MW300UM */
7975 {USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0100, 0xff, 0xff, 0xff),
7976 .driver_info = (unsigned long)&rtl8192eu_fops},
7977 /* Mercusys MW300UH */
7978 {USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0104, 0xff, 0xff, 0xff),
7979 .driver_info = (unsigned long)&rtl8192eu_fops},
7980 #endif
7981 { }
7982 };
7983
7984 static struct usb_driver rtl8xxxu_driver = {
7985 .name = DRIVER_NAME,
7986 .probe = rtl8xxxu_probe,
7987 .disconnect = rtl8xxxu_disconnect,
7988 .id_table = dev_table,
7989 .no_dynamic_id = 1,
7990 .disable_hub_initiated_lpm = 1,
7991 };
7992
7993 MODULE_DEVICE_TABLE(usb, dev_table);
7994
7995 module_usb_driver(rtl8xxxu_driver);
7996