1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
4 */
5 #include <common.h>
6 #include <clk.h>
7 #include <dm.h>
8 #include <ram.h>
9 #include <syscon.h>
10 #include <asm/io.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/periph.h>
13 #include <asm/arch/grf_rk3128.h>
14 #include <asm/arch/boot_mode.h>
15 #include <asm/arch/timer.h>
16 #include <power/regulator.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
rk_board_late_init(void)20 __weak int rk_board_late_init(void)
21 {
22 return 0;
23 }
24
board_late_init(void)25 int board_late_init(void)
26 {
27 setup_boot_mode();
28
29 return rk_board_late_init();
30 }
31
board_init(void)32 int board_init(void)
33 {
34 int ret = 0;
35
36 rockchip_timer_init();
37
38 ret = regulators_enable_boot_on(false);
39 if (ret) {
40 debug("%s: Cannot enable boot on regulator\n", __func__);
41 return ret;
42 }
43
44 return 0;
45 }
46
dram_init_banksize(void)47 int dram_init_banksize(void)
48 {
49 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
50 gd->bd->bi_dram[0].size = 0x8400000;
51 /* Reserve 0xe00000(14MB) for OPTEE with TA enabled, otherwise 2MB */
52 gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
53 + gd->bd->bi_dram[0].size + 0xe00000;
54 gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
55 + gd->ram_size - gd->bd->bi_dram[1].start;
56
57 return 0;
58 }
59
60 #ifndef CONFIG_SYS_DCACHE_OFF
enable_caches(void)61 void enable_caches(void)
62 {
63 /* Enable D-cache. I-cache is already enabled in start.S */
64 dcache_enable();
65 }
66 #endif
67
68 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
69 #include <usb.h>
70 #include <usb/dwc2_udc.h>
71
72 static struct dwc2_plat_otg_data rk3128_otg_data = {
73 .rx_fifo_sz = 512,
74 .np_tx_fifo_sz = 16,
75 .tx_fifo_sz = 128,
76 };
77
board_usb_init(int index,enum usb_init_type init)78 int board_usb_init(int index, enum usb_init_type init)
79 {
80 int node;
81 const char *mode;
82 bool matched = false;
83 const void *blob = gd->fdt_blob;
84
85 /* find the usb_otg node */
86 node = fdt_node_offset_by_compatible(blob, -1,
87 "rockchip,rk3128-usb");
88
89 while (node > 0) {
90 mode = fdt_getprop(blob, node, "dr_mode", NULL);
91 if (mode && strcmp(mode, "otg") == 0) {
92 matched = true;
93 break;
94 }
95
96 node = fdt_node_offset_by_compatible(blob, node,
97 "rockchip,rk3128-usb");
98 }
99 if (!matched) {
100 debug("Not found usb_otg device\n");
101 return -ENODEV;
102 }
103 rk3128_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
104
105 return dwc2_udc_probe(&rk3128_otg_data);
106 }
107
board_usb_cleanup(int index,enum usb_init_type init)108 int board_usb_cleanup(int index, enum usb_init_type init)
109 {
110 return 0;
111 }
112 #endif
113
114 #if CONFIG_IS_ENABLED(FASTBOOT)
fastboot_set_reboot_flag(void)115 int fastboot_set_reboot_flag(void)
116 {
117 struct rk3128_grf *grf;
118
119 printf("Setting reboot to fastboot flag ...\n");
120 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
121 /* Set boot mode to fastboot */
122 writel(BOOT_FASTBOOT, &grf->os_reg[0]);
123
124 return 0;
125 }
126 #endif
127