1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2017 SiFive
4 */
5
6 #include <linux/acpi.h>
7 #include <linux/cpu.h>
8 #include <linux/of.h>
9 #include <asm/cacheinfo.h>
10
11 static struct riscv_cacheinfo_ops *rv_cache_ops;
12
riscv_set_cacheinfo_ops(struct riscv_cacheinfo_ops * ops)13 void riscv_set_cacheinfo_ops(struct riscv_cacheinfo_ops *ops)
14 {
15 rv_cache_ops = ops;
16 }
17 EXPORT_SYMBOL_GPL(riscv_set_cacheinfo_ops);
18
19 const struct attribute_group *
cache_get_priv_group(struct cacheinfo * this_leaf)20 cache_get_priv_group(struct cacheinfo *this_leaf)
21 {
22 if (rv_cache_ops && rv_cache_ops->get_priv_group)
23 return rv_cache_ops->get_priv_group(this_leaf);
24 return NULL;
25 }
26
get_cacheinfo(u32 level,enum cache_type type)27 static struct cacheinfo *get_cacheinfo(u32 level, enum cache_type type)
28 {
29 /*
30 * Using raw_smp_processor_id() elides a preemptability check, but this
31 * is really indicative of a larger problem: the cacheinfo UABI assumes
32 * that cores have a homonogenous view of the cache hierarchy. That
33 * happens to be the case for the current set of RISC-V systems, but
34 * likely won't be true in general. Since there's no way to provide
35 * correct information for these systems via the current UABI we're
36 * just eliding the check for now.
37 */
38 struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(raw_smp_processor_id());
39 struct cacheinfo *this_leaf;
40 int index;
41
42 for (index = 0; index < this_cpu_ci->num_leaves; index++) {
43 this_leaf = this_cpu_ci->info_list + index;
44 if (this_leaf->level == level && this_leaf->type == type)
45 return this_leaf;
46 }
47
48 return NULL;
49 }
50
get_cache_size(u32 level,enum cache_type type)51 uintptr_t get_cache_size(u32 level, enum cache_type type)
52 {
53 struct cacheinfo *this_leaf = get_cacheinfo(level, type);
54
55 return this_leaf ? this_leaf->size : 0;
56 }
57
get_cache_geometry(u32 level,enum cache_type type)58 uintptr_t get_cache_geometry(u32 level, enum cache_type type)
59 {
60 struct cacheinfo *this_leaf = get_cacheinfo(level, type);
61
62 return this_leaf ? (this_leaf->ways_of_associativity << 16 |
63 this_leaf->coherency_line_size) :
64 0;
65 }
66
ci_leaf_init(struct cacheinfo * this_leaf,enum cache_type type,unsigned int level)67 static void ci_leaf_init(struct cacheinfo *this_leaf,
68 enum cache_type type, unsigned int level)
69 {
70 this_leaf->level = level;
71 this_leaf->type = type;
72 }
73
populate_cache_leaves(unsigned int cpu)74 int populate_cache_leaves(unsigned int cpu)
75 {
76 struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
77 struct cacheinfo *this_leaf = this_cpu_ci->info_list;
78 struct device_node *np, *prev;
79 int levels = 1, level = 1;
80
81 if (!acpi_disabled) {
82 int ret, fw_levels, split_levels;
83
84 ret = acpi_get_cache_info(cpu, &fw_levels, &split_levels);
85 if (ret)
86 return ret;
87
88 BUG_ON((split_levels > fw_levels) ||
89 (split_levels + fw_levels > this_cpu_ci->num_leaves));
90
91 for (; level <= this_cpu_ci->num_levels; level++) {
92 if (level <= split_levels) {
93 ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
94 ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
95 } else {
96 ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
97 }
98 }
99 return 0;
100 }
101
102 np = of_cpu_device_node_get(cpu);
103 if (!np)
104 return -ENOENT;
105
106 if (of_property_present(np, "cache-size"))
107 ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
108 if (of_property_present(np, "i-cache-size"))
109 ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
110 if (of_property_present(np, "d-cache-size"))
111 ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
112
113 prev = np;
114 while ((np = of_find_next_cache_node(np))) {
115 of_node_put(prev);
116 prev = np;
117 if (!of_device_is_compatible(np, "cache"))
118 break;
119 if (of_property_read_u32(np, "cache-level", &level))
120 break;
121 if (level <= levels)
122 break;
123 if (of_property_present(np, "cache-size"))
124 ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
125 if (of_property_present(np, "i-cache-size"))
126 ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
127 if (of_property_present(np, "d-cache-size"))
128 ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
129 levels = level;
130 }
131 of_node_put(np);
132
133 return 0;
134 }
135