1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * xHCI host controller driver PCI Bus Glue.
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11 #include <linux/pci.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/acpi.h>
15 #include <linux/reset.h>
16 #include <linux/suspend.h>
17
18 #include "xhci.h"
19 #include "xhci-trace.h"
20 #include "xhci-pci.h"
21
22 #define SSIC_PORT_NUM 2
23 #define SSIC_PORT_CFG2 0x880c
24 #define SSIC_PORT_CFG2_OFFSET 0x30
25 #define PROG_DONE (1 << 30)
26 #define SSIC_PORT_UNUSED (1 << 31)
27 #define SPARSE_DISABLE_BIT 17
28 #define SPARSE_CNTL_ENABLE 0xC12C
29
30 /* Device for a quirk */
31 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
32 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100
35 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
36
37 #define PCI_VENDOR_ID_ETRON 0x1b6f
38 #define PCI_DEVICE_ID_EJ168 0x7023
39 #define PCI_DEVICE_ID_EJ188 0x7052
40
41 #define PCI_DEVICE_ID_VIA_VL805 0x3483
42
43 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
44 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
45 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
46 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
47 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
48 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
49 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
50 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
51 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
52 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5
54 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6
55 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1
56 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db
57 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4
58 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9
59 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec
60 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0
61 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13
62 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af
63 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13
64 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138
65 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed
66 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed
67
68 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639
69 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
70 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
71 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
72 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
73
74 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042
75 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
76 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242
77 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142
78 #define PCI_DEVICE_ID_ASMEDIA_3042_XHCI 0x3042
79 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242
80
81 #define PCI_DEVICE_ID_CADENCE 0x17CD
82 #define PCI_DEVICE_ID_CADENCE_SSP 0x0200
83
84 static const char hcd_name[] = "xhci_hcd";
85
86 static struct hc_driver __read_mostly xhci_pci_hc_driver;
87
88 static int xhci_pci_setup(struct usb_hcd *hcd);
89 static int xhci_pci_run(struct usb_hcd *hcd);
90 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
91 struct usb_tt *tt, gfp_t mem_flags);
92
93 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
94 .reset = xhci_pci_setup,
95 .start = xhci_pci_run,
96 .update_hub_device = xhci_pci_update_hub_device,
97 };
98
xhci_msix_sync_irqs(struct xhci_hcd * xhci)99 static void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
100 {
101 struct usb_hcd *hcd = xhci_to_hcd(xhci);
102
103 if (hcd->msix_enabled) {
104 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
105 int i;
106
107 for (i = 0; i < xhci->msix_count; i++)
108 synchronize_irq(pci_irq_vector(pdev, i));
109 }
110 }
111
112 /* Free any IRQs and disable MSI-X */
xhci_cleanup_msix(struct xhci_hcd * xhci)113 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
114 {
115 struct usb_hcd *hcd = xhci_to_hcd(xhci);
116 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
117
118 /* return if using legacy interrupt */
119 if (hcd->irq > 0)
120 return;
121
122 if (hcd->msix_enabled) {
123 int i;
124
125 for (i = 0; i < xhci->msix_count; i++)
126 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
127 } else {
128 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
129 }
130
131 pci_free_irq_vectors(pdev);
132 hcd->msix_enabled = 0;
133 }
134
135 /*
136 * Set up MSI
137 */
xhci_setup_msi(struct xhci_hcd * xhci)138 static int xhci_setup_msi(struct xhci_hcd *xhci)
139 {
140 int ret;
141 /*
142 * TODO:Check with MSI Soc for sysdev
143 */
144 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
145
146 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
147 if (ret < 0) {
148 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
149 "failed to allocate MSI entry");
150 return ret;
151 }
152
153 ret = request_irq(pdev->irq, xhci_msi_irq,
154 0, "xhci_hcd", xhci_to_hcd(xhci));
155 if (ret) {
156 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
157 "disable MSI interrupt");
158 pci_free_irq_vectors(pdev);
159 }
160
161 return ret;
162 }
163
164 /*
165 * Set up MSI-X
166 */
xhci_setup_msix(struct xhci_hcd * xhci)167 static int xhci_setup_msix(struct xhci_hcd *xhci)
168 {
169 int i, ret;
170 struct usb_hcd *hcd = xhci_to_hcd(xhci);
171 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
172
173 /*
174 * calculate number of msi-x vectors supported.
175 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
176 * with max number of interrupters based on the xhci HCSPARAMS1.
177 * - num_online_cpus: maximum msi-x vectors per CPUs core.
178 * Add additional 1 vector to ensure always available interrupt.
179 */
180 xhci->msix_count = min(num_online_cpus() + 1,
181 HCS_MAX_INTRS(xhci->hcs_params1));
182
183 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
184 PCI_IRQ_MSIX);
185 if (ret < 0) {
186 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
187 "Failed to enable MSI-X");
188 return ret;
189 }
190
191 for (i = 0; i < xhci->msix_count; i++) {
192 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
193 "xhci_hcd", xhci_to_hcd(xhci));
194 if (ret)
195 goto disable_msix;
196 }
197
198 hcd->msix_enabled = 1;
199 return ret;
200
201 disable_msix:
202 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
203 while (--i >= 0)
204 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
205 pci_free_irq_vectors(pdev);
206 return ret;
207 }
208
xhci_try_enable_msi(struct usb_hcd * hcd)209 static int xhci_try_enable_msi(struct usb_hcd *hcd)
210 {
211 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
212 struct pci_dev *pdev;
213 int ret;
214
215 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
216 /*
217 * Some Fresco Logic host controllers advertise MSI, but fail to
218 * generate interrupts. Don't even try to enable MSI.
219 */
220 if (xhci->quirks & XHCI_BROKEN_MSI)
221 goto legacy_irq;
222
223 /* unregister the legacy interrupt */
224 if (hcd->irq)
225 free_irq(hcd->irq, hcd);
226 hcd->irq = 0;
227
228 ret = xhci_setup_msix(xhci);
229 if (ret)
230 /* fall back to msi*/
231 ret = xhci_setup_msi(xhci);
232
233 if (!ret) {
234 hcd->msi_enabled = 1;
235 return 0;
236 }
237
238 if (!pdev->irq) {
239 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
240 return -EINVAL;
241 }
242
243 legacy_irq:
244 if (!strlen(hcd->irq_descr))
245 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
246 hcd->driver->description, hcd->self.busnum);
247
248 /* fall back to legacy interrupt*/
249 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
250 hcd->irq_descr, hcd);
251 if (ret) {
252 xhci_err(xhci, "request interrupt %d failed\n",
253 pdev->irq);
254 return ret;
255 }
256 hcd->irq = pdev->irq;
257 return 0;
258 }
259
xhci_pci_run(struct usb_hcd * hcd)260 static int xhci_pci_run(struct usb_hcd *hcd)
261 {
262 int ret;
263
264 if (usb_hcd_is_primary_hcd(hcd)) {
265 ret = xhci_try_enable_msi(hcd);
266 if (ret)
267 return ret;
268 }
269
270 return xhci_run(hcd);
271 }
272
xhci_pci_stop(struct usb_hcd * hcd)273 static void xhci_pci_stop(struct usb_hcd *hcd)
274 {
275 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
276
277 xhci_stop(hcd);
278
279 if (usb_hcd_is_primary_hcd(hcd))
280 xhci_cleanup_msix(xhci);
281 }
282
283 /* called after powerup, by probe or system-pm "wakeup" */
xhci_pci_reinit(struct xhci_hcd * xhci,struct pci_dev * pdev)284 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
285 {
286 /*
287 * TODO: Implement finding debug ports later.
288 * TODO: see if there are any quirks that need to be added to handle
289 * new extended capabilities.
290 */
291
292 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
293 if (!pci_set_mwi(pdev))
294 xhci_dbg(xhci, "MWI active\n");
295
296 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
297 return 0;
298 }
299
xhci_pci_quirks(struct device * dev,struct xhci_hcd * xhci)300 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
301 {
302 struct pci_dev *pdev = to_pci_dev(dev);
303 struct xhci_driver_data *driver_data;
304 const struct pci_device_id *id;
305
306 id = pci_match_id(to_pci_driver(pdev->dev.driver)->id_table, pdev);
307
308 if (id && id->driver_data) {
309 driver_data = (struct xhci_driver_data *)id->driver_data;
310 xhci->quirks |= driver_data->quirks;
311 }
312
313 /* Look for vendor-specific quirks */
314 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
315 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
316 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
317 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
318 pdev->revision == 0x0) {
319 xhci->quirks |= XHCI_RESET_EP_QUIRK;
320 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
321 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated");
322 }
323 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
324 pdev->revision == 0x4) {
325 xhci->quirks |= XHCI_SLOW_SUSPEND;
326 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
327 "QUIRK: Fresco Logic xHC revision %u"
328 "must be suspended extra slowly",
329 pdev->revision);
330 }
331 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
332 xhci->quirks |= XHCI_BROKEN_STREAMS;
333 /* Fresco Logic confirms: all revisions of this chip do not
334 * support MSI, even though some of them claim to in their PCI
335 * capabilities.
336 */
337 xhci->quirks |= XHCI_BROKEN_MSI;
338 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
339 "QUIRK: Fresco Logic revision %u "
340 "has broken MSI implementation",
341 pdev->revision);
342 }
343
344 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
345 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
346 xhci->quirks |= XHCI_BROKEN_STREAMS;
347
348 if (pdev->vendor == PCI_VENDOR_ID_NEC)
349 xhci->quirks |= XHCI_NEC_HOST;
350
351 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
352 xhci->quirks |= XHCI_AMD_0x96_HOST;
353
354 /* AMD PLL quirk */
355 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
356 xhci->quirks |= XHCI_AMD_PLL_FIX;
357
358 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
359 (pdev->device == 0x145c ||
360 pdev->device == 0x15e0 ||
361 pdev->device == 0x15e1 ||
362 pdev->device == 0x43bb))
363 xhci->quirks |= XHCI_SUSPEND_DELAY;
364
365 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
366 (pdev->device == 0x15e0 || pdev->device == 0x15e1))
367 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
368
369 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
370 xhci->quirks |= XHCI_DISABLE_SPARSE;
371 xhci->quirks |= XHCI_RESET_ON_RESUME;
372 }
373
374 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x43f7)
375 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
376
377 if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
378 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
379 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
380 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
381 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
382 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
383
384 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
385 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI)
386 xhci->quirks |= XHCI_BROKEN_D3COLD_S2I;
387
388 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
389 xhci->quirks |= XHCI_LPM_SUPPORT;
390 xhci->quirks |= XHCI_INTEL_HOST;
391 xhci->quirks |= XHCI_AVOID_BEI;
392 }
393 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
394 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
395 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
396 xhci->limit_active_eps = 64;
397 xhci->quirks |= XHCI_SW_BW_CHECKING;
398 /*
399 * PPT desktop boards DH77EB and DH77DF will power back on after
400 * a few seconds of being shutdown. The fix for this is to
401 * switch the ports from xHCI to EHCI on shutdown. We can't use
402 * DMI information to find those particular boards (since each
403 * vendor will change the board name), so we have to key off all
404 * PPT chipsets.
405 */
406 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
407 }
408 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
409 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
410 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
411 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
412 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
413 }
414 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
415 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
416 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
417 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
418 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
419 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
420 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
421 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
422 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
423 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
424 }
425 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
426 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
427 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
428 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
429 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
430 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
431 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
432 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
433 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
434 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
435 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
436 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
437 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
438 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
439 xhci->quirks |= XHCI_MISSING_CAS;
440
441 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
442 (pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI ||
443 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI))
444 xhci->quirks |= XHCI_RESET_TO_DEFAULT;
445
446 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
447 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
448 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
449 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
450 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
451 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
452 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
453 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
454 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
455 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
456 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
457 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI))
458 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
459
460 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
461 (pdev->device == PCI_DEVICE_ID_EJ168 ||
462 pdev->device == PCI_DEVICE_ID_EJ188)) {
463 xhci->quirks |= XHCI_ETRON_HOST;
464 xhci->quirks |= XHCI_RESET_ON_RESUME;
465 xhci->quirks |= XHCI_BROKEN_STREAMS;
466 }
467
468 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
469 pdev->device == 0x0014) {
470 xhci->quirks |= XHCI_ZERO_64B_REGS;
471 }
472 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
473 pdev->device == 0x0015) {
474 xhci->quirks |= XHCI_RESET_ON_RESUME;
475 xhci->quirks |= XHCI_ZERO_64B_REGS;
476 }
477 if (pdev->vendor == PCI_VENDOR_ID_VIA)
478 xhci->quirks |= XHCI_RESET_ON_RESUME;
479
480 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
481 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
482 pdev->device == 0x3432)
483 xhci->quirks |= XHCI_BROKEN_STREAMS;
484
485 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == PCI_DEVICE_ID_VIA_VL805) {
486 xhci->quirks |= XHCI_LPM_SUPPORT;
487 xhci->quirks |= XHCI_TRB_OVERFETCH;
488 }
489
490 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
491 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) {
492 /*
493 * try to tame the ASMedia 1042 controller which reports 0.96
494 * but appears to behave more like 1.0
495 */
496 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
497 xhci->quirks |= XHCI_BROKEN_STREAMS;
498 }
499 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
500 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
501 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
502 }
503 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
504 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
505 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
506 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
507 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
508
509 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
510 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
511 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
512
513 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
514 pdev->device == PCI_DEVICE_ID_ASMEDIA_3042_XHCI)
515 xhci->quirks |= XHCI_RESET_ON_RESUME;
516
517 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
518 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
519
520 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
521 pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
522 pdev->device == 0x9026)
523 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
524
525 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
526 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
527 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
528 xhci->quirks |= XHCI_NO_SOFT_RETRY;
529
530 if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) {
531 xhci->quirks |= XHCI_ZHAOXIN_HOST;
532 xhci->quirks |= XHCI_LPM_SUPPORT;
533
534 if (pdev->device == 0x9202) {
535 xhci->quirks |= XHCI_RESET_ON_RESUME;
536 xhci->quirks |= XHCI_TRB_OVERFETCH;
537 }
538
539 if (pdev->device == 0x9203)
540 xhci->quirks |= XHCI_TRB_OVERFETCH;
541 }
542
543 if (pdev->vendor == PCI_DEVICE_ID_CADENCE &&
544 pdev->device == PCI_DEVICE_ID_CADENCE_SSP)
545 xhci->quirks |= XHCI_CDNS_SCTX_QUIRK;
546
547 /* xHC spec requires PCI devices to support D3hot and D3cold */
548 if (xhci->hci_version >= 0x120)
549 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
550
551 if (xhci->quirks & XHCI_RESET_ON_RESUME)
552 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
553 "QUIRK: Resetting on resume");
554 }
555
556 #ifdef CONFIG_ACPI
xhci_pme_acpi_rtd3_enable(struct pci_dev * dev)557 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
558 {
559 static const guid_t intel_dsm_guid =
560 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
561 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
562 union acpi_object *obj;
563
564 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
565 NULL);
566 ACPI_FREE(obj);
567 }
568
xhci_find_lpm_incapable_ports(struct usb_hcd * hcd,struct usb_device * hdev)569 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev)
570 {
571 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
572 struct xhci_hub *rhub = &xhci->usb3_rhub;
573 int ret;
574 int i;
575
576 /* This is not the usb3 roothub we are looking for */
577 if (hcd != rhub->hcd)
578 return;
579
580 if (hdev->maxchild > rhub->num_ports) {
581 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n");
582 return;
583 }
584
585 for (i = 0; i < hdev->maxchild; i++) {
586 ret = usb_acpi_port_lpm_incapable(hdev, i);
587
588 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret);
589
590 if (ret >= 0) {
591 rhub->ports[i]->lpm_incapable = ret;
592 continue;
593 }
594 }
595 }
596
597 #else
xhci_pme_acpi_rtd3_enable(struct pci_dev * dev)598 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
xhci_find_lpm_incapable_ports(struct usb_hcd * hcd,struct usb_device * hdev)599 static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { }
600 #endif /* CONFIG_ACPI */
601
602 /* called during probe() after chip reset completes */
xhci_pci_setup(struct usb_hcd * hcd)603 static int xhci_pci_setup(struct usb_hcd *hcd)
604 {
605 struct xhci_hcd *xhci;
606 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
607 int retval;
608
609 xhci = hcd_to_xhci(hcd);
610 if (!xhci->sbrn)
611 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
612
613 /* imod_interval is the interrupt moderation value in nanoseconds. */
614 xhci->imod_interval = 40000;
615
616 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
617 if (retval)
618 return retval;
619
620 if (!usb_hcd_is_primary_hcd(hcd))
621 return 0;
622
623 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
624 xhci_pme_acpi_rtd3_enable(pdev);
625
626 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
627
628 /* Find any debug ports */
629 return xhci_pci_reinit(xhci, pdev);
630 }
631
xhci_pci_update_hub_device(struct usb_hcd * hcd,struct usb_device * hdev,struct usb_tt * tt,gfp_t mem_flags)632 static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
633 struct usb_tt *tt, gfp_t mem_flags)
634 {
635 /* Check if acpi claims some USB3 roothub ports are lpm incapable */
636 if (!hdev->parent)
637 xhci_find_lpm_incapable_ports(hcd, hdev);
638
639 return xhci_update_hub_device(hcd, hdev, tt, mem_flags);
640 }
641
642 /*
643 * We need to register our own PCI probe function (instead of the USB core's
644 * function) in order to create a second roothub under xHCI.
645 */
xhci_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)646 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
647 {
648 int retval;
649 struct xhci_hcd *xhci;
650 struct usb_hcd *hcd;
651 struct xhci_driver_data *driver_data;
652 struct reset_control *reset;
653
654 driver_data = (struct xhci_driver_data *)id->driver_data;
655 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
656 retval = renesas_xhci_check_request_fw(dev, id);
657 if (retval)
658 return retval;
659 }
660
661 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
662 if (IS_ERR(reset))
663 return PTR_ERR(reset);
664 reset_control_reset(reset);
665
666 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
667 pm_runtime_get_noresume(&dev->dev);
668
669 /* Register the USB 2.0 roothub.
670 * FIXME: USB core must know to register the USB 2.0 roothub first.
671 * This is sort of silly, because we could just set the HCD driver flags
672 * to say USB 2.0, but I'm not sure what the implications would be in
673 * the other parts of the HCD code.
674 */
675 retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver);
676
677 if (retval)
678 goto put_runtime_pm;
679
680 /* USB 2.0 roothub is stored in the PCI device now. */
681 hcd = dev_get_drvdata(&dev->dev);
682 xhci = hcd_to_xhci(hcd);
683 xhci->reset = reset;
684 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
685 pci_name(dev), hcd);
686 if (!xhci->shared_hcd) {
687 retval = -ENOMEM;
688 goto dealloc_usb2_hcd;
689 }
690
691 retval = xhci_ext_cap_init(xhci);
692 if (retval)
693 goto put_usb3_hcd;
694
695 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
696 IRQF_SHARED);
697 if (retval)
698 goto put_usb3_hcd;
699 /* Roothub already marked as USB 3.0 speed */
700
701 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
702 HCC_MAX_PSA(xhci->hcc_params) >= 4)
703 xhci->shared_hcd->can_do_streams = 1;
704
705 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
706 pm_runtime_put_noidle(&dev->dev);
707
708 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0)
709 pm_runtime_get(&dev->dev);
710 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
711 pm_runtime_allow(&dev->dev);
712
713 dma_set_max_seg_size(&dev->dev, UINT_MAX);
714
715 return 0;
716
717 put_usb3_hcd:
718 usb_put_hcd(xhci->shared_hcd);
719 dealloc_usb2_hcd:
720 usb_hcd_pci_remove(dev);
721 put_runtime_pm:
722 pm_runtime_put_noidle(&dev->dev);
723 return retval;
724 }
725
xhci_pci_remove(struct pci_dev * dev)726 static void xhci_pci_remove(struct pci_dev *dev)
727 {
728 struct xhci_hcd *xhci;
729 bool set_power_d3;
730
731 xhci = hcd_to_xhci(pci_get_drvdata(dev));
732 set_power_d3 = xhci->quirks & XHCI_SPURIOUS_WAKEUP;
733
734 xhci->xhc_state |= XHCI_STATE_REMOVING;
735
736 if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0)
737 pm_runtime_put(&dev->dev);
738 else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
739 pm_runtime_forbid(&dev->dev);
740
741 if (xhci->shared_hcd) {
742 usb_remove_hcd(xhci->shared_hcd);
743 usb_put_hcd(xhci->shared_hcd);
744 xhci->shared_hcd = NULL;
745 }
746
747 usb_hcd_pci_remove(dev);
748
749 /* Workaround for spurious wakeups at shutdown with HSW */
750 if (set_power_d3)
751 pci_set_power_state(dev, PCI_D3hot);
752 }
753
754 /*
755 * In some Intel xHCI controllers, in order to get D3 working,
756 * through a vendor specific SSIC CONFIG register at offset 0x883c,
757 * SSIC PORT need to be marked as "unused" before putting xHCI
758 * into D3. After D3 exit, the SSIC port need to be marked as "used".
759 * Without this change, xHCI might not enter D3 state.
760 */
xhci_ssic_port_unused_quirk(struct usb_hcd * hcd,bool suspend)761 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
762 {
763 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
764 u32 val;
765 void __iomem *reg;
766 int i;
767
768 for (i = 0; i < SSIC_PORT_NUM; i++) {
769 reg = (void __iomem *) xhci->cap_regs +
770 SSIC_PORT_CFG2 +
771 i * SSIC_PORT_CFG2_OFFSET;
772
773 /* Notify SSIC that SSIC profile programming is not done. */
774 val = readl(reg) & ~PROG_DONE;
775 writel(val, reg);
776
777 /* Mark SSIC port as unused(suspend) or used(resume) */
778 val = readl(reg);
779 if (suspend)
780 val |= SSIC_PORT_UNUSED;
781 else
782 val &= ~SSIC_PORT_UNUSED;
783 writel(val, reg);
784
785 /* Notify SSIC that SSIC profile programming is done */
786 val = readl(reg) | PROG_DONE;
787 writel(val, reg);
788 readl(reg);
789 }
790 }
791
792 /*
793 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
794 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
795 */
xhci_pme_quirk(struct usb_hcd * hcd)796 static void xhci_pme_quirk(struct usb_hcd *hcd)
797 {
798 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
799 void __iomem *reg;
800 u32 val;
801
802 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
803 val = readl(reg);
804 writel(val | BIT(28), reg);
805 readl(reg);
806 }
807
xhci_sparse_control_quirk(struct usb_hcd * hcd)808 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
809 {
810 u32 reg;
811
812 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
813 reg &= ~BIT(SPARSE_DISABLE_BIT);
814 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
815 }
816
xhci_pci_suspend(struct usb_hcd * hcd,bool do_wakeup)817 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
818 {
819 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
820 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
821 int ret;
822
823 /*
824 * Systems with the TI redriver that loses port status change events
825 * need to have the registers polled during D3, so avoid D3cold.
826 */
827 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
828 pci_d3cold_disable(pdev);
829
830 #ifdef CONFIG_SUSPEND
831 /* d3cold is broken, but only when s2idle is used */
832 if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE &&
833 xhci->quirks & (XHCI_BROKEN_D3COLD_S2I))
834 pci_d3cold_disable(pdev);
835 #endif
836
837 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
838 xhci_pme_quirk(hcd);
839
840 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
841 xhci_ssic_port_unused_quirk(hcd, true);
842
843 if (xhci->quirks & XHCI_DISABLE_SPARSE)
844 xhci_sparse_control_quirk(hcd);
845
846 ret = xhci_suspend(xhci, do_wakeup);
847
848 /* synchronize irq when using MSI-X */
849 xhci_msix_sync_irqs(xhci);
850
851 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
852 xhci_ssic_port_unused_quirk(hcd, false);
853
854 return ret;
855 }
856
xhci_pci_resume(struct usb_hcd * hcd,pm_message_t msg)857 static int xhci_pci_resume(struct usb_hcd *hcd, pm_message_t msg)
858 {
859 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
860 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
861 int retval = 0;
862
863 reset_control_reset(xhci->reset);
864
865 /* The BIOS on systems with the Intel Panther Point chipset may or may
866 * not support xHCI natively. That means that during system resume, it
867 * may switch the ports back to EHCI so that users can use their
868 * keyboard to select a kernel from GRUB after resume from hibernate.
869 *
870 * The BIOS is supposed to remember whether the OS had xHCI ports
871 * enabled before resume, and switch the ports back to xHCI when the
872 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
873 * writers.
874 *
875 * Unconditionally switch the ports back to xHCI after a system resume.
876 * It should not matter whether the EHCI or xHCI controller is
877 * resumed first. It's enough to do the switchover in xHCI because
878 * USB core won't notice anything as the hub driver doesn't start
879 * running again until after all the devices (including both EHCI and
880 * xHCI host controllers) have been resumed.
881 */
882
883 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
884 usb_enable_intel_xhci_ports(pdev);
885
886 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
887 xhci_ssic_port_unused_quirk(hcd, false);
888
889 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
890 xhci_pme_quirk(hcd);
891
892 retval = xhci_resume(xhci, msg);
893 return retval;
894 }
895
xhci_pci_poweroff_late(struct usb_hcd * hcd,bool do_wakeup)896 static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup)
897 {
898 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
899 struct xhci_port *port;
900 struct usb_device *udev;
901 unsigned int slot_id;
902 u32 portsc;
903 int i;
904
905 /*
906 * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that
907 * cause significant boot delay if usb ports are in suspended U3 state
908 * during boot. Some USB devices survive in U3 state over S4 hibernate
909 *
910 * Disable ports that are in U3 if remote wake is not enabled for either
911 * host controller or connected device
912 */
913
914 if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT))
915 return 0;
916
917 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
918 port = &xhci->hw_ports[i];
919 portsc = readl(port->addr);
920
921 if ((portsc & PORT_PLS_MASK) != XDEV_U3)
922 continue;
923
924 slot_id = xhci_find_slot_id_by_port(port->rhub->hcd, xhci,
925 port->hcd_portnum + 1);
926 if (!slot_id || !xhci->devs[slot_id]) {
927 xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n",
928 slot_id, port->rhub->hcd->self.busnum, port->hcd_portnum + 1);
929 continue;
930 }
931
932 udev = xhci->devs[slot_id]->udev;
933
934 /* if wakeup is enabled then don't disable the port */
935 if (udev->do_remote_wakeup && do_wakeup)
936 continue;
937
938 xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n",
939 port->rhub->hcd->self.busnum, port->hcd_portnum + 1);
940 portsc = xhci_port_state_to_neutral(portsc);
941 writel(portsc | PORT_PE, port->addr);
942 }
943
944 return 0;
945 }
946
xhci_pci_shutdown(struct usb_hcd * hcd)947 static void xhci_pci_shutdown(struct usb_hcd *hcd)
948 {
949 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
950 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
951
952 xhci_shutdown(hcd);
953 xhci_cleanup_msix(xhci);
954
955 /* Yet another workaround for spurious wakeups at shutdown with HSW */
956 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
957 pci_set_power_state(pdev, PCI_D3hot);
958 }
959
960 /*-------------------------------------------------------------------------*/
961
962 static const struct xhci_driver_data reneses_data = {
963 .quirks = XHCI_RENESAS_FW_QUIRK,
964 .firmware = "renesas_usb_fw.mem",
965 };
966
967 /* PCI driver selection metadata; PCI hotplugging uses this */
968 static const struct pci_device_id pci_ids[] = {
969 { PCI_DEVICE(0x1912, 0x0014),
970 .driver_data = (unsigned long)&reneses_data,
971 },
972 { PCI_DEVICE(0x1912, 0x0015),
973 .driver_data = (unsigned long)&reneses_data,
974 },
975 /* handle any USB 3.0 xHCI controller */
976 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
977 },
978 { /* end: all zeroes */ }
979 };
980 MODULE_DEVICE_TABLE(pci, pci_ids);
981
982 /*
983 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't
984 * load firmware, so don't encumber the xhci-pci driver with it.
985 */
986 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS)
987 MODULE_FIRMWARE("renesas_usb_fw.mem");
988 #endif
989
990 /* pci driver glue; this is a "new style" PCI driver module */
991 static struct pci_driver xhci_pci_driver = {
992 .name = hcd_name,
993 .id_table = pci_ids,
994
995 .probe = xhci_pci_probe,
996 .remove = xhci_pci_remove,
997 /* suspend and resume implemented later */
998
999 .shutdown = usb_hcd_pci_shutdown,
1000 .driver = {
1001 .pm = pm_ptr(&usb_hcd_pci_pm_ops),
1002 },
1003 };
1004
xhci_pci_init(void)1005 static int __init xhci_pci_init(void)
1006 {
1007 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
1008 xhci_pci_hc_driver.pci_suspend = pm_ptr(xhci_pci_suspend);
1009 xhci_pci_hc_driver.pci_resume = pm_ptr(xhci_pci_resume);
1010 xhci_pci_hc_driver.pci_poweroff_late = pm_ptr(xhci_pci_poweroff_late);
1011 xhci_pci_hc_driver.shutdown = pm_ptr(xhci_pci_shutdown);
1012 xhci_pci_hc_driver.stop = xhci_pci_stop;
1013 return pci_register_driver(&xhci_pci_driver);
1014 }
1015 module_init(xhci_pci_init);
1016
xhci_pci_exit(void)1017 static void __exit xhci_pci_exit(void)
1018 {
1019 pci_unregister_driver(&xhci_pci_driver);
1020 }
1021 module_exit(xhci_pci_exit);
1022
1023 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
1024 MODULE_LICENSE("GPL");
1025