1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
4 *
5 * Derived from:
6 * https://github.com/yuq/sunxi-nfc-mtd
7 * Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
8 *
9 * https://github.com/hno/Allwinner-Info
10 * Copyright (C) 2013 Henrik Nordström <Henrik Nordström>
11 *
12 * Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
13 * Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
14 */
15
16 #include <linux/dma-mapping.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/platform_device.h>
21 #include <linux/of.h>
22 #include <linux/mtd/mtd.h>
23 #include <linux/mtd/rawnand.h>
24 #include <linux/mtd/partitions.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/dmaengine.h>
28 #include <linux/interrupt.h>
29 #include <linux/iopoll.h>
30 #include <linux/reset.h>
31
32 #define NFC_REG_CTL 0x0000
33 #define NFC_REG_ST 0x0004
34 #define NFC_REG_INT 0x0008
35 #define NFC_REG_TIMING_CTL 0x000C
36 #define NFC_REG_TIMING_CFG 0x0010
37 #define NFC_REG_ADDR_LOW 0x0014
38 #define NFC_REG_ADDR_HIGH 0x0018
39 #define NFC_REG_SECTOR_NUM 0x001C
40 #define NFC_REG_CNT 0x0020
41 #define NFC_REG_CMD 0x0024
42 #define NFC_REG_RCMD_SET 0x0028
43 #define NFC_REG_WCMD_SET 0x002C
44 #define NFC_REG_A10_IO_DATA 0x0030
45 #define NFC_REG_A23_IO_DATA 0x0300
46 #define NFC_REG_ECC_CTL 0x0034
47 #define NFC_REG_ECC_ST 0x0038
48 #define NFC_REG_DEBUG 0x003C
49 #define NFC_REG_ECC_ERR_CNT(x) ((0x0040 + (x)) & ~0x3)
50 #define NFC_REG_USER_DATA(x) (0x0050 + ((x) * 4))
51 #define NFC_REG_SPARE_AREA 0x00A0
52 #define NFC_REG_PAT_ID 0x00A4
53 #define NFC_REG_MDMA_ADDR 0x00C0
54 #define NFC_REG_MDMA_CNT 0x00C4
55 #define NFC_RAM0_BASE 0x0400
56 #define NFC_RAM1_BASE 0x0800
57
58 /* define bit use in NFC_CTL */
59 #define NFC_EN BIT(0)
60 #define NFC_RESET BIT(1)
61 #define NFC_BUS_WIDTH_MSK BIT(2)
62 #define NFC_BUS_WIDTH_8 (0 << 2)
63 #define NFC_BUS_WIDTH_16 (1 << 2)
64 #define NFC_RB_SEL_MSK BIT(3)
65 #define NFC_RB_SEL(x) ((x) << 3)
66 #define NFC_CE_SEL_MSK GENMASK(26, 24)
67 #define NFC_CE_SEL(x) ((x) << 24)
68 #define NFC_CE_CTL BIT(6)
69 #define NFC_PAGE_SHIFT_MSK GENMASK(11, 8)
70 #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
71 #define NFC_SAM BIT(12)
72 #define NFC_RAM_METHOD BIT(14)
73 #define NFC_DMA_TYPE_NORMAL BIT(15)
74 #define NFC_DEBUG_CTL BIT(31)
75
76 /* define bit use in NFC_ST */
77 #define NFC_RB_B2R BIT(0)
78 #define NFC_CMD_INT_FLAG BIT(1)
79 #define NFC_DMA_INT_FLAG BIT(2)
80 #define NFC_CMD_FIFO_STATUS BIT(3)
81 #define NFC_STA BIT(4)
82 #define NFC_NATCH_INT_FLAG BIT(5)
83 #define NFC_RB_STATE(x) BIT(x + 8)
84
85 /* define bit use in NFC_INT */
86 #define NFC_B2R_INT_ENABLE BIT(0)
87 #define NFC_CMD_INT_ENABLE BIT(1)
88 #define NFC_DMA_INT_ENABLE BIT(2)
89 #define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \
90 NFC_CMD_INT_ENABLE | \
91 NFC_DMA_INT_ENABLE)
92
93 /* define bit use in NFC_TIMING_CTL */
94 #define NFC_TIMING_CTL_EDO BIT(8)
95
96 /* define NFC_TIMING_CFG register layout */
97 #define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \
98 (((tWB) & 0x3) | (((tADL) & 0x3) << 2) | \
99 (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) | \
100 (((tCAD) & 0x7) << 8))
101
102 /* define bit use in NFC_CMD */
103 #define NFC_CMD_LOW_BYTE_MSK GENMASK(7, 0)
104 #define NFC_CMD_HIGH_BYTE_MSK GENMASK(15, 8)
105 #define NFC_CMD(x) (x)
106 #define NFC_ADR_NUM_MSK GENMASK(18, 16)
107 #define NFC_ADR_NUM(x) (((x) - 1) << 16)
108 #define NFC_SEND_ADR BIT(19)
109 #define NFC_ACCESS_DIR BIT(20)
110 #define NFC_DATA_TRANS BIT(21)
111 #define NFC_SEND_CMD1 BIT(22)
112 #define NFC_WAIT_FLAG BIT(23)
113 #define NFC_SEND_CMD2 BIT(24)
114 #define NFC_SEQ BIT(25)
115 #define NFC_DATA_SWAP_METHOD BIT(26)
116 #define NFC_ROW_AUTO_INC BIT(27)
117 #define NFC_SEND_CMD3 BIT(28)
118 #define NFC_SEND_CMD4 BIT(29)
119 #define NFC_CMD_TYPE_MSK GENMASK(31, 30)
120 #define NFC_NORMAL_OP (0 << 30)
121 #define NFC_ECC_OP (1 << 30)
122 #define NFC_PAGE_OP (2U << 30)
123
124 /* define bit use in NFC_RCMD_SET */
125 #define NFC_READ_CMD_MSK GENMASK(7, 0)
126 #define NFC_RND_READ_CMD0_MSK GENMASK(15, 8)
127 #define NFC_RND_READ_CMD1_MSK GENMASK(23, 16)
128
129 /* define bit use in NFC_WCMD_SET */
130 #define NFC_PROGRAM_CMD_MSK GENMASK(7, 0)
131 #define NFC_RND_WRITE_CMD_MSK GENMASK(15, 8)
132 #define NFC_READ_CMD0_MSK GENMASK(23, 16)
133 #define NFC_READ_CMD1_MSK GENMASK(31, 24)
134
135 /* define bit use in NFC_ECC_CTL */
136 #define NFC_ECC_EN BIT(0)
137 #define NFC_ECC_PIPELINE BIT(3)
138 #define NFC_ECC_EXCEPTION BIT(4)
139 #define NFC_ECC_BLOCK_SIZE_MSK BIT(5)
140 #define NFC_ECC_BLOCK_512 BIT(5)
141 #define NFC_RANDOM_EN BIT(9)
142 #define NFC_RANDOM_DIRECTION BIT(10)
143 #define NFC_ECC_MODE_MSK GENMASK(15, 12)
144 #define NFC_ECC_MODE(x) ((x) << 12)
145 #define NFC_RANDOM_SEED_MSK GENMASK(30, 16)
146 #define NFC_RANDOM_SEED(x) ((x) << 16)
147
148 /* define bit use in NFC_ECC_ST */
149 #define NFC_ECC_ERR(x) BIT(x)
150 #define NFC_ECC_ERR_MSK GENMASK(15, 0)
151 #define NFC_ECC_PAT_FOUND(x) BIT(x + 16)
152 #define NFC_ECC_ERR_CNT(b, x) (((x) >> (((b) % 4) * 8)) & 0xff)
153
154 #define NFC_DEFAULT_TIMEOUT_MS 1000
155
156 #define NFC_SRAM_SIZE 1024
157
158 #define NFC_MAX_CS 7
159
160 /**
161 * struct sunxi_nand_chip_sel - stores information related to NAND Chip Select
162 *
163 * @cs: the NAND CS id used to communicate with a NAND Chip
164 * @rb: the Ready/Busy pin ID. -1 means no R/B pin connected to the NFC
165 */
166 struct sunxi_nand_chip_sel {
167 u8 cs;
168 s8 rb;
169 };
170
171 /**
172 * struct sunxi_nand_hw_ecc - stores information related to HW ECC support
173 *
174 * @ecc_ctl: ECC_CTL register value for this NAND chip
175 */
176 struct sunxi_nand_hw_ecc {
177 u32 ecc_ctl;
178 };
179
180 /**
181 * struct sunxi_nand_chip - stores NAND chip device related information
182 *
183 * @node: used to store NAND chips into a list
184 * @nand: base NAND chip structure
185 * @ecc: ECC controller structure
186 * @clk_rate: clk_rate required for this NAND chip
187 * @timing_cfg: TIMING_CFG register value for this NAND chip
188 * @timing_ctl: TIMING_CTL register value for this NAND chip
189 * @nsels: number of CS lines required by the NAND chip
190 * @sels: array of CS lines descriptions
191 */
192 struct sunxi_nand_chip {
193 struct list_head node;
194 struct nand_chip nand;
195 struct sunxi_nand_hw_ecc ecc;
196 unsigned long clk_rate;
197 u32 timing_cfg;
198 u32 timing_ctl;
199 int nsels;
200 struct sunxi_nand_chip_sel sels[];
201 };
202
to_sunxi_nand(struct nand_chip * nand)203 static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
204 {
205 return container_of(nand, struct sunxi_nand_chip, nand);
206 }
207
208 /*
209 * NAND Controller capabilities structure: stores NAND controller capabilities
210 * for distinction between compatible strings.
211 *
212 * @has_mdma: Use mbus dma mode, otherwise general dma
213 * through MBUS on A23/A33 needs extra configuration.
214 * @reg_io_data: I/O data register
215 * @dma_maxburst: DMA maxburst
216 */
217 struct sunxi_nfc_caps {
218 bool has_mdma;
219 unsigned int reg_io_data;
220 unsigned int dma_maxburst;
221 };
222
223 /**
224 * struct sunxi_nfc - stores sunxi NAND controller information
225 *
226 * @controller: base controller structure
227 * @dev: parent device (used to print error messages)
228 * @regs: NAND controller registers
229 * @ahb_clk: NAND controller AHB clock
230 * @mod_clk: NAND controller mod clock
231 * @reset: NAND controller reset line
232 * @assigned_cs: bitmask describing already assigned CS lines
233 * @clk_rate: NAND controller current clock rate
234 * @chips: a list containing all the NAND chips attached to this NAND
235 * controller
236 * @complete: a completion object used to wait for NAND controller events
237 * @dmac: the DMA channel attached to the NAND controller
238 * @caps: NAND Controller capabilities
239 */
240 struct sunxi_nfc {
241 struct nand_controller controller;
242 struct device *dev;
243 void __iomem *regs;
244 struct clk *ahb_clk;
245 struct clk *mod_clk;
246 struct reset_control *reset;
247 unsigned long assigned_cs;
248 unsigned long clk_rate;
249 struct list_head chips;
250 struct completion complete;
251 struct dma_chan *dmac;
252 const struct sunxi_nfc_caps *caps;
253 };
254
to_sunxi_nfc(struct nand_controller * ctrl)255 static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_controller *ctrl)
256 {
257 return container_of(ctrl, struct sunxi_nfc, controller);
258 }
259
sunxi_nfc_interrupt(int irq,void * dev_id)260 static irqreturn_t sunxi_nfc_interrupt(int irq, void *dev_id)
261 {
262 struct sunxi_nfc *nfc = dev_id;
263 u32 st = readl(nfc->regs + NFC_REG_ST);
264 u32 ien = readl(nfc->regs + NFC_REG_INT);
265
266 if (!(ien & st))
267 return IRQ_NONE;
268
269 if ((ien & st) == ien)
270 complete(&nfc->complete);
271
272 writel(st & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
273 writel(~st & ien & NFC_INT_MASK, nfc->regs + NFC_REG_INT);
274
275 return IRQ_HANDLED;
276 }
277
sunxi_nfc_wait_events(struct sunxi_nfc * nfc,u32 events,bool use_polling,unsigned int timeout_ms)278 static int sunxi_nfc_wait_events(struct sunxi_nfc *nfc, u32 events,
279 bool use_polling, unsigned int timeout_ms)
280 {
281 int ret;
282
283 if (events & ~NFC_INT_MASK)
284 return -EINVAL;
285
286 if (!timeout_ms)
287 timeout_ms = NFC_DEFAULT_TIMEOUT_MS;
288
289 if (!use_polling) {
290 init_completion(&nfc->complete);
291
292 writel(events, nfc->regs + NFC_REG_INT);
293
294 ret = wait_for_completion_timeout(&nfc->complete,
295 msecs_to_jiffies(timeout_ms));
296 if (!ret)
297 ret = -ETIMEDOUT;
298 else
299 ret = 0;
300
301 writel(0, nfc->regs + NFC_REG_INT);
302 } else {
303 u32 status;
304
305 ret = readl_poll_timeout(nfc->regs + NFC_REG_ST, status,
306 (status & events) == events, 1,
307 timeout_ms * 1000);
308 }
309
310 writel(events & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
311
312 if (ret)
313 dev_err(nfc->dev, "wait interrupt timedout\n");
314
315 return ret;
316 }
317
sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc * nfc)318 static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc)
319 {
320 u32 status;
321 int ret;
322
323 ret = readl_poll_timeout(nfc->regs + NFC_REG_ST, status,
324 !(status & NFC_CMD_FIFO_STATUS), 1,
325 NFC_DEFAULT_TIMEOUT_MS * 1000);
326 if (ret)
327 dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n");
328
329 return ret;
330 }
331
sunxi_nfc_rst(struct sunxi_nfc * nfc)332 static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
333 {
334 u32 ctl;
335 int ret;
336
337 writel(0, nfc->regs + NFC_REG_ECC_CTL);
338 writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
339
340 ret = readl_poll_timeout(nfc->regs + NFC_REG_CTL, ctl,
341 !(ctl & NFC_RESET), 1,
342 NFC_DEFAULT_TIMEOUT_MS * 1000);
343 if (ret)
344 dev_err(nfc->dev, "wait for NAND controller reset timedout\n");
345
346 return ret;
347 }
348
sunxi_nfc_dma_op_prepare(struct sunxi_nfc * nfc,const void * buf,int chunksize,int nchunks,enum dma_data_direction ddir,struct scatterlist * sg)349 static int sunxi_nfc_dma_op_prepare(struct sunxi_nfc *nfc, const void *buf,
350 int chunksize, int nchunks,
351 enum dma_data_direction ddir,
352 struct scatterlist *sg)
353 {
354 struct dma_async_tx_descriptor *dmad;
355 enum dma_transfer_direction tdir;
356 dma_cookie_t dmat;
357 int ret;
358
359 if (ddir == DMA_FROM_DEVICE)
360 tdir = DMA_DEV_TO_MEM;
361 else
362 tdir = DMA_MEM_TO_DEV;
363
364 sg_init_one(sg, buf, nchunks * chunksize);
365 ret = dma_map_sg(nfc->dev, sg, 1, ddir);
366 if (!ret)
367 return -ENOMEM;
368
369 if (!nfc->caps->has_mdma) {
370 dmad = dmaengine_prep_slave_sg(nfc->dmac, sg, 1, tdir, DMA_CTRL_ACK);
371 if (!dmad) {
372 ret = -EINVAL;
373 goto err_unmap_buf;
374 }
375 }
376
377 writel(readl(nfc->regs + NFC_REG_CTL) | NFC_RAM_METHOD,
378 nfc->regs + NFC_REG_CTL);
379 writel(nchunks, nfc->regs + NFC_REG_SECTOR_NUM);
380 writel(chunksize, nfc->regs + NFC_REG_CNT);
381
382 if (nfc->caps->has_mdma) {
383 writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_DMA_TYPE_NORMAL,
384 nfc->regs + NFC_REG_CTL);
385 writel(chunksize * nchunks, nfc->regs + NFC_REG_MDMA_CNT);
386 writel(sg_dma_address(sg), nfc->regs + NFC_REG_MDMA_ADDR);
387 } else {
388 dmat = dmaengine_submit(dmad);
389
390 ret = dma_submit_error(dmat);
391 if (ret)
392 goto err_clr_dma_flag;
393 }
394
395 return 0;
396
397 err_clr_dma_flag:
398 writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD,
399 nfc->regs + NFC_REG_CTL);
400
401 err_unmap_buf:
402 dma_unmap_sg(nfc->dev, sg, 1, ddir);
403 return ret;
404 }
405
sunxi_nfc_dma_op_cleanup(struct sunxi_nfc * nfc,enum dma_data_direction ddir,struct scatterlist * sg)406 static void sunxi_nfc_dma_op_cleanup(struct sunxi_nfc *nfc,
407 enum dma_data_direction ddir,
408 struct scatterlist *sg)
409 {
410 dma_unmap_sg(nfc->dev, sg, 1, ddir);
411 writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD,
412 nfc->regs + NFC_REG_CTL);
413 }
414
sunxi_nfc_select_chip(struct nand_chip * nand,unsigned int cs)415 static void sunxi_nfc_select_chip(struct nand_chip *nand, unsigned int cs)
416 {
417 struct mtd_info *mtd = nand_to_mtd(nand);
418 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
419 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
420 struct sunxi_nand_chip_sel *sel;
421 u32 ctl;
422
423 if (cs >= sunxi_nand->nsels)
424 return;
425
426 ctl = readl(nfc->regs + NFC_REG_CTL) &
427 ~(NFC_PAGE_SHIFT_MSK | NFC_CE_SEL_MSK | NFC_RB_SEL_MSK | NFC_EN);
428
429 sel = &sunxi_nand->sels[cs];
430 ctl |= NFC_CE_SEL(sel->cs) | NFC_EN | NFC_PAGE_SHIFT(nand->page_shift);
431 if (sel->rb >= 0)
432 ctl |= NFC_RB_SEL(sel->rb);
433
434 writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
435
436 if (nfc->clk_rate != sunxi_nand->clk_rate) {
437 clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate);
438 nfc->clk_rate = sunxi_nand->clk_rate;
439 }
440
441 writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
442 writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
443 writel(ctl, nfc->regs + NFC_REG_CTL);
444 }
445
sunxi_nfc_read_buf(struct nand_chip * nand,uint8_t * buf,int len)446 static void sunxi_nfc_read_buf(struct nand_chip *nand, uint8_t *buf, int len)
447 {
448 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
449 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
450 int ret;
451 int cnt;
452 int offs = 0;
453 u32 tmp;
454
455 while (len > offs) {
456 bool poll = false;
457
458 cnt = min(len - offs, NFC_SRAM_SIZE);
459
460 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
461 if (ret)
462 break;
463
464 writel(cnt, nfc->regs + NFC_REG_CNT);
465 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
466 writel(tmp, nfc->regs + NFC_REG_CMD);
467
468 /* Arbitrary limit for polling mode */
469 if (cnt < 64)
470 poll = true;
471
472 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, poll, 0);
473 if (ret)
474 break;
475
476 if (buf)
477 memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
478 cnt);
479 offs += cnt;
480 }
481 }
482
sunxi_nfc_write_buf(struct nand_chip * nand,const uint8_t * buf,int len)483 static void sunxi_nfc_write_buf(struct nand_chip *nand, const uint8_t *buf,
484 int len)
485 {
486 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
487 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
488 int ret;
489 int cnt;
490 int offs = 0;
491 u32 tmp;
492
493 while (len > offs) {
494 bool poll = false;
495
496 cnt = min(len - offs, NFC_SRAM_SIZE);
497
498 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
499 if (ret)
500 break;
501
502 writel(cnt, nfc->regs + NFC_REG_CNT);
503 memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
504 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
505 NFC_ACCESS_DIR;
506 writel(tmp, nfc->regs + NFC_REG_CMD);
507
508 /* Arbitrary limit for polling mode */
509 if (cnt < 64)
510 poll = true;
511
512 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, poll, 0);
513 if (ret)
514 break;
515
516 offs += cnt;
517 }
518 }
519
520 /* These seed values have been extracted from Allwinner's BSP */
521 static const u16 sunxi_nfc_randomizer_page_seeds[] = {
522 0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
523 0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
524 0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
525 0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
526 0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
527 0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
528 0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
529 0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
530 0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
531 0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
532 0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
533 0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
534 0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
535 0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
536 0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
537 0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
538 };
539
540 /*
541 * sunxi_nfc_randomizer_ecc512_seeds and sunxi_nfc_randomizer_ecc1024_seeds
542 * have been generated using
543 * sunxi_nfc_randomizer_step(seed, (step_size * 8) + 15), which is what
544 * the randomizer engine does internally before de/scrambling OOB data.
545 *
546 * Those tables are statically defined to avoid calculating randomizer state
547 * at runtime.
548 */
549 static const u16 sunxi_nfc_randomizer_ecc512_seeds[] = {
550 0x3346, 0x367f, 0x1f18, 0x769a, 0x4f64, 0x068c, 0x2ef1, 0x6b64,
551 0x28a9, 0x15d7, 0x30f8, 0x3659, 0x53db, 0x7c5f, 0x71d4, 0x4409,
552 0x26eb, 0x03cc, 0x655d, 0x47d4, 0x4daa, 0x0877, 0x712d, 0x3617,
553 0x3264, 0x49aa, 0x7f9e, 0x588e, 0x4fbc, 0x7176, 0x7f91, 0x6c6d,
554 0x4b95, 0x5fb7, 0x3844, 0x4037, 0x0184, 0x081b, 0x0ee8, 0x5b91,
555 0x293d, 0x1f71, 0x0e6f, 0x402b, 0x5122, 0x1e52, 0x22be, 0x3d2d,
556 0x75bc, 0x7c60, 0x6291, 0x1a2f, 0x61d4, 0x74aa, 0x4140, 0x29ab,
557 0x472d, 0x2852, 0x017e, 0x15e8, 0x5ec2, 0x17cf, 0x7d0f, 0x06b8,
558 0x117a, 0x6b94, 0x789b, 0x3126, 0x6ac5, 0x5be7, 0x150f, 0x51f8,
559 0x7889, 0x0aa5, 0x663d, 0x77e8, 0x0b87, 0x3dcb, 0x360d, 0x218b,
560 0x512f, 0x7dc9, 0x6a4d, 0x630a, 0x3547, 0x1dd2, 0x5aea, 0x69a5,
561 0x7bfa, 0x5e4f, 0x1519, 0x6430, 0x3a0e, 0x5eb3, 0x5425, 0x0c7a,
562 0x5540, 0x3670, 0x63c1, 0x31e9, 0x5a39, 0x2de7, 0x5979, 0x2891,
563 0x1562, 0x014b, 0x5b05, 0x2756, 0x5a34, 0x13aa, 0x6cb5, 0x2c36,
564 0x5e72, 0x1306, 0x0861, 0x15ef, 0x1ee8, 0x5a37, 0x7ac4, 0x45dd,
565 0x44c4, 0x7266, 0x2f41, 0x3ccc, 0x045e, 0x7d40, 0x7c66, 0x0fa0,
566 };
567
568 static const u16 sunxi_nfc_randomizer_ecc1024_seeds[] = {
569 0x2cf5, 0x35f1, 0x63a4, 0x5274, 0x2bd2, 0x778b, 0x7285, 0x32b6,
570 0x6a5c, 0x70d6, 0x757d, 0x6769, 0x5375, 0x1e81, 0x0cf3, 0x3982,
571 0x6787, 0x042a, 0x6c49, 0x1925, 0x56a8, 0x40a9, 0x063e, 0x7bd9,
572 0x4dbf, 0x55ec, 0x672e, 0x7334, 0x5185, 0x4d00, 0x232a, 0x7e07,
573 0x445d, 0x6b92, 0x528f, 0x4255, 0x53ba, 0x7d82, 0x2a2e, 0x3a4e,
574 0x75eb, 0x450c, 0x6844, 0x1b5d, 0x581a, 0x4cc6, 0x0379, 0x37b2,
575 0x419f, 0x0e92, 0x6b27, 0x5624, 0x01e3, 0x07c1, 0x44a5, 0x130c,
576 0x13e8, 0x5910, 0x0876, 0x60c5, 0x54e3, 0x5b7f, 0x2269, 0x509f,
577 0x7665, 0x36fd, 0x3e9a, 0x0579, 0x6295, 0x14ef, 0x0a81, 0x1bcc,
578 0x4b16, 0x64db, 0x0514, 0x4f07, 0x0591, 0x3576, 0x6853, 0x0d9e,
579 0x259f, 0x38b7, 0x64fb, 0x3094, 0x4693, 0x6ddd, 0x29bb, 0x0bc8,
580 0x3f47, 0x490e, 0x0c0e, 0x7933, 0x3c9e, 0x5840, 0x398d, 0x3e68,
581 0x4af1, 0x71f5, 0x57cf, 0x1121, 0x64eb, 0x3579, 0x15ac, 0x584d,
582 0x5f2a, 0x47e2, 0x6528, 0x6eac, 0x196e, 0x6b96, 0x0450, 0x0179,
583 0x609c, 0x06e1, 0x4626, 0x42c7, 0x273e, 0x486f, 0x0705, 0x1601,
584 0x145b, 0x407e, 0x062b, 0x57a5, 0x53f9, 0x5659, 0x4410, 0x3ccd,
585 };
586
sunxi_nfc_randomizer_step(u16 state,int count)587 static u16 sunxi_nfc_randomizer_step(u16 state, int count)
588 {
589 state &= 0x7fff;
590
591 /*
592 * This loop is just a simple implementation of a Fibonacci LFSR using
593 * the x16 + x15 + 1 polynomial.
594 */
595 while (count--)
596 state = ((state >> 1) |
597 (((state ^ (state >> 1)) & 1) << 14)) & 0x7fff;
598
599 return state;
600 }
601
sunxi_nfc_randomizer_state(struct nand_chip * nand,int page,bool ecc)602 static u16 sunxi_nfc_randomizer_state(struct nand_chip *nand, int page,
603 bool ecc)
604 {
605 struct mtd_info *mtd = nand_to_mtd(nand);
606 const u16 *seeds = sunxi_nfc_randomizer_page_seeds;
607 int mod = mtd_div_by_ws(mtd->erasesize, mtd);
608
609 if (mod > ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds))
610 mod = ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds);
611
612 if (ecc) {
613 if (mtd->ecc_step_size == 512)
614 seeds = sunxi_nfc_randomizer_ecc512_seeds;
615 else
616 seeds = sunxi_nfc_randomizer_ecc1024_seeds;
617 }
618
619 return seeds[page % mod];
620 }
621
sunxi_nfc_randomizer_config(struct nand_chip * nand,int page,bool ecc)622 static void sunxi_nfc_randomizer_config(struct nand_chip *nand, int page,
623 bool ecc)
624 {
625 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
626 u32 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
627 u16 state;
628
629 if (!(nand->options & NAND_NEED_SCRAMBLING))
630 return;
631
632 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
633 state = sunxi_nfc_randomizer_state(nand, page, ecc);
634 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_SEED_MSK;
635 writel(ecc_ctl | NFC_RANDOM_SEED(state), nfc->regs + NFC_REG_ECC_CTL);
636 }
637
sunxi_nfc_randomizer_enable(struct nand_chip * nand)638 static void sunxi_nfc_randomizer_enable(struct nand_chip *nand)
639 {
640 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
641
642 if (!(nand->options & NAND_NEED_SCRAMBLING))
643 return;
644
645 writel(readl(nfc->regs + NFC_REG_ECC_CTL) | NFC_RANDOM_EN,
646 nfc->regs + NFC_REG_ECC_CTL);
647 }
648
sunxi_nfc_randomizer_disable(struct nand_chip * nand)649 static void sunxi_nfc_randomizer_disable(struct nand_chip *nand)
650 {
651 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
652
653 if (!(nand->options & NAND_NEED_SCRAMBLING))
654 return;
655
656 writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_EN,
657 nfc->regs + NFC_REG_ECC_CTL);
658 }
659
sunxi_nfc_randomize_bbm(struct nand_chip * nand,int page,u8 * bbm)660 static void sunxi_nfc_randomize_bbm(struct nand_chip *nand, int page, u8 *bbm)
661 {
662 u16 state = sunxi_nfc_randomizer_state(nand, page, true);
663
664 bbm[0] ^= state;
665 bbm[1] ^= sunxi_nfc_randomizer_step(state, 8);
666 }
667
sunxi_nfc_randomizer_write_buf(struct nand_chip * nand,const uint8_t * buf,int len,bool ecc,int page)668 static void sunxi_nfc_randomizer_write_buf(struct nand_chip *nand,
669 const uint8_t *buf, int len,
670 bool ecc, int page)
671 {
672 sunxi_nfc_randomizer_config(nand, page, ecc);
673 sunxi_nfc_randomizer_enable(nand);
674 sunxi_nfc_write_buf(nand, buf, len);
675 sunxi_nfc_randomizer_disable(nand);
676 }
677
sunxi_nfc_randomizer_read_buf(struct nand_chip * nand,uint8_t * buf,int len,bool ecc,int page)678 static void sunxi_nfc_randomizer_read_buf(struct nand_chip *nand, uint8_t *buf,
679 int len, bool ecc, int page)
680 {
681 sunxi_nfc_randomizer_config(nand, page, ecc);
682 sunxi_nfc_randomizer_enable(nand);
683 sunxi_nfc_read_buf(nand, buf, len);
684 sunxi_nfc_randomizer_disable(nand);
685 }
686
sunxi_nfc_hw_ecc_enable(struct nand_chip * nand)687 static void sunxi_nfc_hw_ecc_enable(struct nand_chip *nand)
688 {
689 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
690 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
691
692 writel(sunxi_nand->ecc.ecc_ctl, nfc->regs + NFC_REG_ECC_CTL);
693 }
694
sunxi_nfc_hw_ecc_disable(struct nand_chip * nand)695 static void sunxi_nfc_hw_ecc_disable(struct nand_chip *nand)
696 {
697 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
698
699 writel(0, nfc->regs + NFC_REG_ECC_CTL);
700 }
701
sunxi_nfc_user_data_to_buf(u32 user_data,u8 * buf)702 static inline void sunxi_nfc_user_data_to_buf(u32 user_data, u8 *buf)
703 {
704 buf[0] = user_data;
705 buf[1] = user_data >> 8;
706 buf[2] = user_data >> 16;
707 buf[3] = user_data >> 24;
708 }
709
sunxi_nfc_buf_to_user_data(const u8 * buf)710 static inline u32 sunxi_nfc_buf_to_user_data(const u8 *buf)
711 {
712 return buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24);
713 }
714
sunxi_nfc_hw_ecc_get_prot_oob_bytes(struct nand_chip * nand,u8 * oob,int step,bool bbm,int page)715 static void sunxi_nfc_hw_ecc_get_prot_oob_bytes(struct nand_chip *nand, u8 *oob,
716 int step, bool bbm, int page)
717 {
718 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
719
720 sunxi_nfc_user_data_to_buf(readl(nfc->regs + NFC_REG_USER_DATA(step)),
721 oob);
722
723 /* De-randomize the Bad Block Marker. */
724 if (bbm && (nand->options & NAND_NEED_SCRAMBLING))
725 sunxi_nfc_randomize_bbm(nand, page, oob);
726 }
727
sunxi_nfc_hw_ecc_set_prot_oob_bytes(struct nand_chip * nand,const u8 * oob,int step,bool bbm,int page)728 static void sunxi_nfc_hw_ecc_set_prot_oob_bytes(struct nand_chip *nand,
729 const u8 *oob, int step,
730 bool bbm, int page)
731 {
732 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
733 u8 user_data[4];
734
735 /* Randomize the Bad Block Marker. */
736 if (bbm && (nand->options & NAND_NEED_SCRAMBLING)) {
737 memcpy(user_data, oob, sizeof(user_data));
738 sunxi_nfc_randomize_bbm(nand, page, user_data);
739 oob = user_data;
740 }
741
742 writel(sunxi_nfc_buf_to_user_data(oob),
743 nfc->regs + NFC_REG_USER_DATA(step));
744 }
745
sunxi_nfc_hw_ecc_update_stats(struct nand_chip * nand,unsigned int * max_bitflips,int ret)746 static void sunxi_nfc_hw_ecc_update_stats(struct nand_chip *nand,
747 unsigned int *max_bitflips, int ret)
748 {
749 struct mtd_info *mtd = nand_to_mtd(nand);
750
751 if (ret < 0) {
752 mtd->ecc_stats.failed++;
753 } else {
754 mtd->ecc_stats.corrected += ret;
755 *max_bitflips = max_t(unsigned int, *max_bitflips, ret);
756 }
757 }
758
sunxi_nfc_hw_ecc_correct(struct nand_chip * nand,u8 * data,u8 * oob,int step,u32 status,bool * erased)759 static int sunxi_nfc_hw_ecc_correct(struct nand_chip *nand, u8 *data, u8 *oob,
760 int step, u32 status, bool *erased)
761 {
762 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
763 struct nand_ecc_ctrl *ecc = &nand->ecc;
764 u32 tmp;
765
766 *erased = false;
767
768 if (status & NFC_ECC_ERR(step))
769 return -EBADMSG;
770
771 if (status & NFC_ECC_PAT_FOUND(step)) {
772 u8 pattern;
773
774 if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID) & 0x1))) {
775 pattern = 0x0;
776 } else {
777 pattern = 0xff;
778 *erased = true;
779 }
780
781 if (data)
782 memset(data, pattern, ecc->size);
783
784 if (oob)
785 memset(oob, pattern, ecc->bytes + 4);
786
787 return 0;
788 }
789
790 tmp = readl(nfc->regs + NFC_REG_ECC_ERR_CNT(step));
791
792 return NFC_ECC_ERR_CNT(step, tmp);
793 }
794
sunxi_nfc_hw_ecc_read_chunk(struct nand_chip * nand,u8 * data,int data_off,u8 * oob,int oob_off,int * cur_off,unsigned int * max_bitflips,bool bbm,bool oob_required,int page)795 static int sunxi_nfc_hw_ecc_read_chunk(struct nand_chip *nand,
796 u8 *data, int data_off,
797 u8 *oob, int oob_off,
798 int *cur_off,
799 unsigned int *max_bitflips,
800 bool bbm, bool oob_required, int page)
801 {
802 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
803 struct nand_ecc_ctrl *ecc = &nand->ecc;
804 int raw_mode = 0;
805 bool erased;
806 int ret;
807
808 if (*cur_off != data_off)
809 nand_change_read_column_op(nand, data_off, NULL, 0, false);
810
811 sunxi_nfc_randomizer_read_buf(nand, NULL, ecc->size, false, page);
812
813 if (data_off + ecc->size != oob_off)
814 nand_change_read_column_op(nand, oob_off, NULL, 0, false);
815
816 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
817 if (ret)
818 return ret;
819
820 sunxi_nfc_randomizer_config(nand, page, false);
821 sunxi_nfc_randomizer_enable(nand);
822 writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP,
823 nfc->regs + NFC_REG_CMD);
824
825 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, false, 0);
826 sunxi_nfc_randomizer_disable(nand);
827 if (ret)
828 return ret;
829
830 *cur_off = oob_off + ecc->bytes + 4;
831
832 ret = sunxi_nfc_hw_ecc_correct(nand, data, oob_required ? oob : NULL, 0,
833 readl(nfc->regs + NFC_REG_ECC_ST),
834 &erased);
835 if (erased)
836 return 1;
837
838 if (ret < 0) {
839 /*
840 * Re-read the data with the randomizer disabled to identify
841 * bitflips in erased pages.
842 */
843 if (nand->options & NAND_NEED_SCRAMBLING)
844 nand_change_read_column_op(nand, data_off, data,
845 ecc->size, false);
846 else
847 memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE,
848 ecc->size);
849
850 nand_change_read_column_op(nand, oob_off, oob, ecc->bytes + 4,
851 false);
852
853 ret = nand_check_erased_ecc_chunk(data, ecc->size,
854 oob, ecc->bytes + 4,
855 NULL, 0, ecc->strength);
856 if (ret >= 0)
857 raw_mode = 1;
858 } else {
859 memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, ecc->size);
860
861 if (oob_required) {
862 nand_change_read_column_op(nand, oob_off, NULL, 0,
863 false);
864 sunxi_nfc_randomizer_read_buf(nand, oob, ecc->bytes + 4,
865 true, page);
866
867 sunxi_nfc_hw_ecc_get_prot_oob_bytes(nand, oob, 0,
868 bbm, page);
869 }
870 }
871
872 sunxi_nfc_hw_ecc_update_stats(nand, max_bitflips, ret);
873
874 return raw_mode;
875 }
876
sunxi_nfc_hw_ecc_read_extra_oob(struct nand_chip * nand,u8 * oob,int * cur_off,bool randomize,int page)877 static void sunxi_nfc_hw_ecc_read_extra_oob(struct nand_chip *nand,
878 u8 *oob, int *cur_off,
879 bool randomize, int page)
880 {
881 struct mtd_info *mtd = nand_to_mtd(nand);
882 struct nand_ecc_ctrl *ecc = &nand->ecc;
883 int offset = ((ecc->bytes + 4) * ecc->steps);
884 int len = mtd->oobsize - offset;
885
886 if (len <= 0)
887 return;
888
889 if (!cur_off || *cur_off != offset)
890 nand_change_read_column_op(nand, mtd->writesize, NULL, 0,
891 false);
892
893 if (!randomize)
894 sunxi_nfc_read_buf(nand, oob + offset, len);
895 else
896 sunxi_nfc_randomizer_read_buf(nand, oob + offset, len,
897 false, page);
898
899 if (cur_off)
900 *cur_off = mtd->oobsize + mtd->writesize;
901 }
902
sunxi_nfc_hw_ecc_read_chunks_dma(struct nand_chip * nand,uint8_t * buf,int oob_required,int page,int nchunks)903 static int sunxi_nfc_hw_ecc_read_chunks_dma(struct nand_chip *nand, uint8_t *buf,
904 int oob_required, int page,
905 int nchunks)
906 {
907 bool randomized = nand->options & NAND_NEED_SCRAMBLING;
908 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
909 struct mtd_info *mtd = nand_to_mtd(nand);
910 struct nand_ecc_ctrl *ecc = &nand->ecc;
911 unsigned int max_bitflips = 0;
912 int ret, i, raw_mode = 0;
913 struct scatterlist sg;
914 u32 status, wait;
915
916 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
917 if (ret)
918 return ret;
919
920 ret = sunxi_nfc_dma_op_prepare(nfc, buf, ecc->size, nchunks,
921 DMA_FROM_DEVICE, &sg);
922 if (ret)
923 return ret;
924
925 sunxi_nfc_hw_ecc_enable(nand);
926 sunxi_nfc_randomizer_config(nand, page, false);
927 sunxi_nfc_randomizer_enable(nand);
928
929 writel((NAND_CMD_RNDOUTSTART << 16) | (NAND_CMD_RNDOUT << 8) |
930 NAND_CMD_READSTART, nfc->regs + NFC_REG_RCMD_SET);
931
932 wait = NFC_CMD_INT_FLAG;
933
934 if (nfc->caps->has_mdma)
935 wait |= NFC_DMA_INT_FLAG;
936 else
937 dma_async_issue_pending(nfc->dmac);
938
939 writel(NFC_PAGE_OP | NFC_DATA_SWAP_METHOD | NFC_DATA_TRANS,
940 nfc->regs + NFC_REG_CMD);
941
942 ret = sunxi_nfc_wait_events(nfc, wait, false, 0);
943 if (ret && !nfc->caps->has_mdma)
944 dmaengine_terminate_all(nfc->dmac);
945
946 sunxi_nfc_randomizer_disable(nand);
947 sunxi_nfc_hw_ecc_disable(nand);
948
949 sunxi_nfc_dma_op_cleanup(nfc, DMA_FROM_DEVICE, &sg);
950
951 if (ret)
952 return ret;
953
954 status = readl(nfc->regs + NFC_REG_ECC_ST);
955
956 for (i = 0; i < nchunks; i++) {
957 int data_off = i * ecc->size;
958 int oob_off = i * (ecc->bytes + 4);
959 u8 *data = buf + data_off;
960 u8 *oob = nand->oob_poi + oob_off;
961 bool erased;
962
963 ret = sunxi_nfc_hw_ecc_correct(nand, randomized ? data : NULL,
964 oob_required ? oob : NULL,
965 i, status, &erased);
966
967 /* ECC errors are handled in the second loop. */
968 if (ret < 0)
969 continue;
970
971 if (oob_required && !erased) {
972 /* TODO: use DMA to retrieve OOB */
973 nand_change_read_column_op(nand,
974 mtd->writesize + oob_off,
975 oob, ecc->bytes + 4, false);
976
977 sunxi_nfc_hw_ecc_get_prot_oob_bytes(nand, oob, i,
978 !i, page);
979 }
980
981 if (erased)
982 raw_mode = 1;
983
984 sunxi_nfc_hw_ecc_update_stats(nand, &max_bitflips, ret);
985 }
986
987 if (status & NFC_ECC_ERR_MSK) {
988 for (i = 0; i < nchunks; i++) {
989 int data_off = i * ecc->size;
990 int oob_off = i * (ecc->bytes + 4);
991 u8 *data = buf + data_off;
992 u8 *oob = nand->oob_poi + oob_off;
993
994 if (!(status & NFC_ECC_ERR(i)))
995 continue;
996
997 /*
998 * Re-read the data with the randomizer disabled to
999 * identify bitflips in erased pages.
1000 * TODO: use DMA to read page in raw mode
1001 */
1002 if (randomized)
1003 nand_change_read_column_op(nand, data_off,
1004 data, ecc->size,
1005 false);
1006
1007 /* TODO: use DMA to retrieve OOB */
1008 nand_change_read_column_op(nand,
1009 mtd->writesize + oob_off,
1010 oob, ecc->bytes + 4, false);
1011
1012 ret = nand_check_erased_ecc_chunk(data, ecc->size,
1013 oob, ecc->bytes + 4,
1014 NULL, 0,
1015 ecc->strength);
1016 if (ret >= 0)
1017 raw_mode = 1;
1018
1019 sunxi_nfc_hw_ecc_update_stats(nand, &max_bitflips, ret);
1020 }
1021 }
1022
1023 if (oob_required)
1024 sunxi_nfc_hw_ecc_read_extra_oob(nand, nand->oob_poi,
1025 NULL, !raw_mode,
1026 page);
1027
1028 return max_bitflips;
1029 }
1030
sunxi_nfc_hw_ecc_write_chunk(struct nand_chip * nand,const u8 * data,int data_off,const u8 * oob,int oob_off,int * cur_off,bool bbm,int page)1031 static int sunxi_nfc_hw_ecc_write_chunk(struct nand_chip *nand,
1032 const u8 *data, int data_off,
1033 const u8 *oob, int oob_off,
1034 int *cur_off, bool bbm,
1035 int page)
1036 {
1037 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
1038 struct nand_ecc_ctrl *ecc = &nand->ecc;
1039 int ret;
1040
1041 if (data_off != *cur_off)
1042 nand_change_write_column_op(nand, data_off, NULL, 0, false);
1043
1044 sunxi_nfc_randomizer_write_buf(nand, data, ecc->size, false, page);
1045
1046 if (data_off + ecc->size != oob_off)
1047 nand_change_write_column_op(nand, oob_off, NULL, 0, false);
1048
1049 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
1050 if (ret)
1051 return ret;
1052
1053 sunxi_nfc_randomizer_config(nand, page, false);
1054 sunxi_nfc_randomizer_enable(nand);
1055 sunxi_nfc_hw_ecc_set_prot_oob_bytes(nand, oob, 0, bbm, page);
1056
1057 writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
1058 NFC_ACCESS_DIR | NFC_ECC_OP,
1059 nfc->regs + NFC_REG_CMD);
1060
1061 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, false, 0);
1062 sunxi_nfc_randomizer_disable(nand);
1063 if (ret)
1064 return ret;
1065
1066 *cur_off = oob_off + ecc->bytes + 4;
1067
1068 return 0;
1069 }
1070
sunxi_nfc_hw_ecc_write_extra_oob(struct nand_chip * nand,u8 * oob,int * cur_off,int page)1071 static void sunxi_nfc_hw_ecc_write_extra_oob(struct nand_chip *nand,
1072 u8 *oob, int *cur_off,
1073 int page)
1074 {
1075 struct mtd_info *mtd = nand_to_mtd(nand);
1076 struct nand_ecc_ctrl *ecc = &nand->ecc;
1077 int offset = ((ecc->bytes + 4) * ecc->steps);
1078 int len = mtd->oobsize - offset;
1079
1080 if (len <= 0)
1081 return;
1082
1083 if (!cur_off || *cur_off != offset)
1084 nand_change_write_column_op(nand, offset + mtd->writesize,
1085 NULL, 0, false);
1086
1087 sunxi_nfc_randomizer_write_buf(nand, oob + offset, len, false, page);
1088
1089 if (cur_off)
1090 *cur_off = mtd->oobsize + mtd->writesize;
1091 }
1092
sunxi_nfc_hw_ecc_read_page(struct nand_chip * nand,uint8_t * buf,int oob_required,int page)1093 static int sunxi_nfc_hw_ecc_read_page(struct nand_chip *nand, uint8_t *buf,
1094 int oob_required, int page)
1095 {
1096 struct mtd_info *mtd = nand_to_mtd(nand);
1097 struct nand_ecc_ctrl *ecc = &nand->ecc;
1098 unsigned int max_bitflips = 0;
1099 int ret, i, cur_off = 0;
1100 bool raw_mode = false;
1101
1102 sunxi_nfc_select_chip(nand, nand->cur_cs);
1103
1104 nand_read_page_op(nand, page, 0, NULL, 0);
1105
1106 sunxi_nfc_hw_ecc_enable(nand);
1107
1108 for (i = 0; i < ecc->steps; i++) {
1109 int data_off = i * ecc->size;
1110 int oob_off = i * (ecc->bytes + 4);
1111 u8 *data = buf + data_off;
1112 u8 *oob = nand->oob_poi + oob_off;
1113
1114 ret = sunxi_nfc_hw_ecc_read_chunk(nand, data, data_off, oob,
1115 oob_off + mtd->writesize,
1116 &cur_off, &max_bitflips,
1117 !i, oob_required, page);
1118 if (ret < 0)
1119 return ret;
1120 else if (ret)
1121 raw_mode = true;
1122 }
1123
1124 if (oob_required)
1125 sunxi_nfc_hw_ecc_read_extra_oob(nand, nand->oob_poi, &cur_off,
1126 !raw_mode, page);
1127
1128 sunxi_nfc_hw_ecc_disable(nand);
1129
1130 return max_bitflips;
1131 }
1132
sunxi_nfc_hw_ecc_read_page_dma(struct nand_chip * nand,u8 * buf,int oob_required,int page)1133 static int sunxi_nfc_hw_ecc_read_page_dma(struct nand_chip *nand, u8 *buf,
1134 int oob_required, int page)
1135 {
1136 int ret;
1137
1138 sunxi_nfc_select_chip(nand, nand->cur_cs);
1139
1140 nand_read_page_op(nand, page, 0, NULL, 0);
1141
1142 ret = sunxi_nfc_hw_ecc_read_chunks_dma(nand, buf, oob_required, page,
1143 nand->ecc.steps);
1144 if (ret >= 0)
1145 return ret;
1146
1147 /* Fallback to PIO mode */
1148 return sunxi_nfc_hw_ecc_read_page(nand, buf, oob_required, page);
1149 }
1150
sunxi_nfc_hw_ecc_read_subpage(struct nand_chip * nand,u32 data_offs,u32 readlen,u8 * bufpoi,int page)1151 static int sunxi_nfc_hw_ecc_read_subpage(struct nand_chip *nand,
1152 u32 data_offs, u32 readlen,
1153 u8 *bufpoi, int page)
1154 {
1155 struct mtd_info *mtd = nand_to_mtd(nand);
1156 struct nand_ecc_ctrl *ecc = &nand->ecc;
1157 int ret, i, cur_off = 0;
1158 unsigned int max_bitflips = 0;
1159
1160 sunxi_nfc_select_chip(nand, nand->cur_cs);
1161
1162 nand_read_page_op(nand, page, 0, NULL, 0);
1163
1164 sunxi_nfc_hw_ecc_enable(nand);
1165
1166 for (i = data_offs / ecc->size;
1167 i < DIV_ROUND_UP(data_offs + readlen, ecc->size); i++) {
1168 int data_off = i * ecc->size;
1169 int oob_off = i * (ecc->bytes + 4);
1170 u8 *data = bufpoi + data_off;
1171 u8 *oob = nand->oob_poi + oob_off;
1172
1173 ret = sunxi_nfc_hw_ecc_read_chunk(nand, data, data_off,
1174 oob,
1175 oob_off + mtd->writesize,
1176 &cur_off, &max_bitflips, !i,
1177 false, page);
1178 if (ret < 0)
1179 return ret;
1180 }
1181
1182 sunxi_nfc_hw_ecc_disable(nand);
1183
1184 return max_bitflips;
1185 }
1186
sunxi_nfc_hw_ecc_read_subpage_dma(struct nand_chip * nand,u32 data_offs,u32 readlen,u8 * buf,int page)1187 static int sunxi_nfc_hw_ecc_read_subpage_dma(struct nand_chip *nand,
1188 u32 data_offs, u32 readlen,
1189 u8 *buf, int page)
1190 {
1191 int nchunks = DIV_ROUND_UP(data_offs + readlen, nand->ecc.size);
1192 int ret;
1193
1194 sunxi_nfc_select_chip(nand, nand->cur_cs);
1195
1196 nand_read_page_op(nand, page, 0, NULL, 0);
1197
1198 ret = sunxi_nfc_hw_ecc_read_chunks_dma(nand, buf, false, page, nchunks);
1199 if (ret >= 0)
1200 return ret;
1201
1202 /* Fallback to PIO mode */
1203 return sunxi_nfc_hw_ecc_read_subpage(nand, data_offs, readlen,
1204 buf, page);
1205 }
1206
sunxi_nfc_hw_ecc_write_page(struct nand_chip * nand,const uint8_t * buf,int oob_required,int page)1207 static int sunxi_nfc_hw_ecc_write_page(struct nand_chip *nand,
1208 const uint8_t *buf, int oob_required,
1209 int page)
1210 {
1211 struct mtd_info *mtd = nand_to_mtd(nand);
1212 struct nand_ecc_ctrl *ecc = &nand->ecc;
1213 int ret, i, cur_off = 0;
1214
1215 sunxi_nfc_select_chip(nand, nand->cur_cs);
1216
1217 nand_prog_page_begin_op(nand, page, 0, NULL, 0);
1218
1219 sunxi_nfc_hw_ecc_enable(nand);
1220
1221 for (i = 0; i < ecc->steps; i++) {
1222 int data_off = i * ecc->size;
1223 int oob_off = i * (ecc->bytes + 4);
1224 const u8 *data = buf + data_off;
1225 const u8 *oob = nand->oob_poi + oob_off;
1226
1227 ret = sunxi_nfc_hw_ecc_write_chunk(nand, data, data_off, oob,
1228 oob_off + mtd->writesize,
1229 &cur_off, !i, page);
1230 if (ret)
1231 return ret;
1232 }
1233
1234 if (oob_required || (nand->options & NAND_NEED_SCRAMBLING))
1235 sunxi_nfc_hw_ecc_write_extra_oob(nand, nand->oob_poi,
1236 &cur_off, page);
1237
1238 sunxi_nfc_hw_ecc_disable(nand);
1239
1240 return nand_prog_page_end_op(nand);
1241 }
1242
sunxi_nfc_hw_ecc_write_subpage(struct nand_chip * nand,u32 data_offs,u32 data_len,const u8 * buf,int oob_required,int page)1243 static int sunxi_nfc_hw_ecc_write_subpage(struct nand_chip *nand,
1244 u32 data_offs, u32 data_len,
1245 const u8 *buf, int oob_required,
1246 int page)
1247 {
1248 struct mtd_info *mtd = nand_to_mtd(nand);
1249 struct nand_ecc_ctrl *ecc = &nand->ecc;
1250 int ret, i, cur_off = 0;
1251
1252 sunxi_nfc_select_chip(nand, nand->cur_cs);
1253
1254 nand_prog_page_begin_op(nand, page, 0, NULL, 0);
1255
1256 sunxi_nfc_hw_ecc_enable(nand);
1257
1258 for (i = data_offs / ecc->size;
1259 i < DIV_ROUND_UP(data_offs + data_len, ecc->size); i++) {
1260 int data_off = i * ecc->size;
1261 int oob_off = i * (ecc->bytes + 4);
1262 const u8 *data = buf + data_off;
1263 const u8 *oob = nand->oob_poi + oob_off;
1264
1265 ret = sunxi_nfc_hw_ecc_write_chunk(nand, data, data_off, oob,
1266 oob_off + mtd->writesize,
1267 &cur_off, !i, page);
1268 if (ret)
1269 return ret;
1270 }
1271
1272 sunxi_nfc_hw_ecc_disable(nand);
1273
1274 return nand_prog_page_end_op(nand);
1275 }
1276
sunxi_nfc_hw_ecc_write_page_dma(struct nand_chip * nand,const u8 * buf,int oob_required,int page)1277 static int sunxi_nfc_hw_ecc_write_page_dma(struct nand_chip *nand,
1278 const u8 *buf,
1279 int oob_required,
1280 int page)
1281 {
1282 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
1283 struct nand_ecc_ctrl *ecc = &nand->ecc;
1284 struct scatterlist sg;
1285 u32 wait;
1286 int ret, i;
1287
1288 sunxi_nfc_select_chip(nand, nand->cur_cs);
1289
1290 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
1291 if (ret)
1292 return ret;
1293
1294 ret = sunxi_nfc_dma_op_prepare(nfc, buf, ecc->size, ecc->steps,
1295 DMA_TO_DEVICE, &sg);
1296 if (ret)
1297 goto pio_fallback;
1298
1299 for (i = 0; i < ecc->steps; i++) {
1300 const u8 *oob = nand->oob_poi + (i * (ecc->bytes + 4));
1301
1302 sunxi_nfc_hw_ecc_set_prot_oob_bytes(nand, oob, i, !i, page);
1303 }
1304
1305 nand_prog_page_begin_op(nand, page, 0, NULL, 0);
1306
1307 sunxi_nfc_hw_ecc_enable(nand);
1308 sunxi_nfc_randomizer_config(nand, page, false);
1309 sunxi_nfc_randomizer_enable(nand);
1310
1311 writel((NAND_CMD_RNDIN << 8) | NAND_CMD_PAGEPROG,
1312 nfc->regs + NFC_REG_WCMD_SET);
1313
1314 wait = NFC_CMD_INT_FLAG;
1315
1316 if (nfc->caps->has_mdma)
1317 wait |= NFC_DMA_INT_FLAG;
1318 else
1319 dma_async_issue_pending(nfc->dmac);
1320
1321 writel(NFC_PAGE_OP | NFC_DATA_SWAP_METHOD |
1322 NFC_DATA_TRANS | NFC_ACCESS_DIR,
1323 nfc->regs + NFC_REG_CMD);
1324
1325 ret = sunxi_nfc_wait_events(nfc, wait, false, 0);
1326 if (ret && !nfc->caps->has_mdma)
1327 dmaengine_terminate_all(nfc->dmac);
1328
1329 sunxi_nfc_randomizer_disable(nand);
1330 sunxi_nfc_hw_ecc_disable(nand);
1331
1332 sunxi_nfc_dma_op_cleanup(nfc, DMA_TO_DEVICE, &sg);
1333
1334 if (ret)
1335 return ret;
1336
1337 if (oob_required || (nand->options & NAND_NEED_SCRAMBLING))
1338 /* TODO: use DMA to transfer extra OOB bytes ? */
1339 sunxi_nfc_hw_ecc_write_extra_oob(nand, nand->oob_poi,
1340 NULL, page);
1341
1342 return nand_prog_page_end_op(nand);
1343
1344 pio_fallback:
1345 return sunxi_nfc_hw_ecc_write_page(nand, buf, oob_required, page);
1346 }
1347
sunxi_nfc_hw_ecc_read_oob(struct nand_chip * nand,int page)1348 static int sunxi_nfc_hw_ecc_read_oob(struct nand_chip *nand, int page)
1349 {
1350 u8 *buf = nand_get_data_buf(nand);
1351
1352 return nand->ecc.read_page(nand, buf, 1, page);
1353 }
1354
sunxi_nfc_hw_ecc_write_oob(struct nand_chip * nand,int page)1355 static int sunxi_nfc_hw_ecc_write_oob(struct nand_chip *nand, int page)
1356 {
1357 struct mtd_info *mtd = nand_to_mtd(nand);
1358 u8 *buf = nand_get_data_buf(nand);
1359 int ret;
1360
1361 memset(buf, 0xff, mtd->writesize);
1362 ret = nand->ecc.write_page(nand, buf, 1, page);
1363 if (ret)
1364 return ret;
1365
1366 /* Send command to program the OOB data */
1367 return nand_prog_page_end_op(nand);
1368 }
1369
1370 static const s32 tWB_lut[] = {6, 12, 16, 20};
1371 static const s32 tRHW_lut[] = {4, 8, 12, 20};
1372
_sunxi_nand_lookup_timing(const s32 * lut,int lut_size,u32 duration,u32 clk_period)1373 static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
1374 u32 clk_period)
1375 {
1376 u32 clk_cycles = DIV_ROUND_UP(duration, clk_period);
1377 int i;
1378
1379 for (i = 0; i < lut_size; i++) {
1380 if (clk_cycles <= lut[i])
1381 return i;
1382 }
1383
1384 /* Doesn't fit */
1385 return -EINVAL;
1386 }
1387
1388 #define sunxi_nand_lookup_timing(l, p, c) \
1389 _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
1390
sunxi_nfc_setup_interface(struct nand_chip * nand,int csline,const struct nand_interface_config * conf)1391 static int sunxi_nfc_setup_interface(struct nand_chip *nand, int csline,
1392 const struct nand_interface_config *conf)
1393 {
1394 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
1395 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
1396 const struct nand_sdr_timings *timings;
1397 u32 min_clk_period = 0;
1398 s32 tWB, tADL, tWHR, tRHW, tCAD;
1399 long real_clk_rate;
1400
1401 timings = nand_get_sdr_timings(conf);
1402 if (IS_ERR(timings))
1403 return -ENOTSUPP;
1404
1405 /* T1 <=> tCLS */
1406 if (timings->tCLS_min > min_clk_period)
1407 min_clk_period = timings->tCLS_min;
1408
1409 /* T2 <=> tCLH */
1410 if (timings->tCLH_min > min_clk_period)
1411 min_clk_period = timings->tCLH_min;
1412
1413 /* T3 <=> tCS */
1414 if (timings->tCS_min > min_clk_period)
1415 min_clk_period = timings->tCS_min;
1416
1417 /* T4 <=> tCH */
1418 if (timings->tCH_min > min_clk_period)
1419 min_clk_period = timings->tCH_min;
1420
1421 /* T5 <=> tWP */
1422 if (timings->tWP_min > min_clk_period)
1423 min_clk_period = timings->tWP_min;
1424
1425 /* T6 <=> tWH */
1426 if (timings->tWH_min > min_clk_period)
1427 min_clk_period = timings->tWH_min;
1428
1429 /* T7 <=> tALS */
1430 if (timings->tALS_min > min_clk_period)
1431 min_clk_period = timings->tALS_min;
1432
1433 /* T8 <=> tDS */
1434 if (timings->tDS_min > min_clk_period)
1435 min_clk_period = timings->tDS_min;
1436
1437 /* T9 <=> tDH */
1438 if (timings->tDH_min > min_clk_period)
1439 min_clk_period = timings->tDH_min;
1440
1441 /* T10 <=> tRR */
1442 if (timings->tRR_min > (min_clk_period * 3))
1443 min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
1444
1445 /* T11 <=> tALH */
1446 if (timings->tALH_min > min_clk_period)
1447 min_clk_period = timings->tALH_min;
1448
1449 /* T12 <=> tRP */
1450 if (timings->tRP_min > min_clk_period)
1451 min_clk_period = timings->tRP_min;
1452
1453 /* T13 <=> tREH */
1454 if (timings->tREH_min > min_clk_period)
1455 min_clk_period = timings->tREH_min;
1456
1457 /* T14 <=> tRC */
1458 if (timings->tRC_min > (min_clk_period * 2))
1459 min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);
1460
1461 /* T15 <=> tWC */
1462 if (timings->tWC_min > (min_clk_period * 2))
1463 min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
1464
1465 /* T16 - T19 + tCAD */
1466 if (timings->tWB_max > (min_clk_period * 20))
1467 min_clk_period = DIV_ROUND_UP(timings->tWB_max, 20);
1468
1469 if (timings->tADL_min > (min_clk_period * 32))
1470 min_clk_period = DIV_ROUND_UP(timings->tADL_min, 32);
1471
1472 if (timings->tWHR_min > (min_clk_period * 32))
1473 min_clk_period = DIV_ROUND_UP(timings->tWHR_min, 32);
1474
1475 if (timings->tRHW_min > (min_clk_period * 20))
1476 min_clk_period = DIV_ROUND_UP(timings->tRHW_min, 20);
1477
1478 /*
1479 * In non-EDO, tREA should be less than tRP to guarantee that the
1480 * controller does not sample the IO lines too early. Unfortunately,
1481 * the sunxi NAND controller does not allow us to have different
1482 * values for tRP and tREH (tRP = tREH = tRW / 2).
1483 *
1484 * We have 2 options to overcome this limitation:
1485 *
1486 * 1/ Extend tRC to fulfil the tREA <= tRC / 2 constraint
1487 * 2/ Use EDO mode (only works if timings->tRLOH > 0)
1488 */
1489 if (timings->tREA_max > min_clk_period && !timings->tRLOH_min)
1490 min_clk_period = timings->tREA_max;
1491
1492 tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
1493 min_clk_period);
1494 if (tWB < 0) {
1495 dev_err(nfc->dev, "unsupported tWB\n");
1496 return tWB;
1497 }
1498
1499 tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;
1500 if (tADL > 3) {
1501 dev_err(nfc->dev, "unsupported tADL\n");
1502 return -EINVAL;
1503 }
1504
1505 tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
1506 if (tWHR > 3) {
1507 dev_err(nfc->dev, "unsupported tWHR\n");
1508 return -EINVAL;
1509 }
1510
1511 tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min,
1512 min_clk_period);
1513 if (tRHW < 0) {
1514 dev_err(nfc->dev, "unsupported tRHW\n");
1515 return tRHW;
1516 }
1517
1518 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1519 return 0;
1520
1521 /*
1522 * TODO: according to ONFI specs this value only applies for DDR NAND,
1523 * but Allwinner seems to set this to 0x7. Mimic them for now.
1524 */
1525 tCAD = 0x7;
1526
1527 /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */
1528 sunxi_nand->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
1529
1530 /* Convert min_clk_period from picoseconds to nanoseconds */
1531 min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
1532
1533 /*
1534 * Unlike what is stated in Allwinner datasheet, the clk_rate should
1535 * be set to (1 / min_clk_period), and not (2 / min_clk_period).
1536 * This new formula was verified with a scope and validated by
1537 * Allwinner engineers.
1538 */
1539 sunxi_nand->clk_rate = NSEC_PER_SEC / min_clk_period;
1540 real_clk_rate = clk_round_rate(nfc->mod_clk, sunxi_nand->clk_rate);
1541 if (real_clk_rate <= 0) {
1542 dev_err(nfc->dev, "Unable to round clk %lu\n",
1543 sunxi_nand->clk_rate);
1544 return -EINVAL;
1545 }
1546
1547 sunxi_nand->timing_ctl = 0;
1548
1549 /*
1550 * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data
1551 * output cycle timings shall be used if the host drives tRC less than
1552 * 30 ns. We should also use EDO mode if tREA is bigger than tRP.
1553 */
1554 min_clk_period = NSEC_PER_SEC / real_clk_rate;
1555 if (min_clk_period * 2 < 30 || min_clk_period * 1000 < timings->tREA_max)
1556 sunxi_nand->timing_ctl = NFC_TIMING_CTL_EDO;
1557
1558 return 0;
1559 }
1560
sunxi_nand_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)1561 static int sunxi_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
1562 struct mtd_oob_region *oobregion)
1563 {
1564 struct nand_chip *nand = mtd_to_nand(mtd);
1565 struct nand_ecc_ctrl *ecc = &nand->ecc;
1566
1567 if (section >= ecc->steps)
1568 return -ERANGE;
1569
1570 oobregion->offset = section * (ecc->bytes + 4) + 4;
1571 oobregion->length = ecc->bytes;
1572
1573 return 0;
1574 }
1575
sunxi_nand_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)1576 static int sunxi_nand_ooblayout_free(struct mtd_info *mtd, int section,
1577 struct mtd_oob_region *oobregion)
1578 {
1579 struct nand_chip *nand = mtd_to_nand(mtd);
1580 struct nand_ecc_ctrl *ecc = &nand->ecc;
1581
1582 if (section > ecc->steps)
1583 return -ERANGE;
1584
1585 /*
1586 * The first 2 bytes are used for BB markers, hence we
1587 * only have 2 bytes available in the first user data
1588 * section.
1589 */
1590 if (!section && ecc->engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
1591 oobregion->offset = 2;
1592 oobregion->length = 2;
1593
1594 return 0;
1595 }
1596
1597 /*
1598 * The controller does not provide access to OOB bytes
1599 * past the end of the ECC data.
1600 */
1601 if (section == ecc->steps && ecc->engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST)
1602 return -ERANGE;
1603
1604 oobregion->offset = section * (ecc->bytes + 4);
1605
1606 if (section < ecc->steps)
1607 oobregion->length = 4;
1608 else
1609 oobregion->length = mtd->oobsize - oobregion->offset;
1610
1611 return 0;
1612 }
1613
1614 static const struct mtd_ooblayout_ops sunxi_nand_ooblayout_ops = {
1615 .ecc = sunxi_nand_ooblayout_ecc,
1616 .free = sunxi_nand_ooblayout_free,
1617 };
1618
sunxi_nand_hw_ecc_ctrl_init(struct nand_chip * nand,struct nand_ecc_ctrl * ecc,struct device_node * np)1619 static int sunxi_nand_hw_ecc_ctrl_init(struct nand_chip *nand,
1620 struct nand_ecc_ctrl *ecc,
1621 struct device_node *np)
1622 {
1623 static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
1624 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
1625 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
1626 struct mtd_info *mtd = nand_to_mtd(nand);
1627 struct nand_device *nanddev = mtd_to_nanddev(mtd);
1628 int nsectors;
1629 int i;
1630
1631 if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH) {
1632 int bytes;
1633
1634 ecc->size = 1024;
1635 nsectors = mtd->writesize / ecc->size;
1636
1637 /* Reserve 2 bytes for the BBM */
1638 bytes = (mtd->oobsize - 2) / nsectors;
1639
1640 /* 4 non-ECC bytes are added before each ECC bytes section */
1641 bytes -= 4;
1642
1643 /* and bytes has to be even. */
1644 if (bytes % 2)
1645 bytes--;
1646
1647 ecc->strength = bytes * 8 / fls(8 * ecc->size);
1648
1649 for (i = 0; i < ARRAY_SIZE(strengths); i++) {
1650 if (strengths[i] > ecc->strength)
1651 break;
1652 }
1653
1654 if (!i)
1655 ecc->strength = 0;
1656 else
1657 ecc->strength = strengths[i - 1];
1658 }
1659
1660 if (ecc->size != 512 && ecc->size != 1024)
1661 return -EINVAL;
1662
1663 /* Prefer 1k ECC chunk over 512 ones */
1664 if (ecc->size == 512 && mtd->writesize > 512) {
1665 ecc->size = 1024;
1666 ecc->strength *= 2;
1667 }
1668
1669 /* Add ECC info retrieval from DT */
1670 for (i = 0; i < ARRAY_SIZE(strengths); i++) {
1671 if (ecc->strength <= strengths[i]) {
1672 /*
1673 * Update ecc->strength value with the actual strength
1674 * that will be used by the ECC engine.
1675 */
1676 ecc->strength = strengths[i];
1677 break;
1678 }
1679 }
1680
1681 if (i >= ARRAY_SIZE(strengths)) {
1682 dev_err(nfc->dev, "unsupported strength\n");
1683 return -ENOTSUPP;
1684 }
1685
1686 /* HW ECC always request ECC bytes for 1024 bytes blocks */
1687 ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8);
1688
1689 /* HW ECC always work with even numbers of ECC bytes */
1690 ecc->bytes = ALIGN(ecc->bytes, 2);
1691
1692 nsectors = mtd->writesize / ecc->size;
1693
1694 if (mtd->oobsize < ((ecc->bytes + 4) * nsectors))
1695 return -EINVAL;
1696
1697 ecc->read_oob = sunxi_nfc_hw_ecc_read_oob;
1698 ecc->write_oob = sunxi_nfc_hw_ecc_write_oob;
1699 mtd_set_ooblayout(mtd, &sunxi_nand_ooblayout_ops);
1700
1701 if (nfc->dmac || nfc->caps->has_mdma) {
1702 ecc->read_page = sunxi_nfc_hw_ecc_read_page_dma;
1703 ecc->read_subpage = sunxi_nfc_hw_ecc_read_subpage_dma;
1704 ecc->write_page = sunxi_nfc_hw_ecc_write_page_dma;
1705 nand->options |= NAND_USES_DMA;
1706 } else {
1707 ecc->read_page = sunxi_nfc_hw_ecc_read_page;
1708 ecc->read_subpage = sunxi_nfc_hw_ecc_read_subpage;
1709 ecc->write_page = sunxi_nfc_hw_ecc_write_page;
1710 }
1711
1712 /* TODO: support DMA for raw accesses and subpage write */
1713 ecc->write_subpage = sunxi_nfc_hw_ecc_write_subpage;
1714 ecc->read_oob_raw = nand_read_oob_std;
1715 ecc->write_oob_raw = nand_write_oob_std;
1716
1717 sunxi_nand->ecc.ecc_ctl = NFC_ECC_MODE(i) | NFC_ECC_EXCEPTION |
1718 NFC_ECC_PIPELINE | NFC_ECC_EN;
1719
1720 if (ecc->size == 512)
1721 sunxi_nand->ecc.ecc_ctl |= NFC_ECC_BLOCK_512;
1722
1723 return 0;
1724 }
1725
sunxi_nand_attach_chip(struct nand_chip * nand)1726 static int sunxi_nand_attach_chip(struct nand_chip *nand)
1727 {
1728 const struct nand_ecc_props *requirements =
1729 nanddev_get_ecc_requirements(&nand->base);
1730 struct nand_ecc_ctrl *ecc = &nand->ecc;
1731 struct device_node *np = nand_get_flash_node(nand);
1732 int ret;
1733
1734 if (nand->bbt_options & NAND_BBT_USE_FLASH)
1735 nand->bbt_options |= NAND_BBT_NO_OOB;
1736
1737 if (nand->options & NAND_NEED_SCRAMBLING)
1738 nand->options |= NAND_NO_SUBPAGE_WRITE;
1739
1740 nand->options |= NAND_SUBPAGE_READ;
1741
1742 if (!ecc->size) {
1743 ecc->size = requirements->step_size;
1744 ecc->strength = requirements->strength;
1745 }
1746
1747 if (!ecc->size || !ecc->strength)
1748 return -EINVAL;
1749
1750 switch (ecc->engine_type) {
1751 case NAND_ECC_ENGINE_TYPE_ON_HOST:
1752 ret = sunxi_nand_hw_ecc_ctrl_init(nand, ecc, np);
1753 if (ret)
1754 return ret;
1755 break;
1756 case NAND_ECC_ENGINE_TYPE_NONE:
1757 case NAND_ECC_ENGINE_TYPE_SOFT:
1758 break;
1759 default:
1760 return -EINVAL;
1761 }
1762
1763 return 0;
1764 }
1765
sunxi_nfc_exec_subop(struct nand_chip * nand,const struct nand_subop * subop)1766 static int sunxi_nfc_exec_subop(struct nand_chip *nand,
1767 const struct nand_subop *subop)
1768 {
1769 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
1770 u32 cmd = 0, extcmd = 0, cnt = 0, addrs[2] = { };
1771 unsigned int i, j, remaining, start;
1772 void *inbuf = NULL;
1773 int ret;
1774
1775 for (i = 0; i < subop->ninstrs; i++) {
1776 const struct nand_op_instr *instr = &subop->instrs[i];
1777
1778 switch (instr->type) {
1779 case NAND_OP_CMD_INSTR:
1780 if (cmd & NFC_SEND_CMD1) {
1781 if (WARN_ON(cmd & NFC_SEND_CMD2))
1782 return -EINVAL;
1783
1784 cmd |= NFC_SEND_CMD2;
1785 extcmd |= instr->ctx.cmd.opcode;
1786 } else {
1787 cmd |= NFC_SEND_CMD1 |
1788 NFC_CMD(instr->ctx.cmd.opcode);
1789 }
1790 break;
1791
1792 case NAND_OP_ADDR_INSTR:
1793 remaining = nand_subop_get_num_addr_cyc(subop, i);
1794 start = nand_subop_get_addr_start_off(subop, i);
1795 for (j = 0; j < 8 && j + start < remaining; j++) {
1796 u32 addr = instr->ctx.addr.addrs[j + start];
1797
1798 addrs[j / 4] |= addr << (j % 4) * 8;
1799 }
1800
1801 if (j)
1802 cmd |= NFC_SEND_ADR | NFC_ADR_NUM(j);
1803
1804 break;
1805
1806 case NAND_OP_DATA_IN_INSTR:
1807 case NAND_OP_DATA_OUT_INSTR:
1808 start = nand_subop_get_data_start_off(subop, i);
1809 remaining = nand_subop_get_data_len(subop, i);
1810 cnt = min_t(u32, remaining, NFC_SRAM_SIZE);
1811 cmd |= NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
1812
1813 if (instr->type == NAND_OP_DATA_OUT_INSTR) {
1814 cmd |= NFC_ACCESS_DIR;
1815 memcpy_toio(nfc->regs + NFC_RAM0_BASE,
1816 instr->ctx.data.buf.out + start,
1817 cnt);
1818 } else {
1819 inbuf = instr->ctx.data.buf.in + start;
1820 }
1821
1822 break;
1823
1824 case NAND_OP_WAITRDY_INSTR:
1825 cmd |= NFC_WAIT_FLAG;
1826 break;
1827 }
1828 }
1829
1830 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
1831 if (ret)
1832 return ret;
1833
1834 if (cmd & NFC_SEND_ADR) {
1835 writel(addrs[0], nfc->regs + NFC_REG_ADDR_LOW);
1836 writel(addrs[1], nfc->regs + NFC_REG_ADDR_HIGH);
1837 }
1838
1839 if (cmd & NFC_SEND_CMD2)
1840 writel(extcmd,
1841 nfc->regs +
1842 (cmd & NFC_ACCESS_DIR ?
1843 NFC_REG_WCMD_SET : NFC_REG_RCMD_SET));
1844
1845 if (cmd & NFC_DATA_TRANS)
1846 writel(cnt, nfc->regs + NFC_REG_CNT);
1847
1848 writel(cmd, nfc->regs + NFC_REG_CMD);
1849
1850 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG,
1851 !(cmd & NFC_WAIT_FLAG) && cnt < 64,
1852 0);
1853 if (ret)
1854 return ret;
1855
1856 if (inbuf)
1857 memcpy_fromio(inbuf, nfc->regs + NFC_RAM0_BASE, cnt);
1858
1859 return 0;
1860 }
1861
sunxi_nfc_soft_waitrdy(struct nand_chip * nand,const struct nand_subop * subop)1862 static int sunxi_nfc_soft_waitrdy(struct nand_chip *nand,
1863 const struct nand_subop *subop)
1864 {
1865 return nand_soft_waitrdy(nand,
1866 subop->instrs[0].ctx.waitrdy.timeout_ms);
1867 }
1868
1869 static const struct nand_op_parser sunxi_nfc_op_parser = NAND_OP_PARSER(
1870 NAND_OP_PARSER_PATTERN(sunxi_nfc_exec_subop,
1871 NAND_OP_PARSER_PAT_CMD_ELEM(true),
1872 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8),
1873 NAND_OP_PARSER_PAT_CMD_ELEM(true),
1874 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
1875 NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, 1024)),
1876 NAND_OP_PARSER_PATTERN(sunxi_nfc_exec_subop,
1877 NAND_OP_PARSER_PAT_CMD_ELEM(true),
1878 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8),
1879 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(true, 1024),
1880 NAND_OP_PARSER_PAT_CMD_ELEM(true),
1881 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)),
1882 );
1883
1884 static const struct nand_op_parser sunxi_nfc_norb_op_parser = NAND_OP_PARSER(
1885 NAND_OP_PARSER_PATTERN(sunxi_nfc_exec_subop,
1886 NAND_OP_PARSER_PAT_CMD_ELEM(true),
1887 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8),
1888 NAND_OP_PARSER_PAT_CMD_ELEM(true),
1889 NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, 1024)),
1890 NAND_OP_PARSER_PATTERN(sunxi_nfc_exec_subop,
1891 NAND_OP_PARSER_PAT_CMD_ELEM(true),
1892 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8),
1893 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(true, 1024),
1894 NAND_OP_PARSER_PAT_CMD_ELEM(true)),
1895 NAND_OP_PARSER_PATTERN(sunxi_nfc_soft_waitrdy,
1896 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
1897 );
1898
sunxi_nfc_exec_op(struct nand_chip * nand,const struct nand_operation * op,bool check_only)1899 static int sunxi_nfc_exec_op(struct nand_chip *nand,
1900 const struct nand_operation *op, bool check_only)
1901 {
1902 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
1903 const struct nand_op_parser *parser;
1904
1905 if (!check_only)
1906 sunxi_nfc_select_chip(nand, op->cs);
1907
1908 if (sunxi_nand->sels[op->cs].rb >= 0)
1909 parser = &sunxi_nfc_op_parser;
1910 else
1911 parser = &sunxi_nfc_norb_op_parser;
1912
1913 return nand_op_parser_exec_op(nand, parser, op, check_only);
1914 }
1915
1916 static const struct nand_controller_ops sunxi_nand_controller_ops = {
1917 .attach_chip = sunxi_nand_attach_chip,
1918 .setup_interface = sunxi_nfc_setup_interface,
1919 .exec_op = sunxi_nfc_exec_op,
1920 };
1921
sunxi_nand_chips_cleanup(struct sunxi_nfc * nfc)1922 static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc)
1923 {
1924 struct sunxi_nand_chip *sunxi_nand;
1925 struct nand_chip *chip;
1926 int ret;
1927
1928 while (!list_empty(&nfc->chips)) {
1929 sunxi_nand = list_first_entry(&nfc->chips,
1930 struct sunxi_nand_chip,
1931 node);
1932 chip = &sunxi_nand->nand;
1933 ret = mtd_device_unregister(nand_to_mtd(chip));
1934 WARN_ON(ret);
1935 nand_cleanup(chip);
1936 list_del(&sunxi_nand->node);
1937 }
1938 }
1939
sunxi_nand_chip_init(struct device * dev,struct sunxi_nfc * nfc,struct device_node * np)1940 static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
1941 struct device_node *np)
1942 {
1943 struct sunxi_nand_chip *sunxi_nand;
1944 struct mtd_info *mtd;
1945 struct nand_chip *nand;
1946 int nsels;
1947 int ret;
1948 int i;
1949 u32 tmp;
1950
1951 if (!of_get_property(np, "reg", &nsels))
1952 return -EINVAL;
1953
1954 nsels /= sizeof(u32);
1955 if (!nsels) {
1956 dev_err(dev, "invalid reg property size\n");
1957 return -EINVAL;
1958 }
1959
1960 sunxi_nand = devm_kzalloc(dev, struct_size(sunxi_nand, sels, nsels),
1961 GFP_KERNEL);
1962 if (!sunxi_nand)
1963 return -ENOMEM;
1964
1965 sunxi_nand->nsels = nsels;
1966
1967 for (i = 0; i < nsels; i++) {
1968 ret = of_property_read_u32_index(np, "reg", i, &tmp);
1969 if (ret) {
1970 dev_err(dev, "could not retrieve reg property: %d\n",
1971 ret);
1972 return ret;
1973 }
1974
1975 if (tmp > NFC_MAX_CS) {
1976 dev_err(dev,
1977 "invalid reg value: %u (max CS = 7)\n",
1978 tmp);
1979 return -EINVAL;
1980 }
1981
1982 if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1983 dev_err(dev, "CS %d already assigned\n", tmp);
1984 return -EINVAL;
1985 }
1986
1987 sunxi_nand->sels[i].cs = tmp;
1988
1989 if (!of_property_read_u32_index(np, "allwinner,rb", i, &tmp) &&
1990 tmp < 2)
1991 sunxi_nand->sels[i].rb = tmp;
1992 else
1993 sunxi_nand->sels[i].rb = -1;
1994 }
1995
1996 nand = &sunxi_nand->nand;
1997 /* Default tR value specified in the ONFI spec (chapter 4.15.1) */
1998 nand->controller = &nfc->controller;
1999 nand->controller->ops = &sunxi_nand_controller_ops;
2000
2001 /*
2002 * Set the ECC mode to the default value in case nothing is specified
2003 * in the DT.
2004 */
2005 nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
2006 nand_set_flash_node(nand, np);
2007
2008 mtd = nand_to_mtd(nand);
2009 mtd->dev.parent = dev;
2010
2011 ret = nand_scan(nand, nsels);
2012 if (ret)
2013 return ret;
2014
2015 ret = mtd_device_register(mtd, NULL, 0);
2016 if (ret) {
2017 dev_err(dev, "failed to register mtd device: %d\n", ret);
2018 nand_cleanup(nand);
2019 return ret;
2020 }
2021
2022 list_add_tail(&sunxi_nand->node, &nfc->chips);
2023
2024 return 0;
2025 }
2026
sunxi_nand_chips_init(struct device * dev,struct sunxi_nfc * nfc)2027 static int sunxi_nand_chips_init(struct device *dev, struct sunxi_nfc *nfc)
2028 {
2029 struct device_node *np = dev->of_node;
2030 struct device_node *nand_np;
2031 int ret;
2032
2033 for_each_child_of_node(np, nand_np) {
2034 ret = sunxi_nand_chip_init(dev, nfc, nand_np);
2035 if (ret) {
2036 of_node_put(nand_np);
2037 sunxi_nand_chips_cleanup(nfc);
2038 return ret;
2039 }
2040 }
2041
2042 return 0;
2043 }
2044
sunxi_nfc_dma_init(struct sunxi_nfc * nfc,struct resource * r)2045 static int sunxi_nfc_dma_init(struct sunxi_nfc *nfc, struct resource *r)
2046 {
2047 int ret;
2048
2049 if (nfc->caps->has_mdma)
2050 return 0;
2051
2052 nfc->dmac = dma_request_chan(nfc->dev, "rxtx");
2053 if (IS_ERR(nfc->dmac)) {
2054 ret = PTR_ERR(nfc->dmac);
2055 if (ret == -EPROBE_DEFER)
2056 return ret;
2057
2058 /* Ignore errors to fall back to PIO mode */
2059 dev_warn(nfc->dev, "failed to request rxtx DMA channel: %d\n", ret);
2060 nfc->dmac = NULL;
2061 } else {
2062 struct dma_slave_config dmac_cfg = { };
2063
2064 dmac_cfg.src_addr = r->start + nfc->caps->reg_io_data;
2065 dmac_cfg.dst_addr = dmac_cfg.src_addr;
2066 dmac_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2067 dmac_cfg.dst_addr_width = dmac_cfg.src_addr_width;
2068 dmac_cfg.src_maxburst = nfc->caps->dma_maxburst;
2069 dmac_cfg.dst_maxburst = nfc->caps->dma_maxburst;
2070 dmaengine_slave_config(nfc->dmac, &dmac_cfg);
2071 }
2072 return 0;
2073 }
2074
sunxi_nfc_probe(struct platform_device * pdev)2075 static int sunxi_nfc_probe(struct platform_device *pdev)
2076 {
2077 struct device *dev = &pdev->dev;
2078 struct resource *r;
2079 struct sunxi_nfc *nfc;
2080 int irq;
2081 int ret;
2082
2083 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
2084 if (!nfc)
2085 return -ENOMEM;
2086
2087 nfc->dev = dev;
2088 nand_controller_init(&nfc->controller);
2089 INIT_LIST_HEAD(&nfc->chips);
2090
2091 nfc->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
2092 if (IS_ERR(nfc->regs))
2093 return PTR_ERR(nfc->regs);
2094
2095 irq = platform_get_irq(pdev, 0);
2096 if (irq < 0)
2097 return irq;
2098
2099 nfc->ahb_clk = devm_clk_get_enabled(dev, "ahb");
2100 if (IS_ERR(nfc->ahb_clk)) {
2101 dev_err(dev, "failed to retrieve ahb clk\n");
2102 return PTR_ERR(nfc->ahb_clk);
2103 }
2104
2105 nfc->mod_clk = devm_clk_get_enabled(dev, "mod");
2106 if (IS_ERR(nfc->mod_clk)) {
2107 dev_err(dev, "failed to retrieve mod clk\n");
2108 return PTR_ERR(nfc->mod_clk);
2109 }
2110
2111 nfc->reset = devm_reset_control_get_optional_exclusive(dev, "ahb");
2112 if (IS_ERR(nfc->reset))
2113 return PTR_ERR(nfc->reset);
2114
2115 ret = reset_control_deassert(nfc->reset);
2116 if (ret) {
2117 dev_err(dev, "reset err %d\n", ret);
2118 return ret;
2119 }
2120
2121 nfc->caps = of_device_get_match_data(&pdev->dev);
2122 if (!nfc->caps) {
2123 ret = -EINVAL;
2124 goto out_ahb_reset_reassert;
2125 }
2126
2127 ret = sunxi_nfc_rst(nfc);
2128 if (ret)
2129 goto out_ahb_reset_reassert;
2130
2131 writel(0, nfc->regs + NFC_REG_INT);
2132 ret = devm_request_irq(dev, irq, sunxi_nfc_interrupt,
2133 0, "sunxi-nand", nfc);
2134 if (ret)
2135 goto out_ahb_reset_reassert;
2136
2137 ret = sunxi_nfc_dma_init(nfc, r);
2138
2139 if (ret)
2140 goto out_ahb_reset_reassert;
2141
2142 platform_set_drvdata(pdev, nfc);
2143
2144 ret = sunxi_nand_chips_init(dev, nfc);
2145 if (ret) {
2146 dev_err(dev, "failed to init nand chips\n");
2147 goto out_release_dmac;
2148 }
2149
2150 return 0;
2151
2152 out_release_dmac:
2153 if (nfc->dmac)
2154 dma_release_channel(nfc->dmac);
2155 out_ahb_reset_reassert:
2156 reset_control_assert(nfc->reset);
2157
2158 return ret;
2159 }
2160
sunxi_nfc_remove(struct platform_device * pdev)2161 static void sunxi_nfc_remove(struct platform_device *pdev)
2162 {
2163 struct sunxi_nfc *nfc = platform_get_drvdata(pdev);
2164
2165 sunxi_nand_chips_cleanup(nfc);
2166
2167 reset_control_assert(nfc->reset);
2168
2169 if (nfc->dmac)
2170 dma_release_channel(nfc->dmac);
2171 }
2172
2173 static const struct sunxi_nfc_caps sunxi_nfc_a10_caps = {
2174 .reg_io_data = NFC_REG_A10_IO_DATA,
2175 .dma_maxburst = 4,
2176 };
2177
2178 static const struct sunxi_nfc_caps sunxi_nfc_a23_caps = {
2179 .has_mdma = true,
2180 .reg_io_data = NFC_REG_A23_IO_DATA,
2181 .dma_maxburst = 8,
2182 };
2183
2184 static const struct of_device_id sunxi_nfc_ids[] = {
2185 {
2186 .compatible = "allwinner,sun4i-a10-nand",
2187 .data = &sunxi_nfc_a10_caps,
2188 },
2189 {
2190 .compatible = "allwinner,sun8i-a23-nand-controller",
2191 .data = &sunxi_nfc_a23_caps,
2192 },
2193 { /* sentinel */ }
2194 };
2195 MODULE_DEVICE_TABLE(of, sunxi_nfc_ids);
2196
2197 static struct platform_driver sunxi_nfc_driver = {
2198 .driver = {
2199 .name = "sunxi_nand",
2200 .of_match_table = sunxi_nfc_ids,
2201 },
2202 .probe = sunxi_nfc_probe,
2203 .remove_new = sunxi_nfc_remove,
2204 };
2205 module_platform_driver(sunxi_nfc_driver);
2206
2207 MODULE_LICENSE("GPL");
2208 MODULE_AUTHOR("Boris BREZILLON");
2209 MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");
2210 MODULE_ALIAS("platform:sunxi_nand");
2211