1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for the Renesas R-Car I2C unit
4 *
5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com>
6 * Copyright (C) 2011-2019 Renesas Electronics Corporation
7 *
8 * Copyright (C) 2012-14 Renesas Solutions Corp.
9 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
10 *
11 * This file is based on the drivers/i2c/busses/i2c-sh7760.c
12 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
13 */
14 #include <linux/bitops.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/dmaengine.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/iopoll.h>
23 #include <linux/i2c.h>
24 #include <linux/i2c-smbus.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/of.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/reset.h>
31 #include <linux/slab.h>
32
33 /* register offsets */
34 #define ICSCR 0x00 /* slave ctrl */
35 #define ICMCR 0x04 /* master ctrl */
36 #define ICSSR 0x08 /* slave status */
37 #define ICMSR 0x0C /* master status */
38 #define ICSIER 0x10 /* slave irq enable */
39 #define ICMIER 0x14 /* master irq enable */
40 #define ICCCR 0x18 /* clock dividers */
41 #define ICSAR 0x1C /* slave address */
42 #define ICMAR 0x20 /* master address */
43 #define ICRXTX 0x24 /* data port */
44 #define ICFBSCR 0x38 /* first bit setup cycle (Gen3) */
45 #define ICDMAER 0x3c /* DMA enable (Gen3) */
46
47 /* ICSCR */
48 #define SDBS BIT(3) /* slave data buffer select */
49 #define SIE BIT(2) /* slave interface enable */
50 #define GCAE BIT(1) /* general call address enable */
51 #define FNA BIT(0) /* forced non acknowledgment */
52
53 /* ICMCR */
54 #define MDBS BIT(7) /* non-fifo mode switch */
55 #define FSCL BIT(6) /* override SCL pin */
56 #define FSDA BIT(5) /* override SDA pin */
57 #define OBPC BIT(4) /* override pins */
58 #define MIE BIT(3) /* master if enable */
59 #define TSBE BIT(2)
60 #define FSB BIT(1) /* force stop bit */
61 #define ESG BIT(0) /* enable start bit gen */
62
63 /* ICSSR (also for ICSIER) */
64 #define GCAR BIT(6) /* general call received */
65 #define STM BIT(5) /* slave transmit mode */
66 #define SSR BIT(4) /* stop received */
67 #define SDE BIT(3) /* slave data empty */
68 #define SDT BIT(2) /* slave data transmitted */
69 #define SDR BIT(1) /* slave data received */
70 #define SAR BIT(0) /* slave addr received */
71
72 /* ICMSR (also for ICMIE) */
73 #define MNR BIT(6) /* nack received */
74 #define MAL BIT(5) /* arbitration lost */
75 #define MST BIT(4) /* sent a stop */
76 #define MDE BIT(3)
77 #define MDT BIT(2)
78 #define MDR BIT(1)
79 #define MAT BIT(0) /* slave addr xfer done */
80
81 /* ICDMAER */
82 #define RSDMAE BIT(3) /* DMA Slave Received Enable */
83 #define TSDMAE BIT(2) /* DMA Slave Transmitted Enable */
84 #define RMDMAE BIT(1) /* DMA Master Received Enable */
85 #define TMDMAE BIT(0) /* DMA Master Transmitted Enable */
86
87 /* ICFBSCR */
88 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */
89
90 #define RCAR_MIN_DMA_LEN 8
91
92 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG)
93 #define RCAR_BUS_PHASE_DATA (MDBS | MIE)
94 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB)
95
96 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE)
97 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR)
98 #define RCAR_IRQ_STOP (MST)
99
100 #define ID_LAST_MSG BIT(0)
101 #define ID_REP_AFTER_RD BIT(1)
102 #define ID_DONE BIT(2)
103 #define ID_ARBLOST BIT(3)
104 #define ID_NACK BIT(4)
105 #define ID_EPROTO BIT(5)
106 /* persistent flags */
107 #define ID_P_NOT_ATOMIC BIT(28)
108 #define ID_P_HOST_NOTIFY BIT(29)
109 #define ID_P_NO_RXDMA BIT(30) /* HW forbids RXDMA sometimes */
110 #define ID_P_PM_BLOCKED BIT(31)
111 #define ID_P_MASK GENMASK(31, 28)
112
113 #define ID_SLAVE_NACK BIT(0)
114
115 enum rcar_i2c_type {
116 I2C_RCAR_GEN1,
117 I2C_RCAR_GEN2,
118 I2C_RCAR_GEN3,
119 I2C_RCAR_GEN4,
120 };
121
122 struct rcar_i2c_priv {
123 u32 flags;
124 void __iomem *io;
125 struct i2c_adapter adap;
126 struct i2c_msg *msg;
127 int msgs_left;
128 struct clk *clk;
129
130 wait_queue_head_t wait;
131
132 int pos;
133 u32 icccr;
134 u8 recovery_icmcr; /* protected by adapter lock */
135 enum rcar_i2c_type devtype;
136 struct i2c_client *slave;
137
138 struct resource *res;
139 struct dma_chan *dma_tx;
140 struct dma_chan *dma_rx;
141 struct scatterlist sg;
142 enum dma_data_direction dma_direction;
143
144 struct reset_control *rstc;
145 int irq;
146
147 struct i2c_client *host_notify_client;
148 u8 slave_flags;
149 };
150
151 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent)
152 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD)
153
rcar_i2c_write(struct rcar_i2c_priv * priv,int reg,u32 val)154 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
155 {
156 writel(val, priv->io + reg);
157 }
158
rcar_i2c_read(struct rcar_i2c_priv * priv,int reg)159 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
160 {
161 return readl(priv->io + reg);
162 }
163
rcar_i2c_clear_irq(struct rcar_i2c_priv * priv,u32 val)164 static void rcar_i2c_clear_irq(struct rcar_i2c_priv *priv, u32 val)
165 {
166 writel(~val & 0x7f, priv->io + ICMSR);
167 }
168
rcar_i2c_get_scl(struct i2c_adapter * adap)169 static int rcar_i2c_get_scl(struct i2c_adapter *adap)
170 {
171 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
172
173 return !!(rcar_i2c_read(priv, ICMCR) & FSCL);
174
175 };
176
rcar_i2c_set_scl(struct i2c_adapter * adap,int val)177 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val)
178 {
179 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
180
181 if (val)
182 priv->recovery_icmcr |= FSCL;
183 else
184 priv->recovery_icmcr &= ~FSCL;
185
186 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
187 };
188
rcar_i2c_set_sda(struct i2c_adapter * adap,int val)189 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val)
190 {
191 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
192
193 if (val)
194 priv->recovery_icmcr |= FSDA;
195 else
196 priv->recovery_icmcr &= ~FSDA;
197
198 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
199 };
200
rcar_i2c_get_bus_free(struct i2c_adapter * adap)201 static int rcar_i2c_get_bus_free(struct i2c_adapter *adap)
202 {
203 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
204
205 return !(rcar_i2c_read(priv, ICMCR) & FSDA);
206
207 };
208
209 static struct i2c_bus_recovery_info rcar_i2c_bri = {
210 .get_scl = rcar_i2c_get_scl,
211 .set_scl = rcar_i2c_set_scl,
212 .set_sda = rcar_i2c_set_sda,
213 .get_bus_free = rcar_i2c_get_bus_free,
214 .recover_bus = i2c_generic_scl_recovery,
215 };
rcar_i2c_init(struct rcar_i2c_priv * priv)216 static void rcar_i2c_init(struct rcar_i2c_priv *priv)
217 {
218 /* reset master mode */
219 rcar_i2c_write(priv, ICMIER, 0);
220 rcar_i2c_write(priv, ICMCR, MDBS);
221 rcar_i2c_write(priv, ICMSR, 0);
222 /* start clock */
223 rcar_i2c_write(priv, ICCCR, priv->icccr);
224
225 if (priv->devtype == I2C_RCAR_GEN3)
226 rcar_i2c_write(priv, ICFBSCR, TCYC17);
227
228 }
229
rcar_i2c_reset_slave(struct rcar_i2c_priv * priv)230 static void rcar_i2c_reset_slave(struct rcar_i2c_priv *priv)
231 {
232 rcar_i2c_write(priv, ICSIER, 0);
233 rcar_i2c_write(priv, ICSSR, 0);
234 rcar_i2c_write(priv, ICSCR, SDBS);
235 rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */
236 }
237
rcar_i2c_bus_barrier(struct rcar_i2c_priv * priv)238 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
239 {
240 int ret;
241 u32 val;
242
243 ret = readl_poll_timeout(priv->io + ICMCR, val, !(val & FSDA), 10,
244 priv->adap.timeout);
245 if (ret) {
246 /* Waiting did not help, try to recover */
247 priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL;
248 ret = i2c_recover_bus(&priv->adap);
249 }
250
251 return ret;
252 }
253
rcar_i2c_clock_calculate(struct rcar_i2c_priv * priv)254 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv)
255 {
256 u32 scgd, cdf, round, ick, sum, scl, cdf_width;
257 unsigned long rate;
258 struct device *dev = rcar_i2c_priv_to_dev(priv);
259 struct i2c_timings t = {
260 .bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ,
261 .scl_fall_ns = 35,
262 .scl_rise_ns = 200,
263 .scl_int_delay_ns = 50,
264 };
265
266 /* Fall back to previously used values if not supplied */
267 i2c_parse_fw_timings(dev, &t, false);
268
269 switch (priv->devtype) {
270 case I2C_RCAR_GEN1:
271 cdf_width = 2;
272 break;
273 case I2C_RCAR_GEN2:
274 case I2C_RCAR_GEN3:
275 cdf_width = 3;
276 break;
277 default:
278 dev_err(dev, "device type error\n");
279 return -EIO;
280 }
281
282 /*
283 * calculate SCL clock
284 * see
285 * ICCCR
286 *
287 * ick = clkp / (1 + CDF)
288 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
289 *
290 * ick : I2C internal clock < 20 MHz
291 * ticf : I2C SCL falling time
292 * tr : I2C SCL rising time
293 * intd : LSI internal delay
294 * clkp : peripheral_clk
295 * F[] : integer up-valuation
296 */
297 rate = clk_get_rate(priv->clk);
298 cdf = rate / 20000000;
299 if (cdf >= 1U << cdf_width) {
300 dev_err(dev, "Input clock %lu too high\n", rate);
301 return -EIO;
302 }
303 ick = rate / (cdf + 1);
304
305 /*
306 * it is impossible to calculate large scale
307 * number on u32. separate it
308 *
309 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
310 * = F[sum * ick / 1000000000]
311 * = F[(ick / 1000000) * sum / 1000]
312 */
313 sum = t.scl_fall_ns + t.scl_rise_ns + t.scl_int_delay_ns;
314 round = (ick + 500000) / 1000000 * sum;
315 round = (round + 500) / 1000;
316
317 /*
318 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
319 *
320 * Calculation result (= SCL) should be less than
321 * bus_speed for hardware safety
322 *
323 * We could use something along the lines of
324 * div = ick / (bus_speed + 1) + 1;
325 * scgd = (div - 20 - round + 7) / 8;
326 * scl = ick / (20 + (scgd * 8) + round);
327 * (not fully verified) but that would get pretty involved
328 */
329 for (scgd = 0; scgd < 0x40; scgd++) {
330 scl = ick / (20 + (scgd * 8) + round);
331 if (scl <= t.bus_freq_hz)
332 goto scgd_find;
333 }
334 dev_err(dev, "it is impossible to calculate best SCL\n");
335 return -EIO;
336
337 scgd_find:
338 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
339 scl, t.bus_freq_hz, rate, round, cdf, scgd);
340
341 /* keep icccr value */
342 priv->icccr = scgd << cdf_width | cdf;
343
344 return 0;
345 }
346
347 /*
348 * We don't have a test case but the HW engineers say that the write order of
349 * ICMSR and ICMCR depends on whether we issue START or REP_START. So, ICMSR
350 * handling is outside of this function. First messages clear ICMSR before this
351 * function, interrupt handlers clear the relevant bits after this function.
352 */
rcar_i2c_prepare_msg(struct rcar_i2c_priv * priv)353 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
354 {
355 int read = !!rcar_i2c_is_recv(priv);
356 bool rep_start = !(priv->flags & ID_REP_AFTER_RD);
357
358 priv->pos = 0;
359 priv->flags &= ID_P_MASK;
360
361 if (priv->msgs_left == 1)
362 priv->flags |= ID_LAST_MSG;
363
364 rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg));
365 if (priv->flags & ID_P_NOT_ATOMIC)
366 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
367
368 if (rep_start)
369 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
370 }
371
rcar_i2c_first_msg(struct rcar_i2c_priv * priv,struct i2c_msg * msgs,int num)372 static void rcar_i2c_first_msg(struct rcar_i2c_priv *priv,
373 struct i2c_msg *msgs, int num)
374 {
375 priv->msg = msgs;
376 priv->msgs_left = num;
377 rcar_i2c_write(priv, ICMSR, 0); /* must be before preparing msg */
378 rcar_i2c_prepare_msg(priv);
379 }
380
rcar_i2c_next_msg(struct rcar_i2c_priv * priv)381 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)
382 {
383 priv->msg++;
384 priv->msgs_left--;
385 rcar_i2c_prepare_msg(priv);
386 /* ICMSR handling must come afterwards in the irq handler */
387 }
388
rcar_i2c_cleanup_dma(struct rcar_i2c_priv * priv,bool terminate)389 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv, bool terminate)
390 {
391 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE
392 ? priv->dma_rx : priv->dma_tx;
393
394 /* only allowed from thread context! */
395 if (terminate)
396 dmaengine_terminate_sync(chan);
397
398 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg),
399 sg_dma_len(&priv->sg), priv->dma_direction);
400
401 /* Gen3+ can only do one RXDMA per transfer and we just completed it */
402 if (priv->devtype >= I2C_RCAR_GEN3 &&
403 priv->dma_direction == DMA_FROM_DEVICE)
404 priv->flags |= ID_P_NO_RXDMA;
405
406 priv->dma_direction = DMA_NONE;
407
408 /* Disable DMA Master Received/Transmitted, must be last! */
409 rcar_i2c_write(priv, ICDMAER, 0);
410 }
411
rcar_i2c_dma_callback(void * data)412 static void rcar_i2c_dma_callback(void *data)
413 {
414 struct rcar_i2c_priv *priv = data;
415
416 priv->pos += sg_dma_len(&priv->sg);
417
418 rcar_i2c_cleanup_dma(priv, false);
419 }
420
rcar_i2c_dma(struct rcar_i2c_priv * priv)421 static bool rcar_i2c_dma(struct rcar_i2c_priv *priv)
422 {
423 struct device *dev = rcar_i2c_priv_to_dev(priv);
424 struct i2c_msg *msg = priv->msg;
425 bool read = msg->flags & I2C_M_RD;
426 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
427 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx;
428 struct dma_async_tx_descriptor *txdesc;
429 dma_addr_t dma_addr;
430 dma_cookie_t cookie;
431 unsigned char *buf;
432 int len;
433
434 /* Do various checks to see if DMA is feasible at all */
435 if (!(priv->flags & ID_P_NOT_ATOMIC) || IS_ERR(chan) || msg->len < RCAR_MIN_DMA_LEN ||
436 !(msg->flags & I2C_M_DMA_SAFE) || (read && priv->flags & ID_P_NO_RXDMA))
437 return false;
438
439 if (read) {
440 /*
441 * The last two bytes needs to be fetched using PIO in
442 * order for the STOP phase to work.
443 */
444 buf = priv->msg->buf;
445 len = priv->msg->len - 2;
446 } else {
447 /*
448 * First byte in message was sent using PIO.
449 */
450 buf = priv->msg->buf + 1;
451 len = priv->msg->len - 1;
452 }
453
454 dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
455 if (dma_mapping_error(chan->device->dev, dma_addr)) {
456 dev_dbg(dev, "dma map failed, using PIO\n");
457 return false;
458 }
459
460 sg_dma_len(&priv->sg) = len;
461 sg_dma_address(&priv->sg) = dma_addr;
462
463 priv->dma_direction = dir;
464
465 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1,
466 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
467 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
468 if (!txdesc) {
469 dev_dbg(dev, "dma prep slave sg failed, using PIO\n");
470 rcar_i2c_cleanup_dma(priv, false);
471 return false;
472 }
473
474 txdesc->callback = rcar_i2c_dma_callback;
475 txdesc->callback_param = priv;
476
477 cookie = dmaengine_submit(txdesc);
478 if (dma_submit_error(cookie)) {
479 dev_dbg(dev, "submitting dma failed, using PIO\n");
480 rcar_i2c_cleanup_dma(priv, false);
481 return false;
482 }
483
484 /* Enable DMA Master Received/Transmitted */
485 if (read)
486 rcar_i2c_write(priv, ICDMAER, RMDMAE);
487 else
488 rcar_i2c_write(priv, ICDMAER, TMDMAE);
489
490 dma_async_issue_pending(chan);
491 return true;
492 }
493
rcar_i2c_irq_send(struct rcar_i2c_priv * priv,u32 msr)494 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
495 {
496 struct i2c_msg *msg = priv->msg;
497 u32 irqs_to_clear = MDE;
498
499 /* FIXME: sometimes, unknown interrupt happened. Do nothing */
500 if (!(msr & MDE))
501 return;
502
503 if (msr & MAT)
504 irqs_to_clear |= MAT;
505
506 /* Check if DMA can be enabled and take over */
507 if (priv->pos == 1 && rcar_i2c_dma(priv))
508 return;
509
510 if (priv->pos < msg->len) {
511 /*
512 * Prepare next data to ICRXTX register.
513 * This data will go to _SHIFT_ register.
514 *
515 * *
516 * [ICRXTX] -> [SHIFT] -> [I2C bus]
517 */
518 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
519 priv->pos++;
520 } else {
521 /*
522 * The last data was pushed to ICRXTX on _PREV_ empty irq.
523 * It is on _SHIFT_ register, and will sent to I2C bus.
524 *
525 * *
526 * [ICRXTX] -> [SHIFT] -> [I2C bus]
527 */
528
529 if (priv->flags & ID_LAST_MSG)
530 /*
531 * If current msg is the _LAST_ msg,
532 * prepare stop condition here.
533 * ID_DONE will be set on STOP irq.
534 */
535 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
536 else
537 rcar_i2c_next_msg(priv);
538 }
539
540 rcar_i2c_clear_irq(priv, irqs_to_clear);
541 }
542
rcar_i2c_irq_recv(struct rcar_i2c_priv * priv,u32 msr)543 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
544 {
545 struct i2c_msg *msg = priv->msg;
546 bool recv_len_init = priv->pos == 0 && msg->flags & I2C_M_RECV_LEN;
547 u32 irqs_to_clear = MDR;
548
549 /* FIXME: sometimes, unknown interrupt happened. Do nothing */
550 if (!(msr & MDR))
551 return;
552
553 if (msr & MAT) {
554 irqs_to_clear |= MAT;
555 /*
556 * Address transfer phase finished, but no data at this point.
557 * Try to use DMA to receive data.
558 */
559 rcar_i2c_dma(priv);
560 } else if (priv->pos < msg->len) {
561 /* get received data */
562 u8 data = rcar_i2c_read(priv, ICRXTX);
563
564 msg->buf[priv->pos] = data;
565 if (recv_len_init) {
566 if (data == 0 || data > I2C_SMBUS_BLOCK_MAX) {
567 priv->flags |= ID_DONE | ID_EPROTO;
568 return;
569 }
570 msg->len += msg->buf[0];
571 /* Enough data for DMA? */
572 if (rcar_i2c_dma(priv))
573 return;
574 /* new length after RECV_LEN now properly initialized */
575 recv_len_init = false;
576 }
577 priv->pos++;
578 }
579
580 /*
581 * If next received data is the _LAST_ and we are not waiting for a new
582 * length because of RECV_LEN, then go to a new phase.
583 */
584 if (priv->pos + 1 == msg->len && !recv_len_init) {
585 if (priv->flags & ID_LAST_MSG) {
586 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
587 } else {
588 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
589 priv->flags |= ID_REP_AFTER_RD;
590 }
591 }
592
593 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG))
594 rcar_i2c_next_msg(priv);
595
596 rcar_i2c_clear_irq(priv, irqs_to_clear);
597 }
598
rcar_i2c_slave_irq(struct rcar_i2c_priv * priv)599 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv)
600 {
601 u32 ssr_raw, ssr_filtered;
602 u8 value;
603 int ret;
604
605 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff;
606 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER);
607
608 if (!ssr_filtered)
609 return false;
610
611 /* address detected */
612 if (ssr_filtered & SAR) {
613 /* read or write request */
614 if (ssr_raw & STM) {
615 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value);
616 rcar_i2c_write(priv, ICRXTX, value);
617 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR);
618 } else {
619 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
620 if (ret)
621 priv->slave_flags |= ID_SLAVE_NACK;
622
623 rcar_i2c_read(priv, ICRXTX); /* dummy read */
624 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR);
625 }
626
627 /* Clear SSR, too, because of old STOPs to other clients than us */
628 rcar_i2c_write(priv, ICSSR, ~(SAR | SSR) & 0xff);
629 }
630
631 /* master sent stop */
632 if (ssr_filtered & SSR) {
633 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
634 rcar_i2c_write(priv, ICSCR, SIE | SDBS); /* clear our NACK */
635 priv->slave_flags &= ~ID_SLAVE_NACK;
636 rcar_i2c_write(priv, ICSIER, SAR);
637 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff);
638 }
639
640 /* master wants to write to us */
641 if (ssr_filtered & SDR) {
642 value = rcar_i2c_read(priv, ICRXTX);
643 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
644 if (ret)
645 priv->slave_flags |= ID_SLAVE_NACK;
646
647 /* Send NACK in case of error, but it will come 1 byte late :( */
648 rcar_i2c_write(priv, ICSCR, SIE | SDBS |
649 (priv->slave_flags & ID_SLAVE_NACK ? FNA : 0));
650 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff);
651 }
652
653 /* master wants to read from us */
654 if (ssr_filtered & SDE) {
655 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value);
656 rcar_i2c_write(priv, ICRXTX, value);
657 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff);
658 }
659
660 return true;
661 }
662
663 /*
664 * This driver has a lock-free design because there are IP cores (at least
665 * R-Car Gen2) which have an inherent race condition in their hardware design.
666 * There, we need to switch to RCAR_BUS_PHASE_DATA as soon as possible after
667 * the interrupt was generated, otherwise an unwanted repeated message gets
668 * generated. It turned out that taking a spinlock at the beginning of the ISR
669 * was already causing repeated messages. Thus, this driver was converted to
670 * the now lockless behaviour. Please keep this in mind when hacking the driver.
671 * R-Car Gen3 seems to have this fixed but earlier versions than R-Car Gen2 are
672 * likely affected. Therefore, we have different interrupt handler entries.
673 */
rcar_i2c_irq(int irq,struct rcar_i2c_priv * priv,u32 msr)674 static irqreturn_t rcar_i2c_irq(int irq, struct rcar_i2c_priv *priv, u32 msr)
675 {
676 if (!msr) {
677 if (rcar_i2c_slave_irq(priv))
678 return IRQ_HANDLED;
679
680 return IRQ_NONE;
681 }
682
683 /* Arbitration lost */
684 if (msr & MAL) {
685 priv->flags |= ID_DONE | ID_ARBLOST;
686 goto out;
687 }
688
689 /* Nack */
690 if (msr & MNR) {
691 /* HW automatically sends STOP after received NACK */
692 if (priv->flags & ID_P_NOT_ATOMIC)
693 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
694 priv->flags |= ID_NACK;
695 goto out;
696 }
697
698 /* Stop */
699 if (msr & MST) {
700 priv->msgs_left--; /* The last message also made it */
701 priv->flags |= ID_DONE;
702 goto out;
703 }
704
705 if (rcar_i2c_is_recv(priv))
706 rcar_i2c_irq_recv(priv, msr);
707 else
708 rcar_i2c_irq_send(priv, msr);
709
710 out:
711 if (priv->flags & ID_DONE) {
712 rcar_i2c_write(priv, ICMIER, 0);
713 rcar_i2c_write(priv, ICMSR, 0);
714 if (priv->flags & ID_P_NOT_ATOMIC)
715 wake_up(&priv->wait);
716 }
717
718 return IRQ_HANDLED;
719 }
720
rcar_i2c_gen2_irq(int irq,void * ptr)721 static irqreturn_t rcar_i2c_gen2_irq(int irq, void *ptr)
722 {
723 struct rcar_i2c_priv *priv = ptr;
724 u32 msr;
725
726 /* Clear START or STOP immediately, except for REPSTART after read */
727 if (likely(!(priv->flags & ID_REP_AFTER_RD)))
728 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
729
730 /* Only handle interrupts that are currently enabled */
731 msr = rcar_i2c_read(priv, ICMSR);
732 if (priv->flags & ID_P_NOT_ATOMIC)
733 msr &= rcar_i2c_read(priv, ICMIER);
734
735 return rcar_i2c_irq(irq, priv, msr);
736 }
737
rcar_i2c_gen3_irq(int irq,void * ptr)738 static irqreturn_t rcar_i2c_gen3_irq(int irq, void *ptr)
739 {
740 struct rcar_i2c_priv *priv = ptr;
741 u32 msr;
742
743 /* Only handle interrupts that are currently enabled */
744 msr = rcar_i2c_read(priv, ICMSR);
745 if (priv->flags & ID_P_NOT_ATOMIC)
746 msr &= rcar_i2c_read(priv, ICMIER);
747
748 /*
749 * Clear START or STOP immediately, except for REPSTART after read or
750 * if a spurious interrupt was detected.
751 */
752 if (likely(!(priv->flags & ID_REP_AFTER_RD) && msr))
753 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
754
755 return rcar_i2c_irq(irq, priv, msr);
756 }
757
rcar_i2c_request_dma_chan(struct device * dev,enum dma_transfer_direction dir,dma_addr_t port_addr)758 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev,
759 enum dma_transfer_direction dir,
760 dma_addr_t port_addr)
761 {
762 struct dma_chan *chan;
763 struct dma_slave_config cfg;
764 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
765 int ret;
766
767 chan = dma_request_chan(dev, chan_name);
768 if (IS_ERR(chan)) {
769 dev_dbg(dev, "request_channel failed for %s (%ld)\n",
770 chan_name, PTR_ERR(chan));
771 return chan;
772 }
773
774 memset(&cfg, 0, sizeof(cfg));
775 cfg.direction = dir;
776 if (dir == DMA_MEM_TO_DEV) {
777 cfg.dst_addr = port_addr;
778 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
779 } else {
780 cfg.src_addr = port_addr;
781 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
782 }
783
784 ret = dmaengine_slave_config(chan, &cfg);
785 if (ret) {
786 dev_dbg(dev, "slave_config failed for %s (%d)\n",
787 chan_name, ret);
788 dma_release_channel(chan);
789 return ERR_PTR(ret);
790 }
791
792 dev_dbg(dev, "got DMA channel for %s\n", chan_name);
793 return chan;
794 }
795
rcar_i2c_request_dma(struct rcar_i2c_priv * priv,struct i2c_msg * msg)796 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv,
797 struct i2c_msg *msg)
798 {
799 struct device *dev = rcar_i2c_priv_to_dev(priv);
800 bool read;
801 struct dma_chan *chan;
802 enum dma_transfer_direction dir;
803
804 read = msg->flags & I2C_M_RD;
805
806 chan = read ? priv->dma_rx : priv->dma_tx;
807 if (PTR_ERR(chan) != -EPROBE_DEFER)
808 return;
809
810 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
811 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX);
812
813 if (read)
814 priv->dma_rx = chan;
815 else
816 priv->dma_tx = chan;
817 }
818
rcar_i2c_release_dma(struct rcar_i2c_priv * priv)819 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv)
820 {
821 if (!IS_ERR(priv->dma_tx)) {
822 dma_release_channel(priv->dma_tx);
823 priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
824 }
825
826 if (!IS_ERR(priv->dma_rx)) {
827 dma_release_channel(priv->dma_rx);
828 priv->dma_rx = ERR_PTR(-EPROBE_DEFER);
829 }
830 }
831
832 /* I2C is a special case, we need to poll the status of a reset */
rcar_i2c_do_reset(struct rcar_i2c_priv * priv)833 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv)
834 {
835 int ret;
836
837 /* Don't reset if a slave instance is currently running */
838 if (priv->slave)
839 return -EISCONN;
840
841 ret = reset_control_reset(priv->rstc);
842 if (ret)
843 return ret;
844
845 return read_poll_timeout_atomic(reset_control_status, ret, ret == 0, 1,
846 100, false, priv->rstc);
847 }
848
rcar_i2c_master_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)849 static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
850 struct i2c_msg *msgs,
851 int num)
852 {
853 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
854 struct device *dev = rcar_i2c_priv_to_dev(priv);
855 int i, ret;
856 long time_left;
857
858 priv->flags |= ID_P_NOT_ATOMIC;
859
860 pm_runtime_get_sync(dev);
861
862 /* Check bus state before init otherwise bus busy info will be lost */
863 ret = rcar_i2c_bus_barrier(priv);
864 if (ret < 0)
865 goto out;
866
867 /* Gen3+ needs a reset. That also allows RXDMA once */
868 if (priv->devtype >= I2C_RCAR_GEN3) {
869 ret = rcar_i2c_do_reset(priv);
870 if (ret)
871 goto out;
872 priv->flags &= ~ID_P_NO_RXDMA;
873 }
874
875 rcar_i2c_init(priv);
876
877 for (i = 0; i < num; i++)
878 rcar_i2c_request_dma(priv, msgs + i);
879
880 rcar_i2c_first_msg(priv, msgs, num);
881
882 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE,
883 num * adap->timeout);
884
885 /* cleanup DMA if it couldn't complete properly due to an error */
886 if (priv->dma_direction != DMA_NONE)
887 rcar_i2c_cleanup_dma(priv, true);
888
889 if (!time_left) {
890 rcar_i2c_init(priv);
891 ret = -ETIMEDOUT;
892 } else if (priv->flags & ID_NACK) {
893 ret = -ENXIO;
894 } else if (priv->flags & ID_ARBLOST) {
895 ret = -EAGAIN;
896 } else if (priv->flags & ID_EPROTO) {
897 ret = -EPROTO;
898 } else {
899 ret = num - priv->msgs_left; /* The number of transfer */
900 }
901 out:
902 pm_runtime_put(dev);
903
904 if (ret < 0 && ret != -ENXIO)
905 dev_err(dev, "error %d : %x\n", ret, priv->flags);
906
907 return ret;
908 }
909
rcar_i2c_master_xfer_atomic(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)910 static int rcar_i2c_master_xfer_atomic(struct i2c_adapter *adap,
911 struct i2c_msg *msgs,
912 int num)
913 {
914 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
915 struct device *dev = rcar_i2c_priv_to_dev(priv);
916 unsigned long j;
917 bool time_left;
918 int ret;
919
920 priv->flags &= ~ID_P_NOT_ATOMIC;
921
922 pm_runtime_get_sync(dev);
923
924 /* Check bus state before init otherwise bus busy info will be lost */
925 ret = rcar_i2c_bus_barrier(priv);
926 if (ret < 0)
927 goto out;
928
929 rcar_i2c_init(priv);
930 rcar_i2c_first_msg(priv, msgs, num);
931
932 j = jiffies + num * adap->timeout;
933 do {
934 u32 msr = rcar_i2c_read(priv, ICMSR);
935
936 msr &= (rcar_i2c_is_recv(priv) ? RCAR_IRQ_RECV : RCAR_IRQ_SEND) | RCAR_IRQ_STOP;
937
938 if (msr) {
939 if (priv->devtype < I2C_RCAR_GEN3)
940 rcar_i2c_gen2_irq(0, priv);
941 else
942 rcar_i2c_gen3_irq(0, priv);
943 }
944
945 time_left = time_before_eq(jiffies, j);
946 } while (!(priv->flags & ID_DONE) && time_left);
947
948 if (!time_left) {
949 rcar_i2c_init(priv);
950 ret = -ETIMEDOUT;
951 } else if (priv->flags & ID_NACK) {
952 ret = -ENXIO;
953 } else if (priv->flags & ID_ARBLOST) {
954 ret = -EAGAIN;
955 } else if (priv->flags & ID_EPROTO) {
956 ret = -EPROTO;
957 } else {
958 ret = num - priv->msgs_left; /* The number of transfer */
959 }
960 out:
961 pm_runtime_put(dev);
962
963 if (ret < 0 && ret != -ENXIO)
964 dev_err(dev, "error %d : %x\n", ret, priv->flags);
965
966 return ret;
967 }
968
rcar_reg_slave(struct i2c_client * slave)969 static int rcar_reg_slave(struct i2c_client *slave)
970 {
971 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
972
973 if (priv->slave)
974 return -EBUSY;
975
976 if (slave->flags & I2C_CLIENT_TEN)
977 return -EAFNOSUPPORT;
978
979 /* Keep device active for slave address detection logic */
980 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv));
981
982 priv->slave = slave;
983 rcar_i2c_write(priv, ICSAR, slave->addr);
984 rcar_i2c_write(priv, ICSSR, 0);
985 rcar_i2c_write(priv, ICSIER, SAR);
986 rcar_i2c_write(priv, ICSCR, SIE | SDBS);
987
988 return 0;
989 }
990
rcar_unreg_slave(struct i2c_client * slave)991 static int rcar_unreg_slave(struct i2c_client *slave)
992 {
993 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
994
995 WARN_ON(!priv->slave);
996
997 /* ensure no irq is running before clearing ptr */
998 disable_irq(priv->irq);
999 rcar_i2c_reset_slave(priv);
1000 enable_irq(priv->irq);
1001
1002 priv->slave = NULL;
1003
1004 pm_runtime_put(rcar_i2c_priv_to_dev(priv));
1005
1006 return 0;
1007 }
1008
rcar_i2c_func(struct i2c_adapter * adap)1009 static u32 rcar_i2c_func(struct i2c_adapter *adap)
1010 {
1011 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
1012
1013 /*
1014 * This HW can't do:
1015 * I2C_SMBUS_QUICK (setting FSB during START didn't work)
1016 * I2C_M_NOSTART (automatically sends address after START)
1017 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK)
1018 */
1019 u32 func = I2C_FUNC_I2C | I2C_FUNC_SLAVE |
1020 (I2C_FUNC_SMBUS_EMUL_ALL & ~I2C_FUNC_SMBUS_QUICK);
1021
1022 if (priv->flags & ID_P_HOST_NOTIFY)
1023 func |= I2C_FUNC_SMBUS_HOST_NOTIFY;
1024
1025 return func;
1026 }
1027
1028 static const struct i2c_algorithm rcar_i2c_algo = {
1029 .master_xfer = rcar_i2c_master_xfer,
1030 .master_xfer_atomic = rcar_i2c_master_xfer_atomic,
1031 .functionality = rcar_i2c_func,
1032 .reg_slave = rcar_reg_slave,
1033 .unreg_slave = rcar_unreg_slave,
1034 };
1035
1036 static const struct i2c_adapter_quirks rcar_i2c_quirks = {
1037 .flags = I2C_AQ_NO_ZERO_LEN,
1038 };
1039
1040 static const struct of_device_id rcar_i2c_dt_ids[] = {
1041 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
1042 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
1043 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
1044 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
1045 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
1046 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
1047 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
1048 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 },
1049 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 },
1050 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 },
1051 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 },
1052 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 },
1053 { .compatible = "renesas,rcar-gen4-i2c", .data = (void *)I2C_RCAR_GEN4 },
1054 {},
1055 };
1056 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
1057
rcar_i2c_probe(struct platform_device * pdev)1058 static int rcar_i2c_probe(struct platform_device *pdev)
1059 {
1060 struct rcar_i2c_priv *priv;
1061 struct i2c_adapter *adap;
1062 struct device *dev = &pdev->dev;
1063 unsigned long irqflags = 0;
1064 irqreturn_t (*irqhandler)(int irq, void *ptr) = rcar_i2c_gen3_irq;
1065 int ret;
1066
1067 /* Otherwise logic will break because some bytes must always use PIO */
1068 BUILD_BUG_ON_MSG(RCAR_MIN_DMA_LEN < 3, "Invalid min DMA length");
1069
1070 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
1071 if (!priv)
1072 return -ENOMEM;
1073
1074 priv->clk = devm_clk_get(dev, NULL);
1075 if (IS_ERR(priv->clk)) {
1076 dev_err(dev, "cannot get clock\n");
1077 return PTR_ERR(priv->clk);
1078 }
1079
1080 priv->io = devm_platform_get_and_ioremap_resource(pdev, 0, &priv->res);
1081 if (IS_ERR(priv->io))
1082 return PTR_ERR(priv->io);
1083
1084 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev);
1085 init_waitqueue_head(&priv->wait);
1086
1087 adap = &priv->adap;
1088 adap->nr = pdev->id;
1089 adap->algo = &rcar_i2c_algo;
1090 adap->class = I2C_CLASS_DEPRECATED;
1091 adap->retries = 3;
1092 adap->dev.parent = dev;
1093 adap->dev.of_node = dev->of_node;
1094 adap->bus_recovery_info = &rcar_i2c_bri;
1095 adap->quirks = &rcar_i2c_quirks;
1096 i2c_set_adapdata(adap, priv);
1097 strscpy(adap->name, pdev->name, sizeof(adap->name));
1098
1099 /* Init DMA */
1100 sg_init_table(&priv->sg, 1);
1101 priv->dma_direction = DMA_NONE;
1102 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
1103
1104 /* Activate device for clock calculation */
1105 pm_runtime_enable(dev);
1106 pm_runtime_get_sync(dev);
1107 ret = rcar_i2c_clock_calculate(priv);
1108 if (ret < 0) {
1109 pm_runtime_put(dev);
1110 goto out_pm_disable;
1111 }
1112
1113 /* Bring hardware to known state */
1114 rcar_i2c_init(priv);
1115 rcar_i2c_reset_slave(priv);
1116
1117 if (priv->devtype < I2C_RCAR_GEN3) {
1118 irqflags |= IRQF_NO_THREAD;
1119 irqhandler = rcar_i2c_gen2_irq;
1120 }
1121
1122 /* Stay always active when multi-master to keep arbitration working */
1123 if (of_property_read_bool(dev->of_node, "multi-master"))
1124 priv->flags |= ID_P_PM_BLOCKED;
1125 else
1126 pm_runtime_put(dev);
1127
1128 if (of_property_read_bool(dev->of_node, "smbus"))
1129 priv->flags |= ID_P_HOST_NOTIFY;
1130
1131 /* R-Car Gen3+ needs a reset before every transfer */
1132 if (priv->devtype >= I2C_RCAR_GEN3) {
1133 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1134 if (IS_ERR(priv->rstc)) {
1135 ret = PTR_ERR(priv->rstc);
1136 goto out_pm_put;
1137 }
1138
1139 ret = reset_control_status(priv->rstc);
1140 if (ret < 0)
1141 goto out_pm_put;
1142
1143 /* hard reset disturbs HostNotify local target, so disable it */
1144 priv->flags &= ~ID_P_HOST_NOTIFY;
1145 }
1146
1147 ret = platform_get_irq(pdev, 0);
1148 if (ret < 0)
1149 goto out_pm_put;
1150 priv->irq = ret;
1151 ret = devm_request_irq(dev, priv->irq, irqhandler, irqflags, dev_name(dev), priv);
1152 if (ret < 0) {
1153 dev_err(dev, "cannot get irq %d\n", priv->irq);
1154 goto out_pm_put;
1155 }
1156
1157 platform_set_drvdata(pdev, priv);
1158
1159 ret = i2c_add_numbered_adapter(adap);
1160 if (ret < 0)
1161 goto out_pm_put;
1162
1163 if (priv->flags & ID_P_HOST_NOTIFY) {
1164 priv->host_notify_client = i2c_new_slave_host_notify_device(adap);
1165 if (IS_ERR(priv->host_notify_client)) {
1166 ret = PTR_ERR(priv->host_notify_client);
1167 goto out_del_device;
1168 }
1169 }
1170
1171 dev_info(dev, "probed\n");
1172
1173 return 0;
1174
1175 out_del_device:
1176 i2c_del_adapter(&priv->adap);
1177 out_pm_put:
1178 if (priv->flags & ID_P_PM_BLOCKED)
1179 pm_runtime_put(dev);
1180 out_pm_disable:
1181 pm_runtime_disable(dev);
1182 return ret;
1183 }
1184
rcar_i2c_remove(struct platform_device * pdev)1185 static void rcar_i2c_remove(struct platform_device *pdev)
1186 {
1187 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
1188 struct device *dev = &pdev->dev;
1189
1190 if (priv->host_notify_client)
1191 i2c_free_slave_host_notify_device(priv->host_notify_client);
1192 i2c_del_adapter(&priv->adap);
1193 rcar_i2c_release_dma(priv);
1194 if (priv->flags & ID_P_PM_BLOCKED)
1195 pm_runtime_put(dev);
1196 pm_runtime_disable(dev);
1197 }
1198
rcar_i2c_suspend(struct device * dev)1199 static int rcar_i2c_suspend(struct device *dev)
1200 {
1201 struct rcar_i2c_priv *priv = dev_get_drvdata(dev);
1202
1203 i2c_mark_adapter_suspended(&priv->adap);
1204 return 0;
1205 }
1206
rcar_i2c_resume(struct device * dev)1207 static int rcar_i2c_resume(struct device *dev)
1208 {
1209 struct rcar_i2c_priv *priv = dev_get_drvdata(dev);
1210
1211 i2c_mark_adapter_resumed(&priv->adap);
1212 return 0;
1213 }
1214
1215 static const struct dev_pm_ops rcar_i2c_pm_ops = {
1216 NOIRQ_SYSTEM_SLEEP_PM_OPS(rcar_i2c_suspend, rcar_i2c_resume)
1217 };
1218
1219 static struct platform_driver rcar_i2c_driver = {
1220 .driver = {
1221 .name = "i2c-rcar",
1222 .of_match_table = rcar_i2c_dt_ids,
1223 .pm = pm_sleep_ptr(&rcar_i2c_pm_ops),
1224 },
1225 .probe = rcar_i2c_probe,
1226 .remove_new = rcar_i2c_remove,
1227 };
1228
1229 module_platform_driver(rcar_i2c_driver);
1230
1231 MODULE_LICENSE("GPL v2");
1232 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
1233 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
1234