1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/module.h>
7 #include <linux/of.h>
8 #include <linux/platform_device.h>
9
10 #include "pinctrl-msm.h"
11
12 #define REG_SIZE 0x1000
13
14 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
15 { \
16 .grp = PINCTRL_PINGROUP("gpio" #id, \
17 gpio##id##_pins, \
18 ARRAY_SIZE(gpio##id##_pins)), \
19 .funcs = (int[]){ \
20 msm_mux_gpio, /* gpio mode */ \
21 msm_mux_##f1, \
22 msm_mux_##f2, \
23 msm_mux_##f3, \
24 msm_mux_##f4, \
25 msm_mux_##f5, \
26 msm_mux_##f6, \
27 msm_mux_##f7, \
28 msm_mux_##f8, \
29 msm_mux_##f9 \
30 }, \
31 .nfuncs = 10, \
32 .ctl_reg = REG_SIZE * id, \
33 .io_reg = 0x4 + REG_SIZE * id, \
34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
35 .intr_status_reg = 0xc + REG_SIZE * id, \
36 .intr_target_reg = 0x8 + REG_SIZE * id, \
37 .mux_bit = 2, \
38 .pull_bit = 0, \
39 .drv_bit = 6, \
40 .oe_bit = 9, \
41 .in_bit = 0, \
42 .out_bit = 1, \
43 .intr_enable_bit = 0, \
44 .intr_status_bit = 0, \
45 .intr_target_bit = 5, \
46 .intr_target_kpss_val = 3, \
47 .intr_raw_status_bit = 4, \
48 .intr_polarity_bit = 1, \
49 .intr_detection_bit = 2, \
50 .intr_detection_width = 2, \
51 }
52
53 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
54 { \
55 .grp = PINCTRL_PINGROUP(#pg_name, \
56 pg_name##_pins, \
57 ARRAY_SIZE(pg_name##_pins)), \
58 .ctl_reg = ctl, \
59 .io_reg = 0, \
60 .intr_cfg_reg = 0, \
61 .intr_status_reg = 0, \
62 .intr_target_reg = 0, \
63 .mux_bit = -1, \
64 .pull_bit = pull, \
65 .drv_bit = drv, \
66 .oe_bit = -1, \
67 .in_bit = -1, \
68 .out_bit = -1, \
69 .intr_enable_bit = -1, \
70 .intr_status_bit = -1, \
71 .intr_target_bit = -1, \
72 .intr_raw_status_bit = -1, \
73 .intr_polarity_bit = -1, \
74 .intr_detection_bit = -1, \
75 .intr_detection_width = -1, \
76 }
77
78 #define UFS_RESET(pg_name, offset) \
79 { \
80 .grp = PINCTRL_PINGROUP(#pg_name, \
81 pg_name##_pins, \
82 ARRAY_SIZE(pg_name##_pins)), \
83 .ctl_reg = offset, \
84 .io_reg = offset + 0x4, \
85 .intr_cfg_reg = 0, \
86 .intr_status_reg = 0, \
87 .intr_target_reg = 0, \
88 .mux_bit = -1, \
89 .pull_bit = 3, \
90 .drv_bit = 0, \
91 .oe_bit = -1, \
92 .in_bit = -1, \
93 .out_bit = 0, \
94 .intr_enable_bit = -1, \
95 .intr_status_bit = -1, \
96 .intr_target_bit = -1, \
97 .intr_raw_status_bit = -1, \
98 .intr_polarity_bit = -1, \
99 .intr_detection_bit = -1, \
100 .intr_detection_width = -1, \
101 }
102 static const struct pinctrl_pin_desc qcm2290_pins[] = {
103 PINCTRL_PIN(0, "GPIO_0"),
104 PINCTRL_PIN(1, "GPIO_1"),
105 PINCTRL_PIN(2, "GPIO_2"),
106 PINCTRL_PIN(3, "GPIO_3"),
107 PINCTRL_PIN(4, "GPIO_4"),
108 PINCTRL_PIN(5, "GPIO_5"),
109 PINCTRL_PIN(6, "GPIO_6"),
110 PINCTRL_PIN(7, "GPIO_7"),
111 PINCTRL_PIN(8, "GPIO_8"),
112 PINCTRL_PIN(9, "GPIO_9"),
113 PINCTRL_PIN(10, "GPIO_10"),
114 PINCTRL_PIN(11, "GPIO_11"),
115 PINCTRL_PIN(12, "GPIO_12"),
116 PINCTRL_PIN(13, "GPIO_13"),
117 PINCTRL_PIN(14, "GPIO_14"),
118 PINCTRL_PIN(15, "GPIO_15"),
119 PINCTRL_PIN(16, "GPIO_16"),
120 PINCTRL_PIN(17, "GPIO_17"),
121 PINCTRL_PIN(18, "GPIO_18"),
122 PINCTRL_PIN(19, "GPIO_19"),
123 PINCTRL_PIN(20, "GPIO_20"),
124 PINCTRL_PIN(21, "GPIO_21"),
125 PINCTRL_PIN(22, "GPIO_22"),
126 PINCTRL_PIN(23, "GPIO_23"),
127 PINCTRL_PIN(24, "GPIO_24"),
128 PINCTRL_PIN(25, "GPIO_25"),
129 PINCTRL_PIN(26, "GPIO_26"),
130 PINCTRL_PIN(27, "GPIO_27"),
131 PINCTRL_PIN(28, "GPIO_28"),
132 PINCTRL_PIN(29, "GPIO_29"),
133 PINCTRL_PIN(30, "GPIO_30"),
134 PINCTRL_PIN(31, "GPIO_31"),
135 PINCTRL_PIN(32, "GPIO_32"),
136 PINCTRL_PIN(33, "GPIO_33"),
137 PINCTRL_PIN(34, "GPIO_34"),
138 PINCTRL_PIN(35, "GPIO_35"),
139 PINCTRL_PIN(36, "GPIO_36"),
140 PINCTRL_PIN(37, "GPIO_37"),
141 PINCTRL_PIN(38, "GPIO_38"),
142 PINCTRL_PIN(39, "GPIO_39"),
143 PINCTRL_PIN(40, "GPIO_40"),
144 PINCTRL_PIN(41, "GPIO_41"),
145 PINCTRL_PIN(42, "GPIO_42"),
146 PINCTRL_PIN(43, "GPIO_43"),
147 PINCTRL_PIN(44, "GPIO_44"),
148 PINCTRL_PIN(45, "GPIO_45"),
149 PINCTRL_PIN(46, "GPIO_46"),
150 PINCTRL_PIN(47, "GPIO_47"),
151 PINCTRL_PIN(48, "GPIO_48"),
152 PINCTRL_PIN(49, "GPIO_49"),
153 PINCTRL_PIN(50, "GPIO_50"),
154 PINCTRL_PIN(51, "GPIO_51"),
155 PINCTRL_PIN(52, "GPIO_52"),
156 PINCTRL_PIN(53, "GPIO_53"),
157 PINCTRL_PIN(54, "GPIO_54"),
158 PINCTRL_PIN(55, "GPIO_55"),
159 PINCTRL_PIN(56, "GPIO_56"),
160 PINCTRL_PIN(57, "GPIO_57"),
161 PINCTRL_PIN(58, "GPIO_58"),
162 PINCTRL_PIN(59, "GPIO_59"),
163 PINCTRL_PIN(60, "GPIO_60"),
164 PINCTRL_PIN(61, "GPIO_61"),
165 PINCTRL_PIN(62, "GPIO_62"),
166 PINCTRL_PIN(63, "GPIO_63"),
167 PINCTRL_PIN(64, "GPIO_64"),
168 PINCTRL_PIN(65, "GPIO_65"),
169 PINCTRL_PIN(66, "GPIO_66"),
170 PINCTRL_PIN(67, "GPIO_67"),
171 PINCTRL_PIN(68, "GPIO_68"),
172 PINCTRL_PIN(69, "GPIO_69"),
173 PINCTRL_PIN(70, "GPIO_70"),
174 PINCTRL_PIN(71, "GPIO_71"),
175 PINCTRL_PIN(72, "GPIO_72"),
176 PINCTRL_PIN(73, "GPIO_73"),
177 PINCTRL_PIN(74, "GPIO_74"),
178 PINCTRL_PIN(75, "GPIO_75"),
179 PINCTRL_PIN(76, "GPIO_76"),
180 PINCTRL_PIN(77, "GPIO_77"),
181 PINCTRL_PIN(78, "GPIO_78"),
182 PINCTRL_PIN(79, "GPIO_79"),
183 PINCTRL_PIN(80, "GPIO_80"),
184 PINCTRL_PIN(81, "GPIO_81"),
185 PINCTRL_PIN(82, "GPIO_82"),
186 PINCTRL_PIN(83, "GPIO_83"),
187 PINCTRL_PIN(84, "GPIO_84"),
188 PINCTRL_PIN(85, "GPIO_85"),
189 PINCTRL_PIN(86, "GPIO_86"),
190 PINCTRL_PIN(87, "GPIO_87"),
191 PINCTRL_PIN(88, "GPIO_88"),
192 PINCTRL_PIN(89, "GPIO_89"),
193 PINCTRL_PIN(90, "GPIO_90"),
194 PINCTRL_PIN(91, "GPIO_91"),
195 PINCTRL_PIN(92, "GPIO_92"),
196 PINCTRL_PIN(93, "GPIO_93"),
197 PINCTRL_PIN(94, "GPIO_94"),
198 PINCTRL_PIN(95, "GPIO_95"),
199 PINCTRL_PIN(96, "GPIO_96"),
200 PINCTRL_PIN(97, "GPIO_97"),
201 PINCTRL_PIN(98, "GPIO_98"),
202 PINCTRL_PIN(99, "GPIO_99"),
203 PINCTRL_PIN(100, "GPIO_100"),
204 PINCTRL_PIN(101, "GPIO_101"),
205 PINCTRL_PIN(102, "GPIO_102"),
206 PINCTRL_PIN(103, "GPIO_103"),
207 PINCTRL_PIN(104, "GPIO_104"),
208 PINCTRL_PIN(105, "GPIO_105"),
209 PINCTRL_PIN(106, "GPIO_106"),
210 PINCTRL_PIN(107, "GPIO_107"),
211 PINCTRL_PIN(108, "GPIO_108"),
212 PINCTRL_PIN(109, "GPIO_109"),
213 PINCTRL_PIN(110, "GPIO_110"),
214 PINCTRL_PIN(111, "GPIO_111"),
215 PINCTRL_PIN(112, "GPIO_112"),
216 PINCTRL_PIN(113, "GPIO_113"),
217 PINCTRL_PIN(114, "GPIO_114"),
218 PINCTRL_PIN(115, "GPIO_115"),
219 PINCTRL_PIN(116, "GPIO_116"),
220 PINCTRL_PIN(117, "GPIO_117"),
221 PINCTRL_PIN(118, "GPIO_118"),
222 PINCTRL_PIN(119, "GPIO_119"),
223 PINCTRL_PIN(120, "GPIO_120"),
224 PINCTRL_PIN(121, "GPIO_121"),
225 PINCTRL_PIN(122, "GPIO_122"),
226 PINCTRL_PIN(123, "GPIO_123"),
227 PINCTRL_PIN(124, "GPIO_124"),
228 PINCTRL_PIN(125, "GPIO_125"),
229 PINCTRL_PIN(126, "GPIO_126"),
230 PINCTRL_PIN(127, "SDC1_RCLK"),
231 PINCTRL_PIN(128, "SDC1_CLK"),
232 PINCTRL_PIN(129, "SDC1_CMD"),
233 PINCTRL_PIN(130, "SDC1_DATA"),
234 PINCTRL_PIN(131, "SDC2_CLK"),
235 PINCTRL_PIN(132, "SDC2_CMD"),
236 PINCTRL_PIN(133, "SDC2_DATA"),
237 };
238
239 #define DECLARE_MSM_GPIO_PINS(pin) \
240 static const unsigned int gpio##pin##_pins[] = { pin }
241 DECLARE_MSM_GPIO_PINS(0);
242 DECLARE_MSM_GPIO_PINS(1);
243 DECLARE_MSM_GPIO_PINS(2);
244 DECLARE_MSM_GPIO_PINS(3);
245 DECLARE_MSM_GPIO_PINS(4);
246 DECLARE_MSM_GPIO_PINS(5);
247 DECLARE_MSM_GPIO_PINS(6);
248 DECLARE_MSM_GPIO_PINS(7);
249 DECLARE_MSM_GPIO_PINS(8);
250 DECLARE_MSM_GPIO_PINS(9);
251 DECLARE_MSM_GPIO_PINS(10);
252 DECLARE_MSM_GPIO_PINS(11);
253 DECLARE_MSM_GPIO_PINS(12);
254 DECLARE_MSM_GPIO_PINS(13);
255 DECLARE_MSM_GPIO_PINS(14);
256 DECLARE_MSM_GPIO_PINS(15);
257 DECLARE_MSM_GPIO_PINS(16);
258 DECLARE_MSM_GPIO_PINS(17);
259 DECLARE_MSM_GPIO_PINS(18);
260 DECLARE_MSM_GPIO_PINS(19);
261 DECLARE_MSM_GPIO_PINS(20);
262 DECLARE_MSM_GPIO_PINS(21);
263 DECLARE_MSM_GPIO_PINS(22);
264 DECLARE_MSM_GPIO_PINS(23);
265 DECLARE_MSM_GPIO_PINS(24);
266 DECLARE_MSM_GPIO_PINS(25);
267 DECLARE_MSM_GPIO_PINS(26);
268 DECLARE_MSM_GPIO_PINS(27);
269 DECLARE_MSM_GPIO_PINS(28);
270 DECLARE_MSM_GPIO_PINS(29);
271 DECLARE_MSM_GPIO_PINS(30);
272 DECLARE_MSM_GPIO_PINS(31);
273 DECLARE_MSM_GPIO_PINS(32);
274 DECLARE_MSM_GPIO_PINS(33);
275 DECLARE_MSM_GPIO_PINS(34);
276 DECLARE_MSM_GPIO_PINS(35);
277 DECLARE_MSM_GPIO_PINS(36);
278 DECLARE_MSM_GPIO_PINS(37);
279 DECLARE_MSM_GPIO_PINS(38);
280 DECLARE_MSM_GPIO_PINS(39);
281 DECLARE_MSM_GPIO_PINS(40);
282 DECLARE_MSM_GPIO_PINS(41);
283 DECLARE_MSM_GPIO_PINS(42);
284 DECLARE_MSM_GPIO_PINS(43);
285 DECLARE_MSM_GPIO_PINS(44);
286 DECLARE_MSM_GPIO_PINS(45);
287 DECLARE_MSM_GPIO_PINS(46);
288 DECLARE_MSM_GPIO_PINS(47);
289 DECLARE_MSM_GPIO_PINS(48);
290 DECLARE_MSM_GPIO_PINS(49);
291 DECLARE_MSM_GPIO_PINS(50);
292 DECLARE_MSM_GPIO_PINS(51);
293 DECLARE_MSM_GPIO_PINS(52);
294 DECLARE_MSM_GPIO_PINS(53);
295 DECLARE_MSM_GPIO_PINS(54);
296 DECLARE_MSM_GPIO_PINS(55);
297 DECLARE_MSM_GPIO_PINS(56);
298 DECLARE_MSM_GPIO_PINS(57);
299 DECLARE_MSM_GPIO_PINS(58);
300 DECLARE_MSM_GPIO_PINS(59);
301 DECLARE_MSM_GPIO_PINS(60);
302 DECLARE_MSM_GPIO_PINS(61);
303 DECLARE_MSM_GPIO_PINS(62);
304 DECLARE_MSM_GPIO_PINS(63);
305 DECLARE_MSM_GPIO_PINS(64);
306 DECLARE_MSM_GPIO_PINS(65);
307 DECLARE_MSM_GPIO_PINS(66);
308 DECLARE_MSM_GPIO_PINS(67);
309 DECLARE_MSM_GPIO_PINS(68);
310 DECLARE_MSM_GPIO_PINS(69);
311 DECLARE_MSM_GPIO_PINS(70);
312 DECLARE_MSM_GPIO_PINS(71);
313 DECLARE_MSM_GPIO_PINS(72);
314 DECLARE_MSM_GPIO_PINS(73);
315 DECLARE_MSM_GPIO_PINS(74);
316 DECLARE_MSM_GPIO_PINS(75);
317 DECLARE_MSM_GPIO_PINS(76);
318 DECLARE_MSM_GPIO_PINS(77);
319 DECLARE_MSM_GPIO_PINS(78);
320 DECLARE_MSM_GPIO_PINS(79);
321 DECLARE_MSM_GPIO_PINS(80);
322 DECLARE_MSM_GPIO_PINS(81);
323 DECLARE_MSM_GPIO_PINS(82);
324 DECLARE_MSM_GPIO_PINS(83);
325 DECLARE_MSM_GPIO_PINS(84);
326 DECLARE_MSM_GPIO_PINS(85);
327 DECLARE_MSM_GPIO_PINS(86);
328 DECLARE_MSM_GPIO_PINS(87);
329 DECLARE_MSM_GPIO_PINS(88);
330 DECLARE_MSM_GPIO_PINS(89);
331 DECLARE_MSM_GPIO_PINS(90);
332 DECLARE_MSM_GPIO_PINS(91);
333 DECLARE_MSM_GPIO_PINS(92);
334 DECLARE_MSM_GPIO_PINS(93);
335 DECLARE_MSM_GPIO_PINS(94);
336 DECLARE_MSM_GPIO_PINS(95);
337 DECLARE_MSM_GPIO_PINS(96);
338 DECLARE_MSM_GPIO_PINS(97);
339 DECLARE_MSM_GPIO_PINS(98);
340 DECLARE_MSM_GPIO_PINS(99);
341 DECLARE_MSM_GPIO_PINS(100);
342 DECLARE_MSM_GPIO_PINS(101);
343 DECLARE_MSM_GPIO_PINS(102);
344 DECLARE_MSM_GPIO_PINS(103);
345 DECLARE_MSM_GPIO_PINS(104);
346 DECLARE_MSM_GPIO_PINS(105);
347 DECLARE_MSM_GPIO_PINS(106);
348 DECLARE_MSM_GPIO_PINS(107);
349 DECLARE_MSM_GPIO_PINS(108);
350 DECLARE_MSM_GPIO_PINS(109);
351 DECLARE_MSM_GPIO_PINS(110);
352 DECLARE_MSM_GPIO_PINS(111);
353 DECLARE_MSM_GPIO_PINS(112);
354 DECLARE_MSM_GPIO_PINS(113);
355 DECLARE_MSM_GPIO_PINS(114);
356 DECLARE_MSM_GPIO_PINS(115);
357 DECLARE_MSM_GPIO_PINS(116);
358 DECLARE_MSM_GPIO_PINS(117);
359 DECLARE_MSM_GPIO_PINS(118);
360 DECLARE_MSM_GPIO_PINS(119);
361 DECLARE_MSM_GPIO_PINS(120);
362 DECLARE_MSM_GPIO_PINS(121);
363 DECLARE_MSM_GPIO_PINS(122);
364 DECLARE_MSM_GPIO_PINS(123);
365 DECLARE_MSM_GPIO_PINS(124);
366 DECLARE_MSM_GPIO_PINS(125);
367 DECLARE_MSM_GPIO_PINS(126);
368
369 static const unsigned int sdc1_rclk_pins[] = { 127 };
370 static const unsigned int sdc1_clk_pins[] = { 128 };
371 static const unsigned int sdc1_cmd_pins[] = { 129 };
372 static const unsigned int sdc1_data_pins[] = { 130 };
373 static const unsigned int sdc2_clk_pins[] = { 131 };
374 static const unsigned int sdc2_cmd_pins[] = { 132 };
375 static const unsigned int sdc2_data_pins[] = { 133 };
376
377 enum qcm2290_functions {
378 msm_mux_adsp_ext,
379 msm_mux_agera_pll,
380 msm_mux_atest,
381 msm_mux_cam_mclk,
382 msm_mux_cci_async,
383 msm_mux_cci_i2c,
384 msm_mux_cci_timer0,
385 msm_mux_cci_timer1,
386 msm_mux_cci_timer2,
387 msm_mux_cci_timer3,
388 msm_mux_char_exec,
389 msm_mux_cri_trng,
390 msm_mux_cri_trng0,
391 msm_mux_cri_trng1,
392 msm_mux_dac_calib,
393 msm_mux_dbg_out,
394 msm_mux_ddr_bist,
395 msm_mux_ddr_pxi0,
396 msm_mux_ddr_pxi1,
397 msm_mux_ddr_pxi2,
398 msm_mux_ddr_pxi3,
399 msm_mux_gcc_gp1,
400 msm_mux_gcc_gp2,
401 msm_mux_gcc_gp3,
402 msm_mux_gpio,
403 msm_mux_gp_pdm0,
404 msm_mux_gp_pdm1,
405 msm_mux_gp_pdm2,
406 msm_mux_gsm0_tx,
407 msm_mux_gsm1_tx,
408 msm_mux_jitter_bist,
409 msm_mux_mdp_vsync,
410 msm_mux_mdp_vsync_out_0,
411 msm_mux_mdp_vsync_out_1,
412 msm_mux_mpm_pwr,
413 msm_mux_mss_lte,
414 msm_mux_m_voc,
415 msm_mux_nav_gpio,
416 msm_mux_pa_indicator,
417 msm_mux_pbs0,
418 msm_mux_pbs1,
419 msm_mux_pbs2,
420 msm_mux_pbs3,
421 msm_mux_pbs4,
422 msm_mux_pbs5,
423 msm_mux_pbs6,
424 msm_mux_pbs7,
425 msm_mux_pbs8,
426 msm_mux_pbs9,
427 msm_mux_pbs10,
428 msm_mux_pbs11,
429 msm_mux_pbs12,
430 msm_mux_pbs13,
431 msm_mux_pbs14,
432 msm_mux_pbs15,
433 msm_mux_pbs_out,
434 msm_mux_phase_flag,
435 msm_mux_pll_bist,
436 msm_mux_pll_bypassnl,
437 msm_mux_pll_reset,
438 msm_mux_prng_rosc,
439 msm_mux_pwm_0,
440 msm_mux_pwm_1,
441 msm_mux_pwm_2,
442 msm_mux_pwm_3,
443 msm_mux_pwm_4,
444 msm_mux_pwm_5,
445 msm_mux_pwm_6,
446 msm_mux_pwm_7,
447 msm_mux_pwm_8,
448 msm_mux_pwm_9,
449 msm_mux_qdss_cti,
450 msm_mux_qdss_gpio,
451 msm_mux_qup0,
452 msm_mux_qup1,
453 msm_mux_qup2,
454 msm_mux_qup3,
455 msm_mux_qup4,
456 msm_mux_qup5,
457 msm_mux_sdc1_tb,
458 msm_mux_sdc2_tb,
459 msm_mux_sd_write,
460 msm_mux_ssbi_wtr1,
461 msm_mux_tgu_ch0,
462 msm_mux_tgu_ch1,
463 msm_mux_tgu_ch2,
464 msm_mux_tgu_ch3,
465 msm_mux_tsense_pwm,
466 msm_mux_uim1_clk,
467 msm_mux_uim1_data,
468 msm_mux_uim1_present,
469 msm_mux_uim1_reset,
470 msm_mux_uim2_clk,
471 msm_mux_uim2_data,
472 msm_mux_uim2_present,
473 msm_mux_uim2_reset,
474 msm_mux_usb_phy,
475 msm_mux_vfr_1,
476 msm_mux_vsense_trigger,
477 msm_mux_wlan1_adc0,
478 msm_mux_wlan1_adc1,
479 msm_mux__,
480 };
481
482 static const char * const qup0_groups[] = {
483 "gpio0", "gpio1", "gpio2", "gpio3", "gpio82", "gpio86",
484 };
485 static const char * const gpio_groups[] = {
486 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
487 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
488 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
489 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
490 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
491 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
492 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
493 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
494 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
495 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
496 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
497 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
498 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
499 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
500 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
501 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
502 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
503 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
504 "gpio123", "gpio124", "gpio125", "gpio126",
505 };
506 static const char * const ddr_bist_groups[] = {
507 "gpio0", "gpio1", "gpio2", "gpio3",
508 };
509 static const char * const phase_flag_groups[] = {
510 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6",
511 "gpio14", "gpio15", "gpio16", "gpio17", "gpio22", "gpio23", "gpio24",
512 "gpio25", "gpio26", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33",
513 "gpio35", "gpio36", "gpio43", "gpio44", "gpio45", "gpio63", "gpio64",
514 "gpio102", "gpio103", "gpio104", "gpio105",
515 };
516 static const char * const qdss_gpio_groups[] = {
517 "gpio0", "gpio1", "gpio2", "gpio3", "gpio8", "gpio9", "gpio10",
518 "gpio11", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
519 "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
520 "gpio47", "gpio48", "gpio69", "gpio70", "gpio87", "gpio90", "gpio91",
521 "gpio94", "gpio95", "gpio104", "gpio105", "gpio106", "gpio107",
522 "gpio109", "gpio110",
523 };
524 static const char * const atest_groups[] = {
525 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6",
526 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio29", "gpio30",
527 "gpio31", "gpio32", "gpio33", "gpio86", "gpio89", "gpio100", "gpio101",
528 };
529 static const char * const mpm_pwr_groups[] = {
530 "gpio1",
531 };
532 static const char * const m_voc_groups[] = {
533 "gpio0",
534 };
535 static const char * const dac_calib_groups[] = {
536 "gpio2",
537 "gpio3",
538 "gpio4",
539 "gpio5",
540 "gpio6",
541 "gpio14",
542 "gpio15",
543 "gpio16",
544 "gpio17",
545 "gpio22",
546 "gpio23",
547 "gpio24",
548 "gpio25",
549 "gpio26",
550 "gpio29",
551 "gpio30",
552 "gpio31",
553 "gpio32",
554 "gpio33",
555 "gpio80",
556 "gpio81",
557 "gpio82",
558 "gpio102",
559 "gpio103",
560 "gpio104",
561 "gpio105",
562 };
563 static const char * const qup1_groups[] = {
564 "gpio4", "gpio5", "gpio69", "gpio70",
565 };
566 static const char * const cri_trng0_groups[] = {
567 "gpio4",
568 };
569 static const char * const cri_trng1_groups[] = {
570 "gpio5",
571 };
572 static const char * const qup2_groups[] = {
573 "gpio6", "gpio7", "gpio71", "gpio80",
574 };
575 static const char * const qup3_groups[] = {
576 "gpio8", "gpio9", "gpio10", "gpio11",
577 };
578 static const char * const pbs_out_groups[] = {
579 "gpio8", "gpio9", "gpio52",
580 };
581 static const char * const pll_bist_groups[] = {
582 "gpio8", "gpio9",
583 };
584 static const char * const tsense_pwm_groups[] = {
585 "gpio8",
586 };
587 static const char * const agera_pll_groups[] = {
588 "gpio10", "gpio11",
589 };
590 static const char * const pbs0_groups[] = {
591 "gpio10",
592 };
593 static const char * const pbs1_groups[] = {
594 "gpio11",
595 };
596 static const char * const qup4_groups[] = {
597 "gpio12", "gpio13", "gpio96", "gpio97",
598 };
599 static const char * const tgu_ch0_groups[] = {
600 "gpio12",
601 };
602 static const char * const tgu_ch1_groups[] = {
603 "gpio13",
604 };
605 static const char * const qup5_groups[] = {
606 "gpio14", "gpio15", "gpio16", "gpio17",
607 };
608 static const char * const tgu_ch2_groups[] = {
609 "gpio14",
610 };
611 static const char * const tgu_ch3_groups[] = {
612 "gpio15",
613 };
614 static const char * const sdc2_tb_groups[] = {
615 "gpio18",
616 };
617 static const char * const cri_trng_groups[] = {
618 "gpio18",
619 };
620 static const char * const pbs2_groups[] = {
621 "gpio18",
622 };
623 static const char * const pwm_0_groups[] = {
624 "gpio18",
625 };
626 static const char * const sdc1_tb_groups[] = {
627 "gpio19",
628 };
629 static const char * const pbs3_groups[] = {
630 "gpio19",
631 };
632 static const char * const cam_mclk_groups[] = {
633 "gpio20", "gpio21", "gpio27", "gpio28",
634 };
635 static const char * const pbs4_groups[] = {
636 "gpio20",
637 };
638 static const char * const adsp_ext_groups[] = {
639 "gpio21",
640 };
641 static const char * const pbs5_groups[] = {
642 "gpio21",
643 };
644 static const char * const cci_i2c_groups[] = {
645 "gpio22", "gpio23", "gpio29", "gpio30",
646 };
647 static const char * const prng_rosc_groups[] = {
648 "gpio22", "gpio23",
649 };
650 static const char * const pbs6_groups[] = {
651 "gpio22",
652 };
653 static const char * const pbs7_groups[] = {
654 "gpio23",
655 };
656 static const char * const cci_timer1_groups[] = {
657 "gpio24",
658 };
659 static const char * const gcc_gp1_groups[] = {
660 "gpio24", "gpio86",
661 };
662 static const char * const pbs8_groups[] = {
663 "gpio24",
664 };
665 static const char * const cci_async_groups[] = {
666 "gpio25",
667 };
668 static const char * const cci_timer0_groups[] = {
669 "gpio25",
670 };
671 static const char * const pbs9_groups[] = {
672 "gpio25",
673 };
674 static const char * const pbs10_groups[] = {
675 "gpio26",
676 };
677 static const char * const vsense_trigger_groups[] = {
678 "gpio26",
679 };
680 static const char * const qdss_cti_groups[] = {
681 "gpio27", "gpio28", "gpio72", "gpio73", "gpio96", "gpio97",
682 };
683 static const char * const cci_timer2_groups[] = {
684 "gpio28",
685 };
686 static const char * const pwm_1_groups[] = {
687 "gpio28",
688 };
689 static const char * const gp_pdm0_groups[] = {
690 "gpio31", "gpio95",
691 };
692 static const char * const cci_timer3_groups[] = {
693 "gpio32",
694 };
695 static const char * const gp_pdm1_groups[] = {
696 "gpio32", "gpio96",
697 };
698 static const char * const gp_pdm2_groups[] = {
699 "gpio33", "gpio97",
700 };
701 static const char * const char_exec_groups[] = {
702 "gpio37", "gpio38",
703 };
704 static const char * const nav_gpio_groups[] = {
705 "gpio42", "gpio47", "gpio52", "gpio95", "gpio96", "gpio97", "gpio106",
706 "gpio107", "gpio108",
707 };
708 static const char * const pbs14_groups[] = {
709 "gpio47",
710 };
711 static const char * const vfr_1_groups[] = {
712 "gpio48",
713 };
714 static const char * const pbs15_groups[] = {
715 "gpio48",
716 };
717 static const char * const pa_indicator_groups[] = {
718 "gpio49",
719 };
720 static const char * const pwm_2_groups[] = {
721 "gpio51",
722 };
723 static const char * const gsm1_tx_groups[] = {
724 "gpio53",
725 };
726 static const char * const ssbi_wtr1_groups[] = {
727 "gpio59", "gpio60",
728 };
729 static const char * const pll_bypassnl_groups[] = {
730 "gpio62",
731 };
732 static const char * const pll_reset_groups[] = {
733 "gpio63",
734 };
735 static const char * const ddr_pxi0_groups[] = {
736 "gpio63", "gpio64",
737 };
738 static const char * const gsm0_tx_groups[] = {
739 "gpio64",
740 };
741 static const char * const gcc_gp2_groups[] = {
742 "gpio69", "gpio107",
743 };
744 static const char * const ddr_pxi1_groups[] = {
745 "gpio69", "gpio70",
746 };
747 static const char * const gcc_gp3_groups[] = {
748 "gpio70", "gpio106",
749 };
750 static const char * const dbg_out_groups[] = {
751 "gpio71",
752 };
753 static const char * const uim2_data_groups[] = {
754 "gpio72",
755 };
756 static const char * const pwm_3_groups[] = {
757 "gpio72",
758 };
759 static const char * const uim2_clk_groups[] = {
760 "gpio73",
761 };
762 static const char * const uim2_reset_groups[] = {
763 "gpio74",
764 };
765 static const char * const pwm_4_groups[] = {
766 "gpio74",
767 };
768 static const char * const uim2_present_groups[] = {
769 "gpio75",
770 };
771 static const char * const pwm_5_groups[] = {
772 "gpio75",
773 };
774 static const char * const uim1_data_groups[] = {
775 "gpio76",
776 };
777 static const char * const uim1_clk_groups[] = {
778 "gpio77",
779 };
780 static const char * const uim1_reset_groups[] = {
781 "gpio78",
782 };
783 static const char * const uim1_present_groups[] = {
784 "gpio79",
785 };
786 static const char * const mdp_vsync_groups[] = {
787 "gpio81", "gpio96", "gpio97",
788 };
789 static const char * const mdp_vsync_out_0_groups[] = {
790 "gpio81",
791 };
792 static const char * const mdp_vsync_out_1_groups[] = {
793 "gpio81",
794 };
795 static const char * const pwm_6_groups[] = {
796 "gpio82",
797 };
798 static const char * const pbs11_groups[] = {
799 "gpio87",
800 };
801 static const char * const usb_phy_groups[] = {
802 "gpio89",
803 };
804 static const char * const pwm_7_groups[] = {
805 "gpio89",
806 };
807 static const char * const mss_lte_groups[] = {
808 "gpio90", "gpio91",
809 };
810 static const char * const pbs12_groups[] = {
811 "gpio90",
812 };
813 static const char * const pbs13_groups[] = {
814 "gpio91",
815 };
816 static const char * const wlan1_adc0_groups[] = {
817 "gpio94",
818 };
819 static const char * const wlan1_adc1_groups[] = {
820 "gpio95",
821 };
822 static const char * const sd_write_groups[] = {
823 "gpio96",
824 };
825 static const char * const jitter_bist_groups[] = {
826 "gpio96", "gpio97",
827 };
828 static const char * const ddr_pxi2_groups[] = {
829 "gpio102", "gpio103",
830 };
831 static const char * const ddr_pxi3_groups[] = {
832 "gpio104", "gpio105",
833 };
834 static const char * const pwm_8_groups[] = {
835 "gpio104",
836 };
837 static const char * const pwm_9_groups[] = {
838 "gpio115",
839 };
840
841 static const struct pinfunction qcm2290_functions[] = {
842 MSM_PIN_FUNCTION(adsp_ext),
843 MSM_PIN_FUNCTION(agera_pll),
844 MSM_PIN_FUNCTION(atest),
845 MSM_PIN_FUNCTION(cam_mclk),
846 MSM_PIN_FUNCTION(cci_async),
847 MSM_PIN_FUNCTION(cci_i2c),
848 MSM_PIN_FUNCTION(cci_timer0),
849 MSM_PIN_FUNCTION(cci_timer1),
850 MSM_PIN_FUNCTION(cci_timer2),
851 MSM_PIN_FUNCTION(cci_timer3),
852 MSM_PIN_FUNCTION(char_exec),
853 MSM_PIN_FUNCTION(cri_trng),
854 MSM_PIN_FUNCTION(cri_trng0),
855 MSM_PIN_FUNCTION(cri_trng1),
856 MSM_PIN_FUNCTION(dac_calib),
857 MSM_PIN_FUNCTION(dbg_out),
858 MSM_PIN_FUNCTION(ddr_bist),
859 MSM_PIN_FUNCTION(ddr_pxi0),
860 MSM_PIN_FUNCTION(ddr_pxi1),
861 MSM_PIN_FUNCTION(ddr_pxi2),
862 MSM_PIN_FUNCTION(ddr_pxi3),
863 MSM_PIN_FUNCTION(gcc_gp1),
864 MSM_PIN_FUNCTION(gcc_gp2),
865 MSM_PIN_FUNCTION(gcc_gp3),
866 MSM_PIN_FUNCTION(gpio),
867 MSM_PIN_FUNCTION(gp_pdm0),
868 MSM_PIN_FUNCTION(gp_pdm1),
869 MSM_PIN_FUNCTION(gp_pdm2),
870 MSM_PIN_FUNCTION(gsm0_tx),
871 MSM_PIN_FUNCTION(gsm1_tx),
872 MSM_PIN_FUNCTION(jitter_bist),
873 MSM_PIN_FUNCTION(mdp_vsync),
874 MSM_PIN_FUNCTION(mdp_vsync_out_0),
875 MSM_PIN_FUNCTION(mdp_vsync_out_1),
876 MSM_PIN_FUNCTION(mpm_pwr),
877 MSM_PIN_FUNCTION(mss_lte),
878 MSM_PIN_FUNCTION(m_voc),
879 MSM_PIN_FUNCTION(nav_gpio),
880 MSM_PIN_FUNCTION(pa_indicator),
881 MSM_PIN_FUNCTION(pbs0),
882 MSM_PIN_FUNCTION(pbs1),
883 MSM_PIN_FUNCTION(pbs2),
884 MSM_PIN_FUNCTION(pbs3),
885 MSM_PIN_FUNCTION(pbs4),
886 MSM_PIN_FUNCTION(pbs5),
887 MSM_PIN_FUNCTION(pbs6),
888 MSM_PIN_FUNCTION(pbs7),
889 MSM_PIN_FUNCTION(pbs8),
890 MSM_PIN_FUNCTION(pbs9),
891 MSM_PIN_FUNCTION(pbs10),
892 MSM_PIN_FUNCTION(pbs11),
893 MSM_PIN_FUNCTION(pbs12),
894 MSM_PIN_FUNCTION(pbs13),
895 MSM_PIN_FUNCTION(pbs14),
896 MSM_PIN_FUNCTION(pbs15),
897 MSM_PIN_FUNCTION(pbs_out),
898 MSM_PIN_FUNCTION(phase_flag),
899 MSM_PIN_FUNCTION(pll_bist),
900 MSM_PIN_FUNCTION(pll_bypassnl),
901 MSM_PIN_FUNCTION(pll_reset),
902 MSM_PIN_FUNCTION(prng_rosc),
903 MSM_PIN_FUNCTION(pwm_0),
904 MSM_PIN_FUNCTION(pwm_1),
905 MSM_PIN_FUNCTION(pwm_2),
906 MSM_PIN_FUNCTION(pwm_3),
907 MSM_PIN_FUNCTION(pwm_4),
908 MSM_PIN_FUNCTION(pwm_5),
909 MSM_PIN_FUNCTION(pwm_6),
910 MSM_PIN_FUNCTION(pwm_7),
911 MSM_PIN_FUNCTION(pwm_8),
912 MSM_PIN_FUNCTION(pwm_9),
913 MSM_PIN_FUNCTION(qdss_cti),
914 MSM_PIN_FUNCTION(qdss_gpio),
915 MSM_PIN_FUNCTION(qup0),
916 MSM_PIN_FUNCTION(qup1),
917 MSM_PIN_FUNCTION(qup2),
918 MSM_PIN_FUNCTION(qup3),
919 MSM_PIN_FUNCTION(qup4),
920 MSM_PIN_FUNCTION(qup5),
921 MSM_PIN_FUNCTION(sdc1_tb),
922 MSM_PIN_FUNCTION(sdc2_tb),
923 MSM_PIN_FUNCTION(sd_write),
924 MSM_PIN_FUNCTION(ssbi_wtr1),
925 MSM_PIN_FUNCTION(tgu_ch0),
926 MSM_PIN_FUNCTION(tgu_ch1),
927 MSM_PIN_FUNCTION(tgu_ch2),
928 MSM_PIN_FUNCTION(tgu_ch3),
929 MSM_PIN_FUNCTION(tsense_pwm),
930 MSM_PIN_FUNCTION(uim1_clk),
931 MSM_PIN_FUNCTION(uim1_data),
932 MSM_PIN_FUNCTION(uim1_present),
933 MSM_PIN_FUNCTION(uim1_reset),
934 MSM_PIN_FUNCTION(uim2_clk),
935 MSM_PIN_FUNCTION(uim2_data),
936 MSM_PIN_FUNCTION(uim2_present),
937 MSM_PIN_FUNCTION(uim2_reset),
938 MSM_PIN_FUNCTION(usb_phy),
939 MSM_PIN_FUNCTION(vfr_1),
940 MSM_PIN_FUNCTION(vsense_trigger),
941 MSM_PIN_FUNCTION(wlan1_adc0),
942 MSM_PIN_FUNCTION(wlan1_adc1),
943 };
944
945 /* Every pin is maintained as a single group, and missing or non-existing pin
946 * would be maintained as dummy group to synchronize pin group index with
947 * pin descriptor registered with pinctrl core.
948 * Clients would not be able to request these dummy pin groups.
949 */
950 static const struct msm_pingroup qcm2290_groups[] = {
951 [0] = PINGROUP(0, qup0, m_voc, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _),
952 [1] = PINGROUP(1, qup0, mpm_pwr, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _),
953 [2] = PINGROUP(2, qup0, ddr_bist, _, phase_flag, qdss_gpio, dac_calib, atest, _, _),
954 [3] = PINGROUP(3, qup0, ddr_bist, _, phase_flag, qdss_gpio, dac_calib, atest, _, _),
955 [4] = PINGROUP(4, qup1, cri_trng0, _, phase_flag, dac_calib, atest, _, _, _),
956 [5] = PINGROUP(5, qup1, cri_trng1, _, phase_flag, dac_calib, atest, _, _, _),
957 [6] = PINGROUP(6, qup2, _, phase_flag, dac_calib, atest, _, _, _, _),
958 [7] = PINGROUP(7, qup2, _, _, _, _, _, _, _, _),
959 [8] = PINGROUP(8, qup3, pbs_out, pll_bist, _, qdss_gpio, _, tsense_pwm, _, _),
960 [9] = PINGROUP(9, qup3, pbs_out, pll_bist, _, qdss_gpio, _, _, _, _),
961 [10] = PINGROUP(10, qup3, agera_pll, _, pbs0, qdss_gpio, _, _, _, _),
962 [11] = PINGROUP(11, qup3, agera_pll, _, pbs1, qdss_gpio, _, _, _, _),
963 [12] = PINGROUP(12, qup4, tgu_ch0, _, _, _, _, _, _, _),
964 [13] = PINGROUP(13, qup4, tgu_ch1, _, _, _, _, _, _, _),
965 [14] = PINGROUP(14, qup5, tgu_ch2, _, phase_flag, qdss_gpio, dac_calib, _, _, _),
966 [15] = PINGROUP(15, qup5, tgu_ch3, _, phase_flag, qdss_gpio, dac_calib, _, _, _),
967 [16] = PINGROUP(16, qup5, _, phase_flag, qdss_gpio, dac_calib, _, _, _, _),
968 [17] = PINGROUP(17, qup5, _, phase_flag, qdss_gpio, dac_calib, _, _, _, _),
969 [18] = PINGROUP(18, sdc2_tb, cri_trng, pbs2, qdss_gpio, _, pwm_0, _, _, _),
970 [19] = PINGROUP(19, sdc1_tb, pbs3, qdss_gpio, _, _, _, _, _, _),
971 [20] = PINGROUP(20, cam_mclk, pbs4, qdss_gpio, _, _, _, _, _, _),
972 [21] = PINGROUP(21, cam_mclk, adsp_ext, pbs5, qdss_gpio, _, _, _, _, _),
973 [22] = PINGROUP(22, cci_i2c, prng_rosc, _, pbs6, phase_flag, qdss_gpio, dac_calib, atest, _),
974 [23] = PINGROUP(23, cci_i2c, prng_rosc, _, pbs7, phase_flag, qdss_gpio, dac_calib, atest, _),
975 [24] = PINGROUP(24, cci_timer1, gcc_gp1, _, pbs8, phase_flag, qdss_gpio, dac_calib, atest, _),
976 [25] = PINGROUP(25, cci_async, cci_timer0, _, pbs9, phase_flag, qdss_gpio, dac_calib, atest, _),
977 [26] = PINGROUP(26, _, pbs10, phase_flag, qdss_gpio, dac_calib, atest, vsense_trigger, _, _),
978 [27] = PINGROUP(27, cam_mclk, qdss_cti, _, _, _, _, _, _, _),
979 [28] = PINGROUP(28, cam_mclk, cci_timer2, qdss_cti, _, pwm_1, _, _, _, _),
980 [29] = PINGROUP(29, cci_i2c, _, phase_flag, dac_calib, atest, _, _, _, _),
981 [30] = PINGROUP(30, cci_i2c, _, phase_flag, dac_calib, atest, _, _, _, _),
982 [31] = PINGROUP(31, gp_pdm0, _, phase_flag, dac_calib, atest, _, _, _, _),
983 [32] = PINGROUP(32, cci_timer3, gp_pdm1, _, phase_flag, dac_calib, atest, _, _, _),
984 [33] = PINGROUP(33, gp_pdm2, _, phase_flag, dac_calib, atest, _, _, _, _),
985 [34] = PINGROUP(34, _, _, _, _, _, _, _, _, _),
986 [35] = PINGROUP(35, _, phase_flag, _, _, _, _, _, _, _),
987 [36] = PINGROUP(36, _, phase_flag, _, _, _, _, _, _, _),
988 [37] = PINGROUP(37, _, _, char_exec, _, _, _, _, _, _),
989 [38] = PINGROUP(38, _, _, _, char_exec, _, _, _, _, _),
990 [39] = PINGROUP(39, _, _, _, _, _, _, _, _, _),
991 [40] = PINGROUP(40, _, _, _, _, _, _, _, _, _),
992 [41] = PINGROUP(41, _, _, _, _, _, _, _, _, _),
993 [42] = PINGROUP(42, _, nav_gpio, _, _, _, _, _, _, _),
994 [43] = PINGROUP(43, _, _, phase_flag, _, _, _, _, _, _),
995 [44] = PINGROUP(44, _, _, phase_flag, _, _, _, _, _, _),
996 [45] = PINGROUP(45, _, _, phase_flag, _, _, _, _, _, _),
997 [46] = PINGROUP(46, _, _, _, _, _, _, _, _, _),
998 [47] = PINGROUP(47, _, nav_gpio, pbs14, qdss_gpio, _, _, _, _, _),
999 [48] = PINGROUP(48, _, vfr_1, _, pbs15, qdss_gpio, _, _, _, _),
1000 [49] = PINGROUP(49, _, pa_indicator, _, _, _, _, _, _, _),
1001 [50] = PINGROUP(50, _, _, _, _, _, _, _, _, _),
1002 [51] = PINGROUP(51, _, _, _, pwm_2, _, _, _, _, _),
1003 [52] = PINGROUP(52, _, nav_gpio, pbs_out, _, _, _, _, _, _),
1004 [53] = PINGROUP(53, _, gsm1_tx, _, _, _, _, _, _, _),
1005 [54] = PINGROUP(54, _, _, _, _, _, _, _, _, _),
1006 [55] = PINGROUP(55, _, _, _, _, _, _, _, _, _),
1007 [56] = PINGROUP(56, _, _, _, _, _, _, _, _, _),
1008 [57] = PINGROUP(57, _, _, _, _, _, _, _, _, _),
1009 [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _),
1010 [59] = PINGROUP(59, _, ssbi_wtr1, _, _, _, _, _, _, _),
1011 [60] = PINGROUP(60, _, ssbi_wtr1, _, _, _, _, _, _, _),
1012 [61] = PINGROUP(61, _, _, _, _, _, _, _, _, _),
1013 [62] = PINGROUP(62, _, pll_bypassnl, _, _, _, _, _, _, _),
1014 [63] = PINGROUP(63, pll_reset, _, phase_flag, ddr_pxi0, _, _, _, _, _),
1015 [64] = PINGROUP(64, gsm0_tx, _, phase_flag, ddr_pxi0, _, _, _, _, _),
1016 [65] = PINGROUP(65, _, _, _, _, _, _, _, _, _),
1017 [66] = PINGROUP(66, _, _, _, _, _, _, _, _, _),
1018 [67] = PINGROUP(67, _, _, _, _, _, _, _, _, _),
1019 [68] = PINGROUP(68, _, _, _, _, _, _, _, _, _),
1020 [69] = PINGROUP(69, qup1, gcc_gp2, qdss_gpio, ddr_pxi1, _, _, _, _, _),
1021 [70] = PINGROUP(70, qup1, gcc_gp3, qdss_gpio, ddr_pxi1, _, _, _, _, _),
1022 [71] = PINGROUP(71, qup2, dbg_out, _, _, _, _, _, _, _),
1023 [72] = PINGROUP(72, uim2_data, qdss_cti, _, pwm_3, _, _, _, _, _),
1024 [73] = PINGROUP(73, uim2_clk, _, qdss_cti, _, _, _, _, _, _),
1025 [74] = PINGROUP(74, uim2_reset, _, _, pwm_4, _, _, _, _, _),
1026 [75] = PINGROUP(75, uim2_present, _, _, pwm_5, _, _, _, _, _),
1027 [76] = PINGROUP(76, uim1_data, _, _, _, _, _, _, _, _),
1028 [77] = PINGROUP(77, uim1_clk, _, _, _, _, _, _, _, _),
1029 [78] = PINGROUP(78, uim1_reset, _, _, _, _, _, _, _, _),
1030 [79] = PINGROUP(79, uim1_present, _, _, _, _, _, _, _, _),
1031 [80] = PINGROUP(80, qup2, dac_calib, _, _, _, _, _, _, _),
1032 [81] = PINGROUP(81, mdp_vsync_out_0, mdp_vsync_out_1, mdp_vsync, dac_calib, _, _, _, _, _),
1033 [82] = PINGROUP(82, qup0, dac_calib, _, pwm_6, _, _, _, _, _),
1034 [83] = PINGROUP(83, _, _, _, _, _, _, _, _, _),
1035 [84] = PINGROUP(84, _, _, _, _, _, _, _, _, _),
1036 [85] = PINGROUP(85, _, _, _, _, _, _, _, _, _),
1037 [86] = PINGROUP(86, qup0, gcc_gp1, atest, _, _, _, _, _, _),
1038 [87] = PINGROUP(87, pbs11, qdss_gpio, _, _, _, _, _, _, _),
1039 [88] = PINGROUP(88, _, _, _, _, _, _, _, _, _),
1040 [89] = PINGROUP(89, usb_phy, atest, _, pwm_7, _, _, _, _, _),
1041 [90] = PINGROUP(90, mss_lte, pbs12, qdss_gpio, _, _, _, _, _, _),
1042 [91] = PINGROUP(91, mss_lte, pbs13, qdss_gpio, _, _, _, _, _, _),
1043 [92] = PINGROUP(92, _, _, _, _, _, _, _, _, _),
1044 [93] = PINGROUP(93, _, _, _, _, _, _, _, _, _),
1045 [94] = PINGROUP(94, _, qdss_gpio, wlan1_adc0, _, _, _, _, _, _),
1046 [95] = PINGROUP(95, nav_gpio, gp_pdm0, qdss_gpio, wlan1_adc1, _, _, _, _, _),
1047 [96] = PINGROUP(96, qup4, nav_gpio, mdp_vsync, gp_pdm1, sd_write, jitter_bist, qdss_cti, qdss_cti, _),
1048 [97] = PINGROUP(97, qup4, nav_gpio, mdp_vsync, gp_pdm2, jitter_bist, qdss_cti, qdss_cti, _, _),
1049 [98] = PINGROUP(98, _, _, _, _, _, _, _, _, _),
1050 [99] = PINGROUP(99, _, _, _, _, _, _, _, _, _),
1051 [100] = PINGROUP(100, atest, _, _, _, _, _, _, _, _),
1052 [101] = PINGROUP(101, atest, _, _, _, _, _, _, _, _),
1053 [102] = PINGROUP(102, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _),
1054 [103] = PINGROUP(103, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _),
1055 [104] = PINGROUP(104, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, pwm_8, _, _),
1056 [105] = PINGROUP(105, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, _),
1057 [106] = PINGROUP(106, nav_gpio, gcc_gp3, qdss_gpio, _, _, _, _, _, _),
1058 [107] = PINGROUP(107, nav_gpio, gcc_gp2, qdss_gpio, _, _, _, _, _, _),
1059 [108] = PINGROUP(108, nav_gpio, _, _, _, _, _, _, _, _),
1060 [109] = PINGROUP(109, _, qdss_gpio, _, _, _, _, _, _, _),
1061 [110] = PINGROUP(110, _, qdss_gpio, _, _, _, _, _, _, _),
1062 [111] = PINGROUP(111, _, _, _, _, _, _, _, _, _),
1063 [112] = PINGROUP(112, _, _, _, _, _, _, _, _, _),
1064 [113] = PINGROUP(113, _, _, _, _, _, _, _, _, _),
1065 [114] = PINGROUP(114, _, _, _, _, _, _, _, _, _),
1066 [115] = PINGROUP(115, _, pwm_9, _, _, _, _, _, _, _),
1067 [116] = PINGROUP(116, _, _, _, _, _, _, _, _, _),
1068 [117] = PINGROUP(117, _, _, _, _, _, _, _, _, _),
1069 [118] = PINGROUP(118, _, _, _, _, _, _, _, _, _),
1070 [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _),
1071 [120] = PINGROUP(120, _, _, _, _, _, _, _, _, _),
1072 [121] = PINGROUP(121, _, _, _, _, _, _, _, _, _),
1073 [122] = PINGROUP(122, _, _, _, _, _, _, _, _, _),
1074 [123] = PINGROUP(123, _, _, _, _, _, _, _, _, _),
1075 [124] = PINGROUP(124, _, _, _, _, _, _, _, _, _),
1076 [125] = PINGROUP(125, _, _, _, _, _, _, _, _, _),
1077 [126] = PINGROUP(126, _, _, _, _, _, _, _, _, _),
1078 [127] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x84004, 0, 0),
1079 [128] = SDC_QDSD_PINGROUP(sdc1_clk, 0x84000, 13, 6),
1080 [129] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x84000, 11, 3),
1081 [130] = SDC_QDSD_PINGROUP(sdc1_data, 0x84000, 9, 0),
1082 [131] = SDC_QDSD_PINGROUP(sdc2_clk, 0x86000, 14, 6),
1083 [132] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x86000, 11, 3),
1084 [133] = SDC_QDSD_PINGROUP(sdc2_data, 0x86000, 9, 0),
1085 };
1086
1087 static const struct msm_gpio_wakeirq_map qcm2290_mpm_map[] = {
1088 { 0, 84 }, { 3, 75 }, { 4, 16 }, { 6, 59 }, { 8, 63 }, { 11, 17 },
1089 { 13, 18 }, { 14, 51 }, { 17, 20 }, { 18, 52 }, { 19, 53 }, { 24, 6 },
1090 { 25, 71 }, { 27, 73 }, { 28, 41 }, { 31, 27 }, { 32, 54 }, { 33, 55 },
1091 { 34, 56 }, { 35, 57 }, { 36, 58 }, { 39, 28 }, { 46, 29 }, { 62, 60 },
1092 { 63, 61 }, { 64, 62 }, { 69, 33 }, { 70, 34 }, { 72, 72 }, { 75, 35 },
1093 { 79, 36 }, { 80, 21 }, { 81, 38 }, { 86, 19 }, { 87, 42 }, { 88, 43 },
1094 { 89, 45 }, { 91, 74 }, { 94, 47 }, { 95, 48 }, { 96, 49 }, { 97, 50 },
1095 };
1096
1097 static const struct msm_pinctrl_soc_data qcm2290_pinctrl = {
1098 .pins = qcm2290_pins,
1099 .npins = ARRAY_SIZE(qcm2290_pins),
1100 .functions = qcm2290_functions,
1101 .nfunctions = ARRAY_SIZE(qcm2290_functions),
1102 .groups = qcm2290_groups,
1103 .ngroups = ARRAY_SIZE(qcm2290_groups),
1104 .ngpios = 127,
1105 .wakeirq_map = qcm2290_mpm_map,
1106 .nwakeirq_map = ARRAY_SIZE(qcm2290_mpm_map),
1107 };
1108
qcm2290_pinctrl_probe(struct platform_device * pdev)1109 static int qcm2290_pinctrl_probe(struct platform_device *pdev)
1110 {
1111 return msm_pinctrl_probe(pdev, &qcm2290_pinctrl);
1112 }
1113
1114 static const struct of_device_id qcm2290_pinctrl_of_match[] = {
1115 { .compatible = "qcom,qcm2290-tlmm", },
1116 { },
1117 };
1118
1119 static struct platform_driver qcm2290_pinctrl_driver = {
1120 .driver = {
1121 .name = "qcm2290-pinctrl",
1122 .of_match_table = qcm2290_pinctrl_of_match,
1123 },
1124 .probe = qcm2290_pinctrl_probe,
1125 .remove_new = msm_pinctrl_remove,
1126 };
1127
qcm2290_pinctrl_init(void)1128 static int __init qcm2290_pinctrl_init(void)
1129 {
1130 return platform_driver_register(&qcm2290_pinctrl_driver);
1131 }
1132 arch_initcall(qcm2290_pinctrl_init);
1133
qcm2290_pinctrl_exit(void)1134 static void __exit qcm2290_pinctrl_exit(void)
1135 {
1136 platform_driver_unregister(&qcm2290_pinctrl_driver);
1137 }
1138 module_exit(qcm2290_pinctrl_exit);
1139
1140 MODULE_DESCRIPTION("QTI QCM2290 pinctrl driver");
1141 MODULE_LICENSE("GPL v2");
1142 MODULE_DEVICE_TABLE(of, qcm2290_pinctrl_of_match);
1143