1 /*
2 * QEMU generic PowerPC hardware System Emulator
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/irq.h"
27 #include "hw/ppc/ppc.h"
28 #include "hw/ppc/ppc_e500.h"
29 #include "qemu/timer.h"
30 #include "sysemu/cpus.h"
31 #include "qemu/log.h"
32 #include "qemu/main-loop.h"
33 #include "qemu/error-report.h"
34 #include "sysemu/kvm.h"
35 #include "sysemu/replay.h"
36 #include "sysemu/runstate.h"
37 #include "kvm_ppc.h"
38 #include "migration/vmstate.h"
39 #include "trace.h"
40
41 static void cpu_ppc_tb_stop (CPUPPCState *env);
42 static void cpu_ppc_tb_start (CPUPPCState *env);
43
ppc_set_irq(PowerPCCPU * cpu,int irq,int level)44 void ppc_set_irq(PowerPCCPU *cpu, int irq, int level)
45 {
46 CPUPPCState *env = &cpu->env;
47 unsigned int old_pending;
48
49 /* We may already have the BQL if coming from the reset path */
50 BQL_LOCK_GUARD();
51
52 old_pending = env->pending_interrupts;
53
54 if (level) {
55 env->pending_interrupts |= irq;
56 } else {
57 env->pending_interrupts &= ~irq;
58 }
59
60 if (old_pending != env->pending_interrupts) {
61 ppc_maybe_interrupt(env);
62 if (kvm_enabled()) {
63 kvmppc_set_interrupt(cpu, irq, level);
64 }
65 }
66
67 trace_ppc_irq_set_exit(env, irq, level, env->pending_interrupts,
68 CPU(cpu)->interrupt_request);
69 }
70
71 /* PowerPC 6xx / 7xx internal IRQ controller */
ppc6xx_set_irq(void * opaque,int pin,int level)72 static void ppc6xx_set_irq(void *opaque, int pin, int level)
73 {
74 PowerPCCPU *cpu = opaque;
75 CPUPPCState *env = &cpu->env;
76 int cur_level;
77
78 trace_ppc_irq_set(env, pin, level);
79
80 cur_level = (env->irq_input_state >> pin) & 1;
81 /* Don't generate spurious events */
82 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
83 CPUState *cs = CPU(cpu);
84
85 switch (pin) {
86 case PPC6xx_INPUT_TBEN:
87 /* Level sensitive - active high */
88 trace_ppc_irq_set_state("time base", level);
89 if (level) {
90 cpu_ppc_tb_start(env);
91 } else {
92 cpu_ppc_tb_stop(env);
93 }
94 break;
95 case PPC6xx_INPUT_INT:
96 /* Level sensitive - active high */
97 trace_ppc_irq_set_state("external IRQ", level);
98 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
99 break;
100 case PPC6xx_INPUT_SMI:
101 /* Level sensitive - active high */
102 trace_ppc_irq_set_state("SMI IRQ", level);
103 ppc_set_irq(cpu, PPC_INTERRUPT_SMI, level);
104 break;
105 case PPC6xx_INPUT_MCP:
106 /* Negative edge sensitive */
107 /* XXX: TODO: actual reaction may depends on HID0 status
108 * 603/604/740/750: check HID0[EMCP]
109 */
110 if (cur_level == 1 && level == 0) {
111 trace_ppc_irq_set_state("machine check", 1);
112 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
113 }
114 break;
115 case PPC6xx_INPUT_CKSTP_IN:
116 /* Level sensitive - active low */
117 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
118 /* XXX: Note that the only way to restart the CPU is to reset it */
119 if (level) {
120 trace_ppc_irq_cpu("stop");
121 cs->halted = 1;
122 }
123 break;
124 case PPC6xx_INPUT_HRESET:
125 /* Level sensitive - active low */
126 if (level) {
127 trace_ppc_irq_reset("CPU");
128 cpu_interrupt(cs, CPU_INTERRUPT_RESET);
129 }
130 break;
131 case PPC6xx_INPUT_SRESET:
132 trace_ppc_irq_set_state("RESET IRQ", level);
133 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
134 break;
135 default:
136 g_assert_not_reached();
137 }
138 if (level)
139 env->irq_input_state |= 1 << pin;
140 else
141 env->irq_input_state &= ~(1 << pin);
142 }
143 }
144
ppc6xx_irq_init(PowerPCCPU * cpu)145 void ppc6xx_irq_init(PowerPCCPU *cpu)
146 {
147 qdev_init_gpio_in(DEVICE(cpu), ppc6xx_set_irq, PPC6xx_INPUT_NB);
148 }
149
150 #if defined(TARGET_PPC64)
151 /* PowerPC 970 internal IRQ controller */
ppc970_set_irq(void * opaque,int pin,int level)152 static void ppc970_set_irq(void *opaque, int pin, int level)
153 {
154 PowerPCCPU *cpu = opaque;
155 CPUPPCState *env = &cpu->env;
156 int cur_level;
157
158 trace_ppc_irq_set(env, pin, level);
159
160 cur_level = (env->irq_input_state >> pin) & 1;
161 /* Don't generate spurious events */
162 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
163 CPUState *cs = CPU(cpu);
164
165 switch (pin) {
166 case PPC970_INPUT_INT:
167 /* Level sensitive - active high */
168 trace_ppc_irq_set_state("external IRQ", level);
169 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
170 break;
171 case PPC970_INPUT_THINT:
172 /* Level sensitive - active high */
173 trace_ppc_irq_set_state("SMI IRQ", level);
174 ppc_set_irq(cpu, PPC_INTERRUPT_THERM, level);
175 break;
176 case PPC970_INPUT_MCP:
177 /* Negative edge sensitive */
178 /* XXX: TODO: actual reaction may depends on HID0 status
179 * 603/604/740/750: check HID0[EMCP]
180 */
181 if (cur_level == 1 && level == 0) {
182 trace_ppc_irq_set_state("machine check", 1);
183 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
184 }
185 break;
186 case PPC970_INPUT_CKSTP:
187 /* Level sensitive - active low */
188 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
189 if (level) {
190 trace_ppc_irq_cpu("stop");
191 cs->halted = 1;
192 } else {
193 trace_ppc_irq_cpu("restart");
194 cs->halted = 0;
195 qemu_cpu_kick(cs);
196 }
197 break;
198 case PPC970_INPUT_HRESET:
199 /* Level sensitive - active low */
200 if (level) {
201 cpu_interrupt(cs, CPU_INTERRUPT_RESET);
202 }
203 break;
204 case PPC970_INPUT_SRESET:
205 trace_ppc_irq_set_state("RESET IRQ", level);
206 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
207 break;
208 case PPC970_INPUT_TBEN:
209 trace_ppc_irq_set_state("TBEN IRQ", level);
210 /* XXX: TODO */
211 break;
212 default:
213 g_assert_not_reached();
214 }
215 if (level)
216 env->irq_input_state |= 1 << pin;
217 else
218 env->irq_input_state &= ~(1 << pin);
219 }
220 }
221
ppc970_irq_init(PowerPCCPU * cpu)222 void ppc970_irq_init(PowerPCCPU *cpu)
223 {
224 qdev_init_gpio_in(DEVICE(cpu), ppc970_set_irq, PPC970_INPUT_NB);
225 }
226
227 /* POWER7 internal IRQ controller */
power7_set_irq(void * opaque,int pin,int level)228 static void power7_set_irq(void *opaque, int pin, int level)
229 {
230 PowerPCCPU *cpu = opaque;
231
232 trace_ppc_irq_set(&cpu->env, pin, level);
233
234 switch (pin) {
235 case POWER7_INPUT_INT:
236 /* Level sensitive - active high */
237 trace_ppc_irq_set_state("external IRQ", level);
238 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
239 break;
240 default:
241 g_assert_not_reached();
242 }
243 }
244
ppcPOWER7_irq_init(PowerPCCPU * cpu)245 void ppcPOWER7_irq_init(PowerPCCPU *cpu)
246 {
247 qdev_init_gpio_in(DEVICE(cpu), power7_set_irq, POWER7_INPUT_NB);
248 }
249
250 /* POWER9 internal IRQ controller */
power9_set_irq(void * opaque,int pin,int level)251 static void power9_set_irq(void *opaque, int pin, int level)
252 {
253 PowerPCCPU *cpu = opaque;
254
255 trace_ppc_irq_set(&cpu->env, pin, level);
256
257 switch (pin) {
258 case POWER9_INPUT_INT:
259 /* Level sensitive - active high */
260 trace_ppc_irq_set_state("external IRQ", level);
261 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
262 break;
263 case POWER9_INPUT_HINT:
264 /* Level sensitive - active high */
265 trace_ppc_irq_set_state("HV external IRQ", level);
266 ppc_set_irq(cpu, PPC_INTERRUPT_HVIRT, level);
267 break;
268 default:
269 g_assert_not_reached();
270 }
271 }
272
ppcPOWER9_irq_init(PowerPCCPU * cpu)273 void ppcPOWER9_irq_init(PowerPCCPU *cpu)
274 {
275 qdev_init_gpio_in(DEVICE(cpu), power9_set_irq, POWER9_INPUT_NB);
276 }
277 #endif /* defined(TARGET_PPC64) */
278
ppc40x_core_reset(PowerPCCPU * cpu)279 void ppc40x_core_reset(PowerPCCPU *cpu)
280 {
281 CPUPPCState *env = &cpu->env;
282 target_ulong dbsr;
283
284 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC core\n");
285 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
286 dbsr = env->spr[SPR_40x_DBSR];
287 dbsr &= ~0x00000300;
288 dbsr |= 0x00000100;
289 env->spr[SPR_40x_DBSR] = dbsr;
290 }
291
ppc40x_chip_reset(PowerPCCPU * cpu)292 void ppc40x_chip_reset(PowerPCCPU *cpu)
293 {
294 CPUPPCState *env = &cpu->env;
295 target_ulong dbsr;
296
297 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC chip\n");
298 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
299 /* XXX: TODO reset all internal peripherals */
300 dbsr = env->spr[SPR_40x_DBSR];
301 dbsr &= ~0x00000300;
302 dbsr |= 0x00000200;
303 env->spr[SPR_40x_DBSR] = dbsr;
304 }
305
ppc40x_system_reset(PowerPCCPU * cpu)306 void ppc40x_system_reset(PowerPCCPU *cpu)
307 {
308 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC system\n");
309 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
310 }
311
store_40x_dbcr0(CPUPPCState * env,uint32_t val)312 void store_40x_dbcr0(CPUPPCState *env, uint32_t val)
313 {
314 PowerPCCPU *cpu = env_archcpu(env);
315
316 bql_lock();
317
318 switch ((val >> 28) & 0x3) {
319 case 0x0:
320 /* No action */
321 break;
322 case 0x1:
323 /* Core reset */
324 ppc40x_core_reset(cpu);
325 break;
326 case 0x2:
327 /* Chip reset */
328 ppc40x_chip_reset(cpu);
329 break;
330 case 0x3:
331 /* System reset */
332 ppc40x_system_reset(cpu);
333 break;
334 }
335
336 bql_unlock();
337 }
338
339 /* PowerPC 40x internal IRQ controller */
ppc40x_set_irq(void * opaque,int pin,int level)340 static void ppc40x_set_irq(void *opaque, int pin, int level)
341 {
342 PowerPCCPU *cpu = opaque;
343 CPUPPCState *env = &cpu->env;
344 int cur_level;
345
346 trace_ppc_irq_set(env, pin, level);
347
348 cur_level = (env->irq_input_state >> pin) & 1;
349 /* Don't generate spurious events */
350 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
351 CPUState *cs = CPU(cpu);
352
353 switch (pin) {
354 case PPC40x_INPUT_RESET_SYS:
355 if (level) {
356 trace_ppc_irq_reset("system");
357 ppc40x_system_reset(cpu);
358 }
359 break;
360 case PPC40x_INPUT_RESET_CHIP:
361 if (level) {
362 trace_ppc_irq_reset("chip");
363 ppc40x_chip_reset(cpu);
364 }
365 break;
366 case PPC40x_INPUT_RESET_CORE:
367 /* XXX: TODO: update DBSR[MRR] */
368 if (level) {
369 trace_ppc_irq_reset("core");
370 ppc40x_core_reset(cpu);
371 }
372 break;
373 case PPC40x_INPUT_CINT:
374 /* Level sensitive - active high */
375 trace_ppc_irq_set_state("critical IRQ", level);
376 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
377 break;
378 case PPC40x_INPUT_INT:
379 /* Level sensitive - active high */
380 trace_ppc_irq_set_state("external IRQ", level);
381 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
382 break;
383 case PPC40x_INPUT_HALT:
384 /* Level sensitive - active low */
385 if (level) {
386 trace_ppc_irq_cpu("stop");
387 cs->halted = 1;
388 } else {
389 trace_ppc_irq_cpu("restart");
390 cs->halted = 0;
391 qemu_cpu_kick(cs);
392 }
393 break;
394 case PPC40x_INPUT_DEBUG:
395 /* Level sensitive - active high */
396 trace_ppc_irq_set_state("debug pin", level);
397 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
398 break;
399 default:
400 g_assert_not_reached();
401 }
402 if (level)
403 env->irq_input_state |= 1 << pin;
404 else
405 env->irq_input_state &= ~(1 << pin);
406 }
407 }
408
ppc40x_irq_init(PowerPCCPU * cpu)409 void ppc40x_irq_init(PowerPCCPU *cpu)
410 {
411 qdev_init_gpio_in(DEVICE(cpu), ppc40x_set_irq, PPC40x_INPUT_NB);
412 }
413
414 /* PowerPC E500 internal IRQ controller */
ppce500_set_irq(void * opaque,int pin,int level)415 static void ppce500_set_irq(void *opaque, int pin, int level)
416 {
417 PowerPCCPU *cpu = opaque;
418 CPUPPCState *env = &cpu->env;
419 int cur_level;
420
421 trace_ppc_irq_set(env, pin, level);
422
423 cur_level = (env->irq_input_state >> pin) & 1;
424 /* Don't generate spurious events */
425 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
426 switch (pin) {
427 case PPCE500_INPUT_MCK:
428 if (level) {
429 trace_ppc_irq_reset("system");
430 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
431 }
432 break;
433 case PPCE500_INPUT_RESET_CORE:
434 if (level) {
435 trace_ppc_irq_reset("core");
436 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, level);
437 }
438 break;
439 case PPCE500_INPUT_CINT:
440 /* Level sensitive - active high */
441 trace_ppc_irq_set_state("critical IRQ", level);
442 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
443 break;
444 case PPCE500_INPUT_INT:
445 /* Level sensitive - active high */
446 trace_ppc_irq_set_state("core IRQ", level);
447 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
448 break;
449 case PPCE500_INPUT_DEBUG:
450 /* Level sensitive - active high */
451 trace_ppc_irq_set_state("debug pin", level);
452 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
453 break;
454 default:
455 g_assert_not_reached();
456 }
457 if (level)
458 env->irq_input_state |= 1 << pin;
459 else
460 env->irq_input_state &= ~(1 << pin);
461 }
462 }
463
ppce500_irq_init(PowerPCCPU * cpu)464 void ppce500_irq_init(PowerPCCPU *cpu)
465 {
466 qdev_init_gpio_in(DEVICE(cpu), ppce500_set_irq, PPCE500_INPUT_NB);
467 }
468
469 /* Enable or Disable the E500 EPR capability */
ppce500_set_mpic_proxy(bool enabled)470 void ppce500_set_mpic_proxy(bool enabled)
471 {
472 CPUState *cs;
473
474 CPU_FOREACH(cs) {
475 PowerPCCPU *cpu = POWERPC_CPU(cs);
476
477 cpu->env.mpic_proxy = enabled;
478 if (kvm_enabled()) {
479 kvmppc_set_mpic_proxy(cpu, enabled);
480 }
481 }
482 }
483
484 /*****************************************************************************/
485 /* PowerPC time base and decrementer emulation */
486
487 /*
488 * Conversion between QEMU_CLOCK_VIRTUAL ns and timebase (TB) ticks:
489 * TB ticks are arrived at by multiplying tb_freq then dividing by
490 * ns per second, and rounding down. TB ticks drive all clocks and
491 * timers in the target machine.
492 *
493 * Converting TB intervals to ns for the purpose of setting a
494 * QEMU_CLOCK_VIRTUAL timer should go the other way, but rounding
495 * up. Rounding down could cause the timer to fire before the TB
496 * value has been reached.
497 */
ns_to_tb(uint32_t freq,int64_t clock)498 static uint64_t ns_to_tb(uint32_t freq, int64_t clock)
499 {
500 return muldiv64(clock, freq, NANOSECONDS_PER_SECOND);
501 }
502
503 /* virtual clock in TB ticks, not adjusted by TB offset */
tb_to_ns_round_up(uint32_t freq,uint64_t tb)504 static int64_t tb_to_ns_round_up(uint32_t freq, uint64_t tb)
505 {
506 return muldiv64_round_up(tb, NANOSECONDS_PER_SECOND, freq);
507 }
508
cpu_ppc_get_tb(ppc_tb_t * tb_env,uint64_t vmclk,int64_t tb_offset)509 uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset)
510 {
511 /* TB time in tb periods */
512 return ns_to_tb(tb_env->tb_freq, vmclk) + tb_offset;
513 }
514
cpu_ppc_load_tbl(CPUPPCState * env)515 uint64_t cpu_ppc_load_tbl (CPUPPCState *env)
516 {
517 ppc_tb_t *tb_env = env->tb_env;
518 uint64_t tb;
519
520 if (kvm_enabled()) {
521 return env->spr[SPR_TBL];
522 }
523
524 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
525 tb_env->tb_offset);
526 trace_ppc_tb_load(tb);
527
528 return tb;
529 }
530
_cpu_ppc_load_tbu(CPUPPCState * env)531 static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env)
532 {
533 ppc_tb_t *tb_env = env->tb_env;
534 uint64_t tb;
535
536 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
537 tb_env->tb_offset);
538 trace_ppc_tb_load(tb);
539
540 return tb >> 32;
541 }
542
cpu_ppc_load_tbu(CPUPPCState * env)543 uint32_t cpu_ppc_load_tbu (CPUPPCState *env)
544 {
545 if (kvm_enabled()) {
546 return env->spr[SPR_TBU];
547 }
548
549 return _cpu_ppc_load_tbu(env);
550 }
551
cpu_ppc_store_tb(ppc_tb_t * tb_env,uint64_t vmclk,int64_t * tb_offsetp,uint64_t value)552 static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk,
553 int64_t *tb_offsetp, uint64_t value)
554 {
555 *tb_offsetp = value - ns_to_tb(tb_env->tb_freq, vmclk);
556
557 trace_ppc_tb_store(value, *tb_offsetp);
558 }
559
cpu_ppc_store_tbl(CPUPPCState * env,uint32_t value)560 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value)
561 {
562 ppc_tb_t *tb_env = env->tb_env;
563 int64_t clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
564 uint64_t tb;
565
566 tb = cpu_ppc_get_tb(tb_env, clock, tb_env->tb_offset);
567 tb &= 0xFFFFFFFF00000000ULL;
568 cpu_ppc_store_tb(tb_env, clock, &tb_env->tb_offset, tb | (uint64_t)value);
569 }
570
_cpu_ppc_store_tbu(CPUPPCState * env,uint32_t value)571 static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value)
572 {
573 ppc_tb_t *tb_env = env->tb_env;
574 int64_t clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
575 uint64_t tb;
576
577 tb = cpu_ppc_get_tb(tb_env, clock, tb_env->tb_offset);
578 tb &= 0x00000000FFFFFFFFULL;
579 cpu_ppc_store_tb(tb_env, clock, &tb_env->tb_offset,
580 ((uint64_t)value << 32) | tb);
581 }
582
cpu_ppc_store_tbu(CPUPPCState * env,uint32_t value)583 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value)
584 {
585 _cpu_ppc_store_tbu(env, value);
586 }
587
cpu_ppc_load_atbl(CPUPPCState * env)588 uint64_t cpu_ppc_load_atbl (CPUPPCState *env)
589 {
590 ppc_tb_t *tb_env = env->tb_env;
591 uint64_t tb;
592
593 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
594 tb_env->atb_offset);
595 trace_ppc_tb_load(tb);
596
597 return tb;
598 }
599
cpu_ppc_load_atbu(CPUPPCState * env)600 uint32_t cpu_ppc_load_atbu (CPUPPCState *env)
601 {
602 ppc_tb_t *tb_env = env->tb_env;
603 uint64_t tb;
604
605 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
606 tb_env->atb_offset);
607 trace_ppc_tb_load(tb);
608
609 return tb >> 32;
610 }
611
cpu_ppc_store_atbl(CPUPPCState * env,uint32_t value)612 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value)
613 {
614 ppc_tb_t *tb_env = env->tb_env;
615 int64_t clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
616 uint64_t tb;
617
618 tb = cpu_ppc_get_tb(tb_env, clock, tb_env->atb_offset);
619 tb &= 0xFFFFFFFF00000000ULL;
620 cpu_ppc_store_tb(tb_env, clock, &tb_env->atb_offset, tb | (uint64_t)value);
621 }
622
cpu_ppc_store_atbu(CPUPPCState * env,uint32_t value)623 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value)
624 {
625 ppc_tb_t *tb_env = env->tb_env;
626 int64_t clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
627 uint64_t tb;
628
629 tb = cpu_ppc_get_tb(tb_env, clock, tb_env->atb_offset);
630 tb &= 0x00000000FFFFFFFFULL;
631 cpu_ppc_store_tb(tb_env, clock, &tb_env->atb_offset,
632 ((uint64_t)value << 32) | tb);
633 }
634
cpu_ppc_increase_tb_by_offset(CPUPPCState * env,int64_t offset)635 void cpu_ppc_increase_tb_by_offset(CPUPPCState *env, int64_t offset)
636 {
637 env->tb_env->tb_offset += offset;
638 }
639
cpu_ppc_decrease_tb_by_offset(CPUPPCState * env,int64_t offset)640 void cpu_ppc_decrease_tb_by_offset(CPUPPCState *env, int64_t offset)
641 {
642 env->tb_env->tb_offset -= offset;
643 }
644
cpu_ppc_load_vtb(CPUPPCState * env)645 uint64_t cpu_ppc_load_vtb(CPUPPCState *env)
646 {
647 ppc_tb_t *tb_env = env->tb_env;
648
649 return cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
650 tb_env->vtb_offset);
651 }
652
cpu_ppc_store_vtb(CPUPPCState * env,uint64_t value)653 void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value)
654 {
655 ppc_tb_t *tb_env = env->tb_env;
656
657 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
658 &tb_env->vtb_offset, value);
659 }
660
cpu_ppc_store_tbu40(CPUPPCState * env,uint64_t value)661 void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value)
662 {
663 ppc_tb_t *tb_env = env->tb_env;
664 int64_t clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
665 uint64_t tb;
666
667 tb = cpu_ppc_get_tb(tb_env, clock, tb_env->tb_offset);
668 tb &= 0xFFFFFFUL;
669 tb |= (value & ~0xFFFFFFUL);
670 cpu_ppc_store_tb(tb_env, clock, &tb_env->tb_offset, tb);
671 }
672
cpu_ppc_tb_stop(CPUPPCState * env)673 static void cpu_ppc_tb_stop (CPUPPCState *env)
674 {
675 ppc_tb_t *tb_env = env->tb_env;
676 uint64_t tb, atb, vmclk;
677
678 /* If the time base is already frozen, do nothing */
679 if (tb_env->tb_freq != 0) {
680 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
681 /* Get the time base */
682 tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset);
683 /* Get the alternate time base */
684 atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset);
685 /* Store the time base value (ie compute the current offset) */
686 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
687 /* Store the alternate time base value (compute the current offset) */
688 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
689 /* Set the time base frequency to zero */
690 tb_env->tb_freq = 0;
691 /* Now, the time bases are frozen to tb_offset / atb_offset value */
692 }
693 }
694
cpu_ppc_tb_start(CPUPPCState * env)695 static void cpu_ppc_tb_start (CPUPPCState *env)
696 {
697 ppc_tb_t *tb_env = env->tb_env;
698 uint64_t tb, atb, vmclk;
699
700 /* If the time base is not frozen, do nothing */
701 if (tb_env->tb_freq == 0) {
702 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
703 /* Get the time base from tb_offset */
704 tb = tb_env->tb_offset;
705 /* Get the alternate time base from atb_offset */
706 atb = tb_env->atb_offset;
707 /* Restore the tb frequency from the decrementer frequency */
708 tb_env->tb_freq = tb_env->decr_freq;
709 /* Store the time base value */
710 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
711 /* Store the alternate time base value */
712 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
713 }
714 }
715
ppc_decr_clear_on_delivery(CPUPPCState * env)716 bool ppc_decr_clear_on_delivery(CPUPPCState *env)
717 {
718 ppc_tb_t *tb_env = env->tb_env;
719 int flags = PPC_DECR_UNDERFLOW_TRIGGERED | PPC_DECR_UNDERFLOW_LEVEL;
720 return ((tb_env->flags & flags) == PPC_DECR_UNDERFLOW_TRIGGERED);
721 }
722
__cpu_ppc_load_decr(CPUPPCState * env,int64_t now,uint64_t next)723 static inline int64_t __cpu_ppc_load_decr(CPUPPCState *env, int64_t now,
724 uint64_t next)
725 {
726 ppc_tb_t *tb_env = env->tb_env;
727 uint64_t n;
728 int64_t decr;
729
730 n = ns_to_tb(tb_env->decr_freq, now);
731
732 /* BookE timers stop when reaching 0. */
733 if (next < n && tb_env->flags & PPC_TIMER_BOOKE) {
734 decr = 0;
735 } else {
736 decr = next - n;
737 }
738
739 trace_ppc_decr_load(decr);
740
741 return decr;
742 }
743
_cpu_ppc_load_decr(CPUPPCState * env,int64_t now)744 static target_ulong _cpu_ppc_load_decr(CPUPPCState *env, int64_t now)
745 {
746 ppc_tb_t *tb_env = env->tb_env;
747 uint64_t decr;
748
749 decr = __cpu_ppc_load_decr(env, now, tb_env->decr_next);
750
751 /*
752 * If large decrementer is enabled then the decrementer is signed extended
753 * to 64 bits, otherwise it is a 32 bit value.
754 */
755 if (env->spr[SPR_LPCR] & LPCR_LD) {
756 PowerPCCPU *cpu = env_archcpu(env);
757 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
758 return sextract64(decr, 0, pcc->lrg_decr_bits);
759 }
760 return (uint32_t) decr;
761 }
762
cpu_ppc_load_decr(CPUPPCState * env)763 target_ulong cpu_ppc_load_decr(CPUPPCState *env)
764 {
765 if (kvm_enabled()) {
766 return env->spr[SPR_DECR];
767 } else {
768 return _cpu_ppc_load_decr(env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
769 }
770 }
771
_cpu_ppc_load_hdecr(CPUPPCState * env,int64_t now)772 static target_ulong _cpu_ppc_load_hdecr(CPUPPCState *env, int64_t now)
773 {
774 PowerPCCPU *cpu = env_archcpu(env);
775 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
776 ppc_tb_t *tb_env = env->tb_env;
777 uint64_t hdecr;
778
779 hdecr = __cpu_ppc_load_decr(env, now, tb_env->hdecr_next);
780
781 /*
782 * If we have a large decrementer (POWER9 or later) then hdecr is sign
783 * extended to 64 bits, otherwise it is 32 bits.
784 */
785 if (pcc->lrg_decr_bits > 32) {
786 return sextract64(hdecr, 0, pcc->lrg_decr_bits);
787 }
788 return (uint32_t) hdecr;
789 }
790
cpu_ppc_load_hdecr(CPUPPCState * env)791 target_ulong cpu_ppc_load_hdecr(CPUPPCState *env)
792 {
793 return _cpu_ppc_load_hdecr(env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
794 }
795
cpu_ppc_load_purr(CPUPPCState * env)796 uint64_t cpu_ppc_load_purr (CPUPPCState *env)
797 {
798 ppc_tb_t *tb_env = env->tb_env;
799
800 return cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
801 tb_env->purr_offset);
802 }
803
804 /* When decrementer expires,
805 * all we need to do is generate or queue a CPU exception
806 */
cpu_ppc_decr_excp(PowerPCCPU * cpu)807 static inline void cpu_ppc_decr_excp(PowerPCCPU *cpu)
808 {
809 /* Raise it */
810 trace_ppc_decr_excp("raise");
811 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 1);
812 }
813
cpu_ppc_decr_lower(PowerPCCPU * cpu)814 static inline void cpu_ppc_decr_lower(PowerPCCPU *cpu)
815 {
816 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 0);
817 }
818
cpu_ppc_hdecr_excp(PowerPCCPU * cpu)819 static inline void cpu_ppc_hdecr_excp(PowerPCCPU *cpu)
820 {
821 CPUPPCState *env = &cpu->env;
822
823 /* Raise it */
824 trace_ppc_decr_excp("raise HV");
825
826 /* The architecture specifies that we don't deliver HDEC
827 * interrupts in a PM state. Not only they don't cause a
828 * wakeup but they also get effectively discarded.
829 */
830 if (!env->resume_as_sreset) {
831 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 1);
832 }
833 }
834
cpu_ppc_hdecr_lower(PowerPCCPU * cpu)835 static inline void cpu_ppc_hdecr_lower(PowerPCCPU *cpu)
836 {
837 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0);
838 }
839
__cpu_ppc_store_decr(PowerPCCPU * cpu,int64_t now,uint64_t * nextp,QEMUTimer * timer,void (* raise_excp)(void *),void (* lower_excp)(PowerPCCPU *),uint32_t flags,target_ulong decr,target_ulong value,int nr_bits)840 static void __cpu_ppc_store_decr(PowerPCCPU *cpu, int64_t now, uint64_t *nextp,
841 QEMUTimer *timer,
842 void (*raise_excp)(void *),
843 void (*lower_excp)(PowerPCCPU *),
844 uint32_t flags, target_ulong decr,
845 target_ulong value, int nr_bits)
846 {
847 CPUPPCState *env = &cpu->env;
848 ppc_tb_t *tb_env = env->tb_env;
849 uint64_t next;
850 int64_t signed_value;
851 int64_t signed_decr;
852
853 /* Truncate value to decr_width and sign extend for simplicity */
854 value = extract64(value, 0, nr_bits);
855 decr = extract64(decr, 0, nr_bits);
856 signed_value = sextract64(value, 0, nr_bits);
857 signed_decr = sextract64(decr, 0, nr_bits);
858
859 trace_ppc_decr_store(nr_bits, decr, value);
860
861 /*
862 * Calculate the next decrementer event and set a timer.
863 * decr_next is in timebase units to keep rounding simple. Note it is
864 * not adjusted by tb_offset because if TB changes via tb_offset changing,
865 * decrementer does not change, so not directly comparable with TB.
866 */
867 next = ns_to_tb(tb_env->decr_freq, now) + value;
868 *nextp = next; /* nextp is in timebase units */
869
870 /*
871 * Going from 1 -> 0 or 0 -> -1 is the event to generate a DEC interrupt.
872 *
873 * On MSB level based DEC implementations the MSB always means the interrupt
874 * is pending, so raise it on those.
875 *
876 * On MSB edge based DEC implementations the MSB going from 0 -> 1 triggers
877 * an edge interrupt, so raise it here too.
878 */
879 if (((flags & PPC_DECR_UNDERFLOW_LEVEL) && signed_value < 0) ||
880 ((flags & PPC_DECR_UNDERFLOW_TRIGGERED) && signed_value < 0
881 && signed_decr >= 0)) {
882 (*raise_excp)(cpu);
883 return;
884 }
885
886 /* On MSB level based systems a 0 for the MSB stops interrupt delivery */
887 if (signed_value >= 0 && (flags & PPC_DECR_UNDERFLOW_LEVEL)) {
888 (*lower_excp)(cpu);
889 }
890
891 /* Adjust timer */
892 timer_mod(timer, tb_to_ns_round_up(tb_env->decr_freq, next));
893 }
894
_cpu_ppc_store_decr(PowerPCCPU * cpu,int64_t now,target_ulong decr,target_ulong value,int nr_bits)895 static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, int64_t now,
896 target_ulong decr, target_ulong value,
897 int nr_bits)
898 {
899 ppc_tb_t *tb_env = cpu->env.tb_env;
900
901 __cpu_ppc_store_decr(cpu, now, &tb_env->decr_next, tb_env->decr_timer,
902 tb_env->decr_timer->cb, &cpu_ppc_decr_lower,
903 tb_env->flags, decr, value, nr_bits);
904 }
905
cpu_ppc_store_decr(CPUPPCState * env,target_ulong value)906 void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value)
907 {
908 PowerPCCPU *cpu = env_archcpu(env);
909 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
910 int64_t now;
911 target_ulong decr;
912 int nr_bits = 32;
913
914 if (kvm_enabled()) {
915 /* KVM handles decrementer exceptions, we don't need our own timer */
916 return;
917 }
918
919 if (env->spr[SPR_LPCR] & LPCR_LD) {
920 nr_bits = pcc->lrg_decr_bits;
921 }
922
923 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
924 decr = _cpu_ppc_load_decr(env, now);
925 _cpu_ppc_store_decr(cpu, now, decr, value, nr_bits);
926 }
927
cpu_ppc_decr_cb(void * opaque)928 static void cpu_ppc_decr_cb(void *opaque)
929 {
930 PowerPCCPU *cpu = opaque;
931
932 cpu_ppc_decr_excp(cpu);
933 }
934
_cpu_ppc_store_hdecr(PowerPCCPU * cpu,int64_t now,target_ulong hdecr,target_ulong value,int nr_bits)935 static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, int64_t now,
936 target_ulong hdecr, target_ulong value,
937 int nr_bits)
938 {
939 ppc_tb_t *tb_env = cpu->env.tb_env;
940
941 if (tb_env->hdecr_timer != NULL) {
942 /* HDECR (Book3S 64bit) is edge-based, not level like DECR */
943 __cpu_ppc_store_decr(cpu, now, &tb_env->hdecr_next, tb_env->hdecr_timer,
944 tb_env->hdecr_timer->cb, &cpu_ppc_hdecr_lower,
945 PPC_DECR_UNDERFLOW_TRIGGERED,
946 hdecr, value, nr_bits);
947 }
948 }
949
cpu_ppc_store_hdecr(CPUPPCState * env,target_ulong value)950 void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value)
951 {
952 PowerPCCPU *cpu = env_archcpu(env);
953 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
954 int64_t now;
955 target_ulong hdecr;
956
957 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
958 hdecr = _cpu_ppc_load_hdecr(env, now);
959 _cpu_ppc_store_hdecr(cpu, now, hdecr, value, pcc->lrg_decr_bits);
960 }
961
cpu_ppc_hdecr_cb(void * opaque)962 static void cpu_ppc_hdecr_cb(void *opaque)
963 {
964 PowerPCCPU *cpu = opaque;
965
966 cpu_ppc_hdecr_excp(cpu);
967 }
968
_cpu_ppc_store_purr(CPUPPCState * env,int64_t now,uint64_t value)969 static void _cpu_ppc_store_purr(CPUPPCState *env, int64_t now, uint64_t value)
970 {
971 ppc_tb_t *tb_env = env->tb_env;
972
973 cpu_ppc_store_tb(tb_env, now, &tb_env->purr_offset, value);
974 }
975
cpu_ppc_store_purr(CPUPPCState * env,uint64_t value)976 void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value)
977 {
978 _cpu_ppc_store_purr(env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), value);
979 }
980
timebase_save(PPCTimebase * tb)981 static void timebase_save(PPCTimebase *tb)
982 {
983 uint64_t ticks = cpu_get_host_ticks();
984 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
985
986 if (!first_ppc_cpu->env.tb_env) {
987 error_report("No timebase object");
988 return;
989 }
990
991 if (replay_mode == REPLAY_MODE_NONE) {
992 /* not used anymore, we keep it for compatibility */
993 tb->time_of_the_day_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST);
994 } else {
995 /* simpler for record-replay to avoid this event, compat not needed */
996 tb->time_of_the_day_ns = 0;
997 }
998
999 /*
1000 * tb_offset is only expected to be changed by QEMU so
1001 * there is no need to update it from KVM here
1002 */
1003 tb->guest_timebase = ticks + first_ppc_cpu->env.tb_env->tb_offset;
1004
1005 tb->runstate_paused =
1006 runstate_check(RUN_STATE_PAUSED) || runstate_check(RUN_STATE_SAVE_VM);
1007 }
1008
timebase_load(PPCTimebase * tb)1009 static void timebase_load(PPCTimebase *tb)
1010 {
1011 CPUState *cpu;
1012 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
1013 int64_t tb_off_adj, tb_off;
1014 unsigned long freq;
1015
1016 if (!first_ppc_cpu->env.tb_env) {
1017 error_report("No timebase object");
1018 return;
1019 }
1020
1021 freq = first_ppc_cpu->env.tb_env->tb_freq;
1022
1023 tb_off_adj = tb->guest_timebase - cpu_get_host_ticks();
1024
1025 tb_off = first_ppc_cpu->env.tb_env->tb_offset;
1026 trace_ppc_tb_adjust(tb_off, tb_off_adj, tb_off_adj - tb_off,
1027 (tb_off_adj - tb_off) / freq);
1028
1029 /* Set new offset to all CPUs */
1030 CPU_FOREACH(cpu) {
1031 PowerPCCPU *pcpu = POWERPC_CPU(cpu);
1032 pcpu->env.tb_env->tb_offset = tb_off_adj;
1033 kvmppc_set_reg_tb_offset(pcpu, pcpu->env.tb_env->tb_offset);
1034 }
1035 }
1036
cpu_ppc_clock_vm_state_change(void * opaque,bool running,RunState state)1037 void cpu_ppc_clock_vm_state_change(void *opaque, bool running,
1038 RunState state)
1039 {
1040 PPCTimebase *tb = opaque;
1041
1042 if (running) {
1043 timebase_load(tb);
1044 } else {
1045 timebase_save(tb);
1046 }
1047 }
1048
1049 /*
1050 * When migrating a running guest, read the clock just
1051 * before migration, so that the guest clock counts
1052 * during the events between:
1053 *
1054 * * vm_stop()
1055 * *
1056 * * pre_save()
1057 *
1058 * This reduces clock difference on migration from 5s
1059 * to 0.1s (when max_downtime == 5s), because sending the
1060 * final pages of memory (which happens between vm_stop()
1061 * and pre_save()) takes max_downtime.
1062 */
timebase_pre_save(void * opaque)1063 static int timebase_pre_save(void *opaque)
1064 {
1065 PPCTimebase *tb = opaque;
1066
1067 /* guest_timebase won't be overridden in case of paused guest or savevm */
1068 if (!tb->runstate_paused) {
1069 timebase_save(tb);
1070 }
1071
1072 return 0;
1073 }
1074
1075 const VMStateDescription vmstate_ppc_timebase = {
1076 .name = "timebase",
1077 .version_id = 1,
1078 .minimum_version_id = 1,
1079 .pre_save = timebase_pre_save,
1080 .fields = (const VMStateField []) {
1081 VMSTATE_UINT64(guest_timebase, PPCTimebase),
1082 VMSTATE_INT64(time_of_the_day_ns, PPCTimebase),
1083 VMSTATE_END_OF_LIST()
1084 },
1085 };
1086
1087 /* Set up (once) timebase frequency (in Hz) */
cpu_ppc_tb_init(CPUPPCState * env,uint32_t freq)1088 void cpu_ppc_tb_init(CPUPPCState *env, uint32_t freq)
1089 {
1090 PowerPCCPU *cpu = env_archcpu(env);
1091 ppc_tb_t *tb_env;
1092
1093 tb_env = g_new0(ppc_tb_t, 1);
1094 env->tb_env = tb_env;
1095 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
1096 if (is_book3s_arch2x(env)) {
1097 /* All Book3S 64bit CPUs implement level based DEC logic */
1098 tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL;
1099 }
1100 /* Create new timer */
1101 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
1102 &cpu_ppc_decr_cb, cpu);
1103 if (env->has_hv_mode && !cpu->vhyp) {
1104 tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
1105 &cpu_ppc_hdecr_cb, cpu);
1106 } else {
1107 tb_env->hdecr_timer = NULL;
1108 }
1109
1110 tb_env->tb_freq = freq;
1111 tb_env->decr_freq = freq;
1112 }
1113
cpu_ppc_tb_reset(CPUPPCState * env)1114 void cpu_ppc_tb_reset(CPUPPCState *env)
1115 {
1116 PowerPCCPU *cpu = env_archcpu(env);
1117 ppc_tb_t *tb_env = env->tb_env;
1118
1119 timer_del(tb_env->decr_timer);
1120 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 0);
1121 tb_env->decr_next = 0;
1122 if (tb_env->hdecr_timer != NULL) {
1123 timer_del(tb_env->hdecr_timer);
1124 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0);
1125 tb_env->hdecr_next = 0;
1126 }
1127
1128 /*
1129 * There is a bug in Linux 2.4 kernels:
1130 * if a decrementer exception is pending when it enables msr_ee at startup,
1131 * it's not ready to handle it...
1132 */
1133 cpu_ppc_store_decr(env, -1);
1134 cpu_ppc_store_hdecr(env, -1);
1135 cpu_ppc_store_purr(env, 0x0000000000000000ULL);
1136 }
1137
cpu_ppc_tb_free(CPUPPCState * env)1138 void cpu_ppc_tb_free(CPUPPCState *env)
1139 {
1140 timer_free(env->tb_env->decr_timer);
1141 timer_free(env->tb_env->hdecr_timer);
1142 g_free(env->tb_env);
1143 }
1144
1145 /* cpu_ppc_hdecr_init may be used if the timer is not used by HDEC emulation */
cpu_ppc_hdecr_init(CPUPPCState * env)1146 void cpu_ppc_hdecr_init(CPUPPCState *env)
1147 {
1148 PowerPCCPU *cpu = env_archcpu(env);
1149
1150 assert(env->tb_env->hdecr_timer == NULL);
1151
1152 env->tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
1153 &cpu_ppc_hdecr_cb, cpu);
1154 }
1155
cpu_ppc_hdecr_exit(CPUPPCState * env)1156 void cpu_ppc_hdecr_exit(CPUPPCState *env)
1157 {
1158 PowerPCCPU *cpu = env_archcpu(env);
1159
1160 timer_free(env->tb_env->hdecr_timer);
1161 env->tb_env->hdecr_timer = NULL;
1162
1163 cpu_ppc_hdecr_lower(cpu);
1164 }
1165
1166 /*****************************************************************************/
1167 /* PowerPC 40x timers */
1168
1169 /* PIT, FIT & WDT */
1170 typedef struct ppc40x_timer_t ppc40x_timer_t;
1171 struct ppc40x_timer_t {
1172 uint64_t pit_reload; /* PIT auto-reload value */
1173 uint64_t fit_next; /* Tick for next FIT interrupt */
1174 QEMUTimer *fit_timer;
1175 uint64_t wdt_next; /* Tick for next WDT interrupt */
1176 QEMUTimer *wdt_timer;
1177
1178 /* 405 have the PIT, 440 have a DECR. */
1179 unsigned int decr_excp;
1180 };
1181
1182 /* Fixed interval timer */
cpu_4xx_fit_cb(void * opaque)1183 static void cpu_4xx_fit_cb (void *opaque)
1184 {
1185 PowerPCCPU *cpu = opaque;
1186 CPUPPCState *env = &cpu->env;
1187 ppc_tb_t *tb_env;
1188 ppc40x_timer_t *ppc40x_timer;
1189 uint64_t now, next;
1190
1191 tb_env = env->tb_env;
1192 ppc40x_timer = tb_env->opaque;
1193 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1194 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
1195 case 0:
1196 next = 1 << 9;
1197 break;
1198 case 1:
1199 next = 1 << 13;
1200 break;
1201 case 2:
1202 next = 1 << 17;
1203 break;
1204 case 3:
1205 next = 1 << 21;
1206 break;
1207 default:
1208 /* Cannot occur, but makes gcc happy */
1209 return;
1210 }
1211 next = now + tb_to_ns_round_up(tb_env->tb_freq, next);
1212 timer_mod(ppc40x_timer->fit_timer, next);
1213 env->spr[SPR_40x_TSR] |= 1 << 26;
1214 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) {
1215 ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1);
1216 }
1217 trace_ppc4xx_fit((int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
1218 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
1219 }
1220
1221 /* Programmable interval timer */
start_stop_pit(CPUPPCState * env,ppc_tb_t * tb_env,int is_excp)1222 static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp)
1223 {
1224 ppc40x_timer_t *ppc40x_timer;
1225 uint64_t now, next;
1226
1227 ppc40x_timer = tb_env->opaque;
1228 if (ppc40x_timer->pit_reload <= 1 ||
1229 !((env->spr[SPR_40x_TCR] >> 26) & 0x1) ||
1230 (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {
1231 /* Stop PIT */
1232 trace_ppc4xx_pit_stop();
1233 timer_del(tb_env->decr_timer);
1234 } else {
1235 trace_ppc4xx_pit_start(ppc40x_timer->pit_reload);
1236 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1237
1238 if (is_excp) {
1239 tb_env->decr_next += ppc40x_timer->pit_reload;
1240 } else {
1241 tb_env->decr_next = ns_to_tb(tb_env->decr_freq, now)
1242 + ppc40x_timer->pit_reload;
1243 }
1244 next = tb_to_ns_round_up(tb_env->decr_freq, tb_env->decr_next);
1245 timer_mod(tb_env->decr_timer, next);
1246 }
1247 }
1248
cpu_4xx_pit_cb(void * opaque)1249 static void cpu_4xx_pit_cb (void *opaque)
1250 {
1251 PowerPCCPU *cpu = opaque;
1252 CPUPPCState *env = &cpu->env;
1253 ppc_tb_t *tb_env;
1254 ppc40x_timer_t *ppc40x_timer;
1255
1256 tb_env = env->tb_env;
1257 ppc40x_timer = tb_env->opaque;
1258 env->spr[SPR_40x_TSR] |= 1 << 27;
1259 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) {
1260 ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1);
1261 }
1262 start_stop_pit(env, tb_env, 1);
1263 trace_ppc4xx_pit((int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
1264 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
1265 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
1266 ppc40x_timer->pit_reload);
1267 }
1268
1269 /* Watchdog timer */
cpu_4xx_wdt_cb(void * opaque)1270 static void cpu_4xx_wdt_cb (void *opaque)
1271 {
1272 PowerPCCPU *cpu = opaque;
1273 CPUPPCState *env = &cpu->env;
1274 ppc_tb_t *tb_env;
1275 ppc40x_timer_t *ppc40x_timer;
1276 uint64_t now, next;
1277
1278 tb_env = env->tb_env;
1279 ppc40x_timer = tb_env->opaque;
1280 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1281 switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
1282 case 0:
1283 next = 1 << 17;
1284 break;
1285 case 1:
1286 next = 1 << 21;
1287 break;
1288 case 2:
1289 next = 1 << 25;
1290 break;
1291 case 3:
1292 next = 1 << 29;
1293 break;
1294 default:
1295 /* Cannot occur, but makes gcc happy */
1296 return;
1297 }
1298 next = now + tb_to_ns_round_up(tb_env->decr_freq, next);
1299 trace_ppc4xx_wdt(env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
1300 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
1301 case 0x0:
1302 case 0x1:
1303 timer_mod(ppc40x_timer->wdt_timer, next);
1304 ppc40x_timer->wdt_next = next;
1305 env->spr[SPR_40x_TSR] |= 1U << 31;
1306 break;
1307 case 0x2:
1308 timer_mod(ppc40x_timer->wdt_timer, next);
1309 ppc40x_timer->wdt_next = next;
1310 env->spr[SPR_40x_TSR] |= 1 << 30;
1311 if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) {
1312 ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1);
1313 }
1314 break;
1315 case 0x3:
1316 env->spr[SPR_40x_TSR] &= ~0x30000000;
1317 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
1318 switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) {
1319 case 0x0:
1320 /* No reset */
1321 break;
1322 case 0x1: /* Core reset */
1323 ppc40x_core_reset(cpu);
1324 break;
1325 case 0x2: /* Chip reset */
1326 ppc40x_chip_reset(cpu);
1327 break;
1328 case 0x3: /* System reset */
1329 ppc40x_system_reset(cpu);
1330 break;
1331 }
1332 }
1333 }
1334
store_40x_pit(CPUPPCState * env,target_ulong val)1335 void store_40x_pit (CPUPPCState *env, target_ulong val)
1336 {
1337 ppc_tb_t *tb_env;
1338 ppc40x_timer_t *ppc40x_timer;
1339
1340 tb_env = env->tb_env;
1341 ppc40x_timer = tb_env->opaque;
1342 trace_ppc40x_store_pit(val);
1343 ppc40x_timer->pit_reload = val;
1344 start_stop_pit(env, tb_env, 0);
1345 }
1346
load_40x_pit(CPUPPCState * env)1347 target_ulong load_40x_pit (CPUPPCState *env)
1348 {
1349 return cpu_ppc_load_decr(env);
1350 }
1351
store_40x_tsr(CPUPPCState * env,target_ulong val)1352 void store_40x_tsr(CPUPPCState *env, target_ulong val)
1353 {
1354 PowerPCCPU *cpu = env_archcpu(env);
1355
1356 trace_ppc40x_store_tcr(val);
1357
1358 env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
1359 if (val & 0x80000000) {
1360 ppc_set_irq(cpu, PPC_INTERRUPT_PIT, 0);
1361 }
1362 }
1363
store_40x_tcr(CPUPPCState * env,target_ulong val)1364 void store_40x_tcr(CPUPPCState *env, target_ulong val)
1365 {
1366 PowerPCCPU *cpu = env_archcpu(env);
1367 ppc_tb_t *tb_env;
1368
1369 trace_ppc40x_store_tsr(val);
1370
1371 tb_env = env->tb_env;
1372 env->spr[SPR_40x_TCR] = val & 0xFFC00000;
1373 start_stop_pit(env, tb_env, 1);
1374 cpu_4xx_wdt_cb(cpu);
1375 }
1376
ppc_40x_set_tb_clk(void * opaque,uint32_t freq)1377 static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq)
1378 {
1379 CPUPPCState *env = opaque;
1380 ppc_tb_t *tb_env = env->tb_env;
1381
1382 trace_ppc40x_set_tb_clk(freq);
1383 tb_env->tb_freq = freq;
1384 tb_env->decr_freq = freq;
1385 /* XXX: we should also update all timers */
1386 }
1387
ppc_40x_timers_init(CPUPPCState * env,uint32_t freq,unsigned int decr_excp)1388 clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
1389 unsigned int decr_excp)
1390 {
1391 ppc_tb_t *tb_env;
1392 ppc40x_timer_t *ppc40x_timer;
1393 PowerPCCPU *cpu = env_archcpu(env);
1394
1395 trace_ppc40x_timers_init(freq);
1396
1397 tb_env = g_new0(ppc_tb_t, 1);
1398 ppc40x_timer = g_new0(ppc40x_timer_t, 1);
1399
1400 env->tb_env = tb_env;
1401 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
1402 tb_env->tb_freq = freq;
1403 tb_env->decr_freq = freq;
1404 tb_env->opaque = ppc40x_timer;
1405
1406 /* We use decr timer for PIT */
1407 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_pit_cb, cpu);
1408 ppc40x_timer->fit_timer =
1409 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_fit_cb, cpu);
1410 ppc40x_timer->wdt_timer =
1411 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_wdt_cb, cpu);
1412 ppc40x_timer->decr_excp = decr_excp;
1413
1414 return &ppc_40x_set_tb_clk;
1415 }
1416
1417 /*****************************************************************************/
1418 /* Embedded PowerPC Device Control Registers */
1419 typedef struct ppc_dcrn_t ppc_dcrn_t;
1420 struct ppc_dcrn_t {
1421 dcr_read_cb dcr_read;
1422 dcr_write_cb dcr_write;
1423 void *opaque;
1424 };
1425
1426 /* XXX: on 460, DCR addresses are 32 bits wide,
1427 * using DCRIPR to get the 22 upper bits of the DCR address
1428 */
1429 #define DCRN_NB 1024
1430 struct ppc_dcr_t {
1431 ppc_dcrn_t dcrn[DCRN_NB];
1432 int (*read_error)(int dcrn);
1433 int (*write_error)(int dcrn);
1434 };
1435
ppc_dcr_read(ppc_dcr_t * dcr_env,int dcrn,uint32_t * valp)1436 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1437 {
1438 ppc_dcrn_t *dcr;
1439
1440 if (dcrn < 0 || dcrn >= DCRN_NB)
1441 goto error;
1442 dcr = &dcr_env->dcrn[dcrn];
1443 if (dcr->dcr_read == NULL)
1444 goto error;
1445 *valp = (*dcr->dcr_read)(dcr->opaque, dcrn);
1446 trace_ppc_dcr_read(dcrn, *valp);
1447
1448 return 0;
1449
1450 error:
1451 if (dcr_env->read_error != NULL)
1452 return (*dcr_env->read_error)(dcrn);
1453
1454 return -1;
1455 }
1456
ppc_dcr_write(ppc_dcr_t * dcr_env,int dcrn,uint32_t val)1457 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1458 {
1459 ppc_dcrn_t *dcr;
1460
1461 if (dcrn < 0 || dcrn >= DCRN_NB)
1462 goto error;
1463 dcr = &dcr_env->dcrn[dcrn];
1464 if (dcr->dcr_write == NULL)
1465 goto error;
1466 trace_ppc_dcr_write(dcrn, val);
1467 (*dcr->dcr_write)(dcr->opaque, dcrn, val);
1468
1469 return 0;
1470
1471 error:
1472 if (dcr_env->write_error != NULL)
1473 return (*dcr_env->write_error)(dcrn);
1474
1475 return -1;
1476 }
1477
ppc_dcr_register(CPUPPCState * env,int dcrn,void * opaque,dcr_read_cb dcr_read,dcr_write_cb dcr_write)1478 int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
1479 dcr_read_cb dcr_read, dcr_write_cb dcr_write)
1480 {
1481 ppc_dcr_t *dcr_env;
1482 ppc_dcrn_t *dcr;
1483
1484 dcr_env = env->dcr_env;
1485 if (dcr_env == NULL)
1486 return -1;
1487 if (dcrn < 0 || dcrn >= DCRN_NB)
1488 return -1;
1489 dcr = &dcr_env->dcrn[dcrn];
1490 if (dcr->opaque != NULL ||
1491 dcr->dcr_read != NULL ||
1492 dcr->dcr_write != NULL)
1493 return -1;
1494 dcr->opaque = opaque;
1495 dcr->dcr_read = dcr_read;
1496 dcr->dcr_write = dcr_write;
1497
1498 return 0;
1499 }
1500
ppc_dcr_init(CPUPPCState * env,int (* read_error)(int dcrn),int (* write_error)(int dcrn))1501 int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn),
1502 int (*write_error)(int dcrn))
1503 {
1504 ppc_dcr_t *dcr_env;
1505
1506 dcr_env = g_new0(ppc_dcr_t, 1);
1507 dcr_env->read_error = read_error;
1508 dcr_env->write_error = write_error;
1509 env->dcr_env = dcr_env;
1510
1511 return 0;
1512 }
1513
1514 /*****************************************************************************/
1515
ppc_cpu_pir(PowerPCCPU * cpu)1516 int ppc_cpu_pir(PowerPCCPU *cpu)
1517 {
1518 CPUPPCState *env = &cpu->env;
1519 return env->spr_cb[SPR_PIR].default_value;
1520 }
1521
ppc_cpu_tir(PowerPCCPU * cpu)1522 int ppc_cpu_tir(PowerPCCPU *cpu)
1523 {
1524 CPUPPCState *env = &cpu->env;
1525 return env->spr_cb[SPR_TIR].default_value;
1526 }
1527
ppc_get_vcpu_by_pir(int pir)1528 PowerPCCPU *ppc_get_vcpu_by_pir(int pir)
1529 {
1530 CPUState *cs;
1531
1532 CPU_FOREACH(cs) {
1533 PowerPCCPU *cpu = POWERPC_CPU(cs);
1534
1535 if (ppc_cpu_pir(cpu) == pir) {
1536 return cpu;
1537 }
1538 }
1539
1540 return NULL;
1541 }
1542
ppc_irq_reset(PowerPCCPU * cpu)1543 void ppc_irq_reset(PowerPCCPU *cpu)
1544 {
1545 CPUPPCState *env = &cpu->env;
1546
1547 env->irq_input_state = 0;
1548 if (kvm_enabled()) {
1549 kvmppc_set_interrupt(cpu, PPC_INTERRUPT_EXT, 0);
1550 }
1551 }
1552