1
2 /*
3 * PowerPC CPU initialization for qemu.
4 *
5 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Copyright 2011 Freescale Semiconductor, Inc.
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include "qemu/osdep.h"
23 #include "disas/dis-asm.h"
24 #include "gdbstub/helpers.h"
25 #include "sysemu/cpus.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/tcg.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qemu/module.h"
33 #include "qemu/qemu-print.h"
34 #include "qapi/error.h"
35 #include "qapi/qmp/qnull.h"
36 #include "qapi/visitor.h"
37 #include "hw/qdev-properties.h"
38 #include "hw/ppc/ppc.h"
39 #include "mmu-book3s-v3.h"
40 #include "qemu/cutils.h"
41 #include "disas/capstone.h"
42 #include "fpu/softfloat.h"
43
44 #include "helper_regs.h"
45 #include "internal.h"
46 #include "spr_common.h"
47 #include "power8-pmu.h"
48
49 #ifndef CONFIG_USER_ONLY
50 #include "hw/boards.h"
51 #include "hw/intc/intc.h"
52 #include "kvm_ppc.h"
53 #endif
54
55 #include "cpu_init.h"
56 /* #define PPC_DEBUG_SPR */
57 /* #define USE_APPLE_GDB */
58
vscr_init(CPUPPCState * env,uint32_t val)59 static inline void vscr_init(CPUPPCState *env, uint32_t val)
60 {
61 /* Altivec always uses round-to-nearest */
62 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
63 ppc_store_vscr(env, val);
64 }
65
register_745_sprs(CPUPPCState * env)66 static void register_745_sprs(CPUPPCState *env)
67 {
68 /* SGPRs */
69 spr_register(env, SPR_SPRG4, "SPRG4",
70 SPR_NOACCESS, SPR_NOACCESS,
71 &spr_read_generic, &spr_write_generic,
72 0x00000000);
73 spr_register(env, SPR_SPRG5, "SPRG5",
74 SPR_NOACCESS, SPR_NOACCESS,
75 &spr_read_generic, &spr_write_generic,
76 0x00000000);
77 spr_register(env, SPR_SPRG6, "SPRG6",
78 SPR_NOACCESS, SPR_NOACCESS,
79 &spr_read_generic, &spr_write_generic,
80 0x00000000);
81 spr_register(env, SPR_SPRG7, "SPRG7",
82 SPR_NOACCESS, SPR_NOACCESS,
83 &spr_read_generic, &spr_write_generic,
84 0x00000000);
85
86 /* Hardware implementation registers */
87 spr_register(env, SPR_HID0, "HID0",
88 SPR_NOACCESS, SPR_NOACCESS,
89 &spr_read_generic, &spr_write_generic,
90 0x00000000);
91
92 spr_register(env, SPR_HID1, "HID1",
93 SPR_NOACCESS, SPR_NOACCESS,
94 &spr_read_generic, &spr_write_generic,
95 0x00000000);
96
97 spr_register(env, SPR_HID2, "HID2",
98 SPR_NOACCESS, SPR_NOACCESS,
99 &spr_read_generic, &spr_write_generic,
100 0x00000000);
101 }
102
register_755_sprs(CPUPPCState * env)103 static void register_755_sprs(CPUPPCState *env)
104 {
105 /* L2 cache control */
106 spr_register(env, SPR_L2CR, "L2CR",
107 SPR_NOACCESS, SPR_NOACCESS,
108 &spr_read_generic, spr_access_nop,
109 0x00000000);
110
111 spr_register(env, SPR_L2PMCR, "L2PMCR",
112 SPR_NOACCESS, SPR_NOACCESS,
113 &spr_read_generic, &spr_write_generic,
114 0x00000000);
115 }
116
117 /* SPR common to all 7xx PowerPC implementations */
register_7xx_sprs(CPUPPCState * env)118 static void register_7xx_sprs(CPUPPCState *env)
119 {
120 /* Breakpoints */
121 spr_register_kvm(env, SPR_DABR, "DABR",
122 SPR_NOACCESS, SPR_NOACCESS,
123 &spr_read_generic, &spr_write_generic,
124 KVM_REG_PPC_DABR, 0x00000000);
125
126 spr_register(env, SPR_IABR, "IABR",
127 SPR_NOACCESS, SPR_NOACCESS,
128 &spr_read_generic, &spr_write_generic,
129 0x00000000);
130 /* Cache management */
131 spr_register(env, SPR_ICTC, "ICTC",
132 SPR_NOACCESS, SPR_NOACCESS,
133 &spr_read_generic, &spr_write_generic,
134 0x00000000);
135 /* Performance monitors */
136 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
137 SPR_NOACCESS, SPR_NOACCESS,
138 &spr_read_generic, &spr_write_generic,
139 0x00000000);
140
141 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
142 SPR_NOACCESS, SPR_NOACCESS,
143 &spr_read_generic, &spr_write_generic,
144 0x00000000);
145
146 spr_register(env, SPR_7XX_PMC1, "PMC1",
147 SPR_NOACCESS, SPR_NOACCESS,
148 &spr_read_generic, &spr_write_generic,
149 0x00000000);
150
151 spr_register(env, SPR_7XX_PMC2, "PMC2",
152 SPR_NOACCESS, SPR_NOACCESS,
153 &spr_read_generic, &spr_write_generic,
154 0x00000000);
155
156 spr_register(env, SPR_7XX_PMC3, "PMC3",
157 SPR_NOACCESS, SPR_NOACCESS,
158 &spr_read_generic, &spr_write_generic,
159 0x00000000);
160
161 spr_register(env, SPR_7XX_PMC4, "PMC4",
162 SPR_NOACCESS, SPR_NOACCESS,
163 &spr_read_generic, &spr_write_generic,
164 0x00000000);
165
166 spr_register(env, SPR_7XX_SIAR, "SIAR",
167 SPR_NOACCESS, SPR_NOACCESS,
168 &spr_read_generic, SPR_NOACCESS,
169 0x00000000);
170
171 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
172 &spr_read_ureg, SPR_NOACCESS,
173 &spr_read_ureg, SPR_NOACCESS,
174 0x00000000);
175
176 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
177 &spr_read_ureg, SPR_NOACCESS,
178 &spr_read_ureg, SPR_NOACCESS,
179 0x00000000);
180
181 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
182 &spr_read_ureg, SPR_NOACCESS,
183 &spr_read_ureg, SPR_NOACCESS,
184 0x00000000);
185
186 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
187 &spr_read_ureg, SPR_NOACCESS,
188 &spr_read_ureg, SPR_NOACCESS,
189 0x00000000);
190
191 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
192 &spr_read_ureg, SPR_NOACCESS,
193 &spr_read_ureg, SPR_NOACCESS,
194 0x00000000);
195
196 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
197 &spr_read_ureg, SPR_NOACCESS,
198 &spr_read_ureg, SPR_NOACCESS,
199 0x00000000);
200
201 spr_register(env, SPR_7XX_USIAR, "USIAR",
202 &spr_read_ureg, SPR_NOACCESS,
203 &spr_read_ureg, SPR_NOACCESS,
204 0x00000000);
205 /* External access control */
206 spr_register(env, SPR_EAR, "EAR",
207 SPR_NOACCESS, SPR_NOACCESS,
208 &spr_read_generic, &spr_write_generic,
209 0x00000000);
210
211 /* Hardware implementation registers */
212 spr_register(env, SPR_HID0, "HID0",
213 SPR_NOACCESS, SPR_NOACCESS,
214 &spr_read_generic, &spr_write_generic,
215 0x00000000);
216
217 spr_register(env, SPR_HID1, "HID1",
218 SPR_NOACCESS, SPR_NOACCESS,
219 &spr_read_generic, &spr_write_generic,
220 0x00000000);
221 }
222
223 #ifdef TARGET_PPC64
register_amr_sprs(CPUPPCState * env)224 static void register_amr_sprs(CPUPPCState *env)
225 {
226 #ifndef CONFIG_USER_ONLY
227 /*
228 * Virtual Page Class Key protection
229 *
230 * The AMR is accessible either via SPR 13 or SPR 29. 13 is
231 * userspace accessible, 29 is privileged. So we only need to set
232 * the kvm ONE_REG id on one of them, we use 29
233 */
234 spr_register(env, SPR_UAMR, "UAMR",
235 &spr_read_generic, &spr_write_amr,
236 &spr_read_generic, &spr_write_amr,
237 0);
238 spr_register_kvm_hv(env, SPR_AMR, "AMR",
239 SPR_NOACCESS, SPR_NOACCESS,
240 &spr_read_generic, &spr_write_amr,
241 &spr_read_generic, &spr_write_generic,
242 KVM_REG_PPC_AMR, 0);
243 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
244 SPR_NOACCESS, SPR_NOACCESS,
245 &spr_read_generic, &spr_write_uamor,
246 &spr_read_generic, &spr_write_generic,
247 KVM_REG_PPC_UAMOR, 0);
248 spr_register_hv(env, SPR_AMOR, "AMOR",
249 SPR_NOACCESS, SPR_NOACCESS,
250 SPR_NOACCESS, SPR_NOACCESS,
251 &spr_read_generic, &spr_core_lpar_write_generic,
252 0);
253 #endif /* !CONFIG_USER_ONLY */
254 }
255
register_iamr_sprs(CPUPPCState * env)256 static void register_iamr_sprs(CPUPPCState *env)
257 {
258 #ifndef CONFIG_USER_ONLY
259 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
260 SPR_NOACCESS, SPR_NOACCESS,
261 &spr_read_generic, &spr_write_iamr,
262 &spr_read_generic, &spr_write_generic,
263 KVM_REG_PPC_IAMR, 0);
264 #endif /* !CONFIG_USER_ONLY */
265 }
266 #endif /* TARGET_PPC64 */
267
268 /* SPR specific to PowerPC 604 implementation */
register_604_sprs(CPUPPCState * env)269 static void register_604_sprs(CPUPPCState *env)
270 {
271 /* Processor identification */
272 spr_register(env, SPR_PIR, "PIR",
273 SPR_NOACCESS, SPR_NOACCESS,
274 &spr_read_generic, &spr_write_pir,
275 0x00000000);
276 /* Breakpoints */
277 spr_register(env, SPR_IABR, "IABR",
278 SPR_NOACCESS, SPR_NOACCESS,
279 &spr_read_generic, &spr_write_generic,
280 0x00000000);
281
282 spr_register_kvm(env, SPR_DABR, "DABR",
283 SPR_NOACCESS, SPR_NOACCESS,
284 &spr_read_generic, &spr_write_generic,
285 KVM_REG_PPC_DABR, 0x00000000);
286 /* Performance counters */
287 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
288 SPR_NOACCESS, SPR_NOACCESS,
289 &spr_read_generic, &spr_write_generic,
290 0x00000000);
291
292 spr_register(env, SPR_7XX_PMC1, "PMC1",
293 SPR_NOACCESS, SPR_NOACCESS,
294 &spr_read_generic, &spr_write_generic,
295 0x00000000);
296
297 spr_register(env, SPR_7XX_PMC2, "PMC2",
298 SPR_NOACCESS, SPR_NOACCESS,
299 &spr_read_generic, &spr_write_generic,
300 0x00000000);
301
302 spr_register(env, SPR_7XX_SIAR, "SIAR",
303 SPR_NOACCESS, SPR_NOACCESS,
304 &spr_read_generic, SPR_NOACCESS,
305 0x00000000);
306
307 spr_register(env, SPR_SDA, "SDA",
308 SPR_NOACCESS, SPR_NOACCESS,
309 &spr_read_generic, SPR_NOACCESS,
310 0x00000000);
311 /* External access control */
312 spr_register(env, SPR_EAR, "EAR",
313 SPR_NOACCESS, SPR_NOACCESS,
314 &spr_read_generic, &spr_write_generic,
315 0x00000000);
316
317 /* Hardware implementation registers */
318 spr_register(env, SPR_HID0, "HID0",
319 SPR_NOACCESS, SPR_NOACCESS,
320 &spr_read_generic, &spr_write_generic,
321 0x00000000);
322 }
323
register_604e_sprs(CPUPPCState * env)324 static void register_604e_sprs(CPUPPCState *env)
325 {
326 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
327 SPR_NOACCESS, SPR_NOACCESS,
328 &spr_read_generic, &spr_write_generic,
329 0x00000000);
330
331 spr_register(env, SPR_7XX_PMC3, "PMC3",
332 SPR_NOACCESS, SPR_NOACCESS,
333 &spr_read_generic, &spr_write_generic,
334 0x00000000);
335
336 spr_register(env, SPR_7XX_PMC4, "PMC4",
337 SPR_NOACCESS, SPR_NOACCESS,
338 &spr_read_generic, &spr_write_generic,
339 0x00000000);
340 /* Hardware implementation registers */
341 spr_register(env, SPR_HID1, "HID1",
342 SPR_NOACCESS, SPR_NOACCESS,
343 &spr_read_generic, &spr_write_generic,
344 0x00000000);
345 }
346
347 /* SPR specific to PowerPC 603 implementation */
register_603_sprs(CPUPPCState * env)348 static void register_603_sprs(CPUPPCState *env)
349 {
350 /* External access control */
351 spr_register(env, SPR_EAR, "EAR",
352 SPR_NOACCESS, SPR_NOACCESS,
353 &spr_read_generic, &spr_write_generic,
354 0x00000000);
355 /* Breakpoints */
356 spr_register(env, SPR_IABR, "IABR",
357 SPR_NOACCESS, SPR_NOACCESS,
358 &spr_read_generic, &spr_write_generic,
359 0x00000000);
360
361 spr_register(env, SPR_HID0, "HID0",
362 SPR_NOACCESS, SPR_NOACCESS,
363 &spr_read_generic, &spr_write_generic,
364 0x00000000);
365
366 spr_register(env, SPR_HID1, "HID1",
367 SPR_NOACCESS, SPR_NOACCESS,
368 &spr_read_generic, &spr_write_generic,
369 0x00000000);
370 }
371
register_e300_sprs(CPUPPCState * env)372 static void register_e300_sprs(CPUPPCState *env)
373 {
374 /* hardware implementation registers */
375 spr_register(env, SPR_HID2, "HID2",
376 SPR_NOACCESS, SPR_NOACCESS,
377 &spr_read_generic, &spr_write_generic,
378 0x00000000);
379 /* Breakpoints */
380 spr_register(env, SPR_DABR, "DABR",
381 SPR_NOACCESS, SPR_NOACCESS,
382 &spr_read_generic, &spr_write_generic,
383 0x00000000);
384
385 spr_register(env, SPR_DABR2, "DABR2",
386 SPR_NOACCESS, SPR_NOACCESS,
387 &spr_read_generic, &spr_write_generic,
388 0x00000000);
389
390 spr_register(env, SPR_IABR2, "IABR2",
391 SPR_NOACCESS, SPR_NOACCESS,
392 &spr_read_generic, &spr_write_generic,
393 0x00000000);
394
395 spr_register(env, SPR_IBCR, "IBCR",
396 SPR_NOACCESS, SPR_NOACCESS,
397 &spr_read_generic, &spr_write_generic,
398 0x00000000);
399
400 spr_register(env, SPR_DBCR, "DBCR",
401 SPR_NOACCESS, SPR_NOACCESS,
402 &spr_read_generic, &spr_write_generic,
403 0x00000000);
404 }
405
406 /* SPR specific to PowerPC G2 implementation */
register_G2_sprs(CPUPPCState * env)407 static void register_G2_sprs(CPUPPCState *env)
408 {
409 /* Memory base address */
410 /* MBAR */
411 spr_register(env, SPR_MBAR, "MBAR",
412 SPR_NOACCESS, SPR_NOACCESS,
413 &spr_read_generic, &spr_write_generic,
414 0x00000000);
415 /* Exception processing */
416 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
417 SPR_NOACCESS, SPR_NOACCESS,
418 &spr_read_generic, &spr_write_generic,
419 0x00000000);
420 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
421 SPR_NOACCESS, SPR_NOACCESS,
422 &spr_read_generic, &spr_write_generic,
423 0x00000000);
424 /* Breakpoints */
425 spr_register(env, SPR_DABR, "DABR",
426 SPR_NOACCESS, SPR_NOACCESS,
427 &spr_read_generic, &spr_write_generic,
428 0x00000000);
429
430 spr_register(env, SPR_DABR2, "DABR2",
431 SPR_NOACCESS, SPR_NOACCESS,
432 &spr_read_generic, &spr_write_generic,
433 0x00000000);
434
435 spr_register(env, SPR_IABR, "IABR",
436 SPR_NOACCESS, SPR_NOACCESS,
437 &spr_read_generic, &spr_write_generic,
438 0x00000000);
439
440 spr_register(env, SPR_IABR2, "IABR2",
441 SPR_NOACCESS, SPR_NOACCESS,
442 &spr_read_generic, &spr_write_generic,
443 0x00000000);
444
445 spr_register(env, SPR_IBCR, "IBCR",
446 SPR_NOACCESS, SPR_NOACCESS,
447 &spr_read_generic, &spr_write_generic,
448 0x00000000);
449
450 spr_register(env, SPR_DBCR, "DBCR",
451 SPR_NOACCESS, SPR_NOACCESS,
452 &spr_read_generic, &spr_write_generic,
453 0x00000000);
454
455 /* External access control */
456 spr_register(env, SPR_EAR, "EAR",
457 SPR_NOACCESS, SPR_NOACCESS,
458 &spr_read_generic, &spr_write_generic,
459 0x00000000);
460 /* Hardware implementation register */
461 spr_register(env, SPR_HID0, "HID0",
462 SPR_NOACCESS, SPR_NOACCESS,
463 &spr_read_generic, &spr_write_generic,
464 0x00000000);
465
466 spr_register(env, SPR_HID1, "HID1",
467 SPR_NOACCESS, SPR_NOACCESS,
468 &spr_read_generic, &spr_write_generic,
469 0x00000000);
470
471 spr_register(env, SPR_HID2, "HID2",
472 SPR_NOACCESS, SPR_NOACCESS,
473 &spr_read_generic, &spr_write_generic,
474 0x00000000);
475
476 /* SGPRs */
477 spr_register(env, SPR_SPRG4, "SPRG4",
478 SPR_NOACCESS, SPR_NOACCESS,
479 &spr_read_generic, &spr_write_generic,
480 0x00000000);
481 spr_register(env, SPR_SPRG5, "SPRG5",
482 SPR_NOACCESS, SPR_NOACCESS,
483 &spr_read_generic, &spr_write_generic,
484 0x00000000);
485 spr_register(env, SPR_SPRG6, "SPRG6",
486 SPR_NOACCESS, SPR_NOACCESS,
487 &spr_read_generic, &spr_write_generic,
488 0x00000000);
489 spr_register(env, SPR_SPRG7, "SPRG7",
490 SPR_NOACCESS, SPR_NOACCESS,
491 &spr_read_generic, &spr_write_generic,
492 0x00000000);
493 }
494
register_74xx_sprs(CPUPPCState * env)495 static void register_74xx_sprs(CPUPPCState *env)
496 {
497 /* Breakpoints */
498 spr_register_kvm(env, SPR_DABR, "DABR",
499 SPR_NOACCESS, SPR_NOACCESS,
500 &spr_read_generic, &spr_write_generic,
501 KVM_REG_PPC_DABR, 0x00000000);
502
503 spr_register(env, SPR_IABR, "IABR",
504 SPR_NOACCESS, SPR_NOACCESS,
505 &spr_read_generic, &spr_write_generic,
506 0x00000000);
507 /* Cache management */
508 spr_register(env, SPR_ICTC, "ICTC",
509 SPR_NOACCESS, SPR_NOACCESS,
510 &spr_read_generic, &spr_write_generic,
511 0x00000000);
512 /* Performance monitors */
513 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
514 SPR_NOACCESS, SPR_NOACCESS,
515 &spr_read_generic, &spr_write_generic,
516 0x00000000);
517
518 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
519 SPR_NOACCESS, SPR_NOACCESS,
520 &spr_read_generic, &spr_write_generic,
521 0x00000000);
522
523 spr_register(env, SPR_7XX_PMC1, "PMC1",
524 SPR_NOACCESS, SPR_NOACCESS,
525 &spr_read_generic, &spr_write_generic,
526 0x00000000);
527
528 spr_register(env, SPR_7XX_PMC2, "PMC2",
529 SPR_NOACCESS, SPR_NOACCESS,
530 &spr_read_generic, &spr_write_generic,
531 0x00000000);
532
533 spr_register(env, SPR_7XX_PMC3, "PMC3",
534 SPR_NOACCESS, SPR_NOACCESS,
535 &spr_read_generic, &spr_write_generic,
536 0x00000000);
537
538 spr_register(env, SPR_7XX_PMC4, "PMC4",
539 SPR_NOACCESS, SPR_NOACCESS,
540 &spr_read_generic, &spr_write_generic,
541 0x00000000);
542
543 spr_register(env, SPR_7XX_SIAR, "SIAR",
544 SPR_NOACCESS, SPR_NOACCESS,
545 &spr_read_generic, SPR_NOACCESS,
546 0x00000000);
547
548 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
549 &spr_read_ureg, SPR_NOACCESS,
550 &spr_read_ureg, SPR_NOACCESS,
551 0x00000000);
552
553 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
554 &spr_read_ureg, SPR_NOACCESS,
555 &spr_read_ureg, SPR_NOACCESS,
556 0x00000000);
557
558 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
559 &spr_read_ureg, SPR_NOACCESS,
560 &spr_read_ureg, SPR_NOACCESS,
561 0x00000000);
562
563 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
564 &spr_read_ureg, SPR_NOACCESS,
565 &spr_read_ureg, SPR_NOACCESS,
566 0x00000000);
567
568 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
569 &spr_read_ureg, SPR_NOACCESS,
570 &spr_read_ureg, SPR_NOACCESS,
571 0x00000000);
572
573 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
574 &spr_read_ureg, SPR_NOACCESS,
575 &spr_read_ureg, SPR_NOACCESS,
576 0x00000000);
577
578 spr_register(env, SPR_7XX_USIAR, "USIAR",
579 &spr_read_ureg, SPR_NOACCESS,
580 &spr_read_ureg, SPR_NOACCESS,
581 0x00000000);
582 /* External access control */
583 spr_register(env, SPR_EAR, "EAR",
584 SPR_NOACCESS, SPR_NOACCESS,
585 &spr_read_generic, &spr_write_generic,
586 0x00000000);
587
588 /* Processor identification */
589 spr_register(env, SPR_PIR, "PIR",
590 SPR_NOACCESS, SPR_NOACCESS,
591 &spr_read_generic, &spr_write_pir,
592 0x00000000);
593
594 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
595 SPR_NOACCESS, SPR_NOACCESS,
596 &spr_read_generic, &spr_write_generic,
597 0x00000000);
598
599 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
600 &spr_read_ureg, SPR_NOACCESS,
601 &spr_read_ureg, SPR_NOACCESS,
602 0x00000000);
603
604 spr_register(env, SPR_BAMR, "BAMR",
605 SPR_NOACCESS, SPR_NOACCESS,
606 &spr_read_generic, &spr_write_generic,
607 0x00000000);
608
609 spr_register(env, SPR_MSSCR0, "MSSCR0",
610 SPR_NOACCESS, SPR_NOACCESS,
611 &spr_read_generic, &spr_write_generic,
612 0x00000000);
613 /* Hardware implementation registers */
614 spr_register(env, SPR_HID0, "HID0",
615 SPR_NOACCESS, SPR_NOACCESS,
616 &spr_read_generic, &spr_write_generic,
617 0x00000000);
618
619 spr_register(env, SPR_HID1, "HID1",
620 SPR_NOACCESS, SPR_NOACCESS,
621 &spr_read_generic, &spr_write_generic,
622 0x00000000);
623 /* Altivec */
624 spr_register(env, SPR_VRSAVE, "VRSAVE",
625 &spr_read_generic, &spr_write_generic,
626 &spr_read_generic, &spr_write_generic,
627 0x00000000);
628
629 spr_register(env, SPR_L2CR, "L2CR",
630 SPR_NOACCESS, SPR_NOACCESS,
631 &spr_read_generic, spr_access_nop,
632 0x00000000);
633 }
634
register_l3_ctrl(CPUPPCState * env)635 static void register_l3_ctrl(CPUPPCState *env)
636 {
637 /* L3CR */
638 spr_register(env, SPR_L3CR, "L3CR",
639 SPR_NOACCESS, SPR_NOACCESS,
640 &spr_read_generic, &spr_write_generic,
641 0x00000000);
642 /* L3ITCR0 */
643 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
644 SPR_NOACCESS, SPR_NOACCESS,
645 &spr_read_generic, &spr_write_generic,
646 0x00000000);
647 /* L3PM */
648 spr_register(env, SPR_L3PM, "L3PM",
649 SPR_NOACCESS, SPR_NOACCESS,
650 &spr_read_generic, &spr_write_generic,
651 0x00000000);
652 }
653
654 /* PowerPC BookE SPR */
register_BookE_sprs(CPUPPCState * env,uint64_t ivor_mask)655 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
656 {
657 const char *ivor_names[64] = {
658 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
659 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
660 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
661 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
662 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
663 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
664 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
665 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
666 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
667 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
668 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
669 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
670 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
671 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
672 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
673 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
674 };
675 #define SPR_BOOKE_IVORxx (-1)
676 int ivor_sprn[64] = {
677 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
678 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
679 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
680 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
681 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
682 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
683 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
684 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
685 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
686 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
687 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
688 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
689 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
690 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
691 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
692 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
693 };
694 int i;
695
696 /* Interrupt processing */
697 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
698 SPR_NOACCESS, SPR_NOACCESS,
699 &spr_read_generic, &spr_write_generic,
700 0x00000000);
701 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
702 SPR_NOACCESS, SPR_NOACCESS,
703 &spr_read_generic, &spr_write_generic,
704 0x00000000);
705 /* Debug */
706 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
707 SPR_NOACCESS, SPR_NOACCESS,
708 &spr_read_generic, &spr_write_generic,
709 0x00000000);
710
711 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
712 SPR_NOACCESS, SPR_NOACCESS,
713 &spr_read_generic, &spr_write_generic,
714 0x00000000);
715
716 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
717 SPR_NOACCESS, SPR_NOACCESS,
718 &spr_read_generic, &spr_write_generic,
719 0x00000000);
720
721 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
722 SPR_NOACCESS, SPR_NOACCESS,
723 &spr_read_generic, &spr_write_generic,
724 0x00000000);
725
726 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
727 SPR_NOACCESS, SPR_NOACCESS,
728 &spr_read_generic, &spr_write_40x_dbcr0,
729 0x00000000);
730
731 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
732 SPR_NOACCESS, SPR_NOACCESS,
733 &spr_read_generic, &spr_write_generic,
734 0x00000000);
735
736 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
737 SPR_NOACCESS, SPR_NOACCESS,
738 &spr_read_generic, &spr_write_generic,
739 0x00000000);
740 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_generic, &spr_write_generic,
743 0x00000000);
744 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
745 SPR_NOACCESS, SPR_NOACCESS,
746 &spr_read_generic, &spr_write_generic,
747 0x00000000);
748
749 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
750 SPR_NOACCESS, SPR_NOACCESS,
751 &spr_read_generic, &spr_write_clear,
752 0x00000000);
753 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
754 SPR_NOACCESS, SPR_NOACCESS,
755 &spr_read_generic, &spr_write_generic,
756 0x00000000);
757 spr_register(env, SPR_BOOKE_ESR, "ESR",
758 SPR_NOACCESS, SPR_NOACCESS,
759 &spr_read_generic, &spr_write_generic,
760 0x00000000);
761 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
762 SPR_NOACCESS, SPR_NOACCESS,
763 &spr_read_generic, &spr_write_excp_prefix,
764 0x00000000);
765 /* Exception vectors */
766 for (i = 0; i < 64; i++) {
767 if (ivor_mask & (1ULL << i)) {
768 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
769 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
770 exit(1);
771 }
772 spr_register(env, ivor_sprn[i], ivor_names[i],
773 SPR_NOACCESS, SPR_NOACCESS,
774 &spr_read_generic, &spr_write_excp_vector,
775 0x00000000);
776 }
777 }
778 spr_register(env, SPR_BOOKE_PID, "PID",
779 SPR_NOACCESS, SPR_NOACCESS,
780 &spr_read_generic, &spr_write_booke_pid,
781 0x00000000);
782 spr_register(env, SPR_BOOKE_TCR, "TCR",
783 SPR_NOACCESS, SPR_NOACCESS,
784 &spr_read_generic, &spr_write_booke_tcr,
785 0x00000000);
786 spr_register(env, SPR_BOOKE_TSR, "TSR",
787 SPR_NOACCESS, SPR_NOACCESS,
788 &spr_read_generic, &spr_write_booke_tsr,
789 0x00000000);
790 /* Timer */
791 spr_register(env, SPR_DECR, "DECR",
792 SPR_NOACCESS, SPR_NOACCESS,
793 &spr_read_decr, &spr_write_decr,
794 0x00000000);
795 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
796 SPR_NOACCESS, SPR_NOACCESS,
797 SPR_NOACCESS, &spr_write_generic32,
798 0x00000000);
799 /* SPRGs */
800 spr_register(env, SPR_USPRG0, "USPRG0",
801 &spr_read_generic, &spr_write_generic,
802 &spr_read_generic, &spr_write_generic,
803 0x00000000);
804 spr_register(env, SPR_SPRG4, "SPRG4",
805 SPR_NOACCESS, SPR_NOACCESS,
806 &spr_read_generic, &spr_write_generic,
807 0x00000000);
808 spr_register(env, SPR_SPRG5, "SPRG5",
809 SPR_NOACCESS, SPR_NOACCESS,
810 &spr_read_generic, &spr_write_generic,
811 0x00000000);
812 spr_register(env, SPR_SPRG6, "SPRG6",
813 SPR_NOACCESS, SPR_NOACCESS,
814 &spr_read_generic, &spr_write_generic,
815 0x00000000);
816 spr_register(env, SPR_SPRG7, "SPRG7",
817 SPR_NOACCESS, SPR_NOACCESS,
818 &spr_read_generic, &spr_write_generic,
819 0x00000000);
820 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
821 SPR_NOACCESS, SPR_NOACCESS,
822 &spr_read_generic, &spr_write_generic,
823 0x00000000);
824 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
825 SPR_NOACCESS, SPR_NOACCESS,
826 &spr_read_generic, &spr_write_generic,
827 0x00000000);
828 }
829
830 #if !defined(CONFIG_USER_ONLY)
register_tlbncfg(uint32_t assoc,uint32_t minsize,uint32_t maxsize,uint32_t flags,uint32_t nentries)831 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
832 uint32_t maxsize, uint32_t flags,
833 uint32_t nentries)
834 {
835 return (assoc << TLBnCFG_ASSOC_SHIFT) |
836 (minsize << TLBnCFG_MINSIZE_SHIFT) |
837 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
838 flags | nentries;
839 }
840 #endif /* !CONFIG_USER_ONLY */
841
842 /* BookE 2.06 storage control registers */
register_BookE206_sprs(CPUPPCState * env,uint32_t mas_mask,uint32_t * tlbncfg,uint32_t mmucfg)843 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
844 uint32_t *tlbncfg, uint32_t mmucfg)
845 {
846 #if !defined(CONFIG_USER_ONLY)
847 const char *mas_names[8] = {
848 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
849 };
850 int mas_sprn[8] = {
851 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
852 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
853 };
854 int i;
855
856 /* TLB assist registers */
857 for (i = 0; i < 8; i++) {
858 if (mas_mask & (1 << i)) {
859 spr_register(env, mas_sprn[i], mas_names[i],
860 SPR_NOACCESS, SPR_NOACCESS,
861 &spr_read_generic,
862 (i == 2 && (env->insns_flags & PPC_64B))
863 ? &spr_write_generic : &spr_write_generic32,
864 0x00000000);
865 }
866 }
867 if (env->nb_pids > 1) {
868 spr_register(env, SPR_BOOKE_PID1, "PID1",
869 SPR_NOACCESS, SPR_NOACCESS,
870 &spr_read_generic, &spr_write_booke_pid,
871 0x00000000);
872 }
873 if (env->nb_pids > 2) {
874 spr_register(env, SPR_BOOKE_PID2, "PID2",
875 SPR_NOACCESS, SPR_NOACCESS,
876 &spr_read_generic, &spr_write_booke_pid,
877 0x00000000);
878 }
879
880 spr_register(env, SPR_BOOKE_EPLC, "EPLC",
881 SPR_NOACCESS, SPR_NOACCESS,
882 &spr_read_generic, &spr_write_eplc,
883 0x00000000);
884 spr_register(env, SPR_BOOKE_EPSC, "EPSC",
885 SPR_NOACCESS, SPR_NOACCESS,
886 &spr_read_generic, &spr_write_epsc,
887 0x00000000);
888
889 spr_register(env, SPR_MMUCFG, "MMUCFG",
890 SPR_NOACCESS, SPR_NOACCESS,
891 &spr_read_generic, SPR_NOACCESS,
892 mmucfg);
893 switch (env->nb_ways) {
894 case 4:
895 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
896 SPR_NOACCESS, SPR_NOACCESS,
897 &spr_read_generic, SPR_NOACCESS,
898 tlbncfg[3]);
899 /* Fallthru */
900 case 3:
901 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
902 SPR_NOACCESS, SPR_NOACCESS,
903 &spr_read_generic, SPR_NOACCESS,
904 tlbncfg[2]);
905 /* Fallthru */
906 case 2:
907 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
908 SPR_NOACCESS, SPR_NOACCESS,
909 &spr_read_generic, SPR_NOACCESS,
910 tlbncfg[1]);
911 /* Fallthru */
912 case 1:
913 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
914 SPR_NOACCESS, SPR_NOACCESS,
915 &spr_read_generic, SPR_NOACCESS,
916 tlbncfg[0]);
917 /* Fallthru */
918 case 0:
919 default:
920 break;
921 }
922 #endif
923 }
924
925 /* SPR specific to PowerPC 440 implementation */
register_440_sprs(CPUPPCState * env)926 static void register_440_sprs(CPUPPCState *env)
927 {
928 /* Cache control */
929 spr_register(env, SPR_440_DNV0, "DNV0",
930 SPR_NOACCESS, SPR_NOACCESS,
931 &spr_read_generic, &spr_write_generic,
932 0x00000000);
933
934 spr_register(env, SPR_440_DNV1, "DNV1",
935 SPR_NOACCESS, SPR_NOACCESS,
936 &spr_read_generic, &spr_write_generic,
937 0x00000000);
938
939 spr_register(env, SPR_440_DNV2, "DNV2",
940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, &spr_write_generic,
942 0x00000000);
943
944 spr_register(env, SPR_440_DNV3, "DNV3",
945 SPR_NOACCESS, SPR_NOACCESS,
946 &spr_read_generic, &spr_write_generic,
947 0x00000000);
948
949 spr_register(env, SPR_440_DTV0, "DTV0",
950 SPR_NOACCESS, SPR_NOACCESS,
951 &spr_read_generic, &spr_write_generic,
952 0x00000000);
953
954 spr_register(env, SPR_440_DTV1, "DTV1",
955 SPR_NOACCESS, SPR_NOACCESS,
956 &spr_read_generic, &spr_write_generic,
957 0x00000000);
958
959 spr_register(env, SPR_440_DTV2, "DTV2",
960 SPR_NOACCESS, SPR_NOACCESS,
961 &spr_read_generic, &spr_write_generic,
962 0x00000000);
963
964 spr_register(env, SPR_440_DTV3, "DTV3",
965 SPR_NOACCESS, SPR_NOACCESS,
966 &spr_read_generic, &spr_write_generic,
967 0x00000000);
968
969 spr_register(env, SPR_440_DVLIM, "DVLIM",
970 SPR_NOACCESS, SPR_NOACCESS,
971 &spr_read_generic, &spr_write_generic,
972 0x00000000);
973
974 spr_register(env, SPR_440_INV0, "INV0",
975 SPR_NOACCESS, SPR_NOACCESS,
976 &spr_read_generic, &spr_write_generic,
977 0x00000000);
978
979 spr_register(env, SPR_440_INV1, "INV1",
980 SPR_NOACCESS, SPR_NOACCESS,
981 &spr_read_generic, &spr_write_generic,
982 0x00000000);
983
984 spr_register(env, SPR_440_INV2, "INV2",
985 SPR_NOACCESS, SPR_NOACCESS,
986 &spr_read_generic, &spr_write_generic,
987 0x00000000);
988
989 spr_register(env, SPR_440_INV3, "INV3",
990 SPR_NOACCESS, SPR_NOACCESS,
991 &spr_read_generic, &spr_write_generic,
992 0x00000000);
993
994 spr_register(env, SPR_440_ITV0, "ITV0",
995 SPR_NOACCESS, SPR_NOACCESS,
996 &spr_read_generic, &spr_write_generic,
997 0x00000000);
998
999 spr_register(env, SPR_440_ITV1, "ITV1",
1000 SPR_NOACCESS, SPR_NOACCESS,
1001 &spr_read_generic, &spr_write_generic,
1002 0x00000000);
1003
1004 spr_register(env, SPR_440_ITV2, "ITV2",
1005 SPR_NOACCESS, SPR_NOACCESS,
1006 &spr_read_generic, &spr_write_generic,
1007 0x00000000);
1008
1009 spr_register(env, SPR_440_ITV3, "ITV3",
1010 SPR_NOACCESS, SPR_NOACCESS,
1011 &spr_read_generic, &spr_write_generic,
1012 0x00000000);
1013
1014 spr_register(env, SPR_440_IVLIM, "IVLIM",
1015 SPR_NOACCESS, SPR_NOACCESS,
1016 &spr_read_generic, &spr_write_generic,
1017 0x00000000);
1018 /* Cache debug */
1019 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1020 SPR_NOACCESS, SPR_NOACCESS,
1021 &spr_read_generic, SPR_NOACCESS,
1022 0x00000000);
1023
1024 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1025 SPR_NOACCESS, SPR_NOACCESS,
1026 &spr_read_generic, SPR_NOACCESS,
1027 0x00000000);
1028
1029 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1030 SPR_NOACCESS, SPR_NOACCESS,
1031 &spr_read_generic, SPR_NOACCESS,
1032 0x00000000);
1033
1034 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1035 SPR_NOACCESS, SPR_NOACCESS,
1036 &spr_read_generic, SPR_NOACCESS,
1037 0x00000000);
1038
1039 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1040 SPR_NOACCESS, SPR_NOACCESS,
1041 &spr_read_generic, SPR_NOACCESS,
1042 0x00000000);
1043
1044 spr_register(env, SPR_440_DBDR, "DBDR",
1045 SPR_NOACCESS, SPR_NOACCESS,
1046 &spr_read_generic, &spr_write_generic,
1047 0x00000000);
1048 /* Processor control */
1049 spr_register(env, SPR_4xx_CCR0, "CCR0",
1050 SPR_NOACCESS, SPR_NOACCESS,
1051 &spr_read_generic, &spr_write_generic,
1052 0x00000000);
1053 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1054 SPR_NOACCESS, SPR_NOACCESS,
1055 &spr_read_generic, SPR_NOACCESS,
1056 0x00000000);
1057 /* Storage control */
1058 spr_register(env, SPR_440_MMUCR, "MMUCR",
1059 SPR_NOACCESS, SPR_NOACCESS,
1060 &spr_read_generic, &spr_write_generic,
1061 0x00000000);
1062
1063 /* Processor identification */
1064 spr_register(env, SPR_BOOKE_PIR, "PIR",
1065 SPR_NOACCESS, SPR_NOACCESS,
1066 &spr_read_generic, &spr_write_pir,
1067 0x00000000);
1068
1069 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1070 SPR_NOACCESS, SPR_NOACCESS,
1071 &spr_read_generic, &spr_write_generic,
1072 0x00000000);
1073
1074 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1075 SPR_NOACCESS, SPR_NOACCESS,
1076 &spr_read_generic, &spr_write_generic,
1077 0x00000000);
1078
1079 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1080 SPR_NOACCESS, SPR_NOACCESS,
1081 &spr_read_generic, &spr_write_generic,
1082 0x00000000);
1083
1084 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1085 SPR_NOACCESS, SPR_NOACCESS,
1086 &spr_read_generic, &spr_write_generic,
1087 0x00000000);
1088 }
1089
1090 /* SPR shared between PowerPC 40x implementations */
register_40x_sprs(CPUPPCState * env)1091 static void register_40x_sprs(CPUPPCState *env)
1092 {
1093 /* Cache */
1094 /* not emulated, as QEMU do not emulate caches */
1095 spr_register(env, SPR_40x_DCCR, "DCCR",
1096 SPR_NOACCESS, SPR_NOACCESS,
1097 &spr_read_generic, &spr_write_generic,
1098 0x00000000);
1099 /* not emulated, as QEMU do not emulate caches */
1100 spr_register(env, SPR_40x_ICCR, "ICCR",
1101 SPR_NOACCESS, SPR_NOACCESS,
1102 &spr_read_generic, &spr_write_generic,
1103 0x00000000);
1104 /* not emulated, as QEMU do not emulate caches */
1105 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1106 SPR_NOACCESS, SPR_NOACCESS,
1107 &spr_read_generic, SPR_NOACCESS,
1108 0x00000000);
1109 /* Exception */
1110 spr_register(env, SPR_40x_DEAR, "DEAR",
1111 SPR_NOACCESS, SPR_NOACCESS,
1112 &spr_read_generic, &spr_write_generic,
1113 0x00000000);
1114 spr_register(env, SPR_40x_ESR, "ESR",
1115 SPR_NOACCESS, SPR_NOACCESS,
1116 &spr_read_generic, &spr_write_generic,
1117 0x00000000);
1118 spr_register(env, SPR_40x_EVPR, "EVPR",
1119 SPR_NOACCESS, SPR_NOACCESS,
1120 &spr_read_generic, &spr_write_excp_prefix,
1121 0x00000000);
1122 spr_register(env, SPR_40x_SRR2, "SRR2",
1123 &spr_read_generic, &spr_write_generic,
1124 &spr_read_generic, &spr_write_generic,
1125 0x00000000);
1126 spr_register(env, SPR_40x_SRR3, "SRR3",
1127 &spr_read_generic, &spr_write_generic,
1128 &spr_read_generic, &spr_write_generic,
1129 0x00000000);
1130 /* Timers */
1131 spr_register(env, SPR_40x_PIT, "PIT",
1132 SPR_NOACCESS, SPR_NOACCESS,
1133 &spr_read_40x_pit, &spr_write_40x_pit,
1134 0x00000000);
1135 spr_register(env, SPR_40x_TCR, "TCR",
1136 SPR_NOACCESS, SPR_NOACCESS,
1137 &spr_read_generic, &spr_write_40x_tcr,
1138 0x00000000);
1139 spr_register(env, SPR_40x_TSR, "TSR",
1140 SPR_NOACCESS, SPR_NOACCESS,
1141 &spr_read_generic, &spr_write_40x_tsr,
1142 0x00000000);
1143 }
1144
1145 /* SPR specific to PowerPC 405 implementation */
register_405_sprs(CPUPPCState * env)1146 static void register_405_sprs(CPUPPCState *env)
1147 {
1148 /* MMU */
1149 spr_register(env, SPR_40x_PID, "PID",
1150 SPR_NOACCESS, SPR_NOACCESS,
1151 &spr_read_generic, &spr_write_40x_pid,
1152 0x00000000);
1153 spr_register(env, SPR_4xx_CCR0, "CCR0",
1154 SPR_NOACCESS, SPR_NOACCESS,
1155 &spr_read_generic, &spr_write_generic,
1156 0x00700000);
1157 /* Debug interface */
1158 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1159 SPR_NOACCESS, SPR_NOACCESS,
1160 &spr_read_generic, &spr_write_40x_dbcr0,
1161 0x00000000);
1162
1163 spr_register(env, SPR_405_DBCR1, "DBCR1",
1164 SPR_NOACCESS, SPR_NOACCESS,
1165 &spr_read_generic, &spr_write_generic,
1166 0x00000000);
1167
1168 spr_register(env, SPR_40x_DBSR, "DBSR",
1169 SPR_NOACCESS, SPR_NOACCESS,
1170 &spr_read_generic, &spr_write_clear,
1171 /* Last reset was system reset */
1172 0x00000300);
1173
1174 spr_register(env, SPR_40x_DAC1, "DAC1",
1175 SPR_NOACCESS, SPR_NOACCESS,
1176 &spr_read_generic, &spr_write_generic,
1177 0x00000000);
1178 spr_register(env, SPR_40x_DAC2, "DAC2",
1179 SPR_NOACCESS, SPR_NOACCESS,
1180 &spr_read_generic, &spr_write_generic,
1181 0x00000000);
1182
1183 spr_register(env, SPR_405_DVC1, "DVC1",
1184 SPR_NOACCESS, SPR_NOACCESS,
1185 &spr_read_generic, &spr_write_generic,
1186 0x00000000);
1187
1188 spr_register(env, SPR_405_DVC2, "DVC2",
1189 SPR_NOACCESS, SPR_NOACCESS,
1190 &spr_read_generic, &spr_write_generic,
1191 0x00000000);
1192
1193 spr_register(env, SPR_40x_IAC1, "IAC1",
1194 SPR_NOACCESS, SPR_NOACCESS,
1195 &spr_read_generic, &spr_write_generic,
1196 0x00000000);
1197 spr_register(env, SPR_40x_IAC2, "IAC2",
1198 SPR_NOACCESS, SPR_NOACCESS,
1199 &spr_read_generic, &spr_write_generic,
1200 0x00000000);
1201
1202 spr_register(env, SPR_405_IAC3, "IAC3",
1203 SPR_NOACCESS, SPR_NOACCESS,
1204 &spr_read_generic, &spr_write_generic,
1205 0x00000000);
1206
1207 spr_register(env, SPR_405_IAC4, "IAC4",
1208 SPR_NOACCESS, SPR_NOACCESS,
1209 &spr_read_generic, &spr_write_generic,
1210 0x00000000);
1211 /* Storage control */
1212 spr_register(env, SPR_405_SLER, "SLER",
1213 SPR_NOACCESS, SPR_NOACCESS,
1214 &spr_read_generic, &spr_write_40x_sler,
1215 0x00000000);
1216 spr_register(env, SPR_40x_ZPR, "ZPR",
1217 SPR_NOACCESS, SPR_NOACCESS,
1218 &spr_read_generic, &spr_write_generic,
1219 0x00000000);
1220
1221 spr_register(env, SPR_405_SU0R, "SU0R",
1222 SPR_NOACCESS, SPR_NOACCESS,
1223 &spr_read_generic, &spr_write_generic,
1224 0x00000000);
1225 /* SPRG */
1226 spr_register(env, SPR_USPRG0, "USPRG0",
1227 &spr_read_ureg, SPR_NOACCESS,
1228 &spr_read_ureg, SPR_NOACCESS,
1229 0x00000000);
1230 spr_register(env, SPR_SPRG4, "SPRG4",
1231 SPR_NOACCESS, SPR_NOACCESS,
1232 &spr_read_generic, &spr_write_generic,
1233 0x00000000);
1234 spr_register(env, SPR_SPRG5, "SPRG5",
1235 SPR_NOACCESS, SPR_NOACCESS,
1236 spr_read_generic, &spr_write_generic,
1237 0x00000000);
1238 spr_register(env, SPR_SPRG6, "SPRG6",
1239 SPR_NOACCESS, SPR_NOACCESS,
1240 spr_read_generic, &spr_write_generic,
1241 0x00000000);
1242 spr_register(env, SPR_SPRG7, "SPRG7",
1243 SPR_NOACCESS, SPR_NOACCESS,
1244 spr_read_generic, &spr_write_generic,
1245 0x00000000);
1246
1247 /* Bus access control */
1248 /* not emulated, as QEMU never does speculative access */
1249 spr_register(env, SPR_40x_SGR, "SGR",
1250 SPR_NOACCESS, SPR_NOACCESS,
1251 &spr_read_generic, &spr_write_generic,
1252 0xFFFFFFFF);
1253 /* not emulated, as QEMU do not emulate caches */
1254 spr_register(env, SPR_40x_DCWR, "DCWR",
1255 SPR_NOACCESS, SPR_NOACCESS,
1256 &spr_read_generic, &spr_write_generic,
1257 0x00000000);
1258 }
1259
1260
register_5xx_8xx_sprs(CPUPPCState * env)1261 static void register_5xx_8xx_sprs(CPUPPCState *env)
1262 {
1263 /* Exception processing */
1264 spr_register_kvm(env, SPR_DSISR, "DSISR",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_generic, &spr_write_generic,
1267 KVM_REG_PPC_DSISR, 0x00000000);
1268 spr_register_kvm(env, SPR_DAR, "DAR",
1269 SPR_NOACCESS, SPR_NOACCESS,
1270 &spr_read_generic, &spr_write_generic,
1271 KVM_REG_PPC_DAR, 0x00000000);
1272 /* Timer */
1273 spr_register(env, SPR_DECR, "DECR",
1274 SPR_NOACCESS, SPR_NOACCESS,
1275 &spr_read_decr, &spr_write_decr,
1276 0x00000000);
1277
1278 spr_register(env, SPR_MPC_EIE, "EIE",
1279 SPR_NOACCESS, SPR_NOACCESS,
1280 &spr_read_generic, &spr_write_generic,
1281 0x00000000);
1282
1283 spr_register(env, SPR_MPC_EID, "EID",
1284 SPR_NOACCESS, SPR_NOACCESS,
1285 &spr_read_generic, &spr_write_generic,
1286 0x00000000);
1287
1288 spr_register(env, SPR_MPC_NRI, "NRI",
1289 SPR_NOACCESS, SPR_NOACCESS,
1290 &spr_read_generic, &spr_write_generic,
1291 0x00000000);
1292
1293 spr_register(env, SPR_MPC_CMPA, "CMPA",
1294 SPR_NOACCESS, SPR_NOACCESS,
1295 &spr_read_generic, &spr_write_generic,
1296 0x00000000);
1297
1298 spr_register(env, SPR_MPC_CMPB, "CMPB",
1299 SPR_NOACCESS, SPR_NOACCESS,
1300 &spr_read_generic, &spr_write_generic,
1301 0x00000000);
1302
1303 spr_register(env, SPR_MPC_CMPC, "CMPC",
1304 SPR_NOACCESS, SPR_NOACCESS,
1305 &spr_read_generic, &spr_write_generic,
1306 0x00000000);
1307
1308 spr_register(env, SPR_MPC_CMPD, "CMPD",
1309 SPR_NOACCESS, SPR_NOACCESS,
1310 &spr_read_generic, &spr_write_generic,
1311 0x00000000);
1312
1313 spr_register(env, SPR_MPC_ECR, "ECR",
1314 SPR_NOACCESS, SPR_NOACCESS,
1315 &spr_read_generic, &spr_write_generic,
1316 0x00000000);
1317
1318 spr_register(env, SPR_MPC_DER, "DER",
1319 SPR_NOACCESS, SPR_NOACCESS,
1320 &spr_read_generic, &spr_write_generic,
1321 0x00000000);
1322
1323 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
1324 SPR_NOACCESS, SPR_NOACCESS,
1325 &spr_read_generic, &spr_write_generic,
1326 0x00000000);
1327
1328 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
1329 SPR_NOACCESS, SPR_NOACCESS,
1330 &spr_read_generic, &spr_write_generic,
1331 0x00000000);
1332
1333 spr_register(env, SPR_MPC_CMPE, "CMPE",
1334 SPR_NOACCESS, SPR_NOACCESS,
1335 &spr_read_generic, &spr_write_generic,
1336 0x00000000);
1337
1338 spr_register(env, SPR_MPC_CMPF, "CMPF",
1339 SPR_NOACCESS, SPR_NOACCESS,
1340 &spr_read_generic, &spr_write_generic,
1341 0x00000000);
1342
1343 spr_register(env, SPR_MPC_CMPG, "CMPG",
1344 SPR_NOACCESS, SPR_NOACCESS,
1345 &spr_read_generic, &spr_write_generic,
1346 0x00000000);
1347
1348 spr_register(env, SPR_MPC_CMPH, "CMPH",
1349 SPR_NOACCESS, SPR_NOACCESS,
1350 &spr_read_generic, &spr_write_generic,
1351 0x00000000);
1352
1353 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
1354 SPR_NOACCESS, SPR_NOACCESS,
1355 &spr_read_generic, &spr_write_generic,
1356 0x00000000);
1357
1358 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
1359 SPR_NOACCESS, SPR_NOACCESS,
1360 &spr_read_generic, &spr_write_generic,
1361 0x00000000);
1362
1363 spr_register(env, SPR_MPC_BAR, "BAR",
1364 SPR_NOACCESS, SPR_NOACCESS,
1365 &spr_read_generic, &spr_write_generic,
1366 0x00000000);
1367
1368 spr_register(env, SPR_MPC_DPDR, "DPDR",
1369 SPR_NOACCESS, SPR_NOACCESS,
1370 &spr_read_generic, &spr_write_generic,
1371 0x00000000);
1372
1373 spr_register(env, SPR_MPC_IMMR, "IMMR",
1374 SPR_NOACCESS, SPR_NOACCESS,
1375 &spr_read_generic, &spr_write_generic,
1376 0x00000000);
1377 }
1378
register_5xx_sprs(CPUPPCState * env)1379 static void register_5xx_sprs(CPUPPCState *env)
1380 {
1381 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
1382 SPR_NOACCESS, SPR_NOACCESS,
1383 &spr_read_generic, &spr_write_generic,
1384 0x00000000);
1385
1386 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
1387 SPR_NOACCESS, SPR_NOACCESS,
1388 &spr_read_generic, &spr_write_generic,
1389 0x00000000);
1390
1391 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
1392 SPR_NOACCESS, SPR_NOACCESS,
1393 &spr_read_generic, &spr_write_generic,
1394 0x00000000);
1395
1396 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
1397 SPR_NOACCESS, SPR_NOACCESS,
1398 &spr_read_generic, &spr_write_generic,
1399 0x00000000);
1400
1401 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
1402 SPR_NOACCESS, SPR_NOACCESS,
1403 &spr_read_generic, &spr_write_generic,
1404 0x00000000);
1405
1406 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
1407 SPR_NOACCESS, SPR_NOACCESS,
1408 &spr_read_generic, &spr_write_generic,
1409 0x00000000);
1410
1411 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
1412 SPR_NOACCESS, SPR_NOACCESS,
1413 &spr_read_generic, &spr_write_generic,
1414 0x00000000);
1415
1416 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
1417 SPR_NOACCESS, SPR_NOACCESS,
1418 &spr_read_generic, &spr_write_generic,
1419 0x00000000);
1420
1421 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
1422 SPR_NOACCESS, SPR_NOACCESS,
1423 &spr_read_generic, &spr_write_generic,
1424 0x00000000);
1425
1426 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
1427 SPR_NOACCESS, SPR_NOACCESS,
1428 &spr_read_generic, &spr_write_generic,
1429 0x00000000);
1430
1431 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
1432 SPR_NOACCESS, SPR_NOACCESS,
1433 &spr_read_generic, &spr_write_generic,
1434 0x00000000);
1435
1436 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
1437 SPR_NOACCESS, SPR_NOACCESS,
1438 &spr_read_generic, &spr_write_generic,
1439 0x00000000);
1440
1441 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
1442 SPR_NOACCESS, SPR_NOACCESS,
1443 &spr_read_generic, &spr_write_generic,
1444 0x00000000);
1445
1446 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
1447 SPR_NOACCESS, SPR_NOACCESS,
1448 &spr_read_generic, &spr_write_generic,
1449 0x00000000);
1450
1451 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
1452 SPR_NOACCESS, SPR_NOACCESS,
1453 &spr_read_generic, &spr_write_generic,
1454 0x00000000);
1455
1456 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
1457 SPR_NOACCESS, SPR_NOACCESS,
1458 &spr_read_generic, &spr_write_generic,
1459 0x00000000);
1460
1461 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
1462 SPR_NOACCESS, SPR_NOACCESS,
1463 &spr_read_generic, &spr_write_generic,
1464 0x00000000);
1465
1466 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
1467 SPR_NOACCESS, SPR_NOACCESS,
1468 &spr_read_generic, &spr_write_generic,
1469 0x00000000);
1470
1471 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
1472 SPR_NOACCESS, SPR_NOACCESS,
1473 &spr_read_generic, &spr_write_generic,
1474 0x00000000);
1475
1476 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
1477 SPR_NOACCESS, SPR_NOACCESS,
1478 &spr_read_generic, &spr_write_generic,
1479 0x00000000);
1480
1481 spr_register(env, SPR_RCPU_FPECR, "FPECR",
1482 SPR_NOACCESS, SPR_NOACCESS,
1483 &spr_read_generic, &spr_write_generic,
1484 0x00000000);
1485 }
1486
register_8xx_sprs(CPUPPCState * env)1487 static void register_8xx_sprs(CPUPPCState *env)
1488 {
1489
1490 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
1491 SPR_NOACCESS, SPR_NOACCESS,
1492 &spr_read_generic, &spr_write_generic,
1493 0x00000000);
1494
1495 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
1496 SPR_NOACCESS, SPR_NOACCESS,
1497 &spr_read_generic, &spr_write_generic,
1498 0x00000000);
1499
1500 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
1501 SPR_NOACCESS, SPR_NOACCESS,
1502 &spr_read_generic, &spr_write_generic,
1503 0x00000000);
1504
1505 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
1506 SPR_NOACCESS, SPR_NOACCESS,
1507 &spr_read_generic, &spr_write_generic,
1508 0x00000000);
1509
1510 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
1511 SPR_NOACCESS, SPR_NOACCESS,
1512 &spr_read_generic, &spr_write_generic,
1513 0x00000000);
1514
1515 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
1516 SPR_NOACCESS, SPR_NOACCESS,
1517 &spr_read_generic, &spr_write_generic,
1518 0x00000000);
1519
1520 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
1521 SPR_NOACCESS, SPR_NOACCESS,
1522 &spr_read_generic, &spr_write_generic,
1523 0x00000000);
1524
1525 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
1526 SPR_NOACCESS, SPR_NOACCESS,
1527 &spr_read_generic, &spr_write_generic,
1528 0x00000000);
1529
1530 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
1531 SPR_NOACCESS, SPR_NOACCESS,
1532 &spr_read_generic, &spr_write_generic,
1533 0x00000000);
1534
1535 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
1536 SPR_NOACCESS, SPR_NOACCESS,
1537 &spr_read_generic, &spr_write_generic,
1538 0x00000000);
1539
1540 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
1541 SPR_NOACCESS, SPR_NOACCESS,
1542 &spr_read_generic, &spr_write_generic,
1543 0x00000000);
1544
1545 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
1546 SPR_NOACCESS, SPR_NOACCESS,
1547 &spr_read_generic, &spr_write_generic,
1548 0x00000000);
1549
1550 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
1551 SPR_NOACCESS, SPR_NOACCESS,
1552 &spr_read_generic, &spr_write_generic,
1553 0x00000000);
1554
1555 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
1556 SPR_NOACCESS, SPR_NOACCESS,
1557 &spr_read_generic, &spr_write_generic,
1558 0x00000000);
1559
1560 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
1561 SPR_NOACCESS, SPR_NOACCESS,
1562 &spr_read_generic, &spr_write_generic,
1563 0x00000000);
1564
1565 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
1566 SPR_NOACCESS, SPR_NOACCESS,
1567 &spr_read_generic, &spr_write_generic,
1568 0x00000000);
1569
1570 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
1571 SPR_NOACCESS, SPR_NOACCESS,
1572 &spr_read_generic, &spr_write_generic,
1573 0x00000000);
1574
1575 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
1576 SPR_NOACCESS, SPR_NOACCESS,
1577 &spr_read_generic, &spr_write_generic,
1578 0x00000000);
1579
1580 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
1581 SPR_NOACCESS, SPR_NOACCESS,
1582 &spr_read_generic, &spr_write_generic,
1583 0x00000000);
1584
1585 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
1586 SPR_NOACCESS, SPR_NOACCESS,
1587 &spr_read_generic, &spr_write_generic,
1588 0x00000000);
1589
1590 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
1591 SPR_NOACCESS, SPR_NOACCESS,
1592 &spr_read_generic, &spr_write_generic,
1593 0x00000000);
1594
1595 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
1596 SPR_NOACCESS, SPR_NOACCESS,
1597 &spr_read_generic, &spr_write_generic,
1598 0x00000000);
1599
1600 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
1601 SPR_NOACCESS, SPR_NOACCESS,
1602 &spr_read_generic, &spr_write_generic,
1603 0x00000000);
1604
1605 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
1606 SPR_NOACCESS, SPR_NOACCESS,
1607 &spr_read_generic, &spr_write_generic,
1608 0x00000000);
1609
1610 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
1611 SPR_NOACCESS, SPR_NOACCESS,
1612 &spr_read_generic, &spr_write_generic,
1613 0x00000000);
1614 }
1615
1616 /*
1617 * AMR => SPR 29 (Power 2.04)
1618 * CTRL => SPR 136 (Power 2.04)
1619 * CTRL => SPR 152 (Power 2.04)
1620 * SCOMC => SPR 276 (64 bits ?)
1621 * SCOMD => SPR 277 (64 bits ?)
1622 * TBU40 => SPR 286 (Power 2.04 hypv)
1623 * HSPRG0 => SPR 304 (Power 2.04 hypv)
1624 * HSPRG1 => SPR 305 (Power 2.04 hypv)
1625 * HDSISR => SPR 306 (Power 2.04 hypv)
1626 * HDAR => SPR 307 (Power 2.04 hypv)
1627 * PURR => SPR 309 (Power 2.04 hypv)
1628 * HDEC => SPR 310 (Power 2.04 hypv)
1629 * HIOR => SPR 311 (hypv)
1630 * RMOR => SPR 312 (970)
1631 * HRMOR => SPR 313 (Power 2.04 hypv)
1632 * HSRR0 => SPR 314 (Power 2.04 hypv)
1633 * HSRR1 => SPR 315 (Power 2.04 hypv)
1634 * LPIDR => SPR 317 (970)
1635 * HEIR => SPR 339 (Power 2.05 hypv) (64-bit reg from 3.1)
1636 * EPR => SPR 702 (Power 2.04 emb)
1637 * perf => 768-783 (Power 2.04)
1638 * perf => 784-799 (Power 2.04)
1639 * PPR => SPR 896 (Power 2.04)
1640 * DABRX => 1015 (Power 2.04 hypv)
1641 * FPECR => SPR 1022 (?)
1642 * ... and more (thermal management, performance counters, ...)
1643 */
1644
1645 /*****************************************************************************/
1646 /* Exception vectors models */
init_excp_4xx(CPUPPCState * env)1647 static void init_excp_4xx(CPUPPCState *env)
1648 {
1649 #if !defined(CONFIG_USER_ONLY)
1650 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
1651 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1652 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1653 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1654 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1655 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1656 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1657 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1658 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
1659 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
1660 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
1661 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
1662 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
1663 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
1664 env->ivor_mask = 0x0000FFF0UL;
1665 env->ivpr_mask = 0xFFFF0000UL;
1666 /* Hardware reset vector */
1667 env->hreset_vector = 0xFFFFFFFCUL;
1668 #endif
1669 }
1670
init_excp_MPC5xx(CPUPPCState * env)1671 static void init_excp_MPC5xx(CPUPPCState *env)
1672 {
1673 #if !defined(CONFIG_USER_ONLY)
1674 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1675 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1676 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1677 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1678 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1679 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1680 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1681 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1682 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1683 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1684 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1685 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1686 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1687 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1688 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
1689 env->ivor_mask = 0x0000FFF0UL;
1690 env->ivpr_mask = 0xFFFF0000UL;
1691 /* Hardware reset vector */
1692 env->hreset_vector = 0x00000100UL;
1693 #endif
1694 }
1695
init_excp_MPC8xx(CPUPPCState * env)1696 static void init_excp_MPC8xx(CPUPPCState *env)
1697 {
1698 #if !defined(CONFIG_USER_ONLY)
1699 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1700 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1701 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1702 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1703 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1704 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1705 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1706 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1707 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1708 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1709 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1710 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1711 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1712 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
1713 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
1714 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
1715 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
1716 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1717 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1718 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1719 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
1720 env->ivor_mask = 0x0000FFF0UL;
1721 env->ivpr_mask = 0xFFFF0000UL;
1722 /* Hardware reset vector */
1723 env->hreset_vector = 0x00000100UL;
1724 #endif
1725 }
1726
init_excp_G2(CPUPPCState * env)1727 static void init_excp_G2(CPUPPCState *env)
1728 {
1729 #if !defined(CONFIG_USER_ONLY)
1730 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1731 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1732 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1733 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1734 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1735 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1736 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1737 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1738 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1739 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
1740 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1741 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1742 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1743 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1744 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1745 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1746 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1747 /* Hardware reset vector */
1748 env->hreset_vector = 0x00000100UL;
1749 #endif
1750 }
1751
init_excp_e200(CPUPPCState * env,target_ulong ivpr_mask)1752 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
1753 {
1754 #if !defined(CONFIG_USER_ONLY)
1755 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
1756 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
1757 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1758 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
1759 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
1760 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
1761 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
1762 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
1763 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
1764 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
1765 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
1766 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
1767 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
1768 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
1769 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
1770 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
1771 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
1772 /*
1773 * These two are the same IVOR as POWERPC_EXCP_VPU and
1774 * POWERPC_EXCP_VPUA. We deal with that when dispatching at
1775 * powerpc_excp().
1776 */
1777 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
1778 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
1779
1780 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
1781 env->ivor_mask = 0x0000FFF7UL;
1782 env->ivpr_mask = ivpr_mask;
1783 /* Hardware reset vector */
1784 env->hreset_vector = 0xFFFFFFFCUL;
1785 #endif
1786 }
1787
init_excp_BookE(CPUPPCState * env)1788 static void init_excp_BookE(CPUPPCState *env)
1789 {
1790 #if !defined(CONFIG_USER_ONLY)
1791 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
1792 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1793 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
1794 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
1795 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
1796 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
1797 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
1798 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
1799 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
1800 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
1801 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
1802 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
1803 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
1804 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
1805 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
1806 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
1807 env->ivor_mask = 0x0000FFF0UL;
1808 env->ivpr_mask = 0xFFFF0000UL;
1809 /* Hardware reset vector */
1810 env->hreset_vector = 0xFFFFFFFCUL;
1811 #endif
1812 }
1813
init_excp_603(CPUPPCState * env)1814 static void init_excp_603(CPUPPCState *env)
1815 {
1816 #if !defined(CONFIG_USER_ONLY)
1817 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1818 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1819 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1820 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1821 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1822 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1823 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1824 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1825 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1826 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1827 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1828 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1829 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1830 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1831 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1832 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1833 /* Hardware reset vector */
1834 env->hreset_vector = 0x00000100UL;
1835 #endif
1836 }
1837
init_excp_604(CPUPPCState * env)1838 static void init_excp_604(CPUPPCState *env)
1839 {
1840 #if !defined(CONFIG_USER_ONLY)
1841 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1842 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1843 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1844 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1845 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1846 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1847 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1848 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1849 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1850 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1851 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1852 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1853 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1854 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1855 /* Hardware reset vector */
1856 env->hreset_vector = 0x00000100UL;
1857 #endif
1858 }
1859
init_excp_7x0(CPUPPCState * env)1860 static void init_excp_7x0(CPUPPCState *env)
1861 {
1862 #if !defined(CONFIG_USER_ONLY)
1863 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1864 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1865 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1866 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1867 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1868 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1869 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1870 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1871 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1872 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1873 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1874 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1875 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1876 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1877 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1878 /* Hardware reset vector */
1879 env->hreset_vector = 0x00000100UL;
1880 #endif
1881 }
1882
init_excp_750cl(CPUPPCState * env)1883 static void init_excp_750cl(CPUPPCState *env)
1884 {
1885 #if !defined(CONFIG_USER_ONLY)
1886 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1887 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1888 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1889 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1890 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1891 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1892 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1893 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1894 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1895 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1896 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1897 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1898 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1899 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1900 /* Hardware reset vector */
1901 env->hreset_vector = 0x00000100UL;
1902 #endif
1903 }
1904
init_excp_750cx(CPUPPCState * env)1905 static void init_excp_750cx(CPUPPCState *env)
1906 {
1907 #if !defined(CONFIG_USER_ONLY)
1908 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1909 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1910 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1911 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1912 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1913 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1914 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1915 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1916 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1917 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1918 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1919 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1920 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1921 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1922 /* Hardware reset vector */
1923 env->hreset_vector = 0x00000100UL;
1924 #endif
1925 }
1926
1927 /* XXX: Check if this is correct */
init_excp_7x5(CPUPPCState * env)1928 static void init_excp_7x5(CPUPPCState *env)
1929 {
1930 #if !defined(CONFIG_USER_ONLY)
1931 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1932 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1933 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1934 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1935 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1936 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1937 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1938 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1939 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1940 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1941 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1942 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1943 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1944 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1945 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1946 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1947 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1948 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1949 /* Hardware reset vector */
1950 env->hreset_vector = 0x00000100UL;
1951 #endif
1952 }
1953
init_excp_7400(CPUPPCState * env)1954 static void init_excp_7400(CPUPPCState *env)
1955 {
1956 #if !defined(CONFIG_USER_ONLY)
1957 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1958 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1959 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1960 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1961 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1962 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1963 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1964 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1965 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1966 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1967 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1968 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1969 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
1970 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1971 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1972 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
1973 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1974 /* Hardware reset vector */
1975 env->hreset_vector = 0x00000100UL;
1976 #endif
1977 }
1978
init_excp_7450(CPUPPCState * env)1979 static void init_excp_7450(CPUPPCState *env)
1980 {
1981 #if !defined(CONFIG_USER_ONLY)
1982 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1983 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1984 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1985 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1986 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1987 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1988 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1989 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1990 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1991 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1992 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1993 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1994 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
1995 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1996 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1997 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
1998 /* Hardware reset vector */
1999 env->hreset_vector = 0x00000100UL;
2000 #endif
2001 }
2002
2003 #if defined(TARGET_PPC64)
init_excp_970(CPUPPCState * env)2004 static void init_excp_970(CPUPPCState *env)
2005 {
2006 #if !defined(CONFIG_USER_ONLY)
2007 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2008 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2009 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2010 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2011 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2012 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2013 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2014 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2015 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2016 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2017 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2018 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2019 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2020 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2021 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2022 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2023 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2024 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2025 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2026 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
2027 /* Hardware reset vector */
2028 env->hreset_vector = 0x0000000000000100ULL;
2029 #endif
2030 }
2031
init_excp_POWER7(CPUPPCState * env)2032 static void init_excp_POWER7(CPUPPCState *env)
2033 {
2034 #if !defined(CONFIG_USER_ONLY)
2035 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2036 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2037 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2038 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2039 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2040 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2041 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2042 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2043 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2044 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2045 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2046 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2047 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2048 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2049 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
2050 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
2051 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
2052 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
2053 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2054 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2055 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
2056 /* Hardware reset vector */
2057 env->hreset_vector = 0x0000000000000100ULL;
2058 #endif
2059 }
2060
init_excp_POWER8(CPUPPCState * env)2061 static void init_excp_POWER8(CPUPPCState *env)
2062 {
2063 init_excp_POWER7(env);
2064
2065 #if !defined(CONFIG_USER_ONLY)
2066 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
2067 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
2068 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
2069 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
2070
2071 /* Userland exceptions without vector value in PowerISA v3.1 */
2072 env->excp_vectors[POWERPC_EXCP_PERFM_EBB] = 0x0;
2073 env->excp_vectors[POWERPC_EXCP_EXTERNAL_EBB] = 0x0;
2074 #endif
2075 }
2076
init_excp_POWER9(CPUPPCState * env)2077 static void init_excp_POWER9(CPUPPCState *env)
2078 {
2079 init_excp_POWER8(env);
2080
2081 #if !defined(CONFIG_USER_ONLY)
2082 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0;
2083 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000;
2084 #endif
2085 }
2086
init_excp_POWER10(CPUPPCState * env)2087 static void init_excp_POWER10(CPUPPCState *env)
2088 {
2089 init_excp_POWER9(env);
2090 }
2091
2092 #endif
2093
check_pow_hid0(CPUPPCState * env)2094 static int check_pow_hid0(CPUPPCState *env)
2095 {
2096 if (env->spr[SPR_HID0] & 0x00E00000) {
2097 return 1;
2098 }
2099
2100 return 0;
2101 }
2102
check_pow_hid0_74xx(CPUPPCState * env)2103 static int check_pow_hid0_74xx(CPUPPCState *env)
2104 {
2105 if (env->spr[SPR_HID0] & 0x00600000) {
2106 return 1;
2107 }
2108
2109 return 0;
2110 }
2111
2112 #if defined(TARGET_PPC64)
check_attn_hid0(CPUPPCState * env)2113 static int check_attn_hid0(CPUPPCState *env)
2114 {
2115 if (env->spr[SPR_HID0] & HID0_ENABLE_ATTN) {
2116 return 1;
2117 }
2118
2119 return 0;
2120 }
2121
check_attn_hid0_power9(CPUPPCState * env)2122 static int check_attn_hid0_power9(CPUPPCState *env)
2123 {
2124 if (env->spr[SPR_HID0] & HID0_POWER9_ENABLE_ATTN) {
2125 return 1;
2126 }
2127
2128 return 0;
2129 }
2130 #endif
2131
init_tlbs_emb(CPUPPCState * env)2132 static void init_tlbs_emb(CPUPPCState *env)
2133 {
2134 #ifndef CONFIG_USER_ONLY
2135 env->nb_tlb = 64;
2136 env->nb_ways = 1;
2137 env->tlb_type = TLB_EMB;
2138 #endif
2139 }
2140
init_proc_405(CPUPPCState * env)2141 static void init_proc_405(CPUPPCState *env)
2142 {
2143 register_40x_sprs(env);
2144 register_405_sprs(env);
2145 register_usprgh_sprs(env);
2146
2147 init_tlbs_emb(env);
2148 init_excp_4xx(env);
2149 env->dcache_line_size = 32;
2150 env->icache_line_size = 32;
2151 /* Allocate hardware IRQ controller */
2152 ppc40x_irq_init(env_archcpu(env));
2153
2154 SET_FIT_PERIOD(8, 12, 16, 20);
2155 SET_WDT_PERIOD(16, 20, 24, 28);
2156 }
2157
2158 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
2159 {
2160 DeviceClass *dc = DEVICE_CLASS(oc);
2161 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2162
2163 dc->desc = "PowerPC 405";
2164 pcc->init_proc = init_proc_405;
2165 pcc->check_pow = check_pow_nocheck;
2166 pcc->check_attn = check_attn_none;
2167 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2168 PPC_DCR | PPC_WRTEE |
2169 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2170 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2171 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2172 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2173 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
2174 pcc->msr_mask = (1ull << MSR_WE) |
2175 (1ull << MSR_CE) |
2176 (1ull << MSR_EE) |
2177 (1ull << MSR_PR) |
2178 (1ull << MSR_FP) |
2179 (1ull << MSR_ME) |
2180 (1ull << MSR_DWE) |
2181 (1ull << MSR_DE) |
2182 (1ull << MSR_IR) |
2183 (1ull << MSR_DR);
2184 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
2185 pcc->excp_model = POWERPC_EXCP_40x;
2186 pcc->bus_model = PPC_FLAGS_INPUT_405;
2187 pcc->bfd_mach = bfd_mach_ppc_403;
2188 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2189 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2190 }
2191
init_proc_440EP(CPUPPCState * env)2192 static void init_proc_440EP(CPUPPCState *env)
2193 {
2194 register_BookE_sprs(env, 0x000000000000FFFFULL);
2195 register_440_sprs(env);
2196 register_usprgh_sprs(env);
2197
2198 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2199 SPR_NOACCESS, SPR_NOACCESS,
2200 &spr_read_generic, &spr_write_generic,
2201 0x00000000);
2202 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2203 SPR_NOACCESS, SPR_NOACCESS,
2204 &spr_read_generic, &spr_write_generic,
2205 0x00000000);
2206 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2207 SPR_NOACCESS, SPR_NOACCESS,
2208 &spr_read_generic, &spr_write_generic,
2209 0x00000000);
2210
2211 spr_register(env, SPR_440_CCR1, "CCR1",
2212 SPR_NOACCESS, SPR_NOACCESS,
2213 &spr_read_generic, &spr_write_generic,
2214 0x00000000);
2215
2216 init_tlbs_emb(env);
2217 init_excp_BookE(env);
2218 env->dcache_line_size = 32;
2219 env->icache_line_size = 32;
2220 ppc40x_irq_init(env_archcpu(env));
2221
2222 SET_FIT_PERIOD(12, 16, 20, 24);
2223 SET_WDT_PERIOD(20, 24, 28, 32);
2224 }
2225
2226 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
2227 {
2228 DeviceClass *dc = DEVICE_CLASS(oc);
2229 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2230
2231 dc->desc = "PowerPC 440 EP";
2232 pcc->init_proc = init_proc_440EP;
2233 pcc->check_pow = check_pow_nocheck;
2234 pcc->check_attn = check_attn_none;
2235 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2236 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2237 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2238 PPC_FLOAT_STFIWX |
2239 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2240 PPC_CACHE | PPC_CACHE_ICBI |
2241 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2242 PPC_MEM_TLBSYNC | PPC_MFTB |
2243 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2244 PPC_440_SPEC;
2245 pcc->msr_mask = (1ull << MSR_POW) |
2246 (1ull << MSR_CE) |
2247 (1ull << MSR_EE) |
2248 (1ull << MSR_PR) |
2249 (1ull << MSR_FP) |
2250 (1ull << MSR_ME) |
2251 (1ull << MSR_FE0) |
2252 (1ull << MSR_DWE) |
2253 (1ull << MSR_DE) |
2254 (1ull << MSR_FE1) |
2255 (1ull << MSR_IR) |
2256 (1ull << MSR_DR);
2257 pcc->mmu_model = POWERPC_MMU_BOOKE;
2258 pcc->excp_model = POWERPC_EXCP_BOOKE;
2259 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2260 pcc->bfd_mach = bfd_mach_ppc_403;
2261 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2262 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2263 }
2264
2265 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
2266 {
2267 DeviceClass *dc = DEVICE_CLASS(oc);
2268 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2269
2270 dc->desc = "PowerPC 460 EX";
2271 pcc->init_proc = init_proc_440EP;
2272 pcc->check_pow = check_pow_nocheck;
2273 pcc->check_attn = check_attn_none;
2274 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2275 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2276 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2277 PPC_FLOAT_STFIWX |
2278 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
2279 PPC_CACHE | PPC_CACHE_ICBI |
2280 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2281 PPC_MEM_TLBSYNC | PPC_MFTB |
2282 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2283 PPC_440_SPEC;
2284 pcc->msr_mask = (1ull << MSR_POW) |
2285 (1ull << MSR_CE) |
2286 (1ull << MSR_EE) |
2287 (1ull << MSR_PR) |
2288 (1ull << MSR_FP) |
2289 (1ull << MSR_ME) |
2290 (1ull << MSR_FE0) |
2291 (1ull << MSR_DWE) |
2292 (1ull << MSR_DE) |
2293 (1ull << MSR_FE1) |
2294 (1ull << MSR_IR) |
2295 (1ull << MSR_DR);
2296 pcc->mmu_model = POWERPC_MMU_BOOKE;
2297 pcc->excp_model = POWERPC_EXCP_BOOKE;
2298 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2299 pcc->bfd_mach = bfd_mach_ppc_403;
2300 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2301 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2302 }
2303
init_proc_440GP(CPUPPCState * env)2304 static void init_proc_440GP(CPUPPCState *env)
2305 {
2306 register_BookE_sprs(env, 0x000000000000FFFFULL);
2307 register_440_sprs(env);
2308 register_usprgh_sprs(env);
2309
2310 init_tlbs_emb(env);
2311 init_excp_BookE(env);
2312 env->dcache_line_size = 32;
2313 env->icache_line_size = 32;
2314 /* XXX: TODO: allocate internal IRQ controller */
2315
2316 SET_FIT_PERIOD(12, 16, 20, 24);
2317 SET_WDT_PERIOD(20, 24, 28, 32);
2318 }
2319
2320 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
2321 {
2322 DeviceClass *dc = DEVICE_CLASS(oc);
2323 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2324
2325 dc->desc = "PowerPC 440 GP";
2326 pcc->init_proc = init_proc_440GP;
2327 pcc->check_pow = check_pow_nocheck;
2328 pcc->check_attn = check_attn_none;
2329 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2330 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
2331 PPC_CACHE | PPC_CACHE_ICBI |
2332 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2333 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
2334 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2335 PPC_440_SPEC;
2336 pcc->msr_mask = (1ull << MSR_POW) |
2337 (1ull << MSR_CE) |
2338 (1ull << MSR_EE) |
2339 (1ull << MSR_PR) |
2340 (1ull << MSR_FP) |
2341 (1ull << MSR_ME) |
2342 (1ull << MSR_FE0) |
2343 (1ull << MSR_DWE) |
2344 (1ull << MSR_DE) |
2345 (1ull << MSR_FE1) |
2346 (1ull << MSR_IR) |
2347 (1ull << MSR_DR);
2348 pcc->mmu_model = POWERPC_MMU_BOOKE;
2349 pcc->excp_model = POWERPC_EXCP_BOOKE;
2350 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2351 pcc->bfd_mach = bfd_mach_ppc_403;
2352 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2353 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2354 }
2355
init_proc_440x5(CPUPPCState * env)2356 static void init_proc_440x5(CPUPPCState *env)
2357 {
2358 register_BookE_sprs(env, 0x000000000000FFFFULL);
2359 register_440_sprs(env);
2360 register_usprgh_sprs(env);
2361
2362 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2363 SPR_NOACCESS, SPR_NOACCESS,
2364 &spr_read_generic, &spr_write_generic,
2365 0x00000000);
2366 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2367 SPR_NOACCESS, SPR_NOACCESS,
2368 &spr_read_generic, &spr_write_generic,
2369 0x00000000);
2370 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2371 SPR_NOACCESS, SPR_NOACCESS,
2372 &spr_read_generic, &spr_write_generic,
2373 0x00000000);
2374
2375 spr_register(env, SPR_440_CCR1, "CCR1",
2376 SPR_NOACCESS, SPR_NOACCESS,
2377 &spr_read_generic, &spr_write_generic,
2378 0x00000000);
2379
2380 init_tlbs_emb(env);
2381 init_excp_BookE(env);
2382 env->dcache_line_size = 32;
2383 env->icache_line_size = 32;
2384 ppc40x_irq_init(env_archcpu(env));
2385
2386 SET_FIT_PERIOD(12, 16, 20, 24);
2387 SET_WDT_PERIOD(20, 24, 28, 32);
2388 }
2389
2390 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
2391 {
2392 DeviceClass *dc = DEVICE_CLASS(oc);
2393 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2394
2395 dc->desc = "PowerPC 440x5";
2396 pcc->init_proc = init_proc_440x5;
2397 pcc->check_pow = check_pow_nocheck;
2398 pcc->check_attn = check_attn_none;
2399 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2400 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2401 PPC_CACHE | PPC_CACHE_ICBI |
2402 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2403 PPC_MEM_TLBSYNC | PPC_MFTB |
2404 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2405 PPC_440_SPEC;
2406 pcc->msr_mask = (1ull << MSR_POW) |
2407 (1ull << MSR_CE) |
2408 (1ull << MSR_EE) |
2409 (1ull << MSR_PR) |
2410 (1ull << MSR_FP) |
2411 (1ull << MSR_ME) |
2412 (1ull << MSR_FE0) |
2413 (1ull << MSR_DWE) |
2414 (1ull << MSR_DE) |
2415 (1ull << MSR_FE1) |
2416 (1ull << MSR_IR) |
2417 (1ull << MSR_DR);
2418 pcc->mmu_model = POWERPC_MMU_BOOKE;
2419 pcc->excp_model = POWERPC_EXCP_BOOKE;
2420 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2421 pcc->bfd_mach = bfd_mach_ppc_403;
2422 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2423 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2424 }
2425
2426 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
2427 {
2428 DeviceClass *dc = DEVICE_CLASS(oc);
2429 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2430
2431 dc->desc = "PowerPC 440x5 with double precision FPU";
2432 pcc->init_proc = init_proc_440x5;
2433 pcc->check_pow = check_pow_nocheck;
2434 pcc->check_attn = check_attn_none;
2435 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2436 PPC_FLOAT | PPC_FLOAT_FSQRT |
2437 PPC_FLOAT_STFIWX |
2438 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2439 PPC_CACHE | PPC_CACHE_ICBI |
2440 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2441 PPC_MEM_TLBSYNC | PPC_MFTB |
2442 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2443 PPC_440_SPEC;
2444 pcc->insns_flags2 = PPC2_FP_CVT_S64;
2445 pcc->msr_mask = (1ull << MSR_POW) |
2446 (1ull << MSR_CE) |
2447 (1ull << MSR_EE) |
2448 (1ull << MSR_PR) |
2449 (1ull << MSR_FP) |
2450 (1ull << MSR_ME) |
2451 (1ull << MSR_FE0) |
2452 (1ull << MSR_DWE) |
2453 (1ull << MSR_DE) |
2454 (1ull << MSR_FE1) |
2455 (1ull << MSR_IR) |
2456 (1ull << MSR_DR);
2457 pcc->mmu_model = POWERPC_MMU_BOOKE;
2458 pcc->excp_model = POWERPC_EXCP_BOOKE;
2459 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2460 pcc->bfd_mach = bfd_mach_ppc_403;
2461 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2462 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2463 }
2464
init_proc_MPC5xx(CPUPPCState * env)2465 static void init_proc_MPC5xx(CPUPPCState *env)
2466 {
2467 register_5xx_8xx_sprs(env);
2468 register_5xx_sprs(env);
2469 init_excp_MPC5xx(env);
2470 env->dcache_line_size = 32;
2471 env->icache_line_size = 32;
2472 /* XXX: TODO: allocate internal IRQ controller */
2473 }
2474
POWERPC_FAMILY(MPC5xx)2475 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
2476 {
2477 DeviceClass *dc = DEVICE_CLASS(oc);
2478 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2479
2480 dc->desc = "Freescale 5xx cores (aka RCPU)";
2481 pcc->init_proc = init_proc_MPC5xx;
2482 pcc->check_pow = check_pow_none;
2483 pcc->check_attn = check_attn_none;
2484 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2485 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2486 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
2487 PPC_MFTB;
2488 pcc->msr_mask = (1ull << MSR_ILE) |
2489 (1ull << MSR_EE) |
2490 (1ull << MSR_PR) |
2491 (1ull << MSR_FP) |
2492 (1ull << MSR_ME) |
2493 (1ull << MSR_FE0) |
2494 (1ull << MSR_SE) |
2495 (1ull << MSR_DE) |
2496 (1ull << MSR_FE1) |
2497 (1ull << MSR_EP) |
2498 (1ull << MSR_RI) |
2499 (1ull << MSR_LE);
2500 pcc->mmu_model = POWERPC_MMU_REAL;
2501 pcc->excp_model = POWERPC_EXCP_6xx;
2502 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2503 pcc->bfd_mach = bfd_mach_ppc_505;
2504 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2505 POWERPC_FLAG_BUS_CLK;
2506 }
2507
init_proc_MPC8xx(CPUPPCState * env)2508 static void init_proc_MPC8xx(CPUPPCState *env)
2509 {
2510 register_5xx_8xx_sprs(env);
2511 register_8xx_sprs(env);
2512 init_excp_MPC8xx(env);
2513 env->dcache_line_size = 32;
2514 env->icache_line_size = 32;
2515 /* XXX: TODO: allocate internal IRQ controller */
2516 }
2517
POWERPC_FAMILY(MPC8xx)2518 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
2519 {
2520 DeviceClass *dc = DEVICE_CLASS(oc);
2521 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2522
2523 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
2524 pcc->init_proc = init_proc_MPC8xx;
2525 pcc->check_pow = check_pow_none;
2526 pcc->check_attn = check_attn_none;
2527 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2528 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2529 PPC_CACHE_ICBI | PPC_MFTB;
2530 pcc->msr_mask = (1ull << MSR_ILE) |
2531 (1ull << MSR_EE) |
2532 (1ull << MSR_PR) |
2533 (1ull << MSR_FP) |
2534 (1ull << MSR_ME) |
2535 (1ull << MSR_SE) |
2536 (1ull << MSR_DE) |
2537 (1ull << MSR_EP) |
2538 (1ull << MSR_IR) |
2539 (1ull << MSR_DR) |
2540 (1ull << MSR_RI) |
2541 (1ull << MSR_LE);
2542 pcc->mmu_model = POWERPC_MMU_MPC8xx;
2543 pcc->excp_model = POWERPC_EXCP_6xx;
2544 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2545 pcc->bfd_mach = bfd_mach_ppc_860;
2546 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2547 POWERPC_FLAG_BUS_CLK;
2548 }
2549
2550 /* Freescale 82xx cores (aka PowerQUICC-II) */
2551
init_proc_G2(CPUPPCState * env)2552 static void init_proc_G2(CPUPPCState *env)
2553 {
2554 register_non_embedded_sprs(env);
2555 register_sdr1_sprs(env);
2556 register_G2_sprs(env);
2557
2558 /* Memory management */
2559 register_low_BATs(env);
2560 register_high_BATs(env);
2561 register_6xx_7xx_soft_tlb(env, 64, 2);
2562 init_excp_G2(env);
2563 env->dcache_line_size = 32;
2564 env->icache_line_size = 32;
2565 /* Allocate hardware IRQ controller */
2566 ppc6xx_irq_init(env_archcpu(env));
2567 }
2568
POWERPC_FAMILY(G2)2569 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
2570 {
2571 DeviceClass *dc = DEVICE_CLASS(oc);
2572 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2573
2574 dc->desc = "PowerPC G2";
2575 pcc->init_proc = init_proc_G2;
2576 pcc->check_pow = check_pow_hid0;
2577 pcc->check_attn = check_attn_none;
2578 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2579 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
2580 PPC_FLOAT_STFIWX |
2581 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
2582 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2583 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
2584 PPC_SEGMENT | PPC_EXTERN;
2585 pcc->msr_mask = (1ull << MSR_POW) |
2586 (1ull << MSR_TGPR) |
2587 (1ull << MSR_EE) |
2588 (1ull << MSR_PR) |
2589 (1ull << MSR_FP) |
2590 (1ull << MSR_ME) |
2591 (1ull << MSR_FE0) |
2592 (1ull << MSR_SE) |
2593 (1ull << MSR_DE) |
2594 (1ull << MSR_FE1) |
2595 (1ull << MSR_AL) |
2596 (1ull << MSR_EP) |
2597 (1ull << MSR_IR) |
2598 (1ull << MSR_DR) |
2599 (1ull << MSR_RI);
2600 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
2601 pcc->excp_model = POWERPC_EXCP_6xx;
2602 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
2603 pcc->bfd_mach = bfd_mach_ppc_ec603e;
2604 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
2605 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
2606 }
2607
POWERPC_FAMILY(G2LE)2608 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
2609 {
2610 DeviceClass *dc = DEVICE_CLASS(oc);
2611 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2612
2613 dc->desc = "PowerPC G2LE";
2614 pcc->init_proc = init_proc_G2;
2615 pcc->check_pow = check_pow_hid0;
2616 pcc->check_attn = check_attn_none;
2617 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2618 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
2619 PPC_FLOAT_STFIWX |
2620 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
2621 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2622 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
2623 PPC_SEGMENT | PPC_EXTERN;
2624 pcc->msr_mask = (1ull << MSR_POW) |
2625 (1ull << MSR_TGPR) |
2626 (1ull << MSR_ILE) |
2627 (1ull << MSR_EE) |
2628 (1ull << MSR_PR) |
2629 (1ull << MSR_FP) |
2630 (1ull << MSR_ME) |
2631 (1ull << MSR_FE0) |
2632 (1ull << MSR_SE) |
2633 (1ull << MSR_DE) |
2634 (1ull << MSR_FE1) |
2635 (1ull << MSR_AL) |
2636 (1ull << MSR_EP) |
2637 (1ull << MSR_IR) |
2638 (1ull << MSR_DR) |
2639 (1ull << MSR_RI) |
2640 (1ull << MSR_LE);
2641 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
2642 pcc->excp_model = POWERPC_EXCP_6xx;
2643 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
2644 pcc->bfd_mach = bfd_mach_ppc_ec603e;
2645 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
2646 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
2647 }
2648
init_proc_e200(CPUPPCState * env)2649 static void init_proc_e200(CPUPPCState *env)
2650 {
2651 register_BookE_sprs(env, 0x000000070000FFFFULL);
2652
2653 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
2654 &spr_read_spefscr, &spr_write_spefscr,
2655 &spr_read_spefscr, &spr_write_spefscr,
2656 0x00000000);
2657 /* Memory management */
2658 register_BookE206_sprs(env, 0x0000005D, NULL, 0);
2659 register_usprgh_sprs(env);
2660
2661 spr_register(env, SPR_HID0, "HID0",
2662 SPR_NOACCESS, SPR_NOACCESS,
2663 &spr_read_generic, &spr_write_generic,
2664 0x00000000);
2665
2666 spr_register(env, SPR_HID1, "HID1",
2667 SPR_NOACCESS, SPR_NOACCESS,
2668 &spr_read_generic, &spr_write_generic,
2669 0x00000000);
2670
2671 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
2672 SPR_NOACCESS, SPR_NOACCESS,
2673 &spr_read_generic, &spr_write_generic,
2674 0x00000000);
2675
2676 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
2677 SPR_NOACCESS, SPR_NOACCESS,
2678 &spr_read_generic, &spr_write_generic,
2679 0x00000000);
2680
2681 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
2682 SPR_NOACCESS, SPR_NOACCESS,
2683 &spr_read_generic, &spr_write_generic,
2684 0x00000000);
2685
2686 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
2687 SPR_NOACCESS, SPR_NOACCESS,
2688 &spr_read_generic, &spr_write_generic,
2689 0x00000000);
2690
2691 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
2692 SPR_NOACCESS, SPR_NOACCESS,
2693 &spr_read_generic, &spr_write_generic,
2694 0x00000000);
2695
2696 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
2697 &spr_read_generic, SPR_NOACCESS,
2698 &spr_read_generic, SPR_NOACCESS,
2699 0x00000000);
2700
2701 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
2702 SPR_NOACCESS, SPR_NOACCESS,
2703 &spr_read_generic, &spr_write_generic,
2704 0x00000000);
2705
2706 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
2707 SPR_NOACCESS, SPR_NOACCESS,
2708 &spr_read_generic, &spr_write_generic,
2709 0x00000000);
2710
2711 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
2712 SPR_NOACCESS, SPR_NOACCESS,
2713 &spr_read_generic, &spr_write_generic,
2714 0x00000000);
2715
2716 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
2717 SPR_NOACCESS, SPR_NOACCESS,
2718 &spr_read_generic, &spr_write_generic,
2719 0x00000000);
2720
2721 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
2722 SPR_NOACCESS, SPR_NOACCESS,
2723 &spr_read_generic, &spr_write_generic,
2724 0x00000000);
2725
2726 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
2727 SPR_NOACCESS, SPR_NOACCESS,
2728 &spr_read_generic, &spr_write_generic,
2729 0x00000000);
2730
2731 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
2732 SPR_NOACCESS, SPR_NOACCESS,
2733 &spr_read_generic, &spr_write_generic,
2734 0x00000000); /* TOFIX */
2735
2736 init_tlbs_emb(env);
2737 init_excp_e200(env, 0xFFFF0000UL);
2738 env->dcache_line_size = 32;
2739 env->icache_line_size = 32;
2740 /* XXX: TODO: allocate internal IRQ controller */
2741 }
2742
POWERPC_FAMILY(e200)2743 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
2744 {
2745 DeviceClass *dc = DEVICE_CLASS(oc);
2746 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2747
2748 dc->desc = "e200 core";
2749 pcc->init_proc = init_proc_e200;
2750 pcc->check_pow = check_pow_hid0;
2751 pcc->check_attn = check_attn_none;
2752 /*
2753 * XXX: unimplemented instructions:
2754 * dcblc
2755 * dcbtlst
2756 * dcbtstls
2757 * icblc
2758 * icbtls
2759 * tlbivax
2760 * all SPE multiply-accumulate instructions
2761 */
2762 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
2763 PPC_SPE | PPC_SPE_SINGLE |
2764 PPC_WRTEE | PPC_RFDI |
2765 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
2766 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2767 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
2768 PPC_BOOKE;
2769 pcc->msr_mask = (1ull << MSR_UCLE) |
2770 (1ull << MSR_SPE) |
2771 (1ull << MSR_POW) |
2772 (1ull << MSR_CE) |
2773 (1ull << MSR_EE) |
2774 (1ull << MSR_PR) |
2775 (1ull << MSR_FP) |
2776 (1ull << MSR_ME) |
2777 (1ull << MSR_FE0) |
2778 (1ull << MSR_DWE) |
2779 (1ull << MSR_DE) |
2780 (1ull << MSR_FE1) |
2781 (1ull << MSR_IR) |
2782 (1ull << MSR_DR);
2783 pcc->mmu_model = POWERPC_MMU_BOOKE206;
2784 pcc->excp_model = POWERPC_EXCP_BOOKE;
2785 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2786 pcc->bfd_mach = bfd_mach_ppc_860;
2787 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
2788 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
2789 POWERPC_FLAG_BUS_CLK;
2790 }
2791
2792 enum fsl_e500_version {
2793 fsl_e500v1,
2794 fsl_e500v2,
2795 fsl_e500mc,
2796 fsl_e5500,
2797 fsl_e6500,
2798 };
2799
init_proc_e500(CPUPPCState * env,int version)2800 static void init_proc_e500(CPUPPCState *env, int version)
2801 {
2802 uint32_t tlbncfg[2];
2803 uint64_t ivor_mask;
2804 uint64_t ivpr_mask = 0xFFFF0000ULL;
2805 uint32_t l1cfg0 = 0x3800 /* 8 ways */
2806 | 0x0020; /* 32 kb */
2807 uint32_t l1cfg1 = 0x3800 /* 8 ways */
2808 | 0x0020; /* 32 kb */
2809 uint32_t mmucfg = 0;
2810 #if !defined(CONFIG_USER_ONLY)
2811 int i;
2812 #endif
2813
2814 /*
2815 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
2816 * complain when accessing them.
2817 * register_BookE_sprs(env, 0x0000000F0000FD7FULL);
2818 */
2819 switch (version) {
2820 case fsl_e500v1:
2821 case fsl_e500v2:
2822 default:
2823 ivor_mask = 0x0000000F0000FFFFULL;
2824 break;
2825 case fsl_e500mc:
2826 case fsl_e5500:
2827 ivor_mask = 0x000003FE0000FFFFULL;
2828 break;
2829 case fsl_e6500:
2830 ivor_mask = 0x000003FF0000FFFFULL;
2831 break;
2832 }
2833 register_BookE_sprs(env, ivor_mask);
2834
2835 spr_register(env, SPR_USPRG3, "USPRG3",
2836 &spr_read_ureg, SPR_NOACCESS,
2837 &spr_read_ureg, SPR_NOACCESS,
2838 0x00000000);
2839
2840 /* Processor identification */
2841 spr_register(env, SPR_BOOKE_PIR, "PIR",
2842 SPR_NOACCESS, SPR_NOACCESS,
2843 &spr_read_generic, &spr_write_pir,
2844 0x00000000);
2845
2846 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
2847 &spr_read_spefscr, &spr_write_spefscr,
2848 &spr_read_spefscr, &spr_write_spefscr,
2849 0x00000000);
2850 #if !defined(CONFIG_USER_ONLY)
2851 /* Memory management */
2852 env->nb_pids = 3;
2853 env->nb_ways = 2;
2854 switch (version) {
2855 case fsl_e500v1:
2856 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
2857 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
2858 break;
2859 case fsl_e500v2:
2860 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
2861 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
2862 break;
2863 case fsl_e500mc:
2864 case fsl_e5500:
2865 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
2866 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
2867 break;
2868 case fsl_e6500:
2869 mmucfg = 0x6510B45;
2870 env->nb_pids = 1;
2871 tlbncfg[0] = 0x08052400;
2872 tlbncfg[1] = 0x40028040;
2873 break;
2874 default:
2875 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
2876 env->spr[SPR_PVR]);
2877 }
2878 #endif
2879 /* Cache sizes */
2880 switch (version) {
2881 case fsl_e500v1:
2882 case fsl_e500v2:
2883 env->dcache_line_size = 32;
2884 env->icache_line_size = 32;
2885 break;
2886 case fsl_e500mc:
2887 case fsl_e5500:
2888 env->dcache_line_size = 64;
2889 env->icache_line_size = 64;
2890 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
2891 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
2892 break;
2893 case fsl_e6500:
2894 env->dcache_line_size = 32;
2895 env->icache_line_size = 32;
2896 l1cfg0 |= 0x0F83820;
2897 l1cfg1 |= 0x0B83820;
2898 break;
2899 default:
2900 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
2901 env->spr[SPR_PVR]);
2902 }
2903 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
2904 register_usprgh_sprs(env);
2905
2906 spr_register(env, SPR_HID0, "HID0",
2907 SPR_NOACCESS, SPR_NOACCESS,
2908 &spr_read_generic, &spr_write_generic,
2909 0x00000000);
2910
2911 spr_register(env, SPR_HID1, "HID1",
2912 SPR_NOACCESS, SPR_NOACCESS,
2913 &spr_read_generic, &spr_write_generic,
2914 0x00000000);
2915
2916 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
2917 SPR_NOACCESS, SPR_NOACCESS,
2918 &spr_read_generic, &spr_write_generic,
2919 0x00000000);
2920
2921 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
2922 SPR_NOACCESS, SPR_NOACCESS,
2923 &spr_read_generic, &spr_write_generic,
2924 0x00000000);
2925
2926 spr_register(env, SPR_Exxx_MCAR, "MCAR",
2927 SPR_NOACCESS, SPR_NOACCESS,
2928 &spr_read_generic, &spr_write_generic,
2929 0x00000000);
2930
2931 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2932 SPR_NOACCESS, SPR_NOACCESS,
2933 &spr_read_generic, &spr_write_generic,
2934 0x00000000);
2935
2936 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
2937 SPR_NOACCESS, SPR_NOACCESS,
2938 &spr_read_generic, &spr_write_generic,
2939 0x00000000);
2940
2941 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
2942 SPR_NOACCESS, SPR_NOACCESS,
2943 &spr_read_generic, &spr_write_generic,
2944 0x00000000);
2945
2946 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
2947 &spr_read_generic, SPR_NOACCESS,
2948 &spr_read_generic, SPR_NOACCESS,
2949 l1cfg0);
2950 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
2951 &spr_read_generic, SPR_NOACCESS,
2952 &spr_read_generic, SPR_NOACCESS,
2953 l1cfg1);
2954 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
2955 SPR_NOACCESS, SPR_NOACCESS,
2956 &spr_read_generic, &spr_write_e500_l1csr0,
2957 0x00000000);
2958 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
2959 SPR_NOACCESS, SPR_NOACCESS,
2960 &spr_read_generic, &spr_write_e500_l1csr1,
2961 0x00000000);
2962 if (version != fsl_e500v1 && version != fsl_e500v2) {
2963 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0",
2964 SPR_NOACCESS, SPR_NOACCESS,
2965 &spr_read_generic, &spr_write_e500_l2csr0,
2966 0x00000000);
2967 }
2968 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2969 SPR_NOACCESS, SPR_NOACCESS,
2970 &spr_read_generic, &spr_write_generic,
2971 0x00000000);
2972 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2973 SPR_NOACCESS, SPR_NOACCESS,
2974 &spr_read_generic, &spr_write_generic,
2975 0x00000000);
2976 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
2977 SPR_NOACCESS, SPR_NOACCESS,
2978 &spr_read_generic, &spr_write_booke206_mmucsr0,
2979 0x00000000);
2980 spr_register(env, SPR_BOOKE_EPR, "EPR",
2981 SPR_NOACCESS, SPR_NOACCESS,
2982 &spr_read_generic, SPR_NOACCESS,
2983 0x00000000);
2984 /* XXX better abstract into Emb.xxx features */
2985 if ((version == fsl_e5500) || (version == fsl_e6500)) {
2986 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
2987 SPR_NOACCESS, SPR_NOACCESS,
2988 &spr_read_generic, &spr_write_generic,
2989 0x00000000);
2990 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
2991 SPR_NOACCESS, SPR_NOACCESS,
2992 &spr_read_mas73, &spr_write_mas73,
2993 0x00000000);
2994 ivpr_mask = (target_ulong)~0xFFFFULL;
2995 }
2996
2997 if (version == fsl_e6500) {
2998 /* Thread identification */
2999 spr_register(env, SPR_TIR, "TIR",
3000 SPR_NOACCESS, SPR_NOACCESS,
3001 &spr_read_generic, SPR_NOACCESS,
3002 0x00000000);
3003 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
3004 SPR_NOACCESS, SPR_NOACCESS,
3005 &spr_read_generic, SPR_NOACCESS,
3006 0x00000004);
3007 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
3008 SPR_NOACCESS, SPR_NOACCESS,
3009 &spr_read_generic, SPR_NOACCESS,
3010 0x7FFFFFFC);
3011 }
3012
3013 #if !defined(CONFIG_USER_ONLY)
3014 env->nb_tlb = 0;
3015 env->tlb_type = TLB_MAS;
3016 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
3017 env->nb_tlb += booke206_tlb_size(env, i);
3018 }
3019 #endif
3020
3021 init_excp_e200(env, ivpr_mask);
3022 /* Allocate hardware IRQ controller */
3023 ppce500_irq_init(env_archcpu(env));
3024 }
3025
init_proc_e500v1(CPUPPCState * env)3026 static void init_proc_e500v1(CPUPPCState *env)
3027 {
3028 init_proc_e500(env, fsl_e500v1);
3029 }
3030
POWERPC_FAMILY(e500v1)3031 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
3032 {
3033 DeviceClass *dc = DEVICE_CLASS(oc);
3034 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3035
3036 dc->desc = "e500v1 core";
3037 pcc->init_proc = init_proc_e500v1;
3038 pcc->check_pow = check_pow_hid0;
3039 pcc->check_attn = check_attn_none;
3040 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3041 PPC_SPE | PPC_SPE_SINGLE |
3042 PPC_WRTEE | PPC_RFDI |
3043 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3044 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3045 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3046 pcc->insns_flags2 = PPC2_BOOKE206;
3047 pcc->msr_mask = (1ull << MSR_UCLE) |
3048 (1ull << MSR_SPE) |
3049 (1ull << MSR_POW) |
3050 (1ull << MSR_CE) |
3051 (1ull << MSR_EE) |
3052 (1ull << MSR_PR) |
3053 (1ull << MSR_FP) |
3054 (1ull << MSR_ME) |
3055 (1ull << MSR_FE0) |
3056 (1ull << MSR_DWE) |
3057 (1ull << MSR_DE) |
3058 (1ull << MSR_FE1) |
3059 (1ull << MSR_IR) |
3060 (1ull << MSR_DR);
3061 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3062 pcc->excp_model = POWERPC_EXCP_BOOKE;
3063 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3064 pcc->bfd_mach = bfd_mach_ppc_860;
3065 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3066 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3067 POWERPC_FLAG_BUS_CLK;
3068 }
3069
init_proc_e500v2(CPUPPCState * env)3070 static void init_proc_e500v2(CPUPPCState *env)
3071 {
3072 init_proc_e500(env, fsl_e500v2);
3073 }
3074
POWERPC_FAMILY(e500v2)3075 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
3076 {
3077 DeviceClass *dc = DEVICE_CLASS(oc);
3078 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3079
3080 dc->desc = "e500v2 core";
3081 pcc->init_proc = init_proc_e500v2;
3082 pcc->check_pow = check_pow_hid0;
3083 pcc->check_attn = check_attn_none;
3084 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3085 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
3086 PPC_WRTEE | PPC_RFDI |
3087 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3088 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3089 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3090 pcc->insns_flags2 = PPC2_BOOKE206;
3091 pcc->msr_mask = (1ull << MSR_UCLE) |
3092 (1ull << MSR_SPE) |
3093 (1ull << MSR_POW) |
3094 (1ull << MSR_CE) |
3095 (1ull << MSR_EE) |
3096 (1ull << MSR_PR) |
3097 (1ull << MSR_FP) |
3098 (1ull << MSR_ME) |
3099 (1ull << MSR_FE0) |
3100 (1ull << MSR_DWE) |
3101 (1ull << MSR_DE) |
3102 (1ull << MSR_FE1) |
3103 (1ull << MSR_IR) |
3104 (1ull << MSR_DR);
3105 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3106 pcc->excp_model = POWERPC_EXCP_BOOKE;
3107 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3108 pcc->bfd_mach = bfd_mach_ppc_860;
3109 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3110 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3111 POWERPC_FLAG_BUS_CLK;
3112 }
3113
init_proc_e500mc(CPUPPCState * env)3114 static void init_proc_e500mc(CPUPPCState *env)
3115 {
3116 init_proc_e500(env, fsl_e500mc);
3117 }
3118
POWERPC_FAMILY(e500mc)3119 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
3120 {
3121 DeviceClass *dc = DEVICE_CLASS(oc);
3122 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3123
3124 dc->desc = "e500mc core";
3125 pcc->init_proc = init_proc_e500mc;
3126 pcc->check_pow = check_pow_none;
3127 pcc->check_attn = check_attn_none;
3128 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3129 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3130 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3131 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3132 PPC_FLOAT | PPC_FLOAT_FRES |
3133 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3134 PPC_FLOAT_STFIWX | PPC_WAIT |
3135 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3136 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
3137 pcc->msr_mask = (1ull << MSR_GS) |
3138 (1ull << MSR_UCLE) |
3139 (1ull << MSR_CE) |
3140 (1ull << MSR_EE) |
3141 (1ull << MSR_PR) |
3142 (1ull << MSR_FP) |
3143 (1ull << MSR_ME) |
3144 (1ull << MSR_FE0) |
3145 (1ull << MSR_DE) |
3146 (1ull << MSR_FE1) |
3147 (1ull << MSR_IR) |
3148 (1ull << MSR_DR) |
3149 (1ull << MSR_PX) |
3150 (1ull << MSR_RI);
3151 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3152 pcc->excp_model = POWERPC_EXCP_BOOKE;
3153 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3154 /* FIXME: figure out the correct flag for e500mc */
3155 pcc->bfd_mach = bfd_mach_ppc_e500;
3156 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3157 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3158 }
3159
3160 #ifdef TARGET_PPC64
init_proc_e5500(CPUPPCState * env)3161 static void init_proc_e5500(CPUPPCState *env)
3162 {
3163 init_proc_e500(env, fsl_e5500);
3164 }
3165
POWERPC_FAMILY(e5500)3166 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
3167 {
3168 DeviceClass *dc = DEVICE_CLASS(oc);
3169 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3170
3171 dc->desc = "e5500 core";
3172 pcc->init_proc = init_proc_e5500;
3173 pcc->check_pow = check_pow_none;
3174 pcc->check_attn = check_attn_none;
3175 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3176 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3177 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3178 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3179 PPC_FLOAT | PPC_FLOAT_FRES |
3180 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3181 PPC_FLOAT_STFIWX | PPC_WAIT |
3182 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3183 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
3184 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3185 PPC2_FP_CVT_S64;
3186 pcc->msr_mask = (1ull << MSR_CM) |
3187 (1ull << MSR_GS) |
3188 (1ull << MSR_UCLE) |
3189 (1ull << MSR_CE) |
3190 (1ull << MSR_EE) |
3191 (1ull << MSR_PR) |
3192 (1ull << MSR_FP) |
3193 (1ull << MSR_ME) |
3194 (1ull << MSR_FE0) |
3195 (1ull << MSR_DE) |
3196 (1ull << MSR_FE1) |
3197 (1ull << MSR_IR) |
3198 (1ull << MSR_DR) |
3199 (1ull << MSR_PX) |
3200 (1ull << MSR_RI);
3201 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3202 pcc->excp_model = POWERPC_EXCP_BOOKE;
3203 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3204 /* FIXME: figure out the correct flag for e5500 */
3205 pcc->bfd_mach = bfd_mach_ppc_e500;
3206 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3207 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3208 }
3209
init_proc_e6500(CPUPPCState * env)3210 static void init_proc_e6500(CPUPPCState *env)
3211 {
3212 init_proc_e500(env, fsl_e6500);
3213 }
3214
POWERPC_FAMILY(e6500)3215 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
3216 {
3217 DeviceClass *dc = DEVICE_CLASS(oc);
3218 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3219
3220 dc->desc = "e6500 core";
3221 pcc->init_proc = init_proc_e6500;
3222 pcc->check_pow = check_pow_none;
3223 pcc->check_attn = check_attn_none;
3224 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3225 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3226 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3227 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3228 PPC_FLOAT | PPC_FLOAT_FRES |
3229 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3230 PPC_FLOAT_STFIWX | PPC_WAIT |
3231 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3232 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
3233 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3234 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
3235 pcc->msr_mask = (1ull << MSR_CM) |
3236 (1ull << MSR_GS) |
3237 (1ull << MSR_UCLE) |
3238 (1ull << MSR_CE) |
3239 (1ull << MSR_EE) |
3240 (1ull << MSR_PR) |
3241 (1ull << MSR_FP) |
3242 (1ull << MSR_ME) |
3243 (1ull << MSR_FE0) |
3244 (1ull << MSR_DE) |
3245 (1ull << MSR_FE1) |
3246 (1ull << MSR_IS) |
3247 (1ull << MSR_DS) |
3248 (1ull << MSR_PX) |
3249 (1ull << MSR_RI) |
3250 (1ull << MSR_VR);
3251 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3252 pcc->excp_model = POWERPC_EXCP_BOOKE;
3253 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3254 pcc->bfd_mach = bfd_mach_ppc_e500;
3255 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3256 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
3257 }
3258
3259 #endif
3260
3261 /* Non-embedded PowerPC */
init_proc_603(CPUPPCState * env)3262 static void init_proc_603(CPUPPCState *env)
3263 {
3264 register_non_embedded_sprs(env);
3265 register_sdr1_sprs(env);
3266 register_603_sprs(env);
3267
3268 /* Memory management */
3269 register_low_BATs(env);
3270 register_6xx_7xx_soft_tlb(env, 64, 2);
3271 init_excp_603(env);
3272 env->dcache_line_size = 32;
3273 env->icache_line_size = 32;
3274 /* Allocate hardware IRQ controller */
3275 ppc6xx_irq_init(env_archcpu(env));
3276 }
3277
3278 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
3279 {
3280 DeviceClass *dc = DEVICE_CLASS(oc);
3281 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3282
3283 dc->desc = "PowerPC 603";
3284 pcc->init_proc = init_proc_603;
3285 pcc->check_pow = check_pow_hid0;
3286 pcc->check_attn = check_attn_none;
3287 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3288 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3289 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3290 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3291 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3292 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3293 PPC_SEGMENT | PPC_EXTERN;
3294 pcc->msr_mask = (1ull << MSR_POW) |
3295 (1ull << MSR_TGPR) |
3296 (1ull << MSR_ILE) |
3297 (1ull << MSR_EE) |
3298 (1ull << MSR_PR) |
3299 (1ull << MSR_FP) |
3300 (1ull << MSR_ME) |
3301 (1ull << MSR_FE0) |
3302 (1ull << MSR_SE) |
3303 (1ull << MSR_DE) |
3304 (1ull << MSR_FE1) |
3305 (1ull << MSR_EP) |
3306 (1ull << MSR_IR) |
3307 (1ull << MSR_DR) |
3308 (1ull << MSR_RI) |
3309 (1ull << MSR_LE);
3310 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3311 pcc->excp_model = POWERPC_EXCP_6xx;
3312 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3313 pcc->bfd_mach = bfd_mach_ppc_603;
3314 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3315 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3316 }
3317
3318 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
3319 {
3320 DeviceClass *dc = DEVICE_CLASS(oc);
3321 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3322
3323 dc->desc = "PowerPC 603e";
3324 pcc->init_proc = init_proc_603;
3325 pcc->check_pow = check_pow_hid0;
3326 pcc->check_attn = check_attn_none;
3327 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3328 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3329 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3330 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3331 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3332 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3333 PPC_SEGMENT | PPC_EXTERN;
3334 pcc->msr_mask = (1ull << MSR_POW) |
3335 (1ull << MSR_TGPR) |
3336 (1ull << MSR_ILE) |
3337 (1ull << MSR_EE) |
3338 (1ull << MSR_PR) |
3339 (1ull << MSR_FP) |
3340 (1ull << MSR_ME) |
3341 (1ull << MSR_FE0) |
3342 (1ull << MSR_SE) |
3343 (1ull << MSR_DE) |
3344 (1ull << MSR_FE1) |
3345 (1ull << MSR_EP) |
3346 (1ull << MSR_IR) |
3347 (1ull << MSR_DR) |
3348 (1ull << MSR_RI) |
3349 (1ull << MSR_LE);
3350 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3351 pcc->excp_model = POWERPC_EXCP_6xx;
3352 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3353 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3354 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3355 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3356 }
3357
init_proc_e300(CPUPPCState * env)3358 static void init_proc_e300(CPUPPCState *env)
3359 {
3360 init_proc_603(env);
3361 register_e300_sprs(env);
3362 }
3363
POWERPC_FAMILY(e300)3364 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
3365 {
3366 DeviceClass *dc = DEVICE_CLASS(oc);
3367 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3368
3369 dc->desc = "e300 core";
3370 pcc->init_proc = init_proc_e300;
3371 pcc->check_pow = check_pow_hid0;
3372 pcc->check_attn = check_attn_none;
3373 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3374 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3375 PPC_FLOAT_STFIWX |
3376 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3377 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3378 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3379 PPC_SEGMENT | PPC_EXTERN;
3380 pcc->msr_mask = (1ull << MSR_POW) |
3381 (1ull << MSR_TGPR) |
3382 (1ull << MSR_ILE) |
3383 (1ull << MSR_EE) |
3384 (1ull << MSR_PR) |
3385 (1ull << MSR_FP) |
3386 (1ull << MSR_ME) |
3387 (1ull << MSR_FE0) |
3388 (1ull << MSR_SE) |
3389 (1ull << MSR_DE) |
3390 (1ull << MSR_FE1) |
3391 (1ull << MSR_AL) |
3392 (1ull << MSR_EP) |
3393 (1ull << MSR_IR) |
3394 (1ull << MSR_DR) |
3395 (1ull << MSR_RI) |
3396 (1ull << MSR_LE);
3397 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3398 pcc->excp_model = POWERPC_EXCP_6xx;
3399 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3400 pcc->bfd_mach = bfd_mach_ppc_603;
3401 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3402 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3403 }
3404
init_proc_604(CPUPPCState * env)3405 static void init_proc_604(CPUPPCState *env)
3406 {
3407 register_non_embedded_sprs(env);
3408 register_sdr1_sprs(env);
3409 register_604_sprs(env);
3410
3411 /* Memory management */
3412 register_low_BATs(env);
3413 init_excp_604(env);
3414 env->dcache_line_size = 32;
3415 env->icache_line_size = 32;
3416 /* Allocate hardware IRQ controller */
3417 ppc6xx_irq_init(env_archcpu(env));
3418 }
3419
3420 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
3421 {
3422 DeviceClass *dc = DEVICE_CLASS(oc);
3423 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3424
3425 dc->desc = "PowerPC 604";
3426 pcc->init_proc = init_proc_604;
3427 pcc->check_pow = check_pow_nocheck;
3428 pcc->check_attn = check_attn_none;
3429 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3430 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3431 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3432 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3433 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3434 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3435 PPC_SEGMENT | PPC_EXTERN;
3436 pcc->msr_mask = (1ull << MSR_POW) |
3437 (1ull << MSR_ILE) |
3438 (1ull << MSR_EE) |
3439 (1ull << MSR_PR) |
3440 (1ull << MSR_FP) |
3441 (1ull << MSR_ME) |
3442 (1ull << MSR_FE0) |
3443 (1ull << MSR_SE) |
3444 (1ull << MSR_DE) |
3445 (1ull << MSR_FE1) |
3446 (1ull << MSR_EP) |
3447 (1ull << MSR_IR) |
3448 (1ull << MSR_DR) |
3449 (1ull << MSR_PMM) |
3450 (1ull << MSR_RI) |
3451 (1ull << MSR_LE);
3452 pcc->mmu_model = POWERPC_MMU_32B;
3453 pcc->excp_model = POWERPC_EXCP_6xx;
3454 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3455 pcc->bfd_mach = bfd_mach_ppc_604;
3456 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3457 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3458 }
3459
init_proc_604E(CPUPPCState * env)3460 static void init_proc_604E(CPUPPCState *env)
3461 {
3462 init_proc_604(env);
3463 register_604e_sprs(env);
3464 }
3465
3466 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
3467 {
3468 DeviceClass *dc = DEVICE_CLASS(oc);
3469 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3470
3471 dc->desc = "PowerPC 604E";
3472 pcc->init_proc = init_proc_604E;
3473 pcc->check_pow = check_pow_nocheck;
3474 pcc->check_attn = check_attn_none;
3475 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3476 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3477 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3478 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3479 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3480 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3481 PPC_SEGMENT | PPC_EXTERN;
3482 pcc->msr_mask = (1ull << MSR_POW) |
3483 (1ull << MSR_ILE) |
3484 (1ull << MSR_EE) |
3485 (1ull << MSR_PR) |
3486 (1ull << MSR_FP) |
3487 (1ull << MSR_ME) |
3488 (1ull << MSR_FE0) |
3489 (1ull << MSR_SE) |
3490 (1ull << MSR_DE) |
3491 (1ull << MSR_FE1) |
3492 (1ull << MSR_EP) |
3493 (1ull << MSR_IR) |
3494 (1ull << MSR_DR) |
3495 (1ull << MSR_PMM) |
3496 (1ull << MSR_RI) |
3497 (1ull << MSR_LE);
3498 pcc->mmu_model = POWERPC_MMU_32B;
3499 pcc->excp_model = POWERPC_EXCP_6xx;
3500 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3501 pcc->bfd_mach = bfd_mach_ppc_604;
3502 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3503 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3504 }
3505
init_proc_740(CPUPPCState * env)3506 static void init_proc_740(CPUPPCState *env)
3507 {
3508 register_non_embedded_sprs(env);
3509 register_sdr1_sprs(env);
3510 register_7xx_sprs(env);
3511 /* Thermal management */
3512 register_thrm_sprs(env);
3513
3514 /* Memory management */
3515 register_low_BATs(env);
3516 init_excp_7x0(env);
3517 env->dcache_line_size = 32;
3518 env->icache_line_size = 32;
3519 /* Allocate hardware IRQ controller */
3520 ppc6xx_irq_init(env_archcpu(env));
3521 }
3522
3523 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
3524 {
3525 DeviceClass *dc = DEVICE_CLASS(oc);
3526 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3527
3528 dc->desc = "PowerPC 740";
3529 pcc->init_proc = init_proc_740;
3530 pcc->check_pow = check_pow_hid0;
3531 pcc->check_attn = check_attn_none;
3532 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3533 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3534 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3535 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3536 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3537 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3538 PPC_SEGMENT | PPC_EXTERN;
3539 pcc->msr_mask = (1ull << MSR_POW) |
3540 (1ull << MSR_ILE) |
3541 (1ull << MSR_EE) |
3542 (1ull << MSR_PR) |
3543 (1ull << MSR_FP) |
3544 (1ull << MSR_ME) |
3545 (1ull << MSR_FE0) |
3546 (1ull << MSR_SE) |
3547 (1ull << MSR_DE) |
3548 (1ull << MSR_FE1) |
3549 (1ull << MSR_EP) |
3550 (1ull << MSR_IR) |
3551 (1ull << MSR_DR) |
3552 (1ull << MSR_PMM) |
3553 (1ull << MSR_RI) |
3554 (1ull << MSR_LE);
3555 pcc->mmu_model = POWERPC_MMU_32B;
3556 pcc->excp_model = POWERPC_EXCP_7xx;
3557 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3558 pcc->bfd_mach = bfd_mach_ppc_750;
3559 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3560 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3561 }
3562
init_proc_750(CPUPPCState * env)3563 static void init_proc_750(CPUPPCState *env)
3564 {
3565 register_non_embedded_sprs(env);
3566 register_sdr1_sprs(env);
3567 register_7xx_sprs(env);
3568
3569 spr_register(env, SPR_L2CR, "L2CR",
3570 SPR_NOACCESS, SPR_NOACCESS,
3571 &spr_read_generic, spr_access_nop,
3572 0x00000000);
3573 /* Thermal management */
3574 register_thrm_sprs(env);
3575
3576 /* Memory management */
3577 register_low_BATs(env);
3578 /*
3579 * XXX: high BATs are also present but are known to be bugged on
3580 * die version 1.x
3581 */
3582 init_excp_7x0(env);
3583 env->dcache_line_size = 32;
3584 env->icache_line_size = 32;
3585 /* Allocate hardware IRQ controller */
3586 ppc6xx_irq_init(env_archcpu(env));
3587 }
3588
3589 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
3590 {
3591 DeviceClass *dc = DEVICE_CLASS(oc);
3592 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3593
3594 dc->desc = "PowerPC 750";
3595 pcc->init_proc = init_proc_750;
3596 pcc->check_pow = check_pow_hid0;
3597 pcc->check_attn = check_attn_none;
3598 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3599 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3600 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3601 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3602 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3603 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3604 PPC_SEGMENT | PPC_EXTERN;
3605 pcc->msr_mask = (1ull << MSR_POW) |
3606 (1ull << MSR_ILE) |
3607 (1ull << MSR_EE) |
3608 (1ull << MSR_PR) |
3609 (1ull << MSR_FP) |
3610 (1ull << MSR_ME) |
3611 (1ull << MSR_FE0) |
3612 (1ull << MSR_SE) |
3613 (1ull << MSR_DE) |
3614 (1ull << MSR_FE1) |
3615 (1ull << MSR_EP) |
3616 (1ull << MSR_IR) |
3617 (1ull << MSR_DR) |
3618 (1ull << MSR_PMM) |
3619 (1ull << MSR_RI) |
3620 (1ull << MSR_LE);
3621 pcc->mmu_model = POWERPC_MMU_32B;
3622 pcc->excp_model = POWERPC_EXCP_7xx;
3623 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3624 pcc->bfd_mach = bfd_mach_ppc_750;
3625 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3626 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3627 }
3628
init_proc_750cl(CPUPPCState * env)3629 static void init_proc_750cl(CPUPPCState *env)
3630 {
3631 register_non_embedded_sprs(env);
3632 register_sdr1_sprs(env);
3633 register_7xx_sprs(env);
3634
3635 spr_register(env, SPR_L2CR, "L2CR",
3636 SPR_NOACCESS, SPR_NOACCESS,
3637 &spr_read_generic, spr_access_nop,
3638 0x00000000);
3639 /* Thermal management */
3640 /* Those registers are fake on 750CL */
3641 spr_register(env, SPR_THRM1, "THRM1",
3642 SPR_NOACCESS, SPR_NOACCESS,
3643 &spr_read_generic, &spr_write_generic,
3644 0x00000000);
3645 spr_register(env, SPR_THRM2, "THRM2",
3646 SPR_NOACCESS, SPR_NOACCESS,
3647 &spr_read_generic, &spr_write_generic,
3648 0x00000000);
3649 spr_register(env, SPR_THRM3, "THRM3",
3650 SPR_NOACCESS, SPR_NOACCESS,
3651 &spr_read_generic, &spr_write_generic,
3652 0x00000000);
3653
3654 spr_register(env, SPR_750_TDCL, "TDCL",
3655 SPR_NOACCESS, SPR_NOACCESS,
3656 &spr_read_generic, &spr_write_generic,
3657 0x00000000);
3658 spr_register(env, SPR_750_TDCH, "TDCH",
3659 SPR_NOACCESS, SPR_NOACCESS,
3660 &spr_read_generic, &spr_write_generic,
3661 0x00000000);
3662 /* DMA */
3663 spr_register(env, SPR_750_WPAR, "WPAR",
3664 SPR_NOACCESS, SPR_NOACCESS,
3665 &spr_read_generic, &spr_write_generic,
3666 0x00000000);
3667 spr_register(env, SPR_750_DMAL, "DMAL",
3668 SPR_NOACCESS, SPR_NOACCESS,
3669 &spr_read_generic, &spr_write_generic,
3670 0x00000000);
3671 spr_register(env, SPR_750_DMAU, "DMAU",
3672 SPR_NOACCESS, SPR_NOACCESS,
3673 &spr_read_generic, &spr_write_generic,
3674 0x00000000);
3675 /* Hardware implementation registers */
3676 spr_register(env, SPR_750CL_HID2, "HID2",
3677 SPR_NOACCESS, SPR_NOACCESS,
3678 &spr_read_generic, &spr_write_generic,
3679 0x00000000);
3680
3681 spr_register(env, SPR_750CL_HID4, "HID4",
3682 SPR_NOACCESS, SPR_NOACCESS,
3683 &spr_read_generic, &spr_write_generic,
3684 0x00000000);
3685 /* Quantization registers */
3686 spr_register(env, SPR_750_GQR0, "GQR0",
3687 SPR_NOACCESS, SPR_NOACCESS,
3688 &spr_read_generic, &spr_write_generic,
3689 0x00000000);
3690
3691 spr_register(env, SPR_750_GQR1, "GQR1",
3692 SPR_NOACCESS, SPR_NOACCESS,
3693 &spr_read_generic, &spr_write_generic,
3694 0x00000000);
3695
3696 spr_register(env, SPR_750_GQR2, "GQR2",
3697 SPR_NOACCESS, SPR_NOACCESS,
3698 &spr_read_generic, &spr_write_generic,
3699 0x00000000);
3700
3701 spr_register(env, SPR_750_GQR3, "GQR3",
3702 SPR_NOACCESS, SPR_NOACCESS,
3703 &spr_read_generic, &spr_write_generic,
3704 0x00000000);
3705
3706 spr_register(env, SPR_750_GQR4, "GQR4",
3707 SPR_NOACCESS, SPR_NOACCESS,
3708 &spr_read_generic, &spr_write_generic,
3709 0x00000000);
3710
3711 spr_register(env, SPR_750_GQR5, "GQR5",
3712 SPR_NOACCESS, SPR_NOACCESS,
3713 &spr_read_generic, &spr_write_generic,
3714 0x00000000);
3715
3716 spr_register(env, SPR_750_GQR6, "GQR6",
3717 SPR_NOACCESS, SPR_NOACCESS,
3718 &spr_read_generic, &spr_write_generic,
3719 0x00000000);
3720
3721 spr_register(env, SPR_750_GQR7, "GQR7",
3722 SPR_NOACCESS, SPR_NOACCESS,
3723 &spr_read_generic, &spr_write_generic,
3724 0x00000000);
3725 /* Memory management */
3726 register_low_BATs(env);
3727 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
3728 register_high_BATs(env);
3729 init_excp_750cl(env);
3730 env->dcache_line_size = 32;
3731 env->icache_line_size = 32;
3732 /* Allocate hardware IRQ controller */
3733 ppc6xx_irq_init(env_archcpu(env));
3734 }
3735
3736 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
3737 {
3738 DeviceClass *dc = DEVICE_CLASS(oc);
3739 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3740
3741 dc->desc = "PowerPC 750 CL";
3742 pcc->init_proc = init_proc_750cl;
3743 pcc->check_pow = check_pow_hid0;
3744 pcc->check_attn = check_attn_none;
3745 /*
3746 * XXX: not implemented:
3747 * cache lock instructions:
3748 * dcbz_l
3749 * floating point paired instructions
3750 * psq_lux
3751 * psq_lx
3752 * psq_stux
3753 * psq_stx
3754 * ps_abs
3755 * ps_add
3756 * ps_cmpo0
3757 * ps_cmpo1
3758 * ps_cmpu0
3759 * ps_cmpu1
3760 * ps_div
3761 * ps_madd
3762 * ps_madds0
3763 * ps_madds1
3764 * ps_merge00
3765 * ps_merge01
3766 * ps_merge10
3767 * ps_merge11
3768 * ps_mr
3769 * ps_msub
3770 * ps_mul
3771 * ps_muls0
3772 * ps_muls1
3773 * ps_nabs
3774 * ps_neg
3775 * ps_nmadd
3776 * ps_nmsub
3777 * ps_res
3778 * ps_rsqrte
3779 * ps_sel
3780 * ps_sub
3781 * ps_sum0
3782 * ps_sum1
3783 */
3784 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3785 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3786 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3787 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3788 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3789 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3790 PPC_SEGMENT | PPC_EXTERN;
3791 pcc->msr_mask = (1ull << MSR_POW) |
3792 (1ull << MSR_ILE) |
3793 (1ull << MSR_EE) |
3794 (1ull << MSR_PR) |
3795 (1ull << MSR_FP) |
3796 (1ull << MSR_ME) |
3797 (1ull << MSR_FE0) |
3798 (1ull << MSR_SE) |
3799 (1ull << MSR_DE) |
3800 (1ull << MSR_FE1) |
3801 (1ull << MSR_EP) |
3802 (1ull << MSR_IR) |
3803 (1ull << MSR_DR) |
3804 (1ull << MSR_PMM) |
3805 (1ull << MSR_RI) |
3806 (1ull << MSR_LE);
3807 pcc->mmu_model = POWERPC_MMU_32B;
3808 pcc->excp_model = POWERPC_EXCP_7xx;
3809 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3810 pcc->bfd_mach = bfd_mach_ppc_750;
3811 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3812 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3813 }
3814
init_proc_750cx(CPUPPCState * env)3815 static void init_proc_750cx(CPUPPCState *env)
3816 {
3817 register_non_embedded_sprs(env);
3818 register_sdr1_sprs(env);
3819 register_7xx_sprs(env);
3820
3821 spr_register(env, SPR_L2CR, "L2CR",
3822 SPR_NOACCESS, SPR_NOACCESS,
3823 &spr_read_generic, spr_access_nop,
3824 0x00000000);
3825 /* Thermal management */
3826 register_thrm_sprs(env);
3827
3828 spr_register(env, SPR_SDA, "SDA",
3829 SPR_NOACCESS, SPR_NOACCESS,
3830 &spr_read_generic, &spr_write_generic,
3831 0x00000000);
3832
3833 /* Memory management */
3834 register_low_BATs(env);
3835 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
3836 register_high_BATs(env);
3837 init_excp_750cx(env);
3838 env->dcache_line_size = 32;
3839 env->icache_line_size = 32;
3840 /* Allocate hardware IRQ controller */
3841 ppc6xx_irq_init(env_archcpu(env));
3842 }
3843
3844 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
3845 {
3846 DeviceClass *dc = DEVICE_CLASS(oc);
3847 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3848
3849 dc->desc = "PowerPC 750CX";
3850 pcc->init_proc = init_proc_750cx;
3851 pcc->check_pow = check_pow_hid0;
3852 pcc->check_attn = check_attn_none;
3853 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3854 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3855 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3856 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3857 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3858 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3859 PPC_SEGMENT | PPC_EXTERN;
3860 pcc->msr_mask = (1ull << MSR_POW) |
3861 (1ull << MSR_ILE) |
3862 (1ull << MSR_EE) |
3863 (1ull << MSR_PR) |
3864 (1ull << MSR_FP) |
3865 (1ull << MSR_ME) |
3866 (1ull << MSR_FE0) |
3867 (1ull << MSR_SE) |
3868 (1ull << MSR_DE) |
3869 (1ull << MSR_FE1) |
3870 (1ull << MSR_EP) |
3871 (1ull << MSR_IR) |
3872 (1ull << MSR_DR) |
3873 (1ull << MSR_PMM) |
3874 (1ull << MSR_RI) |
3875 (1ull << MSR_LE);
3876 pcc->mmu_model = POWERPC_MMU_32B;
3877 pcc->excp_model = POWERPC_EXCP_7xx;
3878 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3879 pcc->bfd_mach = bfd_mach_ppc_750;
3880 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3881 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3882 }
3883
init_proc_750fx(CPUPPCState * env)3884 static void init_proc_750fx(CPUPPCState *env)
3885 {
3886 register_non_embedded_sprs(env);
3887 register_sdr1_sprs(env);
3888 register_7xx_sprs(env);
3889
3890 spr_register(env, SPR_L2CR, "L2CR",
3891 SPR_NOACCESS, SPR_NOACCESS,
3892 &spr_read_generic, spr_access_nop,
3893 0x00000000);
3894 /* Thermal management */
3895 register_thrm_sprs(env);
3896
3897 spr_register(env, SPR_750_THRM4, "THRM4",
3898 SPR_NOACCESS, SPR_NOACCESS,
3899 &spr_read_generic, &spr_write_generic,
3900 0x00000000);
3901 /* Hardware implementation registers */
3902 spr_register(env, SPR_750FX_HID2, "HID2",
3903 SPR_NOACCESS, SPR_NOACCESS,
3904 &spr_read_generic, &spr_write_generic,
3905 0x00000000);
3906 /* Memory management */
3907 register_low_BATs(env);
3908 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3909 register_high_BATs(env);
3910 init_excp_7x0(env);
3911 env->dcache_line_size = 32;
3912 env->icache_line_size = 32;
3913 /* Allocate hardware IRQ controller */
3914 ppc6xx_irq_init(env_archcpu(env));
3915 }
3916
3917 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
3918 {
3919 DeviceClass *dc = DEVICE_CLASS(oc);
3920 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3921
3922 dc->desc = "PowerPC 750FX";
3923 pcc->init_proc = init_proc_750fx;
3924 pcc->check_pow = check_pow_hid0;
3925 pcc->check_attn = check_attn_none;
3926 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3927 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3928 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3929 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3930 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3931 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3932 PPC_SEGMENT | PPC_EXTERN;
3933 pcc->msr_mask = (1ull << MSR_POW) |
3934 (1ull << MSR_ILE) |
3935 (1ull << MSR_EE) |
3936 (1ull << MSR_PR) |
3937 (1ull << MSR_FP) |
3938 (1ull << MSR_ME) |
3939 (1ull << MSR_FE0) |
3940 (1ull << MSR_SE) |
3941 (1ull << MSR_DE) |
3942 (1ull << MSR_FE1) |
3943 (1ull << MSR_EP) |
3944 (1ull << MSR_IR) |
3945 (1ull << MSR_DR) |
3946 (1ull << MSR_PMM) |
3947 (1ull << MSR_RI) |
3948 (1ull << MSR_LE);
3949 pcc->mmu_model = POWERPC_MMU_32B;
3950 pcc->excp_model = POWERPC_EXCP_7xx;
3951 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3952 pcc->bfd_mach = bfd_mach_ppc_750;
3953 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3954 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3955 }
3956
init_proc_750gx(CPUPPCState * env)3957 static void init_proc_750gx(CPUPPCState *env)
3958 {
3959 register_non_embedded_sprs(env);
3960 register_sdr1_sprs(env);
3961 register_7xx_sprs(env);
3962
3963 spr_register(env, SPR_L2CR, "L2CR",
3964 SPR_NOACCESS, SPR_NOACCESS,
3965 &spr_read_generic, spr_access_nop,
3966 0x00000000);
3967 /* Thermal management */
3968 register_thrm_sprs(env);
3969
3970 spr_register(env, SPR_750_THRM4, "THRM4",
3971 SPR_NOACCESS, SPR_NOACCESS,
3972 &spr_read_generic, &spr_write_generic,
3973 0x00000000);
3974 /* Hardware implementation registers */
3975 spr_register(env, SPR_750FX_HID2, "HID2",
3976 SPR_NOACCESS, SPR_NOACCESS,
3977 &spr_read_generic, &spr_write_generic,
3978 0x00000000);
3979 /* Memory management */
3980 register_low_BATs(env);
3981 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3982 register_high_BATs(env);
3983 init_excp_7x0(env);
3984 env->dcache_line_size = 32;
3985 env->icache_line_size = 32;
3986 /* Allocate hardware IRQ controller */
3987 ppc6xx_irq_init(env_archcpu(env));
3988 }
3989
3990 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
3991 {
3992 DeviceClass *dc = DEVICE_CLASS(oc);
3993 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3994
3995 dc->desc = "PowerPC 750GX";
3996 pcc->init_proc = init_proc_750gx;
3997 pcc->check_pow = check_pow_hid0;
3998 pcc->check_attn = check_attn_none;
3999 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4000 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4001 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4002 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4003 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4004 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4005 PPC_SEGMENT | PPC_EXTERN;
4006 pcc->msr_mask = (1ull << MSR_POW) |
4007 (1ull << MSR_ILE) |
4008 (1ull << MSR_EE) |
4009 (1ull << MSR_PR) |
4010 (1ull << MSR_FP) |
4011 (1ull << MSR_ME) |
4012 (1ull << MSR_FE0) |
4013 (1ull << MSR_SE) |
4014 (1ull << MSR_DE) |
4015 (1ull << MSR_FE1) |
4016 (1ull << MSR_EP) |
4017 (1ull << MSR_IR) |
4018 (1ull << MSR_DR) |
4019 (1ull << MSR_PMM) |
4020 (1ull << MSR_RI) |
4021 (1ull << MSR_LE);
4022 pcc->mmu_model = POWERPC_MMU_32B;
4023 pcc->excp_model = POWERPC_EXCP_7xx;
4024 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4025 pcc->bfd_mach = bfd_mach_ppc_750;
4026 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4027 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4028 }
4029
init_proc_745(CPUPPCState * env)4030 static void init_proc_745(CPUPPCState *env)
4031 {
4032 register_non_embedded_sprs(env);
4033 register_sdr1_sprs(env);
4034 register_7xx_sprs(env);
4035 register_745_sprs(env);
4036 /* Thermal management */
4037 register_thrm_sprs(env);
4038
4039 /* Memory management */
4040 register_low_BATs(env);
4041 register_high_BATs(env);
4042 register_6xx_7xx_soft_tlb(env, 64, 2);
4043 init_excp_7x5(env);
4044 env->dcache_line_size = 32;
4045 env->icache_line_size = 32;
4046 /* Allocate hardware IRQ controller */
4047 ppc6xx_irq_init(env_archcpu(env));
4048 }
4049
4050 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
4051 {
4052 DeviceClass *dc = DEVICE_CLASS(oc);
4053 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4054
4055 dc->desc = "PowerPC 745";
4056 pcc->init_proc = init_proc_745;
4057 pcc->check_pow = check_pow_hid0;
4058 pcc->check_attn = check_attn_none;
4059 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4060 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4061 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4062 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4063 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4064 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4065 PPC_SEGMENT | PPC_EXTERN;
4066 pcc->msr_mask = (1ull << MSR_POW) |
4067 (1ull << MSR_ILE) |
4068 (1ull << MSR_EE) |
4069 (1ull << MSR_PR) |
4070 (1ull << MSR_FP) |
4071 (1ull << MSR_ME) |
4072 (1ull << MSR_FE0) |
4073 (1ull << MSR_SE) |
4074 (1ull << MSR_DE) |
4075 (1ull << MSR_FE1) |
4076 (1ull << MSR_EP) |
4077 (1ull << MSR_IR) |
4078 (1ull << MSR_DR) |
4079 (1ull << MSR_PMM) |
4080 (1ull << MSR_RI) |
4081 (1ull << MSR_LE);
4082 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4083 pcc->excp_model = POWERPC_EXCP_7xx;
4084 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4085 pcc->bfd_mach = bfd_mach_ppc_750;
4086 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4087 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4088 }
4089
init_proc_755(CPUPPCState * env)4090 static void init_proc_755(CPUPPCState *env)
4091 {
4092 init_proc_745(env);
4093 register_755_sprs(env);
4094 }
4095
4096 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
4097 {
4098 DeviceClass *dc = DEVICE_CLASS(oc);
4099 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4100
4101 dc->desc = "PowerPC 755";
4102 pcc->init_proc = init_proc_755;
4103 pcc->check_pow = check_pow_hid0;
4104 pcc->check_attn = check_attn_none;
4105 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4106 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4107 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4108 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4109 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4110 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4111 PPC_SEGMENT | PPC_EXTERN;
4112 pcc->msr_mask = (1ull << MSR_POW) |
4113 (1ull << MSR_ILE) |
4114 (1ull << MSR_EE) |
4115 (1ull << MSR_PR) |
4116 (1ull << MSR_FP) |
4117 (1ull << MSR_ME) |
4118 (1ull << MSR_FE0) |
4119 (1ull << MSR_SE) |
4120 (1ull << MSR_DE) |
4121 (1ull << MSR_FE1) |
4122 (1ull << MSR_EP) |
4123 (1ull << MSR_IR) |
4124 (1ull << MSR_DR) |
4125 (1ull << MSR_PMM) |
4126 (1ull << MSR_RI) |
4127 (1ull << MSR_LE);
4128 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4129 pcc->excp_model = POWERPC_EXCP_7xx;
4130 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4131 pcc->bfd_mach = bfd_mach_ppc_750;
4132 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4133 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4134 }
4135
init_proc_7400(CPUPPCState * env)4136 static void init_proc_7400(CPUPPCState *env)
4137 {
4138 register_non_embedded_sprs(env);
4139 register_sdr1_sprs(env);
4140 register_74xx_sprs(env);
4141 vscr_init(env, 0x00010000);
4142
4143 spr_register(env, SPR_UBAMR, "UBAMR",
4144 &spr_read_ureg, SPR_NOACCESS,
4145 &spr_read_ureg, SPR_NOACCESS,
4146 0x00000000);
4147
4148 spr_register(env, SPR_MSSCR1, "MSSCR1",
4149 SPR_NOACCESS, SPR_NOACCESS,
4150 &spr_read_generic, &spr_write_generic,
4151 0x00000000);
4152 /* Thermal management */
4153 register_thrm_sprs(env);
4154 /* Memory management */
4155 register_low_BATs(env);
4156 init_excp_7400(env);
4157 env->dcache_line_size = 32;
4158 env->icache_line_size = 32;
4159 /* Allocate hardware IRQ controller */
4160 ppc6xx_irq_init(env_archcpu(env));
4161 }
4162
4163 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
4164 {
4165 DeviceClass *dc = DEVICE_CLASS(oc);
4166 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4167
4168 dc->desc = "PowerPC 7400 (aka G4)";
4169 pcc->init_proc = init_proc_7400;
4170 pcc->check_pow = check_pow_hid0;
4171 pcc->check_attn = check_attn_none;
4172 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4173 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4174 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4175 PPC_FLOAT_STFIWX |
4176 PPC_CACHE | PPC_CACHE_ICBI |
4177 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4178 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4179 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4180 PPC_MEM_TLBIA |
4181 PPC_SEGMENT | PPC_EXTERN |
4182 PPC_ALTIVEC;
4183 pcc->msr_mask = (1ull << MSR_VR) |
4184 (1ull << MSR_POW) |
4185 (1ull << MSR_ILE) |
4186 (1ull << MSR_EE) |
4187 (1ull << MSR_PR) |
4188 (1ull << MSR_FP) |
4189 (1ull << MSR_ME) |
4190 (1ull << MSR_FE0) |
4191 (1ull << MSR_SE) |
4192 (1ull << MSR_DE) |
4193 (1ull << MSR_FE1) |
4194 (1ull << MSR_EP) |
4195 (1ull << MSR_IR) |
4196 (1ull << MSR_DR) |
4197 (1ull << MSR_PMM) |
4198 (1ull << MSR_RI) |
4199 (1ull << MSR_LE);
4200 pcc->mmu_model = POWERPC_MMU_32B;
4201 pcc->excp_model = POWERPC_EXCP_74xx;
4202 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4203 pcc->bfd_mach = bfd_mach_ppc_7400;
4204 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4205 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4206 POWERPC_FLAG_BUS_CLK;
4207 }
4208
init_proc_7410(CPUPPCState * env)4209 static void init_proc_7410(CPUPPCState *env)
4210 {
4211 register_non_embedded_sprs(env);
4212 register_sdr1_sprs(env);
4213 register_74xx_sprs(env);
4214 vscr_init(env, 0x00010000);
4215
4216 spr_register(env, SPR_UBAMR, "UBAMR",
4217 &spr_read_ureg, SPR_NOACCESS,
4218 &spr_read_ureg, SPR_NOACCESS,
4219 0x00000000);
4220 /* Thermal management */
4221 register_thrm_sprs(env);
4222 /* L2PMCR */
4223
4224 spr_register(env, SPR_L2PMCR, "L2PMCR",
4225 SPR_NOACCESS, SPR_NOACCESS,
4226 &spr_read_generic, &spr_write_generic,
4227 0x00000000);
4228 /* LDSTDB */
4229
4230 spr_register(env, SPR_LDSTDB, "LDSTDB",
4231 SPR_NOACCESS, SPR_NOACCESS,
4232 &spr_read_generic, &spr_write_generic,
4233 0x00000000);
4234 /* Memory management */
4235 register_low_BATs(env);
4236 init_excp_7400(env);
4237 env->dcache_line_size = 32;
4238 env->icache_line_size = 32;
4239 /* Allocate hardware IRQ controller */
4240 ppc6xx_irq_init(env_archcpu(env));
4241 }
4242
4243 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
4244 {
4245 DeviceClass *dc = DEVICE_CLASS(oc);
4246 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4247
4248 dc->desc = "PowerPC 7410 (aka G4)";
4249 pcc->init_proc = init_proc_7410;
4250 pcc->check_pow = check_pow_hid0;
4251 pcc->check_attn = check_attn_none;
4252 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4253 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4254 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4255 PPC_FLOAT_STFIWX |
4256 PPC_CACHE | PPC_CACHE_ICBI |
4257 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4258 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4259 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4260 PPC_MEM_TLBIA |
4261 PPC_SEGMENT | PPC_EXTERN |
4262 PPC_ALTIVEC;
4263 pcc->msr_mask = (1ull << MSR_VR) |
4264 (1ull << MSR_POW) |
4265 (1ull << MSR_ILE) |
4266 (1ull << MSR_EE) |
4267 (1ull << MSR_PR) |
4268 (1ull << MSR_FP) |
4269 (1ull << MSR_ME) |
4270 (1ull << MSR_FE0) |
4271 (1ull << MSR_SE) |
4272 (1ull << MSR_DE) |
4273 (1ull << MSR_FE1) |
4274 (1ull << MSR_EP) |
4275 (1ull << MSR_IR) |
4276 (1ull << MSR_DR) |
4277 (1ull << MSR_PMM) |
4278 (1ull << MSR_RI) |
4279 (1ull << MSR_LE);
4280 pcc->mmu_model = POWERPC_MMU_32B;
4281 pcc->excp_model = POWERPC_EXCP_74xx;
4282 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4283 pcc->bfd_mach = bfd_mach_ppc_7400;
4284 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4285 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4286 POWERPC_FLAG_BUS_CLK;
4287 }
4288
init_proc_7440(CPUPPCState * env)4289 static void init_proc_7440(CPUPPCState *env)
4290 {
4291 register_non_embedded_sprs(env);
4292 register_sdr1_sprs(env);
4293 register_74xx_sprs(env);
4294 vscr_init(env, 0x00010000);
4295
4296 spr_register(env, SPR_UBAMR, "UBAMR",
4297 &spr_read_ureg, SPR_NOACCESS,
4298 &spr_read_ureg, SPR_NOACCESS,
4299 0x00000000);
4300 /* LDSTCR */
4301 spr_register(env, SPR_LDSTCR, "LDSTCR",
4302 SPR_NOACCESS, SPR_NOACCESS,
4303 &spr_read_generic, &spr_write_generic,
4304 0x00000000);
4305 /* ICTRL */
4306 spr_register(env, SPR_ICTRL, "ICTRL",
4307 SPR_NOACCESS, SPR_NOACCESS,
4308 &spr_read_generic, &spr_write_generic,
4309 0x00000000);
4310 /* MSSSR0 */
4311 spr_register(env, SPR_MSSSR0, "MSSSR0",
4312 SPR_NOACCESS, SPR_NOACCESS,
4313 &spr_read_generic, &spr_write_generic,
4314 0x00000000);
4315 /* PMC */
4316 spr_register(env, SPR_7XX_PMC5, "PMC5",
4317 SPR_NOACCESS, SPR_NOACCESS,
4318 &spr_read_generic, &spr_write_generic,
4319 0x00000000);
4320
4321 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4322 &spr_read_ureg, SPR_NOACCESS,
4323 &spr_read_ureg, SPR_NOACCESS,
4324 0x00000000);
4325
4326 spr_register(env, SPR_7XX_PMC6, "PMC6",
4327 SPR_NOACCESS, SPR_NOACCESS,
4328 &spr_read_generic, &spr_write_generic,
4329 0x00000000);
4330
4331 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4332 &spr_read_ureg, SPR_NOACCESS,
4333 &spr_read_ureg, SPR_NOACCESS,
4334 0x00000000);
4335 /* Memory management */
4336 register_low_BATs(env);
4337 init_excp_7450(env);
4338 env->dcache_line_size = 32;
4339 env->icache_line_size = 32;
4340 /* Allocate hardware IRQ controller */
4341 ppc6xx_irq_init(env_archcpu(env));
4342 }
4343
4344 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
4345 {
4346 DeviceClass *dc = DEVICE_CLASS(oc);
4347 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4348
4349 dc->desc = "PowerPC 7440 (aka G4)";
4350 pcc->init_proc = init_proc_7440;
4351 pcc->check_pow = check_pow_hid0_74xx;
4352 pcc->check_attn = check_attn_none;
4353 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4354 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4355 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4356 PPC_FLOAT_STFIWX |
4357 PPC_CACHE | PPC_CACHE_ICBI |
4358 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4359 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4360 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4361 PPC_MEM_TLBIA |
4362 PPC_SEGMENT | PPC_EXTERN |
4363 PPC_ALTIVEC;
4364 pcc->msr_mask = (1ull << MSR_VR) |
4365 (1ull << MSR_POW) |
4366 (1ull << MSR_ILE) |
4367 (1ull << MSR_EE) |
4368 (1ull << MSR_PR) |
4369 (1ull << MSR_FP) |
4370 (1ull << MSR_ME) |
4371 (1ull << MSR_FE0) |
4372 (1ull << MSR_SE) |
4373 (1ull << MSR_DE) |
4374 (1ull << MSR_FE1) |
4375 (1ull << MSR_EP) |
4376 (1ull << MSR_IR) |
4377 (1ull << MSR_DR) |
4378 (1ull << MSR_PMM) |
4379 (1ull << MSR_RI) |
4380 (1ull << MSR_LE);
4381 pcc->mmu_model = POWERPC_MMU_32B;
4382 pcc->excp_model = POWERPC_EXCP_74xx;
4383 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4384 pcc->bfd_mach = bfd_mach_ppc_7400;
4385 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4386 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4387 POWERPC_FLAG_BUS_CLK;
4388 }
4389
init_proc_7450(CPUPPCState * env)4390 static void init_proc_7450(CPUPPCState *env)
4391 {
4392 register_non_embedded_sprs(env);
4393 register_sdr1_sprs(env);
4394 register_74xx_sprs(env);
4395 vscr_init(env, 0x00010000);
4396 /* Level 3 cache control */
4397 register_l3_ctrl(env);
4398 /* L3ITCR1 */
4399 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
4400 SPR_NOACCESS, SPR_NOACCESS,
4401 &spr_read_generic, &spr_write_generic,
4402 0x00000000);
4403 /* L3ITCR2 */
4404 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
4405 SPR_NOACCESS, SPR_NOACCESS,
4406 &spr_read_generic, &spr_write_generic,
4407 0x00000000);
4408 /* L3ITCR3 */
4409 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
4410 SPR_NOACCESS, SPR_NOACCESS,
4411 &spr_read_generic, &spr_write_generic,
4412 0x00000000);
4413 /* L3OHCR */
4414 spr_register(env, SPR_L3OHCR, "L3OHCR",
4415 SPR_NOACCESS, SPR_NOACCESS,
4416 &spr_read_generic, &spr_write_generic,
4417 0x00000000);
4418
4419 spr_register(env, SPR_UBAMR, "UBAMR",
4420 &spr_read_ureg, SPR_NOACCESS,
4421 &spr_read_ureg, SPR_NOACCESS,
4422 0x00000000);
4423 /* LDSTCR */
4424 spr_register(env, SPR_LDSTCR, "LDSTCR",
4425 SPR_NOACCESS, SPR_NOACCESS,
4426 &spr_read_generic, &spr_write_generic,
4427 0x00000000);
4428 /* ICTRL */
4429 spr_register(env, SPR_ICTRL, "ICTRL",
4430 SPR_NOACCESS, SPR_NOACCESS,
4431 &spr_read_generic, &spr_write_generic,
4432 0x00000000);
4433 /* MSSSR0 */
4434 spr_register(env, SPR_MSSSR0, "MSSSR0",
4435 SPR_NOACCESS, SPR_NOACCESS,
4436 &spr_read_generic, &spr_write_generic,
4437 0x00000000);
4438 /* PMC */
4439 spr_register(env, SPR_7XX_PMC5, "PMC5",
4440 SPR_NOACCESS, SPR_NOACCESS,
4441 &spr_read_generic, &spr_write_generic,
4442 0x00000000);
4443
4444 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4445 &spr_read_ureg, SPR_NOACCESS,
4446 &spr_read_ureg, SPR_NOACCESS,
4447 0x00000000);
4448
4449 spr_register(env, SPR_7XX_PMC6, "PMC6",
4450 SPR_NOACCESS, SPR_NOACCESS,
4451 &spr_read_generic, &spr_write_generic,
4452 0x00000000);
4453
4454 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4455 &spr_read_ureg, SPR_NOACCESS,
4456 &spr_read_ureg, SPR_NOACCESS,
4457 0x00000000);
4458 /* Memory management */
4459 register_low_BATs(env);
4460 init_excp_7450(env);
4461 env->dcache_line_size = 32;
4462 env->icache_line_size = 32;
4463 /* Allocate hardware IRQ controller */
4464 ppc6xx_irq_init(env_archcpu(env));
4465 }
4466
4467 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
4468 {
4469 DeviceClass *dc = DEVICE_CLASS(oc);
4470 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4471
4472 dc->desc = "PowerPC 7450 (aka G4)";
4473 pcc->init_proc = init_proc_7450;
4474 pcc->check_pow = check_pow_hid0_74xx;
4475 pcc->check_attn = check_attn_none;
4476 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4477 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4478 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4479 PPC_FLOAT_STFIWX |
4480 PPC_CACHE | PPC_CACHE_ICBI |
4481 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4482 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4483 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4484 PPC_MEM_TLBIA |
4485 PPC_SEGMENT | PPC_EXTERN |
4486 PPC_ALTIVEC;
4487 pcc->msr_mask = (1ull << MSR_VR) |
4488 (1ull << MSR_POW) |
4489 (1ull << MSR_ILE) |
4490 (1ull << MSR_EE) |
4491 (1ull << MSR_PR) |
4492 (1ull << MSR_FP) |
4493 (1ull << MSR_ME) |
4494 (1ull << MSR_FE0) |
4495 (1ull << MSR_SE) |
4496 (1ull << MSR_DE) |
4497 (1ull << MSR_FE1) |
4498 (1ull << MSR_EP) |
4499 (1ull << MSR_IR) |
4500 (1ull << MSR_DR) |
4501 (1ull << MSR_PMM) |
4502 (1ull << MSR_RI) |
4503 (1ull << MSR_LE);
4504 pcc->mmu_model = POWERPC_MMU_32B;
4505 pcc->excp_model = POWERPC_EXCP_74xx;
4506 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4507 pcc->bfd_mach = bfd_mach_ppc_7400;
4508 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4509 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4510 POWERPC_FLAG_BUS_CLK;
4511 }
4512
init_proc_7445(CPUPPCState * env)4513 static void init_proc_7445(CPUPPCState *env)
4514 {
4515 register_non_embedded_sprs(env);
4516 register_sdr1_sprs(env);
4517 register_74xx_sprs(env);
4518 vscr_init(env, 0x00010000);
4519 /* LDSTCR */
4520 spr_register(env, SPR_LDSTCR, "LDSTCR",
4521 SPR_NOACCESS, SPR_NOACCESS,
4522 &spr_read_generic, &spr_write_generic,
4523 0x00000000);
4524 /* ICTRL */
4525 spr_register(env, SPR_ICTRL, "ICTRL",
4526 SPR_NOACCESS, SPR_NOACCESS,
4527 &spr_read_generic, &spr_write_generic,
4528 0x00000000);
4529 /* MSSSR0 */
4530 spr_register(env, SPR_MSSSR0, "MSSSR0",
4531 SPR_NOACCESS, SPR_NOACCESS,
4532 &spr_read_generic, &spr_write_generic,
4533 0x00000000);
4534 /* PMC */
4535 spr_register(env, SPR_7XX_PMC5, "PMC5",
4536 SPR_NOACCESS, SPR_NOACCESS,
4537 &spr_read_generic, &spr_write_generic,
4538 0x00000000);
4539
4540 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4541 &spr_read_ureg, SPR_NOACCESS,
4542 &spr_read_ureg, SPR_NOACCESS,
4543 0x00000000);
4544
4545 spr_register(env, SPR_7XX_PMC6, "PMC6",
4546 SPR_NOACCESS, SPR_NOACCESS,
4547 &spr_read_generic, &spr_write_generic,
4548 0x00000000);
4549
4550 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4551 &spr_read_ureg, SPR_NOACCESS,
4552 &spr_read_ureg, SPR_NOACCESS,
4553 0x00000000);
4554 /* SPRGs */
4555 spr_register(env, SPR_SPRG4, "SPRG4",
4556 SPR_NOACCESS, SPR_NOACCESS,
4557 &spr_read_generic, &spr_write_generic,
4558 0x00000000);
4559 spr_register(env, SPR_USPRG4, "USPRG4",
4560 &spr_read_ureg, SPR_NOACCESS,
4561 &spr_read_ureg, SPR_NOACCESS,
4562 0x00000000);
4563 spr_register(env, SPR_SPRG5, "SPRG5",
4564 SPR_NOACCESS, SPR_NOACCESS,
4565 &spr_read_generic, &spr_write_generic,
4566 0x00000000);
4567 spr_register(env, SPR_USPRG5, "USPRG5",
4568 &spr_read_ureg, SPR_NOACCESS,
4569 &spr_read_ureg, SPR_NOACCESS,
4570 0x00000000);
4571 spr_register(env, SPR_SPRG6, "SPRG6",
4572 SPR_NOACCESS, SPR_NOACCESS,
4573 &spr_read_generic, &spr_write_generic,
4574 0x00000000);
4575 spr_register(env, SPR_USPRG6, "USPRG6",
4576 &spr_read_ureg, SPR_NOACCESS,
4577 &spr_read_ureg, SPR_NOACCESS,
4578 0x00000000);
4579 spr_register(env, SPR_SPRG7, "SPRG7",
4580 SPR_NOACCESS, SPR_NOACCESS,
4581 &spr_read_generic, &spr_write_generic,
4582 0x00000000);
4583 spr_register(env, SPR_USPRG7, "USPRG7",
4584 &spr_read_ureg, SPR_NOACCESS,
4585 &spr_read_ureg, SPR_NOACCESS,
4586 0x00000000);
4587 /* Memory management */
4588 register_low_BATs(env);
4589 register_high_BATs(env);
4590 init_excp_7450(env);
4591 env->dcache_line_size = 32;
4592 env->icache_line_size = 32;
4593 /* Allocate hardware IRQ controller */
4594 ppc6xx_irq_init(env_archcpu(env));
4595 }
4596
4597 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
4598 {
4599 DeviceClass *dc = DEVICE_CLASS(oc);
4600 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4601
4602 dc->desc = "PowerPC 7445 (aka G4)";
4603 pcc->init_proc = init_proc_7445;
4604 pcc->check_pow = check_pow_hid0_74xx;
4605 pcc->check_attn = check_attn_none;
4606 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4607 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4608 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4609 PPC_FLOAT_STFIWX |
4610 PPC_CACHE | PPC_CACHE_ICBI |
4611 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4612 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4613 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4614 PPC_MEM_TLBIA |
4615 PPC_SEGMENT | PPC_EXTERN |
4616 PPC_ALTIVEC;
4617 pcc->msr_mask = (1ull << MSR_VR) |
4618 (1ull << MSR_POW) |
4619 (1ull << MSR_ILE) |
4620 (1ull << MSR_EE) |
4621 (1ull << MSR_PR) |
4622 (1ull << MSR_FP) |
4623 (1ull << MSR_ME) |
4624 (1ull << MSR_FE0) |
4625 (1ull << MSR_SE) |
4626 (1ull << MSR_DE) |
4627 (1ull << MSR_FE1) |
4628 (1ull << MSR_EP) |
4629 (1ull << MSR_IR) |
4630 (1ull << MSR_DR) |
4631 (1ull << MSR_PMM) |
4632 (1ull << MSR_RI) |
4633 (1ull << MSR_LE);
4634 pcc->mmu_model = POWERPC_MMU_32B;
4635 pcc->excp_model = POWERPC_EXCP_74xx;
4636 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4637 pcc->bfd_mach = bfd_mach_ppc_7400;
4638 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4639 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4640 POWERPC_FLAG_BUS_CLK;
4641 }
4642
init_proc_7455(CPUPPCState * env)4643 static void init_proc_7455(CPUPPCState *env)
4644 {
4645 register_non_embedded_sprs(env);
4646 register_sdr1_sprs(env);
4647 register_74xx_sprs(env);
4648 vscr_init(env, 0x00010000);
4649 /* Level 3 cache control */
4650 register_l3_ctrl(env);
4651 /* LDSTCR */
4652 spr_register(env, SPR_LDSTCR, "LDSTCR",
4653 SPR_NOACCESS, SPR_NOACCESS,
4654 &spr_read_generic, &spr_write_generic,
4655 0x00000000);
4656 /* ICTRL */
4657 spr_register(env, SPR_ICTRL, "ICTRL",
4658 SPR_NOACCESS, SPR_NOACCESS,
4659 &spr_read_generic, &spr_write_generic,
4660 0x00000000);
4661 /* MSSSR0 */
4662 spr_register(env, SPR_MSSSR0, "MSSSR0",
4663 SPR_NOACCESS, SPR_NOACCESS,
4664 &spr_read_generic, &spr_write_generic,
4665 0x00000000);
4666 /* PMC */
4667 spr_register(env, SPR_7XX_PMC5, "PMC5",
4668 SPR_NOACCESS, SPR_NOACCESS,
4669 &spr_read_generic, &spr_write_generic,
4670 0x00000000);
4671
4672 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4673 &spr_read_ureg, SPR_NOACCESS,
4674 &spr_read_ureg, SPR_NOACCESS,
4675 0x00000000);
4676
4677 spr_register(env, SPR_7XX_PMC6, "PMC6",
4678 SPR_NOACCESS, SPR_NOACCESS,
4679 &spr_read_generic, &spr_write_generic,
4680 0x00000000);
4681
4682 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4683 &spr_read_ureg, SPR_NOACCESS,
4684 &spr_read_ureg, SPR_NOACCESS,
4685 0x00000000);
4686 /* SPRGs */
4687 spr_register(env, SPR_SPRG4, "SPRG4",
4688 SPR_NOACCESS, SPR_NOACCESS,
4689 &spr_read_generic, &spr_write_generic,
4690 0x00000000);
4691 spr_register(env, SPR_USPRG4, "USPRG4",
4692 &spr_read_ureg, SPR_NOACCESS,
4693 &spr_read_ureg, SPR_NOACCESS,
4694 0x00000000);
4695 spr_register(env, SPR_SPRG5, "SPRG5",
4696 SPR_NOACCESS, SPR_NOACCESS,
4697 &spr_read_generic, &spr_write_generic,
4698 0x00000000);
4699 spr_register(env, SPR_USPRG5, "USPRG5",
4700 &spr_read_ureg, SPR_NOACCESS,
4701 &spr_read_ureg, SPR_NOACCESS,
4702 0x00000000);
4703 spr_register(env, SPR_SPRG6, "SPRG6",
4704 SPR_NOACCESS, SPR_NOACCESS,
4705 &spr_read_generic, &spr_write_generic,
4706 0x00000000);
4707 spr_register(env, SPR_USPRG6, "USPRG6",
4708 &spr_read_ureg, SPR_NOACCESS,
4709 &spr_read_ureg, SPR_NOACCESS,
4710 0x00000000);
4711 spr_register(env, SPR_SPRG7, "SPRG7",
4712 SPR_NOACCESS, SPR_NOACCESS,
4713 &spr_read_generic, &spr_write_generic,
4714 0x00000000);
4715 spr_register(env, SPR_USPRG7, "USPRG7",
4716 &spr_read_ureg, SPR_NOACCESS,
4717 &spr_read_ureg, SPR_NOACCESS,
4718 0x00000000);
4719 /* Memory management */
4720 register_low_BATs(env);
4721 register_high_BATs(env);
4722 init_excp_7450(env);
4723 env->dcache_line_size = 32;
4724 env->icache_line_size = 32;
4725 /* Allocate hardware IRQ controller */
4726 ppc6xx_irq_init(env_archcpu(env));
4727 }
4728
4729 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
4730 {
4731 DeviceClass *dc = DEVICE_CLASS(oc);
4732 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4733
4734 dc->desc = "PowerPC 7455 (aka G4)";
4735 pcc->init_proc = init_proc_7455;
4736 pcc->check_pow = check_pow_hid0_74xx;
4737 pcc->check_attn = check_attn_none;
4738 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4739 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4740 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4741 PPC_FLOAT_STFIWX |
4742 PPC_CACHE | PPC_CACHE_ICBI |
4743 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4744 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4745 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4746 PPC_MEM_TLBIA |
4747 PPC_SEGMENT | PPC_EXTERN |
4748 PPC_ALTIVEC;
4749 pcc->msr_mask = (1ull << MSR_VR) |
4750 (1ull << MSR_POW) |
4751 (1ull << MSR_ILE) |
4752 (1ull << MSR_EE) |
4753 (1ull << MSR_PR) |
4754 (1ull << MSR_FP) |
4755 (1ull << MSR_ME) |
4756 (1ull << MSR_FE0) |
4757 (1ull << MSR_SE) |
4758 (1ull << MSR_DE) |
4759 (1ull << MSR_FE1) |
4760 (1ull << MSR_EP) |
4761 (1ull << MSR_IR) |
4762 (1ull << MSR_DR) |
4763 (1ull << MSR_PMM) |
4764 (1ull << MSR_RI) |
4765 (1ull << MSR_LE);
4766 pcc->mmu_model = POWERPC_MMU_32B;
4767 pcc->excp_model = POWERPC_EXCP_74xx;
4768 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4769 pcc->bfd_mach = bfd_mach_ppc_7400;
4770 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4771 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4772 POWERPC_FLAG_BUS_CLK;
4773 }
4774
init_proc_7457(CPUPPCState * env)4775 static void init_proc_7457(CPUPPCState *env)
4776 {
4777 register_non_embedded_sprs(env);
4778 register_sdr1_sprs(env);
4779 register_74xx_sprs(env);
4780 vscr_init(env, 0x00010000);
4781 /* Level 3 cache control */
4782 register_l3_ctrl(env);
4783 /* L3ITCR1 */
4784 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
4785 SPR_NOACCESS, SPR_NOACCESS,
4786 &spr_read_generic, &spr_write_generic,
4787 0x00000000);
4788 /* L3ITCR2 */
4789 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
4790 SPR_NOACCESS, SPR_NOACCESS,
4791 &spr_read_generic, &spr_write_generic,
4792 0x00000000);
4793 /* L3ITCR3 */
4794 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
4795 SPR_NOACCESS, SPR_NOACCESS,
4796 &spr_read_generic, &spr_write_generic,
4797 0x00000000);
4798 /* L3OHCR */
4799 spr_register(env, SPR_L3OHCR, "L3OHCR",
4800 SPR_NOACCESS, SPR_NOACCESS,
4801 &spr_read_generic, &spr_write_generic,
4802 0x00000000);
4803 /* LDSTCR */
4804 spr_register(env, SPR_LDSTCR, "LDSTCR",
4805 SPR_NOACCESS, SPR_NOACCESS,
4806 &spr_read_generic, &spr_write_generic,
4807 0x00000000);
4808 /* ICTRL */
4809 spr_register(env, SPR_ICTRL, "ICTRL",
4810 SPR_NOACCESS, SPR_NOACCESS,
4811 &spr_read_generic, &spr_write_generic,
4812 0x00000000);
4813 /* MSSSR0 */
4814 spr_register(env, SPR_MSSSR0, "MSSSR0",
4815 SPR_NOACCESS, SPR_NOACCESS,
4816 &spr_read_generic, &spr_write_generic,
4817 0x00000000);
4818 /* PMC */
4819 spr_register(env, SPR_7XX_PMC5, "PMC5",
4820 SPR_NOACCESS, SPR_NOACCESS,
4821 &spr_read_generic, &spr_write_generic,
4822 0x00000000);
4823
4824 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4825 &spr_read_ureg, SPR_NOACCESS,
4826 &spr_read_ureg, SPR_NOACCESS,
4827 0x00000000);
4828
4829 spr_register(env, SPR_7XX_PMC6, "PMC6",
4830 SPR_NOACCESS, SPR_NOACCESS,
4831 &spr_read_generic, &spr_write_generic,
4832 0x00000000);
4833
4834 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4835 &spr_read_ureg, SPR_NOACCESS,
4836 &spr_read_ureg, SPR_NOACCESS,
4837 0x00000000);
4838 /* SPRGs */
4839 spr_register(env, SPR_SPRG4, "SPRG4",
4840 SPR_NOACCESS, SPR_NOACCESS,
4841 &spr_read_generic, &spr_write_generic,
4842 0x00000000);
4843 spr_register(env, SPR_USPRG4, "USPRG4",
4844 &spr_read_ureg, SPR_NOACCESS,
4845 &spr_read_ureg, SPR_NOACCESS,
4846 0x00000000);
4847 spr_register(env, SPR_SPRG5, "SPRG5",
4848 SPR_NOACCESS, SPR_NOACCESS,
4849 &spr_read_generic, &spr_write_generic,
4850 0x00000000);
4851 spr_register(env, SPR_USPRG5, "USPRG5",
4852 &spr_read_ureg, SPR_NOACCESS,
4853 &spr_read_ureg, SPR_NOACCESS,
4854 0x00000000);
4855 spr_register(env, SPR_SPRG6, "SPRG6",
4856 SPR_NOACCESS, SPR_NOACCESS,
4857 &spr_read_generic, &spr_write_generic,
4858 0x00000000);
4859 spr_register(env, SPR_USPRG6, "USPRG6",
4860 &spr_read_ureg, SPR_NOACCESS,
4861 &spr_read_ureg, SPR_NOACCESS,
4862 0x00000000);
4863 spr_register(env, SPR_SPRG7, "SPRG7",
4864 SPR_NOACCESS, SPR_NOACCESS,
4865 &spr_read_generic, &spr_write_generic,
4866 0x00000000);
4867 spr_register(env, SPR_USPRG7, "USPRG7",
4868 &spr_read_ureg, SPR_NOACCESS,
4869 &spr_read_ureg, SPR_NOACCESS,
4870 0x00000000);
4871 /* Memory management */
4872 register_low_BATs(env);
4873 register_high_BATs(env);
4874 init_excp_7450(env);
4875 env->dcache_line_size = 32;
4876 env->icache_line_size = 32;
4877 /* Allocate hardware IRQ controller */
4878 ppc6xx_irq_init(env_archcpu(env));
4879 }
4880
4881 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
4882 {
4883 DeviceClass *dc = DEVICE_CLASS(oc);
4884 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4885
4886 dc->desc = "PowerPC 7457 (aka G4)";
4887 pcc->init_proc = init_proc_7457;
4888 pcc->check_pow = check_pow_hid0_74xx;
4889 pcc->check_attn = check_attn_none;
4890 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4891 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4892 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4893 PPC_FLOAT_STFIWX |
4894 PPC_CACHE | PPC_CACHE_ICBI |
4895 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4896 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4897 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4898 PPC_MEM_TLBIA |
4899 PPC_SEGMENT | PPC_EXTERN |
4900 PPC_ALTIVEC;
4901 pcc->msr_mask = (1ull << MSR_VR) |
4902 (1ull << MSR_POW) |
4903 (1ull << MSR_ILE) |
4904 (1ull << MSR_EE) |
4905 (1ull << MSR_PR) |
4906 (1ull << MSR_FP) |
4907 (1ull << MSR_ME) |
4908 (1ull << MSR_FE0) |
4909 (1ull << MSR_SE) |
4910 (1ull << MSR_DE) |
4911 (1ull << MSR_FE1) |
4912 (1ull << MSR_EP) |
4913 (1ull << MSR_IR) |
4914 (1ull << MSR_DR) |
4915 (1ull << MSR_PMM) |
4916 (1ull << MSR_RI) |
4917 (1ull << MSR_LE);
4918 pcc->mmu_model = POWERPC_MMU_32B;
4919 pcc->excp_model = POWERPC_EXCP_74xx;
4920 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4921 pcc->bfd_mach = bfd_mach_ppc_7400;
4922 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4923 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4924 POWERPC_FLAG_BUS_CLK;
4925 }
4926
init_proc_e600(CPUPPCState * env)4927 static void init_proc_e600(CPUPPCState *env)
4928 {
4929 register_non_embedded_sprs(env);
4930 register_sdr1_sprs(env);
4931 register_74xx_sprs(env);
4932 vscr_init(env, 0x00010000);
4933
4934 spr_register(env, SPR_UBAMR, "UBAMR",
4935 &spr_read_ureg, SPR_NOACCESS,
4936 &spr_read_ureg, SPR_NOACCESS,
4937 0x00000000);
4938
4939 spr_register(env, SPR_LDSTCR, "LDSTCR",
4940 SPR_NOACCESS, SPR_NOACCESS,
4941 &spr_read_generic, &spr_write_generic,
4942 0x00000000);
4943
4944 spr_register(env, SPR_ICTRL, "ICTRL",
4945 SPR_NOACCESS, SPR_NOACCESS,
4946 &spr_read_generic, &spr_write_generic,
4947 0x00000000);
4948
4949 spr_register(env, SPR_MSSSR0, "MSSSR0",
4950 SPR_NOACCESS, SPR_NOACCESS,
4951 &spr_read_generic, &spr_write_generic,
4952 0x00000000);
4953
4954 spr_register(env, SPR_7XX_PMC5, "PMC5",
4955 SPR_NOACCESS, SPR_NOACCESS,
4956 &spr_read_generic, &spr_write_generic,
4957 0x00000000);
4958
4959 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4960 &spr_read_ureg, SPR_NOACCESS,
4961 &spr_read_ureg, SPR_NOACCESS,
4962 0x00000000);
4963
4964 spr_register(env, SPR_7XX_PMC6, "PMC6",
4965 SPR_NOACCESS, SPR_NOACCESS,
4966 &spr_read_generic, &spr_write_generic,
4967 0x00000000);
4968
4969 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4970 &spr_read_ureg, SPR_NOACCESS,
4971 &spr_read_ureg, SPR_NOACCESS,
4972 0x00000000);
4973 /* SPRGs */
4974 spr_register(env, SPR_SPRG4, "SPRG4",
4975 SPR_NOACCESS, SPR_NOACCESS,
4976 &spr_read_generic, &spr_write_generic,
4977 0x00000000);
4978 spr_register(env, SPR_USPRG4, "USPRG4",
4979 &spr_read_ureg, SPR_NOACCESS,
4980 &spr_read_ureg, SPR_NOACCESS,
4981 0x00000000);
4982 spr_register(env, SPR_SPRG5, "SPRG5",
4983 SPR_NOACCESS, SPR_NOACCESS,
4984 &spr_read_generic, &spr_write_generic,
4985 0x00000000);
4986 spr_register(env, SPR_USPRG5, "USPRG5",
4987 &spr_read_ureg, SPR_NOACCESS,
4988 &spr_read_ureg, SPR_NOACCESS,
4989 0x00000000);
4990 spr_register(env, SPR_SPRG6, "SPRG6",
4991 SPR_NOACCESS, SPR_NOACCESS,
4992 &spr_read_generic, &spr_write_generic,
4993 0x00000000);
4994 spr_register(env, SPR_USPRG6, "USPRG6",
4995 &spr_read_ureg, SPR_NOACCESS,
4996 &spr_read_ureg, SPR_NOACCESS,
4997 0x00000000);
4998 spr_register(env, SPR_SPRG7, "SPRG7",
4999 SPR_NOACCESS, SPR_NOACCESS,
5000 &spr_read_generic, &spr_write_generic,
5001 0x00000000);
5002 spr_register(env, SPR_USPRG7, "USPRG7",
5003 &spr_read_ureg, SPR_NOACCESS,
5004 &spr_read_ureg, SPR_NOACCESS,
5005 0x00000000);
5006 /* Memory management */
5007 register_low_BATs(env);
5008 register_high_BATs(env);
5009 init_excp_7450(env);
5010 env->dcache_line_size = 32;
5011 env->icache_line_size = 32;
5012 /* Allocate hardware IRQ controller */
5013 ppc6xx_irq_init(env_archcpu(env));
5014 }
5015
POWERPC_FAMILY(e600)5016 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
5017 {
5018 DeviceClass *dc = DEVICE_CLASS(oc);
5019 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5020
5021 dc->desc = "PowerPC e600";
5022 pcc->init_proc = init_proc_e600;
5023 pcc->check_pow = check_pow_hid0_74xx;
5024 pcc->check_attn = check_attn_none;
5025 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5026 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5027 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5028 PPC_FLOAT_STFIWX |
5029 PPC_CACHE | PPC_CACHE_ICBI |
5030 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5031 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5032 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5033 PPC_MEM_TLBIA |
5034 PPC_SEGMENT | PPC_EXTERN |
5035 PPC_ALTIVEC;
5036 pcc->insns_flags2 = PPC_NONE;
5037 pcc->msr_mask = (1ull << MSR_VR) |
5038 (1ull << MSR_POW) |
5039 (1ull << MSR_ILE) |
5040 (1ull << MSR_EE) |
5041 (1ull << MSR_PR) |
5042 (1ull << MSR_FP) |
5043 (1ull << MSR_ME) |
5044 (1ull << MSR_FE0) |
5045 (1ull << MSR_SE) |
5046 (1ull << MSR_DE) |
5047 (1ull << MSR_FE1) |
5048 (1ull << MSR_EP) |
5049 (1ull << MSR_IR) |
5050 (1ull << MSR_DR) |
5051 (1ull << MSR_PMM) |
5052 (1ull << MSR_RI) |
5053 (1ull << MSR_LE);
5054 pcc->mmu_model = POWERPC_MMU_32B;
5055 pcc->excp_model = POWERPC_EXCP_74xx;
5056 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5057 pcc->bfd_mach = bfd_mach_ppc_7400;
5058 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5059 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5060 POWERPC_FLAG_BUS_CLK;
5061 }
5062
5063 #if defined(TARGET_PPC64)
5064 #if defined(CONFIG_USER_ONLY)
5065 #define POWERPC970_HID5_INIT 0x00000080
5066 #else
5067 #define POWERPC970_HID5_INIT 0x00000000
5068 #endif
5069
check_pow_970(CPUPPCState * env)5070 static int check_pow_970(CPUPPCState *env)
5071 {
5072 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
5073 return 1;
5074 }
5075
5076 return 0;
5077 }
5078
register_970_hid_sprs(CPUPPCState * env)5079 static void register_970_hid_sprs(CPUPPCState *env)
5080 {
5081 /* Hardware implementation registers */
5082 spr_register(env, SPR_HID0, "HID0",
5083 SPR_NOACCESS, SPR_NOACCESS,
5084 &spr_read_generic, &spr_write_clear,
5085 0x60000000);
5086 spr_register(env, SPR_HID1, "HID1",
5087 SPR_NOACCESS, SPR_NOACCESS,
5088 &spr_read_generic, &spr_write_generic,
5089 0x00000000);
5090 spr_register(env, SPR_970_HID5, "HID5",
5091 SPR_NOACCESS, SPR_NOACCESS,
5092 &spr_read_generic, &spr_write_generic,
5093 POWERPC970_HID5_INIT);
5094 }
5095
register_970_hior_sprs(CPUPPCState * env)5096 static void register_970_hior_sprs(CPUPPCState *env)
5097 {
5098 spr_register(env, SPR_HIOR, "HIOR",
5099 SPR_NOACCESS, SPR_NOACCESS,
5100 &spr_read_hior, &spr_write_hior,
5101 0x00000000);
5102 }
5103
register_book3s_ctrl_sprs(CPUPPCState * env)5104 static void register_book3s_ctrl_sprs(CPUPPCState *env)
5105 {
5106 spr_register(env, SPR_CTRL, "CTRL",
5107 SPR_NOACCESS, SPR_NOACCESS,
5108 SPR_NOACCESS, &spr_write_CTRL,
5109 0x00000000);
5110 spr_register(env, SPR_UCTRL, "UCTRL",
5111 &spr_read_ureg, SPR_NOACCESS,
5112 &spr_read_ureg, SPR_NOACCESS,
5113 0x00000000);
5114 }
5115
register_book3s_altivec_sprs(CPUPPCState * env)5116 static void register_book3s_altivec_sprs(CPUPPCState *env)
5117 {
5118 if (!(env->insns_flags & PPC_ALTIVEC)) {
5119 return;
5120 }
5121
5122 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
5123 &spr_read_generic, &spr_write_generic32,
5124 &spr_read_generic, &spr_write_generic32,
5125 KVM_REG_PPC_VRSAVE, 0x00000000);
5126
5127 }
5128
register_book3s_dbg_sprs(CPUPPCState * env)5129 static void register_book3s_dbg_sprs(CPUPPCState *env)
5130 {
5131 /*
5132 * TODO: different specs define different scopes for these,
5133 * will have to address this:
5134 * 970: super/write and super/read
5135 * powerisa 2.03..2.04: hypv/write and super/read.
5136 * powerisa 2.05 and newer: hypv/write and hypv/read.
5137 */
5138 spr_register_kvm(env, SPR_DABR, "DABR",
5139 SPR_NOACCESS, SPR_NOACCESS,
5140 &spr_read_generic, &spr_write_generic,
5141 KVM_REG_PPC_DABR, 0x00000000);
5142 spr_register_kvm(env, SPR_DABRX, "DABRX",
5143 SPR_NOACCESS, SPR_NOACCESS,
5144 &spr_read_generic, &spr_write_generic,
5145 KVM_REG_PPC_DABRX, 0x00000000);
5146 }
5147
register_book3s_207_dbg_sprs(CPUPPCState * env)5148 static void register_book3s_207_dbg_sprs(CPUPPCState *env)
5149 {
5150 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0",
5151 SPR_NOACCESS, SPR_NOACCESS,
5152 SPR_NOACCESS, SPR_NOACCESS,
5153 &spr_read_generic, &spr_write_dawr0,
5154 KVM_REG_PPC_DAWR, 0x00000000);
5155 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0",
5156 SPR_NOACCESS, SPR_NOACCESS,
5157 SPR_NOACCESS, SPR_NOACCESS,
5158 &spr_read_generic, &spr_write_dawrx0,
5159 KVM_REG_PPC_DAWRX, 0x00000000);
5160 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
5161 SPR_NOACCESS, SPR_NOACCESS,
5162 SPR_NOACCESS, SPR_NOACCESS,
5163 &spr_read_generic, &spr_write_ciabr,
5164 KVM_REG_PPC_CIABR, 0x00000000);
5165 }
5166
register_970_dbg_sprs(CPUPPCState * env)5167 static void register_970_dbg_sprs(CPUPPCState *env)
5168 {
5169 /* Breakpoints */
5170 spr_register(env, SPR_IABR, "IABR",
5171 SPR_NOACCESS, SPR_NOACCESS,
5172 &spr_read_generic, &spr_write_generic,
5173 0x00000000);
5174 }
5175
register_book3s_pmu_sup_sprs(CPUPPCState * env)5176 static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
5177 {
5178 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
5179 SPR_NOACCESS, SPR_NOACCESS,
5180 &spr_read_generic, &spr_write_MMCR0,
5181 KVM_REG_PPC_MMCR0, 0x80000000);
5182 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
5183 SPR_NOACCESS, SPR_NOACCESS,
5184 &spr_read_generic, &spr_write_MMCR1,
5185 KVM_REG_PPC_MMCR1, 0x00000000);
5186 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
5187 SPR_NOACCESS, SPR_NOACCESS,
5188 &spr_read_generic, &spr_write_MMCRA,
5189 KVM_REG_PPC_MMCRA, 0x00000000);
5190 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
5191 SPR_NOACCESS, SPR_NOACCESS,
5192 &spr_read_PMC, &spr_write_PMC,
5193 KVM_REG_PPC_PMC1, 0x00000000);
5194 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
5195 SPR_NOACCESS, SPR_NOACCESS,
5196 &spr_read_PMC, &spr_write_PMC,
5197 KVM_REG_PPC_PMC2, 0x00000000);
5198 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
5199 SPR_NOACCESS, SPR_NOACCESS,
5200 &spr_read_PMC, &spr_write_PMC,
5201 KVM_REG_PPC_PMC3, 0x00000000);
5202 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
5203 SPR_NOACCESS, SPR_NOACCESS,
5204 &spr_read_PMC, &spr_write_PMC,
5205 KVM_REG_PPC_PMC4, 0x00000000);
5206 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
5207 SPR_NOACCESS, SPR_NOACCESS,
5208 &spr_read_PMC, &spr_write_PMC,
5209 KVM_REG_PPC_PMC5, 0x00000000);
5210 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
5211 SPR_NOACCESS, SPR_NOACCESS,
5212 &spr_read_PMC, &spr_write_PMC,
5213 KVM_REG_PPC_PMC6, 0x00000000);
5214 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
5215 SPR_NOACCESS, SPR_NOACCESS,
5216 &spr_read_generic, &spr_write_generic,
5217 KVM_REG_PPC_SIAR, 0x00000000);
5218 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
5219 SPR_NOACCESS, SPR_NOACCESS,
5220 &spr_read_generic, &spr_write_generic,
5221 KVM_REG_PPC_SDAR, 0x00000000);
5222 }
5223
register_book3s_pmu_user_sprs(CPUPPCState * env)5224 static void register_book3s_pmu_user_sprs(CPUPPCState *env)
5225 {
5226 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
5227 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg,
5228 &spr_read_ureg, &spr_write_ureg,
5229 0x80000000);
5230 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
5231 &spr_read_ureg, SPR_NOACCESS,
5232 &spr_read_ureg, &spr_write_ureg,
5233 0x00000000);
5234 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
5235 &spr_read_ureg, SPR_NOACCESS,
5236 &spr_read_ureg, &spr_write_ureg,
5237 0x00000000);
5238 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
5239 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5240 &spr_read_ureg, &spr_write_ureg,
5241 0x00000000);
5242 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
5243 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5244 &spr_read_ureg, &spr_write_ureg,
5245 0x00000000);
5246 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
5247 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5248 &spr_read_ureg, &spr_write_ureg,
5249 0x00000000);
5250 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
5251 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5252 &spr_read_ureg, &spr_write_ureg,
5253 0x00000000);
5254 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
5255 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5256 &spr_read_ureg, &spr_write_ureg,
5257 0x00000000);
5258 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
5259 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5260 &spr_read_ureg, &spr_write_ureg,
5261 0x00000000);
5262 spr_register(env, SPR_POWER_USIAR, "USIAR",
5263 &spr_read_ureg, SPR_NOACCESS,
5264 &spr_read_ureg, &spr_write_ureg,
5265 0x00000000);
5266 spr_register(env, SPR_POWER_USDAR, "USDAR",
5267 &spr_read_ureg, SPR_NOACCESS,
5268 &spr_read_ureg, &spr_write_ureg,
5269 0x00000000);
5270 }
5271
register_970_pmu_sup_sprs(CPUPPCState * env)5272 static void register_970_pmu_sup_sprs(CPUPPCState *env)
5273 {
5274 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
5275 SPR_NOACCESS, SPR_NOACCESS,
5276 &spr_read_generic, &spr_write_generic,
5277 KVM_REG_PPC_PMC7, 0x00000000);
5278 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
5279 SPR_NOACCESS, SPR_NOACCESS,
5280 &spr_read_generic, &spr_write_generic,
5281 KVM_REG_PPC_PMC8, 0x00000000);
5282 }
5283
register_970_pmu_user_sprs(CPUPPCState * env)5284 static void register_970_pmu_user_sprs(CPUPPCState *env)
5285 {
5286 spr_register(env, SPR_970_UPMC7, "UPMC7",
5287 &spr_read_ureg, SPR_NOACCESS,
5288 &spr_read_ureg, &spr_write_ureg,
5289 0x00000000);
5290 spr_register(env, SPR_970_UPMC8, "UPMC8",
5291 &spr_read_ureg, SPR_NOACCESS,
5292 &spr_read_ureg, &spr_write_ureg,
5293 0x00000000);
5294 }
5295
register_power8_pmu_sup_sprs(CPUPPCState * env)5296 static void register_power8_pmu_sup_sprs(CPUPPCState *env)
5297 {
5298 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
5299 SPR_NOACCESS, SPR_NOACCESS,
5300 &spr_read_generic, &spr_write_generic,
5301 KVM_REG_PPC_MMCR2, 0x00000000);
5302 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
5303 SPR_NOACCESS, SPR_NOACCESS,
5304 &spr_read_generic, &spr_write_generic,
5305 KVM_REG_PPC_MMCRS, 0x00000000);
5306 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
5307 SPR_NOACCESS, SPR_NOACCESS,
5308 &spr_read_generic, &spr_write_generic,
5309 KVM_REG_PPC_SIER, 0x00000000);
5310 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
5311 SPR_NOACCESS, SPR_NOACCESS,
5312 &spr_read_generic, &spr_write_generic,
5313 KVM_REG_PPC_SPMC1, 0x00000000);
5314 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
5315 SPR_NOACCESS, SPR_NOACCESS,
5316 &spr_read_generic, &spr_write_generic,
5317 KVM_REG_PPC_SPMC2, 0x00000000);
5318 spr_register_kvm(env, SPR_TACR, "TACR",
5319 SPR_NOACCESS, SPR_NOACCESS,
5320 &spr_read_generic, &spr_write_generic,
5321 KVM_REG_PPC_TACR, 0x00000000);
5322 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
5323 SPR_NOACCESS, SPR_NOACCESS,
5324 &spr_read_generic, &spr_write_generic,
5325 KVM_REG_PPC_TCSCR, 0x00000000);
5326 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
5327 SPR_NOACCESS, SPR_NOACCESS,
5328 &spr_read_generic, &spr_write_generic,
5329 KVM_REG_PPC_CSIGR, 0x00000000);
5330 }
5331
register_power8_pmu_user_sprs(CPUPPCState * env)5332 static void register_power8_pmu_user_sprs(CPUPPCState *env)
5333 {
5334 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
5335 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg,
5336 &spr_read_ureg, &spr_write_ureg,
5337 0x00000000);
5338 spr_register(env, SPR_POWER_USIER, "USIER",
5339 &spr_read_generic, SPR_NOACCESS,
5340 &spr_read_generic, &spr_write_generic,
5341 0x00000000);
5342 }
5343
register_power10_pmu_sup_sprs(CPUPPCState * env)5344 static void register_power10_pmu_sup_sprs(CPUPPCState *env)
5345 {
5346 spr_register_kvm(env, SPR_POWER_MMCR3, "MMCR3",
5347 SPR_NOACCESS, SPR_NOACCESS,
5348 &spr_read_generic, &spr_write_generic,
5349 KVM_REG_PPC_MMCR3, 0x00000000);
5350 spr_register_kvm(env, SPR_POWER_SIER2, "SIER2",
5351 SPR_NOACCESS, SPR_NOACCESS,
5352 &spr_read_generic, &spr_write_generic,
5353 KVM_REG_PPC_SIER2, 0x00000000);
5354 spr_register_kvm(env, SPR_POWER_SIER3, "SIER3",
5355 SPR_NOACCESS, SPR_NOACCESS,
5356 &spr_read_generic, &spr_write_generic,
5357 KVM_REG_PPC_SIER3, 0x00000000);
5358 }
5359
register_power10_pmu_user_sprs(CPUPPCState * env)5360 static void register_power10_pmu_user_sprs(CPUPPCState *env)
5361 {
5362 spr_register(env, SPR_POWER_UMMCR3, "UMMCR3",
5363 &spr_read_generic, &spr_write_generic,
5364 &spr_read_generic, &spr_write_generic,
5365 0x00000000);
5366 spr_register(env, SPR_POWER_USIER2, "USIER2",
5367 &spr_read_generic, SPR_NOACCESS,
5368 &spr_read_generic, &spr_write_generic,
5369 0x00000000);
5370 spr_register(env, SPR_POWER_USIER3, "USIER3",
5371 &spr_read_generic, SPR_NOACCESS,
5372 &spr_read_generic, &spr_write_generic,
5373 0x00000000);
5374 }
5375
register_power5p_ear_sprs(CPUPPCState * env)5376 static void register_power5p_ear_sprs(CPUPPCState *env)
5377 {
5378 /* External access control */
5379 spr_register(env, SPR_EAR, "EAR",
5380 SPR_NOACCESS, SPR_NOACCESS,
5381 &spr_read_generic, &spr_write_generic,
5382 0x00000000);
5383 }
5384
register_power5p_tb_sprs(CPUPPCState * env)5385 static void register_power5p_tb_sprs(CPUPPCState *env)
5386 {
5387 /* TBU40 (High 40 bits of the Timebase register */
5388 spr_register_hv(env, SPR_TBU40, "TBU40",
5389 SPR_NOACCESS, SPR_NOACCESS,
5390 SPR_NOACCESS, SPR_NOACCESS,
5391 SPR_NOACCESS, &spr_write_tbu40,
5392 0x00000000);
5393 }
5394
register_970_lpar_sprs(CPUPPCState * env)5395 static void register_970_lpar_sprs(CPUPPCState *env)
5396 {
5397 #if !defined(CONFIG_USER_ONLY)
5398 /*
5399 * PPC970: HID4 covers things later controlled by the LPCR and
5400 * RMOR in later CPUs, but with a different encoding. We only
5401 * support the 970 in "Apple mode" which has all hypervisor
5402 * facilities disabled by strapping, so we can basically just
5403 * ignore it
5404 */
5405 spr_register(env, SPR_970_HID4, "HID4",
5406 SPR_NOACCESS, SPR_NOACCESS,
5407 &spr_read_generic, &spr_write_generic,
5408 0x00000000);
5409 #endif
5410 }
5411
register_power5p_lpar_sprs(CPUPPCState * env)5412 static void register_power5p_lpar_sprs(CPUPPCState *env)
5413 {
5414 #if !defined(CONFIG_USER_ONLY)
5415 /* Logical partitioning */
5416 spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
5417 SPR_NOACCESS, SPR_NOACCESS,
5418 SPR_NOACCESS, SPR_NOACCESS,
5419 &spr_read_generic, &spr_write_lpcr,
5420 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
5421 spr_register_hv(env, SPR_HDEC, "HDEC",
5422 SPR_NOACCESS, SPR_NOACCESS,
5423 SPR_NOACCESS, SPR_NOACCESS,
5424 &spr_read_hdecr, &spr_write_hdecr, 0);
5425 #endif
5426 }
5427
register_book3s_ids_sprs(CPUPPCState * env)5428 static void register_book3s_ids_sprs(CPUPPCState *env)
5429 {
5430 /* FIXME: Will need to deal with thread vs core only SPRs */
5431
5432 /* Processor identification */
5433 spr_register_hv(env, SPR_PIR, "PIR",
5434 SPR_NOACCESS, SPR_NOACCESS,
5435 &spr_read_generic, SPR_NOACCESS,
5436 &spr_read_generic, NULL,
5437 0x00000000);
5438 spr_register_hv(env, SPR_LPIDR, "LPIDR",
5439 SPR_NOACCESS, SPR_NOACCESS,
5440 SPR_NOACCESS, SPR_NOACCESS,
5441 &spr_read_generic, &spr_write_lpidr,
5442 0x00000000);
5443 spr_register_hv(env, SPR_HFSCR, "HFSCR",
5444 SPR_NOACCESS, SPR_NOACCESS,
5445 SPR_NOACCESS, SPR_NOACCESS,
5446 &spr_read_generic, &spr_write_generic,
5447 0x00000000);
5448 spr_register_hv(env, SPR_MMCRC, "MMCRC",
5449 SPR_NOACCESS, SPR_NOACCESS,
5450 SPR_NOACCESS, SPR_NOACCESS,
5451 &spr_read_generic, &spr_core_write_generic32,
5452 0x00000000);
5453 spr_register_hv(env, SPR_MMCRH, "MMCRH",
5454 SPR_NOACCESS, SPR_NOACCESS,
5455 SPR_NOACCESS, SPR_NOACCESS,
5456 &spr_read_generic, &spr_write_generic,
5457 0x00000000);
5458 spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
5459 SPR_NOACCESS, SPR_NOACCESS,
5460 SPR_NOACCESS, SPR_NOACCESS,
5461 &spr_read_generic, &spr_write_generic,
5462 0x00000000);
5463 spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
5464 SPR_NOACCESS, SPR_NOACCESS,
5465 SPR_NOACCESS, SPR_NOACCESS,
5466 &spr_read_generic, &spr_write_generic,
5467 0x00000000);
5468 spr_register_hv(env, SPR_HSRR0, "HSRR0",
5469 SPR_NOACCESS, SPR_NOACCESS,
5470 SPR_NOACCESS, SPR_NOACCESS,
5471 &spr_read_generic, &spr_write_generic,
5472 0x00000000);
5473 spr_register_hv(env, SPR_HSRR1, "HSRR1",
5474 SPR_NOACCESS, SPR_NOACCESS,
5475 SPR_NOACCESS, SPR_NOACCESS,
5476 &spr_read_generic, &spr_write_generic,
5477 0x00000000);
5478 spr_register_hv(env, SPR_HDAR, "HDAR",
5479 SPR_NOACCESS, SPR_NOACCESS,
5480 SPR_NOACCESS, SPR_NOACCESS,
5481 &spr_read_generic, &spr_write_generic,
5482 0x00000000);
5483 spr_register_hv(env, SPR_HDSISR, "HDSISR",
5484 SPR_NOACCESS, SPR_NOACCESS,
5485 SPR_NOACCESS, SPR_NOACCESS,
5486 &spr_read_generic, &spr_write_generic32,
5487 0x00000000);
5488 spr_register_hv(env, SPR_HRMOR, "HRMOR",
5489 SPR_NOACCESS, SPR_NOACCESS,
5490 SPR_NOACCESS, SPR_NOACCESS,
5491 &spr_read_generic, &spr_core_write_generic,
5492 0x00000000);
5493 }
5494
register_rmor_sprs(CPUPPCState * env)5495 static void register_rmor_sprs(CPUPPCState *env)
5496 {
5497 spr_register_hv(env, SPR_RMOR, "RMOR",
5498 SPR_NOACCESS, SPR_NOACCESS,
5499 SPR_NOACCESS, SPR_NOACCESS,
5500 &spr_read_generic, &spr_write_generic,
5501 0x00000000);
5502 }
5503
register_power8_ids_sprs(CPUPPCState * env)5504 static void register_power8_ids_sprs(CPUPPCState *env)
5505 {
5506 /* Thread identification */
5507 spr_register(env, SPR_TIR, "TIR",
5508 SPR_NOACCESS, SPR_NOACCESS,
5509 &spr_read_generic, SPR_NOACCESS,
5510 0x00000000);
5511 }
5512
register_book3s_purr_sprs(CPUPPCState * env)5513 static void register_book3s_purr_sprs(CPUPPCState *env)
5514 {
5515 #if !defined(CONFIG_USER_ONLY)
5516 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
5517 spr_register_kvm_hv(env, SPR_PURR, "PURR",
5518 &spr_read_purr, SPR_NOACCESS,
5519 &spr_read_purr, SPR_NOACCESS,
5520 &spr_read_purr, &spr_write_purr,
5521 KVM_REG_PPC_PURR, 0x00000000);
5522 spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
5523 &spr_read_purr, SPR_NOACCESS,
5524 &spr_read_purr, SPR_NOACCESS,
5525 &spr_read_purr, &spr_write_purr,
5526 KVM_REG_PPC_SPURR, 0x00000000);
5527 #endif
5528 }
5529
register_power6_dbg_sprs(CPUPPCState * env)5530 static void register_power6_dbg_sprs(CPUPPCState *env)
5531 {
5532 #if !defined(CONFIG_USER_ONLY)
5533 spr_register(env, SPR_CFAR, "CFAR",
5534 SPR_NOACCESS, SPR_NOACCESS,
5535 &spr_read_cfar, &spr_write_cfar,
5536 0x00000000);
5537 #endif
5538 }
5539
register_power5p_common_sprs(CPUPPCState * env)5540 static void register_power5p_common_sprs(CPUPPCState *env)
5541 {
5542 spr_register_kvm(env, SPR_PPR, "PPR",
5543 &spr_read_generic, &spr_write_generic,
5544 &spr_read_generic, &spr_write_generic,
5545 KVM_REG_PPC_PPR, 0x00000000);
5546 }
5547
register_power6_common_sprs(CPUPPCState * env)5548 static void register_power6_common_sprs(CPUPPCState *env)
5549 {
5550 #if !defined(CONFIG_USER_ONLY)
5551 spr_register_kvm(env, SPR_DSCR, "DSCR",
5552 SPR_NOACCESS, SPR_NOACCESS,
5553 &spr_read_generic, &spr_write_generic,
5554 KVM_REG_PPC_DSCR, 0x00000000);
5555 #endif
5556 /*
5557 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
5558 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
5559 */
5560 spr_register_hv(env, SPR_PCR, "PCR",
5561 SPR_NOACCESS, SPR_NOACCESS,
5562 SPR_NOACCESS, SPR_NOACCESS,
5563 &spr_read_generic, &spr_write_pcr,
5564 0x00000000);
5565 }
5566
register_HEIR32_spr(CPUPPCState * env)5567 static void register_HEIR32_spr(CPUPPCState *env)
5568 {
5569 spr_register_hv(env, SPR_HEIR, "HEIR",
5570 SPR_NOACCESS, SPR_NOACCESS,
5571 SPR_NOACCESS, SPR_NOACCESS,
5572 &spr_read_generic, &spr_write_generic32,
5573 0x00000000);
5574 }
5575
register_HEIR64_spr(CPUPPCState * env)5576 static void register_HEIR64_spr(CPUPPCState *env)
5577 {
5578 spr_register_hv(env, SPR_HEIR, "HEIR",
5579 SPR_NOACCESS, SPR_NOACCESS,
5580 SPR_NOACCESS, SPR_NOACCESS,
5581 &spr_read_generic, &spr_write_generic,
5582 0x00000000);
5583 }
5584
register_power7_common_sprs(CPUPPCState * env)5585 static void register_power7_common_sprs(CPUPPCState *env)
5586 {
5587 spr_register(env, SPR_PPR32, "PPR32",
5588 &spr_read_ppr32, &spr_write_ppr32,
5589 &spr_read_ppr32, &spr_write_ppr32,
5590 0x00000000);
5591 }
5592
register_power8_tce_address_control_sprs(CPUPPCState * env)5593 static void register_power8_tce_address_control_sprs(CPUPPCState *env)
5594 {
5595 spr_register_kvm(env, SPR_TAR, "TAR",
5596 &spr_read_tar, &spr_write_tar,
5597 &spr_read_generic, &spr_write_generic,
5598 KVM_REG_PPC_TAR, 0x00000000);
5599 }
5600
register_power8_tm_sprs(CPUPPCState * env)5601 static void register_power8_tm_sprs(CPUPPCState *env)
5602 {
5603 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
5604 &spr_read_tm, &spr_write_tm,
5605 &spr_read_tm, &spr_write_tm,
5606 KVM_REG_PPC_TFHAR, 0x00000000);
5607 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
5608 &spr_read_tm, &spr_write_tm,
5609 &spr_read_tm, &spr_write_tm,
5610 KVM_REG_PPC_TFIAR, 0x00000000);
5611 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
5612 &spr_read_tm, &spr_write_tm,
5613 &spr_read_tm, &spr_write_tm,
5614 KVM_REG_PPC_TEXASR, 0x00000000);
5615 spr_register(env, SPR_TEXASRU, "TEXASRU",
5616 &spr_read_tm_upper32, &spr_write_tm_upper32,
5617 &spr_read_tm_upper32, &spr_write_tm_upper32,
5618 0x00000000);
5619 }
5620
register_power8_ebb_sprs(CPUPPCState * env)5621 static void register_power8_ebb_sprs(CPUPPCState *env)
5622 {
5623 spr_register(env, SPR_BESCRS, "BESCRS",
5624 &spr_read_ebb, &spr_write_ebb,
5625 &spr_read_generic, &spr_write_generic,
5626 0x00000000);
5627 spr_register(env, SPR_BESCRSU, "BESCRSU",
5628 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
5629 &spr_read_prev_upper32, &spr_write_prev_upper32,
5630 0x00000000);
5631 spr_register(env, SPR_BESCRR, "BESCRR",
5632 &spr_read_ebb, &spr_write_ebb,
5633 &spr_read_generic, &spr_write_generic,
5634 0x00000000);
5635 spr_register(env, SPR_BESCRRU, "BESCRRU",
5636 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
5637 &spr_read_prev_upper32, &spr_write_prev_upper32,
5638 0x00000000);
5639 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
5640 &spr_read_ebb, &spr_write_ebb,
5641 &spr_read_generic, &spr_write_generic,
5642 KVM_REG_PPC_EBBHR, 0x00000000);
5643 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
5644 &spr_read_ebb, &spr_write_ebb,
5645 &spr_read_generic, &spr_write_generic,
5646 KVM_REG_PPC_EBBRR, 0x00000000);
5647 spr_register_kvm(env, SPR_BESCR, "BESCR",
5648 &spr_read_ebb, &spr_write_ebb,
5649 &spr_read_generic, &spr_write_generic,
5650 KVM_REG_PPC_BESCR, 0x00000000);
5651 }
5652
5653 /* Virtual Time Base */
register_vtb_sprs(CPUPPCState * env)5654 static void register_vtb_sprs(CPUPPCState *env)
5655 {
5656 spr_register_kvm_hv(env, SPR_VTB, "VTB",
5657 SPR_NOACCESS, SPR_NOACCESS,
5658 &spr_read_vtb, SPR_NOACCESS,
5659 &spr_read_vtb, &spr_write_vtb,
5660 KVM_REG_PPC_VTB, 0x00000000);
5661 }
5662
register_power8_fscr_sprs(CPUPPCState * env)5663 static void register_power8_fscr_sprs(CPUPPCState *env)
5664 {
5665 #if defined(CONFIG_USER_ONLY)
5666 target_ulong initval = 1ULL << FSCR_TAR;
5667 #else
5668 target_ulong initval = 0;
5669 #endif
5670 spr_register_kvm(env, SPR_FSCR, "FSCR",
5671 SPR_NOACCESS, SPR_NOACCESS,
5672 &spr_read_generic, &spr_write_generic,
5673 KVM_REG_PPC_FSCR, initval);
5674 }
5675
register_power8_pspb_sprs(CPUPPCState * env)5676 static void register_power8_pspb_sprs(CPUPPCState *env)
5677 {
5678 spr_register_kvm(env, SPR_PSPB, "PSPB",
5679 SPR_NOACCESS, SPR_NOACCESS,
5680 &spr_read_generic, &spr_write_generic32,
5681 KVM_REG_PPC_PSPB, 0);
5682 }
5683
register_power8_dpdes_sprs(CPUPPCState * env)5684 static void register_power8_dpdes_sprs(CPUPPCState *env)
5685 {
5686 #if !defined(CONFIG_USER_ONLY)
5687 /* Directed Privileged Door-bell Exception State, used for IPI */
5688 spr_register_kvm_hv(env, SPR_DPDES, "DPDES",
5689 SPR_NOACCESS, SPR_NOACCESS,
5690 &spr_read_dpdes, SPR_NOACCESS,
5691 &spr_read_dpdes, &spr_write_dpdes,
5692 KVM_REG_PPC_DPDES, 0x00000000);
5693 #endif
5694 }
5695
register_power8_ic_sprs(CPUPPCState * env)5696 static void register_power8_ic_sprs(CPUPPCState *env)
5697 {
5698 #if !defined(CONFIG_USER_ONLY)
5699 spr_register_hv(env, SPR_IC, "IC",
5700 SPR_NOACCESS, SPR_NOACCESS,
5701 &spr_read_generic, SPR_NOACCESS,
5702 &spr_read_generic, &spr_write_generic,
5703 0);
5704 #endif
5705 }
5706
5707 /* SPRs specific to IBM POWER CPUs */
register_power_common_book4_sprs(CPUPPCState * env)5708 static void register_power_common_book4_sprs(CPUPPCState *env)
5709 {
5710 #if !defined(CONFIG_USER_ONLY)
5711 spr_register_hv(env, SPR_HID0, "HID0",
5712 SPR_NOACCESS, SPR_NOACCESS,
5713 SPR_NOACCESS, SPR_NOACCESS,
5714 &spr_read_generic, &spr_core_write_generic,
5715 0x00000000);
5716 spr_register_hv(env, SPR_TSCR, "TSCR",
5717 SPR_NOACCESS, SPR_NOACCESS,
5718 SPR_NOACCESS, SPR_NOACCESS,
5719 &spr_read_generic, &spr_core_write_generic32,
5720 0x00000000);
5721 spr_register_hv(env, SPR_HMER, "HMER",
5722 SPR_NOACCESS, SPR_NOACCESS,
5723 SPR_NOACCESS, SPR_NOACCESS,
5724 &spr_read_generic, &spr_write_hmer,
5725 0x00000000);
5726 spr_register_hv(env, SPR_HMEER, "HMEER",
5727 SPR_NOACCESS, SPR_NOACCESS,
5728 SPR_NOACCESS, SPR_NOACCESS,
5729 &spr_read_generic, &spr_core_write_generic,
5730 0x00000000);
5731 spr_register_hv(env, SPR_TFMR, "TFMR",
5732 SPR_NOACCESS, SPR_NOACCESS,
5733 SPR_NOACCESS, SPR_NOACCESS,
5734 &spr_read_tfmr, &spr_write_tfmr,
5735 0x00000000);
5736 spr_register_hv(env, SPR_TRIG1, "TRIG1",
5737 SPR_NOACCESS, SPR_NOACCESS,
5738 &spr_access_nop, &spr_write_generic,
5739 &spr_access_nop, &spr_write_generic,
5740 0x00000000);
5741 spr_register_hv(env, SPR_TRIG2, "TRIG2",
5742 SPR_NOACCESS, SPR_NOACCESS,
5743 &spr_access_nop, &spr_write_generic,
5744 &spr_access_nop, &spr_write_generic,
5745 0x00000000);
5746 spr_register_hv(env, SPR_LDBAR, "LDBAR",
5747 SPR_NOACCESS, SPR_NOACCESS,
5748 SPR_NOACCESS, SPR_NOACCESS,
5749 &spr_read_generic, &spr_core_lpar_write_generic,
5750 0x00000000);
5751 spr_register_hv(env, SPR_POWER_TTR, "TTR",
5752 SPR_NOACCESS, SPR_NOACCESS,
5753 SPR_NOACCESS, SPR_NOACCESS,
5754 &spr_read_generic, &spr_core_write_generic,
5755 0x00000000);
5756 #endif
5757 }
5758
register_power9_book4_sprs(CPUPPCState * env)5759 static void register_power9_book4_sprs(CPUPPCState *env)
5760 {
5761 /* Add a number of P9 book4 registers */
5762 register_power_common_book4_sprs(env);
5763 #if !defined(CONFIG_USER_ONLY)
5764 spr_register_kvm(env, SPR_WORT, "WORT",
5765 SPR_NOACCESS, SPR_NOACCESS,
5766 &spr_read_generic, &spr_write_generic,
5767 KVM_REG_PPC_WORT, 0);
5768 #endif
5769 }
5770
register_power8_book4_sprs(CPUPPCState * env)5771 static void register_power8_book4_sprs(CPUPPCState *env)
5772 {
5773 /* Add a number of P8 book4 registers */
5774 register_power_common_book4_sprs(env);
5775 #if !defined(CONFIG_USER_ONLY)
5776 spr_register_kvm(env, SPR_ACOP, "ACOP",
5777 SPR_NOACCESS, SPR_NOACCESS,
5778 &spr_read_generic, &spr_write_generic,
5779 KVM_REG_PPC_ACOP, 0);
5780 /* PID is only in BookE in ISA v2.07 */
5781 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR",
5782 SPR_NOACCESS, SPR_NOACCESS,
5783 &spr_read_generic, &spr_write_pidr,
5784 KVM_REG_PPC_PID, 0);
5785 spr_register_kvm(env, SPR_WORT, "WORT",
5786 SPR_NOACCESS, SPR_NOACCESS,
5787 &spr_read_generic, &spr_write_generic,
5788 KVM_REG_PPC_WORT, 0);
5789 /* SPRC/SPRD exist in earlier CPUs but only tested on POWER9/10 */
5790 spr_register_hv(env, SPR_POWER_SPRC, "SPRC",
5791 SPR_NOACCESS, SPR_NOACCESS,
5792 SPR_NOACCESS, SPR_NOACCESS,
5793 &spr_read_generic, &spr_write_sprc,
5794 0x00000000);
5795 spr_register_hv(env, SPR_POWER_SPRD, "SPRD",
5796 SPR_NOACCESS, SPR_NOACCESS,
5797 SPR_NOACCESS, SPR_NOACCESS,
5798 &spr_read_sprd, &spr_write_sprd,
5799 0x00000000);
5800 #endif
5801 }
5802
register_power7_book4_sprs(CPUPPCState * env)5803 static void register_power7_book4_sprs(CPUPPCState *env)
5804 {
5805 /* Add a number of P7 book4 registers */
5806 #if !defined(CONFIG_USER_ONLY)
5807 register_power_common_book4_sprs(env);
5808 spr_register_kvm(env, SPR_ACOP, "ACOP",
5809 SPR_NOACCESS, SPR_NOACCESS,
5810 &spr_read_generic, &spr_write_generic,
5811 KVM_REG_PPC_ACOP, 0);
5812 /* PID is only in BookE in ISA v2.06 */
5813 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR",
5814 SPR_NOACCESS, SPR_NOACCESS,
5815 &spr_read_generic, &spr_write_generic32,
5816 KVM_REG_PPC_PID, 0);
5817 #endif
5818 }
5819
register_power8_rpr_sprs(CPUPPCState * env)5820 static void register_power8_rpr_sprs(CPUPPCState *env)
5821 {
5822 #if !defined(CONFIG_USER_ONLY)
5823 spr_register_hv(env, SPR_RPR, "RPR",
5824 SPR_NOACCESS, SPR_NOACCESS,
5825 SPR_NOACCESS, SPR_NOACCESS,
5826 &spr_read_generic, &spr_core_write_generic,
5827 0x00000103070F1F3F);
5828 #endif
5829 }
5830
register_power9_mmu_sprs(CPUPPCState * env)5831 static void register_power9_mmu_sprs(CPUPPCState *env)
5832 {
5833 #if !defined(CONFIG_USER_ONLY)
5834 /* Partition Table Control */
5835 spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
5836 SPR_NOACCESS, SPR_NOACCESS,
5837 SPR_NOACCESS, SPR_NOACCESS,
5838 &spr_read_generic, &spr_write_ptcr,
5839 KVM_REG_PPC_PTCR, 0x00000000);
5840 /* Address Segment Descriptor Register */
5841 spr_register_hv(env, SPR_ASDR, "ASDR",
5842 SPR_NOACCESS, SPR_NOACCESS,
5843 SPR_NOACCESS, SPR_NOACCESS,
5844 &spr_read_generic, &spr_write_generic,
5845 0x0000000000000000);
5846 /* PID is part of the BookS ISA from v3.0 */
5847 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR",
5848 SPR_NOACCESS, SPR_NOACCESS,
5849 &spr_read_generic, &spr_write_pidr,
5850 KVM_REG_PPC_PID, 0);
5851 #endif
5852 }
5853
register_power10_hash_sprs(CPUPPCState * env)5854 static void register_power10_hash_sprs(CPUPPCState *env)
5855 {
5856 /*
5857 * it's the OS responsibility to generate a random value for the registers
5858 * in each process' context. So, initialize it with 0 here.
5859 */
5860 uint64_t hashkeyr_initial_value = 0, hashpkeyr_initial_value = 0;
5861 #if defined(CONFIG_USER_ONLY)
5862 /* in linux-user, setup the hash register with a random value */
5863 GRand *rand = g_rand_new();
5864 hashkeyr_initial_value =
5865 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand);
5866 hashpkeyr_initial_value =
5867 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand);
5868 g_rand_free(rand);
5869 #endif
5870 spr_register_kvm(env, SPR_HASHKEYR, "HASHKEYR",
5871 SPR_NOACCESS, SPR_NOACCESS,
5872 &spr_read_generic, &spr_write_generic,
5873 KVM_REG_PPC_HASHKEYR, hashkeyr_initial_value);
5874 spr_register_kvm_hv(env, SPR_HASHPKEYR, "HASHPKEYR",
5875 SPR_NOACCESS, SPR_NOACCESS,
5876 SPR_NOACCESS, SPR_NOACCESS,
5877 &spr_read_generic, &spr_write_generic,
5878 KVM_REG_PPC_HASHPKEYR, hashpkeyr_initial_value);
5879 }
5880
register_power10_dexcr_sprs(CPUPPCState * env)5881 static void register_power10_dexcr_sprs(CPUPPCState *env)
5882 {
5883 spr_register_kvm(env, SPR_DEXCR, "DEXCR",
5884 SPR_NOACCESS, SPR_NOACCESS,
5885 &spr_read_generic, &spr_write_generic, KVM_REG_PPC_DEXCR,
5886 0);
5887
5888 spr_register(env, SPR_UDEXCR, "UDEXCR",
5889 &spr_read_dexcr_ureg, SPR_NOACCESS,
5890 &spr_read_dexcr_ureg, SPR_NOACCESS,
5891 0);
5892
5893 spr_register_hv(env, SPR_HDEXCR, "HDEXCR",
5894 SPR_NOACCESS, SPR_NOACCESS,
5895 SPR_NOACCESS, SPR_NOACCESS,
5896 &spr_read_generic, &spr_write_generic,
5897 0);
5898
5899 spr_register(env, SPR_UHDEXCR, "UHDEXCR",
5900 &spr_read_dexcr_ureg, SPR_NOACCESS,
5901 &spr_read_dexcr_ureg, SPR_NOACCESS,
5902 0);
5903 }
5904
5905 /*
5906 * Initialize PMU counter overflow timers for Power8 and
5907 * newer Power chips when using TCG.
5908 */
init_tcg_pmu_power8(CPUPPCState * env)5909 static void init_tcg_pmu_power8(CPUPPCState *env)
5910 {
5911 /* Init PMU overflow timers */
5912 if (tcg_enabled()) {
5913 cpu_ppc_pmu_init(env);
5914 }
5915 }
5916
init_proc_book3s_common(CPUPPCState * env)5917 static void init_proc_book3s_common(CPUPPCState *env)
5918 {
5919 register_non_embedded_sprs(env);
5920 register_book3s_altivec_sprs(env);
5921 register_book3s_pmu_sup_sprs(env);
5922 register_book3s_pmu_user_sprs(env);
5923 register_book3s_ctrl_sprs(env);
5924 /*
5925 * Can't find information on what this should be on reset. This
5926 * value is the one used by 74xx processors.
5927 */
5928 vscr_init(env, 0x00010000);
5929
5930 spr_register(env, SPR_USPRG3, "USPRG3",
5931 &spr_read_ureg, SPR_NOACCESS,
5932 &spr_read_ureg, SPR_NOACCESS,
5933 0x00000000);
5934 }
5935
init_proc_970(CPUPPCState * env)5936 static void init_proc_970(CPUPPCState *env)
5937 {
5938 /* Common Registers */
5939 init_proc_book3s_common(env);
5940 register_sdr1_sprs(env);
5941 register_book3s_dbg_sprs(env);
5942
5943 /* 970 Specific Registers */
5944 register_970_hid_sprs(env);
5945 register_970_hior_sprs(env);
5946 register_low_BATs(env);
5947 register_970_pmu_sup_sprs(env);
5948 register_970_pmu_user_sprs(env);
5949 register_970_lpar_sprs(env);
5950 register_970_dbg_sprs(env);
5951
5952 /* env variables */
5953 env->dcache_line_size = 128;
5954 env->icache_line_size = 128;
5955
5956 /* Allocate hardware IRQ controller */
5957 init_excp_970(env);
5958 ppc970_irq_init(env_archcpu(env));
5959 }
5960
5961 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
5962 {
5963 DeviceClass *dc = DEVICE_CLASS(oc);
5964 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5965
5966 dc->desc = "PowerPC 970";
5967 pcc->init_proc = init_proc_970;
5968 pcc->check_pow = check_pow_970;
5969 pcc->check_attn = check_attn_hid0;
5970 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5971 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5972 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5973 PPC_FLOAT_STFIWX |
5974 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5975 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5976 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5977 PPC_64B | PPC_ALTIVEC |
5978 PPC_SEGMENT_64B | PPC_SLBI;
5979 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC;
5980 pcc->msr_mask = (1ull << MSR_SF) |
5981 (1ull << MSR_VR) |
5982 (1ull << MSR_POW) |
5983 (1ull << MSR_EE) |
5984 (1ull << MSR_PR) |
5985 (1ull << MSR_FP) |
5986 (1ull << MSR_ME) |
5987 (1ull << MSR_FE0) |
5988 (1ull << MSR_SE) |
5989 (1ull << MSR_DE) |
5990 (1ull << MSR_FE1) |
5991 (1ull << MSR_IR) |
5992 (1ull << MSR_DR) |
5993 (1ull << MSR_PMM) |
5994 (1ull << MSR_RI);
5995 pcc->mmu_model = POWERPC_MMU_64B;
5996 #if !defined(CONFIG_USER_ONLY)
5997 pcc->hash64_opts = &ppc_hash64_opts_basic;
5998 #endif
5999 pcc->excp_model = POWERPC_EXCP_970;
6000 pcc->bus_model = PPC_FLAGS_INPUT_970;
6001 pcc->bfd_mach = bfd_mach_ppc64;
6002 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6003 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6004 POWERPC_FLAG_BUS_CLK;
6005 pcc->l1_dcache_size = 0x8000;
6006 pcc->l1_icache_size = 0x10000;
6007 }
6008
init_proc_power5plus(CPUPPCState * env)6009 static void init_proc_power5plus(CPUPPCState *env)
6010 {
6011 /* Common Registers */
6012 init_proc_book3s_common(env);
6013 register_sdr1_sprs(env);
6014 register_book3s_dbg_sprs(env);
6015
6016 /* POWER5+ Specific Registers */
6017 register_970_hid_sprs(env);
6018 register_970_hior_sprs(env);
6019 register_low_BATs(env);
6020 register_970_pmu_sup_sprs(env);
6021 register_970_pmu_user_sprs(env);
6022 register_power5p_common_sprs(env);
6023 register_power5p_lpar_sprs(env);
6024 register_power5p_ear_sprs(env);
6025 register_power5p_tb_sprs(env);
6026
6027 /* env variables */
6028 env->dcache_line_size = 128;
6029 env->icache_line_size = 128;
6030
6031 /* Allocate hardware IRQ controller */
6032 init_excp_970(env);
6033 ppc970_irq_init(env_archcpu(env));
6034 }
6035
POWERPC_FAMILY(POWER5P)6036 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
6037 {
6038 DeviceClass *dc = DEVICE_CLASS(oc);
6039 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6040
6041 dc->fw_name = "PowerPC,POWER5";
6042 dc->desc = "POWER5+";
6043 pcc->init_proc = init_proc_power5plus;
6044 pcc->check_pow = check_pow_970;
6045 pcc->check_attn = check_attn_hid0;
6046 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6047 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6048 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6049 PPC_FLOAT_STFIWX |
6050 PPC_FLOAT_EXT |
6051 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6052 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6053 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6054 PPC_64B |
6055 PPC_POPCNTB |
6056 PPC_SEGMENT_64B | PPC_SLBI;
6057 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC;
6058 pcc->msr_mask = (1ull << MSR_SF) |
6059 (1ull << MSR_VR) |
6060 (1ull << MSR_POW) |
6061 (1ull << MSR_EE) |
6062 (1ull << MSR_PR) |
6063 (1ull << MSR_FP) |
6064 (1ull << MSR_ME) |
6065 (1ull << MSR_FE0) |
6066 (1ull << MSR_SE) |
6067 (1ull << MSR_DE) |
6068 (1ull << MSR_FE1) |
6069 (1ull << MSR_IR) |
6070 (1ull << MSR_DR) |
6071 (1ull << MSR_PMM) |
6072 (1ull << MSR_RI);
6073 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
6074 LPCR_RMI | LPCR_HDICE;
6075 pcc->mmu_model = POWERPC_MMU_2_03;
6076 #if !defined(CONFIG_USER_ONLY)
6077 pcc->hash64_opts = &ppc_hash64_opts_basic;
6078 pcc->lrg_decr_bits = 32;
6079 #endif
6080 pcc->excp_model = POWERPC_EXCP_970;
6081 pcc->bus_model = PPC_FLAGS_INPUT_970;
6082 pcc->bfd_mach = bfd_mach_ppc64;
6083 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6084 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6085 POWERPC_FLAG_BUS_CLK;
6086 pcc->l1_dcache_size = 0x8000;
6087 pcc->l1_icache_size = 0x10000;
6088 }
6089
init_proc_POWER7(CPUPPCState * env)6090 static void init_proc_POWER7(CPUPPCState *env)
6091 {
6092 /* Common Registers */
6093 init_proc_book3s_common(env);
6094 register_sdr1_sprs(env);
6095 register_book3s_dbg_sprs(env);
6096
6097 /* POWER7 Specific Registers */
6098 register_book3s_ids_sprs(env);
6099 register_rmor_sprs(env);
6100 register_amr_sprs(env);
6101 register_book3s_purr_sprs(env);
6102 register_power5p_common_sprs(env);
6103 register_power5p_lpar_sprs(env);
6104 register_power5p_ear_sprs(env);
6105 register_power5p_tb_sprs(env);
6106 register_power6_common_sprs(env);
6107 register_HEIR32_spr(env);
6108 register_power6_dbg_sprs(env);
6109 register_power7_common_sprs(env);
6110 register_power7_book4_sprs(env);
6111
6112 /* env variables */
6113 env->dcache_line_size = 128;
6114 env->icache_line_size = 128;
6115
6116 /* Allocate hardware IRQ controller */
6117 init_excp_POWER7(env);
6118 ppcPOWER7_irq_init(env_archcpu(env));
6119 }
6120
ppc_pvr_match_power7(PowerPCCPUClass * pcc,uint32_t pvr,bool best)6121 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6122 {
6123 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6124 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6125
6126 if (!best) {
6127 if (base == CPU_POWERPC_POWER7_BASE) {
6128 return true;
6129 }
6130 if (base == CPU_POWERPC_POWER7P_BASE) {
6131 return true;
6132 }
6133 }
6134
6135 if (base != pcc_base) {
6136 return false;
6137 }
6138
6139 return true;
6140 }
6141
POWERPC_FAMILY(POWER7)6142 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
6143 {
6144 DeviceClass *dc = DEVICE_CLASS(oc);
6145 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6146
6147 dc->fw_name = "PowerPC,POWER7";
6148 dc->desc = "POWER7";
6149 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_2_06_PLUS;
6150 pcc->pvr_match = ppc_pvr_match_power7;
6151 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
6152 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6153 pcc->init_proc = init_proc_POWER7;
6154 pcc->check_pow = check_pow_nocheck;
6155 pcc->check_attn = check_attn_hid0;
6156 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6157 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6158 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6159 PPC_FLOAT_FRSQRTES |
6160 PPC_FLOAT_STFIWX |
6161 PPC_FLOAT_EXT |
6162 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6163 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6164 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6165 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6166 PPC_SEGMENT_64B | PPC_SLBI |
6167 PPC_POPCNTB | PPC_POPCNTWD |
6168 PPC_CILDST;
6169 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
6170 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6171 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6172 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
6173 PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206;
6174 pcc->msr_mask = (1ull << MSR_SF) |
6175 (1ull << MSR_VR) |
6176 (1ull << MSR_VSX) |
6177 (1ull << MSR_EE) |
6178 (1ull << MSR_PR) |
6179 (1ull << MSR_FP) |
6180 (1ull << MSR_ME) |
6181 (1ull << MSR_FE0) |
6182 (1ull << MSR_SE) |
6183 (1ull << MSR_DE) |
6184 (1ull << MSR_FE1) |
6185 (1ull << MSR_IR) |
6186 (1ull << MSR_DR) |
6187 (1ull << MSR_PMM) |
6188 (1ull << MSR_RI) |
6189 (1ull << MSR_LE);
6190 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
6191 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6192 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
6193 LPCR_MER | LPCR_TC |
6194 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
6195 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
6196 pcc->mmu_model = POWERPC_MMU_2_06;
6197 #if !defined(CONFIG_USER_ONLY)
6198 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6199 pcc->lrg_decr_bits = 32;
6200 #endif
6201 pcc->excp_model = POWERPC_EXCP_POWER7;
6202 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6203 pcc->bfd_mach = bfd_mach_ppc64;
6204 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6205 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6206 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6207 POWERPC_FLAG_VSX;
6208 pcc->l1_dcache_size = 0x8000;
6209 pcc->l1_icache_size = 0x8000;
6210 }
6211
bhrb_init_state(CPUPPCState * env,target_long num_entries_log2)6212 static void bhrb_init_state(CPUPPCState *env, target_long num_entries_log2)
6213 {
6214 if (env->flags & POWERPC_FLAG_BHRB) {
6215 if (num_entries_log2 > BHRB_MAX_NUM_ENTRIES_LOG2) {
6216 num_entries_log2 = BHRB_MAX_NUM_ENTRIES_LOG2;
6217 }
6218 env->bhrb_num_entries = 1 << num_entries_log2;
6219 env->bhrb_base = (intptr_t)&env->bhrb[0];
6220 env->bhrb_offset_mask = (env->bhrb_num_entries * sizeof(uint64_t)) - 1;
6221 }
6222 }
6223
bhrb_reset_state(CPUPPCState * env)6224 static void bhrb_reset_state(CPUPPCState *env)
6225 {
6226 if (env->flags & POWERPC_FLAG_BHRB) {
6227 env->bhrb_offset = 0;
6228 env->bhrb_filter = 0;
6229 memset(env->bhrb, 0, sizeof(env->bhrb));
6230 }
6231 }
6232
6233 #define POWER8_BHRB_ENTRIES_LOG2 5
init_proc_POWER8(CPUPPCState * env)6234 static void init_proc_POWER8(CPUPPCState *env)
6235 {
6236 /* Common Registers */
6237 init_proc_book3s_common(env);
6238 register_sdr1_sprs(env);
6239 register_book3s_207_dbg_sprs(env);
6240
6241 /* Common TCG PMU */
6242 init_tcg_pmu_power8(env);
6243
6244 /* POWER8 Specific Registers */
6245 register_book3s_ids_sprs(env);
6246 register_rmor_sprs(env);
6247 register_amr_sprs(env);
6248 register_iamr_sprs(env);
6249 register_book3s_purr_sprs(env);
6250 register_power5p_common_sprs(env);
6251 register_power5p_lpar_sprs(env);
6252 register_power5p_ear_sprs(env);
6253 register_power5p_tb_sprs(env);
6254 register_power6_common_sprs(env);
6255 register_HEIR32_spr(env);
6256 register_power6_dbg_sprs(env);
6257 register_power7_common_sprs(env);
6258 register_power8_tce_address_control_sprs(env);
6259 register_power8_ids_sprs(env);
6260 register_power8_ebb_sprs(env);
6261 register_power8_fscr_sprs(env);
6262 register_power8_pmu_sup_sprs(env);
6263 register_power8_pmu_user_sprs(env);
6264 register_power8_tm_sprs(env);
6265 register_power8_pspb_sprs(env);
6266 register_power8_dpdes_sprs(env);
6267 register_vtb_sprs(env);
6268 register_power8_ic_sprs(env);
6269 register_power8_book4_sprs(env);
6270 register_power8_rpr_sprs(env);
6271
6272 /* env variables */
6273 env->dcache_line_size = 128;
6274 env->icache_line_size = 128;
6275
6276 bhrb_init_state(env, POWER8_BHRB_ENTRIES_LOG2);
6277
6278 /* Allocate hardware IRQ controller */
6279 init_excp_POWER8(env);
6280 ppcPOWER7_irq_init(env_archcpu(env));
6281 }
6282
ppc_pvr_match_power8(PowerPCCPUClass * pcc,uint32_t pvr,bool best)6283 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6284 {
6285 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6286 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6287
6288 if (!best) {
6289 if (base == CPU_POWERPC_POWER8_BASE) {
6290 return true;
6291 }
6292 if (base == CPU_POWERPC_POWER8E_BASE) {
6293 return true;
6294 }
6295 if (base == CPU_POWERPC_POWER8NVL_BASE) {
6296 return true;
6297 }
6298 }
6299 if (base != pcc_base) {
6300 return false;
6301 }
6302
6303 return true;
6304 }
6305
POWERPC_FAMILY(POWER8)6306 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
6307 {
6308 DeviceClass *dc = DEVICE_CLASS(oc);
6309 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6310
6311 dc->fw_name = "PowerPC,POWER8";
6312 dc->desc = "POWER8";
6313 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_2_07;
6314 pcc->pvr_match = ppc_pvr_match_power8;
6315 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6316 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6317 pcc->init_proc = init_proc_POWER8;
6318 pcc->check_pow = check_pow_nocheck;
6319 pcc->check_attn = check_attn_hid0;
6320 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6321 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6322 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6323 PPC_FLOAT_FRSQRTES |
6324 PPC_FLOAT_STFIWX |
6325 PPC_FLOAT_EXT |
6326 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6327 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6328 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6329 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6330 PPC_SEGMENT_64B | PPC_SLBI |
6331 PPC_POPCNTB | PPC_POPCNTWD |
6332 PPC_CILDST;
6333 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6334 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6335 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6336 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6337 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6338 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6339 PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC |
6340 PPC2_BCDA_ISA206;
6341 pcc->msr_mask = (1ull << MSR_SF) |
6342 (1ull << MSR_HV) |
6343 (1ull << MSR_TM) |
6344 (1ull << MSR_VR) |
6345 (1ull << MSR_VSX) |
6346 (1ull << MSR_EE) |
6347 (1ull << MSR_PR) |
6348 (1ull << MSR_FP) |
6349 (1ull << MSR_ME) |
6350 (1ull << MSR_FE0) |
6351 (1ull << MSR_SE) |
6352 (1ull << MSR_DE) |
6353 (1ull << MSR_FE1) |
6354 (1ull << MSR_IR) |
6355 (1ull << MSR_DR) |
6356 (1ull << MSR_PMM) |
6357 (1ull << MSR_RI) |
6358 (1ull << MSR_TS0) |
6359 (1ull << MSR_TS1) |
6360 (1ull << MSR_LE);
6361 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
6362 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6363 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
6364 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
6365 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
6366 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
6367 LPCR_P8_PECE3 | LPCR_P8_PECE4;
6368 pcc->mmu_model = POWERPC_MMU_2_07;
6369 #if !defined(CONFIG_USER_ONLY)
6370 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6371 pcc->lrg_decr_bits = 32;
6372 pcc->n_host_threads = 8;
6373 #endif
6374 pcc->excp_model = POWERPC_EXCP_POWER8;
6375 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6376 pcc->bfd_mach = bfd_mach_ppc64;
6377 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6378 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6379 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6380 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
6381 pcc->l1_dcache_size = 0x8000;
6382 pcc->l1_icache_size = 0x8000;
6383 }
6384
6385 #ifndef CONFIG_USER_ONLY
6386 /*
6387 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6388 * Encoded as array of int_32s in the form:
6389 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6390 * x -> AP encoding
6391 * y -> radix mode supported page size (encoded as a shift)
6392 */
6393 static struct ppc_radix_page_info POWER9_radix_page_info = {
6394 .count = 4,
6395 .entries = {
6396 0x0000000c, /* 4K - enc: 0x0 */
6397 0xa0000010, /* 64K - enc: 0x5 */
6398 0x20000015, /* 2M - enc: 0x1 */
6399 0x4000001e /* 1G - enc: 0x2 */
6400 }
6401 };
6402 #endif /* CONFIG_USER_ONLY */
6403
6404 #define POWER9_BHRB_ENTRIES_LOG2 5
register_power9_common_sprs(CPUPPCState * env)6405 static void register_power9_common_sprs(CPUPPCState *env)
6406 {
6407 /* Common Registers */
6408 init_proc_book3s_common(env);
6409 register_book3s_207_dbg_sprs(env);
6410
6411 /* Common TCG PMU */
6412 init_tcg_pmu_power8(env);
6413
6414 /* POWER8 Specific Registers */
6415 register_book3s_ids_sprs(env);
6416 register_amr_sprs(env);
6417 register_iamr_sprs(env);
6418 register_book3s_purr_sprs(env);
6419 register_power5p_common_sprs(env);
6420 register_power5p_lpar_sprs(env);
6421 register_power5p_ear_sprs(env);
6422 register_power5p_tb_sprs(env);
6423 register_power6_common_sprs(env);
6424 register_power6_dbg_sprs(env);
6425 register_power7_common_sprs(env);
6426 register_power8_tce_address_control_sprs(env);
6427 register_power8_ids_sprs(env);
6428 register_power8_ebb_sprs(env);
6429 register_power8_fscr_sprs(env);
6430 register_power8_pmu_sup_sprs(env);
6431 register_power8_pmu_user_sprs(env);
6432 register_power8_tm_sprs(env);
6433 register_power8_pspb_sprs(env);
6434 register_power8_dpdes_sprs(env);
6435 register_vtb_sprs(env);
6436 register_power8_ic_sprs(env);
6437 register_power9_book4_sprs(env);
6438 register_power8_rpr_sprs(env);
6439 register_power9_mmu_sprs(env);
6440
6441 /* FIXME: Filter fields properly based on privilege level */
6442 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
6443 spr_read_generic, spr_write_generic,
6444 KVM_REG_PPC_PSSCR, 0);
6445
6446 }
6447
init_proc_POWER9(CPUPPCState * env)6448 static void init_proc_POWER9(CPUPPCState *env)
6449 {
6450 register_power9_common_sprs(env);
6451 register_HEIR32_spr(env);
6452 /* POWER9 Specific registers */
6453 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
6454 spr_read_generic, spr_write_generic,
6455 KVM_REG_PPC_TIDR, 0);
6456 /* env variables */
6457 env->dcache_line_size = 128;
6458 env->icache_line_size = 128;
6459
6460 bhrb_init_state(env, POWER9_BHRB_ENTRIES_LOG2);
6461
6462 /* Allocate hardware IRQ controller */
6463 init_excp_POWER9(env);
6464 ppcPOWER9_irq_init(env_archcpu(env));
6465 }
6466
ppc_pvr_match_power9(PowerPCCPUClass * pcc,uint32_t pvr,bool best)6467 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6468 {
6469 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6470 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6471
6472 if (!best) {
6473 if (base == CPU_POWERPC_POWER9_BASE) {
6474 return true;
6475 }
6476 }
6477
6478 if (base != pcc_base) {
6479 return false;
6480 }
6481
6482 if ((pvr & 0x0f00) != (pcc->pvr & 0x0f00)) {
6483 /* Major DD version does not match */
6484 return false;
6485 }
6486
6487 if ((pvr & 0x0f00) == 0x200) {
6488 if ((pvr & 0xf) < 2) {
6489 /* DD2.0, DD2.1 match power9_v2.0 */
6490 if ((pcc->pvr & 0xf) == 0) {
6491 return true;
6492 }
6493 } else {
6494 /* DD2.2, DD2.3 match power9_v2.2 */
6495 if ((pcc->pvr & 0xf) == 2) {
6496 return true;
6497 }
6498 }
6499 }
6500
6501 return false;
6502 }
6503
POWERPC_FAMILY(POWER9)6504 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
6505 {
6506 DeviceClass *dc = DEVICE_CLASS(oc);
6507 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6508
6509 dc->fw_name = "PowerPC,POWER9";
6510 dc->desc = "POWER9";
6511 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_00;
6512 pcc->pvr_match = ppc_pvr_match_power9;
6513 pcc->pcr_mask = PPC_PCR_MASK_POWER9;
6514 pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER9;
6515 pcc->init_proc = init_proc_POWER9;
6516 pcc->check_pow = check_pow_nocheck;
6517 pcc->check_attn = check_attn_hid0_power9;
6518 pcc->insns_flags = PPC_INSNS_FLAGS_POWER9;
6519 pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER9;
6520 pcc->msr_mask = PPC_MSR_MASK_POWER9;
6521 pcc->lpcr_mask = PPC_LPCR_MASK_POWER9;
6522 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
6523 pcc->mmu_model = POWERPC_MMU_3_00;
6524 #if !defined(CONFIG_USER_ONLY)
6525 /* segment page size remain the same */
6526 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6527 pcc->radix_page_info = &POWER9_radix_page_info;
6528 pcc->lrg_decr_bits = 56;
6529 pcc->n_host_threads = 4;
6530 #endif
6531 pcc->excp_model = POWERPC_EXCP_POWER9;
6532 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6533 pcc->bfd_mach = bfd_mach_ppc64;
6534 pcc->flags = POWERPC_FLAGS_POWER9;
6535 pcc->l1_dcache_size = 0x8000;
6536 pcc->l1_icache_size = 0x8000;
6537 }
6538
6539 #ifndef CONFIG_USER_ONLY
6540 /*
6541 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6542 * Encoded as array of int_32s in the form:
6543 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6544 * x -> AP encoding
6545 * y -> radix mode supported page size (encoded as a shift)
6546 */
6547 static struct ppc_radix_page_info POWER10_radix_page_info = {
6548 .count = 4,
6549 .entries = {
6550 0x0000000c, /* 4K - enc: 0x0 */
6551 0xa0000010, /* 64K - enc: 0x5 */
6552 0x20000015, /* 2M - enc: 0x1 */
6553 0x4000001e /* 1G - enc: 0x2 */
6554 }
6555 };
6556 #endif /* !CONFIG_USER_ONLY */
6557
6558 #define POWER10_BHRB_ENTRIES_LOG2 5
init_proc_POWER10(CPUPPCState * env)6559 static void init_proc_POWER10(CPUPPCState *env)
6560 {
6561 register_power9_common_sprs(env);
6562 register_HEIR64_spr(env);
6563 register_power10_hash_sprs(env);
6564 register_power10_dexcr_sprs(env);
6565 register_power10_pmu_sup_sprs(env);
6566 register_power10_pmu_user_sprs(env);
6567 /* env variables */
6568 env->dcache_line_size = 128;
6569 env->icache_line_size = 128;
6570
6571 bhrb_init_state(env, POWER10_BHRB_ENTRIES_LOG2);
6572
6573 /* Allocate hardware IRQ controller */
6574 init_excp_POWER10(env);
6575 ppcPOWER9_irq_init(env_archcpu(env));
6576 }
6577
ppc_pvr_match_power10(PowerPCCPUClass * pcc,uint32_t pvr,bool best)6578 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6579 {
6580 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6581 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6582
6583 if (!best) {
6584 if (base == CPU_POWERPC_POWER10_BASE) {
6585 return true;
6586 }
6587 }
6588
6589 if (base != pcc_base) {
6590 return false;
6591 }
6592
6593 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) {
6594 /* Major DD version matches power10_v2.0 */
6595 return true;
6596 }
6597
6598 return false;
6599 }
6600
POWERPC_FAMILY(POWER10)6601 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
6602 {
6603 DeviceClass *dc = DEVICE_CLASS(oc);
6604 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6605
6606 dc->fw_name = "PowerPC,POWER10";
6607 dc->desc = "POWER10";
6608 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_10;
6609 pcc->pvr_match = ppc_pvr_match_power10;
6610 pcc->pcr_mask = PPC_PCR_MASK_POWER10;
6611 pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER10;
6612 pcc->init_proc = init_proc_POWER10;
6613 pcc->check_pow = check_pow_nocheck;
6614 pcc->check_attn = check_attn_hid0_power9;
6615 pcc->insns_flags = PPC_INSNS_FLAGS_POWER10;
6616 pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER10;
6617 pcc->msr_mask = PPC_MSR_MASK_POWER10;
6618 pcc->lpcr_mask = PPC_LPCR_MASK_POWER10;
6619
6620 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
6621 pcc->mmu_model = POWERPC_MMU_3_00;
6622 #if !defined(CONFIG_USER_ONLY)
6623 /* segment page size remain the same */
6624 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6625 pcc->radix_page_info = &POWER10_radix_page_info;
6626 pcc->lrg_decr_bits = 56;
6627 #endif
6628 pcc->excp_model = POWERPC_EXCP_POWER10;
6629 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6630 pcc->bfd_mach = bfd_mach_ppc64;
6631 pcc->flags = POWERPC_FLAGS_POWER10;
6632 pcc->l1_dcache_size = 0x8000;
6633 pcc->l1_icache_size = 0x8000;
6634 }
6635
init_proc_POWER11(CPUPPCState * env)6636 static void init_proc_POWER11(CPUPPCState *env)
6637 {
6638 init_proc_POWER10(env);
6639 }
6640
ppc_pvr_match_power11(PowerPCCPUClass * pcc,uint32_t pvr,bool best)6641 static bool ppc_pvr_match_power11(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6642 {
6643 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6644 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6645
6646 if (!best && (base == CPU_POWERPC_POWER11_BASE)) {
6647 return true;
6648 }
6649
6650 if (base != pcc_base) {
6651 return false;
6652 }
6653
6654 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) {
6655 return true;
6656 }
6657
6658 return false;
6659 }
6660
POWERPC_FAMILY(POWER11)6661 POWERPC_FAMILY(POWER11)(ObjectClass *oc, void *data)
6662 {
6663 DeviceClass *dc = DEVICE_CLASS(oc);
6664 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6665
6666 dc->fw_name = "PowerPC,POWER11";
6667 dc->desc = "POWER11";
6668 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_10_P11;
6669 pcc->pvr_match = ppc_pvr_match_power11;
6670 pcc->pcr_mask = PPC_PCR_MASK_POWER11;
6671 pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER11;
6672 pcc->init_proc = init_proc_POWER11;
6673 pcc->check_pow = check_pow_nocheck;
6674 pcc->check_attn = check_attn_hid0_power9;
6675 pcc->insns_flags = PPC_INSNS_FLAGS_POWER11;
6676 pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER11;
6677 pcc->msr_mask = PPC_MSR_MASK_POWER11;
6678 pcc->lpcr_mask = PPC_LPCR_MASK_POWER11;
6679
6680 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
6681 pcc->mmu_model = POWERPC_MMU_3_00;
6682 #if !defined(CONFIG_USER_ONLY)
6683 /* segment page size remain the same */
6684 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6685 pcc->radix_page_info = &POWER10_radix_page_info;
6686 pcc->lrg_decr_bits = 56;
6687 #endif
6688 pcc->excp_model = POWERPC_EXCP_POWER11;
6689 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6690 pcc->bfd_mach = bfd_mach_ppc64;
6691 pcc->flags = POWERPC_FLAGS_POWER11;
6692 pcc->l1_dcache_size = 0x8000;
6693 pcc->l1_icache_size = 0x8000;
6694 }
6695
6696 #if !defined(CONFIG_USER_ONLY)
cpu_ppc_set_vhyp(PowerPCCPU * cpu,PPCVirtualHypervisor * vhyp)6697 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
6698 {
6699 CPUPPCState *env = &cpu->env;
6700
6701 cpu->vhyp = vhyp;
6702 cpu->vhyp_class = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(vhyp);
6703
6704 /*
6705 * With a virtual hypervisor mode we never allow the CPU to go
6706 * hypervisor mode itself
6707 */
6708 env->msr_mask &= ~MSR_HVB;
6709 }
6710
cpu_ppc_set_1lpar(PowerPCCPU * cpu)6711 void cpu_ppc_set_1lpar(PowerPCCPU *cpu)
6712 {
6713 CPUPPCState *env = &cpu->env;
6714
6715 /*
6716 * pseries SMT means "LPAR per core" mode, e.g., msgsndp is usable
6717 * between threads. powernv be in either mode, and it mostly affects
6718 * supervisor visible registers and instructions.
6719 */
6720 if (env->flags & POWERPC_FLAG_SMT) {
6721 env->flags |= POWERPC_FLAG_SMT_1LPAR;
6722 }
6723 }
6724 #endif /* !defined(CONFIG_USER_ONLY) */
6725
6726 #endif /* defined(TARGET_PPC64) */
6727
6728 /*****************************************************************************/
6729 /* Generic CPU instantiation routine */
init_ppc_proc(PowerPCCPU * cpu)6730 static void init_ppc_proc(PowerPCCPU *cpu)
6731 {
6732 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6733 CPUPPCState *env = &cpu->env;
6734 #if !defined(CONFIG_USER_ONLY)
6735 int i;
6736
6737 /* Set all exception vectors to an invalid address */
6738 for (i = 0; i < POWERPC_EXCP_NB; i++) {
6739 env->excp_vectors[i] = (target_ulong)(-1ULL);
6740 }
6741 env->ivor_mask = 0x00000000;
6742 env->ivpr_mask = 0x00000000;
6743 /* Default MMU definitions */
6744 env->nb_BATs = 0;
6745 env->nb_tlb = 0;
6746 env->nb_ways = 0;
6747 env->tlb_type = TLB_NONE;
6748 #endif
6749 /* Register SPR common to all PowerPC implementations */
6750 register_generic_sprs(cpu);
6751
6752 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
6753 (*pcc->init_proc)(env);
6754
6755 /* MSR bits & flags consistency checks */
6756 if (env->msr_mask & (1 << 25)) {
6757 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
6758 case POWERPC_FLAG_SPE:
6759 case POWERPC_FLAG_VRE:
6760 break;
6761 default:
6762 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6763 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
6764 exit(1);
6765 }
6766 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
6767 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6768 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
6769 exit(1);
6770 }
6771 if (env->msr_mask & (1 << 17)) {
6772 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
6773 case POWERPC_FLAG_TGPR:
6774 case POWERPC_FLAG_CE:
6775 break;
6776 default:
6777 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6778 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
6779 exit(1);
6780 }
6781 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
6782 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6783 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
6784 exit(1);
6785 }
6786 if (env->msr_mask & (1 << 10)) {
6787 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
6788 POWERPC_FLAG_UBLE)) {
6789 case POWERPC_FLAG_SE:
6790 case POWERPC_FLAG_DWE:
6791 case POWERPC_FLAG_UBLE:
6792 break;
6793 default:
6794 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6795 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
6796 "POWERPC_FLAG_UBLE\n");
6797 exit(1);
6798 }
6799 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
6800 POWERPC_FLAG_UBLE)) {
6801 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6802 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
6803 "POWERPC_FLAG_UBLE\n");
6804 exit(1);
6805 }
6806 if (env->msr_mask & (1 << 9)) {
6807 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6808 case POWERPC_FLAG_BE:
6809 case POWERPC_FLAG_DE:
6810 break;
6811 default:
6812 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6813 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
6814 exit(1);
6815 }
6816 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6817 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6818 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
6819 exit(1);
6820 }
6821 if (env->msr_mask & (1 << 2)) {
6822 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
6823 case POWERPC_FLAG_PX:
6824 case POWERPC_FLAG_PMM:
6825 break;
6826 default:
6827 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6828 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
6829 exit(1);
6830 }
6831 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
6832 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6833 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
6834 exit(1);
6835 }
6836 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) {
6837 fprintf(stderr, "PowerPC flags inconsistency\n"
6838 "Should define the time-base and decrementer clock source\n");
6839 exit(1);
6840 }
6841 /* Allocate TLBs buffer when needed */
6842 #if !defined(CONFIG_USER_ONLY)
6843 if (env->nb_tlb) {
6844 switch (env->tlb_type) {
6845 case TLB_6XX:
6846 /* 6xx has separate TLBs for instructions and data hence times 2 */
6847 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, 2 * env->nb_tlb);
6848 break;
6849 case TLB_EMB:
6850 env->tlb.tlbe = g_new0(ppcemb_tlb_t, env->nb_tlb);
6851 break;
6852 case TLB_MAS:
6853 env->tlb.tlbm = g_new0(ppcmas_tlb_t, env->nb_tlb);
6854 break;
6855 }
6856 /* Pre-compute some useful values */
6857 env->tlb_per_way = env->nb_tlb / env->nb_ways;
6858 }
6859 #endif
6860 if (env->check_pow == NULL) {
6861 warn_report("no power management check handler registered."
6862 " Attempt QEMU to crash very soon !");
6863 }
6864
6865 if (env->check_attn == NULL) {
6866 warn_report("no attn check handler registered."
6867 " Attempt QEMU to crash very soon !");
6868 }
6869 }
6870
6871
ppc_cpu_realize(DeviceState * dev,Error ** errp)6872 static void ppc_cpu_realize(DeviceState *dev, Error **errp)
6873 {
6874 CPUState *cs = CPU(dev);
6875 PowerPCCPU *cpu = POWERPC_CPU(dev);
6876 CPUPPCState *env = &cpu->env;
6877 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6878 Error *local_err = NULL;
6879
6880 cpu_exec_realizefn(cs, &local_err);
6881 if (local_err != NULL) {
6882 error_propagate(errp, local_err);
6883 return;
6884 }
6885 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
6886 cpu->vcpu_id = cs->cpu_index;
6887 }
6888
6889 if (tcg_enabled()) {
6890 if (ppc_fixup_cpu(cpu) != 0) {
6891 error_setg(errp, "Unable to emulate selected CPU with TCG");
6892 goto unrealize;
6893 }
6894 }
6895
6896 create_ppc_opcodes(cpu, &local_err);
6897 if (local_err != NULL) {
6898 error_propagate(errp, local_err);
6899 goto unrealize;
6900 }
6901 init_ppc_proc(cpu);
6902
6903 ppc_gdb_init(cs, pcc);
6904 qemu_init_vcpu(cs);
6905
6906 pcc->parent_realize(dev, errp);
6907
6908 if (!ppc_cpu_core_single_threaded(cs)) {
6909 env->flags |= POWERPC_FLAG_SMT;
6910 }
6911
6912 return;
6913
6914 unrealize:
6915 cpu_exec_unrealizefn(cs);
6916 }
6917
ppc_cpu_unrealize(DeviceState * dev)6918 static void ppc_cpu_unrealize(DeviceState *dev)
6919 {
6920 PowerPCCPU *cpu = POWERPC_CPU(dev);
6921 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6922
6923 pcc->parent_unrealize(dev);
6924
6925 cpu_remove_sync(CPU(cpu));
6926
6927 destroy_ppc_opcodes(cpu);
6928 }
6929
ppc_cpu_compare_class_pvr(gconstpointer a,gconstpointer b)6930 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
6931 {
6932 ObjectClass *oc = (ObjectClass *)a;
6933 uint32_t pvr = *(uint32_t *)b;
6934 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
6935
6936 /* -cpu host does a PVR lookup during construction */
6937 if (unlikely(strcmp(object_class_get_name(oc),
6938 TYPE_HOST_POWERPC_CPU) == 0)) {
6939 return -1;
6940 }
6941
6942 return pcc->pvr == pvr ? 0 : -1;
6943 }
6944
ppc_cpu_class_by_pvr(uint32_t pvr)6945 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
6946 {
6947 GSList *list, *item;
6948 PowerPCCPUClass *pcc = NULL;
6949
6950 list = object_class_get_list(TYPE_POWERPC_CPU, false);
6951 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
6952 if (item != NULL) {
6953 pcc = POWERPC_CPU_CLASS(item->data);
6954 }
6955 g_slist_free(list);
6956
6957 return pcc;
6958 }
6959
ppc_cpu_compare_class_pvr_mask(gconstpointer a,gconstpointer b)6960 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
6961 {
6962 ObjectClass *oc = (ObjectClass *)a;
6963 uint32_t pvr = *(uint32_t *)b;
6964 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
6965
6966 /* -cpu host does a PVR lookup during construction */
6967 if (unlikely(strcmp(object_class_get_name(oc),
6968 TYPE_HOST_POWERPC_CPU) == 0)) {
6969 return -1;
6970 }
6971
6972 if (pcc->pvr_match(pcc, pvr, true)) {
6973 return 0;
6974 }
6975
6976 return -1;
6977 }
6978
ppc_cpu_class_by_pvr_mask(uint32_t pvr)6979 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
6980 {
6981 GSList *list, *item;
6982 PowerPCCPUClass *pcc = NULL;
6983
6984 list = object_class_get_list(TYPE_POWERPC_CPU, true);
6985 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
6986 if (item != NULL) {
6987 pcc = POWERPC_CPU_CLASS(item->data);
6988 }
6989 g_slist_free(list);
6990
6991 return pcc;
6992 }
6993
ppc_cpu_lookup_alias(const char * alias)6994 static const char *ppc_cpu_lookup_alias(const char *alias)
6995 {
6996 int ai;
6997
6998 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
6999 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
7000 return ppc_cpu_aliases[ai].model;
7001 }
7002 }
7003
7004 return NULL;
7005 }
7006
ppc_cpu_class_by_name(const char * name)7007 ObjectClass *ppc_cpu_class_by_name(const char *name)
7008 {
7009 char *cpu_model, *typename;
7010 ObjectClass *oc;
7011 const char *p;
7012 unsigned long pvr;
7013
7014 /*
7015 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
7016 * 0x prefix if present)
7017 */
7018 if (!qemu_strtoul(name, &p, 16, &pvr)) {
7019 int len = p - name;
7020 len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
7021 if ((len == 8) && (*p == '\0')) {
7022 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
7023 }
7024 }
7025
7026 /*
7027 * All ppc CPUs represent hardware that exists in the real world, i.e.: we
7028 * do not have a "max" CPU with all possible emulated features enabled.
7029 * Return the default CPU type for the machine because that has greater
7030 * chance of being useful as the "max" CPU.
7031 */
7032 #if !defined(CONFIG_USER_ONLY)
7033 if (strcmp(name, "max") == 0) {
7034 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
7035 if (mc) {
7036 return object_class_by_name(mc->default_cpu_type);
7037 }
7038 }
7039 #endif
7040
7041 cpu_model = g_ascii_strdown(name, -1);
7042 p = ppc_cpu_lookup_alias(cpu_model);
7043 if (p) {
7044 g_free(cpu_model);
7045 cpu_model = g_strdup(p);
7046 }
7047
7048 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
7049 oc = object_class_by_name(typename);
7050 g_free(typename);
7051 g_free(cpu_model);
7052
7053 return oc;
7054 }
7055
ppc_cpu_get_family_class(PowerPCCPUClass * pcc)7056 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
7057 {
7058 ObjectClass *oc = OBJECT_CLASS(pcc);
7059
7060 while (oc && !object_class_is_abstract(oc)) {
7061 oc = object_class_get_parent(oc);
7062 }
7063 assert(oc);
7064
7065 return POWERPC_CPU_CLASS(oc);
7066 }
7067
7068 /* Sort by PVR, ordering special case "host" last. */
ppc_cpu_list_compare(gconstpointer a,gconstpointer b)7069 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
7070 {
7071 ObjectClass *oc_a = (ObjectClass *)a;
7072 ObjectClass *oc_b = (ObjectClass *)b;
7073 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
7074 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
7075 const char *name_a = object_class_get_name(oc_a);
7076 const char *name_b = object_class_get_name(oc_b);
7077
7078 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
7079 return 1;
7080 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
7081 return -1;
7082 } else {
7083 /* Avoid an integer overflow during subtraction */
7084 if (pcc_a->pvr < pcc_b->pvr) {
7085 return -1;
7086 } else if (pcc_a->pvr > pcc_b->pvr) {
7087 return 1;
7088 } else {
7089 return 0;
7090 }
7091 }
7092 }
7093
ppc_cpu_list_entry(gpointer data,gpointer user_data)7094 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
7095 {
7096 ObjectClass *oc = data;
7097 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7098 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
7099 const char *typename = object_class_get_name(oc);
7100 char *name;
7101 int i;
7102
7103 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
7104 return;
7105 }
7106
7107 name = cpu_model_from_type(typename);
7108 qemu_printf(" %-16s PVR %08x\n", name, pcc->pvr);
7109 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
7110 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
7111 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
7112
7113 if (alias_oc != oc) {
7114 continue;
7115 }
7116 /*
7117 * If running with KVM, we might update the family alias later, so
7118 * avoid printing the wrong alias here and use "preferred" instead
7119 */
7120 if (strcmp(alias->alias, family->desc) == 0) {
7121 qemu_printf(" %-16s (alias for preferred %s CPU)\n",
7122 alias->alias, family->desc);
7123 } else {
7124 qemu_printf(" %-16s (alias for %s)\n",
7125 alias->alias, name);
7126 }
7127 }
7128 g_free(name);
7129 }
7130
ppc_cpu_list(void)7131 void ppc_cpu_list(void)
7132 {
7133 GSList *list;
7134
7135 qemu_printf("Available CPUs:\n");
7136 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7137 list = g_slist_sort(list, ppc_cpu_list_compare);
7138 g_slist_foreach(list, ppc_cpu_list_entry, NULL);
7139 g_slist_free(list);
7140
7141 #ifdef CONFIG_KVM
7142 qemu_printf("\n");
7143 qemu_printf(" %s\n", "host");
7144 #endif
7145 }
7146
ppc_cpu_set_pc(CPUState * cs,vaddr value)7147 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
7148 {
7149 PowerPCCPU *cpu = POWERPC_CPU(cs);
7150
7151 cpu->env.nip = value;
7152 }
7153
ppc_cpu_get_pc(CPUState * cs)7154 static vaddr ppc_cpu_get_pc(CPUState *cs)
7155 {
7156 PowerPCCPU *cpu = POWERPC_CPU(cs);
7157
7158 return cpu->env.nip;
7159 }
7160
7161 #ifdef CONFIG_TCG
ppc_restore_state_to_opc(CPUState * cs,const TranslationBlock * tb,const uint64_t * data)7162 static void ppc_restore_state_to_opc(CPUState *cs,
7163 const TranslationBlock *tb,
7164 const uint64_t *data)
7165 {
7166 PowerPCCPU *cpu = POWERPC_CPU(cs);
7167
7168 cpu->env.nip = data[0];
7169 }
7170 #endif /* CONFIG_TCG */
7171
ppc_cpu_has_work(CPUState * cs)7172 static bool ppc_cpu_has_work(CPUState *cs)
7173 {
7174 return cs->interrupt_request & CPU_INTERRUPT_HARD;
7175 }
7176
ppc_cpu_mmu_index(CPUState * cs,bool ifetch)7177 static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch)
7178 {
7179 return ppc_env_mmu_index(cpu_env(cs), ifetch);
7180 }
7181
ppc_cpu_reset_hold(Object * obj,ResetType type)7182 static void ppc_cpu_reset_hold(Object *obj, ResetType type)
7183 {
7184 CPUState *cs = CPU(obj);
7185 PowerPCCPU *cpu = POWERPC_CPU(cs);
7186 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(obj);
7187 CPUPPCState *env = &cpu->env;
7188 target_ulong msr;
7189 int i;
7190
7191 if (pcc->parent_phases.hold) {
7192 pcc->parent_phases.hold(obj, type);
7193 }
7194
7195 msr = (target_ulong)0;
7196 msr |= (target_ulong)MSR_HVB;
7197 msr |= (target_ulong)1 << MSR_EP;
7198 #if defined(DO_SINGLE_STEP) && 0
7199 /* Single step trace mode */
7200 msr |= (target_ulong)1 << MSR_SE;
7201 msr |= (target_ulong)1 << MSR_BE;
7202 #endif
7203 #if defined(CONFIG_USER_ONLY)
7204 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
7205 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
7206 msr |= (target_ulong)1 << MSR_FE1;
7207 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
7208 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
7209 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
7210 msr |= (target_ulong)1 << MSR_PR;
7211 #if defined(TARGET_PPC64)
7212 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
7213 #endif
7214 #if !TARGET_BIG_ENDIAN
7215 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
7216 if (!((env->msr_mask >> MSR_LE) & 1)) {
7217 fprintf(stderr, "Selected CPU does not support little-endian.\n");
7218 exit(1);
7219 }
7220 #endif
7221 #endif
7222
7223 #if defined(TARGET_PPC64)
7224 if (mmu_is_64bit(env->mmu_model)) {
7225 msr |= (1ULL << MSR_SF);
7226 }
7227 #endif
7228
7229 hreg_store_msr(env, msr, 1);
7230
7231 #if !defined(CONFIG_USER_ONLY)
7232 env->nip = env->hreset_vector | env->excp_prefix;
7233
7234 if (tcg_enabled()) {
7235 cpu_breakpoint_remove_all(cs, BP_CPU);
7236 cpu_watchpoint_remove_all(cs, BP_CPU);
7237 if (env->mmu_model != POWERPC_MMU_REAL) {
7238 ppc_tlb_invalidate_all(env);
7239 }
7240 pmu_mmcr01a_updated(env);
7241 }
7242
7243 /* clean any pending stop state */
7244 env->resume_as_sreset = 0;
7245 #endif
7246 hreg_compute_hflags(env);
7247 env->reserve_addr = (target_ulong)-1ULL;
7248 /* Be sure no exception or interrupt is pending */
7249 env->pending_interrupts = 0;
7250 cs->exception_index = POWERPC_EXCP_NONE;
7251 env->error_code = 0;
7252 ppc_irq_reset(cpu);
7253
7254 /* tininess for underflow is detected before rounding */
7255 set_float_detect_tininess(float_tininess_before_rounding,
7256 &env->fp_status);
7257 /*
7258 * PowerPC propagation rules:
7259 * 1. A if it sNaN or qNaN
7260 * 2. B if it sNaN or qNaN
7261 * A signaling NaN is always silenced before returning it.
7262 */
7263 set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
7264 set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
7265
7266 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
7267 ppc_spr_t *spr = &env->spr_cb[i];
7268
7269 if (!spr->name) {
7270 continue;
7271 }
7272 env->spr[i] = spr->default_value;
7273 }
7274
7275 #if defined(TARGET_PPC64)
7276 bhrb_reset_state(env);
7277 #endif
7278 }
7279
7280 #ifndef CONFIG_USER_ONLY
7281
ppc_cpu_is_big_endian(CPUState * cs)7282 static bool ppc_cpu_is_big_endian(CPUState *cs)
7283 {
7284 cpu_synchronize_state(cs);
7285
7286 return !FIELD_EX64(cpu_env(cs)->msr, MSR, LE);
7287 }
7288
ppc_get_irq_stats(InterruptStatsProvider * obj,uint64_t ** irq_counts,unsigned int * nb_irqs)7289 static bool ppc_get_irq_stats(InterruptStatsProvider *obj,
7290 uint64_t **irq_counts, unsigned int *nb_irqs)
7291 {
7292 CPUPPCState *env = &POWERPC_CPU(obj)->env;
7293
7294 *irq_counts = env->excp_stats;
7295 *nb_irqs = ARRAY_SIZE(env->excp_stats);
7296 return true;
7297 }
7298
7299 #ifdef CONFIG_TCG
ppc_cpu_exec_enter(CPUState * cs)7300 static void ppc_cpu_exec_enter(CPUState *cs)
7301 {
7302 PowerPCCPU *cpu = POWERPC_CPU(cs);
7303
7304 if (cpu->vhyp) {
7305 cpu->vhyp_class->cpu_exec_enter(cpu->vhyp, cpu);
7306 }
7307 }
7308
ppc_cpu_exec_exit(CPUState * cs)7309 static void ppc_cpu_exec_exit(CPUState *cs)
7310 {
7311 PowerPCCPU *cpu = POWERPC_CPU(cs);
7312
7313 if (cpu->vhyp) {
7314 cpu->vhyp_class->cpu_exec_exit(cpu->vhyp, cpu);
7315 }
7316 }
7317 #endif /* CONFIG_TCG */
7318
7319 #endif /* !CONFIG_USER_ONLY */
7320
ppc_cpu_instance_init(Object * obj)7321 static void ppc_cpu_instance_init(Object *obj)
7322 {
7323 PowerPCCPU *cpu = POWERPC_CPU(obj);
7324 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7325 CPUPPCState *env = &cpu->env;
7326
7327 cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
7328
7329 env->msr_mask = pcc->msr_mask;
7330 env->mmu_model = pcc->mmu_model;
7331 env->excp_model = pcc->excp_model;
7332 env->bus_model = pcc->bus_model;
7333 env->insns_flags = pcc->insns_flags;
7334 env->insns_flags2 = pcc->insns_flags2;
7335 env->flags = pcc->flags;
7336 env->bfd_mach = pcc->bfd_mach;
7337 env->check_pow = pcc->check_pow;
7338 env->check_attn = pcc->check_attn;
7339
7340 /*
7341 * Mark HV mode as supported if the CPU has an MSR_HV bit in the
7342 * msr_mask. The mask can later be cleared by PAPR mode but the hv
7343 * mode support will remain, thus enforcing that we cannot use
7344 * priv. instructions in guest in PAPR mode. For 970 we currently
7345 * simply don't set HV in msr_mask thus simulating an "Apple mode"
7346 * 970. If we ever want to support 970 HV mode, we'll have to add
7347 * a processor attribute of some sort.
7348 */
7349 #if !defined(CONFIG_USER_ONLY)
7350 env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
7351 #endif
7352
7353 ppc_hash64_init(cpu);
7354 }
7355
ppc_cpu_instance_finalize(Object * obj)7356 static void ppc_cpu_instance_finalize(Object *obj)
7357 {
7358 PowerPCCPU *cpu = POWERPC_CPU(obj);
7359
7360 ppc_hash64_finalize(cpu);
7361 }
7362
ppc_pvr_match_default(PowerPCCPUClass * pcc,uint32_t pvr,bool best)7363 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
7364 {
7365 return pcc->pvr == pvr;
7366 }
7367
ppc_disas_set_info(CPUState * cs,disassemble_info * info)7368 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
7369 {
7370 CPUPPCState *env = cpu_env(cs);
7371
7372 if ((env->hflags >> MSR_LE) & 1) {
7373 info->endian = BFD_ENDIAN_LITTLE;
7374 }
7375 info->mach = env->bfd_mach;
7376 if (!env->bfd_mach) {
7377 #ifdef TARGET_PPC64
7378 info->mach = bfd_mach_ppc64;
7379 #else
7380 info->mach = bfd_mach_ppc;
7381 #endif
7382 }
7383
7384 info->cap_arch = CS_ARCH_PPC;
7385 #ifdef TARGET_PPC64
7386 info->cap_mode = CS_MODE_64;
7387 #endif
7388 }
7389
7390 static Property ppc_cpu_properties[] = {
7391 /* add default property here */
7392 DEFINE_PROP_END_OF_LIST(),
7393 };
7394
7395 #ifndef CONFIG_USER_ONLY
7396 #include "hw/core/sysemu-cpu-ops.h"
7397
7398 static const struct SysemuCPUOps ppc_sysemu_ops = {
7399 .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
7400 .write_elf32_note = ppc32_cpu_write_elf32_note,
7401 .write_elf64_note = ppc64_cpu_write_elf64_note,
7402 .virtio_is_big_endian = ppc_cpu_is_big_endian,
7403 .legacy_vmsd = &vmstate_ppc_cpu,
7404 };
7405 #endif
7406
7407 #ifdef CONFIG_TCG
7408 #include "hw/core/tcg-cpu-ops.h"
7409
7410 static const TCGCPUOps ppc_tcg_ops = {
7411 .initialize = ppc_translate_init,
7412 .restore_state_to_opc = ppc_restore_state_to_opc,
7413
7414 #ifdef CONFIG_USER_ONLY
7415 .record_sigsegv = ppc_cpu_record_sigsegv,
7416 #else
7417 .tlb_fill = ppc_cpu_tlb_fill,
7418 .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
7419 .cpu_exec_halt = ppc_cpu_has_work,
7420 .do_interrupt = ppc_cpu_do_interrupt,
7421 .cpu_exec_enter = ppc_cpu_exec_enter,
7422 .cpu_exec_exit = ppc_cpu_exec_exit,
7423 .do_unaligned_access = ppc_cpu_do_unaligned_access,
7424 .do_transaction_failed = ppc_cpu_do_transaction_failed,
7425 .debug_excp_handler = ppc_cpu_debug_excp_handler,
7426 .debug_check_breakpoint = ppc_cpu_debug_check_breakpoint,
7427 .debug_check_watchpoint = ppc_cpu_debug_check_watchpoint,
7428 #endif /* !CONFIG_USER_ONLY */
7429 };
7430 #endif /* CONFIG_TCG */
7431
ppc_cpu_class_init(ObjectClass * oc,void * data)7432 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
7433 {
7434 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7435 CPUClass *cc = CPU_CLASS(oc);
7436 DeviceClass *dc = DEVICE_CLASS(oc);
7437 ResettableClass *rc = RESETTABLE_CLASS(oc);
7438
7439 device_class_set_parent_realize(dc, ppc_cpu_realize,
7440 &pcc->parent_realize);
7441 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
7442 &pcc->parent_unrealize);
7443 pcc->pvr_match = ppc_pvr_match_default;
7444 device_class_set_props(dc, ppc_cpu_properties);
7445
7446 resettable_class_set_parent_phases(rc, NULL, ppc_cpu_reset_hold, NULL,
7447 &pcc->parent_phases);
7448
7449 cc->class_by_name = ppc_cpu_class_by_name;
7450 cc->has_work = ppc_cpu_has_work;
7451 cc->mmu_index = ppc_cpu_mmu_index;
7452 cc->dump_state = ppc_cpu_dump_state;
7453 cc->set_pc = ppc_cpu_set_pc;
7454 cc->get_pc = ppc_cpu_get_pc;
7455 cc->gdb_read_register = ppc_cpu_gdb_read_register;
7456 cc->gdb_write_register = ppc_cpu_gdb_write_register;
7457 #ifndef CONFIG_USER_ONLY
7458 cc->sysemu_ops = &ppc_sysemu_ops;
7459 INTERRUPT_STATS_PROVIDER_CLASS(oc)->get_statistics = ppc_get_irq_stats;
7460
7461 /* check_prot_access_type relies on MMU access and PAGE bits relations */
7462 qemu_build_assert(MMU_DATA_LOAD == 0 && MMU_DATA_STORE == 1 &&
7463 MMU_INST_FETCH == 2 && PAGE_READ == 1 &&
7464 PAGE_WRITE == 2 && PAGE_EXEC == 4);
7465 #endif
7466
7467 cc->gdb_num_core_regs = 71;
7468 #ifdef USE_APPLE_GDB
7469 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
7470 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
7471 cc->gdb_num_core_regs = 71 + 32;
7472 #endif
7473
7474 cc->gdb_arch_name = ppc_gdb_arch_name;
7475 #if defined(TARGET_PPC64)
7476 cc->gdb_core_xml_file = "power64-core.xml";
7477 #else
7478 cc->gdb_core_xml_file = "power-core.xml";
7479 #endif
7480 cc->disas_set_info = ppc_disas_set_info;
7481
7482 dc->fw_name = "PowerPC,UNKNOWN";
7483
7484 #ifdef CONFIG_TCG
7485 cc->tcg_ops = &ppc_tcg_ops;
7486 #endif /* CONFIG_TCG */
7487 }
7488
7489 static const TypeInfo ppc_cpu_type_info = {
7490 .name = TYPE_POWERPC_CPU,
7491 .parent = TYPE_CPU,
7492 .instance_size = sizeof(PowerPCCPU),
7493 .instance_align = __alignof__(PowerPCCPU),
7494 .instance_init = ppc_cpu_instance_init,
7495 .instance_finalize = ppc_cpu_instance_finalize,
7496 .abstract = true,
7497 .class_size = sizeof(PowerPCCPUClass),
7498 .class_init = ppc_cpu_class_init,
7499 #ifndef CONFIG_USER_ONLY
7500 .interfaces = (InterfaceInfo[]) {
7501 { TYPE_INTERRUPT_STATS_PROVIDER },
7502 { }
7503 },
7504 #endif
7505 };
7506
7507 #ifndef CONFIG_USER_ONLY
7508 static const TypeInfo ppc_vhyp_type_info = {
7509 .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
7510 .parent = TYPE_INTERFACE,
7511 .class_size = sizeof(PPCVirtualHypervisorClass),
7512 };
7513 #endif
7514
ppc_cpu_register_types(void)7515 static void ppc_cpu_register_types(void)
7516 {
7517 type_register_static(&ppc_cpu_type_info);
7518 #ifndef CONFIG_USER_ONLY
7519 type_register_static(&ppc_vhyp_type_info);
7520 #endif
7521 }
7522
ppc_cpu_dump_state(CPUState * cs,FILE * f,int flags)7523 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
7524 {
7525 #define RGPL 4
7526 #define RFPL 4
7527
7528 CPUPPCState *env = cpu_env(cs);
7529 int i;
7530
7531 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
7532 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
7533 env->nip, env->lr, env->ctr, cpu_read_xer(env),
7534 cs->cpu_index);
7535 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
7536 "%08x iidx %d didx %d\n",
7537 env->msr, env->spr[SPR_HID0], env->hflags,
7538 ppc_env_mmu_index(env, true), ppc_env_mmu_index(env, false));
7539 #if !defined(CONFIG_USER_ONLY)
7540 if (env->tb_env) {
7541 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
7542 " DECR " TARGET_FMT_lu "\n", cpu_ppc_load_tbu(env),
7543 cpu_ppc_load_tbl(env), cpu_ppc_load_decr(env));
7544 }
7545 #else
7546 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 "\n", cpu_ppc_load_tbu(env),
7547 cpu_ppc_load_tbl(env));
7548 #endif
7549 for (i = 0; i < 32; i++) {
7550 if ((i & (RGPL - 1)) == 0) {
7551 qemu_fprintf(f, "GPR%02d", i);
7552 }
7553 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
7554 if ((i & (RGPL - 1)) == (RGPL - 1)) {
7555 qemu_fprintf(f, "\n");
7556 }
7557 }
7558 qemu_fprintf(f, "CR ");
7559 for (i = 0; i < 8; i++)
7560 qemu_fprintf(f, "%01x", env->crf[i]);
7561 qemu_fprintf(f, " [");
7562 for (i = 0; i < 8; i++) {
7563 char a = '-';
7564 if (env->crf[i] & 0x08) {
7565 a = 'L';
7566 } else if (env->crf[i] & 0x04) {
7567 a = 'G';
7568 } else if (env->crf[i] & 0x02) {
7569 a = 'E';
7570 }
7571 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7572 }
7573 qemu_fprintf(f, " ] RES %03x@" TARGET_FMT_lx "\n",
7574 (int)env->reserve_length, env->reserve_addr);
7575
7576 if (flags & CPU_DUMP_FPU) {
7577 for (i = 0; i < 32; i++) {
7578 if ((i & (RFPL - 1)) == 0) {
7579 qemu_fprintf(f, "FPR%02d", i);
7580 }
7581 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
7582 if ((i & (RFPL - 1)) == (RFPL - 1)) {
7583 qemu_fprintf(f, "\n");
7584 }
7585 }
7586 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
7587 }
7588
7589 #if !defined(CONFIG_USER_ONLY)
7590 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
7591 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
7592 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
7593 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
7594
7595 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
7596 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
7597 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
7598 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
7599
7600 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
7601 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
7602 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
7603 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
7604
7605 switch (env->excp_model) {
7606 #if defined(TARGET_PPC64)
7607 case POWERPC_EXCP_POWER7:
7608 case POWERPC_EXCP_POWER8:
7609 case POWERPC_EXCP_POWER9:
7610 case POWERPC_EXCP_POWER10:
7611 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
7612 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
7613 break;
7614 #endif
7615 case POWERPC_EXCP_BOOKE:
7616 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
7617 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
7618 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
7619 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
7620
7621 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7622 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7623 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
7624 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
7625
7626 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
7627 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
7628 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
7629 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
7630
7631 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
7632 " EPR " TARGET_FMT_lx "\n",
7633 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
7634 env->spr[SPR_BOOKE_EPR]);
7635
7636 /* FSL-specific */
7637 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
7638 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
7639 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
7640 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
7641
7642 /*
7643 * IVORs are left out as they are large and do not change often --
7644 * they can be read with "p $ivor0", "p $ivor1", etc.
7645 */
7646 break;
7647 case POWERPC_EXCP_40x:
7648 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7649 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7650 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
7651 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]);
7652
7653 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx
7654 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7655 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2],
7656 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]);
7657 break;
7658 default:
7659 break;
7660 }
7661
7662 #if defined(TARGET_PPC64)
7663 if (env->flags & POWERPC_FLAG_CFAR) {
7664 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
7665 }
7666 #endif
7667
7668 if (env->spr_cb[SPR_LPCR].name) {
7669 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
7670 }
7671
7672 switch (env->mmu_model) {
7673 case POWERPC_MMU_32B:
7674 case POWERPC_MMU_SOFT_6xx:
7675 #if defined(TARGET_PPC64)
7676 case POWERPC_MMU_64B:
7677 case POWERPC_MMU_2_03:
7678 case POWERPC_MMU_2_06:
7679 case POWERPC_MMU_2_07:
7680 case POWERPC_MMU_3_00:
7681 #endif
7682 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
7683 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
7684 }
7685 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
7686 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
7687 }
7688 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
7689 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
7690 break;
7691 case POWERPC_MMU_BOOKE206:
7692 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
7693 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
7694 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
7695 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
7696
7697 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
7698 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7699 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
7700 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
7701
7702 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
7703 " TLB1CFG " TARGET_FMT_lx "\n",
7704 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
7705 env->spr[SPR_BOOKE_TLB1CFG]);
7706 break;
7707 default:
7708 break;
7709 }
7710 #endif
7711
7712 #undef RGPL
7713 #undef RFPL
7714 }
7715 type_init(ppc_cpu_register_types)
7716