xref: /openbmc/u-boot/arch/m68k/include/asm/immap_5235.h (revision 83d290c56fab2d38cd1ab4c4cc7099559c1d5046)
1  /* SPDX-License-Identifier: GPL-2.0+ */
2  /*
3   * MCF5329 Internal Memory Map
4   *
5   * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6   * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7   */
8  
9  #ifndef __IMMAP_5235__
10  #define __IMMAP_5235__
11  
12  #define MMAP_SCM	(CONFIG_SYS_MBAR + 0x00000000)
13  #define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x00000040)
14  #define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00000080)
15  #define MMAP_DMA0	(CONFIG_SYS_MBAR + 0x00000100)
16  #define MMAP_DMA1	(CONFIG_SYS_MBAR + 0x00000110)
17  #define MMAP_DMA2	(CONFIG_SYS_MBAR + 0x00000120)
18  #define MMAP_DMA3	(CONFIG_SYS_MBAR + 0x00000130)
19  #define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00000200)
20  #define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000240)
21  #define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00000280)
22  #define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00000300)
23  #define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x00000340)
24  #define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00000400)
25  #define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00000440)
26  #define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00000480)
27  #define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x000004C0)
28  #define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00000C00)
29  #define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x00000D00)
30  #define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00000F00)
31  #define MMAP_FEC	(CONFIG_SYS_MBAR + 0x00001000)
32  #define MMAP_FECFIFO	(CONFIG_SYS_MBAR + 0x00001400)
33  #define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00100000)
34  #define MMAP_CCM	(CONFIG_SYS_MBAR + 0x00110000)
35  #define MMAP_PLL	(CONFIG_SYS_MBAR + 0x00120000)
36  #define MMAP_EPORT	(CONFIG_SYS_MBAR + 0x00130000)
37  #define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x00140000)
38  #define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00150000)
39  #define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00160000)
40  #define MMAP_PIT2	(CONFIG_SYS_MBAR + 0x00170000)
41  #define MMAP_PIT3	(CONFIG_SYS_MBAR + 0x00180000)
42  #define MMAP_MDHA	(CONFIG_SYS_MBAR + 0x00190000)
43  #define MMAP_RNG	(CONFIG_SYS_MBAR + 0x001A0000)
44  #define MMAP_SKHA	(CONFIG_SYS_MBAR + 0x001B0000)
45  #define MMAP_CAN1	(CONFIG_SYS_MBAR + 0x001C0000)
46  #define MMAP_ETPU	(CONFIG_SYS_MBAR + 0x001D0000)
47  #define MMAP_CAN2	(CONFIG_SYS_MBAR + 0x001F0000)
48  
49  #include <asm/coldfire/eport.h>
50  #include <asm/coldfire/flexbus.h>
51  #include <asm/coldfire/flexcan.h>
52  #include <asm/coldfire/intctrl.h>
53  #include <asm/coldfire/mdha.h>
54  #include <asm/coldfire/qspi.h>
55  #include <asm/coldfire/rng.h>
56  #include <asm/coldfire/skha.h>
57  
58  /* System Control Module register */
59  typedef struct scm_ctrl {
60  	u32 ipsbar;		/* 0x00 - MBAR */
61  	u32 res1;		/* 0x04 */
62  	u32 rambar;		/* 0x08 - RAMBAR */
63  	u32 res2;		/* 0x0C */
64  	u8 crsr;		/* 0x10 Core Reset Status Register */
65  	u8 cwcr;		/* 0x11 Core Watchdog Control Register */
66  	u8 lpicr;		/* 0x12 Low-Power Interrupt Control Register */
67  	u8 cwsr;		/* 0x13 Core Watchdog Service Register */
68  	u32 dmareqc;		/* 0x14 */
69  	u32 res3;		/* 0x18 */
70  	u32 mpark;		/* 0x1C */
71  	u8 mpr;			/* 0x20 */
72  	u8 res4[3];		/* 0x21 - 0x23 */
73  	u8 pacr0;		/* 0x24 */
74  	u8 pacr1;		/* 0x25 */
75  	u8 pacr2;		/* 0x26 */
76  	u8 pacr3;		/* 0x27 */
77  	u8 pacr4;		/* 0x28 */
78  	u32 res5;		/* 0x29 */
79  	u8 pacr5;		/* 0x2a */
80  	u8 pacr6;		/* 0x2b */
81  	u8 pacr7;		/* 0x2c */
82  	u32 res6;		/* 0x2d */
83  	u8 pacr8;		/* 0x2e */
84  	u32 res7;		/* 0x2f */
85  	u8 gpacr;		/* 0x30 */
86  	u8 res8[3];		/* 0x31 - 0x33 */
87  } scm_t;
88  
89  /* SDRAM controller registers */
90  typedef struct sdram_ctrl {
91  	u16 dcr;		/* 0x00 Control register */
92  	u16 res1[3];		/* 0x02 - 0x07 */
93  	u32 dacr0;		/* 0x08 address and control register 0 */
94  	u32 dmr0;		/* 0x0C mask register block 0 */
95  	u32 dacr1;		/* 0x10 address and control register 1 */
96  	u32 dmr1;		/* 0x14 mask register block 1 */
97  } sdram_t;
98  
99  typedef struct canex_ctrl {
100  	can_msg_t msg[16];	/* 0x00 Message Buffer 0-15 */
101  } canex_t;
102  
103  /* GPIO port registers */
104  typedef struct gpio_ctrl {
105  	/* Port Output Data Registers */
106  	u8 podr_addr;		/* 0x00 */
107  	u8 podr_datah;		/* 0x01 */
108  	u8 podr_datal;		/* 0x02 */
109  	u8 podr_busctl;		/* 0x03 */
110  	u8 podr_bs;		/* 0x04 */
111  	u8 podr_cs;		/* 0x05 */
112  	u8 podr_sdram;		/* 0x06 */
113  	u8 podr_feci2c;		/* 0x07 */
114  	u8 podr_uarth;		/* 0x08 */
115  	u8 podr_uartl;		/* 0x09 */
116  	u8 podr_qspi;		/* 0x0A */
117  	u8 podr_timer;		/* 0x0B */
118  	u8 podr_etpu;		/* 0x0C */
119  	u8 res1[3];		/* 0x0D - 0x0F */
120  
121  	/* Port Data Direction Registers */
122  	u8 pddr_addr;		/* 0x10 */
123  	u8 pddr_datah;		/* 0x11 */
124  	u8 pddr_datal;		/* 0x12 */
125  	u8 pddr_busctl;		/* 0x13 */
126  	u8 pddr_bs;		/* 0x14 */
127  	u8 pddr_cs;		/* 0x15 */
128  	u8 pddr_sdram;		/* 0x16 */
129  	u8 pddr_feci2c;		/* 0x17 */
130  	u8 pddr_uarth;		/* 0x18 */
131  	u8 pddr_uartl;		/* 0x19 */
132  	u8 pddr_qspi;		/* 0x1A */
133  	u8 pddr_timer;		/* 0x1B */
134  	u8 pddr_etpu;		/* 0x1C */
135  	u8 res2[3];		/* 0x1D - 0x1F */
136  
137  	/* Port Data Direction Registers */
138  	u8 ppdsdr_addr;		/* 0x20 */
139  	u8 ppdsdr_datah;	/* 0x21 */
140  	u8 ppdsdr_datal;	/* 0x22 */
141  	u8 ppdsdr_busctl;	/* 0x23 */
142  	u8 ppdsdr_bs;		/* 0x24 */
143  	u8 ppdsdr_cs;		/* 0x25 */
144  	u8 ppdsdr_sdram;	/* 0x26 */
145  	u8 ppdsdr_feci2c;	/* 0x27 */
146  	u8 ppdsdr_uarth;	/* 0x28 */
147  	u8 ppdsdr_uartl;	/* 0x29 */
148  	u8 ppdsdr_qspi;		/* 0x2A */
149  	u8 ppdsdr_timer;	/* 0x2B */
150  	u8 ppdsdr_etpu;		/* 0x2C */
151  	u8 res3[3];		/* 0x2D - 0x2F */
152  
153  	/* Port Clear Output Data Registers */
154  	u8 pclrr_addr;		/* 0x30 */
155  	u8 pclrr_datah;		/* 0x31 */
156  	u8 pclrr_datal;		/* 0x32 */
157  	u8 pclrr_busctl;	/* 0x33 */
158  	u8 pclrr_bs;		/* 0x34 */
159  	u8 pclrr_cs;		/* 0x35 */
160  	u8 pclrr_sdram;		/* 0x36 */
161  	u8 pclrr_feci2c;	/* 0x37 */
162  	u8 pclrr_uarth;		/* 0x38 */
163  	u8 pclrr_uartl;		/* 0x39 */
164  	u8 pclrr_qspi;		/* 0x3A */
165  	u8 pclrr_timer;		/* 0x3B */
166  	u8 pclrr_etpu;		/* 0x3C */
167  	u8 res4[3];		/* 0x3D - 0x3F */
168  
169  	/* Pin Assignment Registers */
170  	u8 par_ad;		/* 0x40 */
171  	u8 res5;		/* 0x41 */
172  	u16 par_busctl;		/* 0x42 */
173  	u8 par_bs;		/* 0x44 */
174  	u8 par_cs;		/* 0x45 */
175  	u8 par_sdram;		/* 0x46 */
176  	u8 par_feci2c;		/* 0x47 */
177  	u16 par_uart;		/* 0x48 */
178  	u8 par_qspi;		/* 0x4A */
179  	u8 res6;		/* 0x4B */
180  	u16 par_timer;		/* 0x4C */
181  	u8 par_etpu;		/* 0x4E */
182  	u8 res7;		/* 0x4F */
183  
184  	/* Drive Strength Control Registers */
185  	u8 dscr_eim;		/* 0x50 */
186  	u8 dscr_etpu;		/* 0x51 */
187  	u8 dscr_feci2c;		/* 0x52 */
188  	u8 dscr_uart;		/* 0x53 */
189  	u8 dscr_qspi;		/* 0x54 */
190  	u8 dscr_timer;		/* 0x55 */
191  	u16 res8;		/* 0x56 */
192  } gpio_t;
193  
194  /*Chip configuration module registers */
195  typedef struct ccm_ctrl {
196  	u8 rcr;			/* 0x01 */
197  	u8 rsr;			/* 0x02 */
198  	u16 res1;		/* 0x03 */
199  	u16 ccr;		/* 0x04 Chip configuration register */
200  	u16 lpcr;		/* 0x06 Low-power Control register */
201  	u16 rcon;		/* 0x08 Rreset configuration register */
202  	u16 cir;		/* 0x0a Chip identification register */
203  } ccm_t;
204  
205  /* Clock Module registers */
206  typedef struct pll_ctrl {
207  	u32 syncr;		/* 0x00 synthesizer control register */
208  	u32 synsr;		/* 0x04 synthesizer status register */
209  } pll_t;
210  
211  /* Watchdog registers */
212  typedef struct wdog_ctrl {
213  	u16 cr;			/* 0x00 Control register */
214  	u16 mr;			/* 0x02 Modulus register */
215  	u16 cntr;		/* 0x04 Count register */
216  	u16 sr;			/* 0x06 Service register */
217  } wdog_t;
218  
219  #endif				/* __IMMAP_5235__ */
220