1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 /* FILE POLICY AND INTENDED USAGE:
27 * This file implements all generic dp link training helper functions and top
28 * level generic training sequence. All variations of dp link training sequence
29 * should be called inside the top level training functions in this file to
30 * ensure the integrity of our overall training procedure across different types
31 * of link encoding and back end hardware.
32 */
33 #include "link_dp_training.h"
34 #include "link_dp_training_8b_10b.h"
35 #include "link_dp_training_128b_132b.h"
36 #include "link_dp_training_auxless.h"
37 #include "link_dp_training_dpia.h"
38 #include "link_dp_training_fixed_vs_pe_retimer.h"
39 #include "link_dpcd.h"
40 #include "link/accessories/link_dp_trace.h"
41 #include "link_dp_phy.h"
42 #include "link_dp_capability.h"
43 #include "link_edp_panel_control.h"
44 #include "link/link_detection.h"
45 #include "link/link_validation.h"
46 #include "atomfirmware.h"
47 #include "link_enc_cfg.h"
48 #include "resource.h"
49 #include "dm_helpers.h"
50
51 #define DC_LOGGER \
52 link->ctx->logger
53
54 #define POST_LT_ADJ_REQ_LIMIT 6
55 #define POST_LT_ADJ_REQ_TIMEOUT 200
56 #define LINK_TRAINING_RETRY_DELAY 50 /* ms */
57
dp_log_training_result(struct dc_link * link,const struct link_training_settings * lt_settings,enum link_training_result status)58 void dp_log_training_result(
59 struct dc_link *link,
60 const struct link_training_settings *lt_settings,
61 enum link_training_result status)
62 {
63 char *link_rate = "Unknown";
64 char *lt_result = "Unknown";
65 char *lt_spread = "Disabled";
66
67 switch (lt_settings->link_settings.link_rate) {
68 case LINK_RATE_LOW:
69 link_rate = "RBR";
70 break;
71 case LINK_RATE_RATE_2:
72 link_rate = "R2";
73 break;
74 case LINK_RATE_RATE_3:
75 link_rate = "R3";
76 break;
77 case LINK_RATE_HIGH:
78 link_rate = "HBR";
79 break;
80 case LINK_RATE_RBR2:
81 link_rate = "RBR2";
82 break;
83 case LINK_RATE_RATE_6:
84 link_rate = "R6";
85 break;
86 case LINK_RATE_HIGH2:
87 link_rate = "HBR2";
88 break;
89 case LINK_RATE_RATE_8:
90 link_rate = "R8";
91 break;
92 case LINK_RATE_HIGH3:
93 link_rate = "HBR3";
94 break;
95 case LINK_RATE_UHBR10:
96 link_rate = "UHBR10";
97 break;
98 case LINK_RATE_UHBR13_5:
99 link_rate = "UHBR13.5";
100 break;
101 case LINK_RATE_UHBR20:
102 link_rate = "UHBR20";
103 break;
104 default:
105 break;
106 }
107
108 switch (status) {
109 case LINK_TRAINING_SUCCESS:
110 lt_result = "pass";
111 break;
112 case LINK_TRAINING_CR_FAIL_LANE0:
113 lt_result = "CR failed lane0";
114 break;
115 case LINK_TRAINING_CR_FAIL_LANE1:
116 lt_result = "CR failed lane1";
117 break;
118 case LINK_TRAINING_CR_FAIL_LANE23:
119 lt_result = "CR failed lane23";
120 break;
121 case LINK_TRAINING_EQ_FAIL_CR:
122 lt_result = "CR failed in EQ";
123 break;
124 case LINK_TRAINING_EQ_FAIL_CR_PARTIAL:
125 lt_result = "CR failed in EQ partially";
126 break;
127 case LINK_TRAINING_EQ_FAIL_EQ:
128 lt_result = "EQ failed";
129 break;
130 case LINK_TRAINING_LQA_FAIL:
131 lt_result = "LQA failed";
132 break;
133 case LINK_TRAINING_LINK_LOSS:
134 lt_result = "Link loss";
135 break;
136 case DP_128b_132b_LT_FAILED:
137 lt_result = "LT_FAILED received";
138 break;
139 case DP_128b_132b_MAX_LOOP_COUNT_REACHED:
140 lt_result = "max loop count reached";
141 break;
142 case DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT:
143 lt_result = "channel EQ timeout";
144 break;
145 case DP_128b_132b_CDS_DONE_TIMEOUT:
146 lt_result = "CDS timeout";
147 break;
148 default:
149 break;
150 }
151
152 switch (lt_settings->link_settings.link_spread) {
153 case LINK_SPREAD_DISABLED:
154 lt_spread = "Disabled";
155 break;
156 case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
157 lt_spread = "0.5% 30KHz";
158 break;
159 case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
160 lt_spread = "0.5% 33KHz";
161 break;
162 default:
163 break;
164 }
165
166 /* Connectivity log: link training */
167
168 /* TODO - DP2.0 Log: add connectivity log for FFE PRESET */
169
170 CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
171 link_rate,
172 lt_settings->link_settings.lane_count,
173 lt_result,
174 lt_settings->hw_lane_settings[0].VOLTAGE_SWING,
175 lt_settings->hw_lane_settings[0].PRE_EMPHASIS,
176 lt_spread);
177 }
178
dp_initialize_scrambling_data_symbols(struct dc_link * link,enum dc_dp_training_pattern pattern)179 uint8_t dp_initialize_scrambling_data_symbols(
180 struct dc_link *link,
181 enum dc_dp_training_pattern pattern)
182 {
183 uint8_t disable_scrabled_data_symbols = 0;
184
185 switch (pattern) {
186 case DP_TRAINING_PATTERN_SEQUENCE_1:
187 case DP_TRAINING_PATTERN_SEQUENCE_2:
188 case DP_TRAINING_PATTERN_SEQUENCE_3:
189 disable_scrabled_data_symbols = 1;
190 break;
191 case DP_TRAINING_PATTERN_SEQUENCE_4:
192 case DP_128b_132b_TPS1:
193 case DP_128b_132b_TPS2:
194 disable_scrabled_data_symbols = 0;
195 break;
196 default:
197 ASSERT(0);
198 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
199 __func__, pattern);
200 break;
201 }
202 return disable_scrabled_data_symbols;
203 }
204
205 enum dpcd_training_patterns
dp_training_pattern_to_dpcd_training_pattern(struct dc_link * link,enum dc_dp_training_pattern pattern)206 dp_training_pattern_to_dpcd_training_pattern(
207 struct dc_link *link,
208 enum dc_dp_training_pattern pattern)
209 {
210 enum dpcd_training_patterns dpcd_tr_pattern =
211 DPCD_TRAINING_PATTERN_VIDEOIDLE;
212
213 switch (pattern) {
214 case DP_TRAINING_PATTERN_SEQUENCE_1:
215 DC_LOG_HW_LINK_TRAINING("%s: Using DP training pattern TPS1\n", __func__);
216 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
217 break;
218 case DP_TRAINING_PATTERN_SEQUENCE_2:
219 DC_LOG_HW_LINK_TRAINING("%s: Using DP training pattern TPS2\n", __func__);
220 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
221 break;
222 case DP_TRAINING_PATTERN_SEQUENCE_3:
223 DC_LOG_HW_LINK_TRAINING("%s: Using DP training pattern TPS3\n", __func__);
224 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
225 break;
226 case DP_TRAINING_PATTERN_SEQUENCE_4:
227 DC_LOG_HW_LINK_TRAINING("%s: Using DP training pattern TPS4\n", __func__);
228 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
229 break;
230 case DP_128b_132b_TPS1:
231 DC_LOG_HW_LINK_TRAINING("%s: Using DP 128b/132b training pattern TPS1\n", __func__);
232 dpcd_tr_pattern = DPCD_128b_132b_TPS1;
233 break;
234 case DP_128b_132b_TPS2:
235 DC_LOG_HW_LINK_TRAINING("%s: Using DP 128b/132b training pattern TPS2\n", __func__);
236 dpcd_tr_pattern = DPCD_128b_132b_TPS2;
237 break;
238 case DP_128b_132b_TPS2_CDS:
239 DC_LOG_HW_LINK_TRAINING("%s: Using DP 128b/132b training pattern TPS2 CDS\n",
240 __func__);
241 dpcd_tr_pattern = DPCD_128b_132b_TPS2_CDS;
242 break;
243 case DP_TRAINING_PATTERN_VIDEOIDLE:
244 DC_LOG_HW_LINK_TRAINING("%s: Using DP training pattern videoidle\n", __func__);
245 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_VIDEOIDLE;
246 break;
247 default:
248 ASSERT(0);
249 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
250 __func__, pattern);
251 break;
252 }
253
254 return dpcd_tr_pattern;
255 }
256
dp_get_nibble_at_index(const uint8_t * buf,uint32_t index)257 uint8_t dp_get_nibble_at_index(const uint8_t *buf,
258 uint32_t index)
259 {
260 uint8_t nibble;
261 nibble = buf[index / 2];
262
263 if (index % 2)
264 nibble >>= 4;
265 else
266 nibble &= 0x0F;
267
268 return nibble;
269 }
270
dp_wait_for_training_aux_rd_interval(struct dc_link * link,uint32_t wait_in_micro_secs)271 void dp_wait_for_training_aux_rd_interval(
272 struct dc_link *link,
273 uint32_t wait_in_micro_secs)
274 {
275 fsleep(wait_in_micro_secs);
276
277 DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
278 __func__,
279 wait_in_micro_secs);
280 }
281
282 /* maximum pre emphasis level allowed for each voltage swing level*/
283 static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
284 PRE_EMPHASIS_LEVEL3,
285 PRE_EMPHASIS_LEVEL2,
286 PRE_EMPHASIS_LEVEL1,
287 PRE_EMPHASIS_DISABLED };
288
get_max_pre_emphasis_for_voltage_swing(enum dc_voltage_swing voltage)289 static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
290 enum dc_voltage_swing voltage)
291 {
292 enum dc_pre_emphasis pre_emphasis;
293 pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
294
295 if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
296 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
297
298 return pre_emphasis;
299
300 }
301
maximize_lane_settings(const struct link_training_settings * lt_settings,struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])302 static void maximize_lane_settings(const struct link_training_settings *lt_settings,
303 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
304 {
305 uint32_t lane;
306 struct dc_lane_settings max_requested;
307
308 max_requested.VOLTAGE_SWING = lane_settings[0].VOLTAGE_SWING;
309 max_requested.PRE_EMPHASIS = lane_settings[0].PRE_EMPHASIS;
310 max_requested.FFE_PRESET = lane_settings[0].FFE_PRESET;
311
312 /* Determine what the maximum of the requested settings are*/
313 for (lane = 1; lane < lt_settings->link_settings.lane_count; lane++) {
314 if (lane_settings[lane].VOLTAGE_SWING > max_requested.VOLTAGE_SWING)
315 max_requested.VOLTAGE_SWING = lane_settings[lane].VOLTAGE_SWING;
316
317 if (lane_settings[lane].PRE_EMPHASIS > max_requested.PRE_EMPHASIS)
318 max_requested.PRE_EMPHASIS = lane_settings[lane].PRE_EMPHASIS;
319 if (lane_settings[lane].FFE_PRESET.settings.level >
320 max_requested.FFE_PRESET.settings.level)
321 max_requested.FFE_PRESET.settings.level =
322 lane_settings[lane].FFE_PRESET.settings.level;
323 }
324
325 /* make sure the requested settings are
326 * not higher than maximum settings*/
327 if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
328 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
329
330 if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
331 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
332 if (max_requested.FFE_PRESET.settings.level > DP_FFE_PRESET_MAX_LEVEL)
333 max_requested.FFE_PRESET.settings.level = DP_FFE_PRESET_MAX_LEVEL;
334
335 /* make sure the pre-emphasis matches the voltage swing*/
336 if (max_requested.PRE_EMPHASIS >
337 get_max_pre_emphasis_for_voltage_swing(
338 max_requested.VOLTAGE_SWING))
339 max_requested.PRE_EMPHASIS =
340 get_max_pre_emphasis_for_voltage_swing(
341 max_requested.VOLTAGE_SWING);
342
343 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
344 lane_settings[lane].VOLTAGE_SWING = max_requested.VOLTAGE_SWING;
345 lane_settings[lane].PRE_EMPHASIS = max_requested.PRE_EMPHASIS;
346 lane_settings[lane].FFE_PRESET = max_requested.FFE_PRESET;
347 }
348 }
349
dp_hw_to_dpcd_lane_settings(const struct link_training_settings * lt_settings,const struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX])350 void dp_hw_to_dpcd_lane_settings(
351 const struct link_training_settings *lt_settings,
352 const struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
353 union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX])
354 {
355 uint8_t lane = 0;
356
357 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
358 if (link_dp_get_encoding_format(<_settings->link_settings) ==
359 DP_8b_10b_ENCODING) {
360 dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET =
361 (uint8_t)(hw_lane_settings[lane].VOLTAGE_SWING);
362 dpcd_lane_settings[lane].bits.PRE_EMPHASIS_SET =
363 (uint8_t)(hw_lane_settings[lane].PRE_EMPHASIS);
364 dpcd_lane_settings[lane].bits.MAX_SWING_REACHED =
365 (hw_lane_settings[lane].VOLTAGE_SWING ==
366 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
367 dpcd_lane_settings[lane].bits.MAX_PRE_EMPHASIS_REACHED =
368 (hw_lane_settings[lane].PRE_EMPHASIS ==
369 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
370 } else if (link_dp_get_encoding_format(<_settings->link_settings) ==
371 DP_128b_132b_ENCODING) {
372 dpcd_lane_settings[lane].tx_ffe.PRESET_VALUE =
373 hw_lane_settings[lane].FFE_PRESET.settings.level;
374 }
375 }
376 }
377
get_dpcd_link_rate(const struct dc_link_settings * link_settings)378 uint8_t get_dpcd_link_rate(const struct dc_link_settings *link_settings)
379 {
380 uint8_t link_rate = 0;
381 enum dp_link_encoding encoding = link_dp_get_encoding_format(link_settings);
382
383 if (encoding == DP_128b_132b_ENCODING)
384 switch (link_settings->link_rate) {
385 case LINK_RATE_UHBR10:
386 link_rate = 0x1;
387 break;
388 case LINK_RATE_UHBR20:
389 link_rate = 0x2;
390 break;
391 case LINK_RATE_UHBR13_5:
392 link_rate = 0x4;
393 break;
394 default:
395 link_rate = 0;
396 break;
397 }
398 else if (encoding == DP_8b_10b_ENCODING)
399 link_rate = (uint8_t) link_settings->link_rate;
400 else
401 link_rate = 0;
402
403 return link_rate;
404 }
405
406 /* Only used for channel equalization */
dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)407 uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
408 {
409 unsigned int aux_rd_interval_us = 400;
410
411 switch (dpcd_aux_read_interval) {
412 case 0x01:
413 aux_rd_interval_us = 4000;
414 break;
415 case 0x02:
416 aux_rd_interval_us = 8000;
417 break;
418 case 0x03:
419 aux_rd_interval_us = 12000;
420 break;
421 case 0x04:
422 aux_rd_interval_us = 16000;
423 break;
424 case 0x05:
425 aux_rd_interval_us = 32000;
426 break;
427 case 0x06:
428 aux_rd_interval_us = 64000;
429 break;
430 default:
431 break;
432 }
433
434 return aux_rd_interval_us;
435 }
436
dp_get_cr_failure(enum dc_lane_count ln_count,union lane_status * dpcd_lane_status)437 enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count,
438 union lane_status *dpcd_lane_status)
439 {
440 enum link_training_result result = LINK_TRAINING_SUCCESS;
441
442 if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
443 result = LINK_TRAINING_CR_FAIL_LANE0;
444 else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
445 result = LINK_TRAINING_CR_FAIL_LANE1;
446 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
447 result = LINK_TRAINING_CR_FAIL_LANE23;
448 else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
449 result = LINK_TRAINING_CR_FAIL_LANE23;
450 return result;
451 }
452
is_repeater(const struct link_training_settings * lt_settings,uint32_t offset)453 bool is_repeater(const struct link_training_settings *lt_settings, uint32_t offset)
454 {
455 return (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (offset != 0);
456 }
457
dp_is_max_vs_reached(const struct link_training_settings * lt_settings)458 bool dp_is_max_vs_reached(
459 const struct link_training_settings *lt_settings)
460 {
461 uint32_t lane;
462 for (lane = 0; lane <
463 (uint32_t)(lt_settings->link_settings.lane_count);
464 lane++) {
465 if (lt_settings->dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET
466 == VOLTAGE_SWING_MAX_LEVEL)
467 return true;
468 }
469 return false;
470
471 }
472
dp_is_cr_done(enum dc_lane_count ln_count,union lane_status * dpcd_lane_status)473 bool dp_is_cr_done(enum dc_lane_count ln_count,
474 union lane_status *dpcd_lane_status)
475 {
476 bool done = true;
477 uint32_t lane;
478 /*LANEx_CR_DONE bits All 1's?*/
479 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
480 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
481 done = false;
482 }
483 return done;
484
485 }
486
dp_is_ch_eq_done(enum dc_lane_count ln_count,union lane_status * dpcd_lane_status)487 bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
488 union lane_status *dpcd_lane_status)
489 {
490 bool done = true;
491 uint32_t lane;
492 for (lane = 0; lane < (uint32_t)(ln_count); lane++)
493 if (!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
494 done = false;
495 return done;
496 }
497
dp_is_symbol_locked(enum dc_lane_count ln_count,union lane_status * dpcd_lane_status)498 bool dp_is_symbol_locked(enum dc_lane_count ln_count,
499 union lane_status *dpcd_lane_status)
500 {
501 bool locked = true;
502 uint32_t lane;
503 for (lane = 0; lane < (uint32_t)(ln_count); lane++)
504 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0)
505 locked = false;
506 return locked;
507 }
508
dp_is_interlane_aligned(union lane_align_status_updated align_status)509 bool dp_is_interlane_aligned(union lane_align_status_updated align_status)
510 {
511 return align_status.bits.INTERLANE_ALIGN_DONE == 1;
512 }
513
dp_check_link_loss_status(struct dc_link * link,const struct link_training_settings * link_training_setting)514 enum link_training_result dp_check_link_loss_status(
515 struct dc_link *link,
516 const struct link_training_settings *link_training_setting)
517 {
518 enum link_training_result status = LINK_TRAINING_SUCCESS;
519 union lane_status lane_status;
520 union lane_align_status_updated dpcd_lane_status_updated;
521 uint8_t dpcd_buf[6] = {0};
522 uint32_t lane;
523
524 core_link_read_dpcd(
525 link,
526 DP_SINK_COUNT,
527 (uint8_t *)(dpcd_buf),
528 sizeof(dpcd_buf));
529
530 /*parse lane status*/
531 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
532 /*
533 * check lanes status
534 */
535 lane_status.raw = dp_get_nibble_at_index(&dpcd_buf[2], lane);
536 dpcd_lane_status_updated.raw = dpcd_buf[4];
537
538 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
539 !lane_status.bits.CR_DONE_0 ||
540 !lane_status.bits.SYMBOL_LOCKED_0 ||
541 !dp_is_interlane_aligned(dpcd_lane_status_updated)) {
542 /* if one of the channel equalization, clock
543 * recovery or symbol lock is dropped
544 * consider it as (link has been
545 * dropped) dp sink status has changed
546 */
547 status = LINK_TRAINING_LINK_LOSS;
548 break;
549 }
550 }
551
552 return status;
553 }
554
dp_get_lane_status_and_lane_adjust(struct dc_link * link,const struct link_training_settings * link_training_setting,union lane_status ln_status[LANE_COUNT_DP_MAX],union lane_align_status_updated * ln_align,union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],uint32_t offset)555 enum dc_status dp_get_lane_status_and_lane_adjust(
556 struct dc_link *link,
557 const struct link_training_settings *link_training_setting,
558 union lane_status ln_status[LANE_COUNT_DP_MAX],
559 union lane_align_status_updated *ln_align,
560 union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
561 uint32_t offset)
562 {
563 unsigned int lane01_status_address = DP_LANE0_1_STATUS;
564 uint8_t lane_adjust_offset = 4;
565 unsigned int lane01_adjust_address;
566 uint8_t dpcd_buf[6] = {0};
567 uint32_t lane;
568 enum dc_status status;
569
570 if (is_repeater(link_training_setting, offset)) {
571 lane01_status_address =
572 DP_LANE0_1_STATUS_PHY_REPEATER1 +
573 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
574 lane_adjust_offset = 3;
575 }
576
577 status = core_link_read_dpcd(
578 link,
579 lane01_status_address,
580 (uint8_t *)(dpcd_buf),
581 sizeof(dpcd_buf));
582
583 if (status != DC_OK) {
584 DC_LOG_HW_LINK_TRAINING("%s:\n Failed to read from address 0x%X,"
585 " keep current lane status and lane adjust unchanged",
586 __func__,
587 lane01_status_address);
588 return status;
589 }
590
591 for (lane = 0; lane <
592 (uint32_t)(link_training_setting->link_settings.lane_count);
593 lane++) {
594
595 ln_status[lane].raw =
596 dp_get_nibble_at_index(&dpcd_buf[0], lane);
597 ln_adjust[lane].raw =
598 dp_get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
599 }
600
601 ln_align->raw = dpcd_buf[2];
602
603 if (is_repeater(link_training_setting, offset)) {
604 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
605 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
606 __func__,
607 offset,
608 lane01_status_address, dpcd_buf[0],
609 lane01_status_address + 1, dpcd_buf[1]);
610
611 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
612 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
613
614 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
615 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
616 __func__,
617 offset,
618 lane01_adjust_address,
619 dpcd_buf[lane_adjust_offset],
620 lane01_adjust_address + 1,
621 dpcd_buf[lane_adjust_offset + 1]);
622 } else {
623 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
624 __func__,
625 lane01_status_address, dpcd_buf[0],
626 lane01_status_address + 1, dpcd_buf[1]);
627
628 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
629
630 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
631 __func__,
632 lane01_adjust_address,
633 dpcd_buf[lane_adjust_offset],
634 lane01_adjust_address + 1,
635 dpcd_buf[lane_adjust_offset + 1]);
636 }
637
638 return status;
639 }
640
override_lane_settings(const struct link_training_settings * lt_settings,struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])641 static void override_lane_settings(const struct link_training_settings *lt_settings,
642 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
643 {
644 uint32_t lane;
645
646 if (lt_settings->voltage_swing == NULL &&
647 lt_settings->pre_emphasis == NULL &&
648 lt_settings->ffe_preset == NULL &&
649 lt_settings->post_cursor2 == NULL)
650
651 return;
652
653 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
654 if (lt_settings->voltage_swing)
655 lane_settings[lane].VOLTAGE_SWING = *lt_settings->voltage_swing;
656 if (lt_settings->pre_emphasis)
657 lane_settings[lane].PRE_EMPHASIS = *lt_settings->pre_emphasis;
658 if (lt_settings->post_cursor2)
659 lane_settings[lane].POST_CURSOR2 = *lt_settings->post_cursor2;
660 if (lt_settings->ffe_preset)
661 lane_settings[lane].FFE_PRESET = *lt_settings->ffe_preset;
662 }
663 }
664
dp_get_lttpr_mode_override(struct dc_link * link,enum lttpr_mode * override)665 void dp_get_lttpr_mode_override(struct dc_link *link, enum lttpr_mode *override)
666 {
667 if (!dp_is_lttpr_present(link))
668 return;
669
670 if (link->dc->debug.lttpr_mode_override == LTTPR_MODE_TRANSPARENT) {
671 *override = LTTPR_MODE_TRANSPARENT;
672 } else if (link->dc->debug.lttpr_mode_override == LTTPR_MODE_NON_TRANSPARENT) {
673 *override = LTTPR_MODE_NON_TRANSPARENT;
674 } else if (link->dc->debug.lttpr_mode_override == LTTPR_MODE_NON_LTTPR) {
675 *override = LTTPR_MODE_NON_LTTPR;
676 }
677 DC_LOG_DC("lttpr_mode_override chose LTTPR_MODE = %d\n", (uint8_t)(*override));
678 }
679
override_training_settings(struct dc_link * link,const struct dc_link_training_overrides * overrides,struct link_training_settings * lt_settings)680 void override_training_settings(
681 struct dc_link *link,
682 const struct dc_link_training_overrides *overrides,
683 struct link_training_settings *lt_settings)
684 {
685 uint32_t lane;
686
687 /* Override link spread */
688 if (!link->dp_ss_off && overrides->downspread != NULL)
689 lt_settings->link_settings.link_spread = *overrides->downspread ?
690 LINK_SPREAD_05_DOWNSPREAD_30KHZ
691 : LINK_SPREAD_DISABLED;
692
693 /* Override lane settings */
694 if (overrides->voltage_swing != NULL)
695 lt_settings->voltage_swing = overrides->voltage_swing;
696 if (overrides->pre_emphasis != NULL)
697 lt_settings->pre_emphasis = overrides->pre_emphasis;
698 if (overrides->post_cursor2 != NULL)
699 lt_settings->post_cursor2 = overrides->post_cursor2;
700 if (link->wa_flags.force_dp_ffe_preset && !dp_is_lttpr_present(link))
701 lt_settings->ffe_preset = &link->forced_dp_ffe_preset;
702 if (overrides->ffe_preset != NULL)
703 lt_settings->ffe_preset = overrides->ffe_preset;
704 /* Override HW lane settings with BIOS forced values if present */
705 if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
706 lt_settings->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
707 lt_settings->voltage_swing = &link->bios_forced_drive_settings.VOLTAGE_SWING;
708 lt_settings->pre_emphasis = &link->bios_forced_drive_settings.PRE_EMPHASIS;
709 lt_settings->always_match_dpcd_with_hw_lane_settings = false;
710 }
711 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
712 lt_settings->hw_lane_settings[lane].VOLTAGE_SWING =
713 lt_settings->voltage_swing != NULL ?
714 *lt_settings->voltage_swing :
715 VOLTAGE_SWING_LEVEL0;
716 lt_settings->hw_lane_settings[lane].PRE_EMPHASIS =
717 lt_settings->pre_emphasis != NULL ?
718 *lt_settings->pre_emphasis
719 : PRE_EMPHASIS_DISABLED;
720 lt_settings->hw_lane_settings[lane].POST_CURSOR2 =
721 lt_settings->post_cursor2 != NULL ?
722 *lt_settings->post_cursor2
723 : POST_CURSOR2_DISABLED;
724 }
725
726 if (lt_settings->always_match_dpcd_with_hw_lane_settings)
727 dp_hw_to_dpcd_lane_settings(lt_settings,
728 lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
729
730 /* Override training timings */
731 if (overrides->cr_pattern_time != NULL)
732 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
733 if (overrides->eq_pattern_time != NULL)
734 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
735 if (overrides->pattern_for_cr != NULL)
736 lt_settings->pattern_for_cr = *overrides->pattern_for_cr;
737 if (overrides->pattern_for_eq != NULL)
738 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
739 if (overrides->enhanced_framing != NULL)
740 lt_settings->enhanced_framing = *overrides->enhanced_framing;
741 if (link->preferred_training_settings.fec_enable != NULL)
742 lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable;
743
744 /* Check DP tunnel LTTPR mode debug option. */
745 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->dc->debug.dpia_debug.bits.force_non_lttpr)
746 lt_settings->lttpr_mode = LTTPR_MODE_NON_LTTPR;
747
748 dp_get_lttpr_mode_override(link, <_settings->lttpr_mode);
749
750 }
751
decide_cr_training_pattern(const struct dc_link_settings * link_settings)752 enum dc_dp_training_pattern decide_cr_training_pattern(
753 const struct dc_link_settings *link_settings)
754 {
755 switch (link_dp_get_encoding_format(link_settings)) {
756 case DP_8b_10b_ENCODING:
757 default:
758 return DP_TRAINING_PATTERN_SEQUENCE_1;
759 case DP_128b_132b_ENCODING:
760 return DP_128b_132b_TPS1;
761 }
762 }
763
decide_eq_training_pattern(struct dc_link * link,const struct dc_link_settings * link_settings)764 enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
765 const struct dc_link_settings *link_settings)
766 {
767 struct link_encoder *link_enc;
768 struct encoder_feature_support *enc_caps;
769 struct dpcd_caps *rx_caps = &link->dpcd_caps;
770 enum dc_dp_training_pattern pattern = DP_TRAINING_PATTERN_SEQUENCE_2;
771
772 link_enc = link_enc_cfg_get_link_enc(link);
773 ASSERT(link_enc);
774 enc_caps = &link_enc->features;
775
776 switch (link_dp_get_encoding_format(link_settings)) {
777 case DP_8b_10b_ENCODING:
778 if (enc_caps->flags.bits.IS_TPS4_CAPABLE &&
779 rx_caps->max_down_spread.bits.TPS4_SUPPORTED)
780 pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
781 else if (enc_caps->flags.bits.IS_TPS3_CAPABLE &&
782 rx_caps->max_ln_count.bits.TPS3_SUPPORTED)
783 pattern = DP_TRAINING_PATTERN_SEQUENCE_3;
784 else
785 pattern = DP_TRAINING_PATTERN_SEQUENCE_2;
786 break;
787 case DP_128b_132b_ENCODING:
788 pattern = DP_128b_132b_TPS2;
789 break;
790 default:
791 pattern = DP_TRAINING_PATTERN_SEQUENCE_2;
792 break;
793 }
794 return pattern;
795 }
796
dp_decide_lttpr_mode(struct dc_link * link,struct dc_link_settings * link_setting)797 enum lttpr_mode dp_decide_lttpr_mode(struct dc_link *link,
798 struct dc_link_settings *link_setting)
799 {
800 enum dp_link_encoding encoding = link_dp_get_encoding_format(link_setting);
801
802 if (encoding == DP_8b_10b_ENCODING)
803 return dp_decide_8b_10b_lttpr_mode(link);
804 else if (encoding == DP_128b_132b_ENCODING)
805 return dp_decide_128b_132b_lttpr_mode(link);
806
807 ASSERT(0);
808 return LTTPR_MODE_NON_LTTPR;
809 }
810
dp_decide_lane_settings(const struct link_training_settings * lt_settings,const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],union dpcd_training_lane * dpcd_lane_settings)811 void dp_decide_lane_settings(
812 const struct link_training_settings *lt_settings,
813 const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
814 struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
815 union dpcd_training_lane *dpcd_lane_settings)
816 {
817 uint32_t lane;
818
819 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
820 if (link_dp_get_encoding_format(<_settings->link_settings) ==
821 DP_8b_10b_ENCODING) {
822 hw_lane_settings[lane].VOLTAGE_SWING =
823 (enum dc_voltage_swing)(ln_adjust[lane].bits.
824 VOLTAGE_SWING_LANE);
825 hw_lane_settings[lane].PRE_EMPHASIS =
826 (enum dc_pre_emphasis)(ln_adjust[lane].bits.
827 PRE_EMPHASIS_LANE);
828 } else if (link_dp_get_encoding_format(<_settings->link_settings) ==
829 DP_128b_132b_ENCODING) {
830 hw_lane_settings[lane].FFE_PRESET.raw =
831 ln_adjust[lane].tx_ffe.PRESET_VALUE;
832 }
833 }
834 dp_hw_to_dpcd_lane_settings(lt_settings, hw_lane_settings, dpcd_lane_settings);
835
836 if (lt_settings->disallow_per_lane_settings) {
837 /* we find the maximum of the requested settings across all lanes*/
838 /* and set this maximum for all lanes*/
839 maximize_lane_settings(lt_settings, hw_lane_settings);
840 override_lane_settings(lt_settings, hw_lane_settings);
841
842 if (lt_settings->always_match_dpcd_with_hw_lane_settings)
843 dp_hw_to_dpcd_lane_settings(lt_settings, hw_lane_settings, dpcd_lane_settings);
844 }
845
846 }
847
dp_decide_training_settings(struct dc_link * link,const struct dc_link_settings * link_settings,struct link_training_settings * lt_settings)848 void dp_decide_training_settings(
849 struct dc_link *link,
850 const struct dc_link_settings *link_settings,
851 struct link_training_settings *lt_settings)
852 {
853 if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING)
854 decide_8b_10b_training_settings(link, link_settings, lt_settings);
855 else if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING)
856 decide_128b_132b_training_settings(link, link_settings, lt_settings);
857 }
858
859
configure_lttpr_mode_transparent(struct dc_link * link)860 enum dc_status configure_lttpr_mode_transparent(struct dc_link *link)
861 {
862 uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
863
864 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
865 return core_link_write_dpcd(link,
866 DP_PHY_REPEATER_MODE,
867 (uint8_t *)&repeater_mode,
868 sizeof(repeater_mode));
869 }
870
configure_lttpr_mode_non_transparent(struct dc_link * link,const struct link_training_settings * lt_settings)871 static enum dc_status configure_lttpr_mode_non_transparent(
872 struct dc_link *link,
873 const struct link_training_settings *lt_settings)
874 {
875 /* aux timeout is already set to extended */
876 /* RESET/SET lttpr mode to enable non transparent mode */
877 uint8_t repeater_cnt;
878 uint32_t aux_interval_address;
879 uint8_t repeater_id;
880 enum dc_status result = DC_ERROR_UNEXPECTED;
881 uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
882 const struct dc *dc = link->dc;
883
884 enum dp_link_encoding encoding = dc->link_srv->dp_get_encoding_format(<_settings->link_settings);
885
886 if (encoding == DP_8b_10b_ENCODING) {
887 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
888 result = core_link_write_dpcd(link,
889 DP_PHY_REPEATER_MODE,
890 (uint8_t *)&repeater_mode,
891 sizeof(repeater_mode));
892
893 }
894
895 if (result == DC_OK) {
896 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
897 }
898
899 if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
900
901 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
902
903 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
904 result = core_link_write_dpcd(link,
905 DP_PHY_REPEATER_MODE,
906 (uint8_t *)&repeater_mode,
907 sizeof(repeater_mode));
908
909 if (result == DC_OK) {
910 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
911 }
912
913 if (encoding == DP_8b_10b_ENCODING) {
914 repeater_cnt = dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
915
916 /* Driver does not need to train the first hop. Skip DPCD read and clear
917 * AUX_RD_INTERVAL for DPTX-to-DPIA hop.
918 */
919 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && repeater_cnt > 0 && repeater_cnt < MAX_REPEATER_CNT)
920 link->dpcd_caps.lttpr_caps.aux_rd_interval[--repeater_cnt] = 0;
921
922 for (repeater_id = repeater_cnt; repeater_id > 0 && repeater_id < MAX_REPEATER_CNT; repeater_id--) {
923 aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
924 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
925 core_link_read_dpcd(
926 link,
927 aux_interval_address,
928 (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
929 sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
930 link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
931 }
932 }
933 }
934
935 return result;
936 }
937
dpcd_configure_lttpr_mode(struct dc_link * link,struct link_training_settings * lt_settings)938 enum dc_status dpcd_configure_lttpr_mode(struct dc_link *link, struct link_training_settings *lt_settings)
939 {
940 enum dc_status status = DC_OK;
941
942 if (lt_settings->lttpr_mode == LTTPR_MODE_TRANSPARENT)
943 status = configure_lttpr_mode_transparent(link);
944
945 else if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
946 status = configure_lttpr_mode_non_transparent(link, lt_settings);
947
948 return status;
949 }
950
repeater_training_done(struct dc_link * link,uint32_t offset)951 void repeater_training_done(struct dc_link *link, uint32_t offset)
952 {
953 union dpcd_training_pattern dpcd_pattern = {0};
954
955 const uint32_t dpcd_base_lt_offset =
956 DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
957 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
958 /* Set training not in progress*/
959 dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
960
961 core_link_write_dpcd(
962 link,
963 dpcd_base_lt_offset,
964 &dpcd_pattern.raw,
965 1);
966
967 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
968 __func__,
969 offset,
970 dpcd_base_lt_offset,
971 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
972 }
973
dpcd_exit_training_mode(struct dc_link * link,enum dp_link_encoding encoding)974 static void dpcd_exit_training_mode(struct dc_link *link, enum dp_link_encoding encoding)
975 {
976 uint8_t sink_status = 0;
977 uint8_t i;
978
979 /* clear training pattern set */
980 dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);
981
982 if (encoding == DP_128b_132b_ENCODING) {
983 /* poll for intra-hop disable */
984 for (i = 0; i < 10; i++) {
985 if ((core_link_read_dpcd(link, DP_SINK_STATUS, &sink_status, 1) == DC_OK) &&
986 (sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION) == 0)
987 break;
988 fsleep(1000);
989 }
990 }
991 }
992
dpcd_configure_channel_coding(struct dc_link * link,struct link_training_settings * lt_settings)993 enum dc_status dpcd_configure_channel_coding(struct dc_link *link,
994 struct link_training_settings *lt_settings)
995 {
996 enum dp_link_encoding encoding =
997 link_dp_get_encoding_format(
998 <_settings->link_settings);
999 enum dc_status status;
1000
1001 status = core_link_write_dpcd(
1002 link,
1003 DP_MAIN_LINK_CHANNEL_CODING_SET,
1004 (uint8_t *) &encoding,
1005 1);
1006 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X MAIN_LINK_CHANNEL_CODING_SET = %x\n",
1007 __func__,
1008 DP_MAIN_LINK_CHANNEL_CODING_SET,
1009 encoding);
1010
1011 return status;
1012 }
1013
dpcd_set_training_pattern(struct dc_link * link,enum dc_dp_training_pattern training_pattern)1014 void dpcd_set_training_pattern(
1015 struct dc_link *link,
1016 enum dc_dp_training_pattern training_pattern)
1017 {
1018 union dpcd_training_pattern dpcd_pattern = {0};
1019
1020 dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
1021 dp_training_pattern_to_dpcd_training_pattern(
1022 link, training_pattern);
1023
1024 core_link_write_dpcd(
1025 link,
1026 DP_TRAINING_PATTERN_SET,
1027 &dpcd_pattern.raw,
1028 1);
1029
1030 DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
1031 __func__,
1032 DP_TRAINING_PATTERN_SET,
1033 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1034 }
1035
dpcd_set_link_settings(struct dc_link * link,const struct link_training_settings * lt_settings)1036 enum dc_status dpcd_set_link_settings(
1037 struct dc_link *link,
1038 const struct link_training_settings *lt_settings)
1039 {
1040 uint8_t rate;
1041 enum dc_status status;
1042
1043 union down_spread_ctrl downspread = {0};
1044 union lane_count_set lane_count_set = {0};
1045
1046 downspread.raw = (uint8_t)
1047 (lt_settings->link_settings.link_spread);
1048
1049 lane_count_set.bits.LANE_COUNT_SET =
1050 lt_settings->link_settings.lane_count;
1051
1052 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
1053 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1054
1055
1056 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
1057 lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
1058 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
1059 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
1060 }
1061
1062 status = core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1063 &downspread.raw, sizeof(downspread));
1064
1065 status = core_link_write_dpcd(link, DP_LANE_COUNT_SET,
1066 &lane_count_set.raw, 1);
1067
1068 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13 &&
1069 lt_settings->link_settings.use_link_rate_set == true) {
1070 rate = 0;
1071 /* WA for some MUX chips that will power down with eDP and lose supported
1072 * link rate set for eDP 1.4. Source reads DPCD 0x010 again to ensure
1073 * MUX chip gets link rate set back before link training.
1074 */
1075 if (link->connector_signal == SIGNAL_TYPE_EDP) {
1076 uint8_t supported_link_rates[16];
1077
1078 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
1079 supported_link_rates, sizeof(supported_link_rates));
1080 }
1081 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
1082 status = core_link_write_dpcd(link, DP_LINK_RATE_SET,
1083 <_settings->link_settings.link_rate_set, 1);
1084 } else {
1085 rate = get_dpcd_link_rate(<_settings->link_settings);
1086
1087 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
1088 }
1089
1090 if (rate) {
1091 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
1092 __func__,
1093 DP_LINK_BW_SET,
1094 lt_settings->link_settings.link_rate,
1095 DP_LANE_COUNT_SET,
1096 lt_settings->link_settings.lane_count,
1097 lt_settings->enhanced_framing,
1098 DP_DOWNSPREAD_CTRL,
1099 lt_settings->link_settings.link_spread);
1100 } else {
1101 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
1102 __func__,
1103 DP_LINK_RATE_SET,
1104 lt_settings->link_settings.link_rate_set,
1105 DP_LANE_COUNT_SET,
1106 lt_settings->link_settings.lane_count,
1107 lt_settings->enhanced_framing,
1108 DP_DOWNSPREAD_CTRL,
1109 lt_settings->link_settings.link_spread);
1110 }
1111
1112 return status;
1113 }
1114
dpcd_set_lane_settings(struct dc_link * link,const struct link_training_settings * link_training_setting,uint32_t offset)1115 enum dc_status dpcd_set_lane_settings(
1116 struct dc_link *link,
1117 const struct link_training_settings *link_training_setting,
1118 uint32_t offset)
1119 {
1120 unsigned int lane0_set_address;
1121 enum dc_status status;
1122 lane0_set_address = DP_TRAINING_LANE0_SET;
1123
1124 if (is_repeater(link_training_setting, offset))
1125 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
1126 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1127
1128 status = core_link_write_dpcd(link,
1129 lane0_set_address,
1130 (uint8_t *)(link_training_setting->dpcd_lane_settings),
1131 link_training_setting->link_settings.lane_count);
1132
1133 if (is_repeater(link_training_setting, offset)) {
1134 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
1135 " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
1136 __func__,
1137 offset,
1138 lane0_set_address,
1139 link_training_setting->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET,
1140 link_training_setting->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET,
1141 link_training_setting->dpcd_lane_settings[0].bits.MAX_SWING_REACHED,
1142 link_training_setting->dpcd_lane_settings[0].bits.MAX_PRE_EMPHASIS_REACHED);
1143
1144 } else {
1145 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
1146 __func__,
1147 lane0_set_address,
1148 link_training_setting->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET,
1149 link_training_setting->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET,
1150 link_training_setting->dpcd_lane_settings[0].bits.MAX_SWING_REACHED,
1151 link_training_setting->dpcd_lane_settings[0].bits.MAX_PRE_EMPHASIS_REACHED);
1152 }
1153
1154 return status;
1155 }
1156
dpcd_set_lt_pattern_and_lane_settings(struct dc_link * link,const struct link_training_settings * lt_settings,enum dc_dp_training_pattern pattern,uint32_t offset)1157 void dpcd_set_lt_pattern_and_lane_settings(
1158 struct dc_link *link,
1159 const struct link_training_settings *lt_settings,
1160 enum dc_dp_training_pattern pattern,
1161 uint32_t offset)
1162 {
1163 uint32_t dpcd_base_lt_offset;
1164 uint8_t dpcd_lt_buffer[5] = {0};
1165 union dpcd_training_pattern dpcd_pattern = {0};
1166 uint32_t size_in_bytes;
1167 bool edp_workaround = false; /* TODO link_prop.INTERNAL */
1168 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
1169
1170 if (is_repeater(lt_settings, offset))
1171 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1172 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1173
1174 /*****************************************************************
1175 * DpcdAddress_TrainingPatternSet
1176 *****************************************************************/
1177 dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
1178 dp_training_pattern_to_dpcd_training_pattern(link, pattern);
1179
1180 dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
1181 dp_initialize_scrambling_data_symbols(link, pattern);
1182
1183 dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
1184 = dpcd_pattern.raw;
1185
1186 if (is_repeater(lt_settings, offset)) {
1187 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
1188 __func__,
1189 offset,
1190 dpcd_base_lt_offset,
1191 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1192 } else {
1193 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
1194 __func__,
1195 dpcd_base_lt_offset,
1196 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1197 }
1198
1199 /* concatenate everything into one buffer*/
1200 size_in_bytes = lt_settings->link_settings.lane_count *
1201 sizeof(lt_settings->dpcd_lane_settings[0]);
1202
1203 // 0x00103 - 0x00102
1204 memmove(
1205 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
1206 lt_settings->dpcd_lane_settings,
1207 size_in_bytes);
1208
1209 if (is_repeater(lt_settings, offset)) {
1210 if (link_dp_get_encoding_format(<_settings->link_settings) ==
1211 DP_128b_132b_ENCODING)
1212 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
1213 " 0x%X TX_FFE_PRESET_VALUE = %x\n",
1214 __func__,
1215 offset,
1216 dpcd_base_lt_offset,
1217 lt_settings->dpcd_lane_settings[0].tx_ffe.PRESET_VALUE);
1218 else if (link_dp_get_encoding_format(<_settings->link_settings) ==
1219 DP_8b_10b_ENCODING)
1220 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
1221 " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
1222 __func__,
1223 offset,
1224 dpcd_base_lt_offset,
1225 lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET,
1226 lt_settings->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET,
1227 lt_settings->dpcd_lane_settings[0].bits.MAX_SWING_REACHED,
1228 lt_settings->dpcd_lane_settings[0].bits.MAX_PRE_EMPHASIS_REACHED);
1229 } else {
1230 if (link_dp_get_encoding_format(<_settings->link_settings) ==
1231 DP_128b_132b_ENCODING)
1232 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X TX_FFE_PRESET_VALUE = %x\n",
1233 __func__,
1234 dpcd_base_lt_offset,
1235 lt_settings->dpcd_lane_settings[0].tx_ffe.PRESET_VALUE);
1236 else if (link_dp_get_encoding_format(<_settings->link_settings) ==
1237 DP_8b_10b_ENCODING)
1238 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
1239 __func__,
1240 dpcd_base_lt_offset,
1241 lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET,
1242 lt_settings->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET,
1243 lt_settings->dpcd_lane_settings[0].bits.MAX_SWING_REACHED,
1244 lt_settings->dpcd_lane_settings[0].bits.MAX_PRE_EMPHASIS_REACHED);
1245 }
1246 if (edp_workaround) {
1247 /* for eDP write in 2 parts because the 5-byte burst is
1248 * causing issues on some eDP panels (EPR#366724)
1249 */
1250 core_link_write_dpcd(
1251 link,
1252 DP_TRAINING_PATTERN_SET,
1253 &dpcd_pattern.raw,
1254 sizeof(dpcd_pattern.raw));
1255
1256 core_link_write_dpcd(
1257 link,
1258 DP_TRAINING_LANE0_SET,
1259 (uint8_t *)(lt_settings->dpcd_lane_settings),
1260 size_in_bytes);
1261
1262 } else if (link_dp_get_encoding_format(<_settings->link_settings) ==
1263 DP_128b_132b_ENCODING) {
1264 core_link_write_dpcd(
1265 link,
1266 dpcd_base_lt_offset,
1267 dpcd_lt_buffer,
1268 sizeof(dpcd_lt_buffer));
1269 } else
1270 /* write it all in (1 + number-of-lanes)-byte burst*/
1271 core_link_write_dpcd(
1272 link,
1273 dpcd_base_lt_offset,
1274 dpcd_lt_buffer,
1275 size_in_bytes + sizeof(dpcd_pattern.raw));
1276 }
1277
start_clock_recovery_pattern_early(struct dc_link * link,const struct link_resource * link_res,struct link_training_settings * lt_settings,uint32_t offset)1278 void start_clock_recovery_pattern_early(struct dc_link *link,
1279 const struct link_resource *link_res,
1280 struct link_training_settings *lt_settings,
1281 uint32_t offset)
1282 {
1283 DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
1284 __func__);
1285 dp_set_hw_training_pattern(link, link_res, lt_settings->pattern_for_cr, offset);
1286 dp_set_hw_lane_settings(link, link_res, lt_settings, offset);
1287 udelay(400);
1288 }
1289
dp_set_hw_test_pattern(struct dc_link * link,const struct link_resource * link_res,enum dp_test_pattern test_pattern,uint8_t * custom_pattern,uint32_t custom_pattern_size)1290 void dp_set_hw_test_pattern(
1291 struct dc_link *link,
1292 const struct link_resource *link_res,
1293 enum dp_test_pattern test_pattern,
1294 uint8_t *custom_pattern,
1295 uint32_t custom_pattern_size)
1296 {
1297 const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
1298 struct encoder_set_dp_phy_pattern_param pattern_param = {0};
1299
1300 pattern_param.dp_phy_pattern = test_pattern;
1301 pattern_param.custom_pattern = custom_pattern;
1302 pattern_param.custom_pattern_size = custom_pattern_size;
1303 pattern_param.dp_panel_mode = dp_get_panel_mode(link);
1304
1305 if (link_hwss->ext.set_dp_link_test_pattern)
1306 link_hwss->ext.set_dp_link_test_pattern(link, link_res, &pattern_param);
1307 }
1308
dp_set_hw_training_pattern(struct dc_link * link,const struct link_resource * link_res,enum dc_dp_training_pattern pattern,uint32_t offset)1309 bool dp_set_hw_training_pattern(
1310 struct dc_link *link,
1311 const struct link_resource *link_res,
1312 enum dc_dp_training_pattern pattern,
1313 uint32_t offset)
1314 {
1315 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
1316
1317 switch (pattern) {
1318 case DP_TRAINING_PATTERN_SEQUENCE_1:
1319 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN1;
1320 break;
1321 case DP_TRAINING_PATTERN_SEQUENCE_2:
1322 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN2;
1323 break;
1324 case DP_TRAINING_PATTERN_SEQUENCE_3:
1325 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN3;
1326 break;
1327 case DP_TRAINING_PATTERN_SEQUENCE_4:
1328 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
1329 break;
1330 case DP_128b_132b_TPS1:
1331 test_pattern = DP_TEST_PATTERN_128b_132b_TPS1_TRAINING_MODE;
1332 break;
1333 case DP_128b_132b_TPS2:
1334 test_pattern = DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE;
1335 break;
1336 default:
1337 break;
1338 }
1339
1340 dp_set_hw_test_pattern(link, link_res, test_pattern, NULL, 0);
1341
1342 return true;
1343 }
1344
perform_post_lt_adj_req_sequence(struct dc_link * link,const struct link_resource * link_res,struct link_training_settings * lt_settings)1345 static bool perform_post_lt_adj_req_sequence(
1346 struct dc_link *link,
1347 const struct link_resource *link_res,
1348 struct link_training_settings *lt_settings)
1349 {
1350 enum dc_lane_count lane_count =
1351 lt_settings->link_settings.lane_count;
1352
1353 uint32_t adj_req_count;
1354 uint32_t adj_req_timer;
1355 bool req_drv_setting_changed;
1356 uint32_t lane;
1357 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
1358 union lane_align_status_updated dpcd_lane_status_updated = {0};
1359 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
1360
1361 req_drv_setting_changed = false;
1362 for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
1363 adj_req_count++) {
1364
1365 req_drv_setting_changed = false;
1366
1367 for (adj_req_timer = 0;
1368 adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
1369 adj_req_timer++) {
1370
1371 dp_get_lane_status_and_lane_adjust(
1372 link,
1373 lt_settings,
1374 dpcd_lane_status,
1375 &dpcd_lane_status_updated,
1376 dpcd_lane_adjust,
1377 DPRX);
1378
1379 if (dpcd_lane_status_updated.bits.
1380 POST_LT_ADJ_REQ_IN_PROGRESS == 0)
1381 return true;
1382
1383 if (!dp_is_cr_done(lane_count, dpcd_lane_status))
1384 return false;
1385
1386 if (!dp_is_ch_eq_done(lane_count, dpcd_lane_status) ||
1387 !dp_is_symbol_locked(lane_count, dpcd_lane_status) ||
1388 !dp_is_interlane_aligned(dpcd_lane_status_updated))
1389 return false;
1390
1391 for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
1392
1393 if (lt_settings->
1394 dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET !=
1395 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_LANE ||
1396 lt_settings->dpcd_lane_settings[lane].bits.PRE_EMPHASIS_SET !=
1397 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_LANE) {
1398
1399 req_drv_setting_changed = true;
1400 break;
1401 }
1402 }
1403
1404 if (req_drv_setting_changed) {
1405 dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
1406 lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
1407
1408 dp_set_drive_settings(link,
1409 link_res,
1410 lt_settings);
1411 break;
1412 }
1413
1414 msleep(1);
1415 }
1416
1417 if (!req_drv_setting_changed) {
1418 DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
1419 __func__);
1420
1421 ASSERT(0);
1422 return true;
1423 }
1424 }
1425 DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
1426 __func__);
1427
1428 ASSERT(0);
1429 return true;
1430
1431 }
1432
dp_transition_to_video_idle(struct dc_link * link,const struct link_resource * link_res,struct link_training_settings * lt_settings,enum link_training_result status)1433 static enum link_training_result dp_transition_to_video_idle(
1434 struct dc_link *link,
1435 const struct link_resource *link_res,
1436 struct link_training_settings *lt_settings,
1437 enum link_training_result status)
1438 {
1439 union lane_count_set lane_count_set = {0};
1440
1441 /* 4. mainlink output idle pattern*/
1442 dp_set_hw_test_pattern(link, link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1443
1444 /*
1445 * 5. post training adjust if required
1446 * If the upstream DPTX and downstream DPRX both support TPS4,
1447 * TPS4 must be used instead of POST_LT_ADJ_REQ.
1448 */
1449 if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
1450 lt_settings->pattern_for_eq >= DP_TRAINING_PATTERN_SEQUENCE_4) {
1451 /* delay 5ms after Main Link output idle pattern and then check
1452 * DPCD 0202h.
1453 */
1454 if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
1455 msleep(5);
1456 status = dp_check_link_loss_status(link, lt_settings);
1457 }
1458 return status;
1459 }
1460
1461 if (status == LINK_TRAINING_SUCCESS &&
1462 perform_post_lt_adj_req_sequence(link, link_res, lt_settings) == false)
1463 status = LINK_TRAINING_LQA_FAIL;
1464
1465 lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
1466 lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
1467 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1468
1469 core_link_write_dpcd(
1470 link,
1471 DP_LANE_COUNT_SET,
1472 &lane_count_set.raw,
1473 sizeof(lane_count_set));
1474
1475 return status;
1476 }
1477
dp_perform_link_training(struct dc_link * link,const struct link_resource * link_res,const struct dc_link_settings * link_settings,bool skip_video_pattern)1478 enum link_training_result dp_perform_link_training(
1479 struct dc_link *link,
1480 const struct link_resource *link_res,
1481 const struct dc_link_settings *link_settings,
1482 bool skip_video_pattern)
1483 {
1484 enum link_training_result status = LINK_TRAINING_SUCCESS;
1485 struct link_training_settings lt_settings = {0};
1486 enum dp_link_encoding encoding =
1487 link_dp_get_encoding_format(link_settings);
1488
1489 /* decide training settings */
1490 dp_decide_training_settings(
1491 link,
1492 link_settings,
1493 <_settings);
1494
1495 override_training_settings(
1496 link,
1497 &link->preferred_training_settings,
1498 <_settings);
1499
1500 /* reset previous training states */
1501 dpcd_exit_training_mode(link, encoding);
1502
1503 /* configure link prior to entering training mode */
1504 dpcd_configure_lttpr_mode(link, <_settings);
1505 dp_set_fec_ready(link, link_res, lt_settings.should_set_fec_ready);
1506 dpcd_configure_channel_coding(link, <_settings);
1507
1508 /* enter training mode:
1509 * Per DP specs starting from here, DPTX device shall not issue
1510 * Non-LT AUX transactions inside training mode.
1511 */
1512 if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && encoding == DP_8b_10b_ENCODING)
1513 if (link->dc->config.use_old_fixed_vs_sequence)
1514 status = dp_perform_fixed_vs_pe_training_sequence_legacy(link, link_res, <_settings);
1515 else
1516 status = dp_perform_fixed_vs_pe_training_sequence(link, link_res, <_settings);
1517 else if (encoding == DP_8b_10b_ENCODING)
1518 status = dp_perform_8b_10b_link_training(link, link_res, <_settings);
1519 else if (encoding == DP_128b_132b_ENCODING)
1520 status = dp_perform_128b_132b_link_training(link, link_res, <_settings);
1521 else
1522 ASSERT(0);
1523
1524 /* exit training mode */
1525 dpcd_exit_training_mode(link, encoding);
1526
1527 /* switch to video idle */
1528 if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern)
1529 status = dp_transition_to_video_idle(link,
1530 link_res,
1531 <_settings,
1532 status);
1533
1534 /* dump debug data */
1535 dp_log_training_result(link, <_settings, status);
1536 if (status != LINK_TRAINING_SUCCESS)
1537 link->ctx->dc->debug_data.ltFailCount++;
1538 return status;
1539 }
1540
perform_link_training_with_retries(const struct dc_link_settings * link_setting,bool skip_video_pattern,int attempts,struct pipe_ctx * pipe_ctx,enum signal_type signal,bool do_fallback)1541 bool perform_link_training_with_retries(
1542 const struct dc_link_settings *link_setting,
1543 bool skip_video_pattern,
1544 int attempts,
1545 struct pipe_ctx *pipe_ctx,
1546 enum signal_type signal,
1547 bool do_fallback)
1548 {
1549 int j;
1550 uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1551 struct dc_stream_state *stream = pipe_ctx->stream;
1552 struct dc_link *link = stream->link;
1553 enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
1554 enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
1555 struct dc_link_settings cur_link_settings = *link_setting;
1556 struct dc_link_settings max_link_settings = *link_setting;
1557 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
1558 int fail_count = 0;
1559 bool is_link_bw_low = false; /* link bandwidth < stream bandwidth */
1560 bool is_link_bw_min = /* RBR x 1 */
1561 (cur_link_settings.link_rate <= LINK_RATE_LOW) &&
1562 (cur_link_settings.lane_count <= LANE_COUNT_ONE);
1563
1564 dp_trace_commit_lt_init(link);
1565
1566
1567 if (link_dp_get_encoding_format(&cur_link_settings) == DP_8b_10b_ENCODING)
1568 /* We need to do this before the link training to ensure the idle
1569 * pattern in SST mode will be sent right after the link training
1570 */
1571 link_hwss->setup_stream_encoder(pipe_ctx);
1572
1573 dp_trace_set_lt_start_timestamp(link, false);
1574 j = 0;
1575 while (j < attempts && fail_count < (attempts * 10)) {
1576
1577 DC_LOG_HW_LINK_TRAINING("%s: Beginning link(%d) training attempt %u of %d @ rate(%d) x lane(%d) @ spread = %x\n",
1578 __func__, link->link_index, (unsigned int)j + 1, attempts,
1579 cur_link_settings.link_rate, cur_link_settings.lane_count,
1580 cur_link_settings.link_spread);
1581
1582 dp_enable_link_phy(
1583 link,
1584 &pipe_ctx->link_res,
1585 signal,
1586 pipe_ctx->clock_source->id,
1587 &cur_link_settings);
1588
1589 if (stream->sink_patches.dppowerup_delay > 0) {
1590 int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1591
1592 msleep(delay_dp_power_up_in_ms);
1593 }
1594
1595 if (panel_mode == DP_PANEL_MODE_EDP) {
1596 struct cp_psp *cp_psp = &stream->ctx->cp_psp;
1597
1598 if (cp_psp && cp_psp->funcs.enable_assr) {
1599 /* ASSR is bound to fail with unsigned PSP
1600 * verstage used during devlopment phase.
1601 * Report and continue with eDP panel mode to
1602 * perform eDP link training with right settings
1603 */
1604 bool result;
1605 result = cp_psp->funcs.enable_assr(cp_psp->handle, link);
1606 if (!result && link->panel_mode != DP_PANEL_MODE_EDP)
1607 panel_mode = DP_PANEL_MODE_DEFAULT;
1608 }
1609 }
1610
1611 dp_set_panel_mode(link, panel_mode);
1612
1613 if (link->aux_access_disabled) {
1614 dp_perform_link_training_skip_aux(link, &pipe_ctx->link_res, &cur_link_settings);
1615 return true;
1616 } else {
1617 /** @todo Consolidate USB4 DP and DPx.x training. */
1618 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
1619 status = dpia_perform_link_training(
1620 link,
1621 &pipe_ctx->link_res,
1622 &cur_link_settings,
1623 skip_video_pattern);
1624
1625 /* Transmit idle pattern once training successful. */
1626 if (status == LINK_TRAINING_SUCCESS && !is_link_bw_low) {
1627 dp_set_hw_test_pattern(link, &pipe_ctx->link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1628 // Update verified link settings to current one
1629 // Because DPIA LT might fallback to lower link setting.
1630 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1631 link->verified_link_cap.link_rate = link->cur_link_settings.link_rate;
1632 link->verified_link_cap.lane_count = link->cur_link_settings.lane_count;
1633 dm_helpers_dp_mst_update_branch_bandwidth(link->ctx, link);
1634 }
1635 }
1636 } else {
1637 status = dp_perform_link_training(
1638 link,
1639 &pipe_ctx->link_res,
1640 &cur_link_settings,
1641 skip_video_pattern);
1642 }
1643
1644 dp_trace_lt_total_count_increment(link, false);
1645 dp_trace_lt_result_update(link, status, false);
1646 dp_trace_set_lt_end_timestamp(link, false);
1647 if (status == LINK_TRAINING_SUCCESS && !is_link_bw_low)
1648 return true;
1649 }
1650
1651 fail_count++;
1652 dp_trace_lt_fail_count_update(link, fail_count, false);
1653 if (link->ep_type == DISPLAY_ENDPOINT_PHY) {
1654 /* latest link training still fail or link training is aborted
1655 * skip delay and keep PHY on
1656 */
1657 if (j == (attempts - 1) || (status == LINK_TRAINING_ABORT))
1658 break;
1659 }
1660
1661 if (j == (attempts - 1)) {
1662 DC_LOG_WARNING(
1663 "%s: Link(%d) training attempt %u of %d failed @ rate(%d) x lane(%d) @ spread = %x : fail reason:(%d)\n",
1664 __func__, link->link_index, (unsigned int)j + 1, attempts,
1665 cur_link_settings.link_rate, cur_link_settings.lane_count,
1666 cur_link_settings.link_spread, status);
1667 } else {
1668 DC_LOG_HW_LINK_TRAINING(
1669 "%s: Link(%d) training attempt %u of %d failed @ rate(%d) x lane(%d) @ spread = %x : fail reason:(%d)\n",
1670 __func__, link->link_index, (unsigned int)j + 1, attempts,
1671 cur_link_settings.link_rate, cur_link_settings.lane_count,
1672 cur_link_settings.link_spread, status);
1673 }
1674
1675 dp_disable_link_phy(link, &pipe_ctx->link_res, signal);
1676
1677 /* Abort link training if failure due to sink being unplugged. */
1678 if (status == LINK_TRAINING_ABORT) {
1679 enum dc_connection_type type = dc_connection_none;
1680
1681 link_detect_connection_type(link, &type);
1682 if (type == dc_connection_none) {
1683 DC_LOG_HW_LINK_TRAINING("%s: Aborting training because sink unplugged\n", __func__);
1684 break;
1685 }
1686 }
1687
1688 /* Try to train again at original settings if:
1689 * - not falling back between training attempts;
1690 * - aborted previous attempt due to reasons other than sink unplug;
1691 * - successfully trained but at a link rate lower than that required by stream;
1692 * - reached minimum link bandwidth.
1693 */
1694 if (!do_fallback || (status == LINK_TRAINING_ABORT) ||
1695 (status == LINK_TRAINING_SUCCESS && is_link_bw_low) ||
1696 is_link_bw_min) {
1697 j++;
1698 cur_link_settings = *link_setting;
1699 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1700 is_link_bw_low = false;
1701 is_link_bw_min = (cur_link_settings.link_rate <= LINK_RATE_LOW) &&
1702 (cur_link_settings.lane_count <= LANE_COUNT_ONE);
1703
1704 } else if (do_fallback) { /* Try training at lower link bandwidth if doing fallback. */
1705 uint32_t req_bw;
1706 uint32_t link_bw;
1707 enum dc_link_encoding_format link_encoding = DC_LINK_ENCODING_UNSPECIFIED;
1708
1709 decide_fallback_link_setting(link, &max_link_settings,
1710 &cur_link_settings, status);
1711
1712 if (link_dp_get_encoding_format(&cur_link_settings) == DP_8b_10b_ENCODING)
1713 link_encoding = DC_LINK_ENCODING_DP_8b_10b;
1714 else if (link_dp_get_encoding_format(&cur_link_settings) == DP_128b_132b_ENCODING)
1715 link_encoding = DC_LINK_ENCODING_DP_128b_132b;
1716
1717 /* Flag if reduced link bandwidth no longer meets stream requirements or fallen back to
1718 * minimum link bandwidth.
1719 */
1720 req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, link_encoding);
1721 link_bw = dp_link_bandwidth_kbps(link, &cur_link_settings);
1722 is_link_bw_low = (req_bw > link_bw);
1723 is_link_bw_min = ((cur_link_settings.link_rate <= LINK_RATE_LOW) &&
1724 (cur_link_settings.lane_count <= LANE_COUNT_ONE));
1725
1726 if (is_link_bw_low)
1727 DC_LOG_WARNING(
1728 "%s: Link(%d) bandwidth too low after fallback req_bw(%d) > link_bw(%d)\n",
1729 __func__, link->link_index, req_bw, link_bw);
1730 }
1731
1732 msleep(delay_between_attempts);
1733 }
1734
1735 return false;
1736 }
1737
1738