1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
3 /*
4 Copyright (c) 2001, 2002 by D-Link Corporation
5 Written by Edward Peng.<edward_peng@dlink.com.tw>
6 Created 03-May-2001, base on Linux' sundance.c.
7
8 */
9
10 #include "dl2k.h"
11 #include <linux/dma-mapping.h>
12
13 #define dw32(reg, val) iowrite32(val, ioaddr + (reg))
14 #define dw16(reg, val) iowrite16(val, ioaddr + (reg))
15 #define dw8(reg, val) iowrite8(val, ioaddr + (reg))
16 #define dr32(reg) ioread32(ioaddr + (reg))
17 #define dr16(reg) ioread16(ioaddr + (reg))
18 #define dr8(reg) ioread8(ioaddr + (reg))
19
20 #define MAX_UNITS 8
21 static int mtu[MAX_UNITS];
22 static int vlan[MAX_UNITS];
23 static int jumbo[MAX_UNITS];
24 static char *media[MAX_UNITS];
25 static int tx_flow=-1;
26 static int rx_flow=-1;
27 static int copy_thresh;
28 static int rx_coalesce=10; /* Rx frame count each interrupt */
29 static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
30 static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
31
32
33 MODULE_AUTHOR ("Edward Peng");
34 MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
35 MODULE_LICENSE("GPL");
36 module_param_array(mtu, int, NULL, 0);
37 module_param_array(media, charp, NULL, 0);
38 module_param_array(vlan, int, NULL, 0);
39 module_param_array(jumbo, int, NULL, 0);
40 module_param(tx_flow, int, 0);
41 module_param(rx_flow, int, 0);
42 module_param(copy_thresh, int, 0);
43 module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
44 module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
45 module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
46
47
48 /* Enable the default interrupts */
49 #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
50 UpdateStats | LinkEvent)
51
dl2k_enable_int(struct netdev_private * np)52 static void dl2k_enable_int(struct netdev_private *np)
53 {
54 void __iomem *ioaddr = np->ioaddr;
55
56 dw16(IntEnable, DEFAULT_INTR);
57 }
58
59 static const int max_intrloop = 50;
60 static const int multicast_filter_limit = 0x40;
61
62 static int rio_open (struct net_device *dev);
63 static void rio_timer (struct timer_list *t);
64 static void rio_tx_timeout (struct net_device *dev, unsigned int txqueue);
65 static netdev_tx_t start_xmit (struct sk_buff *skb, struct net_device *dev);
66 static irqreturn_t rio_interrupt (int irq, void *dev_instance);
67 static void rio_free_tx (struct net_device *dev, int irq);
68 static void tx_error (struct net_device *dev, int tx_status);
69 static int receive_packet (struct net_device *dev);
70 static void rio_error (struct net_device *dev, int int_status);
71 static void set_multicast (struct net_device *dev);
72 static struct net_device_stats *get_stats (struct net_device *dev);
73 static int clear_stats (struct net_device *dev);
74 static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
75 static int rio_close (struct net_device *dev);
76 static int find_miiphy (struct net_device *dev);
77 static int parse_eeprom (struct net_device *dev);
78 static int read_eeprom (struct netdev_private *, int eep_addr);
79 static int mii_wait_link (struct net_device *dev, int wait);
80 static int mii_set_media (struct net_device *dev);
81 static int mii_get_media (struct net_device *dev);
82 static int mii_set_media_pcs (struct net_device *dev);
83 static int mii_get_media_pcs (struct net_device *dev);
84 static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
85 static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
86 u16 data);
87
88 static const struct ethtool_ops ethtool_ops;
89
90 static const struct net_device_ops netdev_ops = {
91 .ndo_open = rio_open,
92 .ndo_start_xmit = start_xmit,
93 .ndo_stop = rio_close,
94 .ndo_get_stats = get_stats,
95 .ndo_validate_addr = eth_validate_addr,
96 .ndo_set_mac_address = eth_mac_addr,
97 .ndo_set_rx_mode = set_multicast,
98 .ndo_eth_ioctl = rio_ioctl,
99 .ndo_tx_timeout = rio_tx_timeout,
100 };
101
102 static int
rio_probe1(struct pci_dev * pdev,const struct pci_device_id * ent)103 rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
104 {
105 struct net_device *dev;
106 struct netdev_private *np;
107 static int card_idx;
108 int chip_idx = ent->driver_data;
109 int err, irq;
110 void __iomem *ioaddr;
111 void *ring_space;
112 dma_addr_t ring_dma;
113
114 err = pci_enable_device (pdev);
115 if (err)
116 return err;
117
118 irq = pdev->irq;
119 err = pci_request_regions (pdev, "dl2k");
120 if (err)
121 goto err_out_disable;
122
123 pci_set_master (pdev);
124
125 err = -ENOMEM;
126
127 dev = alloc_etherdev (sizeof (*np));
128 if (!dev)
129 goto err_out_res;
130 SET_NETDEV_DEV(dev, &pdev->dev);
131
132 np = netdev_priv(dev);
133
134 /* IO registers range. */
135 ioaddr = pci_iomap(pdev, 0, 0);
136 if (!ioaddr)
137 goto err_out_dev;
138 np->eeprom_addr = ioaddr;
139
140 #ifdef MEM_MAPPING
141 /* MM registers range. */
142 ioaddr = pci_iomap(pdev, 1, 0);
143 if (!ioaddr)
144 goto err_out_iounmap;
145 #endif
146 np->ioaddr = ioaddr;
147 np->chip_id = chip_idx;
148 np->pdev = pdev;
149
150 spin_lock_init(&np->stats_lock);
151 spin_lock_init (&np->tx_lock);
152 spin_lock_init (&np->rx_lock);
153
154 /* Parse manual configuration */
155 np->an_enable = 1;
156 np->tx_coalesce = 1;
157 if (card_idx < MAX_UNITS) {
158 if (media[card_idx] != NULL) {
159 np->an_enable = 0;
160 if (strcmp (media[card_idx], "auto") == 0 ||
161 strcmp (media[card_idx], "autosense") == 0 ||
162 strcmp (media[card_idx], "0") == 0 ) {
163 np->an_enable = 2;
164 } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
165 strcmp (media[card_idx], "4") == 0) {
166 np->speed = 100;
167 np->full_duplex = 1;
168 } else if (strcmp (media[card_idx], "100mbps_hd") == 0 ||
169 strcmp (media[card_idx], "3") == 0) {
170 np->speed = 100;
171 np->full_duplex = 0;
172 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
173 strcmp (media[card_idx], "2") == 0) {
174 np->speed = 10;
175 np->full_duplex = 1;
176 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
177 strcmp (media[card_idx], "1") == 0) {
178 np->speed = 10;
179 np->full_duplex = 0;
180 } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
181 strcmp (media[card_idx], "6") == 0) {
182 np->speed=1000;
183 np->full_duplex=1;
184 } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
185 strcmp (media[card_idx], "5") == 0) {
186 np->speed = 1000;
187 np->full_duplex = 0;
188 } else {
189 np->an_enable = 1;
190 }
191 }
192 if (jumbo[card_idx] != 0) {
193 np->jumbo = 1;
194 dev->mtu = MAX_JUMBO;
195 } else {
196 np->jumbo = 0;
197 if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
198 dev->mtu = mtu[card_idx];
199 }
200 np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
201 vlan[card_idx] : 0;
202 if (rx_coalesce > 0 && rx_timeout > 0) {
203 np->rx_coalesce = rx_coalesce;
204 np->rx_timeout = rx_timeout;
205 np->coalesce = 1;
206 }
207 np->tx_flow = (tx_flow == 0) ? 0 : 1;
208 np->rx_flow = (rx_flow == 0) ? 0 : 1;
209
210 if (tx_coalesce < 1)
211 tx_coalesce = 1;
212 else if (tx_coalesce > TX_RING_SIZE-1)
213 tx_coalesce = TX_RING_SIZE - 1;
214 }
215 dev->netdev_ops = &netdev_ops;
216 dev->watchdog_timeo = TX_TIMEOUT;
217 dev->ethtool_ops = ðtool_ops;
218 #if 0
219 dev->features = NETIF_F_IP_CSUM;
220 #endif
221 /* MTU range: 68 - 1536 or 8000 */
222 dev->min_mtu = ETH_MIN_MTU;
223 dev->max_mtu = np->jumbo ? MAX_JUMBO : PACKET_SIZE;
224
225 pci_set_drvdata (pdev, dev);
226
227 ring_space = dma_alloc_coherent(&pdev->dev, TX_TOTAL_SIZE, &ring_dma,
228 GFP_KERNEL);
229 if (!ring_space)
230 goto err_out_iounmap;
231 np->tx_ring = ring_space;
232 np->tx_ring_dma = ring_dma;
233
234 ring_space = dma_alloc_coherent(&pdev->dev, RX_TOTAL_SIZE, &ring_dma,
235 GFP_KERNEL);
236 if (!ring_space)
237 goto err_out_unmap_tx;
238 np->rx_ring = ring_space;
239 np->rx_ring_dma = ring_dma;
240
241 /* Parse eeprom data */
242 parse_eeprom (dev);
243
244 /* Find PHY address */
245 err = find_miiphy (dev);
246 if (err)
247 goto err_out_unmap_rx;
248
249 /* Fiber device? */
250 np->phy_media = (dr16(ASICCtrl) & PhyMedia) ? 1 : 0;
251 np->link_status = 0;
252 /* Set media and reset PHY */
253 if (np->phy_media) {
254 /* default Auto-Negotiation for fiber deivices */
255 if (np->an_enable == 2) {
256 np->an_enable = 1;
257 }
258 } else {
259 /* Auto-Negotiation is mandatory for 1000BASE-T,
260 IEEE 802.3ab Annex 28D page 14 */
261 if (np->speed == 1000)
262 np->an_enable = 1;
263 }
264
265 err = register_netdev (dev);
266 if (err)
267 goto err_out_unmap_rx;
268
269 card_idx++;
270
271 printk (KERN_INFO "%s: %s, %pM, IRQ %d\n",
272 dev->name, np->name, dev->dev_addr, irq);
273 if (tx_coalesce > 1)
274 printk(KERN_INFO "tx_coalesce:\t%d packets\n",
275 tx_coalesce);
276 if (np->coalesce)
277 printk(KERN_INFO
278 "rx_coalesce:\t%d packets\n"
279 "rx_timeout: \t%d ns\n",
280 np->rx_coalesce, np->rx_timeout*640);
281 if (np->vlan)
282 printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
283 return 0;
284
285 err_out_unmap_rx:
286 dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, np->rx_ring,
287 np->rx_ring_dma);
288 err_out_unmap_tx:
289 dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, np->tx_ring,
290 np->tx_ring_dma);
291 err_out_iounmap:
292 #ifdef MEM_MAPPING
293 pci_iounmap(pdev, np->ioaddr);
294 #endif
295 pci_iounmap(pdev, np->eeprom_addr);
296 err_out_dev:
297 free_netdev (dev);
298 err_out_res:
299 pci_release_regions (pdev);
300 err_out_disable:
301 pci_disable_device (pdev);
302 return err;
303 }
304
305 static int
find_miiphy(struct net_device * dev)306 find_miiphy (struct net_device *dev)
307 {
308 struct netdev_private *np = netdev_priv(dev);
309 int i, phy_found = 0;
310
311 np->phy_addr = 1;
312
313 for (i = 31; i >= 0; i--) {
314 int mii_status = mii_read (dev, i, 1);
315 if (mii_status != 0xffff && mii_status != 0x0000) {
316 np->phy_addr = i;
317 phy_found++;
318 }
319 }
320 if (!phy_found) {
321 printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
322 return -ENODEV;
323 }
324 return 0;
325 }
326
327 static int
parse_eeprom(struct net_device * dev)328 parse_eeprom (struct net_device *dev)
329 {
330 struct netdev_private *np = netdev_priv(dev);
331 void __iomem *ioaddr = np->ioaddr;
332 int i, j;
333 u8 sromdata[256];
334 u8 *psib;
335 u32 crc;
336 PSROM_t psrom = (PSROM_t) sromdata;
337
338 int cid, next;
339
340 for (i = 0; i < 128; i++)
341 ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom(np, i));
342
343 if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */
344 /* Check CRC */
345 crc = ~ether_crc_le (256 - 4, sromdata);
346 if (psrom->crc != cpu_to_le32(crc)) {
347 printk (KERN_ERR "%s: EEPROM data CRC error.\n",
348 dev->name);
349 return -1;
350 }
351 }
352
353 /* Set MAC address */
354 eth_hw_addr_set(dev, psrom->mac_addr);
355
356 if (np->chip_id == CHIP_IP1000A) {
357 np->led_mode = le16_to_cpu(psrom->led_mode);
358 return 0;
359 }
360
361 if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) {
362 return 0;
363 }
364
365 /* Parse Software Information Block */
366 i = 0x30;
367 psib = (u8 *) sromdata;
368 do {
369 cid = psib[i++];
370 next = psib[i++];
371 if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
372 printk (KERN_ERR "Cell data error\n");
373 return -1;
374 }
375 switch (cid) {
376 case 0: /* Format version */
377 break;
378 case 1: /* End of cell */
379 return 0;
380 case 2: /* Duplex Polarity */
381 np->duplex_polarity = psib[i];
382 dw8(PhyCtrl, dr8(PhyCtrl) | psib[i]);
383 break;
384 case 3: /* Wake Polarity */
385 np->wake_polarity = psib[i];
386 break;
387 case 9: /* Adapter description */
388 j = (next - i > 255) ? 255 : next - i;
389 memcpy (np->name, &(psib[i]), j);
390 break;
391 case 4:
392 case 5:
393 case 6:
394 case 7:
395 case 8: /* Reversed */
396 break;
397 default: /* Unknown cell */
398 return -1;
399 }
400 i = next;
401 } while (1);
402
403 return 0;
404 }
405
rio_set_led_mode(struct net_device * dev)406 static void rio_set_led_mode(struct net_device *dev)
407 {
408 struct netdev_private *np = netdev_priv(dev);
409 void __iomem *ioaddr = np->ioaddr;
410 u32 mode;
411
412 if (np->chip_id != CHIP_IP1000A)
413 return;
414
415 mode = dr32(ASICCtrl);
416 mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
417
418 if (np->led_mode & 0x01)
419 mode |= IPG_AC_LED_MODE;
420 if (np->led_mode & 0x02)
421 mode |= IPG_AC_LED_MODE_BIT_1;
422 if (np->led_mode & 0x08)
423 mode |= IPG_AC_LED_SPEED;
424
425 dw32(ASICCtrl, mode);
426 }
427
desc_to_dma(struct netdev_desc * desc)428 static inline dma_addr_t desc_to_dma(struct netdev_desc *desc)
429 {
430 return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48);
431 }
432
free_list(struct net_device * dev)433 static void free_list(struct net_device *dev)
434 {
435 struct netdev_private *np = netdev_priv(dev);
436 struct sk_buff *skb;
437 int i;
438
439 /* Free all the skbuffs in the queue. */
440 for (i = 0; i < RX_RING_SIZE; i++) {
441 skb = np->rx_skbuff[i];
442 if (skb) {
443 dma_unmap_single(&np->pdev->dev,
444 desc_to_dma(&np->rx_ring[i]),
445 skb->len, DMA_FROM_DEVICE);
446 dev_kfree_skb(skb);
447 np->rx_skbuff[i] = NULL;
448 }
449 np->rx_ring[i].status = 0;
450 np->rx_ring[i].fraginfo = 0;
451 }
452 for (i = 0; i < TX_RING_SIZE; i++) {
453 skb = np->tx_skbuff[i];
454 if (skb) {
455 dma_unmap_single(&np->pdev->dev,
456 desc_to_dma(&np->tx_ring[i]),
457 skb->len, DMA_TO_DEVICE);
458 dev_kfree_skb(skb);
459 np->tx_skbuff[i] = NULL;
460 }
461 }
462 }
463
rio_reset_ring(struct netdev_private * np)464 static void rio_reset_ring(struct netdev_private *np)
465 {
466 int i;
467
468 np->cur_rx = 0;
469 np->cur_tx = 0;
470 np->old_rx = 0;
471 np->old_tx = 0;
472
473 for (i = 0; i < TX_RING_SIZE; i++)
474 np->tx_ring[i].status = cpu_to_le64(TFDDone);
475
476 for (i = 0; i < RX_RING_SIZE; i++)
477 np->rx_ring[i].status = 0;
478 }
479
480 /* allocate and initialize Tx and Rx descriptors */
alloc_list(struct net_device * dev)481 static int alloc_list(struct net_device *dev)
482 {
483 struct netdev_private *np = netdev_priv(dev);
484 int i;
485
486 rio_reset_ring(np);
487 np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
488
489 /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
490 for (i = 0; i < TX_RING_SIZE; i++) {
491 np->tx_skbuff[i] = NULL;
492 np->tx_ring[i].next_desc = cpu_to_le64(np->tx_ring_dma +
493 ((i + 1) % TX_RING_SIZE) *
494 sizeof(struct netdev_desc));
495 }
496
497 /* Initialize Rx descriptors & allocate buffers */
498 for (i = 0; i < RX_RING_SIZE; i++) {
499 /* Allocated fixed size of skbuff */
500 struct sk_buff *skb;
501
502 skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
503 np->rx_skbuff[i] = skb;
504 if (!skb) {
505 free_list(dev);
506 return -ENOMEM;
507 }
508
509 np->rx_ring[i].next_desc = cpu_to_le64(np->rx_ring_dma +
510 ((i + 1) % RX_RING_SIZE) *
511 sizeof(struct netdev_desc));
512 /* Rubicon now supports 40 bits of addressing space. */
513 np->rx_ring[i].fraginfo =
514 cpu_to_le64(dma_map_single(&np->pdev->dev, skb->data,
515 np->rx_buf_sz, DMA_FROM_DEVICE));
516 np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48);
517 }
518
519 return 0;
520 }
521
rio_hw_init(struct net_device * dev)522 static void rio_hw_init(struct net_device *dev)
523 {
524 struct netdev_private *np = netdev_priv(dev);
525 void __iomem *ioaddr = np->ioaddr;
526 int i;
527 u16 macctrl;
528
529 /* Reset all logic functions */
530 dw16(ASICCtrl + 2,
531 GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset);
532 mdelay(10);
533
534 rio_set_led_mode(dev);
535
536 /* DebugCtrl bit 4, 5, 9 must set */
537 dw32(DebugCtrl, dr32(DebugCtrl) | 0x0230);
538
539 if (np->chip_id == CHIP_IP1000A &&
540 (np->pdev->revision == 0x40 || np->pdev->revision == 0x41)) {
541 /* PHY magic taken from ipg driver, undocumented registers */
542 mii_write(dev, np->phy_addr, 31, 0x0001);
543 mii_write(dev, np->phy_addr, 27, 0x01e0);
544 mii_write(dev, np->phy_addr, 31, 0x0002);
545 mii_write(dev, np->phy_addr, 27, 0xeb8e);
546 mii_write(dev, np->phy_addr, 31, 0x0000);
547 mii_write(dev, np->phy_addr, 30, 0x005e);
548 /* advertise 1000BASE-T half & full duplex, prefer MASTER */
549 mii_write(dev, np->phy_addr, MII_CTRL1000, 0x0700);
550 }
551
552 if (np->phy_media)
553 mii_set_media_pcs(dev);
554 else
555 mii_set_media(dev);
556
557 /* Jumbo frame */
558 if (np->jumbo != 0)
559 dw16(MaxFrameSize, MAX_JUMBO+14);
560
561 /* Set RFDListPtr */
562 dw32(RFDListPtr0, np->rx_ring_dma);
563 dw32(RFDListPtr1, 0);
564
565 /* Set station address */
566 /* 16 or 32-bit access is required by TC9020 datasheet but 8-bit works
567 * too. However, it doesn't work on IP1000A so we use 16-bit access.
568 */
569 for (i = 0; i < 3; i++)
570 dw16(StationAddr0 + 2 * i,
571 cpu_to_le16(((const u16 *)dev->dev_addr)[i]));
572
573 set_multicast (dev);
574 if (np->coalesce) {
575 dw32(RxDMAIntCtrl, np->rx_coalesce | np->rx_timeout << 16);
576 }
577 /* Set RIO to poll every N*320nsec. */
578 dw8(RxDMAPollPeriod, 0x20);
579 dw8(TxDMAPollPeriod, 0xff);
580 dw8(RxDMABurstThresh, 0x30);
581 dw8(RxDMAUrgentThresh, 0x30);
582 dw32(RmonStatMask, 0x0007ffff);
583 /* clear statistics */
584 clear_stats (dev);
585
586 /* VLAN supported */
587 if (np->vlan) {
588 /* priority field in RxDMAIntCtrl */
589 dw32(RxDMAIntCtrl, dr32(RxDMAIntCtrl) | 0x7 << 10);
590 /* VLANId */
591 dw16(VLANId, np->vlan);
592 /* Length/Type should be 0x8100 */
593 dw32(VLANTag, 0x8100 << 16 | np->vlan);
594 /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
595 VLAN information tagged by TFC' VID, CFI fields. */
596 dw32(MACCtrl, dr32(MACCtrl) | AutoVLANuntagging);
597 }
598
599 /* Start Tx/Rx */
600 dw32(MACCtrl, dr32(MACCtrl) | StatsEnable | RxEnable | TxEnable);
601
602 macctrl = 0;
603 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
604 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
605 macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
606 macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
607 dw16(MACCtrl, macctrl);
608 }
609
rio_hw_stop(struct net_device * dev)610 static void rio_hw_stop(struct net_device *dev)
611 {
612 struct netdev_private *np = netdev_priv(dev);
613 void __iomem *ioaddr = np->ioaddr;
614
615 /* Disable interrupts */
616 dw16(IntEnable, 0);
617
618 /* Stop Tx and Rx logics */
619 dw32(MACCtrl, TxDisable | RxDisable | StatsDisable);
620 }
621
rio_open(struct net_device * dev)622 static int rio_open(struct net_device *dev)
623 {
624 struct netdev_private *np = netdev_priv(dev);
625 const int irq = np->pdev->irq;
626 int i;
627
628 i = alloc_list(dev);
629 if (i)
630 return i;
631
632 rio_hw_init(dev);
633
634 i = request_irq(irq, rio_interrupt, IRQF_SHARED, dev->name, dev);
635 if (i) {
636 rio_hw_stop(dev);
637 free_list(dev);
638 return i;
639 }
640
641 timer_setup(&np->timer, rio_timer, 0);
642 np->timer.expires = jiffies + 1 * HZ;
643 add_timer(&np->timer);
644
645 netif_start_queue (dev);
646
647 dl2k_enable_int(np);
648 return 0;
649 }
650
651 static void
rio_timer(struct timer_list * t)652 rio_timer (struct timer_list *t)
653 {
654 struct netdev_private *np = from_timer(np, t, timer);
655 struct net_device *dev = pci_get_drvdata(np->pdev);
656 unsigned int entry;
657 int next_tick = 1*HZ;
658 unsigned long flags;
659
660 spin_lock_irqsave(&np->rx_lock, flags);
661 /* Recover rx ring exhausted error */
662 if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
663 printk(KERN_INFO "Try to recover rx ring exhausted...\n");
664 /* Re-allocate skbuffs to fill the descriptor ring */
665 for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
666 struct sk_buff *skb;
667 entry = np->old_rx % RX_RING_SIZE;
668 /* Dropped packets don't need to re-allocate */
669 if (np->rx_skbuff[entry] == NULL) {
670 skb = netdev_alloc_skb_ip_align(dev,
671 np->rx_buf_sz);
672 if (skb == NULL) {
673 np->rx_ring[entry].fraginfo = 0;
674 printk (KERN_INFO
675 "%s: Still unable to re-allocate Rx skbuff.#%d\n",
676 dev->name, entry);
677 break;
678 }
679 np->rx_skbuff[entry] = skb;
680 np->rx_ring[entry].fraginfo =
681 cpu_to_le64 (dma_map_single(&np->pdev->dev, skb->data,
682 np->rx_buf_sz, DMA_FROM_DEVICE));
683 }
684 np->rx_ring[entry].fraginfo |=
685 cpu_to_le64((u64)np->rx_buf_sz << 48);
686 np->rx_ring[entry].status = 0;
687 } /* end for */
688 } /* end if */
689 spin_unlock_irqrestore (&np->rx_lock, flags);
690 np->timer.expires = jiffies + next_tick;
691 add_timer(&np->timer);
692 }
693
694 static void
rio_tx_timeout(struct net_device * dev,unsigned int txqueue)695 rio_tx_timeout (struct net_device *dev, unsigned int txqueue)
696 {
697 struct netdev_private *np = netdev_priv(dev);
698 void __iomem *ioaddr = np->ioaddr;
699
700 printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
701 dev->name, dr32(TxStatus));
702 rio_free_tx(dev, 0);
703 dev->if_port = 0;
704 netif_trans_update(dev); /* prevent tx timeout */
705 }
706
707 static netdev_tx_t
start_xmit(struct sk_buff * skb,struct net_device * dev)708 start_xmit (struct sk_buff *skb, struct net_device *dev)
709 {
710 struct netdev_private *np = netdev_priv(dev);
711 void __iomem *ioaddr = np->ioaddr;
712 struct netdev_desc *txdesc;
713 unsigned entry;
714 u64 tfc_vlan_tag = 0;
715
716 if (np->link_status == 0) { /* Link Down */
717 dev_kfree_skb(skb);
718 return NETDEV_TX_OK;
719 }
720 entry = np->cur_tx % TX_RING_SIZE;
721 np->tx_skbuff[entry] = skb;
722 txdesc = &np->tx_ring[entry];
723
724 #if 0
725 if (skb->ip_summed == CHECKSUM_PARTIAL) {
726 txdesc->status |=
727 cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
728 IPChecksumEnable);
729 }
730 #endif
731 if (np->vlan) {
732 tfc_vlan_tag = VLANTagInsert |
733 ((u64)np->vlan << 32) |
734 ((u64)skb->priority << 45);
735 }
736 txdesc->fraginfo = cpu_to_le64 (dma_map_single(&np->pdev->dev, skb->data,
737 skb->len, DMA_TO_DEVICE));
738 txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48);
739
740 /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
741 * Work around: Always use 1 descriptor in 10Mbps mode */
742 if (entry % np->tx_coalesce == 0 || np->speed == 10)
743 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
744 WordAlignDisable |
745 TxDMAIndicate |
746 (1 << FragCountShift));
747 else
748 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
749 WordAlignDisable |
750 (1 << FragCountShift));
751
752 /* TxDMAPollNow */
753 dw32(DMACtrl, dr32(DMACtrl) | 0x00001000);
754 /* Schedule ISR */
755 dw32(CountDown, 10000);
756 np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
757 if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
758 < TX_QUEUE_LEN - 1 && np->speed != 10) {
759 /* do nothing */
760 } else if (!netif_queue_stopped(dev)) {
761 netif_stop_queue (dev);
762 }
763
764 /* The first TFDListPtr */
765 if (!dr32(TFDListPtr0)) {
766 dw32(TFDListPtr0, np->tx_ring_dma +
767 entry * sizeof (struct netdev_desc));
768 dw32(TFDListPtr1, 0);
769 }
770
771 return NETDEV_TX_OK;
772 }
773
774 static irqreturn_t
rio_interrupt(int irq,void * dev_instance)775 rio_interrupt (int irq, void *dev_instance)
776 {
777 struct net_device *dev = dev_instance;
778 struct netdev_private *np = netdev_priv(dev);
779 void __iomem *ioaddr = np->ioaddr;
780 unsigned int_status;
781 int cnt = max_intrloop;
782 int handled = 0;
783
784 while (1) {
785 int_status = dr16(IntStatus);
786 dw16(IntStatus, int_status);
787 int_status &= DEFAULT_INTR;
788 if (int_status == 0 || --cnt < 0)
789 break;
790 handled = 1;
791 /* Processing received packets */
792 if (int_status & RxDMAComplete)
793 receive_packet (dev);
794 /* TxDMAComplete interrupt */
795 if ((int_status & (TxDMAComplete|IntRequested))) {
796 int tx_status;
797 tx_status = dr32(TxStatus);
798 if (tx_status & 0x01)
799 tx_error (dev, tx_status);
800 /* Free used tx skbuffs */
801 rio_free_tx (dev, 1);
802 }
803
804 /* Handle uncommon events */
805 if (int_status &
806 (HostError | LinkEvent | UpdateStats))
807 rio_error (dev, int_status);
808 }
809 if (np->cur_tx != np->old_tx)
810 dw32(CountDown, 100);
811 return IRQ_RETVAL(handled);
812 }
813
814 static void
rio_free_tx(struct net_device * dev,int irq)815 rio_free_tx (struct net_device *dev, int irq)
816 {
817 struct netdev_private *np = netdev_priv(dev);
818 int entry = np->old_tx % TX_RING_SIZE;
819 unsigned long flag = 0;
820
821 if (irq)
822 spin_lock(&np->tx_lock);
823 else
824 spin_lock_irqsave(&np->tx_lock, flag);
825
826 /* Free used tx skbuffs */
827 while (entry != np->cur_tx) {
828 struct sk_buff *skb;
829
830 if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone)))
831 break;
832 skb = np->tx_skbuff[entry];
833 dma_unmap_single(&np->pdev->dev,
834 desc_to_dma(&np->tx_ring[entry]), skb->len,
835 DMA_TO_DEVICE);
836 if (irq)
837 dev_consume_skb_irq(skb);
838 else
839 dev_kfree_skb(skb);
840
841 np->tx_skbuff[entry] = NULL;
842 entry = (entry + 1) % TX_RING_SIZE;
843 }
844 if (irq)
845 spin_unlock(&np->tx_lock);
846 else
847 spin_unlock_irqrestore(&np->tx_lock, flag);
848 np->old_tx = entry;
849
850 /* If the ring is no longer full, clear tx_full and
851 call netif_wake_queue() */
852
853 if (netif_queue_stopped(dev) &&
854 ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
855 < TX_QUEUE_LEN - 1 || np->speed == 10)) {
856 netif_wake_queue (dev);
857 }
858 }
859
860 static void
tx_error(struct net_device * dev,int tx_status)861 tx_error (struct net_device *dev, int tx_status)
862 {
863 struct netdev_private *np = netdev_priv(dev);
864 void __iomem *ioaddr = np->ioaddr;
865 int frame_id;
866 int i;
867
868 frame_id = (tx_status & 0xffff0000);
869 printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
870 dev->name, tx_status, frame_id);
871 /* Ttransmit Underrun */
872 if (tx_status & 0x10) {
873 dev->stats.tx_fifo_errors++;
874 dw16(TxStartThresh, dr16(TxStartThresh) + 0x10);
875 /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
876 dw16(ASICCtrl + 2,
877 TxReset | DMAReset | FIFOReset | NetworkReset);
878 /* Wait for ResetBusy bit clear */
879 for (i = 50; i > 0; i--) {
880 if (!(dr16(ASICCtrl + 2) & ResetBusy))
881 break;
882 mdelay (1);
883 }
884 rio_set_led_mode(dev);
885 rio_free_tx (dev, 1);
886 /* Reset TFDListPtr */
887 dw32(TFDListPtr0, np->tx_ring_dma +
888 np->old_tx * sizeof (struct netdev_desc));
889 dw32(TFDListPtr1, 0);
890
891 /* Let TxStartThresh stay default value */
892 }
893 /* Late Collision */
894 if (tx_status & 0x04) {
895 dev->stats.tx_fifo_errors++;
896 /* TxReset and clear FIFO */
897 dw16(ASICCtrl + 2, TxReset | FIFOReset);
898 /* Wait reset done */
899 for (i = 50; i > 0; i--) {
900 if (!(dr16(ASICCtrl + 2) & ResetBusy))
901 break;
902 mdelay (1);
903 }
904 rio_set_led_mode(dev);
905 /* Let TxStartThresh stay default value */
906 }
907
908 spin_lock(&np->stats_lock);
909 /* Maximum Collisions */
910 if (tx_status & 0x08)
911 dev->stats.collisions++;
912
913 dev->stats.tx_errors++;
914 spin_unlock(&np->stats_lock);
915
916 /* Restart the Tx */
917 dw32(MACCtrl, dr16(MACCtrl) | TxEnable);
918 }
919
920 static int
receive_packet(struct net_device * dev)921 receive_packet (struct net_device *dev)
922 {
923 struct netdev_private *np = netdev_priv(dev);
924 int entry = np->cur_rx % RX_RING_SIZE;
925 int cnt = 30;
926
927 /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
928 while (1) {
929 struct netdev_desc *desc = &np->rx_ring[entry];
930 int pkt_len;
931 u64 frame_status;
932
933 if (!(desc->status & cpu_to_le64(RFDDone)) ||
934 !(desc->status & cpu_to_le64(FrameStart)) ||
935 !(desc->status & cpu_to_le64(FrameEnd)))
936 break;
937
938 /* Chip omits the CRC. */
939 frame_status = le64_to_cpu(desc->status);
940 pkt_len = frame_status & 0xffff;
941 if (--cnt < 0)
942 break;
943 /* Update rx error statistics, drop packet. */
944 if (frame_status & RFS_Errors) {
945 dev->stats.rx_errors++;
946 if (frame_status & (RxRuntFrame | RxLengthError))
947 dev->stats.rx_length_errors++;
948 if (frame_status & RxFCSError)
949 dev->stats.rx_crc_errors++;
950 if (frame_status & RxAlignmentError && np->speed != 1000)
951 dev->stats.rx_frame_errors++;
952 if (frame_status & RxFIFOOverrun)
953 dev->stats.rx_fifo_errors++;
954 } else {
955 struct sk_buff *skb;
956
957 /* Small skbuffs for short packets */
958 if (pkt_len > copy_thresh) {
959 dma_unmap_single(&np->pdev->dev,
960 desc_to_dma(desc),
961 np->rx_buf_sz,
962 DMA_FROM_DEVICE);
963 skb_put (skb = np->rx_skbuff[entry], pkt_len);
964 np->rx_skbuff[entry] = NULL;
965 } else if ((skb = netdev_alloc_skb_ip_align(dev, pkt_len))) {
966 dma_sync_single_for_cpu(&np->pdev->dev,
967 desc_to_dma(desc),
968 np->rx_buf_sz,
969 DMA_FROM_DEVICE);
970 skb_copy_to_linear_data (skb,
971 np->rx_skbuff[entry]->data,
972 pkt_len);
973 skb_put (skb, pkt_len);
974 dma_sync_single_for_device(&np->pdev->dev,
975 desc_to_dma(desc),
976 np->rx_buf_sz,
977 DMA_FROM_DEVICE);
978 }
979 skb->protocol = eth_type_trans (skb, dev);
980 #if 0
981 /* Checksum done by hw, but csum value unavailable. */
982 if (np->pdev->pci_rev_id >= 0x0c &&
983 !(frame_status & (TCPError | UDPError | IPError))) {
984 skb->ip_summed = CHECKSUM_UNNECESSARY;
985 }
986 #endif
987 netif_rx (skb);
988 }
989 entry = (entry + 1) % RX_RING_SIZE;
990 }
991 spin_lock(&np->rx_lock);
992 np->cur_rx = entry;
993 /* Re-allocate skbuffs to fill the descriptor ring */
994 entry = np->old_rx;
995 while (entry != np->cur_rx) {
996 struct sk_buff *skb;
997 /* Dropped packets don't need to re-allocate */
998 if (np->rx_skbuff[entry] == NULL) {
999 skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
1000 if (skb == NULL) {
1001 np->rx_ring[entry].fraginfo = 0;
1002 printk (KERN_INFO
1003 "%s: receive_packet: "
1004 "Unable to re-allocate Rx skbuff.#%d\n",
1005 dev->name, entry);
1006 break;
1007 }
1008 np->rx_skbuff[entry] = skb;
1009 np->rx_ring[entry].fraginfo =
1010 cpu_to_le64(dma_map_single(&np->pdev->dev, skb->data,
1011 np->rx_buf_sz, DMA_FROM_DEVICE));
1012 }
1013 np->rx_ring[entry].fraginfo |=
1014 cpu_to_le64((u64)np->rx_buf_sz << 48);
1015 np->rx_ring[entry].status = 0;
1016 entry = (entry + 1) % RX_RING_SIZE;
1017 }
1018 np->old_rx = entry;
1019 spin_unlock(&np->rx_lock);
1020 return 0;
1021 }
1022
1023 static void
rio_error(struct net_device * dev,int int_status)1024 rio_error (struct net_device *dev, int int_status)
1025 {
1026 struct netdev_private *np = netdev_priv(dev);
1027 void __iomem *ioaddr = np->ioaddr;
1028 u16 macctrl;
1029
1030 /* Link change event */
1031 if (int_status & LinkEvent) {
1032 if (mii_wait_link (dev, 10) == 0) {
1033 printk (KERN_INFO "%s: Link up\n", dev->name);
1034 if (np->phy_media)
1035 mii_get_media_pcs (dev);
1036 else
1037 mii_get_media (dev);
1038 if (np->speed == 1000)
1039 np->tx_coalesce = tx_coalesce;
1040 else
1041 np->tx_coalesce = 1;
1042 macctrl = 0;
1043 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
1044 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
1045 macctrl |= (np->tx_flow) ?
1046 TxFlowControlEnable : 0;
1047 macctrl |= (np->rx_flow) ?
1048 RxFlowControlEnable : 0;
1049 dw16(MACCtrl, macctrl);
1050 np->link_status = 1;
1051 netif_carrier_on(dev);
1052 } else {
1053 printk (KERN_INFO "%s: Link off\n", dev->name);
1054 np->link_status = 0;
1055 netif_carrier_off(dev);
1056 }
1057 }
1058
1059 /* UpdateStats statistics registers */
1060 if (int_status & UpdateStats) {
1061 get_stats (dev);
1062 }
1063
1064 /* PCI Error, a catastronphic error related to the bus interface
1065 occurs, set GlobalReset and HostReset to reset. */
1066 if (int_status & HostError) {
1067 printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
1068 dev->name, int_status);
1069 dw16(ASICCtrl + 2, GlobalReset | HostReset);
1070 mdelay (500);
1071 rio_set_led_mode(dev);
1072 }
1073 }
1074
1075 static struct net_device_stats *
get_stats(struct net_device * dev)1076 get_stats (struct net_device *dev)
1077 {
1078 struct netdev_private *np = netdev_priv(dev);
1079 void __iomem *ioaddr = np->ioaddr;
1080 #ifdef MEM_MAPPING
1081 int i;
1082 #endif
1083 unsigned int stat_reg;
1084 unsigned long flags;
1085
1086 spin_lock_irqsave(&np->stats_lock, flags);
1087 /* All statistics registers need to be acknowledged,
1088 else statistic overflow could cause problems */
1089
1090 dev->stats.rx_packets += dr32(FramesRcvOk);
1091 dev->stats.tx_packets += dr32(FramesXmtOk);
1092 dev->stats.rx_bytes += dr32(OctetRcvOk);
1093 dev->stats.tx_bytes += dr32(OctetXmtOk);
1094
1095 dev->stats.multicast = dr32(McstFramesRcvdOk);
1096 dev->stats.collisions += dr32(SingleColFrames)
1097 + dr32(MultiColFrames);
1098
1099 /* detailed tx errors */
1100 stat_reg = dr16(FramesAbortXSColls);
1101 dev->stats.tx_aborted_errors += stat_reg;
1102 dev->stats.tx_errors += stat_reg;
1103
1104 stat_reg = dr16(CarrierSenseErrors);
1105 dev->stats.tx_carrier_errors += stat_reg;
1106 dev->stats.tx_errors += stat_reg;
1107
1108 /* Clear all other statistic register. */
1109 dr32(McstOctetXmtOk);
1110 dr16(BcstFramesXmtdOk);
1111 dr32(McstFramesXmtdOk);
1112 dr16(BcstFramesRcvdOk);
1113 dr16(MacControlFramesRcvd);
1114 dr16(FrameTooLongErrors);
1115 dr16(InRangeLengthErrors);
1116 dr16(FramesCheckSeqErrors);
1117 dr16(FramesLostRxErrors);
1118 dr32(McstOctetXmtOk);
1119 dr32(BcstOctetXmtOk);
1120 dr32(McstFramesXmtdOk);
1121 dr32(FramesWDeferredXmt);
1122 dr32(LateCollisions);
1123 dr16(BcstFramesXmtdOk);
1124 dr16(MacControlFramesXmtd);
1125 dr16(FramesWEXDeferal);
1126
1127 #ifdef MEM_MAPPING
1128 for (i = 0x100; i <= 0x150; i += 4)
1129 dr32(i);
1130 #endif
1131 dr16(TxJumboFrames);
1132 dr16(RxJumboFrames);
1133 dr16(TCPCheckSumErrors);
1134 dr16(UDPCheckSumErrors);
1135 dr16(IPCheckSumErrors);
1136
1137 spin_unlock_irqrestore(&np->stats_lock, flags);
1138
1139 return &dev->stats;
1140 }
1141
1142 static int
clear_stats(struct net_device * dev)1143 clear_stats (struct net_device *dev)
1144 {
1145 struct netdev_private *np = netdev_priv(dev);
1146 void __iomem *ioaddr = np->ioaddr;
1147 #ifdef MEM_MAPPING
1148 int i;
1149 #endif
1150
1151 /* All statistics registers need to be acknowledged,
1152 else statistic overflow could cause problems */
1153 dr32(FramesRcvOk);
1154 dr32(FramesXmtOk);
1155 dr32(OctetRcvOk);
1156 dr32(OctetXmtOk);
1157
1158 dr32(McstFramesRcvdOk);
1159 dr32(SingleColFrames);
1160 dr32(MultiColFrames);
1161 dr32(LateCollisions);
1162 /* detailed rx errors */
1163 dr16(FrameTooLongErrors);
1164 dr16(InRangeLengthErrors);
1165 dr16(FramesCheckSeqErrors);
1166 dr16(FramesLostRxErrors);
1167
1168 /* detailed tx errors */
1169 dr16(FramesAbortXSColls);
1170 dr16(CarrierSenseErrors);
1171
1172 /* Clear all other statistic register. */
1173 dr32(McstOctetXmtOk);
1174 dr16(BcstFramesXmtdOk);
1175 dr32(McstFramesXmtdOk);
1176 dr16(BcstFramesRcvdOk);
1177 dr16(MacControlFramesRcvd);
1178 dr32(McstOctetXmtOk);
1179 dr32(BcstOctetXmtOk);
1180 dr32(McstFramesXmtdOk);
1181 dr32(FramesWDeferredXmt);
1182 dr16(BcstFramesXmtdOk);
1183 dr16(MacControlFramesXmtd);
1184 dr16(FramesWEXDeferal);
1185 #ifdef MEM_MAPPING
1186 for (i = 0x100; i <= 0x150; i += 4)
1187 dr32(i);
1188 #endif
1189 dr16(TxJumboFrames);
1190 dr16(RxJumboFrames);
1191 dr16(TCPCheckSumErrors);
1192 dr16(UDPCheckSumErrors);
1193 dr16(IPCheckSumErrors);
1194 return 0;
1195 }
1196
1197 static void
set_multicast(struct net_device * dev)1198 set_multicast (struct net_device *dev)
1199 {
1200 struct netdev_private *np = netdev_priv(dev);
1201 void __iomem *ioaddr = np->ioaddr;
1202 u32 hash_table[2];
1203 u16 rx_mode = 0;
1204
1205 hash_table[0] = hash_table[1] = 0;
1206 /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
1207 hash_table[1] |= 0x02000000;
1208 if (dev->flags & IFF_PROMISC) {
1209 /* Receive all frames promiscuously. */
1210 rx_mode = ReceiveAllFrames;
1211 } else if ((dev->flags & IFF_ALLMULTI) ||
1212 (netdev_mc_count(dev) > multicast_filter_limit)) {
1213 /* Receive broadcast and multicast frames */
1214 rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
1215 } else if (!netdev_mc_empty(dev)) {
1216 struct netdev_hw_addr *ha;
1217 /* Receive broadcast frames and multicast frames filtering
1218 by Hashtable */
1219 rx_mode =
1220 ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
1221 netdev_for_each_mc_addr(ha, dev) {
1222 int bit, index = 0;
1223 int crc = ether_crc_le(ETH_ALEN, ha->addr);
1224 /* The inverted high significant 6 bits of CRC are
1225 used as an index to hashtable */
1226 for (bit = 0; bit < 6; bit++)
1227 if (crc & (1 << (31 - bit)))
1228 index |= (1 << bit);
1229 hash_table[index / 32] |= (1 << (index % 32));
1230 }
1231 } else {
1232 rx_mode = ReceiveBroadcast | ReceiveUnicast;
1233 }
1234 if (np->vlan) {
1235 /* ReceiveVLANMatch field in ReceiveMode */
1236 rx_mode |= ReceiveVLANMatch;
1237 }
1238
1239 dw32(HashTable0, hash_table[0]);
1240 dw32(HashTable1, hash_table[1]);
1241 dw16(ReceiveMode, rx_mode);
1242 }
1243
rio_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1244 static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1245 {
1246 struct netdev_private *np = netdev_priv(dev);
1247
1248 strscpy(info->driver, "dl2k", sizeof(info->driver));
1249 strscpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
1250 }
1251
rio_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * cmd)1252 static int rio_get_link_ksettings(struct net_device *dev,
1253 struct ethtool_link_ksettings *cmd)
1254 {
1255 struct netdev_private *np = netdev_priv(dev);
1256 u32 supported, advertising;
1257
1258 if (np->phy_media) {
1259 /* fiber device */
1260 supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1261 advertising = ADVERTISED_Autoneg | ADVERTISED_FIBRE;
1262 cmd->base.port = PORT_FIBRE;
1263 } else {
1264 /* copper device */
1265 supported = SUPPORTED_10baseT_Half |
1266 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
1267 | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
1268 SUPPORTED_Autoneg | SUPPORTED_MII;
1269 advertising = ADVERTISED_10baseT_Half |
1270 ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
1271 ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full |
1272 ADVERTISED_Autoneg | ADVERTISED_MII;
1273 cmd->base.port = PORT_MII;
1274 }
1275 if (np->link_status) {
1276 cmd->base.speed = np->speed;
1277 cmd->base.duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1278 } else {
1279 cmd->base.speed = SPEED_UNKNOWN;
1280 cmd->base.duplex = DUPLEX_UNKNOWN;
1281 }
1282 if (np->an_enable)
1283 cmd->base.autoneg = AUTONEG_ENABLE;
1284 else
1285 cmd->base.autoneg = AUTONEG_DISABLE;
1286
1287 cmd->base.phy_address = np->phy_addr;
1288
1289 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1290 supported);
1291 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1292 advertising);
1293
1294 return 0;
1295 }
1296
rio_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)1297 static int rio_set_link_ksettings(struct net_device *dev,
1298 const struct ethtool_link_ksettings *cmd)
1299 {
1300 struct netdev_private *np = netdev_priv(dev);
1301 u32 speed = cmd->base.speed;
1302 u8 duplex = cmd->base.duplex;
1303
1304 netif_carrier_off(dev);
1305 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1306 if (np->an_enable) {
1307 return 0;
1308 } else {
1309 np->an_enable = 1;
1310 mii_set_media(dev);
1311 return 0;
1312 }
1313 } else {
1314 np->an_enable = 0;
1315 if (np->speed == 1000) {
1316 speed = SPEED_100;
1317 duplex = DUPLEX_FULL;
1318 printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
1319 }
1320 switch (speed) {
1321 case SPEED_10:
1322 np->speed = 10;
1323 np->full_duplex = (duplex == DUPLEX_FULL);
1324 break;
1325 case SPEED_100:
1326 np->speed = 100;
1327 np->full_duplex = (duplex == DUPLEX_FULL);
1328 break;
1329 case SPEED_1000: /* not supported */
1330 default:
1331 return -EINVAL;
1332 }
1333 mii_set_media(dev);
1334 }
1335 return 0;
1336 }
1337
rio_get_link(struct net_device * dev)1338 static u32 rio_get_link(struct net_device *dev)
1339 {
1340 struct netdev_private *np = netdev_priv(dev);
1341 return np->link_status;
1342 }
1343
1344 static const struct ethtool_ops ethtool_ops = {
1345 .get_drvinfo = rio_get_drvinfo,
1346 .get_link = rio_get_link,
1347 .get_link_ksettings = rio_get_link_ksettings,
1348 .set_link_ksettings = rio_set_link_ksettings,
1349 };
1350
1351 static int
rio_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)1352 rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1353 {
1354 int phy_addr;
1355 struct netdev_private *np = netdev_priv(dev);
1356 struct mii_ioctl_data *miidata = if_mii(rq);
1357
1358 phy_addr = np->phy_addr;
1359 switch (cmd) {
1360 case SIOCGMIIPHY:
1361 miidata->phy_id = phy_addr;
1362 break;
1363 case SIOCGMIIREG:
1364 miidata->val_out = mii_read (dev, phy_addr, miidata->reg_num);
1365 break;
1366 case SIOCSMIIREG:
1367 if (!capable(CAP_NET_ADMIN))
1368 return -EPERM;
1369 mii_write (dev, phy_addr, miidata->reg_num, miidata->val_in);
1370 break;
1371 default:
1372 return -EOPNOTSUPP;
1373 }
1374 return 0;
1375 }
1376
1377 #define EEP_READ 0x0200
1378 #define EEP_BUSY 0x8000
1379 /* Read the EEPROM word */
1380 /* We use I/O instruction to read/write eeprom to avoid fail on some machines */
read_eeprom(struct netdev_private * np,int eep_addr)1381 static int read_eeprom(struct netdev_private *np, int eep_addr)
1382 {
1383 void __iomem *ioaddr = np->eeprom_addr;
1384 int i = 1000;
1385
1386 dw16(EepromCtrl, EEP_READ | (eep_addr & 0xff));
1387 while (i-- > 0) {
1388 if (!(dr16(EepromCtrl) & EEP_BUSY))
1389 return dr16(EepromData);
1390 }
1391 return 0;
1392 }
1393
1394 enum phy_ctrl_bits {
1395 MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
1396 MII_DUPLEX = 0x08,
1397 };
1398
1399 #define mii_delay() dr8(PhyCtrl)
1400 static void
mii_sendbit(struct net_device * dev,u32 data)1401 mii_sendbit (struct net_device *dev, u32 data)
1402 {
1403 struct netdev_private *np = netdev_priv(dev);
1404 void __iomem *ioaddr = np->ioaddr;
1405
1406 data = ((data) ? MII_DATA1 : 0) | (dr8(PhyCtrl) & 0xf8) | MII_WRITE;
1407 dw8(PhyCtrl, data);
1408 mii_delay ();
1409 dw8(PhyCtrl, data | MII_CLK);
1410 mii_delay ();
1411 }
1412
1413 static int
mii_getbit(struct net_device * dev)1414 mii_getbit (struct net_device *dev)
1415 {
1416 struct netdev_private *np = netdev_priv(dev);
1417 void __iomem *ioaddr = np->ioaddr;
1418 u8 data;
1419
1420 data = (dr8(PhyCtrl) & 0xf8) | MII_READ;
1421 dw8(PhyCtrl, data);
1422 mii_delay ();
1423 dw8(PhyCtrl, data | MII_CLK);
1424 mii_delay ();
1425 return (dr8(PhyCtrl) >> 1) & 1;
1426 }
1427
1428 static void
mii_send_bits(struct net_device * dev,u32 data,int len)1429 mii_send_bits (struct net_device *dev, u32 data, int len)
1430 {
1431 int i;
1432
1433 for (i = len - 1; i >= 0; i--) {
1434 mii_sendbit (dev, data & (1 << i));
1435 }
1436 }
1437
1438 static int
mii_read(struct net_device * dev,int phy_addr,int reg_num)1439 mii_read (struct net_device *dev, int phy_addr, int reg_num)
1440 {
1441 u32 cmd;
1442 int i;
1443 u32 retval = 0;
1444
1445 /* Preamble */
1446 mii_send_bits (dev, 0xffffffff, 32);
1447 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1448 /* ST,OP = 0110'b for read operation */
1449 cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
1450 mii_send_bits (dev, cmd, 14);
1451 /* Turnaround */
1452 if (mii_getbit (dev))
1453 goto err_out;
1454 /* Read data */
1455 for (i = 0; i < 16; i++) {
1456 retval |= mii_getbit (dev);
1457 retval <<= 1;
1458 }
1459 /* End cycle */
1460 mii_getbit (dev);
1461 return (retval >> 1) & 0xffff;
1462
1463 err_out:
1464 return 0;
1465 }
1466 static int
mii_write(struct net_device * dev,int phy_addr,int reg_num,u16 data)1467 mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
1468 {
1469 u32 cmd;
1470
1471 /* Preamble */
1472 mii_send_bits (dev, 0xffffffff, 32);
1473 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1474 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1475 cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
1476 mii_send_bits (dev, cmd, 32);
1477 /* End cycle */
1478 mii_getbit (dev);
1479 return 0;
1480 }
1481 static int
mii_wait_link(struct net_device * dev,int wait)1482 mii_wait_link (struct net_device *dev, int wait)
1483 {
1484 __u16 bmsr;
1485 int phy_addr;
1486 struct netdev_private *np;
1487
1488 np = netdev_priv(dev);
1489 phy_addr = np->phy_addr;
1490
1491 do {
1492 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1493 if (bmsr & BMSR_LSTATUS)
1494 return 0;
1495 mdelay (1);
1496 } while (--wait > 0);
1497 return -1;
1498 }
1499 static int
mii_get_media(struct net_device * dev)1500 mii_get_media (struct net_device *dev)
1501 {
1502 __u16 negotiate;
1503 __u16 bmsr;
1504 __u16 mscr;
1505 __u16 mssr;
1506 int phy_addr;
1507 struct netdev_private *np;
1508
1509 np = netdev_priv(dev);
1510 phy_addr = np->phy_addr;
1511
1512 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1513 if (np->an_enable) {
1514 if (!(bmsr & BMSR_ANEGCOMPLETE)) {
1515 /* Auto-Negotiation not completed */
1516 return -1;
1517 }
1518 negotiate = mii_read (dev, phy_addr, MII_ADVERTISE) &
1519 mii_read (dev, phy_addr, MII_LPA);
1520 mscr = mii_read (dev, phy_addr, MII_CTRL1000);
1521 mssr = mii_read (dev, phy_addr, MII_STAT1000);
1522 if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) {
1523 np->speed = 1000;
1524 np->full_duplex = 1;
1525 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1526 } else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) {
1527 np->speed = 1000;
1528 np->full_duplex = 0;
1529 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
1530 } else if (negotiate & ADVERTISE_100FULL) {
1531 np->speed = 100;
1532 np->full_duplex = 1;
1533 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
1534 } else if (negotiate & ADVERTISE_100HALF) {
1535 np->speed = 100;
1536 np->full_duplex = 0;
1537 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
1538 } else if (negotiate & ADVERTISE_10FULL) {
1539 np->speed = 10;
1540 np->full_duplex = 1;
1541 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
1542 } else if (negotiate & ADVERTISE_10HALF) {
1543 np->speed = 10;
1544 np->full_duplex = 0;
1545 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
1546 }
1547 if (negotiate & ADVERTISE_PAUSE_CAP) {
1548 np->tx_flow &= 1;
1549 np->rx_flow &= 1;
1550 } else if (negotiate & ADVERTISE_PAUSE_ASYM) {
1551 np->tx_flow = 0;
1552 np->rx_flow &= 1;
1553 }
1554 /* else tx_flow, rx_flow = user select */
1555 } else {
1556 __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1557 switch (bmcr & (BMCR_SPEED100 | BMCR_SPEED1000)) {
1558 case BMCR_SPEED1000:
1559 printk (KERN_INFO "Operating at 1000 Mbps, ");
1560 break;
1561 case BMCR_SPEED100:
1562 printk (KERN_INFO "Operating at 100 Mbps, ");
1563 break;
1564 case 0:
1565 printk (KERN_INFO "Operating at 10 Mbps, ");
1566 }
1567 if (bmcr & BMCR_FULLDPLX) {
1568 printk (KERN_CONT "Full duplex\n");
1569 } else {
1570 printk (KERN_CONT "Half duplex\n");
1571 }
1572 }
1573 if (np->tx_flow)
1574 printk(KERN_INFO "Enable Tx Flow Control\n");
1575 else
1576 printk(KERN_INFO "Disable Tx Flow Control\n");
1577 if (np->rx_flow)
1578 printk(KERN_INFO "Enable Rx Flow Control\n");
1579 else
1580 printk(KERN_INFO "Disable Rx Flow Control\n");
1581
1582 return 0;
1583 }
1584
1585 static int
mii_set_media(struct net_device * dev)1586 mii_set_media (struct net_device *dev)
1587 {
1588 __u16 pscr;
1589 __u16 bmcr;
1590 __u16 bmsr;
1591 __u16 anar;
1592 int phy_addr;
1593 struct netdev_private *np;
1594 np = netdev_priv(dev);
1595 phy_addr = np->phy_addr;
1596
1597 /* Does user set speed? */
1598 if (np->an_enable) {
1599 /* Advertise capabilities */
1600 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1601 anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
1602 ~(ADVERTISE_100FULL | ADVERTISE_10FULL |
1603 ADVERTISE_100HALF | ADVERTISE_10HALF |
1604 ADVERTISE_100BASE4);
1605 if (bmsr & BMSR_100FULL)
1606 anar |= ADVERTISE_100FULL;
1607 if (bmsr & BMSR_100HALF)
1608 anar |= ADVERTISE_100HALF;
1609 if (bmsr & BMSR_100BASE4)
1610 anar |= ADVERTISE_100BASE4;
1611 if (bmsr & BMSR_10FULL)
1612 anar |= ADVERTISE_10FULL;
1613 if (bmsr & BMSR_10HALF)
1614 anar |= ADVERTISE_10HALF;
1615 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1616 mii_write (dev, phy_addr, MII_ADVERTISE, anar);
1617
1618 /* Enable Auto crossover */
1619 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1620 pscr |= 3 << 5; /* 11'b */
1621 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1622
1623 /* Soft reset PHY */
1624 mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
1625 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
1626 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1627 mdelay(1);
1628 } else {
1629 /* Force speed setting */
1630 /* 1) Disable Auto crossover */
1631 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1632 pscr &= ~(3 << 5);
1633 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1634
1635 /* 2) PHY Reset */
1636 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1637 bmcr |= BMCR_RESET;
1638 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1639
1640 /* 3) Power Down */
1641 bmcr = 0x1940; /* must be 0x1940 */
1642 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1643 mdelay (100); /* wait a certain time */
1644
1645 /* 4) Advertise nothing */
1646 mii_write (dev, phy_addr, MII_ADVERTISE, 0);
1647
1648 /* 5) Set media and Power Up */
1649 bmcr = BMCR_PDOWN;
1650 if (np->speed == 100) {
1651 bmcr |= BMCR_SPEED100;
1652 printk (KERN_INFO "Manual 100 Mbps, ");
1653 } else if (np->speed == 10) {
1654 printk (KERN_INFO "Manual 10 Mbps, ");
1655 }
1656 if (np->full_duplex) {
1657 bmcr |= BMCR_FULLDPLX;
1658 printk (KERN_CONT "Full duplex\n");
1659 } else {
1660 printk (KERN_CONT "Half duplex\n");
1661 }
1662 #if 0
1663 /* Set 1000BaseT Master/Slave setting */
1664 mscr = mii_read (dev, phy_addr, MII_CTRL1000);
1665 mscr |= MII_MSCR_CFG_ENABLE;
1666 mscr &= ~MII_MSCR_CFG_VALUE = 0;
1667 #endif
1668 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1669 mdelay(10);
1670 }
1671 return 0;
1672 }
1673
1674 static int
mii_get_media_pcs(struct net_device * dev)1675 mii_get_media_pcs (struct net_device *dev)
1676 {
1677 __u16 negotiate;
1678 __u16 bmsr;
1679 int phy_addr;
1680 struct netdev_private *np;
1681
1682 np = netdev_priv(dev);
1683 phy_addr = np->phy_addr;
1684
1685 bmsr = mii_read (dev, phy_addr, PCS_BMSR);
1686 if (np->an_enable) {
1687 if (!(bmsr & BMSR_ANEGCOMPLETE)) {
1688 /* Auto-Negotiation not completed */
1689 return -1;
1690 }
1691 negotiate = mii_read (dev, phy_addr, PCS_ANAR) &
1692 mii_read (dev, phy_addr, PCS_ANLPAR);
1693 np->speed = 1000;
1694 if (negotiate & PCS_ANAR_FULL_DUPLEX) {
1695 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1696 np->full_duplex = 1;
1697 } else {
1698 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
1699 np->full_duplex = 0;
1700 }
1701 if (negotiate & PCS_ANAR_PAUSE) {
1702 np->tx_flow &= 1;
1703 np->rx_flow &= 1;
1704 } else if (negotiate & PCS_ANAR_ASYMMETRIC) {
1705 np->tx_flow = 0;
1706 np->rx_flow &= 1;
1707 }
1708 /* else tx_flow, rx_flow = user select */
1709 } else {
1710 __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR);
1711 printk (KERN_INFO "Operating at 1000 Mbps, ");
1712 if (bmcr & BMCR_FULLDPLX) {
1713 printk (KERN_CONT "Full duplex\n");
1714 } else {
1715 printk (KERN_CONT "Half duplex\n");
1716 }
1717 }
1718 if (np->tx_flow)
1719 printk(KERN_INFO "Enable Tx Flow Control\n");
1720 else
1721 printk(KERN_INFO "Disable Tx Flow Control\n");
1722 if (np->rx_flow)
1723 printk(KERN_INFO "Enable Rx Flow Control\n");
1724 else
1725 printk(KERN_INFO "Disable Rx Flow Control\n");
1726
1727 return 0;
1728 }
1729
1730 static int
mii_set_media_pcs(struct net_device * dev)1731 mii_set_media_pcs (struct net_device *dev)
1732 {
1733 __u16 bmcr;
1734 __u16 esr;
1735 __u16 anar;
1736 int phy_addr;
1737 struct netdev_private *np;
1738 np = netdev_priv(dev);
1739 phy_addr = np->phy_addr;
1740
1741 /* Auto-Negotiation? */
1742 if (np->an_enable) {
1743 /* Advertise capabilities */
1744 esr = mii_read (dev, phy_addr, PCS_ESR);
1745 anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
1746 ~PCS_ANAR_HALF_DUPLEX &
1747 ~PCS_ANAR_FULL_DUPLEX;
1748 if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD))
1749 anar |= PCS_ANAR_HALF_DUPLEX;
1750 if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD))
1751 anar |= PCS_ANAR_FULL_DUPLEX;
1752 anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
1753 mii_write (dev, phy_addr, MII_ADVERTISE, anar);
1754
1755 /* Soft reset PHY */
1756 mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
1757 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
1758 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1759 mdelay(1);
1760 } else {
1761 /* Force speed setting */
1762 /* PHY Reset */
1763 bmcr = BMCR_RESET;
1764 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1765 mdelay(10);
1766 if (np->full_duplex) {
1767 bmcr = BMCR_FULLDPLX;
1768 printk (KERN_INFO "Manual full duplex\n");
1769 } else {
1770 bmcr = 0;
1771 printk (KERN_INFO "Manual half duplex\n");
1772 }
1773 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1774 mdelay(10);
1775
1776 /* Advertise nothing */
1777 mii_write (dev, phy_addr, MII_ADVERTISE, 0);
1778 }
1779 return 0;
1780 }
1781
1782
1783 static int
rio_close(struct net_device * dev)1784 rio_close (struct net_device *dev)
1785 {
1786 struct netdev_private *np = netdev_priv(dev);
1787 struct pci_dev *pdev = np->pdev;
1788
1789 netif_stop_queue (dev);
1790
1791 rio_hw_stop(dev);
1792
1793 free_irq(pdev->irq, dev);
1794 del_timer_sync (&np->timer);
1795
1796 free_list(dev);
1797
1798 return 0;
1799 }
1800
1801 static void
rio_remove1(struct pci_dev * pdev)1802 rio_remove1 (struct pci_dev *pdev)
1803 {
1804 struct net_device *dev = pci_get_drvdata (pdev);
1805
1806 if (dev) {
1807 struct netdev_private *np = netdev_priv(dev);
1808
1809 unregister_netdev (dev);
1810 dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, np->rx_ring,
1811 np->rx_ring_dma);
1812 dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, np->tx_ring,
1813 np->tx_ring_dma);
1814 #ifdef MEM_MAPPING
1815 pci_iounmap(pdev, np->ioaddr);
1816 #endif
1817 pci_iounmap(pdev, np->eeprom_addr);
1818 free_netdev (dev);
1819 pci_release_regions (pdev);
1820 pci_disable_device (pdev);
1821 }
1822 }
1823
1824 #ifdef CONFIG_PM_SLEEP
rio_suspend(struct device * device)1825 static int rio_suspend(struct device *device)
1826 {
1827 struct net_device *dev = dev_get_drvdata(device);
1828 struct netdev_private *np = netdev_priv(dev);
1829
1830 if (!netif_running(dev))
1831 return 0;
1832
1833 netif_device_detach(dev);
1834 del_timer_sync(&np->timer);
1835 rio_hw_stop(dev);
1836
1837 return 0;
1838 }
1839
rio_resume(struct device * device)1840 static int rio_resume(struct device *device)
1841 {
1842 struct net_device *dev = dev_get_drvdata(device);
1843 struct netdev_private *np = netdev_priv(dev);
1844
1845 if (!netif_running(dev))
1846 return 0;
1847
1848 rio_reset_ring(np);
1849 rio_hw_init(dev);
1850 np->timer.expires = jiffies + 1 * HZ;
1851 add_timer(&np->timer);
1852 netif_device_attach(dev);
1853 dl2k_enable_int(np);
1854
1855 return 0;
1856 }
1857
1858 static SIMPLE_DEV_PM_OPS(rio_pm_ops, rio_suspend, rio_resume);
1859 #define RIO_PM_OPS (&rio_pm_ops)
1860
1861 #else
1862
1863 #define RIO_PM_OPS NULL
1864
1865 #endif /* CONFIG_PM_SLEEP */
1866
1867 static struct pci_driver rio_driver = {
1868 .name = "dl2k",
1869 .id_table = rio_pci_tbl,
1870 .probe = rio_probe1,
1871 .remove = rio_remove1,
1872 .driver.pm = RIO_PM_OPS,
1873 };
1874
1875 module_pci_driver(rio_driver);
1876
1877 /* Read Documentation/networking/device_drivers/ethernet/dlink/dl2k.rst. */
1878