xref: /openbmc/linux/drivers/net/ethernet/freescale/enetc/enetc.c (revision 8ebc80a25f9d9bf7a8e368b266d5b740c485c362)
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* Copyright 2017-2019 NXP */
3 
4 #include "enetc.h"
5 #include <linux/bpf_trace.h>
6 #include <linux/tcp.h>
7 #include <linux/udp.h>
8 #include <linux/vmalloc.h>
9 #include <linux/ptp_classify.h>
10 #include <net/ip6_checksum.h>
11 #include <net/pkt_sched.h>
12 #include <net/tso.h>
13 
enetc_port_mac_rd(struct enetc_si * si,u32 reg)14 u32 enetc_port_mac_rd(struct enetc_si *si, u32 reg)
15 {
16 	return enetc_port_rd(&si->hw, reg);
17 }
18 EXPORT_SYMBOL_GPL(enetc_port_mac_rd);
19 
enetc_port_mac_wr(struct enetc_si * si,u32 reg,u32 val)20 void enetc_port_mac_wr(struct enetc_si *si, u32 reg, u32 val)
21 {
22 	enetc_port_wr(&si->hw, reg, val);
23 	if (si->hw_features & ENETC_SI_F_QBU)
24 		enetc_port_wr(&si->hw, reg + ENETC_PMAC_OFFSET, val);
25 }
26 EXPORT_SYMBOL_GPL(enetc_port_mac_wr);
27 
enetc_change_preemptible_tcs(struct enetc_ndev_priv * priv,u8 preemptible_tcs)28 static void enetc_change_preemptible_tcs(struct enetc_ndev_priv *priv,
29 					 u8 preemptible_tcs)
30 {
31 	if (!(priv->si->hw_features & ENETC_SI_F_QBU))
32 		return;
33 
34 	priv->preemptible_tcs = preemptible_tcs;
35 	enetc_mm_commit_preemptible_tcs(priv);
36 }
37 
enetc_num_stack_tx_queues(struct enetc_ndev_priv * priv)38 static int enetc_num_stack_tx_queues(struct enetc_ndev_priv *priv)
39 {
40 	int num_tx_rings = priv->num_tx_rings;
41 
42 	if (priv->xdp_prog)
43 		return num_tx_rings - num_possible_cpus();
44 
45 	return num_tx_rings;
46 }
47 
enetc_rx_ring_from_xdp_tx_ring(struct enetc_ndev_priv * priv,struct enetc_bdr * tx_ring)48 static struct enetc_bdr *enetc_rx_ring_from_xdp_tx_ring(struct enetc_ndev_priv *priv,
49 							struct enetc_bdr *tx_ring)
50 {
51 	int index = &priv->tx_ring[tx_ring->index] - priv->xdp_tx_ring;
52 
53 	return priv->rx_ring[index];
54 }
55 
enetc_tx_swbd_get_skb(struct enetc_tx_swbd * tx_swbd)56 static struct sk_buff *enetc_tx_swbd_get_skb(struct enetc_tx_swbd *tx_swbd)
57 {
58 	if (tx_swbd->is_xdp_tx || tx_swbd->is_xdp_redirect)
59 		return NULL;
60 
61 	return tx_swbd->skb;
62 }
63 
64 static struct xdp_frame *
enetc_tx_swbd_get_xdp_frame(struct enetc_tx_swbd * tx_swbd)65 enetc_tx_swbd_get_xdp_frame(struct enetc_tx_swbd *tx_swbd)
66 {
67 	if (tx_swbd->is_xdp_redirect)
68 		return tx_swbd->xdp_frame;
69 
70 	return NULL;
71 }
72 
enetc_unmap_tx_buff(struct enetc_bdr * tx_ring,struct enetc_tx_swbd * tx_swbd)73 static void enetc_unmap_tx_buff(struct enetc_bdr *tx_ring,
74 				struct enetc_tx_swbd *tx_swbd)
75 {
76 	/* For XDP_TX, pages come from RX, whereas for the other contexts where
77 	 * we have is_dma_page_set, those come from skb_frag_dma_map. We need
78 	 * to match the DMA mapping length, so we need to differentiate those.
79 	 */
80 	if (tx_swbd->is_dma_page)
81 		dma_unmap_page(tx_ring->dev, tx_swbd->dma,
82 			       tx_swbd->is_xdp_tx ? PAGE_SIZE : tx_swbd->len,
83 			       tx_swbd->dir);
84 	else
85 		dma_unmap_single(tx_ring->dev, tx_swbd->dma,
86 				 tx_swbd->len, tx_swbd->dir);
87 	tx_swbd->dma = 0;
88 }
89 
enetc_free_tx_frame(struct enetc_bdr * tx_ring,struct enetc_tx_swbd * tx_swbd)90 static void enetc_free_tx_frame(struct enetc_bdr *tx_ring,
91 				struct enetc_tx_swbd *tx_swbd)
92 {
93 	struct xdp_frame *xdp_frame = enetc_tx_swbd_get_xdp_frame(tx_swbd);
94 	struct sk_buff *skb = enetc_tx_swbd_get_skb(tx_swbd);
95 
96 	if (tx_swbd->dma)
97 		enetc_unmap_tx_buff(tx_ring, tx_swbd);
98 
99 	if (xdp_frame) {
100 		xdp_return_frame(tx_swbd->xdp_frame);
101 		tx_swbd->xdp_frame = NULL;
102 	} else if (skb) {
103 		dev_kfree_skb_any(skb);
104 		tx_swbd->skb = NULL;
105 	}
106 }
107 
108 /* Let H/W know BD ring has been updated */
enetc_update_tx_ring_tail(struct enetc_bdr * tx_ring)109 static void enetc_update_tx_ring_tail(struct enetc_bdr *tx_ring)
110 {
111 	/* includes wmb() */
112 	enetc_wr_reg_hot(tx_ring->tpir, tx_ring->next_to_use);
113 }
114 
enetc_ptp_parse(struct sk_buff * skb,u8 * udp,u8 * msgtype,u8 * twostep,u16 * correction_offset,u16 * body_offset)115 static int enetc_ptp_parse(struct sk_buff *skb, u8 *udp,
116 			   u8 *msgtype, u8 *twostep,
117 			   u16 *correction_offset, u16 *body_offset)
118 {
119 	unsigned int ptp_class;
120 	struct ptp_header *hdr;
121 	unsigned int type;
122 	u8 *base;
123 
124 	ptp_class = ptp_classify_raw(skb);
125 	if (ptp_class == PTP_CLASS_NONE)
126 		return -EINVAL;
127 
128 	hdr = ptp_parse_header(skb, ptp_class);
129 	if (!hdr)
130 		return -EINVAL;
131 
132 	type = ptp_class & PTP_CLASS_PMASK;
133 	if (type == PTP_CLASS_IPV4 || type == PTP_CLASS_IPV6)
134 		*udp = 1;
135 	else
136 		*udp = 0;
137 
138 	*msgtype = ptp_get_msgtype(hdr, ptp_class);
139 	*twostep = hdr->flag_field[0] & 0x2;
140 
141 	base = skb_mac_header(skb);
142 	*correction_offset = (u8 *)&hdr->correction - base;
143 	*body_offset = (u8 *)hdr + sizeof(struct ptp_header) - base;
144 
145 	return 0;
146 }
147 
148 /**
149  * enetc_unwind_tx_frame() - Unwind the DMA mappings of a multi-buffer Tx frame
150  * @tx_ring: Pointer to the Tx ring on which the buffer descriptors are located
151  * @count: Number of Tx buffer descriptors which need to be unmapped
152  * @i: Index of the last successfully mapped Tx buffer descriptor
153  */
enetc_unwind_tx_frame(struct enetc_bdr * tx_ring,int count,int i)154 static void enetc_unwind_tx_frame(struct enetc_bdr *tx_ring, int count, int i)
155 {
156 	while (count--) {
157 		struct enetc_tx_swbd *tx_swbd = &tx_ring->tx_swbd[i];
158 
159 		enetc_free_tx_frame(tx_ring, tx_swbd);
160 		if (i == 0)
161 			i = tx_ring->bd_count;
162 		i--;
163 	}
164 }
165 
enetc_map_tx_buffs(struct enetc_bdr * tx_ring,struct sk_buff * skb)166 static int enetc_map_tx_buffs(struct enetc_bdr *tx_ring, struct sk_buff *skb)
167 {
168 	bool do_vlan, do_onestep_tstamp = false, do_twostep_tstamp = false;
169 	struct enetc_ndev_priv *priv = netdev_priv(tx_ring->ndev);
170 	struct enetc_hw *hw = &priv->si->hw;
171 	struct enetc_tx_swbd *tx_swbd;
172 	int len = skb_headlen(skb);
173 	union enetc_tx_bd temp_bd;
174 	u8 msgtype, twostep, udp;
175 	union enetc_tx_bd *txbd;
176 	u16 offset1, offset2;
177 	int i, count = 0;
178 	skb_frag_t *frag;
179 	unsigned int f;
180 	dma_addr_t dma;
181 	u8 flags = 0;
182 
183 	i = tx_ring->next_to_use;
184 	txbd = ENETC_TXBD(*tx_ring, i);
185 	prefetchw(txbd);
186 
187 	dma = dma_map_single(tx_ring->dev, skb->data, len, DMA_TO_DEVICE);
188 	if (unlikely(dma_mapping_error(tx_ring->dev, dma)))
189 		goto dma_err;
190 
191 	temp_bd.addr = cpu_to_le64(dma);
192 	temp_bd.buf_len = cpu_to_le16(len);
193 	temp_bd.lstatus = 0;
194 
195 	tx_swbd = &tx_ring->tx_swbd[i];
196 	tx_swbd->dma = dma;
197 	tx_swbd->len = len;
198 	tx_swbd->is_dma_page = 0;
199 	tx_swbd->dir = DMA_TO_DEVICE;
200 	count++;
201 
202 	do_vlan = skb_vlan_tag_present(skb);
203 	if (skb->cb[0] & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) {
204 		if (enetc_ptp_parse(skb, &udp, &msgtype, &twostep, &offset1,
205 				    &offset2) ||
206 		    msgtype != PTP_MSGTYPE_SYNC || twostep)
207 			WARN_ONCE(1, "Bad packet for one-step timestamping\n");
208 		else
209 			do_onestep_tstamp = true;
210 	} else if (skb->cb[0] & ENETC_F_TX_TSTAMP) {
211 		do_twostep_tstamp = true;
212 	}
213 
214 	tx_swbd->do_twostep_tstamp = do_twostep_tstamp;
215 	tx_swbd->qbv_en = !!(priv->active_offloads & ENETC_F_QBV);
216 	tx_swbd->check_wb = tx_swbd->do_twostep_tstamp || tx_swbd->qbv_en;
217 
218 	if (do_vlan || do_onestep_tstamp || do_twostep_tstamp)
219 		flags |= ENETC_TXBD_FLAGS_EX;
220 
221 	if (tx_ring->tsd_enable)
222 		flags |= ENETC_TXBD_FLAGS_TSE | ENETC_TXBD_FLAGS_TXSTART;
223 
224 	/* first BD needs frm_len and offload flags set */
225 	temp_bd.frm_len = cpu_to_le16(skb->len);
226 	temp_bd.flags = flags;
227 
228 	if (flags & ENETC_TXBD_FLAGS_TSE)
229 		temp_bd.txstart = enetc_txbd_set_tx_start(skb->skb_mstamp_ns,
230 							  flags);
231 
232 	if (flags & ENETC_TXBD_FLAGS_EX) {
233 		u8 e_flags = 0;
234 		*txbd = temp_bd;
235 		enetc_clear_tx_bd(&temp_bd);
236 
237 		/* add extension BD for VLAN and/or timestamping */
238 		flags = 0;
239 		tx_swbd++;
240 		txbd++;
241 		i++;
242 		if (unlikely(i == tx_ring->bd_count)) {
243 			i = 0;
244 			tx_swbd = tx_ring->tx_swbd;
245 			txbd = ENETC_TXBD(*tx_ring, 0);
246 		}
247 		prefetchw(txbd);
248 
249 		if (do_vlan) {
250 			temp_bd.ext.vid = cpu_to_le16(skb_vlan_tag_get(skb));
251 			temp_bd.ext.tpid = 0; /* < C-TAG */
252 			e_flags |= ENETC_TXBD_E_FLAGS_VLAN_INS;
253 		}
254 
255 		if (do_onestep_tstamp) {
256 			__be32 new_sec_l, new_nsec;
257 			u32 lo, hi, nsec, val;
258 			__be16 new_sec_h;
259 			u8 *data;
260 			u64 sec;
261 
262 			lo = enetc_rd_hot(hw, ENETC_SICTR0);
263 			hi = enetc_rd_hot(hw, ENETC_SICTR1);
264 			sec = (u64)hi << 32 | lo;
265 			nsec = do_div(sec, 1000000000);
266 
267 			/* Configure extension BD */
268 			temp_bd.ext.tstamp = cpu_to_le32(lo & 0x3fffffff);
269 			e_flags |= ENETC_TXBD_E_FLAGS_ONE_STEP_PTP;
270 
271 			/* Update originTimestamp field of Sync packet
272 			 * - 48 bits seconds field
273 			 * - 32 bits nanseconds field
274 			 *
275 			 * In addition, the UDP checksum needs to be updated
276 			 * by software after updating originTimestamp field,
277 			 * otherwise the hardware will calculate the wrong
278 			 * checksum when updating the correction field and
279 			 * update it to the packet.
280 			 */
281 			data = skb_mac_header(skb);
282 			new_sec_h = htons((sec >> 32) & 0xffff);
283 			new_sec_l = htonl(sec & 0xffffffff);
284 			new_nsec = htonl(nsec);
285 			if (udp) {
286 				struct udphdr *uh = udp_hdr(skb);
287 				__be32 old_sec_l, old_nsec;
288 				__be16 old_sec_h;
289 
290 				old_sec_h = *(__be16 *)(data + offset2);
291 				inet_proto_csum_replace2(&uh->check, skb, old_sec_h,
292 							 new_sec_h, false);
293 
294 				old_sec_l = *(__be32 *)(data + offset2 + 2);
295 				inet_proto_csum_replace4(&uh->check, skb, old_sec_l,
296 							 new_sec_l, false);
297 
298 				old_nsec = *(__be32 *)(data + offset2 + 6);
299 				inet_proto_csum_replace4(&uh->check, skb, old_nsec,
300 							 new_nsec, false);
301 			}
302 
303 			*(__be16 *)(data + offset2) = new_sec_h;
304 			*(__be32 *)(data + offset2 + 2) = new_sec_l;
305 			*(__be32 *)(data + offset2 + 6) = new_nsec;
306 
307 			/* Configure single-step register */
308 			val = ENETC_PM0_SINGLE_STEP_EN;
309 			val |= ENETC_SET_SINGLE_STEP_OFFSET(offset1);
310 			if (udp)
311 				val |= ENETC_PM0_SINGLE_STEP_CH;
312 
313 			enetc_port_mac_wr(priv->si, ENETC_PM0_SINGLE_STEP,
314 					  val);
315 		} else if (do_twostep_tstamp) {
316 			skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
317 			e_flags |= ENETC_TXBD_E_FLAGS_TWO_STEP_PTP;
318 		}
319 
320 		temp_bd.ext.e_flags = e_flags;
321 		count++;
322 	}
323 
324 	frag = &skb_shinfo(skb)->frags[0];
325 	for (f = 0; f < skb_shinfo(skb)->nr_frags; f++, frag++) {
326 		len = skb_frag_size(frag);
327 		dma = skb_frag_dma_map(tx_ring->dev, frag, 0, len,
328 				       DMA_TO_DEVICE);
329 		if (dma_mapping_error(tx_ring->dev, dma))
330 			goto dma_err;
331 
332 		*txbd = temp_bd;
333 		enetc_clear_tx_bd(&temp_bd);
334 
335 		flags = 0;
336 		tx_swbd++;
337 		txbd++;
338 		i++;
339 		if (unlikely(i == tx_ring->bd_count)) {
340 			i = 0;
341 			tx_swbd = tx_ring->tx_swbd;
342 			txbd = ENETC_TXBD(*tx_ring, 0);
343 		}
344 		prefetchw(txbd);
345 
346 		temp_bd.addr = cpu_to_le64(dma);
347 		temp_bd.buf_len = cpu_to_le16(len);
348 
349 		tx_swbd->dma = dma;
350 		tx_swbd->len = len;
351 		tx_swbd->is_dma_page = 1;
352 		tx_swbd->dir = DMA_TO_DEVICE;
353 		count++;
354 	}
355 
356 	/* last BD needs 'F' bit set */
357 	flags |= ENETC_TXBD_FLAGS_F;
358 	temp_bd.flags = flags;
359 	*txbd = temp_bd;
360 
361 	tx_ring->tx_swbd[i].is_eof = true;
362 	tx_ring->tx_swbd[i].skb = skb;
363 
364 	enetc_bdr_idx_inc(tx_ring, &i);
365 	tx_ring->next_to_use = i;
366 
367 	skb_tx_timestamp(skb);
368 
369 	enetc_update_tx_ring_tail(tx_ring);
370 
371 	return count;
372 
373 dma_err:
374 	dev_err(tx_ring->dev, "DMA map error");
375 
376 	enetc_unwind_tx_frame(tx_ring, count, i);
377 
378 	return 0;
379 }
380 
enetc_map_tx_tso_hdr(struct enetc_bdr * tx_ring,struct sk_buff * skb,struct enetc_tx_swbd * tx_swbd,union enetc_tx_bd * txbd,int * i,int hdr_len,int data_len)381 static int enetc_map_tx_tso_hdr(struct enetc_bdr *tx_ring, struct sk_buff *skb,
382 				struct enetc_tx_swbd *tx_swbd,
383 				union enetc_tx_bd *txbd, int *i, int hdr_len,
384 				int data_len)
385 {
386 	union enetc_tx_bd txbd_tmp;
387 	u8 flags = 0, e_flags = 0;
388 	dma_addr_t addr;
389 	int count = 1;
390 
391 	enetc_clear_tx_bd(&txbd_tmp);
392 	addr = tx_ring->tso_headers_dma + *i * TSO_HEADER_SIZE;
393 
394 	if (skb_vlan_tag_present(skb))
395 		flags |= ENETC_TXBD_FLAGS_EX;
396 
397 	txbd_tmp.addr = cpu_to_le64(addr);
398 	txbd_tmp.buf_len = cpu_to_le16(hdr_len);
399 
400 	/* first BD needs frm_len and offload flags set */
401 	txbd_tmp.frm_len = cpu_to_le16(hdr_len + data_len);
402 	txbd_tmp.flags = flags;
403 
404 	/* For the TSO header we do not set the dma address since we do not
405 	 * want it unmapped when we do cleanup. We still set len so that we
406 	 * count the bytes sent.
407 	 */
408 	tx_swbd->len = hdr_len;
409 	tx_swbd->do_twostep_tstamp = false;
410 	tx_swbd->check_wb = false;
411 
412 	/* Actually write the header in the BD */
413 	*txbd = txbd_tmp;
414 
415 	/* Add extension BD for VLAN */
416 	if (flags & ENETC_TXBD_FLAGS_EX) {
417 		/* Get the next BD */
418 		enetc_bdr_idx_inc(tx_ring, i);
419 		txbd = ENETC_TXBD(*tx_ring, *i);
420 		tx_swbd = &tx_ring->tx_swbd[*i];
421 		prefetchw(txbd);
422 
423 		/* Setup the VLAN fields */
424 		enetc_clear_tx_bd(&txbd_tmp);
425 		txbd_tmp.ext.vid = cpu_to_le16(skb_vlan_tag_get(skb));
426 		txbd_tmp.ext.tpid = 0; /* < C-TAG */
427 		e_flags |= ENETC_TXBD_E_FLAGS_VLAN_INS;
428 
429 		/* Write the BD */
430 		txbd_tmp.ext.e_flags = e_flags;
431 		*txbd = txbd_tmp;
432 		count++;
433 	}
434 
435 	return count;
436 }
437 
enetc_map_tx_tso_data(struct enetc_bdr * tx_ring,struct sk_buff * skb,struct enetc_tx_swbd * tx_swbd,union enetc_tx_bd * txbd,char * data,int size,bool last_bd)438 static int enetc_map_tx_tso_data(struct enetc_bdr *tx_ring, struct sk_buff *skb,
439 				 struct enetc_tx_swbd *tx_swbd,
440 				 union enetc_tx_bd *txbd, char *data,
441 				 int size, bool last_bd)
442 {
443 	union enetc_tx_bd txbd_tmp;
444 	dma_addr_t addr;
445 	u8 flags = 0;
446 
447 	enetc_clear_tx_bd(&txbd_tmp);
448 
449 	addr = dma_map_single(tx_ring->dev, data, size, DMA_TO_DEVICE);
450 	if (unlikely(dma_mapping_error(tx_ring->dev, addr))) {
451 		netdev_err(tx_ring->ndev, "DMA map error\n");
452 		return -ENOMEM;
453 	}
454 
455 	if (last_bd) {
456 		flags |= ENETC_TXBD_FLAGS_F;
457 		tx_swbd->is_eof = 1;
458 	}
459 
460 	txbd_tmp.addr = cpu_to_le64(addr);
461 	txbd_tmp.buf_len = cpu_to_le16(size);
462 	txbd_tmp.flags = flags;
463 
464 	tx_swbd->dma = addr;
465 	tx_swbd->len = size;
466 	tx_swbd->dir = DMA_TO_DEVICE;
467 
468 	*txbd = txbd_tmp;
469 
470 	return 0;
471 }
472 
enetc_tso_hdr_csum(struct tso_t * tso,struct sk_buff * skb,char * hdr,int hdr_len,int * l4_hdr_len)473 static __wsum enetc_tso_hdr_csum(struct tso_t *tso, struct sk_buff *skb,
474 				 char *hdr, int hdr_len, int *l4_hdr_len)
475 {
476 	char *l4_hdr = hdr + skb_transport_offset(skb);
477 	int mac_hdr_len = skb_network_offset(skb);
478 
479 	if (tso->tlen != sizeof(struct udphdr)) {
480 		struct tcphdr *tcph = (struct tcphdr *)(l4_hdr);
481 
482 		tcph->check = 0;
483 	} else {
484 		struct udphdr *udph = (struct udphdr *)(l4_hdr);
485 
486 		udph->check = 0;
487 	}
488 
489 	/* Compute the IP checksum. This is necessary since tso_build_hdr()
490 	 * already incremented the IP ID field.
491 	 */
492 	if (!tso->ipv6) {
493 		struct iphdr *iph = (void *)(hdr + mac_hdr_len);
494 
495 		iph->check = 0;
496 		iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
497 	}
498 
499 	/* Compute the checksum over the L4 header. */
500 	*l4_hdr_len = hdr_len - skb_transport_offset(skb);
501 	return csum_partial(l4_hdr, *l4_hdr_len, 0);
502 }
503 
enetc_tso_complete_csum(struct enetc_bdr * tx_ring,struct tso_t * tso,struct sk_buff * skb,char * hdr,int len,__wsum sum)504 static void enetc_tso_complete_csum(struct enetc_bdr *tx_ring, struct tso_t *tso,
505 				    struct sk_buff *skb, char *hdr, int len,
506 				    __wsum sum)
507 {
508 	char *l4_hdr = hdr + skb_transport_offset(skb);
509 	__sum16 csum_final;
510 
511 	/* Complete the L4 checksum by appending the pseudo-header to the
512 	 * already computed checksum.
513 	 */
514 	if (!tso->ipv6)
515 		csum_final = csum_tcpudp_magic(ip_hdr(skb)->saddr,
516 					       ip_hdr(skb)->daddr,
517 					       len, ip_hdr(skb)->protocol, sum);
518 	else
519 		csum_final = csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
520 					     &ipv6_hdr(skb)->daddr,
521 					     len, ipv6_hdr(skb)->nexthdr, sum);
522 
523 	if (tso->tlen != sizeof(struct udphdr)) {
524 		struct tcphdr *tcph = (struct tcphdr *)(l4_hdr);
525 
526 		tcph->check = csum_final;
527 	} else {
528 		struct udphdr *udph = (struct udphdr *)(l4_hdr);
529 
530 		udph->check = csum_final;
531 	}
532 }
533 
enetc_map_tx_tso_buffs(struct enetc_bdr * tx_ring,struct sk_buff * skb)534 static int enetc_map_tx_tso_buffs(struct enetc_bdr *tx_ring, struct sk_buff *skb)
535 {
536 	int hdr_len, total_len, data_len;
537 	struct enetc_tx_swbd *tx_swbd;
538 	union enetc_tx_bd *txbd;
539 	struct tso_t tso;
540 	__wsum csum, csum2;
541 	int count = 0, pos;
542 	int err, i, bd_data_num;
543 
544 	/* Initialize the TSO handler, and prepare the first payload */
545 	hdr_len = tso_start(skb, &tso);
546 	total_len = skb->len - hdr_len;
547 	i = tx_ring->next_to_use;
548 
549 	while (total_len > 0) {
550 		char *hdr;
551 
552 		/* Get the BD */
553 		txbd = ENETC_TXBD(*tx_ring, i);
554 		tx_swbd = &tx_ring->tx_swbd[i];
555 		prefetchw(txbd);
556 
557 		/* Determine the length of this packet */
558 		data_len = min_t(int, skb_shinfo(skb)->gso_size, total_len);
559 		total_len -= data_len;
560 
561 		/* prepare packet headers: MAC + IP + TCP */
562 		hdr = tx_ring->tso_headers + i * TSO_HEADER_SIZE;
563 		tso_build_hdr(skb, hdr, &tso, data_len, total_len == 0);
564 
565 		/* compute the csum over the L4 header */
566 		csum = enetc_tso_hdr_csum(&tso, skb, hdr, hdr_len, &pos);
567 		count += enetc_map_tx_tso_hdr(tx_ring, skb, tx_swbd, txbd,
568 					      &i, hdr_len, data_len);
569 		bd_data_num = 0;
570 
571 		while (data_len > 0) {
572 			int size;
573 
574 			size = min_t(int, tso.size, data_len);
575 
576 			/* Advance the index in the BDR */
577 			enetc_bdr_idx_inc(tx_ring, &i);
578 			txbd = ENETC_TXBD(*tx_ring, i);
579 			tx_swbd = &tx_ring->tx_swbd[i];
580 			prefetchw(txbd);
581 
582 			/* Compute the checksum over this segment of data and
583 			 * add it to the csum already computed (over the L4
584 			 * header and possible other data segments).
585 			 */
586 			csum2 = csum_partial(tso.data, size, 0);
587 			csum = csum_block_add(csum, csum2, pos);
588 			pos += size;
589 
590 			err = enetc_map_tx_tso_data(tx_ring, skb, tx_swbd, txbd,
591 						    tso.data, size,
592 						    size == data_len);
593 			if (err) {
594 				if (i == 0)
595 					i = tx_ring->bd_count;
596 				i--;
597 
598 				goto err_map_data;
599 			}
600 
601 			data_len -= size;
602 			count++;
603 			bd_data_num++;
604 			tso_build_data(skb, &tso, size);
605 
606 			if (unlikely(bd_data_num >= ENETC_MAX_SKB_FRAGS && data_len))
607 				goto err_chained_bd;
608 		}
609 
610 		enetc_tso_complete_csum(tx_ring, &tso, skb, hdr, pos, csum);
611 
612 		if (total_len == 0)
613 			tx_swbd->skb = skb;
614 
615 		/* Go to the next BD */
616 		enetc_bdr_idx_inc(tx_ring, &i);
617 	}
618 
619 	tx_ring->next_to_use = i;
620 	enetc_update_tx_ring_tail(tx_ring);
621 
622 	return count;
623 
624 err_map_data:
625 	dev_err(tx_ring->dev, "DMA map error");
626 
627 err_chained_bd:
628 	enetc_unwind_tx_frame(tx_ring, count, i);
629 
630 	return 0;
631 }
632 
enetc_start_xmit(struct sk_buff * skb,struct net_device * ndev)633 static netdev_tx_t enetc_start_xmit(struct sk_buff *skb,
634 				    struct net_device *ndev)
635 {
636 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
637 	struct enetc_bdr *tx_ring;
638 	int count, err;
639 
640 	/* Queue one-step Sync packet if already locked */
641 	if (skb->cb[0] & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) {
642 		if (test_and_set_bit_lock(ENETC_TX_ONESTEP_TSTAMP_IN_PROGRESS,
643 					  &priv->flags)) {
644 			skb_queue_tail(&priv->tx_skbs, skb);
645 			return NETDEV_TX_OK;
646 		}
647 	}
648 
649 	tx_ring = priv->tx_ring[skb->queue_mapping];
650 
651 	if (skb_is_gso(skb)) {
652 		if (enetc_bd_unused(tx_ring) < tso_count_descs(skb)) {
653 			netif_stop_subqueue(ndev, tx_ring->index);
654 			return NETDEV_TX_BUSY;
655 		}
656 
657 		enetc_lock_mdio();
658 		count = enetc_map_tx_tso_buffs(tx_ring, skb);
659 		enetc_unlock_mdio();
660 	} else {
661 		if (unlikely(skb_shinfo(skb)->nr_frags > ENETC_MAX_SKB_FRAGS))
662 			if (unlikely(skb_linearize(skb)))
663 				goto drop_packet_err;
664 
665 		count = skb_shinfo(skb)->nr_frags + 1; /* fragments + head */
666 		if (enetc_bd_unused(tx_ring) < ENETC_TXBDS_NEEDED(count)) {
667 			netif_stop_subqueue(ndev, tx_ring->index);
668 			return NETDEV_TX_BUSY;
669 		}
670 
671 		if (skb->ip_summed == CHECKSUM_PARTIAL) {
672 			err = skb_checksum_help(skb);
673 			if (err)
674 				goto drop_packet_err;
675 		}
676 		enetc_lock_mdio();
677 		count = enetc_map_tx_buffs(tx_ring, skb);
678 		enetc_unlock_mdio();
679 	}
680 
681 	if (unlikely(!count))
682 		goto drop_packet_err;
683 
684 	if (enetc_bd_unused(tx_ring) < ENETC_TXBDS_MAX_NEEDED)
685 		netif_stop_subqueue(ndev, tx_ring->index);
686 
687 	return NETDEV_TX_OK;
688 
689 drop_packet_err:
690 	dev_kfree_skb_any(skb);
691 	return NETDEV_TX_OK;
692 }
693 
enetc_xmit(struct sk_buff * skb,struct net_device * ndev)694 netdev_tx_t enetc_xmit(struct sk_buff *skb, struct net_device *ndev)
695 {
696 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
697 	u8 udp, msgtype, twostep;
698 	u16 offset1, offset2;
699 
700 	/* Mark tx timestamp type on skb->cb[0] if requires */
701 	if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
702 	    (priv->active_offloads & ENETC_F_TX_TSTAMP_MASK)) {
703 		skb->cb[0] = priv->active_offloads & ENETC_F_TX_TSTAMP_MASK;
704 	} else {
705 		skb->cb[0] = 0;
706 	}
707 
708 	/* Fall back to two-step timestamp if not one-step Sync packet */
709 	if (skb->cb[0] & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) {
710 		if (enetc_ptp_parse(skb, &udp, &msgtype, &twostep,
711 				    &offset1, &offset2) ||
712 		    msgtype != PTP_MSGTYPE_SYNC || twostep != 0)
713 			skb->cb[0] = ENETC_F_TX_TSTAMP;
714 	}
715 
716 	return enetc_start_xmit(skb, ndev);
717 }
718 EXPORT_SYMBOL_GPL(enetc_xmit);
719 
enetc_msix(int irq,void * data)720 static irqreturn_t enetc_msix(int irq, void *data)
721 {
722 	struct enetc_int_vector	*v = data;
723 	int i;
724 
725 	enetc_lock_mdio();
726 
727 	/* disable interrupts */
728 	enetc_wr_reg_hot(v->rbier, 0);
729 	enetc_wr_reg_hot(v->ricr1, v->rx_ictt);
730 
731 	for_each_set_bit(i, &v->tx_rings_map, ENETC_MAX_NUM_TXQS)
732 		enetc_wr_reg_hot(v->tbier_base + ENETC_BDR_OFF(i), 0);
733 
734 	enetc_unlock_mdio();
735 
736 	napi_schedule(&v->napi);
737 
738 	return IRQ_HANDLED;
739 }
740 
enetc_rx_dim_work(struct work_struct * w)741 static void enetc_rx_dim_work(struct work_struct *w)
742 {
743 	struct dim *dim = container_of(w, struct dim, work);
744 	struct dim_cq_moder moder =
745 		net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
746 	struct enetc_int_vector	*v =
747 		container_of(dim, struct enetc_int_vector, rx_dim);
748 
749 	v->rx_ictt = enetc_usecs_to_cycles(moder.usec);
750 	dim->state = DIM_START_MEASURE;
751 }
752 
enetc_rx_net_dim(struct enetc_int_vector * v)753 static void enetc_rx_net_dim(struct enetc_int_vector *v)
754 {
755 	struct dim_sample dim_sample = {};
756 
757 	v->comp_cnt++;
758 
759 	if (!v->rx_napi_work)
760 		return;
761 
762 	dim_update_sample(v->comp_cnt,
763 			  v->rx_ring.stats.packets,
764 			  v->rx_ring.stats.bytes,
765 			  &dim_sample);
766 	net_dim(&v->rx_dim, dim_sample);
767 }
768 
enetc_bd_ready_count(struct enetc_bdr * tx_ring,int ci)769 static int enetc_bd_ready_count(struct enetc_bdr *tx_ring, int ci)
770 {
771 	int pi = enetc_rd_reg_hot(tx_ring->tcir) & ENETC_TBCIR_IDX_MASK;
772 
773 	return pi >= ci ? pi - ci : tx_ring->bd_count - ci + pi;
774 }
775 
enetc_page_reusable(struct page * page)776 static bool enetc_page_reusable(struct page *page)
777 {
778 	return (!page_is_pfmemalloc(page) && page_ref_count(page) == 1);
779 }
780 
enetc_reuse_page(struct enetc_bdr * rx_ring,struct enetc_rx_swbd * old)781 static void enetc_reuse_page(struct enetc_bdr *rx_ring,
782 			     struct enetc_rx_swbd *old)
783 {
784 	struct enetc_rx_swbd *new;
785 
786 	new = &rx_ring->rx_swbd[rx_ring->next_to_alloc];
787 
788 	/* next buf that may reuse a page */
789 	enetc_bdr_idx_inc(rx_ring, &rx_ring->next_to_alloc);
790 
791 	/* copy page reference */
792 	*new = *old;
793 }
794 
enetc_get_tx_tstamp(struct enetc_hw * hw,union enetc_tx_bd * txbd,u64 * tstamp)795 static void enetc_get_tx_tstamp(struct enetc_hw *hw, union enetc_tx_bd *txbd,
796 				u64 *tstamp)
797 {
798 	u32 lo, hi, tstamp_lo;
799 
800 	lo = enetc_rd_hot(hw, ENETC_SICTR0);
801 	hi = enetc_rd_hot(hw, ENETC_SICTR1);
802 	tstamp_lo = le32_to_cpu(txbd->wb.tstamp);
803 	if (lo <= tstamp_lo)
804 		hi -= 1;
805 	*tstamp = (u64)hi << 32 | tstamp_lo;
806 }
807 
enetc_tstamp_tx(struct sk_buff * skb,u64 tstamp)808 static void enetc_tstamp_tx(struct sk_buff *skb, u64 tstamp)
809 {
810 	struct skb_shared_hwtstamps shhwtstamps;
811 
812 	if (skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) {
813 		memset(&shhwtstamps, 0, sizeof(shhwtstamps));
814 		shhwtstamps.hwtstamp = ns_to_ktime(tstamp);
815 		skb_txtime_consumed(skb);
816 		skb_tstamp_tx(skb, &shhwtstamps);
817 	}
818 }
819 
enetc_recycle_xdp_tx_buff(struct enetc_bdr * tx_ring,struct enetc_tx_swbd * tx_swbd)820 static void enetc_recycle_xdp_tx_buff(struct enetc_bdr *tx_ring,
821 				      struct enetc_tx_swbd *tx_swbd)
822 {
823 	struct enetc_ndev_priv *priv = netdev_priv(tx_ring->ndev);
824 	struct enetc_rx_swbd rx_swbd = {
825 		.dma = tx_swbd->dma,
826 		.page = tx_swbd->page,
827 		.page_offset = tx_swbd->page_offset,
828 		.dir = tx_swbd->dir,
829 		.len = tx_swbd->len,
830 	};
831 	struct enetc_bdr *rx_ring;
832 
833 	rx_ring = enetc_rx_ring_from_xdp_tx_ring(priv, tx_ring);
834 
835 	if (likely(enetc_swbd_unused(rx_ring))) {
836 		enetc_reuse_page(rx_ring, &rx_swbd);
837 
838 		/* sync for use by the device */
839 		dma_sync_single_range_for_device(rx_ring->dev, rx_swbd.dma,
840 						 rx_swbd.page_offset,
841 						 ENETC_RXB_DMA_SIZE_XDP,
842 						 rx_swbd.dir);
843 
844 		rx_ring->stats.recycles++;
845 	} else {
846 		/* RX ring is already full, we need to unmap and free the
847 		 * page, since there's nothing useful we can do with it.
848 		 */
849 		rx_ring->stats.recycle_failures++;
850 
851 		dma_unmap_page(rx_ring->dev, rx_swbd.dma, PAGE_SIZE,
852 			       rx_swbd.dir);
853 		__free_page(rx_swbd.page);
854 	}
855 
856 	rx_ring->xdp.xdp_tx_in_flight--;
857 }
858 
enetc_clean_tx_ring(struct enetc_bdr * tx_ring,int napi_budget)859 static bool enetc_clean_tx_ring(struct enetc_bdr *tx_ring, int napi_budget)
860 {
861 	int tx_frm_cnt = 0, tx_byte_cnt = 0, tx_win_drop = 0;
862 	struct net_device *ndev = tx_ring->ndev;
863 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
864 	struct enetc_tx_swbd *tx_swbd;
865 	int i, bds_to_clean;
866 	bool do_twostep_tstamp;
867 	u64 tstamp = 0;
868 
869 	i = tx_ring->next_to_clean;
870 	tx_swbd = &tx_ring->tx_swbd[i];
871 
872 	bds_to_clean = enetc_bd_ready_count(tx_ring, i);
873 
874 	do_twostep_tstamp = false;
875 
876 	while (bds_to_clean && tx_frm_cnt < ENETC_DEFAULT_TX_WORK) {
877 		struct xdp_frame *xdp_frame = enetc_tx_swbd_get_xdp_frame(tx_swbd);
878 		struct sk_buff *skb = enetc_tx_swbd_get_skb(tx_swbd);
879 		bool is_eof = tx_swbd->is_eof;
880 
881 		if (unlikely(tx_swbd->check_wb)) {
882 			union enetc_tx_bd *txbd = ENETC_TXBD(*tx_ring, i);
883 
884 			if (txbd->flags & ENETC_TXBD_FLAGS_W &&
885 			    tx_swbd->do_twostep_tstamp) {
886 				enetc_get_tx_tstamp(&priv->si->hw, txbd,
887 						    &tstamp);
888 				do_twostep_tstamp = true;
889 			}
890 
891 			if (tx_swbd->qbv_en &&
892 			    txbd->wb.status & ENETC_TXBD_STATS_WIN)
893 				tx_win_drop++;
894 		}
895 
896 		if (tx_swbd->is_xdp_tx)
897 			enetc_recycle_xdp_tx_buff(tx_ring, tx_swbd);
898 		else if (likely(tx_swbd->dma))
899 			enetc_unmap_tx_buff(tx_ring, tx_swbd);
900 
901 		if (xdp_frame) {
902 			xdp_return_frame(xdp_frame);
903 		} else if (skb) {
904 			if (unlikely(skb->cb[0] & ENETC_F_TX_ONESTEP_SYNC_TSTAMP)) {
905 				/* Start work to release lock for next one-step
906 				 * timestamping packet. And send one skb in
907 				 * tx_skbs queue if has.
908 				 */
909 				schedule_work(&priv->tx_onestep_tstamp);
910 			} else if (unlikely(do_twostep_tstamp)) {
911 				enetc_tstamp_tx(skb, tstamp);
912 				do_twostep_tstamp = false;
913 			}
914 			napi_consume_skb(skb, napi_budget);
915 		}
916 
917 		tx_byte_cnt += tx_swbd->len;
918 		/* Scrub the swbd here so we don't have to do that
919 		 * when we reuse it during xmit
920 		 */
921 		memset(tx_swbd, 0, sizeof(*tx_swbd));
922 
923 		bds_to_clean--;
924 		tx_swbd++;
925 		i++;
926 		if (unlikely(i == tx_ring->bd_count)) {
927 			i = 0;
928 			tx_swbd = tx_ring->tx_swbd;
929 		}
930 
931 		/* BD iteration loop end */
932 		if (is_eof) {
933 			tx_frm_cnt++;
934 			/* re-arm interrupt source */
935 			enetc_wr_reg_hot(tx_ring->idr, BIT(tx_ring->index) |
936 					 BIT(16 + tx_ring->index));
937 		}
938 
939 		if (unlikely(!bds_to_clean))
940 			bds_to_clean = enetc_bd_ready_count(tx_ring, i);
941 	}
942 
943 	tx_ring->next_to_clean = i;
944 	tx_ring->stats.packets += tx_frm_cnt;
945 	tx_ring->stats.bytes += tx_byte_cnt;
946 	tx_ring->stats.win_drop += tx_win_drop;
947 
948 	if (unlikely(tx_frm_cnt && netif_carrier_ok(ndev) &&
949 		     __netif_subqueue_stopped(ndev, tx_ring->index) &&
950 		     !test_bit(ENETC_TX_DOWN, &priv->flags) &&
951 		     (enetc_bd_unused(tx_ring) >= ENETC_TXBDS_MAX_NEEDED))) {
952 		netif_wake_subqueue(ndev, tx_ring->index);
953 	}
954 
955 	return tx_frm_cnt != ENETC_DEFAULT_TX_WORK;
956 }
957 
enetc_new_page(struct enetc_bdr * rx_ring,struct enetc_rx_swbd * rx_swbd)958 static bool enetc_new_page(struct enetc_bdr *rx_ring,
959 			   struct enetc_rx_swbd *rx_swbd)
960 {
961 	bool xdp = !!(rx_ring->xdp.prog);
962 	struct page *page;
963 	dma_addr_t addr;
964 
965 	page = dev_alloc_page();
966 	if (unlikely(!page))
967 		return false;
968 
969 	/* For XDP_TX, we forgo dma_unmap -> dma_map */
970 	rx_swbd->dir = xdp ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
971 
972 	addr = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, rx_swbd->dir);
973 	if (unlikely(dma_mapping_error(rx_ring->dev, addr))) {
974 		__free_page(page);
975 
976 		return false;
977 	}
978 
979 	rx_swbd->dma = addr;
980 	rx_swbd->page = page;
981 	rx_swbd->page_offset = rx_ring->buffer_offset;
982 
983 	return true;
984 }
985 
enetc_refill_rx_ring(struct enetc_bdr * rx_ring,const int buff_cnt)986 static int enetc_refill_rx_ring(struct enetc_bdr *rx_ring, const int buff_cnt)
987 {
988 	struct enetc_rx_swbd *rx_swbd;
989 	union enetc_rx_bd *rxbd;
990 	int i, j;
991 
992 	i = rx_ring->next_to_use;
993 	rx_swbd = &rx_ring->rx_swbd[i];
994 	rxbd = enetc_rxbd(rx_ring, i);
995 
996 	for (j = 0; j < buff_cnt; j++) {
997 		/* try reuse page */
998 		if (unlikely(!rx_swbd->page)) {
999 			if (unlikely(!enetc_new_page(rx_ring, rx_swbd))) {
1000 				rx_ring->stats.rx_alloc_errs++;
1001 				break;
1002 			}
1003 		}
1004 
1005 		/* update RxBD */
1006 		rxbd->w.addr = cpu_to_le64(rx_swbd->dma +
1007 					   rx_swbd->page_offset);
1008 		/* clear 'R" as well */
1009 		rxbd->r.lstatus = 0;
1010 
1011 		enetc_rxbd_next(rx_ring, &rxbd, &i);
1012 		rx_swbd = &rx_ring->rx_swbd[i];
1013 	}
1014 
1015 	if (likely(j)) {
1016 		rx_ring->next_to_alloc = i; /* keep track from page reuse */
1017 		rx_ring->next_to_use = i;
1018 
1019 		/* update ENETC's consumer index */
1020 		enetc_wr_reg_hot(rx_ring->rcir, rx_ring->next_to_use);
1021 	}
1022 
1023 	return j;
1024 }
1025 
enetc_get_rx_tstamp(struct net_device * ndev,union enetc_rx_bd * rxbd,struct sk_buff * skb)1026 static void enetc_get_rx_tstamp(struct net_device *ndev,
1027 				union enetc_rx_bd *rxbd,
1028 				struct sk_buff *skb)
1029 {
1030 	struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
1031 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
1032 	struct enetc_hw *hw = &priv->si->hw;
1033 	u32 lo, hi, tstamp_lo;
1034 	u64 tstamp;
1035 
1036 	if (le16_to_cpu(rxbd->r.flags) & ENETC_RXBD_FLAG_TSTMP) {
1037 		lo = enetc_rd_reg_hot(hw->reg + ENETC_SICTR0);
1038 		hi = enetc_rd_reg_hot(hw->reg + ENETC_SICTR1);
1039 		rxbd = enetc_rxbd_ext(rxbd);
1040 		tstamp_lo = le32_to_cpu(rxbd->ext.tstamp);
1041 		if (lo <= tstamp_lo)
1042 			hi -= 1;
1043 
1044 		tstamp = (u64)hi << 32 | tstamp_lo;
1045 		memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1046 		shhwtstamps->hwtstamp = ns_to_ktime(tstamp);
1047 	}
1048 }
1049 
enetc_get_offloads(struct enetc_bdr * rx_ring,union enetc_rx_bd * rxbd,struct sk_buff * skb)1050 static void enetc_get_offloads(struct enetc_bdr *rx_ring,
1051 			       union enetc_rx_bd *rxbd, struct sk_buff *skb)
1052 {
1053 	struct enetc_ndev_priv *priv = netdev_priv(rx_ring->ndev);
1054 
1055 	/* TODO: hashing */
1056 	if (rx_ring->ndev->features & NETIF_F_RXCSUM) {
1057 		u16 inet_csum = le16_to_cpu(rxbd->r.inet_csum);
1058 
1059 		skb->csum = csum_unfold((__force __sum16)~htons(inet_csum));
1060 		skb->ip_summed = CHECKSUM_COMPLETE;
1061 	}
1062 
1063 	if (le16_to_cpu(rxbd->r.flags) & ENETC_RXBD_FLAG_VLAN) {
1064 		__be16 tpid = 0;
1065 
1066 		switch (le16_to_cpu(rxbd->r.flags) & ENETC_RXBD_FLAG_TPID) {
1067 		case 0:
1068 			tpid = htons(ETH_P_8021Q);
1069 			break;
1070 		case 1:
1071 			tpid = htons(ETH_P_8021AD);
1072 			break;
1073 		case 2:
1074 			tpid = htons(enetc_port_rd(&priv->si->hw,
1075 						   ENETC_PCVLANR1));
1076 			break;
1077 		case 3:
1078 			tpid = htons(enetc_port_rd(&priv->si->hw,
1079 						   ENETC_PCVLANR2));
1080 			break;
1081 		default:
1082 			break;
1083 		}
1084 
1085 		__vlan_hwaccel_put_tag(skb, tpid, le16_to_cpu(rxbd->r.vlan_opt));
1086 	}
1087 
1088 	if (IS_ENABLED(CONFIG_FSL_ENETC_PTP_CLOCK) &&
1089 	    (priv->active_offloads & ENETC_F_RX_TSTAMP))
1090 		enetc_get_rx_tstamp(rx_ring->ndev, rxbd, skb);
1091 }
1092 
1093 /* This gets called during the non-XDP NAPI poll cycle as well as on XDP_PASS,
1094  * so it needs to work with both DMA_FROM_DEVICE as well as DMA_BIDIRECTIONAL
1095  * mapped buffers.
1096  */
enetc_get_rx_buff(struct enetc_bdr * rx_ring,int i,u16 size)1097 static struct enetc_rx_swbd *enetc_get_rx_buff(struct enetc_bdr *rx_ring,
1098 					       int i, u16 size)
1099 {
1100 	struct enetc_rx_swbd *rx_swbd = &rx_ring->rx_swbd[i];
1101 
1102 	dma_sync_single_range_for_cpu(rx_ring->dev, rx_swbd->dma,
1103 				      rx_swbd->page_offset,
1104 				      size, rx_swbd->dir);
1105 	return rx_swbd;
1106 }
1107 
1108 /* Reuse the current page without performing half-page buffer flipping */
enetc_put_rx_buff(struct enetc_bdr * rx_ring,struct enetc_rx_swbd * rx_swbd)1109 static void enetc_put_rx_buff(struct enetc_bdr *rx_ring,
1110 			      struct enetc_rx_swbd *rx_swbd)
1111 {
1112 	size_t buffer_size = ENETC_RXB_TRUESIZE - rx_ring->buffer_offset;
1113 
1114 	enetc_reuse_page(rx_ring, rx_swbd);
1115 
1116 	dma_sync_single_range_for_device(rx_ring->dev, rx_swbd->dma,
1117 					 rx_swbd->page_offset,
1118 					 buffer_size, rx_swbd->dir);
1119 
1120 	rx_swbd->page = NULL;
1121 }
1122 
1123 /* Reuse the current page by performing half-page buffer flipping */
enetc_flip_rx_buff(struct enetc_bdr * rx_ring,struct enetc_rx_swbd * rx_swbd)1124 static void enetc_flip_rx_buff(struct enetc_bdr *rx_ring,
1125 			       struct enetc_rx_swbd *rx_swbd)
1126 {
1127 	if (likely(enetc_page_reusable(rx_swbd->page))) {
1128 		rx_swbd->page_offset ^= ENETC_RXB_TRUESIZE;
1129 		page_ref_inc(rx_swbd->page);
1130 
1131 		enetc_put_rx_buff(rx_ring, rx_swbd);
1132 	} else {
1133 		dma_unmap_page(rx_ring->dev, rx_swbd->dma, PAGE_SIZE,
1134 			       rx_swbd->dir);
1135 		rx_swbd->page = NULL;
1136 	}
1137 }
1138 
enetc_map_rx_buff_to_skb(struct enetc_bdr * rx_ring,int i,u16 size)1139 static struct sk_buff *enetc_map_rx_buff_to_skb(struct enetc_bdr *rx_ring,
1140 						int i, u16 size)
1141 {
1142 	struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size);
1143 	struct sk_buff *skb;
1144 	void *ba;
1145 
1146 	ba = page_address(rx_swbd->page) + rx_swbd->page_offset;
1147 	skb = build_skb(ba - rx_ring->buffer_offset, ENETC_RXB_TRUESIZE);
1148 	if (unlikely(!skb)) {
1149 		rx_ring->stats.rx_alloc_errs++;
1150 		return NULL;
1151 	}
1152 
1153 	skb_reserve(skb, rx_ring->buffer_offset);
1154 	__skb_put(skb, size);
1155 
1156 	enetc_flip_rx_buff(rx_ring, rx_swbd);
1157 
1158 	return skb;
1159 }
1160 
enetc_add_rx_buff_to_skb(struct enetc_bdr * rx_ring,int i,u16 size,struct sk_buff * skb)1161 static void enetc_add_rx_buff_to_skb(struct enetc_bdr *rx_ring, int i,
1162 				     u16 size, struct sk_buff *skb)
1163 {
1164 	struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size);
1165 
1166 	skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_swbd->page,
1167 			rx_swbd->page_offset, size, ENETC_RXB_TRUESIZE);
1168 
1169 	enetc_flip_rx_buff(rx_ring, rx_swbd);
1170 }
1171 
enetc_check_bd_errors_and_consume(struct enetc_bdr * rx_ring,u32 bd_status,union enetc_rx_bd ** rxbd,int * i)1172 static bool enetc_check_bd_errors_and_consume(struct enetc_bdr *rx_ring,
1173 					      u32 bd_status,
1174 					      union enetc_rx_bd **rxbd, int *i)
1175 {
1176 	if (likely(!(bd_status & ENETC_RXBD_LSTATUS(ENETC_RXBD_ERR_MASK))))
1177 		return false;
1178 
1179 	enetc_put_rx_buff(rx_ring, &rx_ring->rx_swbd[*i]);
1180 	enetc_rxbd_next(rx_ring, rxbd, i);
1181 
1182 	while (!(bd_status & ENETC_RXBD_LSTATUS_F)) {
1183 		dma_rmb();
1184 		bd_status = le32_to_cpu((*rxbd)->r.lstatus);
1185 
1186 		enetc_put_rx_buff(rx_ring, &rx_ring->rx_swbd[*i]);
1187 		enetc_rxbd_next(rx_ring, rxbd, i);
1188 	}
1189 
1190 	rx_ring->ndev->stats.rx_dropped++;
1191 	rx_ring->ndev->stats.rx_errors++;
1192 
1193 	return true;
1194 }
1195 
enetc_build_skb(struct enetc_bdr * rx_ring,u32 bd_status,union enetc_rx_bd ** rxbd,int * i,int * cleaned_cnt,int buffer_size)1196 static struct sk_buff *enetc_build_skb(struct enetc_bdr *rx_ring,
1197 				       u32 bd_status, union enetc_rx_bd **rxbd,
1198 				       int *i, int *cleaned_cnt, int buffer_size)
1199 {
1200 	struct sk_buff *skb;
1201 	u16 size;
1202 
1203 	size = le16_to_cpu((*rxbd)->r.buf_len);
1204 	skb = enetc_map_rx_buff_to_skb(rx_ring, *i, size);
1205 	if (!skb)
1206 		return NULL;
1207 
1208 	enetc_get_offloads(rx_ring, *rxbd, skb);
1209 
1210 	(*cleaned_cnt)++;
1211 
1212 	enetc_rxbd_next(rx_ring, rxbd, i);
1213 
1214 	/* not last BD in frame? */
1215 	while (!(bd_status & ENETC_RXBD_LSTATUS_F)) {
1216 		bd_status = le32_to_cpu((*rxbd)->r.lstatus);
1217 		size = buffer_size;
1218 
1219 		if (bd_status & ENETC_RXBD_LSTATUS_F) {
1220 			dma_rmb();
1221 			size = le16_to_cpu((*rxbd)->r.buf_len);
1222 		}
1223 
1224 		enetc_add_rx_buff_to_skb(rx_ring, *i, size, skb);
1225 
1226 		(*cleaned_cnt)++;
1227 
1228 		enetc_rxbd_next(rx_ring, rxbd, i);
1229 	}
1230 
1231 	skb_record_rx_queue(skb, rx_ring->index);
1232 	skb->protocol = eth_type_trans(skb, rx_ring->ndev);
1233 
1234 	return skb;
1235 }
1236 
1237 #define ENETC_RXBD_BUNDLE 16 /* # of BDs to update at once */
1238 
enetc_clean_rx_ring(struct enetc_bdr * rx_ring,struct napi_struct * napi,int work_limit)1239 static int enetc_clean_rx_ring(struct enetc_bdr *rx_ring,
1240 			       struct napi_struct *napi, int work_limit)
1241 {
1242 	int rx_frm_cnt = 0, rx_byte_cnt = 0;
1243 	int cleaned_cnt, i;
1244 
1245 	cleaned_cnt = enetc_bd_unused(rx_ring);
1246 	/* next descriptor to process */
1247 	i = rx_ring->next_to_clean;
1248 
1249 	while (likely(rx_frm_cnt < work_limit)) {
1250 		union enetc_rx_bd *rxbd;
1251 		struct sk_buff *skb;
1252 		u32 bd_status;
1253 
1254 		if (cleaned_cnt >= ENETC_RXBD_BUNDLE)
1255 			cleaned_cnt -= enetc_refill_rx_ring(rx_ring,
1256 							    cleaned_cnt);
1257 
1258 		rxbd = enetc_rxbd(rx_ring, i);
1259 		bd_status = le32_to_cpu(rxbd->r.lstatus);
1260 		if (!bd_status)
1261 			break;
1262 
1263 		enetc_wr_reg_hot(rx_ring->idr, BIT(rx_ring->index));
1264 		dma_rmb(); /* for reading other rxbd fields */
1265 
1266 		if (enetc_check_bd_errors_and_consume(rx_ring, bd_status,
1267 						      &rxbd, &i))
1268 			break;
1269 
1270 		skb = enetc_build_skb(rx_ring, bd_status, &rxbd, &i,
1271 				      &cleaned_cnt, ENETC_RXB_DMA_SIZE);
1272 		if (!skb)
1273 			break;
1274 
1275 		/* When set, the outer VLAN header is extracted and reported
1276 		 * in the receive buffer descriptor. So rx_byte_cnt should
1277 		 * add the length of the extracted VLAN header.
1278 		 */
1279 		if (bd_status & ENETC_RXBD_FLAG_VLAN)
1280 			rx_byte_cnt += VLAN_HLEN;
1281 		rx_byte_cnt += skb->len + ETH_HLEN;
1282 		rx_frm_cnt++;
1283 
1284 		napi_gro_receive(napi, skb);
1285 	}
1286 
1287 	rx_ring->next_to_clean = i;
1288 
1289 	rx_ring->stats.packets += rx_frm_cnt;
1290 	rx_ring->stats.bytes += rx_byte_cnt;
1291 
1292 	return rx_frm_cnt;
1293 }
1294 
enetc_xdp_map_tx_buff(struct enetc_bdr * tx_ring,int i,struct enetc_tx_swbd * tx_swbd,int frm_len)1295 static void enetc_xdp_map_tx_buff(struct enetc_bdr *tx_ring, int i,
1296 				  struct enetc_tx_swbd *tx_swbd,
1297 				  int frm_len)
1298 {
1299 	union enetc_tx_bd *txbd = ENETC_TXBD(*tx_ring, i);
1300 
1301 	prefetchw(txbd);
1302 
1303 	enetc_clear_tx_bd(txbd);
1304 	txbd->addr = cpu_to_le64(tx_swbd->dma + tx_swbd->page_offset);
1305 	txbd->buf_len = cpu_to_le16(tx_swbd->len);
1306 	txbd->frm_len = cpu_to_le16(frm_len);
1307 
1308 	memcpy(&tx_ring->tx_swbd[i], tx_swbd, sizeof(*tx_swbd));
1309 }
1310 
1311 /* Puts in the TX ring one XDP frame, mapped as an array of TX software buffer
1312  * descriptors.
1313  */
enetc_xdp_tx(struct enetc_bdr * tx_ring,struct enetc_tx_swbd * xdp_tx_arr,int num_tx_swbd)1314 static bool enetc_xdp_tx(struct enetc_bdr *tx_ring,
1315 			 struct enetc_tx_swbd *xdp_tx_arr, int num_tx_swbd)
1316 {
1317 	struct enetc_tx_swbd *tmp_tx_swbd = xdp_tx_arr;
1318 	int i, k, frm_len = tmp_tx_swbd->len;
1319 
1320 	if (unlikely(enetc_bd_unused(tx_ring) < ENETC_TXBDS_NEEDED(num_tx_swbd)))
1321 		return false;
1322 
1323 	while (unlikely(!tmp_tx_swbd->is_eof)) {
1324 		tmp_tx_swbd++;
1325 		frm_len += tmp_tx_swbd->len;
1326 	}
1327 
1328 	i = tx_ring->next_to_use;
1329 
1330 	for (k = 0; k < num_tx_swbd; k++) {
1331 		struct enetc_tx_swbd *xdp_tx_swbd = &xdp_tx_arr[k];
1332 
1333 		enetc_xdp_map_tx_buff(tx_ring, i, xdp_tx_swbd, frm_len);
1334 
1335 		/* last BD needs 'F' bit set */
1336 		if (xdp_tx_swbd->is_eof) {
1337 			union enetc_tx_bd *txbd = ENETC_TXBD(*tx_ring, i);
1338 
1339 			txbd->flags = ENETC_TXBD_FLAGS_F;
1340 		}
1341 
1342 		enetc_bdr_idx_inc(tx_ring, &i);
1343 	}
1344 
1345 	tx_ring->next_to_use = i;
1346 
1347 	return true;
1348 }
1349 
enetc_xdp_frame_to_xdp_tx_swbd(struct enetc_bdr * tx_ring,struct enetc_tx_swbd * xdp_tx_arr,struct xdp_frame * xdp_frame)1350 static int enetc_xdp_frame_to_xdp_tx_swbd(struct enetc_bdr *tx_ring,
1351 					  struct enetc_tx_swbd *xdp_tx_arr,
1352 					  struct xdp_frame *xdp_frame)
1353 {
1354 	struct enetc_tx_swbd *xdp_tx_swbd = &xdp_tx_arr[0];
1355 	struct skb_shared_info *shinfo;
1356 	void *data = xdp_frame->data;
1357 	int len = xdp_frame->len;
1358 	skb_frag_t *frag;
1359 	dma_addr_t dma;
1360 	unsigned int f;
1361 	int n = 0;
1362 
1363 	dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE);
1364 	if (unlikely(dma_mapping_error(tx_ring->dev, dma))) {
1365 		netdev_err(tx_ring->ndev, "DMA map error\n");
1366 		return -1;
1367 	}
1368 
1369 	xdp_tx_swbd->dma = dma;
1370 	xdp_tx_swbd->dir = DMA_TO_DEVICE;
1371 	xdp_tx_swbd->len = len;
1372 	xdp_tx_swbd->is_xdp_redirect = true;
1373 	xdp_tx_swbd->is_eof = false;
1374 	xdp_tx_swbd->xdp_frame = NULL;
1375 
1376 	n++;
1377 
1378 	if (!xdp_frame_has_frags(xdp_frame))
1379 		goto out;
1380 
1381 	xdp_tx_swbd = &xdp_tx_arr[n];
1382 
1383 	shinfo = xdp_get_shared_info_from_frame(xdp_frame);
1384 
1385 	for (f = 0, frag = &shinfo->frags[0]; f < shinfo->nr_frags;
1386 	     f++, frag++) {
1387 		data = skb_frag_address(frag);
1388 		len = skb_frag_size(frag);
1389 
1390 		dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE);
1391 		if (unlikely(dma_mapping_error(tx_ring->dev, dma))) {
1392 			/* Undo the DMA mapping for all fragments */
1393 			while (--n >= 0)
1394 				enetc_unmap_tx_buff(tx_ring, &xdp_tx_arr[n]);
1395 
1396 			netdev_err(tx_ring->ndev, "DMA map error\n");
1397 			return -1;
1398 		}
1399 
1400 		xdp_tx_swbd->dma = dma;
1401 		xdp_tx_swbd->dir = DMA_TO_DEVICE;
1402 		xdp_tx_swbd->len = len;
1403 		xdp_tx_swbd->is_xdp_redirect = true;
1404 		xdp_tx_swbd->is_eof = false;
1405 		xdp_tx_swbd->xdp_frame = NULL;
1406 
1407 		n++;
1408 		xdp_tx_swbd = &xdp_tx_arr[n];
1409 	}
1410 out:
1411 	xdp_tx_arr[n - 1].is_eof = true;
1412 	xdp_tx_arr[n - 1].xdp_frame = xdp_frame;
1413 
1414 	return n;
1415 }
1416 
enetc_xdp_xmit(struct net_device * ndev,int num_frames,struct xdp_frame ** frames,u32 flags)1417 int enetc_xdp_xmit(struct net_device *ndev, int num_frames,
1418 		   struct xdp_frame **frames, u32 flags)
1419 {
1420 	struct enetc_tx_swbd xdp_redirect_arr[ENETC_MAX_SKB_FRAGS] = {0};
1421 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
1422 	struct enetc_bdr *tx_ring;
1423 	int xdp_tx_bd_cnt, i, k;
1424 	int xdp_tx_frm_cnt = 0;
1425 
1426 	if (unlikely(test_bit(ENETC_TX_DOWN, &priv->flags)))
1427 		return -ENETDOWN;
1428 
1429 	enetc_lock_mdio();
1430 
1431 	tx_ring = priv->xdp_tx_ring[smp_processor_id()];
1432 
1433 	prefetchw(ENETC_TXBD(*tx_ring, tx_ring->next_to_use));
1434 
1435 	for (k = 0; k < num_frames; k++) {
1436 		xdp_tx_bd_cnt = enetc_xdp_frame_to_xdp_tx_swbd(tx_ring,
1437 							       xdp_redirect_arr,
1438 							       frames[k]);
1439 		if (unlikely(xdp_tx_bd_cnt < 0))
1440 			break;
1441 
1442 		if (unlikely(!enetc_xdp_tx(tx_ring, xdp_redirect_arr,
1443 					   xdp_tx_bd_cnt))) {
1444 			for (i = 0; i < xdp_tx_bd_cnt; i++)
1445 				enetc_unmap_tx_buff(tx_ring,
1446 						    &xdp_redirect_arr[i]);
1447 			tx_ring->stats.xdp_tx_drops++;
1448 			break;
1449 		}
1450 
1451 		xdp_tx_frm_cnt++;
1452 	}
1453 
1454 	if (unlikely((flags & XDP_XMIT_FLUSH) || k != xdp_tx_frm_cnt))
1455 		enetc_update_tx_ring_tail(tx_ring);
1456 
1457 	tx_ring->stats.xdp_tx += xdp_tx_frm_cnt;
1458 
1459 	enetc_unlock_mdio();
1460 
1461 	return xdp_tx_frm_cnt;
1462 }
1463 EXPORT_SYMBOL_GPL(enetc_xdp_xmit);
1464 
enetc_map_rx_buff_to_xdp(struct enetc_bdr * rx_ring,int i,struct xdp_buff * xdp_buff,u16 size)1465 static void enetc_map_rx_buff_to_xdp(struct enetc_bdr *rx_ring, int i,
1466 				     struct xdp_buff *xdp_buff, u16 size)
1467 {
1468 	struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size);
1469 	void *hard_start = page_address(rx_swbd->page) + rx_swbd->page_offset;
1470 
1471 	/* To be used for XDP_TX */
1472 	rx_swbd->len = size;
1473 
1474 	xdp_prepare_buff(xdp_buff, hard_start - rx_ring->buffer_offset,
1475 			 rx_ring->buffer_offset, size, false);
1476 }
1477 
enetc_add_rx_buff_to_xdp(struct enetc_bdr * rx_ring,int i,u16 size,struct xdp_buff * xdp_buff)1478 static void enetc_add_rx_buff_to_xdp(struct enetc_bdr *rx_ring, int i,
1479 				     u16 size, struct xdp_buff *xdp_buff)
1480 {
1481 	struct skb_shared_info *shinfo = xdp_get_shared_info_from_buff(xdp_buff);
1482 	struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size);
1483 	skb_frag_t *frag;
1484 
1485 	/* To be used for XDP_TX */
1486 	rx_swbd->len = size;
1487 
1488 	if (!xdp_buff_has_frags(xdp_buff)) {
1489 		xdp_buff_set_frags_flag(xdp_buff);
1490 		shinfo->xdp_frags_size = size;
1491 		shinfo->nr_frags = 0;
1492 	} else {
1493 		shinfo->xdp_frags_size += size;
1494 	}
1495 
1496 	if (page_is_pfmemalloc(rx_swbd->page))
1497 		xdp_buff_set_frag_pfmemalloc(xdp_buff);
1498 
1499 	frag = &shinfo->frags[shinfo->nr_frags];
1500 	skb_frag_fill_page_desc(frag, rx_swbd->page, rx_swbd->page_offset,
1501 				size);
1502 
1503 	shinfo->nr_frags++;
1504 }
1505 
enetc_build_xdp_buff(struct enetc_bdr * rx_ring,u32 bd_status,union enetc_rx_bd ** rxbd,int * i,int * cleaned_cnt,struct xdp_buff * xdp_buff)1506 static void enetc_build_xdp_buff(struct enetc_bdr *rx_ring, u32 bd_status,
1507 				 union enetc_rx_bd **rxbd, int *i,
1508 				 int *cleaned_cnt, struct xdp_buff *xdp_buff)
1509 {
1510 	u16 size = le16_to_cpu((*rxbd)->r.buf_len);
1511 
1512 	xdp_init_buff(xdp_buff, ENETC_RXB_TRUESIZE, &rx_ring->xdp.rxq);
1513 
1514 	enetc_map_rx_buff_to_xdp(rx_ring, *i, xdp_buff, size);
1515 	(*cleaned_cnt)++;
1516 	enetc_rxbd_next(rx_ring, rxbd, i);
1517 
1518 	/* not last BD in frame? */
1519 	while (!(bd_status & ENETC_RXBD_LSTATUS_F)) {
1520 		bd_status = le32_to_cpu((*rxbd)->r.lstatus);
1521 		size = ENETC_RXB_DMA_SIZE_XDP;
1522 
1523 		if (bd_status & ENETC_RXBD_LSTATUS_F) {
1524 			dma_rmb();
1525 			size = le16_to_cpu((*rxbd)->r.buf_len);
1526 		}
1527 
1528 		enetc_add_rx_buff_to_xdp(rx_ring, *i, size, xdp_buff);
1529 		(*cleaned_cnt)++;
1530 		enetc_rxbd_next(rx_ring, rxbd, i);
1531 	}
1532 }
1533 
1534 /* Convert RX buffer descriptors to TX buffer descriptors. These will be
1535  * recycled back into the RX ring in enetc_clean_tx_ring.
1536  */
enetc_rx_swbd_to_xdp_tx_swbd(struct enetc_tx_swbd * xdp_tx_arr,struct enetc_bdr * rx_ring,int rx_ring_first,int rx_ring_last)1537 static int enetc_rx_swbd_to_xdp_tx_swbd(struct enetc_tx_swbd *xdp_tx_arr,
1538 					struct enetc_bdr *rx_ring,
1539 					int rx_ring_first, int rx_ring_last)
1540 {
1541 	int n = 0;
1542 
1543 	for (; rx_ring_first != rx_ring_last;
1544 	     n++, enetc_bdr_idx_inc(rx_ring, &rx_ring_first)) {
1545 		struct enetc_rx_swbd *rx_swbd = &rx_ring->rx_swbd[rx_ring_first];
1546 		struct enetc_tx_swbd *tx_swbd = &xdp_tx_arr[n];
1547 
1548 		/* No need to dma_map, we already have DMA_BIDIRECTIONAL */
1549 		tx_swbd->dma = rx_swbd->dma;
1550 		tx_swbd->dir = rx_swbd->dir;
1551 		tx_swbd->page = rx_swbd->page;
1552 		tx_swbd->page_offset = rx_swbd->page_offset;
1553 		tx_swbd->len = rx_swbd->len;
1554 		tx_swbd->is_dma_page = true;
1555 		tx_swbd->is_xdp_tx = true;
1556 		tx_swbd->is_eof = false;
1557 	}
1558 
1559 	/* We rely on caller providing an rx_ring_last > rx_ring_first */
1560 	xdp_tx_arr[n - 1].is_eof = true;
1561 
1562 	return n;
1563 }
1564 
enetc_xdp_drop(struct enetc_bdr * rx_ring,int rx_ring_first,int rx_ring_last)1565 static void enetc_xdp_drop(struct enetc_bdr *rx_ring, int rx_ring_first,
1566 			   int rx_ring_last)
1567 {
1568 	while (rx_ring_first != rx_ring_last) {
1569 		enetc_put_rx_buff(rx_ring,
1570 				  &rx_ring->rx_swbd[rx_ring_first]);
1571 		enetc_bdr_idx_inc(rx_ring, &rx_ring_first);
1572 	}
1573 }
1574 
enetc_clean_rx_ring_xdp(struct enetc_bdr * rx_ring,struct napi_struct * napi,int work_limit,struct bpf_prog * prog)1575 static int enetc_clean_rx_ring_xdp(struct enetc_bdr *rx_ring,
1576 				   struct napi_struct *napi, int work_limit,
1577 				   struct bpf_prog *prog)
1578 {
1579 	int xdp_tx_bd_cnt, xdp_tx_frm_cnt = 0, xdp_redirect_frm_cnt = 0;
1580 	struct enetc_tx_swbd xdp_tx_arr[ENETC_MAX_SKB_FRAGS] = {0};
1581 	struct enetc_ndev_priv *priv = netdev_priv(rx_ring->ndev);
1582 	int rx_frm_cnt = 0, rx_byte_cnt = 0;
1583 	struct enetc_bdr *tx_ring;
1584 	int cleaned_cnt, i;
1585 	u32 xdp_act;
1586 
1587 	cleaned_cnt = enetc_bd_unused(rx_ring);
1588 	/* next descriptor to process */
1589 	i = rx_ring->next_to_clean;
1590 
1591 	while (likely(rx_frm_cnt < work_limit)) {
1592 		union enetc_rx_bd *rxbd, *orig_rxbd;
1593 		int orig_i, orig_cleaned_cnt;
1594 		struct xdp_buff xdp_buff;
1595 		struct sk_buff *skb;
1596 		u32 bd_status;
1597 		int err;
1598 
1599 		rxbd = enetc_rxbd(rx_ring, i);
1600 		bd_status = le32_to_cpu(rxbd->r.lstatus);
1601 		if (!bd_status)
1602 			break;
1603 
1604 		enetc_wr_reg_hot(rx_ring->idr, BIT(rx_ring->index));
1605 		dma_rmb(); /* for reading other rxbd fields */
1606 
1607 		if (enetc_check_bd_errors_and_consume(rx_ring, bd_status,
1608 						      &rxbd, &i))
1609 			break;
1610 
1611 		orig_rxbd = rxbd;
1612 		orig_cleaned_cnt = cleaned_cnt;
1613 		orig_i = i;
1614 
1615 		enetc_build_xdp_buff(rx_ring, bd_status, &rxbd, &i,
1616 				     &cleaned_cnt, &xdp_buff);
1617 
1618 		/* When set, the outer VLAN header is extracted and reported
1619 		 * in the receive buffer descriptor. So rx_byte_cnt should
1620 		 * add the length of the extracted VLAN header.
1621 		 */
1622 		if (bd_status & ENETC_RXBD_FLAG_VLAN)
1623 			rx_byte_cnt += VLAN_HLEN;
1624 		rx_byte_cnt += xdp_get_buff_len(&xdp_buff);
1625 
1626 		xdp_act = bpf_prog_run_xdp(prog, &xdp_buff);
1627 
1628 		switch (xdp_act) {
1629 		default:
1630 			bpf_warn_invalid_xdp_action(rx_ring->ndev, prog, xdp_act);
1631 			fallthrough;
1632 		case XDP_ABORTED:
1633 			trace_xdp_exception(rx_ring->ndev, prog, xdp_act);
1634 			fallthrough;
1635 		case XDP_DROP:
1636 			enetc_xdp_drop(rx_ring, orig_i, i);
1637 			rx_ring->stats.xdp_drops++;
1638 			break;
1639 		case XDP_PASS:
1640 			rxbd = orig_rxbd;
1641 			cleaned_cnt = orig_cleaned_cnt;
1642 			i = orig_i;
1643 
1644 			skb = enetc_build_skb(rx_ring, bd_status, &rxbd,
1645 					      &i, &cleaned_cnt,
1646 					      ENETC_RXB_DMA_SIZE_XDP);
1647 			if (unlikely(!skb))
1648 				goto out;
1649 
1650 			napi_gro_receive(napi, skb);
1651 			break;
1652 		case XDP_TX:
1653 			tx_ring = priv->xdp_tx_ring[rx_ring->index];
1654 			if (unlikely(test_bit(ENETC_TX_DOWN, &priv->flags))) {
1655 				enetc_xdp_drop(rx_ring, orig_i, i);
1656 				tx_ring->stats.xdp_tx_drops++;
1657 				break;
1658 			}
1659 
1660 			xdp_tx_bd_cnt = enetc_rx_swbd_to_xdp_tx_swbd(xdp_tx_arr,
1661 								     rx_ring,
1662 								     orig_i, i);
1663 
1664 			if (!enetc_xdp_tx(tx_ring, xdp_tx_arr, xdp_tx_bd_cnt)) {
1665 				enetc_xdp_drop(rx_ring, orig_i, i);
1666 				tx_ring->stats.xdp_tx_drops++;
1667 			} else {
1668 				tx_ring->stats.xdp_tx++;
1669 				rx_ring->xdp.xdp_tx_in_flight += xdp_tx_bd_cnt;
1670 				xdp_tx_frm_cnt++;
1671 				/* The XDP_TX enqueue was successful, so we
1672 				 * need to scrub the RX software BDs because
1673 				 * the ownership of the buffers no longer
1674 				 * belongs to the RX ring, and we must prevent
1675 				 * enetc_refill_rx_ring() from reusing
1676 				 * rx_swbd->page.
1677 				 */
1678 				while (orig_i != i) {
1679 					rx_ring->rx_swbd[orig_i].page = NULL;
1680 					enetc_bdr_idx_inc(rx_ring, &orig_i);
1681 				}
1682 			}
1683 			break;
1684 		case XDP_REDIRECT:
1685 			err = xdp_do_redirect(rx_ring->ndev, &xdp_buff, prog);
1686 			if (unlikely(err)) {
1687 				enetc_xdp_drop(rx_ring, orig_i, i);
1688 				rx_ring->stats.xdp_redirect_failures++;
1689 			} else {
1690 				while (orig_i != i) {
1691 					enetc_flip_rx_buff(rx_ring,
1692 							   &rx_ring->rx_swbd[orig_i]);
1693 					enetc_bdr_idx_inc(rx_ring, &orig_i);
1694 				}
1695 				xdp_redirect_frm_cnt++;
1696 				rx_ring->stats.xdp_redirect++;
1697 			}
1698 		}
1699 
1700 		rx_frm_cnt++;
1701 	}
1702 
1703 out:
1704 	rx_ring->next_to_clean = i;
1705 
1706 	rx_ring->stats.packets += rx_frm_cnt;
1707 	rx_ring->stats.bytes += rx_byte_cnt;
1708 
1709 	if (xdp_redirect_frm_cnt)
1710 		xdp_do_flush_map();
1711 
1712 	if (xdp_tx_frm_cnt)
1713 		enetc_update_tx_ring_tail(tx_ring);
1714 
1715 	if (cleaned_cnt > rx_ring->xdp.xdp_tx_in_flight)
1716 		enetc_refill_rx_ring(rx_ring, enetc_bd_unused(rx_ring) -
1717 				     rx_ring->xdp.xdp_tx_in_flight);
1718 
1719 	return rx_frm_cnt;
1720 }
1721 
enetc_poll(struct napi_struct * napi,int budget)1722 static int enetc_poll(struct napi_struct *napi, int budget)
1723 {
1724 	struct enetc_int_vector
1725 		*v = container_of(napi, struct enetc_int_vector, napi);
1726 	struct enetc_bdr *rx_ring = &v->rx_ring;
1727 	struct bpf_prog *prog;
1728 	bool complete = true;
1729 	int work_done;
1730 	int i;
1731 
1732 	enetc_lock_mdio();
1733 
1734 	for (i = 0; i < v->count_tx_rings; i++)
1735 		if (!enetc_clean_tx_ring(&v->tx_ring[i], budget))
1736 			complete = false;
1737 
1738 	prog = rx_ring->xdp.prog;
1739 	if (prog)
1740 		work_done = enetc_clean_rx_ring_xdp(rx_ring, napi, budget, prog);
1741 	else
1742 		work_done = enetc_clean_rx_ring(rx_ring, napi, budget);
1743 	if (work_done == budget)
1744 		complete = false;
1745 	if (work_done)
1746 		v->rx_napi_work = true;
1747 
1748 	if (!complete) {
1749 		enetc_unlock_mdio();
1750 		return budget;
1751 	}
1752 
1753 	napi_complete_done(napi, work_done);
1754 
1755 	if (likely(v->rx_dim_en))
1756 		enetc_rx_net_dim(v);
1757 
1758 	v->rx_napi_work = false;
1759 
1760 	/* enable interrupts */
1761 	enetc_wr_reg_hot(v->rbier, ENETC_RBIER_RXTIE);
1762 
1763 	for_each_set_bit(i, &v->tx_rings_map, ENETC_MAX_NUM_TXQS)
1764 		enetc_wr_reg_hot(v->tbier_base + ENETC_BDR_OFF(i),
1765 				 ENETC_TBIER_TXTIE);
1766 
1767 	enetc_unlock_mdio();
1768 
1769 	return work_done;
1770 }
1771 
1772 /* Probing and Init */
1773 #define ENETC_MAX_RFS_SIZE 64
enetc_get_si_caps(struct enetc_si * si)1774 void enetc_get_si_caps(struct enetc_si *si)
1775 {
1776 	struct enetc_hw *hw = &si->hw;
1777 	u32 val;
1778 
1779 	/* find out how many of various resources we have to work with */
1780 	val = enetc_rd(hw, ENETC_SICAPR0);
1781 	si->num_rx_rings = (val >> 16) & 0xff;
1782 	si->num_tx_rings = val & 0xff;
1783 
1784 	val = enetc_rd(hw, ENETC_SIRFSCAPR);
1785 	si->num_fs_entries = ENETC_SIRFSCAPR_GET_NUM_RFS(val);
1786 	si->num_fs_entries = min(si->num_fs_entries, ENETC_MAX_RFS_SIZE);
1787 
1788 	si->num_rss = 0;
1789 	val = enetc_rd(hw, ENETC_SIPCAPR0);
1790 	if (val & ENETC_SIPCAPR0_RSS) {
1791 		u32 rss;
1792 
1793 		rss = enetc_rd(hw, ENETC_SIRSSCAPR);
1794 		si->num_rss = ENETC_SIRSSCAPR_GET_NUM_RSS(rss);
1795 	}
1796 
1797 	if (val & ENETC_SIPCAPR0_QBV)
1798 		si->hw_features |= ENETC_SI_F_QBV;
1799 
1800 	if (val & ENETC_SIPCAPR0_QBU)
1801 		si->hw_features |= ENETC_SI_F_QBU;
1802 
1803 	if (val & ENETC_SIPCAPR0_PSFP)
1804 		si->hw_features |= ENETC_SI_F_PSFP;
1805 }
1806 EXPORT_SYMBOL_GPL(enetc_get_si_caps);
1807 
enetc_dma_alloc_bdr(struct enetc_bdr_resource * res)1808 static int enetc_dma_alloc_bdr(struct enetc_bdr_resource *res)
1809 {
1810 	size_t bd_base_size = res->bd_count * res->bd_size;
1811 
1812 	res->bd_base = dma_alloc_coherent(res->dev, bd_base_size,
1813 					  &res->bd_dma_base, GFP_KERNEL);
1814 	if (!res->bd_base)
1815 		return -ENOMEM;
1816 
1817 	/* h/w requires 128B alignment */
1818 	if (!IS_ALIGNED(res->bd_dma_base, 128)) {
1819 		dma_free_coherent(res->dev, bd_base_size, res->bd_base,
1820 				  res->bd_dma_base);
1821 		return -EINVAL;
1822 	}
1823 
1824 	return 0;
1825 }
1826 
enetc_dma_free_bdr(const struct enetc_bdr_resource * res)1827 static void enetc_dma_free_bdr(const struct enetc_bdr_resource *res)
1828 {
1829 	size_t bd_base_size = res->bd_count * res->bd_size;
1830 
1831 	dma_free_coherent(res->dev, bd_base_size, res->bd_base,
1832 			  res->bd_dma_base);
1833 }
1834 
enetc_alloc_tx_resource(struct enetc_bdr_resource * res,struct device * dev,size_t bd_count)1835 static int enetc_alloc_tx_resource(struct enetc_bdr_resource *res,
1836 				   struct device *dev, size_t bd_count)
1837 {
1838 	int err;
1839 
1840 	res->dev = dev;
1841 	res->bd_count = bd_count;
1842 	res->bd_size = sizeof(union enetc_tx_bd);
1843 
1844 	res->tx_swbd = vcalloc(bd_count, sizeof(*res->tx_swbd));
1845 	if (!res->tx_swbd)
1846 		return -ENOMEM;
1847 
1848 	err = enetc_dma_alloc_bdr(res);
1849 	if (err)
1850 		goto err_alloc_bdr;
1851 
1852 	res->tso_headers = dma_alloc_coherent(dev, bd_count * TSO_HEADER_SIZE,
1853 					      &res->tso_headers_dma,
1854 					      GFP_KERNEL);
1855 	if (!res->tso_headers) {
1856 		err = -ENOMEM;
1857 		goto err_alloc_tso;
1858 	}
1859 
1860 	return 0;
1861 
1862 err_alloc_tso:
1863 	enetc_dma_free_bdr(res);
1864 err_alloc_bdr:
1865 	vfree(res->tx_swbd);
1866 	res->tx_swbd = NULL;
1867 
1868 	return err;
1869 }
1870 
enetc_free_tx_resource(const struct enetc_bdr_resource * res)1871 static void enetc_free_tx_resource(const struct enetc_bdr_resource *res)
1872 {
1873 	dma_free_coherent(res->dev, res->bd_count * TSO_HEADER_SIZE,
1874 			  res->tso_headers, res->tso_headers_dma);
1875 	enetc_dma_free_bdr(res);
1876 	vfree(res->tx_swbd);
1877 }
1878 
1879 static struct enetc_bdr_resource *
enetc_alloc_tx_resources(struct enetc_ndev_priv * priv)1880 enetc_alloc_tx_resources(struct enetc_ndev_priv *priv)
1881 {
1882 	struct enetc_bdr_resource *tx_res;
1883 	int i, err;
1884 
1885 	tx_res = kcalloc(priv->num_tx_rings, sizeof(*tx_res), GFP_KERNEL);
1886 	if (!tx_res)
1887 		return ERR_PTR(-ENOMEM);
1888 
1889 	for (i = 0; i < priv->num_tx_rings; i++) {
1890 		struct enetc_bdr *tx_ring = priv->tx_ring[i];
1891 
1892 		err = enetc_alloc_tx_resource(&tx_res[i], tx_ring->dev,
1893 					      tx_ring->bd_count);
1894 		if (err)
1895 			goto fail;
1896 	}
1897 
1898 	return tx_res;
1899 
1900 fail:
1901 	while (i-- > 0)
1902 		enetc_free_tx_resource(&tx_res[i]);
1903 
1904 	kfree(tx_res);
1905 
1906 	return ERR_PTR(err);
1907 }
1908 
enetc_free_tx_resources(const struct enetc_bdr_resource * tx_res,size_t num_resources)1909 static void enetc_free_tx_resources(const struct enetc_bdr_resource *tx_res,
1910 				    size_t num_resources)
1911 {
1912 	size_t i;
1913 
1914 	for (i = 0; i < num_resources; i++)
1915 		enetc_free_tx_resource(&tx_res[i]);
1916 
1917 	kfree(tx_res);
1918 }
1919 
enetc_alloc_rx_resource(struct enetc_bdr_resource * res,struct device * dev,size_t bd_count,bool extended)1920 static int enetc_alloc_rx_resource(struct enetc_bdr_resource *res,
1921 				   struct device *dev, size_t bd_count,
1922 				   bool extended)
1923 {
1924 	int err;
1925 
1926 	res->dev = dev;
1927 	res->bd_count = bd_count;
1928 	res->bd_size = sizeof(union enetc_rx_bd);
1929 	if (extended)
1930 		res->bd_size *= 2;
1931 
1932 	res->rx_swbd = vcalloc(bd_count, sizeof(struct enetc_rx_swbd));
1933 	if (!res->rx_swbd)
1934 		return -ENOMEM;
1935 
1936 	err = enetc_dma_alloc_bdr(res);
1937 	if (err) {
1938 		vfree(res->rx_swbd);
1939 		return err;
1940 	}
1941 
1942 	return 0;
1943 }
1944 
enetc_free_rx_resource(const struct enetc_bdr_resource * res)1945 static void enetc_free_rx_resource(const struct enetc_bdr_resource *res)
1946 {
1947 	enetc_dma_free_bdr(res);
1948 	vfree(res->rx_swbd);
1949 }
1950 
1951 static struct enetc_bdr_resource *
enetc_alloc_rx_resources(struct enetc_ndev_priv * priv,bool extended)1952 enetc_alloc_rx_resources(struct enetc_ndev_priv *priv, bool extended)
1953 {
1954 	struct enetc_bdr_resource *rx_res;
1955 	int i, err;
1956 
1957 	rx_res = kcalloc(priv->num_rx_rings, sizeof(*rx_res), GFP_KERNEL);
1958 	if (!rx_res)
1959 		return ERR_PTR(-ENOMEM);
1960 
1961 	for (i = 0; i < priv->num_rx_rings; i++) {
1962 		struct enetc_bdr *rx_ring = priv->rx_ring[i];
1963 
1964 		err = enetc_alloc_rx_resource(&rx_res[i], rx_ring->dev,
1965 					      rx_ring->bd_count, extended);
1966 		if (err)
1967 			goto fail;
1968 	}
1969 
1970 	return rx_res;
1971 
1972 fail:
1973 	while (i-- > 0)
1974 		enetc_free_rx_resource(&rx_res[i]);
1975 
1976 	kfree(rx_res);
1977 
1978 	return ERR_PTR(err);
1979 }
1980 
enetc_free_rx_resources(const struct enetc_bdr_resource * rx_res,size_t num_resources)1981 static void enetc_free_rx_resources(const struct enetc_bdr_resource *rx_res,
1982 				    size_t num_resources)
1983 {
1984 	size_t i;
1985 
1986 	for (i = 0; i < num_resources; i++)
1987 		enetc_free_rx_resource(&rx_res[i]);
1988 
1989 	kfree(rx_res);
1990 }
1991 
enetc_assign_tx_resource(struct enetc_bdr * tx_ring,const struct enetc_bdr_resource * res)1992 static void enetc_assign_tx_resource(struct enetc_bdr *tx_ring,
1993 				     const struct enetc_bdr_resource *res)
1994 {
1995 	tx_ring->bd_base = res ? res->bd_base : NULL;
1996 	tx_ring->bd_dma_base = res ? res->bd_dma_base : 0;
1997 	tx_ring->tx_swbd = res ? res->tx_swbd : NULL;
1998 	tx_ring->tso_headers = res ? res->tso_headers : NULL;
1999 	tx_ring->tso_headers_dma = res ? res->tso_headers_dma : 0;
2000 }
2001 
enetc_assign_rx_resource(struct enetc_bdr * rx_ring,const struct enetc_bdr_resource * res)2002 static void enetc_assign_rx_resource(struct enetc_bdr *rx_ring,
2003 				     const struct enetc_bdr_resource *res)
2004 {
2005 	rx_ring->bd_base = res ? res->bd_base : NULL;
2006 	rx_ring->bd_dma_base = res ? res->bd_dma_base : 0;
2007 	rx_ring->rx_swbd = res ? res->rx_swbd : NULL;
2008 }
2009 
enetc_assign_tx_resources(struct enetc_ndev_priv * priv,const struct enetc_bdr_resource * res)2010 static void enetc_assign_tx_resources(struct enetc_ndev_priv *priv,
2011 				      const struct enetc_bdr_resource *res)
2012 {
2013 	int i;
2014 
2015 	if (priv->tx_res)
2016 		enetc_free_tx_resources(priv->tx_res, priv->num_tx_rings);
2017 
2018 	for (i = 0; i < priv->num_tx_rings; i++) {
2019 		enetc_assign_tx_resource(priv->tx_ring[i],
2020 					 res ? &res[i] : NULL);
2021 	}
2022 
2023 	priv->tx_res = res;
2024 }
2025 
enetc_assign_rx_resources(struct enetc_ndev_priv * priv,const struct enetc_bdr_resource * res)2026 static void enetc_assign_rx_resources(struct enetc_ndev_priv *priv,
2027 				      const struct enetc_bdr_resource *res)
2028 {
2029 	int i;
2030 
2031 	if (priv->rx_res)
2032 		enetc_free_rx_resources(priv->rx_res, priv->num_rx_rings);
2033 
2034 	for (i = 0; i < priv->num_rx_rings; i++) {
2035 		enetc_assign_rx_resource(priv->rx_ring[i],
2036 					 res ? &res[i] : NULL);
2037 	}
2038 
2039 	priv->rx_res = res;
2040 }
2041 
enetc_free_tx_ring(struct enetc_bdr * tx_ring)2042 static void enetc_free_tx_ring(struct enetc_bdr *tx_ring)
2043 {
2044 	int i;
2045 
2046 	for (i = 0; i < tx_ring->bd_count; i++) {
2047 		struct enetc_tx_swbd *tx_swbd = &tx_ring->tx_swbd[i];
2048 
2049 		enetc_free_tx_frame(tx_ring, tx_swbd);
2050 	}
2051 }
2052 
enetc_free_rx_ring(struct enetc_bdr * rx_ring)2053 static void enetc_free_rx_ring(struct enetc_bdr *rx_ring)
2054 {
2055 	int i;
2056 
2057 	for (i = 0; i < rx_ring->bd_count; i++) {
2058 		struct enetc_rx_swbd *rx_swbd = &rx_ring->rx_swbd[i];
2059 
2060 		if (!rx_swbd->page)
2061 			continue;
2062 
2063 		dma_unmap_page(rx_ring->dev, rx_swbd->dma, PAGE_SIZE,
2064 			       rx_swbd->dir);
2065 		__free_page(rx_swbd->page);
2066 		rx_swbd->page = NULL;
2067 	}
2068 }
2069 
enetc_free_rxtx_rings(struct enetc_ndev_priv * priv)2070 static void enetc_free_rxtx_rings(struct enetc_ndev_priv *priv)
2071 {
2072 	int i;
2073 
2074 	for (i = 0; i < priv->num_rx_rings; i++)
2075 		enetc_free_rx_ring(priv->rx_ring[i]);
2076 
2077 	for (i = 0; i < priv->num_tx_rings; i++)
2078 		enetc_free_tx_ring(priv->tx_ring[i]);
2079 }
2080 
enetc_setup_default_rss_table(struct enetc_si * si,int num_groups)2081 static int enetc_setup_default_rss_table(struct enetc_si *si, int num_groups)
2082 {
2083 	int *rss_table;
2084 	int i;
2085 
2086 	rss_table = kmalloc_array(si->num_rss, sizeof(*rss_table), GFP_KERNEL);
2087 	if (!rss_table)
2088 		return -ENOMEM;
2089 
2090 	/* Set up RSS table defaults */
2091 	for (i = 0; i < si->num_rss; i++)
2092 		rss_table[i] = i % num_groups;
2093 
2094 	enetc_set_rss_table(si, rss_table, si->num_rss);
2095 
2096 	kfree(rss_table);
2097 
2098 	return 0;
2099 }
2100 
enetc_configure_si(struct enetc_ndev_priv * priv)2101 int enetc_configure_si(struct enetc_ndev_priv *priv)
2102 {
2103 	struct enetc_si *si = priv->si;
2104 	struct enetc_hw *hw = &si->hw;
2105 	int err;
2106 
2107 	/* set SI cache attributes */
2108 	enetc_wr(hw, ENETC_SICAR0,
2109 		 ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT);
2110 	enetc_wr(hw, ENETC_SICAR1, ENETC_SICAR_MSI);
2111 	/* enable SI */
2112 	enetc_wr(hw, ENETC_SIMR, ENETC_SIMR_EN);
2113 
2114 	if (si->num_rss) {
2115 		err = enetc_setup_default_rss_table(si, priv->num_rx_rings);
2116 		if (err)
2117 			return err;
2118 	}
2119 
2120 	return 0;
2121 }
2122 EXPORT_SYMBOL_GPL(enetc_configure_si);
2123 
enetc_init_si_rings_params(struct enetc_ndev_priv * priv)2124 void enetc_init_si_rings_params(struct enetc_ndev_priv *priv)
2125 {
2126 	struct enetc_si *si = priv->si;
2127 	int cpus = num_online_cpus();
2128 
2129 	priv->tx_bd_count = ENETC_TX_RING_DEFAULT_SIZE;
2130 	priv->rx_bd_count = ENETC_RX_RING_DEFAULT_SIZE;
2131 
2132 	/* Enable all available TX rings in order to configure as many
2133 	 * priorities as possible, when needed.
2134 	 * TODO: Make # of TX rings run-time configurable
2135 	 */
2136 	priv->num_rx_rings = min_t(int, cpus, si->num_rx_rings);
2137 	priv->num_tx_rings = si->num_tx_rings;
2138 	priv->bdr_int_num = cpus;
2139 	priv->ic_mode = ENETC_IC_RX_ADAPTIVE | ENETC_IC_TX_MANUAL;
2140 	priv->tx_ictt = ENETC_TXIC_TIMETHR;
2141 }
2142 EXPORT_SYMBOL_GPL(enetc_init_si_rings_params);
2143 
enetc_alloc_si_resources(struct enetc_ndev_priv * priv)2144 int enetc_alloc_si_resources(struct enetc_ndev_priv *priv)
2145 {
2146 	struct enetc_si *si = priv->si;
2147 
2148 	priv->cls_rules = kcalloc(si->num_fs_entries, sizeof(*priv->cls_rules),
2149 				  GFP_KERNEL);
2150 	if (!priv->cls_rules)
2151 		return -ENOMEM;
2152 
2153 	return 0;
2154 }
2155 EXPORT_SYMBOL_GPL(enetc_alloc_si_resources);
2156 
enetc_free_si_resources(struct enetc_ndev_priv * priv)2157 void enetc_free_si_resources(struct enetc_ndev_priv *priv)
2158 {
2159 	kfree(priv->cls_rules);
2160 }
2161 EXPORT_SYMBOL_GPL(enetc_free_si_resources);
2162 
enetc_setup_txbdr(struct enetc_hw * hw,struct enetc_bdr * tx_ring)2163 static void enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring)
2164 {
2165 	int idx = tx_ring->index;
2166 	u32 tbmr;
2167 
2168 	enetc_txbdr_wr(hw, idx, ENETC_TBBAR0,
2169 		       lower_32_bits(tx_ring->bd_dma_base));
2170 
2171 	enetc_txbdr_wr(hw, idx, ENETC_TBBAR1,
2172 		       upper_32_bits(tx_ring->bd_dma_base));
2173 
2174 	WARN_ON(!IS_ALIGNED(tx_ring->bd_count, 64)); /* multiple of 64 */
2175 	enetc_txbdr_wr(hw, idx, ENETC_TBLENR,
2176 		       ENETC_RTBLENR_LEN(tx_ring->bd_count));
2177 
2178 	/* clearing PI/CI registers for Tx not supported, adjust sw indexes */
2179 	tx_ring->next_to_use = enetc_txbdr_rd(hw, idx, ENETC_TBPIR);
2180 	tx_ring->next_to_clean = enetc_txbdr_rd(hw, idx, ENETC_TBCIR);
2181 
2182 	/* enable Tx ints by setting pkt thr to 1 */
2183 	enetc_txbdr_wr(hw, idx, ENETC_TBICR0, ENETC_TBICR0_ICEN | 0x1);
2184 
2185 	tbmr = ENETC_TBMR_SET_PRIO(tx_ring->prio);
2186 	if (tx_ring->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
2187 		tbmr |= ENETC_TBMR_VIH;
2188 
2189 	/* enable ring */
2190 	enetc_txbdr_wr(hw, idx, ENETC_TBMR, tbmr);
2191 
2192 	tx_ring->tpir = hw->reg + ENETC_BDR(TX, idx, ENETC_TBPIR);
2193 	tx_ring->tcir = hw->reg + ENETC_BDR(TX, idx, ENETC_TBCIR);
2194 	tx_ring->idr = hw->reg + ENETC_SITXIDR;
2195 }
2196 
enetc_setup_rxbdr(struct enetc_hw * hw,struct enetc_bdr * rx_ring,bool extended)2197 static void enetc_setup_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring,
2198 			      bool extended)
2199 {
2200 	int idx = rx_ring->index;
2201 	u32 rbmr = 0;
2202 
2203 	enetc_rxbdr_wr(hw, idx, ENETC_RBBAR0,
2204 		       lower_32_bits(rx_ring->bd_dma_base));
2205 
2206 	enetc_rxbdr_wr(hw, idx, ENETC_RBBAR1,
2207 		       upper_32_bits(rx_ring->bd_dma_base));
2208 
2209 	WARN_ON(!IS_ALIGNED(rx_ring->bd_count, 64)); /* multiple of 64 */
2210 	enetc_rxbdr_wr(hw, idx, ENETC_RBLENR,
2211 		       ENETC_RTBLENR_LEN(rx_ring->bd_count));
2212 
2213 	if (rx_ring->xdp.prog)
2214 		enetc_rxbdr_wr(hw, idx, ENETC_RBBSR, ENETC_RXB_DMA_SIZE_XDP);
2215 	else
2216 		enetc_rxbdr_wr(hw, idx, ENETC_RBBSR, ENETC_RXB_DMA_SIZE);
2217 
2218 	/* Also prepare the consumer index in case page allocation never
2219 	 * succeeds. In that case, hardware will never advance producer index
2220 	 * to match consumer index, and will drop all frames.
2221 	 */
2222 	enetc_rxbdr_wr(hw, idx, ENETC_RBPIR, 0);
2223 	enetc_rxbdr_wr(hw, idx, ENETC_RBCIR, 1);
2224 
2225 	/* enable Rx ints by setting pkt thr to 1 */
2226 	enetc_rxbdr_wr(hw, idx, ENETC_RBICR0, ENETC_RBICR0_ICEN | 0x1);
2227 
2228 	rx_ring->ext_en = extended;
2229 	if (rx_ring->ext_en)
2230 		rbmr |= ENETC_RBMR_BDS;
2231 
2232 	if (rx_ring->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
2233 		rbmr |= ENETC_RBMR_VTE;
2234 
2235 	rx_ring->rcir = hw->reg + ENETC_BDR(RX, idx, ENETC_RBCIR);
2236 	rx_ring->idr = hw->reg + ENETC_SIRXIDR;
2237 
2238 	rx_ring->next_to_clean = 0;
2239 	rx_ring->next_to_use = 0;
2240 	rx_ring->next_to_alloc = 0;
2241 
2242 	enetc_lock_mdio();
2243 	enetc_refill_rx_ring(rx_ring, enetc_bd_unused(rx_ring));
2244 	enetc_unlock_mdio();
2245 
2246 	enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr);
2247 }
2248 
enetc_setup_bdrs(struct enetc_ndev_priv * priv,bool extended)2249 static void enetc_setup_bdrs(struct enetc_ndev_priv *priv, bool extended)
2250 {
2251 	struct enetc_hw *hw = &priv->si->hw;
2252 	int i;
2253 
2254 	for (i = 0; i < priv->num_tx_rings; i++)
2255 		enetc_setup_txbdr(hw, priv->tx_ring[i]);
2256 
2257 	for (i = 0; i < priv->num_rx_rings; i++)
2258 		enetc_setup_rxbdr(hw, priv->rx_ring[i], extended);
2259 }
2260 
enetc_enable_txbdr(struct enetc_hw * hw,struct enetc_bdr * tx_ring)2261 static void enetc_enable_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring)
2262 {
2263 	int idx = tx_ring->index;
2264 	u32 tbmr;
2265 
2266 	tbmr = enetc_txbdr_rd(hw, idx, ENETC_TBMR);
2267 	tbmr |= ENETC_TBMR_EN;
2268 	enetc_txbdr_wr(hw, idx, ENETC_TBMR, tbmr);
2269 }
2270 
enetc_enable_rxbdr(struct enetc_hw * hw,struct enetc_bdr * rx_ring)2271 static void enetc_enable_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring)
2272 {
2273 	int idx = rx_ring->index;
2274 	u32 rbmr;
2275 
2276 	rbmr = enetc_rxbdr_rd(hw, idx, ENETC_RBMR);
2277 	rbmr |= ENETC_RBMR_EN;
2278 	enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr);
2279 }
2280 
enetc_enable_rx_bdrs(struct enetc_ndev_priv * priv)2281 static void enetc_enable_rx_bdrs(struct enetc_ndev_priv *priv)
2282 {
2283 	struct enetc_hw *hw = &priv->si->hw;
2284 	int i;
2285 
2286 	for (i = 0; i < priv->num_rx_rings; i++)
2287 		enetc_enable_rxbdr(hw, priv->rx_ring[i]);
2288 }
2289 
enetc_enable_tx_bdrs(struct enetc_ndev_priv * priv)2290 static void enetc_enable_tx_bdrs(struct enetc_ndev_priv *priv)
2291 {
2292 	struct enetc_hw *hw = &priv->si->hw;
2293 	int i;
2294 
2295 	for (i = 0; i < priv->num_tx_rings; i++)
2296 		enetc_enable_txbdr(hw, priv->tx_ring[i]);
2297 }
2298 
enetc_disable_rxbdr(struct enetc_hw * hw,struct enetc_bdr * rx_ring)2299 static void enetc_disable_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring)
2300 {
2301 	int idx = rx_ring->index;
2302 
2303 	/* disable EN bit on ring */
2304 	enetc_rxbdr_wr(hw, idx, ENETC_RBMR, 0);
2305 }
2306 
enetc_disable_txbdr(struct enetc_hw * hw,struct enetc_bdr * rx_ring)2307 static void enetc_disable_txbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring)
2308 {
2309 	int idx = rx_ring->index;
2310 
2311 	/* disable EN bit on ring */
2312 	enetc_txbdr_wr(hw, idx, ENETC_TBMR, 0);
2313 }
2314 
enetc_disable_rx_bdrs(struct enetc_ndev_priv * priv)2315 static void enetc_disable_rx_bdrs(struct enetc_ndev_priv *priv)
2316 {
2317 	struct enetc_hw *hw = &priv->si->hw;
2318 	int i;
2319 
2320 	for (i = 0; i < priv->num_rx_rings; i++)
2321 		enetc_disable_rxbdr(hw, priv->rx_ring[i]);
2322 }
2323 
enetc_disable_tx_bdrs(struct enetc_ndev_priv * priv)2324 static void enetc_disable_tx_bdrs(struct enetc_ndev_priv *priv)
2325 {
2326 	struct enetc_hw *hw = &priv->si->hw;
2327 	int i;
2328 
2329 	for (i = 0; i < priv->num_tx_rings; i++)
2330 		enetc_disable_txbdr(hw, priv->tx_ring[i]);
2331 }
2332 
enetc_wait_txbdr(struct enetc_hw * hw,struct enetc_bdr * tx_ring)2333 static void enetc_wait_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring)
2334 {
2335 	int delay = 8, timeout = 100;
2336 	int idx = tx_ring->index;
2337 
2338 	/* wait for busy to clear */
2339 	while (delay < timeout &&
2340 	       enetc_txbdr_rd(hw, idx, ENETC_TBSR) & ENETC_TBSR_BUSY) {
2341 		msleep(delay);
2342 		delay *= 2;
2343 	}
2344 
2345 	if (delay >= timeout)
2346 		netdev_warn(tx_ring->ndev, "timeout for tx ring #%d clear\n",
2347 			    idx);
2348 }
2349 
enetc_wait_bdrs(struct enetc_ndev_priv * priv)2350 static void enetc_wait_bdrs(struct enetc_ndev_priv *priv)
2351 {
2352 	struct enetc_hw *hw = &priv->si->hw;
2353 	int i;
2354 
2355 	for (i = 0; i < priv->num_tx_rings; i++)
2356 		enetc_wait_txbdr(hw, priv->tx_ring[i]);
2357 }
2358 
enetc_setup_irqs(struct enetc_ndev_priv * priv)2359 static int enetc_setup_irqs(struct enetc_ndev_priv *priv)
2360 {
2361 	struct pci_dev *pdev = priv->si->pdev;
2362 	struct enetc_hw *hw = &priv->si->hw;
2363 	int i, j, err;
2364 
2365 	for (i = 0; i < priv->bdr_int_num; i++) {
2366 		int irq = pci_irq_vector(pdev, ENETC_BDR_INT_BASE_IDX + i);
2367 		struct enetc_int_vector *v = priv->int_vector[i];
2368 		int entry = ENETC_BDR_INT_BASE_IDX + i;
2369 
2370 		snprintf(v->name, sizeof(v->name), "%s-rxtx%d",
2371 			 priv->ndev->name, i);
2372 		err = request_irq(irq, enetc_msix, IRQF_NO_AUTOEN, v->name, v);
2373 		if (err) {
2374 			dev_err(priv->dev, "request_irq() failed!\n");
2375 			goto irq_err;
2376 		}
2377 
2378 		v->tbier_base = hw->reg + ENETC_BDR(TX, 0, ENETC_TBIER);
2379 		v->rbier = hw->reg + ENETC_BDR(RX, i, ENETC_RBIER);
2380 		v->ricr1 = hw->reg + ENETC_BDR(RX, i, ENETC_RBICR1);
2381 
2382 		enetc_wr(hw, ENETC_SIMSIRRV(i), entry);
2383 
2384 		for (j = 0; j < v->count_tx_rings; j++) {
2385 			int idx = v->tx_ring[j].index;
2386 
2387 			enetc_wr(hw, ENETC_SIMSITRV(idx), entry);
2388 		}
2389 		irq_set_affinity_hint(irq, get_cpu_mask(i % num_online_cpus()));
2390 	}
2391 
2392 	return 0;
2393 
2394 irq_err:
2395 	while (i--) {
2396 		int irq = pci_irq_vector(pdev, ENETC_BDR_INT_BASE_IDX + i);
2397 
2398 		irq_set_affinity_hint(irq, NULL);
2399 		free_irq(irq, priv->int_vector[i]);
2400 	}
2401 
2402 	return err;
2403 }
2404 
enetc_free_irqs(struct enetc_ndev_priv * priv)2405 static void enetc_free_irqs(struct enetc_ndev_priv *priv)
2406 {
2407 	struct pci_dev *pdev = priv->si->pdev;
2408 	int i;
2409 
2410 	for (i = 0; i < priv->bdr_int_num; i++) {
2411 		int irq = pci_irq_vector(pdev, ENETC_BDR_INT_BASE_IDX + i);
2412 
2413 		irq_set_affinity_hint(irq, NULL);
2414 		free_irq(irq, priv->int_vector[i]);
2415 	}
2416 }
2417 
enetc_setup_interrupts(struct enetc_ndev_priv * priv)2418 static void enetc_setup_interrupts(struct enetc_ndev_priv *priv)
2419 {
2420 	struct enetc_hw *hw = &priv->si->hw;
2421 	u32 icpt, ictt;
2422 	int i;
2423 
2424 	/* enable Tx & Rx event indication */
2425 	if (priv->ic_mode &
2426 	    (ENETC_IC_RX_MANUAL | ENETC_IC_RX_ADAPTIVE)) {
2427 		icpt = ENETC_RBICR0_SET_ICPT(ENETC_RXIC_PKTTHR);
2428 		/* init to non-0 minimum, will be adjusted later */
2429 		ictt = 0x1;
2430 	} else {
2431 		icpt = 0x1; /* enable Rx ints by setting pkt thr to 1 */
2432 		ictt = 0;
2433 	}
2434 
2435 	for (i = 0; i < priv->num_rx_rings; i++) {
2436 		enetc_rxbdr_wr(hw, i, ENETC_RBICR1, ictt);
2437 		enetc_rxbdr_wr(hw, i, ENETC_RBICR0, ENETC_RBICR0_ICEN | icpt);
2438 		enetc_rxbdr_wr(hw, i, ENETC_RBIER, ENETC_RBIER_RXTIE);
2439 	}
2440 
2441 	if (priv->ic_mode & ENETC_IC_TX_MANUAL)
2442 		icpt = ENETC_TBICR0_SET_ICPT(ENETC_TXIC_PKTTHR);
2443 	else
2444 		icpt = 0x1; /* enable Tx ints by setting pkt thr to 1 */
2445 
2446 	for (i = 0; i < priv->num_tx_rings; i++) {
2447 		enetc_txbdr_wr(hw, i, ENETC_TBICR1, priv->tx_ictt);
2448 		enetc_txbdr_wr(hw, i, ENETC_TBICR0, ENETC_TBICR0_ICEN | icpt);
2449 		enetc_txbdr_wr(hw, i, ENETC_TBIER, ENETC_TBIER_TXTIE);
2450 	}
2451 }
2452 
enetc_clear_interrupts(struct enetc_ndev_priv * priv)2453 static void enetc_clear_interrupts(struct enetc_ndev_priv *priv)
2454 {
2455 	struct enetc_hw *hw = &priv->si->hw;
2456 	int i;
2457 
2458 	for (i = 0; i < priv->num_tx_rings; i++)
2459 		enetc_txbdr_wr(hw, i, ENETC_TBIER, 0);
2460 
2461 	for (i = 0; i < priv->num_rx_rings; i++)
2462 		enetc_rxbdr_wr(hw, i, ENETC_RBIER, 0);
2463 }
2464 
enetc_phylink_connect(struct net_device * ndev)2465 static int enetc_phylink_connect(struct net_device *ndev)
2466 {
2467 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2468 	struct ethtool_eee edata;
2469 	int err;
2470 
2471 	if (!priv->phylink) {
2472 		/* phy-less mode */
2473 		netif_carrier_on(ndev);
2474 		return 0;
2475 	}
2476 
2477 	err = phylink_of_phy_connect(priv->phylink, priv->dev->of_node, 0);
2478 	if (err) {
2479 		dev_err(&ndev->dev, "could not attach to PHY\n");
2480 		return err;
2481 	}
2482 
2483 	/* disable EEE autoneg, until ENETC driver supports it */
2484 	memset(&edata, 0, sizeof(struct ethtool_eee));
2485 	phylink_ethtool_set_eee(priv->phylink, &edata);
2486 
2487 	phylink_start(priv->phylink);
2488 
2489 	return 0;
2490 }
2491 
enetc_tx_onestep_tstamp(struct work_struct * work)2492 static void enetc_tx_onestep_tstamp(struct work_struct *work)
2493 {
2494 	struct enetc_ndev_priv *priv;
2495 	struct sk_buff *skb;
2496 
2497 	priv = container_of(work, struct enetc_ndev_priv, tx_onestep_tstamp);
2498 
2499 	netif_tx_lock_bh(priv->ndev);
2500 
2501 	clear_bit_unlock(ENETC_TX_ONESTEP_TSTAMP_IN_PROGRESS, &priv->flags);
2502 	skb = skb_dequeue(&priv->tx_skbs);
2503 	if (skb)
2504 		enetc_start_xmit(skb, priv->ndev);
2505 
2506 	netif_tx_unlock_bh(priv->ndev);
2507 }
2508 
enetc_tx_onestep_tstamp_init(struct enetc_ndev_priv * priv)2509 static void enetc_tx_onestep_tstamp_init(struct enetc_ndev_priv *priv)
2510 {
2511 	INIT_WORK(&priv->tx_onestep_tstamp, enetc_tx_onestep_tstamp);
2512 	skb_queue_head_init(&priv->tx_skbs);
2513 }
2514 
enetc_start(struct net_device * ndev)2515 void enetc_start(struct net_device *ndev)
2516 {
2517 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2518 	int i;
2519 
2520 	enetc_setup_interrupts(priv);
2521 
2522 	for (i = 0; i < priv->bdr_int_num; i++) {
2523 		int irq = pci_irq_vector(priv->si->pdev,
2524 					 ENETC_BDR_INT_BASE_IDX + i);
2525 
2526 		napi_enable(&priv->int_vector[i]->napi);
2527 		enable_irq(irq);
2528 	}
2529 
2530 	enetc_enable_tx_bdrs(priv);
2531 
2532 	enetc_enable_rx_bdrs(priv);
2533 
2534 	netif_tx_start_all_queues(ndev);
2535 
2536 	clear_bit(ENETC_TX_DOWN, &priv->flags);
2537 }
2538 EXPORT_SYMBOL_GPL(enetc_start);
2539 
enetc_open(struct net_device * ndev)2540 int enetc_open(struct net_device *ndev)
2541 {
2542 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2543 	struct enetc_bdr_resource *tx_res, *rx_res;
2544 	bool extended;
2545 	int err;
2546 
2547 	extended = !!(priv->active_offloads & ENETC_F_RX_TSTAMP);
2548 
2549 	err = enetc_setup_irqs(priv);
2550 	if (err)
2551 		return err;
2552 
2553 	err = enetc_phylink_connect(ndev);
2554 	if (err)
2555 		goto err_phy_connect;
2556 
2557 	tx_res = enetc_alloc_tx_resources(priv);
2558 	if (IS_ERR(tx_res)) {
2559 		err = PTR_ERR(tx_res);
2560 		goto err_alloc_tx;
2561 	}
2562 
2563 	rx_res = enetc_alloc_rx_resources(priv, extended);
2564 	if (IS_ERR(rx_res)) {
2565 		err = PTR_ERR(rx_res);
2566 		goto err_alloc_rx;
2567 	}
2568 
2569 	enetc_tx_onestep_tstamp_init(priv);
2570 	enetc_assign_tx_resources(priv, tx_res);
2571 	enetc_assign_rx_resources(priv, rx_res);
2572 	enetc_setup_bdrs(priv, extended);
2573 	enetc_start(ndev);
2574 
2575 	return 0;
2576 
2577 err_alloc_rx:
2578 	enetc_free_tx_resources(tx_res, priv->num_tx_rings);
2579 err_alloc_tx:
2580 	if (priv->phylink)
2581 		phylink_disconnect_phy(priv->phylink);
2582 err_phy_connect:
2583 	enetc_free_irqs(priv);
2584 
2585 	return err;
2586 }
2587 EXPORT_SYMBOL_GPL(enetc_open);
2588 
enetc_stop(struct net_device * ndev)2589 void enetc_stop(struct net_device *ndev)
2590 {
2591 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2592 	int i;
2593 
2594 	set_bit(ENETC_TX_DOWN, &priv->flags);
2595 
2596 	netif_tx_stop_all_queues(ndev);
2597 
2598 	enetc_disable_rx_bdrs(priv);
2599 
2600 	enetc_wait_bdrs(priv);
2601 
2602 	enetc_disable_tx_bdrs(priv);
2603 
2604 	for (i = 0; i < priv->bdr_int_num; i++) {
2605 		int irq = pci_irq_vector(priv->si->pdev,
2606 					 ENETC_BDR_INT_BASE_IDX + i);
2607 
2608 		disable_irq(irq);
2609 		napi_synchronize(&priv->int_vector[i]->napi);
2610 		napi_disable(&priv->int_vector[i]->napi);
2611 	}
2612 
2613 	enetc_clear_interrupts(priv);
2614 }
2615 EXPORT_SYMBOL_GPL(enetc_stop);
2616 
enetc_close(struct net_device * ndev)2617 int enetc_close(struct net_device *ndev)
2618 {
2619 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2620 
2621 	enetc_stop(ndev);
2622 
2623 	if (priv->phylink) {
2624 		phylink_stop(priv->phylink);
2625 		phylink_disconnect_phy(priv->phylink);
2626 	} else {
2627 		netif_carrier_off(ndev);
2628 	}
2629 
2630 	enetc_free_rxtx_rings(priv);
2631 
2632 	/* Avoids dangling pointers and also frees old resources */
2633 	enetc_assign_rx_resources(priv, NULL);
2634 	enetc_assign_tx_resources(priv, NULL);
2635 
2636 	enetc_free_irqs(priv);
2637 
2638 	return 0;
2639 }
2640 EXPORT_SYMBOL_GPL(enetc_close);
2641 
enetc_reconfigure(struct enetc_ndev_priv * priv,bool extended,int (* cb)(struct enetc_ndev_priv * priv,void * ctx),void * ctx)2642 static int enetc_reconfigure(struct enetc_ndev_priv *priv, bool extended,
2643 			     int (*cb)(struct enetc_ndev_priv *priv, void *ctx),
2644 			     void *ctx)
2645 {
2646 	struct enetc_bdr_resource *tx_res, *rx_res;
2647 	int err;
2648 
2649 	ASSERT_RTNL();
2650 
2651 	/* If the interface is down, run the callback right away,
2652 	 * without reconfiguration.
2653 	 */
2654 	if (!netif_running(priv->ndev)) {
2655 		if (cb) {
2656 			err = cb(priv, ctx);
2657 			if (err)
2658 				return err;
2659 		}
2660 
2661 		return 0;
2662 	}
2663 
2664 	tx_res = enetc_alloc_tx_resources(priv);
2665 	if (IS_ERR(tx_res)) {
2666 		err = PTR_ERR(tx_res);
2667 		goto out;
2668 	}
2669 
2670 	rx_res = enetc_alloc_rx_resources(priv, extended);
2671 	if (IS_ERR(rx_res)) {
2672 		err = PTR_ERR(rx_res);
2673 		goto out_free_tx_res;
2674 	}
2675 
2676 	enetc_stop(priv->ndev);
2677 	enetc_free_rxtx_rings(priv);
2678 
2679 	/* Interface is down, run optional callback now */
2680 	if (cb) {
2681 		err = cb(priv, ctx);
2682 		if (err)
2683 			goto out_restart;
2684 	}
2685 
2686 	enetc_assign_tx_resources(priv, tx_res);
2687 	enetc_assign_rx_resources(priv, rx_res);
2688 	enetc_setup_bdrs(priv, extended);
2689 	enetc_start(priv->ndev);
2690 
2691 	return 0;
2692 
2693 out_restart:
2694 	enetc_setup_bdrs(priv, extended);
2695 	enetc_start(priv->ndev);
2696 	enetc_free_rx_resources(rx_res, priv->num_rx_rings);
2697 out_free_tx_res:
2698 	enetc_free_tx_resources(tx_res, priv->num_tx_rings);
2699 out:
2700 	return err;
2701 }
2702 
enetc_debug_tx_ring_prios(struct enetc_ndev_priv * priv)2703 static void enetc_debug_tx_ring_prios(struct enetc_ndev_priv *priv)
2704 {
2705 	int i;
2706 
2707 	for (i = 0; i < priv->num_tx_rings; i++)
2708 		netdev_dbg(priv->ndev, "TX ring %d prio %d\n", i,
2709 			   priv->tx_ring[i]->prio);
2710 }
2711 
enetc_reset_tc_mqprio(struct net_device * ndev)2712 void enetc_reset_tc_mqprio(struct net_device *ndev)
2713 {
2714 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2715 	struct enetc_hw *hw = &priv->si->hw;
2716 	struct enetc_bdr *tx_ring;
2717 	int num_stack_tx_queues;
2718 	int i;
2719 
2720 	num_stack_tx_queues = enetc_num_stack_tx_queues(priv);
2721 
2722 	netdev_reset_tc(ndev);
2723 	netif_set_real_num_tx_queues(ndev, num_stack_tx_queues);
2724 	priv->min_num_stack_tx_queues = num_possible_cpus();
2725 
2726 	/* Reset all ring priorities to 0 */
2727 	for (i = 0; i < priv->num_tx_rings; i++) {
2728 		tx_ring = priv->tx_ring[i];
2729 		tx_ring->prio = 0;
2730 		enetc_set_bdr_prio(hw, tx_ring->index, tx_ring->prio);
2731 	}
2732 
2733 	enetc_debug_tx_ring_prios(priv);
2734 
2735 	enetc_change_preemptible_tcs(priv, 0);
2736 }
2737 EXPORT_SYMBOL_GPL(enetc_reset_tc_mqprio);
2738 
enetc_setup_tc_mqprio(struct net_device * ndev,void * type_data)2739 int enetc_setup_tc_mqprio(struct net_device *ndev, void *type_data)
2740 {
2741 	struct tc_mqprio_qopt_offload *mqprio = type_data;
2742 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2743 	struct tc_mqprio_qopt *qopt = &mqprio->qopt;
2744 	struct enetc_hw *hw = &priv->si->hw;
2745 	int num_stack_tx_queues = 0;
2746 	struct enetc_bdr *tx_ring;
2747 	u8 num_tc = qopt->num_tc;
2748 	int offset, count;
2749 	int err, tc, q;
2750 
2751 	if (!num_tc) {
2752 		enetc_reset_tc_mqprio(ndev);
2753 		return 0;
2754 	}
2755 
2756 	err = netdev_set_num_tc(ndev, num_tc);
2757 	if (err)
2758 		return err;
2759 
2760 	for (tc = 0; tc < num_tc; tc++) {
2761 		offset = qopt->offset[tc];
2762 		count = qopt->count[tc];
2763 		num_stack_tx_queues += count;
2764 
2765 		err = netdev_set_tc_queue(ndev, tc, count, offset);
2766 		if (err)
2767 			goto err_reset_tc;
2768 
2769 		for (q = offset; q < offset + count; q++) {
2770 			tx_ring = priv->tx_ring[q];
2771 			/* The prio_tc_map is skb_tx_hash()'s way of selecting
2772 			 * between TX queues based on skb->priority. As such,
2773 			 * there's nothing to offload based on it.
2774 			 * Make the mqprio "traffic class" be the priority of
2775 			 * this ring group, and leave the Tx IPV to traffic
2776 			 * class mapping as its default mapping value of 1:1.
2777 			 */
2778 			tx_ring->prio = tc;
2779 			enetc_set_bdr_prio(hw, tx_ring->index, tx_ring->prio);
2780 		}
2781 	}
2782 
2783 	err = netif_set_real_num_tx_queues(ndev, num_stack_tx_queues);
2784 	if (err)
2785 		goto err_reset_tc;
2786 
2787 	priv->min_num_stack_tx_queues = num_stack_tx_queues;
2788 
2789 	enetc_debug_tx_ring_prios(priv);
2790 
2791 	enetc_change_preemptible_tcs(priv, mqprio->preemptible_tcs);
2792 
2793 	return 0;
2794 
2795 err_reset_tc:
2796 	enetc_reset_tc_mqprio(ndev);
2797 	return err;
2798 }
2799 EXPORT_SYMBOL_GPL(enetc_setup_tc_mqprio);
2800 
enetc_reconfigure_xdp_cb(struct enetc_ndev_priv * priv,void * ctx)2801 static int enetc_reconfigure_xdp_cb(struct enetc_ndev_priv *priv, void *ctx)
2802 {
2803 	struct bpf_prog *old_prog, *prog = ctx;
2804 	int num_stack_tx_queues;
2805 	int err, i;
2806 
2807 	old_prog = xchg(&priv->xdp_prog, prog);
2808 
2809 	num_stack_tx_queues = enetc_num_stack_tx_queues(priv);
2810 	err = netif_set_real_num_tx_queues(priv->ndev, num_stack_tx_queues);
2811 	if (err) {
2812 		xchg(&priv->xdp_prog, old_prog);
2813 		return err;
2814 	}
2815 
2816 	if (old_prog)
2817 		bpf_prog_put(old_prog);
2818 
2819 	for (i = 0; i < priv->num_rx_rings; i++) {
2820 		struct enetc_bdr *rx_ring = priv->rx_ring[i];
2821 
2822 		rx_ring->xdp.prog = prog;
2823 
2824 		if (prog)
2825 			rx_ring->buffer_offset = XDP_PACKET_HEADROOM;
2826 		else
2827 			rx_ring->buffer_offset = ENETC_RXB_PAD;
2828 	}
2829 
2830 	return 0;
2831 }
2832 
enetc_setup_xdp_prog(struct net_device * ndev,struct bpf_prog * prog,struct netlink_ext_ack * extack)2833 static int enetc_setup_xdp_prog(struct net_device *ndev, struct bpf_prog *prog,
2834 				struct netlink_ext_ack *extack)
2835 {
2836 	int num_xdp_tx_queues = prog ? num_possible_cpus() : 0;
2837 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2838 	bool extended;
2839 
2840 	if (priv->min_num_stack_tx_queues + num_xdp_tx_queues >
2841 	    priv->num_tx_rings) {
2842 		NL_SET_ERR_MSG_FMT_MOD(extack,
2843 				       "Reserving %d XDP TXQs leaves under %d for stack (total %d)",
2844 				       num_xdp_tx_queues,
2845 				       priv->min_num_stack_tx_queues,
2846 				       priv->num_tx_rings);
2847 		return -EBUSY;
2848 	}
2849 
2850 	extended = !!(priv->active_offloads & ENETC_F_RX_TSTAMP);
2851 
2852 	/* The buffer layout is changing, so we need to drain the old
2853 	 * RX buffers and seed new ones.
2854 	 */
2855 	return enetc_reconfigure(priv, extended, enetc_reconfigure_xdp_cb, prog);
2856 }
2857 
enetc_setup_bpf(struct net_device * ndev,struct netdev_bpf * bpf)2858 int enetc_setup_bpf(struct net_device *ndev, struct netdev_bpf *bpf)
2859 {
2860 	switch (bpf->command) {
2861 	case XDP_SETUP_PROG:
2862 		return enetc_setup_xdp_prog(ndev, bpf->prog, bpf->extack);
2863 	default:
2864 		return -EINVAL;
2865 	}
2866 
2867 	return 0;
2868 }
2869 EXPORT_SYMBOL_GPL(enetc_setup_bpf);
2870 
enetc_get_stats(struct net_device * ndev)2871 struct net_device_stats *enetc_get_stats(struct net_device *ndev)
2872 {
2873 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2874 	struct net_device_stats *stats = &ndev->stats;
2875 	unsigned long packets = 0, bytes = 0;
2876 	unsigned long tx_dropped = 0;
2877 	int i;
2878 
2879 	for (i = 0; i < priv->num_rx_rings; i++) {
2880 		packets += priv->rx_ring[i]->stats.packets;
2881 		bytes	+= priv->rx_ring[i]->stats.bytes;
2882 	}
2883 
2884 	stats->rx_packets = packets;
2885 	stats->rx_bytes = bytes;
2886 	bytes = 0;
2887 	packets = 0;
2888 
2889 	for (i = 0; i < priv->num_tx_rings; i++) {
2890 		packets += priv->tx_ring[i]->stats.packets;
2891 		bytes	+= priv->tx_ring[i]->stats.bytes;
2892 		tx_dropped += priv->tx_ring[i]->stats.win_drop;
2893 	}
2894 
2895 	stats->tx_packets = packets;
2896 	stats->tx_bytes = bytes;
2897 	stats->tx_dropped = tx_dropped;
2898 
2899 	return stats;
2900 }
2901 EXPORT_SYMBOL_GPL(enetc_get_stats);
2902 
enetc_set_rss(struct net_device * ndev,int en)2903 static int enetc_set_rss(struct net_device *ndev, int en)
2904 {
2905 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2906 	struct enetc_hw *hw = &priv->si->hw;
2907 	u32 reg;
2908 
2909 	enetc_wr(hw, ENETC_SIRBGCR, priv->num_rx_rings);
2910 
2911 	reg = enetc_rd(hw, ENETC_SIMR);
2912 	reg &= ~ENETC_SIMR_RSSE;
2913 	reg |= (en) ? ENETC_SIMR_RSSE : 0;
2914 	enetc_wr(hw, ENETC_SIMR, reg);
2915 
2916 	return 0;
2917 }
2918 
enetc_enable_rxvlan(struct net_device * ndev,bool en)2919 static void enetc_enable_rxvlan(struct net_device *ndev, bool en)
2920 {
2921 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2922 	struct enetc_hw *hw = &priv->si->hw;
2923 	int i;
2924 
2925 	for (i = 0; i < priv->num_rx_rings; i++)
2926 		enetc_bdr_enable_rxvlan(hw, i, en);
2927 }
2928 
enetc_enable_txvlan(struct net_device * ndev,bool en)2929 static void enetc_enable_txvlan(struct net_device *ndev, bool en)
2930 {
2931 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2932 	struct enetc_hw *hw = &priv->si->hw;
2933 	int i;
2934 
2935 	for (i = 0; i < priv->num_tx_rings; i++)
2936 		enetc_bdr_enable_txvlan(hw, i, en);
2937 }
2938 
enetc_set_features(struct net_device * ndev,netdev_features_t features)2939 void enetc_set_features(struct net_device *ndev, netdev_features_t features)
2940 {
2941 	netdev_features_t changed = ndev->features ^ features;
2942 
2943 	if (changed & NETIF_F_RXHASH)
2944 		enetc_set_rss(ndev, !!(features & NETIF_F_RXHASH));
2945 
2946 	if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2947 		enetc_enable_rxvlan(ndev,
2948 				    !!(features & NETIF_F_HW_VLAN_CTAG_RX));
2949 
2950 	if (changed & NETIF_F_HW_VLAN_CTAG_TX)
2951 		enetc_enable_txvlan(ndev,
2952 				    !!(features & NETIF_F_HW_VLAN_CTAG_TX));
2953 }
2954 EXPORT_SYMBOL_GPL(enetc_set_features);
2955 
enetc_hwtstamp_set(struct net_device * ndev,struct ifreq * ifr)2956 static int enetc_hwtstamp_set(struct net_device *ndev, struct ifreq *ifr)
2957 {
2958 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2959 	int err, new_offloads = priv->active_offloads;
2960 	struct hwtstamp_config config;
2961 
2962 	if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2963 		return -EFAULT;
2964 
2965 	switch (config.tx_type) {
2966 	case HWTSTAMP_TX_OFF:
2967 		new_offloads &= ~ENETC_F_TX_TSTAMP_MASK;
2968 		break;
2969 	case HWTSTAMP_TX_ON:
2970 		new_offloads &= ~ENETC_F_TX_TSTAMP_MASK;
2971 		new_offloads |= ENETC_F_TX_TSTAMP;
2972 		break;
2973 	case HWTSTAMP_TX_ONESTEP_SYNC:
2974 		if (!enetc_si_is_pf(priv->si))
2975 			return -EOPNOTSUPP;
2976 
2977 		new_offloads &= ~ENETC_F_TX_TSTAMP_MASK;
2978 		new_offloads |= ENETC_F_TX_ONESTEP_SYNC_TSTAMP;
2979 		break;
2980 	default:
2981 		return -ERANGE;
2982 	}
2983 
2984 	switch (config.rx_filter) {
2985 	case HWTSTAMP_FILTER_NONE:
2986 		new_offloads &= ~ENETC_F_RX_TSTAMP;
2987 		break;
2988 	default:
2989 		new_offloads |= ENETC_F_RX_TSTAMP;
2990 		config.rx_filter = HWTSTAMP_FILTER_ALL;
2991 	}
2992 
2993 	if ((new_offloads ^ priv->active_offloads) & ENETC_F_RX_TSTAMP) {
2994 		bool extended = !!(new_offloads & ENETC_F_RX_TSTAMP);
2995 
2996 		err = enetc_reconfigure(priv, extended, NULL, NULL);
2997 		if (err)
2998 			return err;
2999 	}
3000 
3001 	priv->active_offloads = new_offloads;
3002 
3003 	return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
3004 	       -EFAULT : 0;
3005 }
3006 
enetc_hwtstamp_get(struct net_device * ndev,struct ifreq * ifr)3007 static int enetc_hwtstamp_get(struct net_device *ndev, struct ifreq *ifr)
3008 {
3009 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
3010 	struct hwtstamp_config config;
3011 
3012 	config.flags = 0;
3013 
3014 	if (priv->active_offloads & ENETC_F_TX_ONESTEP_SYNC_TSTAMP)
3015 		config.tx_type = HWTSTAMP_TX_ONESTEP_SYNC;
3016 	else if (priv->active_offloads & ENETC_F_TX_TSTAMP)
3017 		config.tx_type = HWTSTAMP_TX_ON;
3018 	else
3019 		config.tx_type = HWTSTAMP_TX_OFF;
3020 
3021 	config.rx_filter = (priv->active_offloads & ENETC_F_RX_TSTAMP) ?
3022 			    HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE;
3023 
3024 	return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
3025 	       -EFAULT : 0;
3026 }
3027 
enetc_ioctl(struct net_device * ndev,struct ifreq * rq,int cmd)3028 int enetc_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
3029 {
3030 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
3031 
3032 	if (IS_ENABLED(CONFIG_FSL_ENETC_PTP_CLOCK)) {
3033 		if (cmd == SIOCSHWTSTAMP)
3034 			return enetc_hwtstamp_set(ndev, rq);
3035 		if (cmd == SIOCGHWTSTAMP)
3036 			return enetc_hwtstamp_get(ndev, rq);
3037 	}
3038 
3039 	if (!priv->phylink)
3040 		return -EOPNOTSUPP;
3041 
3042 	return phylink_mii_ioctl(priv->phylink, rq, cmd);
3043 }
3044 EXPORT_SYMBOL_GPL(enetc_ioctl);
3045 
enetc_alloc_msix(struct enetc_ndev_priv * priv)3046 int enetc_alloc_msix(struct enetc_ndev_priv *priv)
3047 {
3048 	struct pci_dev *pdev = priv->si->pdev;
3049 	int num_stack_tx_queues;
3050 	int first_xdp_tx_ring;
3051 	int i, n, err, nvec;
3052 	int v_tx_rings;
3053 
3054 	nvec = ENETC_BDR_INT_BASE_IDX + priv->bdr_int_num;
3055 	/* allocate MSIX for both messaging and Rx/Tx interrupts */
3056 	n = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSIX);
3057 
3058 	if (n < 0)
3059 		return n;
3060 
3061 	if (n != nvec)
3062 		return -EPERM;
3063 
3064 	/* # of tx rings per int vector */
3065 	v_tx_rings = priv->num_tx_rings / priv->bdr_int_num;
3066 
3067 	for (i = 0; i < priv->bdr_int_num; i++) {
3068 		struct enetc_int_vector *v;
3069 		struct enetc_bdr *bdr;
3070 		int j;
3071 
3072 		v = kzalloc(struct_size(v, tx_ring, v_tx_rings), GFP_KERNEL);
3073 		if (!v) {
3074 			err = -ENOMEM;
3075 			goto fail;
3076 		}
3077 
3078 		priv->int_vector[i] = v;
3079 
3080 		bdr = &v->rx_ring;
3081 		bdr->index = i;
3082 		bdr->ndev = priv->ndev;
3083 		bdr->dev = priv->dev;
3084 		bdr->bd_count = priv->rx_bd_count;
3085 		bdr->buffer_offset = ENETC_RXB_PAD;
3086 		priv->rx_ring[i] = bdr;
3087 
3088 		err = xdp_rxq_info_reg(&bdr->xdp.rxq, priv->ndev, i, 0);
3089 		if (err) {
3090 			kfree(v);
3091 			goto fail;
3092 		}
3093 
3094 		err = xdp_rxq_info_reg_mem_model(&bdr->xdp.rxq,
3095 						 MEM_TYPE_PAGE_SHARED, NULL);
3096 		if (err) {
3097 			xdp_rxq_info_unreg(&bdr->xdp.rxq);
3098 			kfree(v);
3099 			goto fail;
3100 		}
3101 
3102 		/* init defaults for adaptive IC */
3103 		if (priv->ic_mode & ENETC_IC_RX_ADAPTIVE) {
3104 			v->rx_ictt = 0x1;
3105 			v->rx_dim_en = true;
3106 		}
3107 		INIT_WORK(&v->rx_dim.work, enetc_rx_dim_work);
3108 		netif_napi_add(priv->ndev, &v->napi, enetc_poll);
3109 		v->count_tx_rings = v_tx_rings;
3110 
3111 		for (j = 0; j < v_tx_rings; j++) {
3112 			int idx;
3113 
3114 			/* default tx ring mapping policy */
3115 			idx = priv->bdr_int_num * j + i;
3116 			__set_bit(idx, &v->tx_rings_map);
3117 			bdr = &v->tx_ring[j];
3118 			bdr->index = idx;
3119 			bdr->ndev = priv->ndev;
3120 			bdr->dev = priv->dev;
3121 			bdr->bd_count = priv->tx_bd_count;
3122 			priv->tx_ring[idx] = bdr;
3123 		}
3124 	}
3125 
3126 	num_stack_tx_queues = enetc_num_stack_tx_queues(priv);
3127 
3128 	err = netif_set_real_num_tx_queues(priv->ndev, num_stack_tx_queues);
3129 	if (err)
3130 		goto fail;
3131 
3132 	err = netif_set_real_num_rx_queues(priv->ndev, priv->num_rx_rings);
3133 	if (err)
3134 		goto fail;
3135 
3136 	priv->min_num_stack_tx_queues = num_possible_cpus();
3137 	first_xdp_tx_ring = priv->num_tx_rings - num_possible_cpus();
3138 	priv->xdp_tx_ring = &priv->tx_ring[first_xdp_tx_ring];
3139 
3140 	return 0;
3141 
3142 fail:
3143 	while (i--) {
3144 		struct enetc_int_vector *v = priv->int_vector[i];
3145 		struct enetc_bdr *rx_ring = &v->rx_ring;
3146 
3147 		xdp_rxq_info_unreg_mem_model(&rx_ring->xdp.rxq);
3148 		xdp_rxq_info_unreg(&rx_ring->xdp.rxq);
3149 		netif_napi_del(&v->napi);
3150 		cancel_work_sync(&v->rx_dim.work);
3151 		kfree(v);
3152 	}
3153 
3154 	pci_free_irq_vectors(pdev);
3155 
3156 	return err;
3157 }
3158 EXPORT_SYMBOL_GPL(enetc_alloc_msix);
3159 
enetc_free_msix(struct enetc_ndev_priv * priv)3160 void enetc_free_msix(struct enetc_ndev_priv *priv)
3161 {
3162 	int i;
3163 
3164 	for (i = 0; i < priv->bdr_int_num; i++) {
3165 		struct enetc_int_vector *v = priv->int_vector[i];
3166 		struct enetc_bdr *rx_ring = &v->rx_ring;
3167 
3168 		xdp_rxq_info_unreg_mem_model(&rx_ring->xdp.rxq);
3169 		xdp_rxq_info_unreg(&rx_ring->xdp.rxq);
3170 		netif_napi_del(&v->napi);
3171 		cancel_work_sync(&v->rx_dim.work);
3172 	}
3173 
3174 	for (i = 0; i < priv->num_rx_rings; i++)
3175 		priv->rx_ring[i] = NULL;
3176 
3177 	for (i = 0; i < priv->num_tx_rings; i++)
3178 		priv->tx_ring[i] = NULL;
3179 
3180 	for (i = 0; i < priv->bdr_int_num; i++) {
3181 		kfree(priv->int_vector[i]);
3182 		priv->int_vector[i] = NULL;
3183 	}
3184 
3185 	/* disable all MSIX for this device */
3186 	pci_free_irq_vectors(priv->si->pdev);
3187 }
3188 EXPORT_SYMBOL_GPL(enetc_free_msix);
3189 
enetc_kfree_si(struct enetc_si * si)3190 static void enetc_kfree_si(struct enetc_si *si)
3191 {
3192 	char *p = (char *)si - si->pad;
3193 
3194 	kfree(p);
3195 }
3196 
enetc_detect_errata(struct enetc_si * si)3197 static void enetc_detect_errata(struct enetc_si *si)
3198 {
3199 	if (si->pdev->revision == ENETC_REV1)
3200 		si->errata = ENETC_ERR_VLAN_ISOL | ENETC_ERR_UCMCSWP;
3201 }
3202 
enetc_pci_probe(struct pci_dev * pdev,const char * name,int sizeof_priv)3203 int enetc_pci_probe(struct pci_dev *pdev, const char *name, int sizeof_priv)
3204 {
3205 	struct enetc_si *si, *p;
3206 	struct enetc_hw *hw;
3207 	size_t alloc_size;
3208 	int err, len;
3209 
3210 	pcie_flr(pdev);
3211 	err = pci_enable_device_mem(pdev);
3212 	if (err)
3213 		return dev_err_probe(&pdev->dev, err, "device enable failed\n");
3214 
3215 	/* set up for high or low dma */
3216 	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3217 	if (err) {
3218 		dev_err(&pdev->dev, "DMA configuration failed: 0x%x\n", err);
3219 		goto err_dma;
3220 	}
3221 
3222 	err = pci_request_mem_regions(pdev, name);
3223 	if (err) {
3224 		dev_err(&pdev->dev, "pci_request_regions failed err=%d\n", err);
3225 		goto err_pci_mem_reg;
3226 	}
3227 
3228 	pci_set_master(pdev);
3229 
3230 	alloc_size = sizeof(struct enetc_si);
3231 	if (sizeof_priv) {
3232 		/* align priv to 32B */
3233 		alloc_size = ALIGN(alloc_size, ENETC_SI_ALIGN);
3234 		alloc_size += sizeof_priv;
3235 	}
3236 	/* force 32B alignment for enetc_si */
3237 	alloc_size += ENETC_SI_ALIGN - 1;
3238 
3239 	p = kzalloc(alloc_size, GFP_KERNEL);
3240 	if (!p) {
3241 		err = -ENOMEM;
3242 		goto err_alloc_si;
3243 	}
3244 
3245 	si = PTR_ALIGN(p, ENETC_SI_ALIGN);
3246 	si->pad = (char *)si - (char *)p;
3247 
3248 	pci_set_drvdata(pdev, si);
3249 	si->pdev = pdev;
3250 	hw = &si->hw;
3251 
3252 	len = pci_resource_len(pdev, ENETC_BAR_REGS);
3253 	hw->reg = ioremap(pci_resource_start(pdev, ENETC_BAR_REGS), len);
3254 	if (!hw->reg) {
3255 		err = -ENXIO;
3256 		dev_err(&pdev->dev, "ioremap() failed\n");
3257 		goto err_ioremap;
3258 	}
3259 	if (len > ENETC_PORT_BASE)
3260 		hw->port = hw->reg + ENETC_PORT_BASE;
3261 	if (len > ENETC_GLOBAL_BASE)
3262 		hw->global = hw->reg + ENETC_GLOBAL_BASE;
3263 
3264 	enetc_detect_errata(si);
3265 
3266 	return 0;
3267 
3268 err_ioremap:
3269 	enetc_kfree_si(si);
3270 err_alloc_si:
3271 	pci_release_mem_regions(pdev);
3272 err_pci_mem_reg:
3273 err_dma:
3274 	pci_disable_device(pdev);
3275 
3276 	return err;
3277 }
3278 EXPORT_SYMBOL_GPL(enetc_pci_probe);
3279 
enetc_pci_remove(struct pci_dev * pdev)3280 void enetc_pci_remove(struct pci_dev *pdev)
3281 {
3282 	struct enetc_si *si = pci_get_drvdata(pdev);
3283 	struct enetc_hw *hw = &si->hw;
3284 
3285 	iounmap(hw->reg);
3286 	enetc_kfree_si(si);
3287 	pci_release_mem_regions(pdev);
3288 	pci_disable_device(pdev);
3289 }
3290 EXPORT_SYMBOL_GPL(enetc_pci_remove);
3291 
3292 MODULE_LICENSE("Dual BSD/GPL");
3293