xref: /openbmc/linux/drivers/net/ethernet/freescale/enetc/enetc.c (revision 0f9b4c3ca5fdf3e177266ef994071b1a03f07318)
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* Copyright 2017-2019 NXP */
3 
4 #include "enetc.h"
5 #include <linux/bpf_trace.h>
6 #include <linux/tcp.h>
7 #include <linux/udp.h>
8 #include <linux/vmalloc.h>
9 #include <linux/ptp_classify.h>
10 #include <net/ip6_checksum.h>
11 #include <net/pkt_sched.h>
12 #include <net/tso.h>
13 
enetc_port_mac_rd(struct enetc_si * si,u32 reg)14 u32 enetc_port_mac_rd(struct enetc_si *si, u32 reg)
15 {
16 	return enetc_port_rd(&si->hw, reg);
17 }
18 EXPORT_SYMBOL_GPL(enetc_port_mac_rd);
19 
enetc_port_mac_wr(struct enetc_si * si,u32 reg,u32 val)20 void enetc_port_mac_wr(struct enetc_si *si, u32 reg, u32 val)
21 {
22 	enetc_port_wr(&si->hw, reg, val);
23 	if (si->hw_features & ENETC_SI_F_QBU)
24 		enetc_port_wr(&si->hw, reg + ENETC_PMAC_OFFSET, val);
25 }
26 EXPORT_SYMBOL_GPL(enetc_port_mac_wr);
27 
enetc_change_preemptible_tcs(struct enetc_ndev_priv * priv,u8 preemptible_tcs)28 static void enetc_change_preemptible_tcs(struct enetc_ndev_priv *priv,
29 					 u8 preemptible_tcs)
30 {
31 	if (!(priv->si->hw_features & ENETC_SI_F_QBU))
32 		return;
33 
34 	priv->preemptible_tcs = preemptible_tcs;
35 	enetc_mm_commit_preemptible_tcs(priv);
36 }
37 
enetc_num_stack_tx_queues(struct enetc_ndev_priv * priv)38 static int enetc_num_stack_tx_queues(struct enetc_ndev_priv *priv)
39 {
40 	int num_tx_rings = priv->num_tx_rings;
41 
42 	if (priv->xdp_prog)
43 		return num_tx_rings - num_possible_cpus();
44 
45 	return num_tx_rings;
46 }
47 
enetc_rx_ring_from_xdp_tx_ring(struct enetc_ndev_priv * priv,struct enetc_bdr * tx_ring)48 static struct enetc_bdr *enetc_rx_ring_from_xdp_tx_ring(struct enetc_ndev_priv *priv,
49 							struct enetc_bdr *tx_ring)
50 {
51 	int index = &priv->tx_ring[tx_ring->index] - priv->xdp_tx_ring;
52 
53 	return priv->rx_ring[index];
54 }
55 
enetc_tx_swbd_get_skb(struct enetc_tx_swbd * tx_swbd)56 static struct sk_buff *enetc_tx_swbd_get_skb(struct enetc_tx_swbd *tx_swbd)
57 {
58 	if (tx_swbd->is_xdp_tx || tx_swbd->is_xdp_redirect)
59 		return NULL;
60 
61 	return tx_swbd->skb;
62 }
63 
64 static struct xdp_frame *
enetc_tx_swbd_get_xdp_frame(struct enetc_tx_swbd * tx_swbd)65 enetc_tx_swbd_get_xdp_frame(struct enetc_tx_swbd *tx_swbd)
66 {
67 	if (tx_swbd->is_xdp_redirect)
68 		return tx_swbd->xdp_frame;
69 
70 	return NULL;
71 }
72 
enetc_unmap_tx_buff(struct enetc_bdr * tx_ring,struct enetc_tx_swbd * tx_swbd)73 static void enetc_unmap_tx_buff(struct enetc_bdr *tx_ring,
74 				struct enetc_tx_swbd *tx_swbd)
75 {
76 	/* For XDP_TX, pages come from RX, whereas for the other contexts where
77 	 * we have is_dma_page_set, those come from skb_frag_dma_map. We need
78 	 * to match the DMA mapping length, so we need to differentiate those.
79 	 */
80 	if (tx_swbd->is_dma_page)
81 		dma_unmap_page(tx_ring->dev, tx_swbd->dma,
82 			       tx_swbd->is_xdp_tx ? PAGE_SIZE : tx_swbd->len,
83 			       tx_swbd->dir);
84 	else
85 		dma_unmap_single(tx_ring->dev, tx_swbd->dma,
86 				 tx_swbd->len, tx_swbd->dir);
87 	tx_swbd->dma = 0;
88 }
89 
enetc_free_tx_frame(struct enetc_bdr * tx_ring,struct enetc_tx_swbd * tx_swbd)90 static void enetc_free_tx_frame(struct enetc_bdr *tx_ring,
91 				struct enetc_tx_swbd *tx_swbd)
92 {
93 	struct xdp_frame *xdp_frame = enetc_tx_swbd_get_xdp_frame(tx_swbd);
94 	struct sk_buff *skb = enetc_tx_swbd_get_skb(tx_swbd);
95 
96 	if (tx_swbd->dma)
97 		enetc_unmap_tx_buff(tx_ring, tx_swbd);
98 
99 	if (xdp_frame) {
100 		xdp_return_frame(tx_swbd->xdp_frame);
101 		tx_swbd->xdp_frame = NULL;
102 	} else if (skb) {
103 		dev_kfree_skb_any(skb);
104 		tx_swbd->skb = NULL;
105 	}
106 }
107 
108 /* Let H/W know BD ring has been updated */
enetc_update_tx_ring_tail(struct enetc_bdr * tx_ring)109 static void enetc_update_tx_ring_tail(struct enetc_bdr *tx_ring)
110 {
111 	/* includes wmb() */
112 	enetc_wr_reg_hot(tx_ring->tpir, tx_ring->next_to_use);
113 }
114 
enetc_ptp_parse(struct sk_buff * skb,u8 * udp,u8 * msgtype,u8 * twostep,u16 * correction_offset,u16 * body_offset)115 static int enetc_ptp_parse(struct sk_buff *skb, u8 *udp,
116 			   u8 *msgtype, u8 *twostep,
117 			   u16 *correction_offset, u16 *body_offset)
118 {
119 	unsigned int ptp_class;
120 	struct ptp_header *hdr;
121 	unsigned int type;
122 	u8 *base;
123 
124 	ptp_class = ptp_classify_raw(skb);
125 	if (ptp_class == PTP_CLASS_NONE)
126 		return -EINVAL;
127 
128 	hdr = ptp_parse_header(skb, ptp_class);
129 	if (!hdr)
130 		return -EINVAL;
131 
132 	type = ptp_class & PTP_CLASS_PMASK;
133 	if (type == PTP_CLASS_IPV4 || type == PTP_CLASS_IPV6)
134 		*udp = 1;
135 	else
136 		*udp = 0;
137 
138 	*msgtype = ptp_get_msgtype(hdr, ptp_class);
139 	*twostep = hdr->flag_field[0] & 0x2;
140 
141 	base = skb_mac_header(skb);
142 	*correction_offset = (u8 *)&hdr->correction - base;
143 	*body_offset = (u8 *)hdr + sizeof(struct ptp_header) - base;
144 
145 	return 0;
146 }
147 
148 /**
149  * enetc_unwind_tx_frame() - Unwind the DMA mappings of a multi-buffer Tx frame
150  * @tx_ring: Pointer to the Tx ring on which the buffer descriptors are located
151  * @count: Number of Tx buffer descriptors which need to be unmapped
152  * @i: Index of the last successfully mapped Tx buffer descriptor
153  */
enetc_unwind_tx_frame(struct enetc_bdr * tx_ring,int count,int i)154 static void enetc_unwind_tx_frame(struct enetc_bdr *tx_ring, int count, int i)
155 {
156 	while (count--) {
157 		struct enetc_tx_swbd *tx_swbd = &tx_ring->tx_swbd[i];
158 
159 		enetc_free_tx_frame(tx_ring, tx_swbd);
160 		if (i == 0)
161 			i = tx_ring->bd_count;
162 		i--;
163 	}
164 }
165 
enetc_map_tx_buffs(struct enetc_bdr * tx_ring,struct sk_buff * skb)166 static int enetc_map_tx_buffs(struct enetc_bdr *tx_ring, struct sk_buff *skb)
167 {
168 	bool do_vlan, do_onestep_tstamp = false, do_twostep_tstamp = false;
169 	struct enetc_ndev_priv *priv = netdev_priv(tx_ring->ndev);
170 	struct enetc_hw *hw = &priv->si->hw;
171 	struct enetc_tx_swbd *tx_swbd;
172 	int len = skb_headlen(skb);
173 	union enetc_tx_bd temp_bd;
174 	u8 msgtype, twostep, udp;
175 	union enetc_tx_bd *txbd;
176 	u16 offset1, offset2;
177 	int i, count = 0;
178 	skb_frag_t *frag;
179 	unsigned int f;
180 	dma_addr_t dma;
181 	u8 flags = 0;
182 
183 	i = tx_ring->next_to_use;
184 	txbd = ENETC_TXBD(*tx_ring, i);
185 	prefetchw(txbd);
186 
187 	dma = dma_map_single(tx_ring->dev, skb->data, len, DMA_TO_DEVICE);
188 	if (unlikely(dma_mapping_error(tx_ring->dev, dma)))
189 		goto dma_err;
190 
191 	temp_bd.addr = cpu_to_le64(dma);
192 	temp_bd.buf_len = cpu_to_le16(len);
193 	temp_bd.lstatus = 0;
194 
195 	tx_swbd = &tx_ring->tx_swbd[i];
196 	tx_swbd->dma = dma;
197 	tx_swbd->len = len;
198 	tx_swbd->is_dma_page = 0;
199 	tx_swbd->dir = DMA_TO_DEVICE;
200 	count++;
201 
202 	do_vlan = skb_vlan_tag_present(skb);
203 	if (skb->cb[0] & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) {
204 		if (enetc_ptp_parse(skb, &udp, &msgtype, &twostep, &offset1,
205 				    &offset2) ||
206 		    msgtype != PTP_MSGTYPE_SYNC || twostep)
207 			WARN_ONCE(1, "Bad packet for one-step timestamping\n");
208 		else
209 			do_onestep_tstamp = true;
210 	} else if (skb->cb[0] & ENETC_F_TX_TSTAMP) {
211 		do_twostep_tstamp = true;
212 	}
213 
214 	tx_swbd->do_twostep_tstamp = do_twostep_tstamp;
215 	tx_swbd->qbv_en = !!(priv->active_offloads & ENETC_F_QBV);
216 	tx_swbd->check_wb = tx_swbd->do_twostep_tstamp || tx_swbd->qbv_en;
217 
218 	if (do_vlan || do_onestep_tstamp || do_twostep_tstamp)
219 		flags |= ENETC_TXBD_FLAGS_EX;
220 
221 	if (tx_ring->tsd_enable)
222 		flags |= ENETC_TXBD_FLAGS_TSE | ENETC_TXBD_FLAGS_TXSTART;
223 
224 	/* first BD needs frm_len and offload flags set */
225 	temp_bd.frm_len = cpu_to_le16(skb->len);
226 	temp_bd.flags = flags;
227 
228 	if (flags & ENETC_TXBD_FLAGS_TSE)
229 		temp_bd.txstart = enetc_txbd_set_tx_start(skb->skb_mstamp_ns,
230 							  flags);
231 
232 	if (flags & ENETC_TXBD_FLAGS_EX) {
233 		u8 e_flags = 0;
234 		*txbd = temp_bd;
235 		enetc_clear_tx_bd(&temp_bd);
236 
237 		/* add extension BD for VLAN and/or timestamping */
238 		flags = 0;
239 		tx_swbd++;
240 		txbd++;
241 		i++;
242 		if (unlikely(i == tx_ring->bd_count)) {
243 			i = 0;
244 			tx_swbd = tx_ring->tx_swbd;
245 			txbd = ENETC_TXBD(*tx_ring, 0);
246 		}
247 		prefetchw(txbd);
248 
249 		if (do_vlan) {
250 			temp_bd.ext.vid = cpu_to_le16(skb_vlan_tag_get(skb));
251 			temp_bd.ext.tpid = 0; /* < C-TAG */
252 			e_flags |= ENETC_TXBD_E_FLAGS_VLAN_INS;
253 		}
254 
255 		if (do_onestep_tstamp) {
256 			__be32 new_sec_l, new_nsec;
257 			u32 lo, hi, nsec, val;
258 			__be16 new_sec_h;
259 			u8 *data;
260 			u64 sec;
261 
262 			lo = enetc_rd_hot(hw, ENETC_SICTR0);
263 			hi = enetc_rd_hot(hw, ENETC_SICTR1);
264 			sec = (u64)hi << 32 | lo;
265 			nsec = do_div(sec, 1000000000);
266 
267 			/* Configure extension BD */
268 			temp_bd.ext.tstamp = cpu_to_le32(lo & 0x3fffffff);
269 			e_flags |= ENETC_TXBD_E_FLAGS_ONE_STEP_PTP;
270 
271 			/* Update originTimestamp field of Sync packet
272 			 * - 48 bits seconds field
273 			 * - 32 bits nanseconds field
274 			 *
275 			 * In addition, the UDP checksum needs to be updated
276 			 * by software after updating originTimestamp field,
277 			 * otherwise the hardware will calculate the wrong
278 			 * checksum when updating the correction field and
279 			 * update it to the packet.
280 			 */
281 			data = skb_mac_header(skb);
282 			new_sec_h = htons((sec >> 32) & 0xffff);
283 			new_sec_l = htonl(sec & 0xffffffff);
284 			new_nsec = htonl(nsec);
285 			if (udp) {
286 				struct udphdr *uh = udp_hdr(skb);
287 				__be32 old_sec_l, old_nsec;
288 				__be16 old_sec_h;
289 
290 				old_sec_h = *(__be16 *)(data + offset2);
291 				inet_proto_csum_replace2(&uh->check, skb, old_sec_h,
292 							 new_sec_h, false);
293 
294 				old_sec_l = *(__be32 *)(data + offset2 + 2);
295 				inet_proto_csum_replace4(&uh->check, skb, old_sec_l,
296 							 new_sec_l, false);
297 
298 				old_nsec = *(__be32 *)(data + offset2 + 6);
299 				inet_proto_csum_replace4(&uh->check, skb, old_nsec,
300 							 new_nsec, false);
301 			}
302 
303 			*(__be16 *)(data + offset2) = new_sec_h;
304 			*(__be32 *)(data + offset2 + 2) = new_sec_l;
305 			*(__be32 *)(data + offset2 + 6) = new_nsec;
306 
307 			/* Configure single-step register */
308 			val = ENETC_PM0_SINGLE_STEP_EN;
309 			val |= ENETC_SET_SINGLE_STEP_OFFSET(offset1);
310 			if (udp)
311 				val |= ENETC_PM0_SINGLE_STEP_CH;
312 
313 			enetc_port_mac_wr(priv->si, ENETC_PM0_SINGLE_STEP,
314 					  val);
315 		} else if (do_twostep_tstamp) {
316 			skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
317 			e_flags |= ENETC_TXBD_E_FLAGS_TWO_STEP_PTP;
318 		}
319 
320 		temp_bd.ext.e_flags = e_flags;
321 		count++;
322 	}
323 
324 	frag = &skb_shinfo(skb)->frags[0];
325 	for (f = 0; f < skb_shinfo(skb)->nr_frags; f++, frag++) {
326 		len = skb_frag_size(frag);
327 		dma = skb_frag_dma_map(tx_ring->dev, frag, 0, len,
328 				       DMA_TO_DEVICE);
329 		if (dma_mapping_error(tx_ring->dev, dma))
330 			goto dma_err;
331 
332 		*txbd = temp_bd;
333 		enetc_clear_tx_bd(&temp_bd);
334 
335 		flags = 0;
336 		tx_swbd++;
337 		txbd++;
338 		i++;
339 		if (unlikely(i == tx_ring->bd_count)) {
340 			i = 0;
341 			tx_swbd = tx_ring->tx_swbd;
342 			txbd = ENETC_TXBD(*tx_ring, 0);
343 		}
344 		prefetchw(txbd);
345 
346 		temp_bd.addr = cpu_to_le64(dma);
347 		temp_bd.buf_len = cpu_to_le16(len);
348 
349 		tx_swbd->dma = dma;
350 		tx_swbd->len = len;
351 		tx_swbd->is_dma_page = 1;
352 		tx_swbd->dir = DMA_TO_DEVICE;
353 		count++;
354 	}
355 
356 	/* last BD needs 'F' bit set */
357 	flags |= ENETC_TXBD_FLAGS_F;
358 	temp_bd.flags = flags;
359 	*txbd = temp_bd;
360 
361 	tx_ring->tx_swbd[i].is_eof = true;
362 	tx_ring->tx_swbd[i].skb = skb;
363 
364 	enetc_bdr_idx_inc(tx_ring, &i);
365 	tx_ring->next_to_use = i;
366 
367 	skb_tx_timestamp(skb);
368 
369 	enetc_update_tx_ring_tail(tx_ring);
370 
371 	return count;
372 
373 dma_err:
374 	dev_err(tx_ring->dev, "DMA map error");
375 
376 	enetc_unwind_tx_frame(tx_ring, count, i);
377 
378 	return 0;
379 }
380 
enetc_map_tx_tso_hdr(struct enetc_bdr * tx_ring,struct sk_buff * skb,struct enetc_tx_swbd * tx_swbd,union enetc_tx_bd * txbd,int * i,int hdr_len,int data_len)381 static int enetc_map_tx_tso_hdr(struct enetc_bdr *tx_ring, struct sk_buff *skb,
382 				struct enetc_tx_swbd *tx_swbd,
383 				union enetc_tx_bd *txbd, int *i, int hdr_len,
384 				int data_len)
385 {
386 	union enetc_tx_bd txbd_tmp;
387 	u8 flags = 0, e_flags = 0;
388 	dma_addr_t addr;
389 	int count = 1;
390 
391 	enetc_clear_tx_bd(&txbd_tmp);
392 	addr = tx_ring->tso_headers_dma + *i * TSO_HEADER_SIZE;
393 
394 	if (skb_vlan_tag_present(skb))
395 		flags |= ENETC_TXBD_FLAGS_EX;
396 
397 	txbd_tmp.addr = cpu_to_le64(addr);
398 	txbd_tmp.buf_len = cpu_to_le16(hdr_len);
399 
400 	/* first BD needs frm_len and offload flags set */
401 	txbd_tmp.frm_len = cpu_to_le16(hdr_len + data_len);
402 	txbd_tmp.flags = flags;
403 
404 	/* For the TSO header we do not set the dma address since we do not
405 	 * want it unmapped when we do cleanup. We still set len so that we
406 	 * count the bytes sent.
407 	 */
408 	tx_swbd->len = hdr_len;
409 	tx_swbd->do_twostep_tstamp = false;
410 	tx_swbd->check_wb = false;
411 
412 	/* Actually write the header in the BD */
413 	*txbd = txbd_tmp;
414 
415 	/* Add extension BD for VLAN */
416 	if (flags & ENETC_TXBD_FLAGS_EX) {
417 		/* Get the next BD */
418 		enetc_bdr_idx_inc(tx_ring, i);
419 		txbd = ENETC_TXBD(*tx_ring, *i);
420 		tx_swbd = &tx_ring->tx_swbd[*i];
421 		prefetchw(txbd);
422 
423 		/* Setup the VLAN fields */
424 		enetc_clear_tx_bd(&txbd_tmp);
425 		txbd_tmp.ext.vid = cpu_to_le16(skb_vlan_tag_get(skb));
426 		txbd_tmp.ext.tpid = 0; /* < C-TAG */
427 		e_flags |= ENETC_TXBD_E_FLAGS_VLAN_INS;
428 
429 		/* Write the BD */
430 		txbd_tmp.ext.e_flags = e_flags;
431 		*txbd = txbd_tmp;
432 		count++;
433 	}
434 
435 	return count;
436 }
437 
enetc_map_tx_tso_data(struct enetc_bdr * tx_ring,struct sk_buff * skb,struct enetc_tx_swbd * tx_swbd,union enetc_tx_bd * txbd,char * data,int size,bool last_bd)438 static int enetc_map_tx_tso_data(struct enetc_bdr *tx_ring, struct sk_buff *skb,
439 				 struct enetc_tx_swbd *tx_swbd,
440 				 union enetc_tx_bd *txbd, char *data,
441 				 int size, bool last_bd)
442 {
443 	union enetc_tx_bd txbd_tmp;
444 	dma_addr_t addr;
445 	u8 flags = 0;
446 
447 	enetc_clear_tx_bd(&txbd_tmp);
448 
449 	addr = dma_map_single(tx_ring->dev, data, size, DMA_TO_DEVICE);
450 	if (unlikely(dma_mapping_error(tx_ring->dev, addr))) {
451 		netdev_err(tx_ring->ndev, "DMA map error\n");
452 		return -ENOMEM;
453 	}
454 
455 	if (last_bd) {
456 		flags |= ENETC_TXBD_FLAGS_F;
457 		tx_swbd->is_eof = 1;
458 	}
459 
460 	txbd_tmp.addr = cpu_to_le64(addr);
461 	txbd_tmp.buf_len = cpu_to_le16(size);
462 	txbd_tmp.flags = flags;
463 
464 	tx_swbd->dma = addr;
465 	tx_swbd->len = size;
466 	tx_swbd->dir = DMA_TO_DEVICE;
467 
468 	*txbd = txbd_tmp;
469 
470 	return 0;
471 }
472 
enetc_tso_hdr_csum(struct tso_t * tso,struct sk_buff * skb,char * hdr,int hdr_len,int * l4_hdr_len)473 static __wsum enetc_tso_hdr_csum(struct tso_t *tso, struct sk_buff *skb,
474 				 char *hdr, int hdr_len, int *l4_hdr_len)
475 {
476 	char *l4_hdr = hdr + skb_transport_offset(skb);
477 	int mac_hdr_len = skb_network_offset(skb);
478 
479 	if (tso->tlen != sizeof(struct udphdr)) {
480 		struct tcphdr *tcph = (struct tcphdr *)(l4_hdr);
481 
482 		tcph->check = 0;
483 	} else {
484 		struct udphdr *udph = (struct udphdr *)(l4_hdr);
485 
486 		udph->check = 0;
487 	}
488 
489 	/* Compute the IP checksum. This is necessary since tso_build_hdr()
490 	 * already incremented the IP ID field.
491 	 */
492 	if (!tso->ipv6) {
493 		struct iphdr *iph = (void *)(hdr + mac_hdr_len);
494 
495 		iph->check = 0;
496 		iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
497 	}
498 
499 	/* Compute the checksum over the L4 header. */
500 	*l4_hdr_len = hdr_len - skb_transport_offset(skb);
501 	return csum_partial(l4_hdr, *l4_hdr_len, 0);
502 }
503 
enetc_tso_complete_csum(struct enetc_bdr * tx_ring,struct tso_t * tso,struct sk_buff * skb,char * hdr,int len,__wsum sum)504 static void enetc_tso_complete_csum(struct enetc_bdr *tx_ring, struct tso_t *tso,
505 				    struct sk_buff *skb, char *hdr, int len,
506 				    __wsum sum)
507 {
508 	char *l4_hdr = hdr + skb_transport_offset(skb);
509 	__sum16 csum_final;
510 
511 	/* Complete the L4 checksum by appending the pseudo-header to the
512 	 * already computed checksum.
513 	 */
514 	if (!tso->ipv6)
515 		csum_final = csum_tcpudp_magic(ip_hdr(skb)->saddr,
516 					       ip_hdr(skb)->daddr,
517 					       len, ip_hdr(skb)->protocol, sum);
518 	else
519 		csum_final = csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
520 					     &ipv6_hdr(skb)->daddr,
521 					     len, ipv6_hdr(skb)->nexthdr, sum);
522 
523 	if (tso->tlen != sizeof(struct udphdr)) {
524 		struct tcphdr *tcph = (struct tcphdr *)(l4_hdr);
525 
526 		tcph->check = csum_final;
527 	} else {
528 		struct udphdr *udph = (struct udphdr *)(l4_hdr);
529 
530 		udph->check = csum_final;
531 	}
532 }
533 
enetc_map_tx_tso_buffs(struct enetc_bdr * tx_ring,struct sk_buff * skb)534 static int enetc_map_tx_tso_buffs(struct enetc_bdr *tx_ring, struct sk_buff *skb)
535 {
536 	int hdr_len, total_len, data_len;
537 	struct enetc_tx_swbd *tx_swbd;
538 	union enetc_tx_bd *txbd;
539 	struct tso_t tso;
540 	__wsum csum, csum2;
541 	int count = 0, pos;
542 	int err, i, bd_data_num;
543 
544 	/* Initialize the TSO handler, and prepare the first payload */
545 	hdr_len = tso_start(skb, &tso);
546 	total_len = skb->len - hdr_len;
547 	i = tx_ring->next_to_use;
548 
549 	while (total_len > 0) {
550 		char *hdr;
551 
552 		/* Get the BD */
553 		txbd = ENETC_TXBD(*tx_ring, i);
554 		tx_swbd = &tx_ring->tx_swbd[i];
555 		prefetchw(txbd);
556 
557 		/* Determine the length of this packet */
558 		data_len = min_t(int, skb_shinfo(skb)->gso_size, total_len);
559 		total_len -= data_len;
560 
561 		/* prepare packet headers: MAC + IP + TCP */
562 		hdr = tx_ring->tso_headers + i * TSO_HEADER_SIZE;
563 		tso_build_hdr(skb, hdr, &tso, data_len, total_len == 0);
564 
565 		/* compute the csum over the L4 header */
566 		csum = enetc_tso_hdr_csum(&tso, skb, hdr, hdr_len, &pos);
567 		count += enetc_map_tx_tso_hdr(tx_ring, skb, tx_swbd, txbd,
568 					      &i, hdr_len, data_len);
569 		bd_data_num = 0;
570 
571 		while (data_len > 0) {
572 			int size;
573 
574 			size = min_t(int, tso.size, data_len);
575 
576 			/* Advance the index in the BDR */
577 			enetc_bdr_idx_inc(tx_ring, &i);
578 			txbd = ENETC_TXBD(*tx_ring, i);
579 			tx_swbd = &tx_ring->tx_swbd[i];
580 			prefetchw(txbd);
581 
582 			/* Compute the checksum over this segment of data and
583 			 * add it to the csum already computed (over the L4
584 			 * header and possible other data segments).
585 			 */
586 			csum2 = csum_partial(tso.data, size, 0);
587 			csum = csum_block_add(csum, csum2, pos);
588 			pos += size;
589 
590 			err = enetc_map_tx_tso_data(tx_ring, skb, tx_swbd, txbd,
591 						    tso.data, size,
592 						    size == data_len);
593 			if (err) {
594 				if (i == 0)
595 					i = tx_ring->bd_count;
596 				i--;
597 
598 				goto err_map_data;
599 			}
600 
601 			data_len -= size;
602 			count++;
603 			bd_data_num++;
604 			tso_build_data(skb, &tso, size);
605 
606 			if (unlikely(bd_data_num >= ENETC_MAX_SKB_FRAGS && data_len))
607 				goto err_chained_bd;
608 		}
609 
610 		enetc_tso_complete_csum(tx_ring, &tso, skb, hdr, pos, csum);
611 
612 		if (total_len == 0)
613 			tx_swbd->skb = skb;
614 
615 		/* Go to the next BD */
616 		enetc_bdr_idx_inc(tx_ring, &i);
617 	}
618 
619 	tx_ring->next_to_use = i;
620 	enetc_update_tx_ring_tail(tx_ring);
621 
622 	return count;
623 
624 err_map_data:
625 	dev_err(tx_ring->dev, "DMA map error");
626 
627 err_chained_bd:
628 	enetc_unwind_tx_frame(tx_ring, count, i);
629 
630 	return 0;
631 }
632 
enetc_start_xmit(struct sk_buff * skb,struct net_device * ndev)633 static netdev_tx_t enetc_start_xmit(struct sk_buff *skb,
634 				    struct net_device *ndev)
635 {
636 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
637 	struct enetc_bdr *tx_ring;
638 	int count, err;
639 
640 	/* Queue one-step Sync packet if already locked */
641 	if (skb->cb[0] & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) {
642 		if (test_and_set_bit_lock(ENETC_TX_ONESTEP_TSTAMP_IN_PROGRESS,
643 					  &priv->flags)) {
644 			skb_queue_tail(&priv->tx_skbs, skb);
645 			return NETDEV_TX_OK;
646 		}
647 	}
648 
649 	tx_ring = priv->tx_ring[skb->queue_mapping];
650 
651 	if (skb_is_gso(skb)) {
652 		if (enetc_bd_unused(tx_ring) < tso_count_descs(skb)) {
653 			netif_stop_subqueue(ndev, tx_ring->index);
654 			return NETDEV_TX_BUSY;
655 		}
656 
657 		enetc_lock_mdio();
658 		count = enetc_map_tx_tso_buffs(tx_ring, skb);
659 		enetc_unlock_mdio();
660 	} else {
661 		if (unlikely(skb_shinfo(skb)->nr_frags > ENETC_MAX_SKB_FRAGS))
662 			if (unlikely(skb_linearize(skb)))
663 				goto drop_packet_err;
664 
665 		count = skb_shinfo(skb)->nr_frags + 1; /* fragments + head */
666 		if (enetc_bd_unused(tx_ring) < ENETC_TXBDS_NEEDED(count)) {
667 			netif_stop_subqueue(ndev, tx_ring->index);
668 			return NETDEV_TX_BUSY;
669 		}
670 
671 		if (skb->ip_summed == CHECKSUM_PARTIAL) {
672 			err = skb_checksum_help(skb);
673 			if (err)
674 				goto drop_packet_err;
675 		}
676 		enetc_lock_mdio();
677 		count = enetc_map_tx_buffs(tx_ring, skb);
678 		enetc_unlock_mdio();
679 	}
680 
681 	if (unlikely(!count))
682 		goto drop_packet_err;
683 
684 	if (enetc_bd_unused(tx_ring) < ENETC_TXBDS_MAX_NEEDED)
685 		netif_stop_subqueue(ndev, tx_ring->index);
686 
687 	return NETDEV_TX_OK;
688 
689 drop_packet_err:
690 	dev_kfree_skb_any(skb);
691 	return NETDEV_TX_OK;
692 }
693 
enetc_xmit(struct sk_buff * skb,struct net_device * ndev)694 netdev_tx_t enetc_xmit(struct sk_buff *skb, struct net_device *ndev)
695 {
696 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
697 	u8 udp, msgtype, twostep;
698 	u16 offset1, offset2;
699 
700 	/* Mark tx timestamp type on skb->cb[0] if requires */
701 	if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
702 	    (priv->active_offloads & ENETC_F_TX_TSTAMP_MASK)) {
703 		skb->cb[0] = priv->active_offloads & ENETC_F_TX_TSTAMP_MASK;
704 	} else {
705 		skb->cb[0] = 0;
706 	}
707 
708 	/* Fall back to two-step timestamp if not one-step Sync packet */
709 	if (skb->cb[0] & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) {
710 		if (enetc_ptp_parse(skb, &udp, &msgtype, &twostep,
711 				    &offset1, &offset2) ||
712 		    msgtype != PTP_MSGTYPE_SYNC || twostep != 0)
713 			skb->cb[0] = ENETC_F_TX_TSTAMP;
714 	}
715 
716 	return enetc_start_xmit(skb, ndev);
717 }
718 EXPORT_SYMBOL_GPL(enetc_xmit);
719 
enetc_msix(int irq,void * data)720 static irqreturn_t enetc_msix(int irq, void *data)
721 {
722 	struct enetc_int_vector	*v = data;
723 	int i;
724 
725 	enetc_lock_mdio();
726 
727 	/* disable interrupts */
728 	enetc_wr_reg_hot(v->rbier, 0);
729 	enetc_wr_reg_hot(v->ricr1, v->rx_ictt);
730 
731 	for_each_set_bit(i, &v->tx_rings_map, ENETC_MAX_NUM_TXQS)
732 		enetc_wr_reg_hot(v->tbier_base + ENETC_BDR_OFF(i), 0);
733 
734 	enetc_unlock_mdio();
735 
736 	napi_schedule(&v->napi);
737 
738 	return IRQ_HANDLED;
739 }
740 
enetc_rx_dim_work(struct work_struct * w)741 static void enetc_rx_dim_work(struct work_struct *w)
742 {
743 	struct dim *dim = container_of(w, struct dim, work);
744 	struct dim_cq_moder moder =
745 		net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
746 	struct enetc_int_vector	*v =
747 		container_of(dim, struct enetc_int_vector, rx_dim);
748 
749 	v->rx_ictt = enetc_usecs_to_cycles(moder.usec);
750 	dim->state = DIM_START_MEASURE;
751 }
752 
enetc_rx_net_dim(struct enetc_int_vector * v)753 static void enetc_rx_net_dim(struct enetc_int_vector *v)
754 {
755 	struct dim_sample dim_sample = {};
756 
757 	v->comp_cnt++;
758 
759 	if (!v->rx_napi_work)
760 		return;
761 
762 	dim_update_sample(v->comp_cnt,
763 			  v->rx_ring.stats.packets,
764 			  v->rx_ring.stats.bytes,
765 			  &dim_sample);
766 	net_dim(&v->rx_dim, dim_sample);
767 }
768 
enetc_bd_ready_count(struct enetc_bdr * tx_ring,int ci)769 static int enetc_bd_ready_count(struct enetc_bdr *tx_ring, int ci)
770 {
771 	int pi = enetc_rd_reg_hot(tx_ring->tcir) & ENETC_TBCIR_IDX_MASK;
772 
773 	return pi >= ci ? pi - ci : tx_ring->bd_count - ci + pi;
774 }
775 
enetc_page_reusable(struct page * page)776 static bool enetc_page_reusable(struct page *page)
777 {
778 	return (!page_is_pfmemalloc(page) && page_ref_count(page) == 1);
779 }
780 
enetc_reuse_page(struct enetc_bdr * rx_ring,struct enetc_rx_swbd * old)781 static void enetc_reuse_page(struct enetc_bdr *rx_ring,
782 			     struct enetc_rx_swbd *old)
783 {
784 	struct enetc_rx_swbd *new;
785 
786 	new = &rx_ring->rx_swbd[rx_ring->next_to_alloc];
787 
788 	/* next buf that may reuse a page */
789 	enetc_bdr_idx_inc(rx_ring, &rx_ring->next_to_alloc);
790 
791 	/* copy page reference */
792 	*new = *old;
793 }
794 
enetc_get_tx_tstamp(struct enetc_hw * hw,union enetc_tx_bd * txbd,u64 * tstamp)795 static void enetc_get_tx_tstamp(struct enetc_hw *hw, union enetc_tx_bd *txbd,
796 				u64 *tstamp)
797 {
798 	u32 lo, hi, tstamp_lo;
799 
800 	lo = enetc_rd_hot(hw, ENETC_SICTR0);
801 	hi = enetc_rd_hot(hw, ENETC_SICTR1);
802 	tstamp_lo = le32_to_cpu(txbd->wb.tstamp);
803 	if (lo <= tstamp_lo)
804 		hi -= 1;
805 	*tstamp = (u64)hi << 32 | tstamp_lo;
806 }
807 
enetc_tstamp_tx(struct sk_buff * skb,u64 tstamp)808 static void enetc_tstamp_tx(struct sk_buff *skb, u64 tstamp)
809 {
810 	struct skb_shared_hwtstamps shhwtstamps;
811 
812 	if (skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) {
813 		memset(&shhwtstamps, 0, sizeof(shhwtstamps));
814 		shhwtstamps.hwtstamp = ns_to_ktime(tstamp);
815 		skb_txtime_consumed(skb);
816 		skb_tstamp_tx(skb, &shhwtstamps);
817 	}
818 }
819 
enetc_recycle_xdp_tx_buff(struct enetc_bdr * tx_ring,struct enetc_tx_swbd * tx_swbd)820 static void enetc_recycle_xdp_tx_buff(struct enetc_bdr *tx_ring,
821 				      struct enetc_tx_swbd *tx_swbd)
822 {
823 	struct enetc_ndev_priv *priv = netdev_priv(tx_ring->ndev);
824 	struct enetc_rx_swbd rx_swbd = {
825 		.dma = tx_swbd->dma,
826 		.page = tx_swbd->page,
827 		.page_offset = tx_swbd->page_offset,
828 		.dir = tx_swbd->dir,
829 		.len = tx_swbd->len,
830 	};
831 	struct enetc_bdr *rx_ring;
832 
833 	rx_ring = enetc_rx_ring_from_xdp_tx_ring(priv, tx_ring);
834 
835 	if (likely(enetc_swbd_unused(rx_ring))) {
836 		enetc_reuse_page(rx_ring, &rx_swbd);
837 
838 		/* sync for use by the device */
839 		dma_sync_single_range_for_device(rx_ring->dev, rx_swbd.dma,
840 						 rx_swbd.page_offset,
841 						 ENETC_RXB_DMA_SIZE_XDP,
842 						 rx_swbd.dir);
843 
844 		rx_ring->stats.recycles++;
845 	} else {
846 		/* RX ring is already full, we need to unmap and free the
847 		 * page, since there's nothing useful we can do with it.
848 		 */
849 		rx_ring->stats.recycle_failures++;
850 
851 		dma_unmap_page(rx_ring->dev, rx_swbd.dma, PAGE_SIZE,
852 			       rx_swbd.dir);
853 		__free_page(rx_swbd.page);
854 	}
855 
856 	rx_ring->xdp.xdp_tx_in_flight--;
857 }
858 
enetc_clean_tx_ring(struct enetc_bdr * tx_ring,int napi_budget)859 static bool enetc_clean_tx_ring(struct enetc_bdr *tx_ring, int napi_budget)
860 {
861 	int tx_frm_cnt = 0, tx_byte_cnt = 0, tx_win_drop = 0;
862 	struct net_device *ndev = tx_ring->ndev;
863 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
864 	struct enetc_tx_swbd *tx_swbd;
865 	int i, bds_to_clean;
866 	bool do_twostep_tstamp;
867 	u64 tstamp = 0;
868 
869 	i = tx_ring->next_to_clean;
870 	tx_swbd = &tx_ring->tx_swbd[i];
871 
872 	bds_to_clean = enetc_bd_ready_count(tx_ring, i);
873 
874 	do_twostep_tstamp = false;
875 
876 	while (bds_to_clean && tx_frm_cnt < ENETC_DEFAULT_TX_WORK) {
877 		struct xdp_frame *xdp_frame = enetc_tx_swbd_get_xdp_frame(tx_swbd);
878 		struct sk_buff *skb = enetc_tx_swbd_get_skb(tx_swbd);
879 		bool is_eof = tx_swbd->is_eof;
880 
881 		if (unlikely(tx_swbd->check_wb)) {
882 			union enetc_tx_bd *txbd = ENETC_TXBD(*tx_ring, i);
883 
884 			if (txbd->flags & ENETC_TXBD_FLAGS_W &&
885 			    tx_swbd->do_twostep_tstamp) {
886 				enetc_get_tx_tstamp(&priv->si->hw, txbd,
887 						    &tstamp);
888 				do_twostep_tstamp = true;
889 			}
890 
891 			if (tx_swbd->qbv_en &&
892 			    txbd->wb.status & ENETC_TXBD_STATS_WIN)
893 				tx_win_drop++;
894 		}
895 
896 		if (tx_swbd->is_xdp_tx)
897 			enetc_recycle_xdp_tx_buff(tx_ring, tx_swbd);
898 		else if (likely(tx_swbd->dma))
899 			enetc_unmap_tx_buff(tx_ring, tx_swbd);
900 
901 		if (xdp_frame) {
902 			xdp_return_frame(xdp_frame);
903 		} else if (skb) {
904 			if (unlikely(skb->cb[0] & ENETC_F_TX_ONESTEP_SYNC_TSTAMP)) {
905 				/* Start work to release lock for next one-step
906 				 * timestamping packet. And send one skb in
907 				 * tx_skbs queue if has.
908 				 */
909 				schedule_work(&priv->tx_onestep_tstamp);
910 			} else if (unlikely(do_twostep_tstamp)) {
911 				enetc_tstamp_tx(skb, tstamp);
912 				do_twostep_tstamp = false;
913 			}
914 			napi_consume_skb(skb, napi_budget);
915 		}
916 
917 		tx_byte_cnt += tx_swbd->len;
918 		/* Scrub the swbd here so we don't have to do that
919 		 * when we reuse it during xmit
920 		 */
921 		memset(tx_swbd, 0, sizeof(*tx_swbd));
922 
923 		bds_to_clean--;
924 		tx_swbd++;
925 		i++;
926 		if (unlikely(i == tx_ring->bd_count)) {
927 			i = 0;
928 			tx_swbd = tx_ring->tx_swbd;
929 		}
930 
931 		/* BD iteration loop end */
932 		if (is_eof) {
933 			tx_frm_cnt++;
934 			/* re-arm interrupt source */
935 			enetc_wr_reg_hot(tx_ring->idr, BIT(tx_ring->index) |
936 					 BIT(16 + tx_ring->index));
937 		}
938 
939 		if (unlikely(!bds_to_clean))
940 			bds_to_clean = enetc_bd_ready_count(tx_ring, i);
941 	}
942 
943 	tx_ring->next_to_clean = i;
944 	tx_ring->stats.packets += tx_frm_cnt;
945 	tx_ring->stats.bytes += tx_byte_cnt;
946 	tx_ring->stats.win_drop += tx_win_drop;
947 
948 	if (unlikely(tx_frm_cnt && netif_carrier_ok(ndev) &&
949 		     __netif_subqueue_stopped(ndev, tx_ring->index) &&
950 		     !test_bit(ENETC_TX_DOWN, &priv->flags) &&
951 		     (enetc_bd_unused(tx_ring) >= ENETC_TXBDS_MAX_NEEDED))) {
952 		netif_wake_subqueue(ndev, tx_ring->index);
953 	}
954 
955 	return tx_frm_cnt != ENETC_DEFAULT_TX_WORK;
956 }
957 
enetc_new_page(struct enetc_bdr * rx_ring,struct enetc_rx_swbd * rx_swbd)958 static bool enetc_new_page(struct enetc_bdr *rx_ring,
959 			   struct enetc_rx_swbd *rx_swbd)
960 {
961 	bool xdp = !!(rx_ring->xdp.prog);
962 	struct page *page;
963 	dma_addr_t addr;
964 
965 	page = dev_alloc_page();
966 	if (unlikely(!page))
967 		return false;
968 
969 	/* For XDP_TX, we forgo dma_unmap -> dma_map */
970 	rx_swbd->dir = xdp ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
971 
972 	addr = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, rx_swbd->dir);
973 	if (unlikely(dma_mapping_error(rx_ring->dev, addr))) {
974 		__free_page(page);
975 
976 		return false;
977 	}
978 
979 	rx_swbd->dma = addr;
980 	rx_swbd->page = page;
981 	rx_swbd->page_offset = rx_ring->buffer_offset;
982 
983 	return true;
984 }
985 
enetc_refill_rx_ring(struct enetc_bdr * rx_ring,const int buff_cnt)986 static int enetc_refill_rx_ring(struct enetc_bdr *rx_ring, const int buff_cnt)
987 {
988 	struct enetc_rx_swbd *rx_swbd;
989 	union enetc_rx_bd *rxbd;
990 	int i, j;
991 
992 	i = rx_ring->next_to_use;
993 	rx_swbd = &rx_ring->rx_swbd[i];
994 	rxbd = enetc_rxbd(rx_ring, i);
995 
996 	for (j = 0; j < buff_cnt; j++) {
997 		/* try reuse page */
998 		if (unlikely(!rx_swbd->page)) {
999 			if (unlikely(!enetc_new_page(rx_ring, rx_swbd))) {
1000 				rx_ring->stats.rx_alloc_errs++;
1001 				break;
1002 			}
1003 		}
1004 
1005 		/* update RxBD */
1006 		rxbd->w.addr = cpu_to_le64(rx_swbd->dma +
1007 					   rx_swbd->page_offset);
1008 		/* clear 'R" as well */
1009 		rxbd->r.lstatus = 0;
1010 
1011 		enetc_rxbd_next(rx_ring, &rxbd, &i);
1012 		rx_swbd = &rx_ring->rx_swbd[i];
1013 	}
1014 
1015 	if (likely(j)) {
1016 		rx_ring->next_to_alloc = i; /* keep track from page reuse */
1017 		rx_ring->next_to_use = i;
1018 
1019 		/* update ENETC's consumer index */
1020 		enetc_wr_reg_hot(rx_ring->rcir, rx_ring->next_to_use);
1021 	}
1022 
1023 	return j;
1024 }
1025 
1026 #ifdef CONFIG_FSL_ENETC_PTP_CLOCK
enetc_get_rx_tstamp(struct net_device * ndev,union enetc_rx_bd * rxbd,struct sk_buff * skb)1027 static void enetc_get_rx_tstamp(struct net_device *ndev,
1028 				union enetc_rx_bd *rxbd,
1029 				struct sk_buff *skb)
1030 {
1031 	struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
1032 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
1033 	struct enetc_hw *hw = &priv->si->hw;
1034 	u32 lo, hi, tstamp_lo;
1035 	u64 tstamp;
1036 
1037 	if (le16_to_cpu(rxbd->r.flags) & ENETC_RXBD_FLAG_TSTMP) {
1038 		lo = enetc_rd_reg_hot(hw->reg + ENETC_SICTR0);
1039 		hi = enetc_rd_reg_hot(hw->reg + ENETC_SICTR1);
1040 		rxbd = enetc_rxbd_ext(rxbd);
1041 		tstamp_lo = le32_to_cpu(rxbd->ext.tstamp);
1042 		if (lo <= tstamp_lo)
1043 			hi -= 1;
1044 
1045 		tstamp = (u64)hi << 32 | tstamp_lo;
1046 		memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1047 		shhwtstamps->hwtstamp = ns_to_ktime(tstamp);
1048 	}
1049 }
1050 #endif
1051 
enetc_get_offloads(struct enetc_bdr * rx_ring,union enetc_rx_bd * rxbd,struct sk_buff * skb)1052 static void enetc_get_offloads(struct enetc_bdr *rx_ring,
1053 			       union enetc_rx_bd *rxbd, struct sk_buff *skb)
1054 {
1055 	struct enetc_ndev_priv *priv = netdev_priv(rx_ring->ndev);
1056 
1057 	/* TODO: hashing */
1058 	if (rx_ring->ndev->features & NETIF_F_RXCSUM) {
1059 		u16 inet_csum = le16_to_cpu(rxbd->r.inet_csum);
1060 
1061 		skb->csum = csum_unfold((__force __sum16)~htons(inet_csum));
1062 		skb->ip_summed = CHECKSUM_COMPLETE;
1063 	}
1064 
1065 	if (le16_to_cpu(rxbd->r.flags) & ENETC_RXBD_FLAG_VLAN) {
1066 		__be16 tpid = 0;
1067 
1068 		switch (le16_to_cpu(rxbd->r.flags) & ENETC_RXBD_FLAG_TPID) {
1069 		case 0:
1070 			tpid = htons(ETH_P_8021Q);
1071 			break;
1072 		case 1:
1073 			tpid = htons(ETH_P_8021AD);
1074 			break;
1075 		case 2:
1076 			tpid = htons(enetc_port_rd(&priv->si->hw,
1077 						   ENETC_PCVLANR1));
1078 			break;
1079 		case 3:
1080 			tpid = htons(enetc_port_rd(&priv->si->hw,
1081 						   ENETC_PCVLANR2));
1082 			break;
1083 		default:
1084 			break;
1085 		}
1086 
1087 		__vlan_hwaccel_put_tag(skb, tpid, le16_to_cpu(rxbd->r.vlan_opt));
1088 	}
1089 
1090 #ifdef CONFIG_FSL_ENETC_PTP_CLOCK
1091 	if (priv->active_offloads & ENETC_F_RX_TSTAMP)
1092 		enetc_get_rx_tstamp(rx_ring->ndev, rxbd, skb);
1093 #endif
1094 }
1095 
1096 /* This gets called during the non-XDP NAPI poll cycle as well as on XDP_PASS,
1097  * so it needs to work with both DMA_FROM_DEVICE as well as DMA_BIDIRECTIONAL
1098  * mapped buffers.
1099  */
enetc_get_rx_buff(struct enetc_bdr * rx_ring,int i,u16 size)1100 static struct enetc_rx_swbd *enetc_get_rx_buff(struct enetc_bdr *rx_ring,
1101 					       int i, u16 size)
1102 {
1103 	struct enetc_rx_swbd *rx_swbd = &rx_ring->rx_swbd[i];
1104 
1105 	dma_sync_single_range_for_cpu(rx_ring->dev, rx_swbd->dma,
1106 				      rx_swbd->page_offset,
1107 				      size, rx_swbd->dir);
1108 	return rx_swbd;
1109 }
1110 
1111 /* Reuse the current page without performing half-page buffer flipping */
enetc_put_rx_buff(struct enetc_bdr * rx_ring,struct enetc_rx_swbd * rx_swbd)1112 static void enetc_put_rx_buff(struct enetc_bdr *rx_ring,
1113 			      struct enetc_rx_swbd *rx_swbd)
1114 {
1115 	size_t buffer_size = ENETC_RXB_TRUESIZE - rx_ring->buffer_offset;
1116 
1117 	enetc_reuse_page(rx_ring, rx_swbd);
1118 
1119 	dma_sync_single_range_for_device(rx_ring->dev, rx_swbd->dma,
1120 					 rx_swbd->page_offset,
1121 					 buffer_size, rx_swbd->dir);
1122 
1123 	rx_swbd->page = NULL;
1124 }
1125 
1126 /* Reuse the current page by performing half-page buffer flipping */
enetc_flip_rx_buff(struct enetc_bdr * rx_ring,struct enetc_rx_swbd * rx_swbd)1127 static void enetc_flip_rx_buff(struct enetc_bdr *rx_ring,
1128 			       struct enetc_rx_swbd *rx_swbd)
1129 {
1130 	if (likely(enetc_page_reusable(rx_swbd->page))) {
1131 		rx_swbd->page_offset ^= ENETC_RXB_TRUESIZE;
1132 		page_ref_inc(rx_swbd->page);
1133 
1134 		enetc_put_rx_buff(rx_ring, rx_swbd);
1135 	} else {
1136 		dma_unmap_page(rx_ring->dev, rx_swbd->dma, PAGE_SIZE,
1137 			       rx_swbd->dir);
1138 		rx_swbd->page = NULL;
1139 	}
1140 }
1141 
enetc_map_rx_buff_to_skb(struct enetc_bdr * rx_ring,int i,u16 size)1142 static struct sk_buff *enetc_map_rx_buff_to_skb(struct enetc_bdr *rx_ring,
1143 						int i, u16 size)
1144 {
1145 	struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size);
1146 	struct sk_buff *skb;
1147 	void *ba;
1148 
1149 	ba = page_address(rx_swbd->page) + rx_swbd->page_offset;
1150 	skb = build_skb(ba - rx_ring->buffer_offset, ENETC_RXB_TRUESIZE);
1151 	if (unlikely(!skb)) {
1152 		rx_ring->stats.rx_alloc_errs++;
1153 		return NULL;
1154 	}
1155 
1156 	skb_reserve(skb, rx_ring->buffer_offset);
1157 	__skb_put(skb, size);
1158 
1159 	enetc_flip_rx_buff(rx_ring, rx_swbd);
1160 
1161 	return skb;
1162 }
1163 
enetc_add_rx_buff_to_skb(struct enetc_bdr * rx_ring,int i,u16 size,struct sk_buff * skb)1164 static void enetc_add_rx_buff_to_skb(struct enetc_bdr *rx_ring, int i,
1165 				     u16 size, struct sk_buff *skb)
1166 {
1167 	struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size);
1168 
1169 	skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_swbd->page,
1170 			rx_swbd->page_offset, size, ENETC_RXB_TRUESIZE);
1171 
1172 	enetc_flip_rx_buff(rx_ring, rx_swbd);
1173 }
1174 
enetc_check_bd_errors_and_consume(struct enetc_bdr * rx_ring,u32 bd_status,union enetc_rx_bd ** rxbd,int * i)1175 static bool enetc_check_bd_errors_and_consume(struct enetc_bdr *rx_ring,
1176 					      u32 bd_status,
1177 					      union enetc_rx_bd **rxbd, int *i)
1178 {
1179 	if (likely(!(bd_status & ENETC_RXBD_LSTATUS(ENETC_RXBD_ERR_MASK))))
1180 		return false;
1181 
1182 	enetc_put_rx_buff(rx_ring, &rx_ring->rx_swbd[*i]);
1183 	enetc_rxbd_next(rx_ring, rxbd, i);
1184 
1185 	while (!(bd_status & ENETC_RXBD_LSTATUS_F)) {
1186 		dma_rmb();
1187 		bd_status = le32_to_cpu((*rxbd)->r.lstatus);
1188 
1189 		enetc_put_rx_buff(rx_ring, &rx_ring->rx_swbd[*i]);
1190 		enetc_rxbd_next(rx_ring, rxbd, i);
1191 	}
1192 
1193 	rx_ring->ndev->stats.rx_dropped++;
1194 	rx_ring->ndev->stats.rx_errors++;
1195 
1196 	return true;
1197 }
1198 
enetc_build_skb(struct enetc_bdr * rx_ring,u32 bd_status,union enetc_rx_bd ** rxbd,int * i,int * cleaned_cnt,int buffer_size)1199 static struct sk_buff *enetc_build_skb(struct enetc_bdr *rx_ring,
1200 				       u32 bd_status, union enetc_rx_bd **rxbd,
1201 				       int *i, int *cleaned_cnt, int buffer_size)
1202 {
1203 	struct sk_buff *skb;
1204 	u16 size;
1205 
1206 	size = le16_to_cpu((*rxbd)->r.buf_len);
1207 	skb = enetc_map_rx_buff_to_skb(rx_ring, *i, size);
1208 	if (!skb)
1209 		return NULL;
1210 
1211 	enetc_get_offloads(rx_ring, *rxbd, skb);
1212 
1213 	(*cleaned_cnt)++;
1214 
1215 	enetc_rxbd_next(rx_ring, rxbd, i);
1216 
1217 	/* not last BD in frame? */
1218 	while (!(bd_status & ENETC_RXBD_LSTATUS_F)) {
1219 		bd_status = le32_to_cpu((*rxbd)->r.lstatus);
1220 		size = buffer_size;
1221 
1222 		if (bd_status & ENETC_RXBD_LSTATUS_F) {
1223 			dma_rmb();
1224 			size = le16_to_cpu((*rxbd)->r.buf_len);
1225 		}
1226 
1227 		enetc_add_rx_buff_to_skb(rx_ring, *i, size, skb);
1228 
1229 		(*cleaned_cnt)++;
1230 
1231 		enetc_rxbd_next(rx_ring, rxbd, i);
1232 	}
1233 
1234 	skb_record_rx_queue(skb, rx_ring->index);
1235 	skb->protocol = eth_type_trans(skb, rx_ring->ndev);
1236 
1237 	return skb;
1238 }
1239 
1240 #define ENETC_RXBD_BUNDLE 16 /* # of BDs to update at once */
1241 
enetc_clean_rx_ring(struct enetc_bdr * rx_ring,struct napi_struct * napi,int work_limit)1242 static int enetc_clean_rx_ring(struct enetc_bdr *rx_ring,
1243 			       struct napi_struct *napi, int work_limit)
1244 {
1245 	int rx_frm_cnt = 0, rx_byte_cnt = 0;
1246 	int cleaned_cnt, i;
1247 
1248 	cleaned_cnt = enetc_bd_unused(rx_ring);
1249 	/* next descriptor to process */
1250 	i = rx_ring->next_to_clean;
1251 
1252 	while (likely(rx_frm_cnt < work_limit)) {
1253 		union enetc_rx_bd *rxbd;
1254 		struct sk_buff *skb;
1255 		u32 bd_status;
1256 
1257 		if (cleaned_cnt >= ENETC_RXBD_BUNDLE)
1258 			cleaned_cnt -= enetc_refill_rx_ring(rx_ring,
1259 							    cleaned_cnt);
1260 
1261 		rxbd = enetc_rxbd(rx_ring, i);
1262 		bd_status = le32_to_cpu(rxbd->r.lstatus);
1263 		if (!bd_status)
1264 			break;
1265 
1266 		enetc_wr_reg_hot(rx_ring->idr, BIT(rx_ring->index));
1267 		dma_rmb(); /* for reading other rxbd fields */
1268 
1269 		if (enetc_check_bd_errors_and_consume(rx_ring, bd_status,
1270 						      &rxbd, &i))
1271 			break;
1272 
1273 		skb = enetc_build_skb(rx_ring, bd_status, &rxbd, &i,
1274 				      &cleaned_cnt, ENETC_RXB_DMA_SIZE);
1275 		if (!skb)
1276 			break;
1277 
1278 		/* When set, the outer VLAN header is extracted and reported
1279 		 * in the receive buffer descriptor. So rx_byte_cnt should
1280 		 * add the length of the extracted VLAN header.
1281 		 */
1282 		if (bd_status & ENETC_RXBD_FLAG_VLAN)
1283 			rx_byte_cnt += VLAN_HLEN;
1284 		rx_byte_cnt += skb->len + ETH_HLEN;
1285 		rx_frm_cnt++;
1286 
1287 		napi_gro_receive(napi, skb);
1288 	}
1289 
1290 	rx_ring->next_to_clean = i;
1291 
1292 	rx_ring->stats.packets += rx_frm_cnt;
1293 	rx_ring->stats.bytes += rx_byte_cnt;
1294 
1295 	return rx_frm_cnt;
1296 }
1297 
enetc_xdp_map_tx_buff(struct enetc_bdr * tx_ring,int i,struct enetc_tx_swbd * tx_swbd,int frm_len)1298 static void enetc_xdp_map_tx_buff(struct enetc_bdr *tx_ring, int i,
1299 				  struct enetc_tx_swbd *tx_swbd,
1300 				  int frm_len)
1301 {
1302 	union enetc_tx_bd *txbd = ENETC_TXBD(*tx_ring, i);
1303 
1304 	prefetchw(txbd);
1305 
1306 	enetc_clear_tx_bd(txbd);
1307 	txbd->addr = cpu_to_le64(tx_swbd->dma + tx_swbd->page_offset);
1308 	txbd->buf_len = cpu_to_le16(tx_swbd->len);
1309 	txbd->frm_len = cpu_to_le16(frm_len);
1310 
1311 	memcpy(&tx_ring->tx_swbd[i], tx_swbd, sizeof(*tx_swbd));
1312 }
1313 
1314 /* Puts in the TX ring one XDP frame, mapped as an array of TX software buffer
1315  * descriptors.
1316  */
enetc_xdp_tx(struct enetc_bdr * tx_ring,struct enetc_tx_swbd * xdp_tx_arr,int num_tx_swbd)1317 static bool enetc_xdp_tx(struct enetc_bdr *tx_ring,
1318 			 struct enetc_tx_swbd *xdp_tx_arr, int num_tx_swbd)
1319 {
1320 	struct enetc_tx_swbd *tmp_tx_swbd = xdp_tx_arr;
1321 	int i, k, frm_len = tmp_tx_swbd->len;
1322 
1323 	if (unlikely(enetc_bd_unused(tx_ring) < ENETC_TXBDS_NEEDED(num_tx_swbd)))
1324 		return false;
1325 
1326 	while (unlikely(!tmp_tx_swbd->is_eof)) {
1327 		tmp_tx_swbd++;
1328 		frm_len += tmp_tx_swbd->len;
1329 	}
1330 
1331 	i = tx_ring->next_to_use;
1332 
1333 	for (k = 0; k < num_tx_swbd; k++) {
1334 		struct enetc_tx_swbd *xdp_tx_swbd = &xdp_tx_arr[k];
1335 
1336 		enetc_xdp_map_tx_buff(tx_ring, i, xdp_tx_swbd, frm_len);
1337 
1338 		/* last BD needs 'F' bit set */
1339 		if (xdp_tx_swbd->is_eof) {
1340 			union enetc_tx_bd *txbd = ENETC_TXBD(*tx_ring, i);
1341 
1342 			txbd->flags = ENETC_TXBD_FLAGS_F;
1343 		}
1344 
1345 		enetc_bdr_idx_inc(tx_ring, &i);
1346 	}
1347 
1348 	tx_ring->next_to_use = i;
1349 
1350 	return true;
1351 }
1352 
enetc_xdp_frame_to_xdp_tx_swbd(struct enetc_bdr * tx_ring,struct enetc_tx_swbd * xdp_tx_arr,struct xdp_frame * xdp_frame)1353 static int enetc_xdp_frame_to_xdp_tx_swbd(struct enetc_bdr *tx_ring,
1354 					  struct enetc_tx_swbd *xdp_tx_arr,
1355 					  struct xdp_frame *xdp_frame)
1356 {
1357 	struct enetc_tx_swbd *xdp_tx_swbd = &xdp_tx_arr[0];
1358 	struct skb_shared_info *shinfo;
1359 	void *data = xdp_frame->data;
1360 	int len = xdp_frame->len;
1361 	skb_frag_t *frag;
1362 	dma_addr_t dma;
1363 	unsigned int f;
1364 	int n = 0;
1365 
1366 	dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE);
1367 	if (unlikely(dma_mapping_error(tx_ring->dev, dma))) {
1368 		netdev_err(tx_ring->ndev, "DMA map error\n");
1369 		return -1;
1370 	}
1371 
1372 	xdp_tx_swbd->dma = dma;
1373 	xdp_tx_swbd->dir = DMA_TO_DEVICE;
1374 	xdp_tx_swbd->len = len;
1375 	xdp_tx_swbd->is_xdp_redirect = true;
1376 	xdp_tx_swbd->is_eof = false;
1377 	xdp_tx_swbd->xdp_frame = NULL;
1378 
1379 	n++;
1380 
1381 	if (!xdp_frame_has_frags(xdp_frame))
1382 		goto out;
1383 
1384 	xdp_tx_swbd = &xdp_tx_arr[n];
1385 
1386 	shinfo = xdp_get_shared_info_from_frame(xdp_frame);
1387 
1388 	for (f = 0, frag = &shinfo->frags[0]; f < shinfo->nr_frags;
1389 	     f++, frag++) {
1390 		data = skb_frag_address(frag);
1391 		len = skb_frag_size(frag);
1392 
1393 		dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE);
1394 		if (unlikely(dma_mapping_error(tx_ring->dev, dma))) {
1395 			/* Undo the DMA mapping for all fragments */
1396 			while (--n >= 0)
1397 				enetc_unmap_tx_buff(tx_ring, &xdp_tx_arr[n]);
1398 
1399 			netdev_err(tx_ring->ndev, "DMA map error\n");
1400 			return -1;
1401 		}
1402 
1403 		xdp_tx_swbd->dma = dma;
1404 		xdp_tx_swbd->dir = DMA_TO_DEVICE;
1405 		xdp_tx_swbd->len = len;
1406 		xdp_tx_swbd->is_xdp_redirect = true;
1407 		xdp_tx_swbd->is_eof = false;
1408 		xdp_tx_swbd->xdp_frame = NULL;
1409 
1410 		n++;
1411 		xdp_tx_swbd = &xdp_tx_arr[n];
1412 	}
1413 out:
1414 	xdp_tx_arr[n - 1].is_eof = true;
1415 	xdp_tx_arr[n - 1].xdp_frame = xdp_frame;
1416 
1417 	return n;
1418 }
1419 
enetc_xdp_xmit(struct net_device * ndev,int num_frames,struct xdp_frame ** frames,u32 flags)1420 int enetc_xdp_xmit(struct net_device *ndev, int num_frames,
1421 		   struct xdp_frame **frames, u32 flags)
1422 {
1423 	struct enetc_tx_swbd xdp_redirect_arr[ENETC_MAX_SKB_FRAGS] = {0};
1424 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
1425 	struct enetc_bdr *tx_ring;
1426 	int xdp_tx_bd_cnt, i, k;
1427 	int xdp_tx_frm_cnt = 0;
1428 
1429 	if (unlikely(test_bit(ENETC_TX_DOWN, &priv->flags)))
1430 		return -ENETDOWN;
1431 
1432 	enetc_lock_mdio();
1433 
1434 	tx_ring = priv->xdp_tx_ring[smp_processor_id()];
1435 
1436 	prefetchw(ENETC_TXBD(*tx_ring, tx_ring->next_to_use));
1437 
1438 	for (k = 0; k < num_frames; k++) {
1439 		xdp_tx_bd_cnt = enetc_xdp_frame_to_xdp_tx_swbd(tx_ring,
1440 							       xdp_redirect_arr,
1441 							       frames[k]);
1442 		if (unlikely(xdp_tx_bd_cnt < 0))
1443 			break;
1444 
1445 		if (unlikely(!enetc_xdp_tx(tx_ring, xdp_redirect_arr,
1446 					   xdp_tx_bd_cnt))) {
1447 			for (i = 0; i < xdp_tx_bd_cnt; i++)
1448 				enetc_unmap_tx_buff(tx_ring,
1449 						    &xdp_redirect_arr[i]);
1450 			tx_ring->stats.xdp_tx_drops++;
1451 			break;
1452 		}
1453 
1454 		xdp_tx_frm_cnt++;
1455 	}
1456 
1457 	if (unlikely((flags & XDP_XMIT_FLUSH) || k != xdp_tx_frm_cnt))
1458 		enetc_update_tx_ring_tail(tx_ring);
1459 
1460 	tx_ring->stats.xdp_tx += xdp_tx_frm_cnt;
1461 
1462 	enetc_unlock_mdio();
1463 
1464 	return xdp_tx_frm_cnt;
1465 }
1466 EXPORT_SYMBOL_GPL(enetc_xdp_xmit);
1467 
enetc_map_rx_buff_to_xdp(struct enetc_bdr * rx_ring,int i,struct xdp_buff * xdp_buff,u16 size)1468 static void enetc_map_rx_buff_to_xdp(struct enetc_bdr *rx_ring, int i,
1469 				     struct xdp_buff *xdp_buff, u16 size)
1470 {
1471 	struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size);
1472 	void *hard_start = page_address(rx_swbd->page) + rx_swbd->page_offset;
1473 
1474 	/* To be used for XDP_TX */
1475 	rx_swbd->len = size;
1476 
1477 	xdp_prepare_buff(xdp_buff, hard_start - rx_ring->buffer_offset,
1478 			 rx_ring->buffer_offset, size, false);
1479 }
1480 
enetc_add_rx_buff_to_xdp(struct enetc_bdr * rx_ring,int i,u16 size,struct xdp_buff * xdp_buff)1481 static void enetc_add_rx_buff_to_xdp(struct enetc_bdr *rx_ring, int i,
1482 				     u16 size, struct xdp_buff *xdp_buff)
1483 {
1484 	struct skb_shared_info *shinfo = xdp_get_shared_info_from_buff(xdp_buff);
1485 	struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size);
1486 	skb_frag_t *frag;
1487 
1488 	/* To be used for XDP_TX */
1489 	rx_swbd->len = size;
1490 
1491 	if (!xdp_buff_has_frags(xdp_buff)) {
1492 		xdp_buff_set_frags_flag(xdp_buff);
1493 		shinfo->xdp_frags_size = size;
1494 		shinfo->nr_frags = 0;
1495 	} else {
1496 		shinfo->xdp_frags_size += size;
1497 	}
1498 
1499 	if (page_is_pfmemalloc(rx_swbd->page))
1500 		xdp_buff_set_frag_pfmemalloc(xdp_buff);
1501 
1502 	frag = &shinfo->frags[shinfo->nr_frags];
1503 	skb_frag_fill_page_desc(frag, rx_swbd->page, rx_swbd->page_offset,
1504 				size);
1505 
1506 	shinfo->nr_frags++;
1507 }
1508 
enetc_build_xdp_buff(struct enetc_bdr * rx_ring,u32 bd_status,union enetc_rx_bd ** rxbd,int * i,int * cleaned_cnt,struct xdp_buff * xdp_buff)1509 static void enetc_build_xdp_buff(struct enetc_bdr *rx_ring, u32 bd_status,
1510 				 union enetc_rx_bd **rxbd, int *i,
1511 				 int *cleaned_cnt, struct xdp_buff *xdp_buff)
1512 {
1513 	u16 size = le16_to_cpu((*rxbd)->r.buf_len);
1514 
1515 	xdp_init_buff(xdp_buff, ENETC_RXB_TRUESIZE, &rx_ring->xdp.rxq);
1516 
1517 	enetc_map_rx_buff_to_xdp(rx_ring, *i, xdp_buff, size);
1518 	(*cleaned_cnt)++;
1519 	enetc_rxbd_next(rx_ring, rxbd, i);
1520 
1521 	/* not last BD in frame? */
1522 	while (!(bd_status & ENETC_RXBD_LSTATUS_F)) {
1523 		bd_status = le32_to_cpu((*rxbd)->r.lstatus);
1524 		size = ENETC_RXB_DMA_SIZE_XDP;
1525 
1526 		if (bd_status & ENETC_RXBD_LSTATUS_F) {
1527 			dma_rmb();
1528 			size = le16_to_cpu((*rxbd)->r.buf_len);
1529 		}
1530 
1531 		enetc_add_rx_buff_to_xdp(rx_ring, *i, size, xdp_buff);
1532 		(*cleaned_cnt)++;
1533 		enetc_rxbd_next(rx_ring, rxbd, i);
1534 	}
1535 }
1536 
1537 /* Convert RX buffer descriptors to TX buffer descriptors. These will be
1538  * recycled back into the RX ring in enetc_clean_tx_ring.
1539  */
enetc_rx_swbd_to_xdp_tx_swbd(struct enetc_tx_swbd * xdp_tx_arr,struct enetc_bdr * rx_ring,int rx_ring_first,int rx_ring_last)1540 static int enetc_rx_swbd_to_xdp_tx_swbd(struct enetc_tx_swbd *xdp_tx_arr,
1541 					struct enetc_bdr *rx_ring,
1542 					int rx_ring_first, int rx_ring_last)
1543 {
1544 	int n = 0;
1545 
1546 	for (; rx_ring_first != rx_ring_last;
1547 	     n++, enetc_bdr_idx_inc(rx_ring, &rx_ring_first)) {
1548 		struct enetc_rx_swbd *rx_swbd = &rx_ring->rx_swbd[rx_ring_first];
1549 		struct enetc_tx_swbd *tx_swbd = &xdp_tx_arr[n];
1550 
1551 		/* No need to dma_map, we already have DMA_BIDIRECTIONAL */
1552 		tx_swbd->dma = rx_swbd->dma;
1553 		tx_swbd->dir = rx_swbd->dir;
1554 		tx_swbd->page = rx_swbd->page;
1555 		tx_swbd->page_offset = rx_swbd->page_offset;
1556 		tx_swbd->len = rx_swbd->len;
1557 		tx_swbd->is_dma_page = true;
1558 		tx_swbd->is_xdp_tx = true;
1559 		tx_swbd->is_eof = false;
1560 	}
1561 
1562 	/* We rely on caller providing an rx_ring_last > rx_ring_first */
1563 	xdp_tx_arr[n - 1].is_eof = true;
1564 
1565 	return n;
1566 }
1567 
enetc_xdp_drop(struct enetc_bdr * rx_ring,int rx_ring_first,int rx_ring_last)1568 static void enetc_xdp_drop(struct enetc_bdr *rx_ring, int rx_ring_first,
1569 			   int rx_ring_last)
1570 {
1571 	while (rx_ring_first != rx_ring_last) {
1572 		enetc_put_rx_buff(rx_ring,
1573 				  &rx_ring->rx_swbd[rx_ring_first]);
1574 		enetc_bdr_idx_inc(rx_ring, &rx_ring_first);
1575 	}
1576 }
1577 
enetc_clean_rx_ring_xdp(struct enetc_bdr * rx_ring,struct napi_struct * napi,int work_limit,struct bpf_prog * prog)1578 static int enetc_clean_rx_ring_xdp(struct enetc_bdr *rx_ring,
1579 				   struct napi_struct *napi, int work_limit,
1580 				   struct bpf_prog *prog)
1581 {
1582 	int xdp_tx_bd_cnt, xdp_tx_frm_cnt = 0, xdp_redirect_frm_cnt = 0;
1583 	struct enetc_tx_swbd xdp_tx_arr[ENETC_MAX_SKB_FRAGS] = {0};
1584 	struct enetc_ndev_priv *priv = netdev_priv(rx_ring->ndev);
1585 	int rx_frm_cnt = 0, rx_byte_cnt = 0;
1586 	struct enetc_bdr *tx_ring;
1587 	int cleaned_cnt, i;
1588 	u32 xdp_act;
1589 
1590 	cleaned_cnt = enetc_bd_unused(rx_ring);
1591 	/* next descriptor to process */
1592 	i = rx_ring->next_to_clean;
1593 
1594 	while (likely(rx_frm_cnt < work_limit)) {
1595 		union enetc_rx_bd *rxbd, *orig_rxbd;
1596 		int orig_i, orig_cleaned_cnt;
1597 		struct xdp_buff xdp_buff;
1598 		struct sk_buff *skb;
1599 		u32 bd_status;
1600 		int err;
1601 
1602 		rxbd = enetc_rxbd(rx_ring, i);
1603 		bd_status = le32_to_cpu(rxbd->r.lstatus);
1604 		if (!bd_status)
1605 			break;
1606 
1607 		enetc_wr_reg_hot(rx_ring->idr, BIT(rx_ring->index));
1608 		dma_rmb(); /* for reading other rxbd fields */
1609 
1610 		if (enetc_check_bd_errors_and_consume(rx_ring, bd_status,
1611 						      &rxbd, &i))
1612 			break;
1613 
1614 		orig_rxbd = rxbd;
1615 		orig_cleaned_cnt = cleaned_cnt;
1616 		orig_i = i;
1617 
1618 		enetc_build_xdp_buff(rx_ring, bd_status, &rxbd, &i,
1619 				     &cleaned_cnt, &xdp_buff);
1620 
1621 		/* When set, the outer VLAN header is extracted and reported
1622 		 * in the receive buffer descriptor. So rx_byte_cnt should
1623 		 * add the length of the extracted VLAN header.
1624 		 */
1625 		if (bd_status & ENETC_RXBD_FLAG_VLAN)
1626 			rx_byte_cnt += VLAN_HLEN;
1627 		rx_byte_cnt += xdp_get_buff_len(&xdp_buff);
1628 
1629 		xdp_act = bpf_prog_run_xdp(prog, &xdp_buff);
1630 
1631 		switch (xdp_act) {
1632 		default:
1633 			bpf_warn_invalid_xdp_action(rx_ring->ndev, prog, xdp_act);
1634 			fallthrough;
1635 		case XDP_ABORTED:
1636 			trace_xdp_exception(rx_ring->ndev, prog, xdp_act);
1637 			fallthrough;
1638 		case XDP_DROP:
1639 			enetc_xdp_drop(rx_ring, orig_i, i);
1640 			rx_ring->stats.xdp_drops++;
1641 			break;
1642 		case XDP_PASS:
1643 			rxbd = orig_rxbd;
1644 			cleaned_cnt = orig_cleaned_cnt;
1645 			i = orig_i;
1646 
1647 			skb = enetc_build_skb(rx_ring, bd_status, &rxbd,
1648 					      &i, &cleaned_cnt,
1649 					      ENETC_RXB_DMA_SIZE_XDP);
1650 			if (unlikely(!skb))
1651 				goto out;
1652 
1653 			napi_gro_receive(napi, skb);
1654 			break;
1655 		case XDP_TX:
1656 			tx_ring = priv->xdp_tx_ring[rx_ring->index];
1657 			if (unlikely(test_bit(ENETC_TX_DOWN, &priv->flags))) {
1658 				enetc_xdp_drop(rx_ring, orig_i, i);
1659 				tx_ring->stats.xdp_tx_drops++;
1660 				break;
1661 			}
1662 
1663 			xdp_tx_bd_cnt = enetc_rx_swbd_to_xdp_tx_swbd(xdp_tx_arr,
1664 								     rx_ring,
1665 								     orig_i, i);
1666 
1667 			if (!enetc_xdp_tx(tx_ring, xdp_tx_arr, xdp_tx_bd_cnt)) {
1668 				enetc_xdp_drop(rx_ring, orig_i, i);
1669 				tx_ring->stats.xdp_tx_drops++;
1670 			} else {
1671 				tx_ring->stats.xdp_tx++;
1672 				rx_ring->xdp.xdp_tx_in_flight += xdp_tx_bd_cnt;
1673 				xdp_tx_frm_cnt++;
1674 				/* The XDP_TX enqueue was successful, so we
1675 				 * need to scrub the RX software BDs because
1676 				 * the ownership of the buffers no longer
1677 				 * belongs to the RX ring, and we must prevent
1678 				 * enetc_refill_rx_ring() from reusing
1679 				 * rx_swbd->page.
1680 				 */
1681 				while (orig_i != i) {
1682 					rx_ring->rx_swbd[orig_i].page = NULL;
1683 					enetc_bdr_idx_inc(rx_ring, &orig_i);
1684 				}
1685 			}
1686 			break;
1687 		case XDP_REDIRECT:
1688 			err = xdp_do_redirect(rx_ring->ndev, &xdp_buff, prog);
1689 			if (unlikely(err)) {
1690 				enetc_xdp_drop(rx_ring, orig_i, i);
1691 				rx_ring->stats.xdp_redirect_failures++;
1692 			} else {
1693 				while (orig_i != i) {
1694 					enetc_flip_rx_buff(rx_ring,
1695 							   &rx_ring->rx_swbd[orig_i]);
1696 					enetc_bdr_idx_inc(rx_ring, &orig_i);
1697 				}
1698 				xdp_redirect_frm_cnt++;
1699 				rx_ring->stats.xdp_redirect++;
1700 			}
1701 		}
1702 
1703 		rx_frm_cnt++;
1704 	}
1705 
1706 out:
1707 	rx_ring->next_to_clean = i;
1708 
1709 	rx_ring->stats.packets += rx_frm_cnt;
1710 	rx_ring->stats.bytes += rx_byte_cnt;
1711 
1712 	if (xdp_redirect_frm_cnt)
1713 		xdp_do_flush_map();
1714 
1715 	if (xdp_tx_frm_cnt)
1716 		enetc_update_tx_ring_tail(tx_ring);
1717 
1718 	if (cleaned_cnt > rx_ring->xdp.xdp_tx_in_flight)
1719 		enetc_refill_rx_ring(rx_ring, enetc_bd_unused(rx_ring) -
1720 				     rx_ring->xdp.xdp_tx_in_flight);
1721 
1722 	return rx_frm_cnt;
1723 }
1724 
enetc_poll(struct napi_struct * napi,int budget)1725 static int enetc_poll(struct napi_struct *napi, int budget)
1726 {
1727 	struct enetc_int_vector
1728 		*v = container_of(napi, struct enetc_int_vector, napi);
1729 	struct enetc_bdr *rx_ring = &v->rx_ring;
1730 	struct bpf_prog *prog;
1731 	bool complete = true;
1732 	int work_done;
1733 	int i;
1734 
1735 	enetc_lock_mdio();
1736 
1737 	for (i = 0; i < v->count_tx_rings; i++)
1738 		if (!enetc_clean_tx_ring(&v->tx_ring[i], budget))
1739 			complete = false;
1740 
1741 	prog = rx_ring->xdp.prog;
1742 	if (prog)
1743 		work_done = enetc_clean_rx_ring_xdp(rx_ring, napi, budget, prog);
1744 	else
1745 		work_done = enetc_clean_rx_ring(rx_ring, napi, budget);
1746 	if (work_done == budget)
1747 		complete = false;
1748 	if (work_done)
1749 		v->rx_napi_work = true;
1750 
1751 	if (!complete) {
1752 		enetc_unlock_mdio();
1753 		return budget;
1754 	}
1755 
1756 	napi_complete_done(napi, work_done);
1757 
1758 	if (likely(v->rx_dim_en))
1759 		enetc_rx_net_dim(v);
1760 
1761 	v->rx_napi_work = false;
1762 
1763 	/* enable interrupts */
1764 	enetc_wr_reg_hot(v->rbier, ENETC_RBIER_RXTIE);
1765 
1766 	for_each_set_bit(i, &v->tx_rings_map, ENETC_MAX_NUM_TXQS)
1767 		enetc_wr_reg_hot(v->tbier_base + ENETC_BDR_OFF(i),
1768 				 ENETC_TBIER_TXTIE);
1769 
1770 	enetc_unlock_mdio();
1771 
1772 	return work_done;
1773 }
1774 
1775 /* Probing and Init */
1776 #define ENETC_MAX_RFS_SIZE 64
enetc_get_si_caps(struct enetc_si * si)1777 void enetc_get_si_caps(struct enetc_si *si)
1778 {
1779 	struct enetc_hw *hw = &si->hw;
1780 	u32 val;
1781 
1782 	/* find out how many of various resources we have to work with */
1783 	val = enetc_rd(hw, ENETC_SICAPR0);
1784 	si->num_rx_rings = (val >> 16) & 0xff;
1785 	si->num_tx_rings = val & 0xff;
1786 
1787 	val = enetc_rd(hw, ENETC_SIRFSCAPR);
1788 	si->num_fs_entries = ENETC_SIRFSCAPR_GET_NUM_RFS(val);
1789 	si->num_fs_entries = min(si->num_fs_entries, ENETC_MAX_RFS_SIZE);
1790 
1791 	si->num_rss = 0;
1792 	val = enetc_rd(hw, ENETC_SIPCAPR0);
1793 	if (val & ENETC_SIPCAPR0_RSS) {
1794 		u32 rss;
1795 
1796 		rss = enetc_rd(hw, ENETC_SIRSSCAPR);
1797 		si->num_rss = ENETC_SIRSSCAPR_GET_NUM_RSS(rss);
1798 	}
1799 
1800 	if (val & ENETC_SIPCAPR0_QBV)
1801 		si->hw_features |= ENETC_SI_F_QBV;
1802 
1803 	if (val & ENETC_SIPCAPR0_QBU)
1804 		si->hw_features |= ENETC_SI_F_QBU;
1805 
1806 	if (val & ENETC_SIPCAPR0_PSFP)
1807 		si->hw_features |= ENETC_SI_F_PSFP;
1808 }
1809 EXPORT_SYMBOL_GPL(enetc_get_si_caps);
1810 
enetc_dma_alloc_bdr(struct enetc_bdr_resource * res)1811 static int enetc_dma_alloc_bdr(struct enetc_bdr_resource *res)
1812 {
1813 	size_t bd_base_size = res->bd_count * res->bd_size;
1814 
1815 	res->bd_base = dma_alloc_coherent(res->dev, bd_base_size,
1816 					  &res->bd_dma_base, GFP_KERNEL);
1817 	if (!res->bd_base)
1818 		return -ENOMEM;
1819 
1820 	/* h/w requires 128B alignment */
1821 	if (!IS_ALIGNED(res->bd_dma_base, 128)) {
1822 		dma_free_coherent(res->dev, bd_base_size, res->bd_base,
1823 				  res->bd_dma_base);
1824 		return -EINVAL;
1825 	}
1826 
1827 	return 0;
1828 }
1829 
enetc_dma_free_bdr(const struct enetc_bdr_resource * res)1830 static void enetc_dma_free_bdr(const struct enetc_bdr_resource *res)
1831 {
1832 	size_t bd_base_size = res->bd_count * res->bd_size;
1833 
1834 	dma_free_coherent(res->dev, bd_base_size, res->bd_base,
1835 			  res->bd_dma_base);
1836 }
1837 
enetc_alloc_tx_resource(struct enetc_bdr_resource * res,struct device * dev,size_t bd_count)1838 static int enetc_alloc_tx_resource(struct enetc_bdr_resource *res,
1839 				   struct device *dev, size_t bd_count)
1840 {
1841 	int err;
1842 
1843 	res->dev = dev;
1844 	res->bd_count = bd_count;
1845 	res->bd_size = sizeof(union enetc_tx_bd);
1846 
1847 	res->tx_swbd = vcalloc(bd_count, sizeof(*res->tx_swbd));
1848 	if (!res->tx_swbd)
1849 		return -ENOMEM;
1850 
1851 	err = enetc_dma_alloc_bdr(res);
1852 	if (err)
1853 		goto err_alloc_bdr;
1854 
1855 	res->tso_headers = dma_alloc_coherent(dev, bd_count * TSO_HEADER_SIZE,
1856 					      &res->tso_headers_dma,
1857 					      GFP_KERNEL);
1858 	if (!res->tso_headers) {
1859 		err = -ENOMEM;
1860 		goto err_alloc_tso;
1861 	}
1862 
1863 	return 0;
1864 
1865 err_alloc_tso:
1866 	enetc_dma_free_bdr(res);
1867 err_alloc_bdr:
1868 	vfree(res->tx_swbd);
1869 	res->tx_swbd = NULL;
1870 
1871 	return err;
1872 }
1873 
enetc_free_tx_resource(const struct enetc_bdr_resource * res)1874 static void enetc_free_tx_resource(const struct enetc_bdr_resource *res)
1875 {
1876 	dma_free_coherent(res->dev, res->bd_count * TSO_HEADER_SIZE,
1877 			  res->tso_headers, res->tso_headers_dma);
1878 	enetc_dma_free_bdr(res);
1879 	vfree(res->tx_swbd);
1880 }
1881 
1882 static struct enetc_bdr_resource *
enetc_alloc_tx_resources(struct enetc_ndev_priv * priv)1883 enetc_alloc_tx_resources(struct enetc_ndev_priv *priv)
1884 {
1885 	struct enetc_bdr_resource *tx_res;
1886 	int i, err;
1887 
1888 	tx_res = kcalloc(priv->num_tx_rings, sizeof(*tx_res), GFP_KERNEL);
1889 	if (!tx_res)
1890 		return ERR_PTR(-ENOMEM);
1891 
1892 	for (i = 0; i < priv->num_tx_rings; i++) {
1893 		struct enetc_bdr *tx_ring = priv->tx_ring[i];
1894 
1895 		err = enetc_alloc_tx_resource(&tx_res[i], tx_ring->dev,
1896 					      tx_ring->bd_count);
1897 		if (err)
1898 			goto fail;
1899 	}
1900 
1901 	return tx_res;
1902 
1903 fail:
1904 	while (i-- > 0)
1905 		enetc_free_tx_resource(&tx_res[i]);
1906 
1907 	kfree(tx_res);
1908 
1909 	return ERR_PTR(err);
1910 }
1911 
enetc_free_tx_resources(const struct enetc_bdr_resource * tx_res,size_t num_resources)1912 static void enetc_free_tx_resources(const struct enetc_bdr_resource *tx_res,
1913 				    size_t num_resources)
1914 {
1915 	size_t i;
1916 
1917 	for (i = 0; i < num_resources; i++)
1918 		enetc_free_tx_resource(&tx_res[i]);
1919 
1920 	kfree(tx_res);
1921 }
1922 
enetc_alloc_rx_resource(struct enetc_bdr_resource * res,struct device * dev,size_t bd_count,bool extended)1923 static int enetc_alloc_rx_resource(struct enetc_bdr_resource *res,
1924 				   struct device *dev, size_t bd_count,
1925 				   bool extended)
1926 {
1927 	int err;
1928 
1929 	res->dev = dev;
1930 	res->bd_count = bd_count;
1931 	res->bd_size = sizeof(union enetc_rx_bd);
1932 	if (extended)
1933 		res->bd_size *= 2;
1934 
1935 	res->rx_swbd = vcalloc(bd_count, sizeof(struct enetc_rx_swbd));
1936 	if (!res->rx_swbd)
1937 		return -ENOMEM;
1938 
1939 	err = enetc_dma_alloc_bdr(res);
1940 	if (err) {
1941 		vfree(res->rx_swbd);
1942 		return err;
1943 	}
1944 
1945 	return 0;
1946 }
1947 
enetc_free_rx_resource(const struct enetc_bdr_resource * res)1948 static void enetc_free_rx_resource(const struct enetc_bdr_resource *res)
1949 {
1950 	enetc_dma_free_bdr(res);
1951 	vfree(res->rx_swbd);
1952 }
1953 
1954 static struct enetc_bdr_resource *
enetc_alloc_rx_resources(struct enetc_ndev_priv * priv,bool extended)1955 enetc_alloc_rx_resources(struct enetc_ndev_priv *priv, bool extended)
1956 {
1957 	struct enetc_bdr_resource *rx_res;
1958 	int i, err;
1959 
1960 	rx_res = kcalloc(priv->num_rx_rings, sizeof(*rx_res), GFP_KERNEL);
1961 	if (!rx_res)
1962 		return ERR_PTR(-ENOMEM);
1963 
1964 	for (i = 0; i < priv->num_rx_rings; i++) {
1965 		struct enetc_bdr *rx_ring = priv->rx_ring[i];
1966 
1967 		err = enetc_alloc_rx_resource(&rx_res[i], rx_ring->dev,
1968 					      rx_ring->bd_count, extended);
1969 		if (err)
1970 			goto fail;
1971 	}
1972 
1973 	return rx_res;
1974 
1975 fail:
1976 	while (i-- > 0)
1977 		enetc_free_rx_resource(&rx_res[i]);
1978 
1979 	kfree(rx_res);
1980 
1981 	return ERR_PTR(err);
1982 }
1983 
enetc_free_rx_resources(const struct enetc_bdr_resource * rx_res,size_t num_resources)1984 static void enetc_free_rx_resources(const struct enetc_bdr_resource *rx_res,
1985 				    size_t num_resources)
1986 {
1987 	size_t i;
1988 
1989 	for (i = 0; i < num_resources; i++)
1990 		enetc_free_rx_resource(&rx_res[i]);
1991 
1992 	kfree(rx_res);
1993 }
1994 
enetc_assign_tx_resource(struct enetc_bdr * tx_ring,const struct enetc_bdr_resource * res)1995 static void enetc_assign_tx_resource(struct enetc_bdr *tx_ring,
1996 				     const struct enetc_bdr_resource *res)
1997 {
1998 	tx_ring->bd_base = res ? res->bd_base : NULL;
1999 	tx_ring->bd_dma_base = res ? res->bd_dma_base : 0;
2000 	tx_ring->tx_swbd = res ? res->tx_swbd : NULL;
2001 	tx_ring->tso_headers = res ? res->tso_headers : NULL;
2002 	tx_ring->tso_headers_dma = res ? res->tso_headers_dma : 0;
2003 }
2004 
enetc_assign_rx_resource(struct enetc_bdr * rx_ring,const struct enetc_bdr_resource * res)2005 static void enetc_assign_rx_resource(struct enetc_bdr *rx_ring,
2006 				     const struct enetc_bdr_resource *res)
2007 {
2008 	rx_ring->bd_base = res ? res->bd_base : NULL;
2009 	rx_ring->bd_dma_base = res ? res->bd_dma_base : 0;
2010 	rx_ring->rx_swbd = res ? res->rx_swbd : NULL;
2011 }
2012 
enetc_assign_tx_resources(struct enetc_ndev_priv * priv,const struct enetc_bdr_resource * res)2013 static void enetc_assign_tx_resources(struct enetc_ndev_priv *priv,
2014 				      const struct enetc_bdr_resource *res)
2015 {
2016 	int i;
2017 
2018 	if (priv->tx_res)
2019 		enetc_free_tx_resources(priv->tx_res, priv->num_tx_rings);
2020 
2021 	for (i = 0; i < priv->num_tx_rings; i++) {
2022 		enetc_assign_tx_resource(priv->tx_ring[i],
2023 					 res ? &res[i] : NULL);
2024 	}
2025 
2026 	priv->tx_res = res;
2027 }
2028 
enetc_assign_rx_resources(struct enetc_ndev_priv * priv,const struct enetc_bdr_resource * res)2029 static void enetc_assign_rx_resources(struct enetc_ndev_priv *priv,
2030 				      const struct enetc_bdr_resource *res)
2031 {
2032 	int i;
2033 
2034 	if (priv->rx_res)
2035 		enetc_free_rx_resources(priv->rx_res, priv->num_rx_rings);
2036 
2037 	for (i = 0; i < priv->num_rx_rings; i++) {
2038 		enetc_assign_rx_resource(priv->rx_ring[i],
2039 					 res ? &res[i] : NULL);
2040 	}
2041 
2042 	priv->rx_res = res;
2043 }
2044 
enetc_free_tx_ring(struct enetc_bdr * tx_ring)2045 static void enetc_free_tx_ring(struct enetc_bdr *tx_ring)
2046 {
2047 	int i;
2048 
2049 	for (i = 0; i < tx_ring->bd_count; i++) {
2050 		struct enetc_tx_swbd *tx_swbd = &tx_ring->tx_swbd[i];
2051 
2052 		enetc_free_tx_frame(tx_ring, tx_swbd);
2053 	}
2054 }
2055 
enetc_free_rx_ring(struct enetc_bdr * rx_ring)2056 static void enetc_free_rx_ring(struct enetc_bdr *rx_ring)
2057 {
2058 	int i;
2059 
2060 	for (i = 0; i < rx_ring->bd_count; i++) {
2061 		struct enetc_rx_swbd *rx_swbd = &rx_ring->rx_swbd[i];
2062 
2063 		if (!rx_swbd->page)
2064 			continue;
2065 
2066 		dma_unmap_page(rx_ring->dev, rx_swbd->dma, PAGE_SIZE,
2067 			       rx_swbd->dir);
2068 		__free_page(rx_swbd->page);
2069 		rx_swbd->page = NULL;
2070 	}
2071 }
2072 
enetc_free_rxtx_rings(struct enetc_ndev_priv * priv)2073 static void enetc_free_rxtx_rings(struct enetc_ndev_priv *priv)
2074 {
2075 	int i;
2076 
2077 	for (i = 0; i < priv->num_rx_rings; i++)
2078 		enetc_free_rx_ring(priv->rx_ring[i]);
2079 
2080 	for (i = 0; i < priv->num_tx_rings; i++)
2081 		enetc_free_tx_ring(priv->tx_ring[i]);
2082 }
2083 
enetc_setup_default_rss_table(struct enetc_si * si,int num_groups)2084 static int enetc_setup_default_rss_table(struct enetc_si *si, int num_groups)
2085 {
2086 	int *rss_table;
2087 	int i;
2088 
2089 	rss_table = kmalloc_array(si->num_rss, sizeof(*rss_table), GFP_KERNEL);
2090 	if (!rss_table)
2091 		return -ENOMEM;
2092 
2093 	/* Set up RSS table defaults */
2094 	for (i = 0; i < si->num_rss; i++)
2095 		rss_table[i] = i % num_groups;
2096 
2097 	enetc_set_rss_table(si, rss_table, si->num_rss);
2098 
2099 	kfree(rss_table);
2100 
2101 	return 0;
2102 }
2103 
enetc_configure_si(struct enetc_ndev_priv * priv)2104 int enetc_configure_si(struct enetc_ndev_priv *priv)
2105 {
2106 	struct enetc_si *si = priv->si;
2107 	struct enetc_hw *hw = &si->hw;
2108 	int err;
2109 
2110 	/* set SI cache attributes */
2111 	enetc_wr(hw, ENETC_SICAR0,
2112 		 ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT);
2113 	enetc_wr(hw, ENETC_SICAR1, ENETC_SICAR_MSI);
2114 	/* enable SI */
2115 	enetc_wr(hw, ENETC_SIMR, ENETC_SIMR_EN);
2116 
2117 	if (si->num_rss) {
2118 		err = enetc_setup_default_rss_table(si, priv->num_rx_rings);
2119 		if (err)
2120 			return err;
2121 	}
2122 
2123 	return 0;
2124 }
2125 EXPORT_SYMBOL_GPL(enetc_configure_si);
2126 
enetc_init_si_rings_params(struct enetc_ndev_priv * priv)2127 void enetc_init_si_rings_params(struct enetc_ndev_priv *priv)
2128 {
2129 	struct enetc_si *si = priv->si;
2130 	int cpus = num_online_cpus();
2131 
2132 	priv->tx_bd_count = ENETC_TX_RING_DEFAULT_SIZE;
2133 	priv->rx_bd_count = ENETC_RX_RING_DEFAULT_SIZE;
2134 
2135 	/* Enable all available TX rings in order to configure as many
2136 	 * priorities as possible, when needed.
2137 	 * TODO: Make # of TX rings run-time configurable
2138 	 */
2139 	priv->num_rx_rings = min_t(int, cpus, si->num_rx_rings);
2140 	priv->num_tx_rings = si->num_tx_rings;
2141 	priv->bdr_int_num = cpus;
2142 	priv->ic_mode = ENETC_IC_RX_ADAPTIVE | ENETC_IC_TX_MANUAL;
2143 	priv->tx_ictt = ENETC_TXIC_TIMETHR;
2144 }
2145 EXPORT_SYMBOL_GPL(enetc_init_si_rings_params);
2146 
enetc_alloc_si_resources(struct enetc_ndev_priv * priv)2147 int enetc_alloc_si_resources(struct enetc_ndev_priv *priv)
2148 {
2149 	struct enetc_si *si = priv->si;
2150 
2151 	priv->cls_rules = kcalloc(si->num_fs_entries, sizeof(*priv->cls_rules),
2152 				  GFP_KERNEL);
2153 	if (!priv->cls_rules)
2154 		return -ENOMEM;
2155 
2156 	return 0;
2157 }
2158 EXPORT_SYMBOL_GPL(enetc_alloc_si_resources);
2159 
enetc_free_si_resources(struct enetc_ndev_priv * priv)2160 void enetc_free_si_resources(struct enetc_ndev_priv *priv)
2161 {
2162 	kfree(priv->cls_rules);
2163 }
2164 EXPORT_SYMBOL_GPL(enetc_free_si_resources);
2165 
enetc_setup_txbdr(struct enetc_hw * hw,struct enetc_bdr * tx_ring)2166 static void enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring)
2167 {
2168 	int idx = tx_ring->index;
2169 	u32 tbmr;
2170 
2171 	enetc_txbdr_wr(hw, idx, ENETC_TBBAR0,
2172 		       lower_32_bits(tx_ring->bd_dma_base));
2173 
2174 	enetc_txbdr_wr(hw, idx, ENETC_TBBAR1,
2175 		       upper_32_bits(tx_ring->bd_dma_base));
2176 
2177 	WARN_ON(!IS_ALIGNED(tx_ring->bd_count, 64)); /* multiple of 64 */
2178 	enetc_txbdr_wr(hw, idx, ENETC_TBLENR,
2179 		       ENETC_RTBLENR_LEN(tx_ring->bd_count));
2180 
2181 	/* clearing PI/CI registers for Tx not supported, adjust sw indexes */
2182 	tx_ring->next_to_use = enetc_txbdr_rd(hw, idx, ENETC_TBPIR);
2183 	tx_ring->next_to_clean = enetc_txbdr_rd(hw, idx, ENETC_TBCIR);
2184 
2185 	/* enable Tx ints by setting pkt thr to 1 */
2186 	enetc_txbdr_wr(hw, idx, ENETC_TBICR0, ENETC_TBICR0_ICEN | 0x1);
2187 
2188 	tbmr = ENETC_TBMR_SET_PRIO(tx_ring->prio);
2189 	if (tx_ring->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
2190 		tbmr |= ENETC_TBMR_VIH;
2191 
2192 	/* enable ring */
2193 	enetc_txbdr_wr(hw, idx, ENETC_TBMR, tbmr);
2194 
2195 	tx_ring->tpir = hw->reg + ENETC_BDR(TX, idx, ENETC_TBPIR);
2196 	tx_ring->tcir = hw->reg + ENETC_BDR(TX, idx, ENETC_TBCIR);
2197 	tx_ring->idr = hw->reg + ENETC_SITXIDR;
2198 }
2199 
enetc_setup_rxbdr(struct enetc_hw * hw,struct enetc_bdr * rx_ring,bool extended)2200 static void enetc_setup_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring,
2201 			      bool extended)
2202 {
2203 	int idx = rx_ring->index;
2204 	u32 rbmr = 0;
2205 
2206 	enetc_rxbdr_wr(hw, idx, ENETC_RBBAR0,
2207 		       lower_32_bits(rx_ring->bd_dma_base));
2208 
2209 	enetc_rxbdr_wr(hw, idx, ENETC_RBBAR1,
2210 		       upper_32_bits(rx_ring->bd_dma_base));
2211 
2212 	WARN_ON(!IS_ALIGNED(rx_ring->bd_count, 64)); /* multiple of 64 */
2213 	enetc_rxbdr_wr(hw, idx, ENETC_RBLENR,
2214 		       ENETC_RTBLENR_LEN(rx_ring->bd_count));
2215 
2216 	if (rx_ring->xdp.prog)
2217 		enetc_rxbdr_wr(hw, idx, ENETC_RBBSR, ENETC_RXB_DMA_SIZE_XDP);
2218 	else
2219 		enetc_rxbdr_wr(hw, idx, ENETC_RBBSR, ENETC_RXB_DMA_SIZE);
2220 
2221 	/* Also prepare the consumer index in case page allocation never
2222 	 * succeeds. In that case, hardware will never advance producer index
2223 	 * to match consumer index, and will drop all frames.
2224 	 */
2225 	enetc_rxbdr_wr(hw, idx, ENETC_RBPIR, 0);
2226 	enetc_rxbdr_wr(hw, idx, ENETC_RBCIR, 1);
2227 
2228 	/* enable Rx ints by setting pkt thr to 1 */
2229 	enetc_rxbdr_wr(hw, idx, ENETC_RBICR0, ENETC_RBICR0_ICEN | 0x1);
2230 
2231 	rx_ring->ext_en = extended;
2232 	if (rx_ring->ext_en)
2233 		rbmr |= ENETC_RBMR_BDS;
2234 
2235 	if (rx_ring->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
2236 		rbmr |= ENETC_RBMR_VTE;
2237 
2238 	rx_ring->rcir = hw->reg + ENETC_BDR(RX, idx, ENETC_RBCIR);
2239 	rx_ring->idr = hw->reg + ENETC_SIRXIDR;
2240 
2241 	rx_ring->next_to_clean = 0;
2242 	rx_ring->next_to_use = 0;
2243 	rx_ring->next_to_alloc = 0;
2244 
2245 	enetc_lock_mdio();
2246 	enetc_refill_rx_ring(rx_ring, enetc_bd_unused(rx_ring));
2247 	enetc_unlock_mdio();
2248 
2249 	enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr);
2250 }
2251 
enetc_setup_bdrs(struct enetc_ndev_priv * priv,bool extended)2252 static void enetc_setup_bdrs(struct enetc_ndev_priv *priv, bool extended)
2253 {
2254 	struct enetc_hw *hw = &priv->si->hw;
2255 	int i;
2256 
2257 	for (i = 0; i < priv->num_tx_rings; i++)
2258 		enetc_setup_txbdr(hw, priv->tx_ring[i]);
2259 
2260 	for (i = 0; i < priv->num_rx_rings; i++)
2261 		enetc_setup_rxbdr(hw, priv->rx_ring[i], extended);
2262 }
2263 
enetc_enable_txbdr(struct enetc_hw * hw,struct enetc_bdr * tx_ring)2264 static void enetc_enable_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring)
2265 {
2266 	int idx = tx_ring->index;
2267 	u32 tbmr;
2268 
2269 	tbmr = enetc_txbdr_rd(hw, idx, ENETC_TBMR);
2270 	tbmr |= ENETC_TBMR_EN;
2271 	enetc_txbdr_wr(hw, idx, ENETC_TBMR, tbmr);
2272 }
2273 
enetc_enable_rxbdr(struct enetc_hw * hw,struct enetc_bdr * rx_ring)2274 static void enetc_enable_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring)
2275 {
2276 	int idx = rx_ring->index;
2277 	u32 rbmr;
2278 
2279 	rbmr = enetc_rxbdr_rd(hw, idx, ENETC_RBMR);
2280 	rbmr |= ENETC_RBMR_EN;
2281 	enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr);
2282 }
2283 
enetc_enable_rx_bdrs(struct enetc_ndev_priv * priv)2284 static void enetc_enable_rx_bdrs(struct enetc_ndev_priv *priv)
2285 {
2286 	struct enetc_hw *hw = &priv->si->hw;
2287 	int i;
2288 
2289 	for (i = 0; i < priv->num_rx_rings; i++)
2290 		enetc_enable_rxbdr(hw, priv->rx_ring[i]);
2291 }
2292 
enetc_enable_tx_bdrs(struct enetc_ndev_priv * priv)2293 static void enetc_enable_tx_bdrs(struct enetc_ndev_priv *priv)
2294 {
2295 	struct enetc_hw *hw = &priv->si->hw;
2296 	int i;
2297 
2298 	for (i = 0; i < priv->num_tx_rings; i++)
2299 		enetc_enable_txbdr(hw, priv->tx_ring[i]);
2300 }
2301 
enetc_disable_rxbdr(struct enetc_hw * hw,struct enetc_bdr * rx_ring)2302 static void enetc_disable_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring)
2303 {
2304 	int idx = rx_ring->index;
2305 
2306 	/* disable EN bit on ring */
2307 	enetc_rxbdr_wr(hw, idx, ENETC_RBMR, 0);
2308 }
2309 
enetc_disable_txbdr(struct enetc_hw * hw,struct enetc_bdr * rx_ring)2310 static void enetc_disable_txbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring)
2311 {
2312 	int idx = rx_ring->index;
2313 
2314 	/* disable EN bit on ring */
2315 	enetc_txbdr_wr(hw, idx, ENETC_TBMR, 0);
2316 }
2317 
enetc_disable_rx_bdrs(struct enetc_ndev_priv * priv)2318 static void enetc_disable_rx_bdrs(struct enetc_ndev_priv *priv)
2319 {
2320 	struct enetc_hw *hw = &priv->si->hw;
2321 	int i;
2322 
2323 	for (i = 0; i < priv->num_rx_rings; i++)
2324 		enetc_disable_rxbdr(hw, priv->rx_ring[i]);
2325 }
2326 
enetc_disable_tx_bdrs(struct enetc_ndev_priv * priv)2327 static void enetc_disable_tx_bdrs(struct enetc_ndev_priv *priv)
2328 {
2329 	struct enetc_hw *hw = &priv->si->hw;
2330 	int i;
2331 
2332 	for (i = 0; i < priv->num_tx_rings; i++)
2333 		enetc_disable_txbdr(hw, priv->tx_ring[i]);
2334 }
2335 
enetc_wait_txbdr(struct enetc_hw * hw,struct enetc_bdr * tx_ring)2336 static void enetc_wait_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring)
2337 {
2338 	int delay = 8, timeout = 100;
2339 	int idx = tx_ring->index;
2340 
2341 	/* wait for busy to clear */
2342 	while (delay < timeout &&
2343 	       enetc_txbdr_rd(hw, idx, ENETC_TBSR) & ENETC_TBSR_BUSY) {
2344 		msleep(delay);
2345 		delay *= 2;
2346 	}
2347 
2348 	if (delay >= timeout)
2349 		netdev_warn(tx_ring->ndev, "timeout for tx ring #%d clear\n",
2350 			    idx);
2351 }
2352 
enetc_wait_bdrs(struct enetc_ndev_priv * priv)2353 static void enetc_wait_bdrs(struct enetc_ndev_priv *priv)
2354 {
2355 	struct enetc_hw *hw = &priv->si->hw;
2356 	int i;
2357 
2358 	for (i = 0; i < priv->num_tx_rings; i++)
2359 		enetc_wait_txbdr(hw, priv->tx_ring[i]);
2360 }
2361 
enetc_setup_irqs(struct enetc_ndev_priv * priv)2362 static int enetc_setup_irqs(struct enetc_ndev_priv *priv)
2363 {
2364 	struct pci_dev *pdev = priv->si->pdev;
2365 	struct enetc_hw *hw = &priv->si->hw;
2366 	int i, j, err;
2367 
2368 	for (i = 0; i < priv->bdr_int_num; i++) {
2369 		int irq = pci_irq_vector(pdev, ENETC_BDR_INT_BASE_IDX + i);
2370 		struct enetc_int_vector *v = priv->int_vector[i];
2371 		int entry = ENETC_BDR_INT_BASE_IDX + i;
2372 
2373 		snprintf(v->name, sizeof(v->name), "%s-rxtx%d",
2374 			 priv->ndev->name, i);
2375 		err = request_irq(irq, enetc_msix, IRQF_NO_AUTOEN, v->name, v);
2376 		if (err) {
2377 			dev_err(priv->dev, "request_irq() failed!\n");
2378 			goto irq_err;
2379 		}
2380 
2381 		v->tbier_base = hw->reg + ENETC_BDR(TX, 0, ENETC_TBIER);
2382 		v->rbier = hw->reg + ENETC_BDR(RX, i, ENETC_RBIER);
2383 		v->ricr1 = hw->reg + ENETC_BDR(RX, i, ENETC_RBICR1);
2384 
2385 		enetc_wr(hw, ENETC_SIMSIRRV(i), entry);
2386 
2387 		for (j = 0; j < v->count_tx_rings; j++) {
2388 			int idx = v->tx_ring[j].index;
2389 
2390 			enetc_wr(hw, ENETC_SIMSITRV(idx), entry);
2391 		}
2392 		irq_set_affinity_hint(irq, get_cpu_mask(i % num_online_cpus()));
2393 	}
2394 
2395 	return 0;
2396 
2397 irq_err:
2398 	while (i--) {
2399 		int irq = pci_irq_vector(pdev, ENETC_BDR_INT_BASE_IDX + i);
2400 
2401 		irq_set_affinity_hint(irq, NULL);
2402 		free_irq(irq, priv->int_vector[i]);
2403 	}
2404 
2405 	return err;
2406 }
2407 
enetc_free_irqs(struct enetc_ndev_priv * priv)2408 static void enetc_free_irqs(struct enetc_ndev_priv *priv)
2409 {
2410 	struct pci_dev *pdev = priv->si->pdev;
2411 	int i;
2412 
2413 	for (i = 0; i < priv->bdr_int_num; i++) {
2414 		int irq = pci_irq_vector(pdev, ENETC_BDR_INT_BASE_IDX + i);
2415 
2416 		irq_set_affinity_hint(irq, NULL);
2417 		free_irq(irq, priv->int_vector[i]);
2418 	}
2419 }
2420 
enetc_setup_interrupts(struct enetc_ndev_priv * priv)2421 static void enetc_setup_interrupts(struct enetc_ndev_priv *priv)
2422 {
2423 	struct enetc_hw *hw = &priv->si->hw;
2424 	u32 icpt, ictt;
2425 	int i;
2426 
2427 	/* enable Tx & Rx event indication */
2428 	if (priv->ic_mode &
2429 	    (ENETC_IC_RX_MANUAL | ENETC_IC_RX_ADAPTIVE)) {
2430 		icpt = ENETC_RBICR0_SET_ICPT(ENETC_RXIC_PKTTHR);
2431 		/* init to non-0 minimum, will be adjusted later */
2432 		ictt = 0x1;
2433 	} else {
2434 		icpt = 0x1; /* enable Rx ints by setting pkt thr to 1 */
2435 		ictt = 0;
2436 	}
2437 
2438 	for (i = 0; i < priv->num_rx_rings; i++) {
2439 		enetc_rxbdr_wr(hw, i, ENETC_RBICR1, ictt);
2440 		enetc_rxbdr_wr(hw, i, ENETC_RBICR0, ENETC_RBICR0_ICEN | icpt);
2441 		enetc_rxbdr_wr(hw, i, ENETC_RBIER, ENETC_RBIER_RXTIE);
2442 	}
2443 
2444 	if (priv->ic_mode & ENETC_IC_TX_MANUAL)
2445 		icpt = ENETC_TBICR0_SET_ICPT(ENETC_TXIC_PKTTHR);
2446 	else
2447 		icpt = 0x1; /* enable Tx ints by setting pkt thr to 1 */
2448 
2449 	for (i = 0; i < priv->num_tx_rings; i++) {
2450 		enetc_txbdr_wr(hw, i, ENETC_TBICR1, priv->tx_ictt);
2451 		enetc_txbdr_wr(hw, i, ENETC_TBICR0, ENETC_TBICR0_ICEN | icpt);
2452 		enetc_txbdr_wr(hw, i, ENETC_TBIER, ENETC_TBIER_TXTIE);
2453 	}
2454 }
2455 
enetc_clear_interrupts(struct enetc_ndev_priv * priv)2456 static void enetc_clear_interrupts(struct enetc_ndev_priv *priv)
2457 {
2458 	struct enetc_hw *hw = &priv->si->hw;
2459 	int i;
2460 
2461 	for (i = 0; i < priv->num_tx_rings; i++)
2462 		enetc_txbdr_wr(hw, i, ENETC_TBIER, 0);
2463 
2464 	for (i = 0; i < priv->num_rx_rings; i++)
2465 		enetc_rxbdr_wr(hw, i, ENETC_RBIER, 0);
2466 }
2467 
enetc_phylink_connect(struct net_device * ndev)2468 static int enetc_phylink_connect(struct net_device *ndev)
2469 {
2470 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2471 	struct ethtool_eee edata;
2472 	int err;
2473 
2474 	if (!priv->phylink) {
2475 		/* phy-less mode */
2476 		netif_carrier_on(ndev);
2477 		return 0;
2478 	}
2479 
2480 	err = phylink_of_phy_connect(priv->phylink, priv->dev->of_node, 0);
2481 	if (err) {
2482 		dev_err(&ndev->dev, "could not attach to PHY\n");
2483 		return err;
2484 	}
2485 
2486 	/* disable EEE autoneg, until ENETC driver supports it */
2487 	memset(&edata, 0, sizeof(struct ethtool_eee));
2488 	phylink_ethtool_set_eee(priv->phylink, &edata);
2489 
2490 	phylink_start(priv->phylink);
2491 
2492 	return 0;
2493 }
2494 
enetc_tx_onestep_tstamp(struct work_struct * work)2495 static void enetc_tx_onestep_tstamp(struct work_struct *work)
2496 {
2497 	struct enetc_ndev_priv *priv;
2498 	struct sk_buff *skb;
2499 
2500 	priv = container_of(work, struct enetc_ndev_priv, tx_onestep_tstamp);
2501 
2502 	netif_tx_lock_bh(priv->ndev);
2503 
2504 	clear_bit_unlock(ENETC_TX_ONESTEP_TSTAMP_IN_PROGRESS, &priv->flags);
2505 	skb = skb_dequeue(&priv->tx_skbs);
2506 	if (skb)
2507 		enetc_start_xmit(skb, priv->ndev);
2508 
2509 	netif_tx_unlock_bh(priv->ndev);
2510 }
2511 
enetc_tx_onestep_tstamp_init(struct enetc_ndev_priv * priv)2512 static void enetc_tx_onestep_tstamp_init(struct enetc_ndev_priv *priv)
2513 {
2514 	INIT_WORK(&priv->tx_onestep_tstamp, enetc_tx_onestep_tstamp);
2515 	skb_queue_head_init(&priv->tx_skbs);
2516 }
2517 
enetc_start(struct net_device * ndev)2518 void enetc_start(struct net_device *ndev)
2519 {
2520 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2521 	int i;
2522 
2523 	enetc_setup_interrupts(priv);
2524 
2525 	for (i = 0; i < priv->bdr_int_num; i++) {
2526 		int irq = pci_irq_vector(priv->si->pdev,
2527 					 ENETC_BDR_INT_BASE_IDX + i);
2528 
2529 		napi_enable(&priv->int_vector[i]->napi);
2530 		enable_irq(irq);
2531 	}
2532 
2533 	enetc_enable_tx_bdrs(priv);
2534 
2535 	enetc_enable_rx_bdrs(priv);
2536 
2537 	netif_tx_start_all_queues(ndev);
2538 
2539 	clear_bit(ENETC_TX_DOWN, &priv->flags);
2540 }
2541 EXPORT_SYMBOL_GPL(enetc_start);
2542 
enetc_open(struct net_device * ndev)2543 int enetc_open(struct net_device *ndev)
2544 {
2545 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2546 	struct enetc_bdr_resource *tx_res, *rx_res;
2547 	bool extended;
2548 	int err;
2549 
2550 	extended = !!(priv->active_offloads & ENETC_F_RX_TSTAMP);
2551 
2552 	err = enetc_setup_irqs(priv);
2553 	if (err)
2554 		return err;
2555 
2556 	err = enetc_phylink_connect(ndev);
2557 	if (err)
2558 		goto err_phy_connect;
2559 
2560 	tx_res = enetc_alloc_tx_resources(priv);
2561 	if (IS_ERR(tx_res)) {
2562 		err = PTR_ERR(tx_res);
2563 		goto err_alloc_tx;
2564 	}
2565 
2566 	rx_res = enetc_alloc_rx_resources(priv, extended);
2567 	if (IS_ERR(rx_res)) {
2568 		err = PTR_ERR(rx_res);
2569 		goto err_alloc_rx;
2570 	}
2571 
2572 	enetc_tx_onestep_tstamp_init(priv);
2573 	enetc_assign_tx_resources(priv, tx_res);
2574 	enetc_assign_rx_resources(priv, rx_res);
2575 	enetc_setup_bdrs(priv, extended);
2576 	enetc_start(ndev);
2577 
2578 	return 0;
2579 
2580 err_alloc_rx:
2581 	enetc_free_tx_resources(tx_res, priv->num_tx_rings);
2582 err_alloc_tx:
2583 	if (priv->phylink)
2584 		phylink_disconnect_phy(priv->phylink);
2585 err_phy_connect:
2586 	enetc_free_irqs(priv);
2587 
2588 	return err;
2589 }
2590 EXPORT_SYMBOL_GPL(enetc_open);
2591 
enetc_stop(struct net_device * ndev)2592 void enetc_stop(struct net_device *ndev)
2593 {
2594 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2595 	int i;
2596 
2597 	set_bit(ENETC_TX_DOWN, &priv->flags);
2598 
2599 	netif_tx_stop_all_queues(ndev);
2600 
2601 	enetc_disable_rx_bdrs(priv);
2602 
2603 	enetc_wait_bdrs(priv);
2604 
2605 	enetc_disable_tx_bdrs(priv);
2606 
2607 	for (i = 0; i < priv->bdr_int_num; i++) {
2608 		int irq = pci_irq_vector(priv->si->pdev,
2609 					 ENETC_BDR_INT_BASE_IDX + i);
2610 
2611 		disable_irq(irq);
2612 		napi_synchronize(&priv->int_vector[i]->napi);
2613 		napi_disable(&priv->int_vector[i]->napi);
2614 	}
2615 
2616 	enetc_clear_interrupts(priv);
2617 }
2618 EXPORT_SYMBOL_GPL(enetc_stop);
2619 
enetc_close(struct net_device * ndev)2620 int enetc_close(struct net_device *ndev)
2621 {
2622 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2623 
2624 	enetc_stop(ndev);
2625 
2626 	if (priv->phylink) {
2627 		phylink_stop(priv->phylink);
2628 		phylink_disconnect_phy(priv->phylink);
2629 	} else {
2630 		netif_carrier_off(ndev);
2631 	}
2632 
2633 	enetc_free_rxtx_rings(priv);
2634 
2635 	/* Avoids dangling pointers and also frees old resources */
2636 	enetc_assign_rx_resources(priv, NULL);
2637 	enetc_assign_tx_resources(priv, NULL);
2638 
2639 	enetc_free_irqs(priv);
2640 
2641 	return 0;
2642 }
2643 EXPORT_SYMBOL_GPL(enetc_close);
2644 
enetc_reconfigure(struct enetc_ndev_priv * priv,bool extended,int (* cb)(struct enetc_ndev_priv * priv,void * ctx),void * ctx)2645 static int enetc_reconfigure(struct enetc_ndev_priv *priv, bool extended,
2646 			     int (*cb)(struct enetc_ndev_priv *priv, void *ctx),
2647 			     void *ctx)
2648 {
2649 	struct enetc_bdr_resource *tx_res, *rx_res;
2650 	int err;
2651 
2652 	ASSERT_RTNL();
2653 
2654 	/* If the interface is down, run the callback right away,
2655 	 * without reconfiguration.
2656 	 */
2657 	if (!netif_running(priv->ndev)) {
2658 		if (cb) {
2659 			err = cb(priv, ctx);
2660 			if (err)
2661 				return err;
2662 		}
2663 
2664 		return 0;
2665 	}
2666 
2667 	tx_res = enetc_alloc_tx_resources(priv);
2668 	if (IS_ERR(tx_res)) {
2669 		err = PTR_ERR(tx_res);
2670 		goto out;
2671 	}
2672 
2673 	rx_res = enetc_alloc_rx_resources(priv, extended);
2674 	if (IS_ERR(rx_res)) {
2675 		err = PTR_ERR(rx_res);
2676 		goto out_free_tx_res;
2677 	}
2678 
2679 	enetc_stop(priv->ndev);
2680 	enetc_free_rxtx_rings(priv);
2681 
2682 	/* Interface is down, run optional callback now */
2683 	if (cb) {
2684 		err = cb(priv, ctx);
2685 		if (err)
2686 			goto out_restart;
2687 	}
2688 
2689 	enetc_assign_tx_resources(priv, tx_res);
2690 	enetc_assign_rx_resources(priv, rx_res);
2691 	enetc_setup_bdrs(priv, extended);
2692 	enetc_start(priv->ndev);
2693 
2694 	return 0;
2695 
2696 out_restart:
2697 	enetc_setup_bdrs(priv, extended);
2698 	enetc_start(priv->ndev);
2699 	enetc_free_rx_resources(rx_res, priv->num_rx_rings);
2700 out_free_tx_res:
2701 	enetc_free_tx_resources(tx_res, priv->num_tx_rings);
2702 out:
2703 	return err;
2704 }
2705 
enetc_debug_tx_ring_prios(struct enetc_ndev_priv * priv)2706 static void enetc_debug_tx_ring_prios(struct enetc_ndev_priv *priv)
2707 {
2708 	int i;
2709 
2710 	for (i = 0; i < priv->num_tx_rings; i++)
2711 		netdev_dbg(priv->ndev, "TX ring %d prio %d\n", i,
2712 			   priv->tx_ring[i]->prio);
2713 }
2714 
enetc_reset_tc_mqprio(struct net_device * ndev)2715 void enetc_reset_tc_mqprio(struct net_device *ndev)
2716 {
2717 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2718 	struct enetc_hw *hw = &priv->si->hw;
2719 	struct enetc_bdr *tx_ring;
2720 	int num_stack_tx_queues;
2721 	int i;
2722 
2723 	num_stack_tx_queues = enetc_num_stack_tx_queues(priv);
2724 
2725 	netdev_reset_tc(ndev);
2726 	netif_set_real_num_tx_queues(ndev, num_stack_tx_queues);
2727 	priv->min_num_stack_tx_queues = num_possible_cpus();
2728 
2729 	/* Reset all ring priorities to 0 */
2730 	for (i = 0; i < priv->num_tx_rings; i++) {
2731 		tx_ring = priv->tx_ring[i];
2732 		tx_ring->prio = 0;
2733 		enetc_set_bdr_prio(hw, tx_ring->index, tx_ring->prio);
2734 	}
2735 
2736 	enetc_debug_tx_ring_prios(priv);
2737 
2738 	enetc_change_preemptible_tcs(priv, 0);
2739 }
2740 EXPORT_SYMBOL_GPL(enetc_reset_tc_mqprio);
2741 
enetc_setup_tc_mqprio(struct net_device * ndev,void * type_data)2742 int enetc_setup_tc_mqprio(struct net_device *ndev, void *type_data)
2743 {
2744 	struct tc_mqprio_qopt_offload *mqprio = type_data;
2745 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2746 	struct tc_mqprio_qopt *qopt = &mqprio->qopt;
2747 	struct enetc_hw *hw = &priv->si->hw;
2748 	int num_stack_tx_queues = 0;
2749 	struct enetc_bdr *tx_ring;
2750 	u8 num_tc = qopt->num_tc;
2751 	int offset, count;
2752 	int err, tc, q;
2753 
2754 	if (!num_tc) {
2755 		enetc_reset_tc_mqprio(ndev);
2756 		return 0;
2757 	}
2758 
2759 	err = netdev_set_num_tc(ndev, num_tc);
2760 	if (err)
2761 		return err;
2762 
2763 	for (tc = 0; tc < num_tc; tc++) {
2764 		offset = qopt->offset[tc];
2765 		count = qopt->count[tc];
2766 		num_stack_tx_queues += count;
2767 
2768 		err = netdev_set_tc_queue(ndev, tc, count, offset);
2769 		if (err)
2770 			goto err_reset_tc;
2771 
2772 		for (q = offset; q < offset + count; q++) {
2773 			tx_ring = priv->tx_ring[q];
2774 			/* The prio_tc_map is skb_tx_hash()'s way of selecting
2775 			 * between TX queues based on skb->priority. As such,
2776 			 * there's nothing to offload based on it.
2777 			 * Make the mqprio "traffic class" be the priority of
2778 			 * this ring group, and leave the Tx IPV to traffic
2779 			 * class mapping as its default mapping value of 1:1.
2780 			 */
2781 			tx_ring->prio = tc;
2782 			enetc_set_bdr_prio(hw, tx_ring->index, tx_ring->prio);
2783 		}
2784 	}
2785 
2786 	err = netif_set_real_num_tx_queues(ndev, num_stack_tx_queues);
2787 	if (err)
2788 		goto err_reset_tc;
2789 
2790 	priv->min_num_stack_tx_queues = num_stack_tx_queues;
2791 
2792 	enetc_debug_tx_ring_prios(priv);
2793 
2794 	enetc_change_preemptible_tcs(priv, mqprio->preemptible_tcs);
2795 
2796 	return 0;
2797 
2798 err_reset_tc:
2799 	enetc_reset_tc_mqprio(ndev);
2800 	return err;
2801 }
2802 EXPORT_SYMBOL_GPL(enetc_setup_tc_mqprio);
2803 
enetc_reconfigure_xdp_cb(struct enetc_ndev_priv * priv,void * ctx)2804 static int enetc_reconfigure_xdp_cb(struct enetc_ndev_priv *priv, void *ctx)
2805 {
2806 	struct bpf_prog *old_prog, *prog = ctx;
2807 	int num_stack_tx_queues;
2808 	int err, i;
2809 
2810 	old_prog = xchg(&priv->xdp_prog, prog);
2811 
2812 	num_stack_tx_queues = enetc_num_stack_tx_queues(priv);
2813 	err = netif_set_real_num_tx_queues(priv->ndev, num_stack_tx_queues);
2814 	if (err) {
2815 		xchg(&priv->xdp_prog, old_prog);
2816 		return err;
2817 	}
2818 
2819 	if (old_prog)
2820 		bpf_prog_put(old_prog);
2821 
2822 	for (i = 0; i < priv->num_rx_rings; i++) {
2823 		struct enetc_bdr *rx_ring = priv->rx_ring[i];
2824 
2825 		rx_ring->xdp.prog = prog;
2826 
2827 		if (prog)
2828 			rx_ring->buffer_offset = XDP_PACKET_HEADROOM;
2829 		else
2830 			rx_ring->buffer_offset = ENETC_RXB_PAD;
2831 	}
2832 
2833 	return 0;
2834 }
2835 
enetc_setup_xdp_prog(struct net_device * ndev,struct bpf_prog * prog,struct netlink_ext_ack * extack)2836 static int enetc_setup_xdp_prog(struct net_device *ndev, struct bpf_prog *prog,
2837 				struct netlink_ext_ack *extack)
2838 {
2839 	int num_xdp_tx_queues = prog ? num_possible_cpus() : 0;
2840 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2841 	bool extended;
2842 
2843 	if (priv->min_num_stack_tx_queues + num_xdp_tx_queues >
2844 	    priv->num_tx_rings) {
2845 		NL_SET_ERR_MSG_FMT_MOD(extack,
2846 				       "Reserving %d XDP TXQs leaves under %d for stack (total %d)",
2847 				       num_xdp_tx_queues,
2848 				       priv->min_num_stack_tx_queues,
2849 				       priv->num_tx_rings);
2850 		return -EBUSY;
2851 	}
2852 
2853 	extended = !!(priv->active_offloads & ENETC_F_RX_TSTAMP);
2854 
2855 	/* The buffer layout is changing, so we need to drain the old
2856 	 * RX buffers and seed new ones.
2857 	 */
2858 	return enetc_reconfigure(priv, extended, enetc_reconfigure_xdp_cb, prog);
2859 }
2860 
enetc_setup_bpf(struct net_device * ndev,struct netdev_bpf * bpf)2861 int enetc_setup_bpf(struct net_device *ndev, struct netdev_bpf *bpf)
2862 {
2863 	switch (bpf->command) {
2864 	case XDP_SETUP_PROG:
2865 		return enetc_setup_xdp_prog(ndev, bpf->prog, bpf->extack);
2866 	default:
2867 		return -EINVAL;
2868 	}
2869 
2870 	return 0;
2871 }
2872 EXPORT_SYMBOL_GPL(enetc_setup_bpf);
2873 
enetc_get_stats(struct net_device * ndev)2874 struct net_device_stats *enetc_get_stats(struct net_device *ndev)
2875 {
2876 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2877 	struct net_device_stats *stats = &ndev->stats;
2878 	unsigned long packets = 0, bytes = 0;
2879 	unsigned long tx_dropped = 0;
2880 	int i;
2881 
2882 	for (i = 0; i < priv->num_rx_rings; i++) {
2883 		packets += priv->rx_ring[i]->stats.packets;
2884 		bytes	+= priv->rx_ring[i]->stats.bytes;
2885 	}
2886 
2887 	stats->rx_packets = packets;
2888 	stats->rx_bytes = bytes;
2889 	bytes = 0;
2890 	packets = 0;
2891 
2892 	for (i = 0; i < priv->num_tx_rings; i++) {
2893 		packets += priv->tx_ring[i]->stats.packets;
2894 		bytes	+= priv->tx_ring[i]->stats.bytes;
2895 		tx_dropped += priv->tx_ring[i]->stats.win_drop;
2896 	}
2897 
2898 	stats->tx_packets = packets;
2899 	stats->tx_bytes = bytes;
2900 	stats->tx_dropped = tx_dropped;
2901 
2902 	return stats;
2903 }
2904 EXPORT_SYMBOL_GPL(enetc_get_stats);
2905 
enetc_set_rss(struct net_device * ndev,int en)2906 static int enetc_set_rss(struct net_device *ndev, int en)
2907 {
2908 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2909 	struct enetc_hw *hw = &priv->si->hw;
2910 	u32 reg;
2911 
2912 	enetc_wr(hw, ENETC_SIRBGCR, priv->num_rx_rings);
2913 
2914 	reg = enetc_rd(hw, ENETC_SIMR);
2915 	reg &= ~ENETC_SIMR_RSSE;
2916 	reg |= (en) ? ENETC_SIMR_RSSE : 0;
2917 	enetc_wr(hw, ENETC_SIMR, reg);
2918 
2919 	return 0;
2920 }
2921 
enetc_enable_rxvlan(struct net_device * ndev,bool en)2922 static void enetc_enable_rxvlan(struct net_device *ndev, bool en)
2923 {
2924 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2925 	struct enetc_hw *hw = &priv->si->hw;
2926 	int i;
2927 
2928 	for (i = 0; i < priv->num_rx_rings; i++)
2929 		enetc_bdr_enable_rxvlan(hw, i, en);
2930 }
2931 
enetc_enable_txvlan(struct net_device * ndev,bool en)2932 static void enetc_enable_txvlan(struct net_device *ndev, bool en)
2933 {
2934 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2935 	struct enetc_hw *hw = &priv->si->hw;
2936 	int i;
2937 
2938 	for (i = 0; i < priv->num_tx_rings; i++)
2939 		enetc_bdr_enable_txvlan(hw, i, en);
2940 }
2941 
enetc_set_features(struct net_device * ndev,netdev_features_t features)2942 void enetc_set_features(struct net_device *ndev, netdev_features_t features)
2943 {
2944 	netdev_features_t changed = ndev->features ^ features;
2945 
2946 	if (changed & NETIF_F_RXHASH)
2947 		enetc_set_rss(ndev, !!(features & NETIF_F_RXHASH));
2948 
2949 	if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2950 		enetc_enable_rxvlan(ndev,
2951 				    !!(features & NETIF_F_HW_VLAN_CTAG_RX));
2952 
2953 	if (changed & NETIF_F_HW_VLAN_CTAG_TX)
2954 		enetc_enable_txvlan(ndev,
2955 				    !!(features & NETIF_F_HW_VLAN_CTAG_TX));
2956 }
2957 EXPORT_SYMBOL_GPL(enetc_set_features);
2958 
2959 #ifdef CONFIG_FSL_ENETC_PTP_CLOCK
enetc_hwtstamp_set(struct net_device * ndev,struct ifreq * ifr)2960 static int enetc_hwtstamp_set(struct net_device *ndev, struct ifreq *ifr)
2961 {
2962 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
2963 	int err, new_offloads = priv->active_offloads;
2964 	struct hwtstamp_config config;
2965 
2966 	if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2967 		return -EFAULT;
2968 
2969 	switch (config.tx_type) {
2970 	case HWTSTAMP_TX_OFF:
2971 		new_offloads &= ~ENETC_F_TX_TSTAMP_MASK;
2972 		break;
2973 	case HWTSTAMP_TX_ON:
2974 		new_offloads &= ~ENETC_F_TX_TSTAMP_MASK;
2975 		new_offloads |= ENETC_F_TX_TSTAMP;
2976 		break;
2977 	case HWTSTAMP_TX_ONESTEP_SYNC:
2978 		new_offloads &= ~ENETC_F_TX_TSTAMP_MASK;
2979 		new_offloads |= ENETC_F_TX_ONESTEP_SYNC_TSTAMP;
2980 		break;
2981 	default:
2982 		return -ERANGE;
2983 	}
2984 
2985 	switch (config.rx_filter) {
2986 	case HWTSTAMP_FILTER_NONE:
2987 		new_offloads &= ~ENETC_F_RX_TSTAMP;
2988 		break;
2989 	default:
2990 		new_offloads |= ENETC_F_RX_TSTAMP;
2991 		config.rx_filter = HWTSTAMP_FILTER_ALL;
2992 	}
2993 
2994 	if ((new_offloads ^ priv->active_offloads) & ENETC_F_RX_TSTAMP) {
2995 		bool extended = !!(new_offloads & ENETC_F_RX_TSTAMP);
2996 
2997 		err = enetc_reconfigure(priv, extended, NULL, NULL);
2998 		if (err)
2999 			return err;
3000 	}
3001 
3002 	priv->active_offloads = new_offloads;
3003 
3004 	return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
3005 	       -EFAULT : 0;
3006 }
3007 
enetc_hwtstamp_get(struct net_device * ndev,struct ifreq * ifr)3008 static int enetc_hwtstamp_get(struct net_device *ndev, struct ifreq *ifr)
3009 {
3010 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
3011 	struct hwtstamp_config config;
3012 
3013 	config.flags = 0;
3014 
3015 	if (priv->active_offloads & ENETC_F_TX_ONESTEP_SYNC_TSTAMP)
3016 		config.tx_type = HWTSTAMP_TX_ONESTEP_SYNC;
3017 	else if (priv->active_offloads & ENETC_F_TX_TSTAMP)
3018 		config.tx_type = HWTSTAMP_TX_ON;
3019 	else
3020 		config.tx_type = HWTSTAMP_TX_OFF;
3021 
3022 	config.rx_filter = (priv->active_offloads & ENETC_F_RX_TSTAMP) ?
3023 			    HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE;
3024 
3025 	return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
3026 	       -EFAULT : 0;
3027 }
3028 #endif
3029 
enetc_ioctl(struct net_device * ndev,struct ifreq * rq,int cmd)3030 int enetc_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
3031 {
3032 	struct enetc_ndev_priv *priv = netdev_priv(ndev);
3033 #ifdef CONFIG_FSL_ENETC_PTP_CLOCK
3034 	if (cmd == SIOCSHWTSTAMP)
3035 		return enetc_hwtstamp_set(ndev, rq);
3036 	if (cmd == SIOCGHWTSTAMP)
3037 		return enetc_hwtstamp_get(ndev, rq);
3038 #endif
3039 
3040 	if (!priv->phylink)
3041 		return -EOPNOTSUPP;
3042 
3043 	return phylink_mii_ioctl(priv->phylink, rq, cmd);
3044 }
3045 EXPORT_SYMBOL_GPL(enetc_ioctl);
3046 
enetc_alloc_msix(struct enetc_ndev_priv * priv)3047 int enetc_alloc_msix(struct enetc_ndev_priv *priv)
3048 {
3049 	struct pci_dev *pdev = priv->si->pdev;
3050 	int num_stack_tx_queues;
3051 	int first_xdp_tx_ring;
3052 	int i, n, err, nvec;
3053 	int v_tx_rings;
3054 
3055 	nvec = ENETC_BDR_INT_BASE_IDX + priv->bdr_int_num;
3056 	/* allocate MSIX for both messaging and Rx/Tx interrupts */
3057 	n = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSIX);
3058 
3059 	if (n < 0)
3060 		return n;
3061 
3062 	if (n != nvec)
3063 		return -EPERM;
3064 
3065 	/* # of tx rings per int vector */
3066 	v_tx_rings = priv->num_tx_rings / priv->bdr_int_num;
3067 
3068 	for (i = 0; i < priv->bdr_int_num; i++) {
3069 		struct enetc_int_vector *v;
3070 		struct enetc_bdr *bdr;
3071 		int j;
3072 
3073 		v = kzalloc(struct_size(v, tx_ring, v_tx_rings), GFP_KERNEL);
3074 		if (!v) {
3075 			err = -ENOMEM;
3076 			goto fail;
3077 		}
3078 
3079 		priv->int_vector[i] = v;
3080 
3081 		bdr = &v->rx_ring;
3082 		bdr->index = i;
3083 		bdr->ndev = priv->ndev;
3084 		bdr->dev = priv->dev;
3085 		bdr->bd_count = priv->rx_bd_count;
3086 		bdr->buffer_offset = ENETC_RXB_PAD;
3087 		priv->rx_ring[i] = bdr;
3088 
3089 		err = xdp_rxq_info_reg(&bdr->xdp.rxq, priv->ndev, i, 0);
3090 		if (err) {
3091 			kfree(v);
3092 			goto fail;
3093 		}
3094 
3095 		err = xdp_rxq_info_reg_mem_model(&bdr->xdp.rxq,
3096 						 MEM_TYPE_PAGE_SHARED, NULL);
3097 		if (err) {
3098 			xdp_rxq_info_unreg(&bdr->xdp.rxq);
3099 			kfree(v);
3100 			goto fail;
3101 		}
3102 
3103 		/* init defaults for adaptive IC */
3104 		if (priv->ic_mode & ENETC_IC_RX_ADAPTIVE) {
3105 			v->rx_ictt = 0x1;
3106 			v->rx_dim_en = true;
3107 		}
3108 		INIT_WORK(&v->rx_dim.work, enetc_rx_dim_work);
3109 		netif_napi_add(priv->ndev, &v->napi, enetc_poll);
3110 		v->count_tx_rings = v_tx_rings;
3111 
3112 		for (j = 0; j < v_tx_rings; j++) {
3113 			int idx;
3114 
3115 			/* default tx ring mapping policy */
3116 			idx = priv->bdr_int_num * j + i;
3117 			__set_bit(idx, &v->tx_rings_map);
3118 			bdr = &v->tx_ring[j];
3119 			bdr->index = idx;
3120 			bdr->ndev = priv->ndev;
3121 			bdr->dev = priv->dev;
3122 			bdr->bd_count = priv->tx_bd_count;
3123 			priv->tx_ring[idx] = bdr;
3124 		}
3125 	}
3126 
3127 	num_stack_tx_queues = enetc_num_stack_tx_queues(priv);
3128 
3129 	err = netif_set_real_num_tx_queues(priv->ndev, num_stack_tx_queues);
3130 	if (err)
3131 		goto fail;
3132 
3133 	err = netif_set_real_num_rx_queues(priv->ndev, priv->num_rx_rings);
3134 	if (err)
3135 		goto fail;
3136 
3137 	priv->min_num_stack_tx_queues = num_possible_cpus();
3138 	first_xdp_tx_ring = priv->num_tx_rings - num_possible_cpus();
3139 	priv->xdp_tx_ring = &priv->tx_ring[first_xdp_tx_ring];
3140 
3141 	return 0;
3142 
3143 fail:
3144 	while (i--) {
3145 		struct enetc_int_vector *v = priv->int_vector[i];
3146 		struct enetc_bdr *rx_ring = &v->rx_ring;
3147 
3148 		xdp_rxq_info_unreg_mem_model(&rx_ring->xdp.rxq);
3149 		xdp_rxq_info_unreg(&rx_ring->xdp.rxq);
3150 		netif_napi_del(&v->napi);
3151 		cancel_work_sync(&v->rx_dim.work);
3152 		kfree(v);
3153 	}
3154 
3155 	pci_free_irq_vectors(pdev);
3156 
3157 	return err;
3158 }
3159 EXPORT_SYMBOL_GPL(enetc_alloc_msix);
3160 
enetc_free_msix(struct enetc_ndev_priv * priv)3161 void enetc_free_msix(struct enetc_ndev_priv *priv)
3162 {
3163 	int i;
3164 
3165 	for (i = 0; i < priv->bdr_int_num; i++) {
3166 		struct enetc_int_vector *v = priv->int_vector[i];
3167 		struct enetc_bdr *rx_ring = &v->rx_ring;
3168 
3169 		xdp_rxq_info_unreg_mem_model(&rx_ring->xdp.rxq);
3170 		xdp_rxq_info_unreg(&rx_ring->xdp.rxq);
3171 		netif_napi_del(&v->napi);
3172 		cancel_work_sync(&v->rx_dim.work);
3173 	}
3174 
3175 	for (i = 0; i < priv->num_rx_rings; i++)
3176 		priv->rx_ring[i] = NULL;
3177 
3178 	for (i = 0; i < priv->num_tx_rings; i++)
3179 		priv->tx_ring[i] = NULL;
3180 
3181 	for (i = 0; i < priv->bdr_int_num; i++) {
3182 		kfree(priv->int_vector[i]);
3183 		priv->int_vector[i] = NULL;
3184 	}
3185 
3186 	/* disable all MSIX for this device */
3187 	pci_free_irq_vectors(priv->si->pdev);
3188 }
3189 EXPORT_SYMBOL_GPL(enetc_free_msix);
3190 
enetc_kfree_si(struct enetc_si * si)3191 static void enetc_kfree_si(struct enetc_si *si)
3192 {
3193 	char *p = (char *)si - si->pad;
3194 
3195 	kfree(p);
3196 }
3197 
enetc_detect_errata(struct enetc_si * si)3198 static void enetc_detect_errata(struct enetc_si *si)
3199 {
3200 	if (si->pdev->revision == ENETC_REV1)
3201 		si->errata = ENETC_ERR_VLAN_ISOL | ENETC_ERR_UCMCSWP;
3202 }
3203 
enetc_pci_probe(struct pci_dev * pdev,const char * name,int sizeof_priv)3204 int enetc_pci_probe(struct pci_dev *pdev, const char *name, int sizeof_priv)
3205 {
3206 	struct enetc_si *si, *p;
3207 	struct enetc_hw *hw;
3208 	size_t alloc_size;
3209 	int err, len;
3210 
3211 	pcie_flr(pdev);
3212 	err = pci_enable_device_mem(pdev);
3213 	if (err)
3214 		return dev_err_probe(&pdev->dev, err, "device enable failed\n");
3215 
3216 	/* set up for high or low dma */
3217 	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3218 	if (err) {
3219 		dev_err(&pdev->dev, "DMA configuration failed: 0x%x\n", err);
3220 		goto err_dma;
3221 	}
3222 
3223 	err = pci_request_mem_regions(pdev, name);
3224 	if (err) {
3225 		dev_err(&pdev->dev, "pci_request_regions failed err=%d\n", err);
3226 		goto err_pci_mem_reg;
3227 	}
3228 
3229 	pci_set_master(pdev);
3230 
3231 	alloc_size = sizeof(struct enetc_si);
3232 	if (sizeof_priv) {
3233 		/* align priv to 32B */
3234 		alloc_size = ALIGN(alloc_size, ENETC_SI_ALIGN);
3235 		alloc_size += sizeof_priv;
3236 	}
3237 	/* force 32B alignment for enetc_si */
3238 	alloc_size += ENETC_SI_ALIGN - 1;
3239 
3240 	p = kzalloc(alloc_size, GFP_KERNEL);
3241 	if (!p) {
3242 		err = -ENOMEM;
3243 		goto err_alloc_si;
3244 	}
3245 
3246 	si = PTR_ALIGN(p, ENETC_SI_ALIGN);
3247 	si->pad = (char *)si - (char *)p;
3248 
3249 	pci_set_drvdata(pdev, si);
3250 	si->pdev = pdev;
3251 	hw = &si->hw;
3252 
3253 	len = pci_resource_len(pdev, ENETC_BAR_REGS);
3254 	hw->reg = ioremap(pci_resource_start(pdev, ENETC_BAR_REGS), len);
3255 	if (!hw->reg) {
3256 		err = -ENXIO;
3257 		dev_err(&pdev->dev, "ioremap() failed\n");
3258 		goto err_ioremap;
3259 	}
3260 	if (len > ENETC_PORT_BASE)
3261 		hw->port = hw->reg + ENETC_PORT_BASE;
3262 	if (len > ENETC_GLOBAL_BASE)
3263 		hw->global = hw->reg + ENETC_GLOBAL_BASE;
3264 
3265 	enetc_detect_errata(si);
3266 
3267 	return 0;
3268 
3269 err_ioremap:
3270 	enetc_kfree_si(si);
3271 err_alloc_si:
3272 	pci_release_mem_regions(pdev);
3273 err_pci_mem_reg:
3274 err_dma:
3275 	pci_disable_device(pdev);
3276 
3277 	return err;
3278 }
3279 EXPORT_SYMBOL_GPL(enetc_pci_probe);
3280 
enetc_pci_remove(struct pci_dev * pdev)3281 void enetc_pci_remove(struct pci_dev *pdev)
3282 {
3283 	struct enetc_si *si = pci_get_drvdata(pdev);
3284 	struct enetc_hw *hw = &si->hw;
3285 
3286 	iounmap(hw->reg);
3287 	enetc_kfree_si(si);
3288 	pci_release_mem_regions(pdev);
3289 	pci_disable_device(pdev);
3290 }
3291 EXPORT_SYMBOL_GPL(enetc_pci_remove);
3292 
3293 MODULE_LICENSE("Dual BSD/GPL");
3294