1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 *
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
7 */
8
9 #include <linux/of.h>
10 #include <linux/of_mdio.h>
11 #include <linux/of_net.h>
12 #include <linux/of_address.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
16 #include <linux/clk.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/if_vlan.h>
19 #include <linux/reset.h>
20 #include <linux/tcp.h>
21 #include <linux/interrupt.h>
22 #include <linux/pinctrl/devinfo.h>
23 #include <linux/phylink.h>
24 #include <linux/pcs/pcs-mtk-lynxi.h>
25 #include <linux/jhash.h>
26 #include <linux/bitfield.h>
27 #include <net/dsa.h>
28 #include <net/dst_metadata.h>
29 #include <net/page_pool/helpers.h>
30
31 #include "mtk_eth_soc.h"
32 #include "mtk_wed.h"
33
34 static int mtk_msg_level = -1;
35 module_param_named(msg_level, mtk_msg_level, int, 0);
36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
37
38 #define MTK_ETHTOOL_STAT(x) { #x, \
39 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
40
41 #define MTK_ETHTOOL_XDP_STAT(x) { #x, \
42 offsetof(struct mtk_hw_stats, xdp_stats.x) / \
43 sizeof(u64) }
44
45 static const struct mtk_reg_map mtk_reg_map = {
46 .tx_irq_mask = 0x1a1c,
47 .tx_irq_status = 0x1a18,
48 .pdma = {
49 .rx_ptr = 0x0900,
50 .rx_cnt_cfg = 0x0904,
51 .pcrx_ptr = 0x0908,
52 .glo_cfg = 0x0a04,
53 .rst_idx = 0x0a08,
54 .delay_irq = 0x0a0c,
55 .irq_status = 0x0a20,
56 .irq_mask = 0x0a28,
57 .adma_rx_dbg0 = 0x0a38,
58 .int_grp = 0x0a50,
59 },
60 .qdma = {
61 .qtx_cfg = 0x1800,
62 .qtx_sch = 0x1804,
63 .rx_ptr = 0x1900,
64 .rx_cnt_cfg = 0x1904,
65 .qcrx_ptr = 0x1908,
66 .glo_cfg = 0x1a04,
67 .rst_idx = 0x1a08,
68 .delay_irq = 0x1a0c,
69 .fc_th = 0x1a10,
70 .tx_sch_rate = 0x1a14,
71 .int_grp = 0x1a20,
72 .hred = 0x1a44,
73 .ctx_ptr = 0x1b00,
74 .dtx_ptr = 0x1b04,
75 .crx_ptr = 0x1b10,
76 .drx_ptr = 0x1b14,
77 .fq_head = 0x1b20,
78 .fq_tail = 0x1b24,
79 .fq_count = 0x1b28,
80 .fq_blen = 0x1b2c,
81 },
82 .gdm1_cnt = 0x2400,
83 .gdma_to_ppe = 0x4444,
84 .ppe_base = 0x0c00,
85 .wdma_base = {
86 [0] = 0x2800,
87 [1] = 0x2c00,
88 },
89 .pse_iq_sta = 0x0110,
90 .pse_oq_sta = 0x0118,
91 };
92
93 static const struct mtk_reg_map mt7628_reg_map = {
94 .tx_irq_mask = 0x0a28,
95 .tx_irq_status = 0x0a20,
96 .pdma = {
97 .rx_ptr = 0x0900,
98 .rx_cnt_cfg = 0x0904,
99 .pcrx_ptr = 0x0908,
100 .glo_cfg = 0x0a04,
101 .rst_idx = 0x0a08,
102 .delay_irq = 0x0a0c,
103 .irq_status = 0x0a20,
104 .irq_mask = 0x0a28,
105 .int_grp = 0x0a50,
106 },
107 };
108
109 static const struct mtk_reg_map mt7986_reg_map = {
110 .tx_irq_mask = 0x461c,
111 .tx_irq_status = 0x4618,
112 .pdma = {
113 .rx_ptr = 0x6100,
114 .rx_cnt_cfg = 0x6104,
115 .pcrx_ptr = 0x6108,
116 .glo_cfg = 0x6204,
117 .rst_idx = 0x6208,
118 .delay_irq = 0x620c,
119 .irq_status = 0x6220,
120 .irq_mask = 0x6228,
121 .adma_rx_dbg0 = 0x6238,
122 .int_grp = 0x6250,
123 },
124 .qdma = {
125 .qtx_cfg = 0x4400,
126 .qtx_sch = 0x4404,
127 .rx_ptr = 0x4500,
128 .rx_cnt_cfg = 0x4504,
129 .qcrx_ptr = 0x4508,
130 .glo_cfg = 0x4604,
131 .rst_idx = 0x4608,
132 .delay_irq = 0x460c,
133 .fc_th = 0x4610,
134 .int_grp = 0x4620,
135 .hred = 0x4644,
136 .ctx_ptr = 0x4700,
137 .dtx_ptr = 0x4704,
138 .crx_ptr = 0x4710,
139 .drx_ptr = 0x4714,
140 .fq_head = 0x4720,
141 .fq_tail = 0x4724,
142 .fq_count = 0x4728,
143 .fq_blen = 0x472c,
144 .tx_sch_rate = 0x4798,
145 },
146 .gdm1_cnt = 0x1c00,
147 .gdma_to_ppe = 0x3333,
148 .ppe_base = 0x2000,
149 .wdma_base = {
150 [0] = 0x4800,
151 [1] = 0x4c00,
152 },
153 .pse_iq_sta = 0x0180,
154 .pse_oq_sta = 0x01a0,
155 };
156
157 static const struct mtk_reg_map mt7988_reg_map = {
158 .tx_irq_mask = 0x461c,
159 .tx_irq_status = 0x4618,
160 .pdma = {
161 .rx_ptr = 0x6900,
162 .rx_cnt_cfg = 0x6904,
163 .pcrx_ptr = 0x6908,
164 .glo_cfg = 0x6a04,
165 .rst_idx = 0x6a08,
166 .delay_irq = 0x6a0c,
167 .irq_status = 0x6a20,
168 .irq_mask = 0x6a28,
169 .adma_rx_dbg0 = 0x6a38,
170 .int_grp = 0x6a50,
171 },
172 .qdma = {
173 .qtx_cfg = 0x4400,
174 .qtx_sch = 0x4404,
175 .rx_ptr = 0x4500,
176 .rx_cnt_cfg = 0x4504,
177 .qcrx_ptr = 0x4508,
178 .glo_cfg = 0x4604,
179 .rst_idx = 0x4608,
180 .delay_irq = 0x460c,
181 .fc_th = 0x4610,
182 .int_grp = 0x4620,
183 .hred = 0x4644,
184 .ctx_ptr = 0x4700,
185 .dtx_ptr = 0x4704,
186 .crx_ptr = 0x4710,
187 .drx_ptr = 0x4714,
188 .fq_head = 0x4720,
189 .fq_tail = 0x4724,
190 .fq_count = 0x4728,
191 .fq_blen = 0x472c,
192 .tx_sch_rate = 0x4798,
193 },
194 .gdm1_cnt = 0x1c00,
195 .gdma_to_ppe = 0x3333,
196 .ppe_base = 0x2000,
197 .wdma_base = {
198 [0] = 0x4800,
199 [1] = 0x4c00,
200 },
201 .pse_iq_sta = 0x0180,
202 .pse_oq_sta = 0x01a0,
203 };
204
205 /* strings used by ethtool */
206 static const struct mtk_ethtool_stats {
207 char str[ETH_GSTRING_LEN];
208 u32 offset;
209 } mtk_ethtool_stats[] = {
210 MTK_ETHTOOL_STAT(tx_bytes),
211 MTK_ETHTOOL_STAT(tx_packets),
212 MTK_ETHTOOL_STAT(tx_skip),
213 MTK_ETHTOOL_STAT(tx_collisions),
214 MTK_ETHTOOL_STAT(rx_bytes),
215 MTK_ETHTOOL_STAT(rx_packets),
216 MTK_ETHTOOL_STAT(rx_overflow),
217 MTK_ETHTOOL_STAT(rx_fcs_errors),
218 MTK_ETHTOOL_STAT(rx_short_errors),
219 MTK_ETHTOOL_STAT(rx_long_errors),
220 MTK_ETHTOOL_STAT(rx_checksum_errors),
221 MTK_ETHTOOL_STAT(rx_flow_control_packets),
222 MTK_ETHTOOL_XDP_STAT(rx_xdp_redirect),
223 MTK_ETHTOOL_XDP_STAT(rx_xdp_pass),
224 MTK_ETHTOOL_XDP_STAT(rx_xdp_drop),
225 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx),
226 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx_errors),
227 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit),
228 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit_errors),
229 };
230
231 static const char * const mtk_clks_source_name[] = {
232 "ethif",
233 "sgmiitop",
234 "esw",
235 "gp0",
236 "gp1",
237 "gp2",
238 "gp3",
239 "xgp1",
240 "xgp2",
241 "xgp3",
242 "crypto",
243 "fe",
244 "trgpll",
245 "sgmii_tx250m",
246 "sgmii_rx250m",
247 "sgmii_cdr_ref",
248 "sgmii_cdr_fb",
249 "sgmii2_tx250m",
250 "sgmii2_rx250m",
251 "sgmii2_cdr_ref",
252 "sgmii2_cdr_fb",
253 "sgmii_ck",
254 "eth2pll",
255 "wocpu0",
256 "wocpu1",
257 "netsys0",
258 "netsys1",
259 "ethwarp_wocpu2",
260 "ethwarp_wocpu1",
261 "ethwarp_wocpu0",
262 "top_usxgmii0_sel",
263 "top_usxgmii1_sel",
264 "top_sgm0_sel",
265 "top_sgm1_sel",
266 "top_xfi_phy0_xtal_sel",
267 "top_xfi_phy1_xtal_sel",
268 "top_eth_gmii_sel",
269 "top_eth_refck_50m_sel",
270 "top_eth_sys_200m_sel",
271 "top_eth_sys_sel",
272 "top_eth_xgmii_sel",
273 "top_eth_mii_sel",
274 "top_netsys_sel",
275 "top_netsys_500m_sel",
276 "top_netsys_pao_2x_sel",
277 "top_netsys_sync_250m_sel",
278 "top_netsys_ppefb_250m_sel",
279 "top_netsys_warp_sel",
280 };
281
mtk_w32(struct mtk_eth * eth,u32 val,unsigned reg)282 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
283 {
284 __raw_writel(val, eth->base + reg);
285 }
286
mtk_r32(struct mtk_eth * eth,unsigned reg)287 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
288 {
289 return __raw_readl(eth->base + reg);
290 }
291
mtk_m32(struct mtk_eth * eth,u32 mask,u32 set,unsigned int reg)292 u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg)
293 {
294 u32 val;
295
296 val = mtk_r32(eth, reg);
297 val &= ~mask;
298 val |= set;
299 mtk_w32(eth, val, reg);
300 return reg;
301 }
302
mtk_mdio_busy_wait(struct mtk_eth * eth)303 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
304 {
305 unsigned long t_start = jiffies;
306
307 while (1) {
308 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
309 return 0;
310 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
311 break;
312 cond_resched();
313 }
314
315 dev_err(eth->dev, "mdio: MDIO timeout\n");
316 return -ETIMEDOUT;
317 }
318
_mtk_mdio_write_c22(struct mtk_eth * eth,u32 phy_addr,u32 phy_reg,u32 write_data)319 static int _mtk_mdio_write_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg,
320 u32 write_data)
321 {
322 int ret;
323
324 ret = mtk_mdio_busy_wait(eth);
325 if (ret < 0)
326 return ret;
327
328 mtk_w32(eth, PHY_IAC_ACCESS |
329 PHY_IAC_START_C22 |
330 PHY_IAC_CMD_WRITE |
331 PHY_IAC_REG(phy_reg) |
332 PHY_IAC_ADDR(phy_addr) |
333 PHY_IAC_DATA(write_data),
334 MTK_PHY_IAC);
335
336 ret = mtk_mdio_busy_wait(eth);
337 if (ret < 0)
338 return ret;
339
340 return 0;
341 }
342
_mtk_mdio_write_c45(struct mtk_eth * eth,u32 phy_addr,u32 devad,u32 phy_reg,u32 write_data)343 static int _mtk_mdio_write_c45(struct mtk_eth *eth, u32 phy_addr,
344 u32 devad, u32 phy_reg, u32 write_data)
345 {
346 int ret;
347
348 ret = mtk_mdio_busy_wait(eth);
349 if (ret < 0)
350 return ret;
351
352 mtk_w32(eth, PHY_IAC_ACCESS |
353 PHY_IAC_START_C45 |
354 PHY_IAC_CMD_C45_ADDR |
355 PHY_IAC_REG(devad) |
356 PHY_IAC_ADDR(phy_addr) |
357 PHY_IAC_DATA(phy_reg),
358 MTK_PHY_IAC);
359
360 ret = mtk_mdio_busy_wait(eth);
361 if (ret < 0)
362 return ret;
363
364 mtk_w32(eth, PHY_IAC_ACCESS |
365 PHY_IAC_START_C45 |
366 PHY_IAC_CMD_WRITE |
367 PHY_IAC_REG(devad) |
368 PHY_IAC_ADDR(phy_addr) |
369 PHY_IAC_DATA(write_data),
370 MTK_PHY_IAC);
371
372 ret = mtk_mdio_busy_wait(eth);
373 if (ret < 0)
374 return ret;
375
376 return 0;
377 }
378
_mtk_mdio_read_c22(struct mtk_eth * eth,u32 phy_addr,u32 phy_reg)379 static int _mtk_mdio_read_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg)
380 {
381 int ret;
382
383 ret = mtk_mdio_busy_wait(eth);
384 if (ret < 0)
385 return ret;
386
387 mtk_w32(eth, PHY_IAC_ACCESS |
388 PHY_IAC_START_C22 |
389 PHY_IAC_CMD_C22_READ |
390 PHY_IAC_REG(phy_reg) |
391 PHY_IAC_ADDR(phy_addr),
392 MTK_PHY_IAC);
393
394 ret = mtk_mdio_busy_wait(eth);
395 if (ret < 0)
396 return ret;
397
398 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK;
399 }
400
_mtk_mdio_read_c45(struct mtk_eth * eth,u32 phy_addr,u32 devad,u32 phy_reg)401 static int _mtk_mdio_read_c45(struct mtk_eth *eth, u32 phy_addr,
402 u32 devad, u32 phy_reg)
403 {
404 int ret;
405
406 ret = mtk_mdio_busy_wait(eth);
407 if (ret < 0)
408 return ret;
409
410 mtk_w32(eth, PHY_IAC_ACCESS |
411 PHY_IAC_START_C45 |
412 PHY_IAC_CMD_C45_ADDR |
413 PHY_IAC_REG(devad) |
414 PHY_IAC_ADDR(phy_addr) |
415 PHY_IAC_DATA(phy_reg),
416 MTK_PHY_IAC);
417
418 ret = mtk_mdio_busy_wait(eth);
419 if (ret < 0)
420 return ret;
421
422 mtk_w32(eth, PHY_IAC_ACCESS |
423 PHY_IAC_START_C45 |
424 PHY_IAC_CMD_C45_READ |
425 PHY_IAC_REG(devad) |
426 PHY_IAC_ADDR(phy_addr),
427 MTK_PHY_IAC);
428
429 ret = mtk_mdio_busy_wait(eth);
430 if (ret < 0)
431 return ret;
432
433 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK;
434 }
435
mtk_mdio_write_c22(struct mii_bus * bus,int phy_addr,int phy_reg,u16 val)436 static int mtk_mdio_write_c22(struct mii_bus *bus, int phy_addr,
437 int phy_reg, u16 val)
438 {
439 struct mtk_eth *eth = bus->priv;
440
441 return _mtk_mdio_write_c22(eth, phy_addr, phy_reg, val);
442 }
443
mtk_mdio_write_c45(struct mii_bus * bus,int phy_addr,int devad,int phy_reg,u16 val)444 static int mtk_mdio_write_c45(struct mii_bus *bus, int phy_addr,
445 int devad, int phy_reg, u16 val)
446 {
447 struct mtk_eth *eth = bus->priv;
448
449 return _mtk_mdio_write_c45(eth, phy_addr, devad, phy_reg, val);
450 }
451
mtk_mdio_read_c22(struct mii_bus * bus,int phy_addr,int phy_reg)452 static int mtk_mdio_read_c22(struct mii_bus *bus, int phy_addr, int phy_reg)
453 {
454 struct mtk_eth *eth = bus->priv;
455
456 return _mtk_mdio_read_c22(eth, phy_addr, phy_reg);
457 }
458
mtk_mdio_read_c45(struct mii_bus * bus,int phy_addr,int devad,int phy_reg)459 static int mtk_mdio_read_c45(struct mii_bus *bus, int phy_addr, int devad,
460 int phy_reg)
461 {
462 struct mtk_eth *eth = bus->priv;
463
464 return _mtk_mdio_read_c45(eth, phy_addr, devad, phy_reg);
465 }
466
mt7621_gmac0_rgmii_adjust(struct mtk_eth * eth,phy_interface_t interface)467 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth,
468 phy_interface_t interface)
469 {
470 u32 val;
471
472 val = (interface == PHY_INTERFACE_MODE_TRGMII) ?
473 ETHSYS_TRGMII_MT7621_DDR_PLL : 0;
474
475 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
476 ETHSYS_TRGMII_MT7621_MASK, val);
477
478 return 0;
479 }
480
mtk_gmac0_rgmii_adjust(struct mtk_eth * eth,phy_interface_t interface)481 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth,
482 phy_interface_t interface)
483 {
484 int ret;
485
486 if (interface == PHY_INTERFACE_MODE_TRGMII) {
487 mtk_w32(eth, TRGMII_MODE, INTF_MODE);
488 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], 500000000);
489 if (ret)
490 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
491 return;
492 }
493
494 dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n");
495 }
496
mtk_setup_bridge_switch(struct mtk_eth * eth)497 static void mtk_setup_bridge_switch(struct mtk_eth *eth)
498 {
499 /* Force Port1 XGMAC Link Up */
500 mtk_m32(eth, 0, MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID),
501 MTK_XGMAC_STS(MTK_GMAC1_ID));
502
503 /* Adjust GSW bridge IPG to 11 */
504 mtk_m32(eth, GSWTX_IPG_MASK | GSWRX_IPG_MASK,
505 (GSW_IPG_11 << GSWTX_IPG_SHIFT) |
506 (GSW_IPG_11 << GSWRX_IPG_SHIFT),
507 MTK_GSW_CFG);
508 }
509
mtk_mac_select_pcs(struct phylink_config * config,phy_interface_t interface)510 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
511 phy_interface_t interface)
512 {
513 struct mtk_mac *mac = container_of(config, struct mtk_mac,
514 phylink_config);
515 struct mtk_eth *eth = mac->hw;
516 unsigned int sid;
517
518 if (interface == PHY_INTERFACE_MODE_SGMII ||
519 phy_interface_mode_is_8023z(interface)) {
520 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
521 0 : mac->id;
522
523 return eth->sgmii_pcs[sid];
524 }
525
526 return NULL;
527 }
528
mtk_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)529 static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
530 const struct phylink_link_state *state)
531 {
532 struct mtk_mac *mac = container_of(config, struct mtk_mac,
533 phylink_config);
534 struct mtk_eth *eth = mac->hw;
535 int val, ge_mode, err = 0;
536 u32 i;
537
538 /* MT76x8 has no hardware settings between for the MAC */
539 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
540 mac->interface != state->interface) {
541 /* Setup soc pin functions */
542 switch (state->interface) {
543 case PHY_INTERFACE_MODE_TRGMII:
544 case PHY_INTERFACE_MODE_RGMII_TXID:
545 case PHY_INTERFACE_MODE_RGMII_RXID:
546 case PHY_INTERFACE_MODE_RGMII_ID:
547 case PHY_INTERFACE_MODE_RGMII:
548 case PHY_INTERFACE_MODE_MII:
549 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) {
550 err = mtk_gmac_rgmii_path_setup(eth, mac->id);
551 if (err)
552 goto init_err;
553 }
554 break;
555 case PHY_INTERFACE_MODE_1000BASEX:
556 case PHY_INTERFACE_MODE_2500BASEX:
557 case PHY_INTERFACE_MODE_SGMII:
558 err = mtk_gmac_sgmii_path_setup(eth, mac->id);
559 if (err)
560 goto init_err;
561 break;
562 case PHY_INTERFACE_MODE_GMII:
563 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) {
564 err = mtk_gmac_gephy_path_setup(eth, mac->id);
565 if (err)
566 goto init_err;
567 }
568 break;
569 case PHY_INTERFACE_MODE_INTERNAL:
570 break;
571 default:
572 goto err_phy;
573 }
574
575 /* Setup clock for 1st gmac */
576 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII &&
577 !phy_interface_mode_is_8023z(state->interface) &&
578 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) {
579 if (MTK_HAS_CAPS(mac->hw->soc->caps,
580 MTK_TRGMII_MT7621_CLK)) {
581 if (mt7621_gmac0_rgmii_adjust(mac->hw,
582 state->interface))
583 goto err_phy;
584 } else {
585 mtk_gmac0_rgmii_adjust(mac->hw,
586 state->interface);
587
588 /* mt7623_pad_clk_setup */
589 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
590 mtk_w32(mac->hw,
591 TD_DM_DRVP(8) | TD_DM_DRVN(8),
592 TRGMII_TD_ODT(i));
593
594 /* Assert/release MT7623 RXC reset */
595 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL,
596 TRGMII_RCK_CTRL);
597 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL);
598 }
599 }
600
601 switch (state->interface) {
602 case PHY_INTERFACE_MODE_MII:
603 case PHY_INTERFACE_MODE_GMII:
604 ge_mode = 1;
605 break;
606 default:
607 ge_mode = 0;
608 break;
609 }
610
611 /* put the gmac into the right mode */
612 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
613 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
614 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
615 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
616
617 mac->interface = state->interface;
618 }
619
620 /* SGMII */
621 if (state->interface == PHY_INTERFACE_MODE_SGMII ||
622 phy_interface_mode_is_8023z(state->interface)) {
623 /* The path GMAC to SGMII will be enabled once the SGMIISYS is
624 * being setup done.
625 */
626 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
627
628 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
629 SYSCFG0_SGMII_MASK,
630 ~(u32)SYSCFG0_SGMII_MASK);
631
632 /* Save the syscfg0 value for mac_finish */
633 mac->syscfg0 = val;
634 } else if (phylink_autoneg_inband(mode)) {
635 dev_err(eth->dev,
636 "In-band mode not supported in non SGMII mode!\n");
637 return;
638 }
639
640 /* Setup gmac */
641 if (mtk_is_netsys_v3_or_greater(eth) &&
642 mac->interface == PHY_INTERFACE_MODE_INTERNAL) {
643 mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
644 mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
645
646 mtk_setup_bridge_switch(eth);
647 }
648
649 return;
650
651 err_phy:
652 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__,
653 mac->id, phy_modes(state->interface));
654 return;
655
656 init_err:
657 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__,
658 mac->id, phy_modes(state->interface), err);
659 }
660
mtk_mac_finish(struct phylink_config * config,unsigned int mode,phy_interface_t interface)661 static int mtk_mac_finish(struct phylink_config *config, unsigned int mode,
662 phy_interface_t interface)
663 {
664 struct mtk_mac *mac = container_of(config, struct mtk_mac,
665 phylink_config);
666 struct mtk_eth *eth = mac->hw;
667 u32 mcr_cur, mcr_new;
668
669 /* Enable SGMII */
670 if (interface == PHY_INTERFACE_MODE_SGMII ||
671 phy_interface_mode_is_8023z(interface))
672 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
673 SYSCFG0_SGMII_MASK, mac->syscfg0);
674
675 /* Setup gmac */
676 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
677 mcr_new = mcr_cur;
678 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE |
679 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_RX_FIFO_CLR_DIS;
680
681 /* Only update control register when needed! */
682 if (mcr_new != mcr_cur)
683 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
684
685 return 0;
686 }
687
mtk_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)688 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
689 phy_interface_t interface)
690 {
691 struct mtk_mac *mac = container_of(config, struct mtk_mac,
692 phylink_config);
693 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
694
695 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK);
696 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
697 }
698
mtk_set_queue_speed(struct mtk_eth * eth,unsigned int idx,int speed)699 static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
700 int speed)
701 {
702 const struct mtk_soc_data *soc = eth->soc;
703 u32 ofs, val;
704
705 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA))
706 return;
707
708 val = MTK_QTX_SCH_MIN_RATE_EN |
709 /* minimum: 10 Mbps */
710 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
711 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
712 MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
713 if (mtk_is_netsys_v1(eth))
714 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
715
716 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
717 switch (speed) {
718 case SPEED_10:
719 val |= MTK_QTX_SCH_MAX_RATE_EN |
720 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) |
721 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 2) |
722 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1);
723 break;
724 case SPEED_100:
725 val |= MTK_QTX_SCH_MAX_RATE_EN |
726 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) |
727 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 3) |
728 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1);
729 break;
730 case SPEED_1000:
731 val |= MTK_QTX_SCH_MAX_RATE_EN |
732 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 105) |
733 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) |
734 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10);
735 break;
736 default:
737 break;
738 }
739 } else {
740 switch (speed) {
741 case SPEED_10:
742 val |= MTK_QTX_SCH_MAX_RATE_EN |
743 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) |
744 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) |
745 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1);
746 break;
747 case SPEED_100:
748 val |= MTK_QTX_SCH_MAX_RATE_EN |
749 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) |
750 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5) |
751 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1);
752 break;
753 case SPEED_1000:
754 val |= MTK_QTX_SCH_MAX_RATE_EN |
755 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) |
756 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 6) |
757 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10);
758 break;
759 default:
760 break;
761 }
762 }
763
764 ofs = MTK_QTX_OFFSET * idx;
765 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
766 }
767
mtk_mac_link_up(struct phylink_config * config,struct phy_device * phy,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)768 static void mtk_mac_link_up(struct phylink_config *config,
769 struct phy_device *phy,
770 unsigned int mode, phy_interface_t interface,
771 int speed, int duplex, bool tx_pause, bool rx_pause)
772 {
773 struct mtk_mac *mac = container_of(config, struct mtk_mac,
774 phylink_config);
775 u32 mcr;
776
777 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
778 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 |
779 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC |
780 MAC_MCR_FORCE_RX_FC);
781
782 /* Configure speed */
783 mac->speed = speed;
784 switch (speed) {
785 case SPEED_2500:
786 case SPEED_1000:
787 mcr |= MAC_MCR_SPEED_1000;
788 break;
789 case SPEED_100:
790 mcr |= MAC_MCR_SPEED_100;
791 break;
792 }
793
794 /* Configure duplex */
795 if (duplex == DUPLEX_FULL)
796 mcr |= MAC_MCR_FORCE_DPX;
797
798 /* Configure pause modes - phylink will avoid these for half duplex */
799 if (tx_pause)
800 mcr |= MAC_MCR_FORCE_TX_FC;
801 if (rx_pause)
802 mcr |= MAC_MCR_FORCE_RX_FC;
803
804 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK;
805 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
806 }
807
808 static const struct phylink_mac_ops mtk_phylink_ops = {
809 .mac_select_pcs = mtk_mac_select_pcs,
810 .mac_config = mtk_mac_config,
811 .mac_finish = mtk_mac_finish,
812 .mac_link_down = mtk_mac_link_down,
813 .mac_link_up = mtk_mac_link_up,
814 };
815
mtk_mdio_init(struct mtk_eth * eth)816 static int mtk_mdio_init(struct mtk_eth *eth)
817 {
818 unsigned int max_clk = 2500000, divider;
819 struct device_node *mii_np;
820 int ret;
821 u32 val;
822
823 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
824 if (!mii_np) {
825 dev_err(eth->dev, "no %s child node found", "mdio-bus");
826 return -ENODEV;
827 }
828
829 if (!of_device_is_available(mii_np)) {
830 ret = -ENODEV;
831 goto err_put_node;
832 }
833
834 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
835 if (!eth->mii_bus) {
836 ret = -ENOMEM;
837 goto err_put_node;
838 }
839
840 eth->mii_bus->name = "mdio";
841 eth->mii_bus->read = mtk_mdio_read_c22;
842 eth->mii_bus->write = mtk_mdio_write_c22;
843 eth->mii_bus->read_c45 = mtk_mdio_read_c45;
844 eth->mii_bus->write_c45 = mtk_mdio_write_c45;
845 eth->mii_bus->priv = eth;
846 eth->mii_bus->parent = eth->dev;
847
848 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
849
850 if (!of_property_read_u32(mii_np, "clock-frequency", &val)) {
851 if (val > MDC_MAX_FREQ || val < MDC_MAX_FREQ / MDC_MAX_DIVIDER) {
852 dev_err(eth->dev, "MDIO clock frequency out of range");
853 ret = -EINVAL;
854 goto err_put_node;
855 }
856 max_clk = val;
857 }
858 divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);
859
860 /* Configure MDC Turbo Mode */
861 if (mtk_is_netsys_v3_or_greater(eth))
862 mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3);
863
864 /* Configure MDC Divider */
865 val = FIELD_PREP(PPSC_MDC_CFG, divider);
866 if (!mtk_is_netsys_v3_or_greater(eth))
867 val |= PPSC_MDC_TURBO;
868 mtk_m32(eth, PPSC_MDC_CFG, val, MTK_PPSC);
869
870 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider);
871
872 ret = of_mdiobus_register(eth->mii_bus, mii_np);
873
874 err_put_node:
875 of_node_put(mii_np);
876 return ret;
877 }
878
mtk_mdio_cleanup(struct mtk_eth * eth)879 static void mtk_mdio_cleanup(struct mtk_eth *eth)
880 {
881 if (!eth->mii_bus)
882 return;
883
884 mdiobus_unregister(eth->mii_bus);
885 }
886
mtk_tx_irq_disable(struct mtk_eth * eth,u32 mask)887 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask)
888 {
889 unsigned long flags;
890 u32 val;
891
892 spin_lock_irqsave(ð->tx_irq_lock, flags);
893 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask);
894 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask);
895 spin_unlock_irqrestore(ð->tx_irq_lock, flags);
896 }
897
mtk_tx_irq_enable(struct mtk_eth * eth,u32 mask)898 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask)
899 {
900 unsigned long flags;
901 u32 val;
902
903 spin_lock_irqsave(ð->tx_irq_lock, flags);
904 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask);
905 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask);
906 spin_unlock_irqrestore(ð->tx_irq_lock, flags);
907 }
908
mtk_rx_irq_disable(struct mtk_eth * eth,u32 mask)909 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask)
910 {
911 unsigned long flags;
912 u32 val;
913
914 spin_lock_irqsave(ð->rx_irq_lock, flags);
915 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask);
916 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask);
917 spin_unlock_irqrestore(ð->rx_irq_lock, flags);
918 }
919
mtk_rx_irq_enable(struct mtk_eth * eth,u32 mask)920 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask)
921 {
922 unsigned long flags;
923 u32 val;
924
925 spin_lock_irqsave(ð->rx_irq_lock, flags);
926 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask);
927 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask);
928 spin_unlock_irqrestore(ð->rx_irq_lock, flags);
929 }
930
mtk_set_mac_address(struct net_device * dev,void * p)931 static int mtk_set_mac_address(struct net_device *dev, void *p)
932 {
933 int ret = eth_mac_addr(dev, p);
934 struct mtk_mac *mac = netdev_priv(dev);
935 struct mtk_eth *eth = mac->hw;
936 const char *macaddr = dev->dev_addr;
937
938 if (ret)
939 return ret;
940
941 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
942 return -EBUSY;
943
944 spin_lock_bh(&mac->hw->page_lock);
945 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
946 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
947 MT7628_SDM_MAC_ADRH);
948 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
949 (macaddr[4] << 8) | macaddr[5],
950 MT7628_SDM_MAC_ADRL);
951 } else {
952 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
953 MTK_GDMA_MAC_ADRH(mac->id));
954 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
955 (macaddr[4] << 8) | macaddr[5],
956 MTK_GDMA_MAC_ADRL(mac->id));
957 }
958 spin_unlock_bh(&mac->hw->page_lock);
959
960 return 0;
961 }
962
mtk_stats_update_mac(struct mtk_mac * mac)963 void mtk_stats_update_mac(struct mtk_mac *mac)
964 {
965 struct mtk_hw_stats *hw_stats = mac->hw_stats;
966 struct mtk_eth *eth = mac->hw;
967
968 u64_stats_update_begin(&hw_stats->syncp);
969
970 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
971 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT);
972 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT);
973 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT);
974 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT);
975 hw_stats->rx_checksum_errors +=
976 mtk_r32(mac->hw, MT7628_SDM_CS_ERR);
977 } else {
978 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
979 unsigned int offs = hw_stats->reg_offset;
980 u64 stats;
981
982 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs);
983 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs);
984 if (stats)
985 hw_stats->rx_bytes += (stats << 32);
986 hw_stats->rx_packets +=
987 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs);
988 hw_stats->rx_overflow +=
989 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs);
990 hw_stats->rx_fcs_errors +=
991 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs);
992 hw_stats->rx_short_errors +=
993 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs);
994 hw_stats->rx_long_errors +=
995 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs);
996 hw_stats->rx_checksum_errors +=
997 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs);
998 hw_stats->rx_flow_control_packets +=
999 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs);
1000
1001 if (mtk_is_netsys_v3_or_greater(eth)) {
1002 hw_stats->tx_skip +=
1003 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs);
1004 hw_stats->tx_collisions +=
1005 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x54 + offs);
1006 hw_stats->tx_bytes +=
1007 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x40 + offs);
1008 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x44 + offs);
1009 if (stats)
1010 hw_stats->tx_bytes += (stats << 32);
1011 hw_stats->tx_packets +=
1012 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x48 + offs);
1013 } else {
1014 hw_stats->tx_skip +=
1015 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs);
1016 hw_stats->tx_collisions +=
1017 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs);
1018 hw_stats->tx_bytes +=
1019 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs);
1020 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs);
1021 if (stats)
1022 hw_stats->tx_bytes += (stats << 32);
1023 hw_stats->tx_packets +=
1024 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs);
1025 }
1026 }
1027
1028 u64_stats_update_end(&hw_stats->syncp);
1029 }
1030
mtk_stats_update(struct mtk_eth * eth)1031 static void mtk_stats_update(struct mtk_eth *eth)
1032 {
1033 int i;
1034
1035 for (i = 0; i < MTK_MAX_DEVS; i++) {
1036 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
1037 continue;
1038 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) {
1039 mtk_stats_update_mac(eth->mac[i]);
1040 spin_unlock(ð->mac[i]->hw_stats->stats_lock);
1041 }
1042 }
1043 }
1044
mtk_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * storage)1045 static void mtk_get_stats64(struct net_device *dev,
1046 struct rtnl_link_stats64 *storage)
1047 {
1048 struct mtk_mac *mac = netdev_priv(dev);
1049 struct mtk_hw_stats *hw_stats = mac->hw_stats;
1050 unsigned int start;
1051
1052 if (netif_running(dev) && netif_device_present(dev)) {
1053 if (spin_trylock_bh(&hw_stats->stats_lock)) {
1054 mtk_stats_update_mac(mac);
1055 spin_unlock_bh(&hw_stats->stats_lock);
1056 }
1057 }
1058
1059 do {
1060 start = u64_stats_fetch_begin(&hw_stats->syncp);
1061 storage->rx_packets = hw_stats->rx_packets;
1062 storage->tx_packets = hw_stats->tx_packets;
1063 storage->rx_bytes = hw_stats->rx_bytes;
1064 storage->tx_bytes = hw_stats->tx_bytes;
1065 storage->collisions = hw_stats->tx_collisions;
1066 storage->rx_length_errors = hw_stats->rx_short_errors +
1067 hw_stats->rx_long_errors;
1068 storage->rx_over_errors = hw_stats->rx_overflow;
1069 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
1070 storage->rx_errors = hw_stats->rx_checksum_errors;
1071 storage->tx_aborted_errors = hw_stats->tx_skip;
1072 } while (u64_stats_fetch_retry(&hw_stats->syncp, start));
1073
1074 storage->tx_errors = dev->stats.tx_errors;
1075 storage->rx_dropped = dev->stats.rx_dropped;
1076 storage->tx_dropped = dev->stats.tx_dropped;
1077 }
1078
mtk_max_frag_size(int mtu)1079 static inline int mtk_max_frag_size(int mtu)
1080 {
1081 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
1082 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K)
1083 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN;
1084
1085 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
1086 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
1087 }
1088
mtk_max_buf_size(int frag_size)1089 static inline int mtk_max_buf_size(int frag_size)
1090 {
1091 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
1092 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
1093
1094 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K);
1095
1096 return buf_size;
1097 }
1098
mtk_rx_get_desc(struct mtk_eth * eth,struct mtk_rx_dma_v2 * rxd,struct mtk_rx_dma_v2 * dma_rxd)1099 static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd,
1100 struct mtk_rx_dma_v2 *dma_rxd)
1101 {
1102 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
1103 if (!(rxd->rxd2 & RX_DMA_DONE))
1104 return false;
1105
1106 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
1107 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
1108 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
1109 if (mtk_is_netsys_v2_or_greater(eth)) {
1110 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
1111 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
1112 }
1113
1114 return true;
1115 }
1116
mtk_max_lro_buf_alloc(gfp_t gfp_mask)1117 static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask)
1118 {
1119 unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH);
1120 unsigned long data;
1121
1122 data = __get_free_pages(gfp_mask | __GFP_COMP | __GFP_NOWARN,
1123 get_order(size));
1124
1125 return (void *)data;
1126 }
1127
1128 /* the qdma core needs scratch memory to be setup */
mtk_init_fq_dma(struct mtk_eth * eth)1129 static int mtk_init_fq_dma(struct mtk_eth *eth)
1130 {
1131 const struct mtk_soc_data *soc = eth->soc;
1132 dma_addr_t phy_ring_tail;
1133 int cnt = MTK_QDMA_RING_SIZE;
1134 dma_addr_t dma_addr;
1135 int i;
1136
1137 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM))
1138 eth->scratch_ring = eth->sram_base;
1139 else
1140 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
1141 cnt * soc->txrx.txd_size,
1142 ð->phy_scratch_ring,
1143 GFP_KERNEL);
1144 if (unlikely(!eth->scratch_ring))
1145 return -ENOMEM;
1146
1147 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, GFP_KERNEL);
1148 if (unlikely(!eth->scratch_head))
1149 return -ENOMEM;
1150
1151 dma_addr = dma_map_single(eth->dma_dev,
1152 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
1153 DMA_FROM_DEVICE);
1154 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
1155 return -ENOMEM;
1156
1157 phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1);
1158
1159 for (i = 0; i < cnt; i++) {
1160 struct mtk_tx_dma_v2 *txd;
1161
1162 txd = eth->scratch_ring + i * soc->txrx.txd_size;
1163 txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
1164 if (i < cnt - 1)
1165 txd->txd2 = eth->phy_scratch_ring +
1166 (i + 1) * soc->txrx.txd_size;
1167
1168 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
1169 txd->txd4 = 0;
1170 if (mtk_is_netsys_v2_or_greater(eth)) {
1171 txd->txd5 = 0;
1172 txd->txd6 = 0;
1173 txd->txd7 = 0;
1174 txd->txd8 = 0;
1175 }
1176 }
1177
1178 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head);
1179 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail);
1180 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count);
1181 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen);
1182
1183 return 0;
1184 }
1185
mtk_qdma_phys_to_virt(struct mtk_tx_ring * ring,u32 desc)1186 static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
1187 {
1188 return ring->dma + (desc - ring->phys);
1189 }
1190
mtk_desc_to_tx_buf(struct mtk_tx_ring * ring,void * txd,u32 txd_size)1191 static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
1192 void *txd, u32 txd_size)
1193 {
1194 int idx = (txd - ring->dma) / txd_size;
1195
1196 return &ring->buf[idx];
1197 }
1198
qdma_to_pdma(struct mtk_tx_ring * ring,struct mtk_tx_dma * dma)1199 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring,
1200 struct mtk_tx_dma *dma)
1201 {
1202 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma;
1203 }
1204
txd_to_idx(struct mtk_tx_ring * ring,void * dma,u32 txd_size)1205 static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size)
1206 {
1207 return (dma - ring->dma) / txd_size;
1208 }
1209
mtk_tx_unmap(struct mtk_eth * eth,struct mtk_tx_buf * tx_buf,struct xdp_frame_bulk * bq,bool napi)1210 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,
1211 struct xdp_frame_bulk *bq, bool napi)
1212 {
1213 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1214 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
1215 dma_unmap_single(eth->dma_dev,
1216 dma_unmap_addr(tx_buf, dma_addr0),
1217 dma_unmap_len(tx_buf, dma_len0),
1218 DMA_TO_DEVICE);
1219 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
1220 dma_unmap_page(eth->dma_dev,
1221 dma_unmap_addr(tx_buf, dma_addr0),
1222 dma_unmap_len(tx_buf, dma_len0),
1223 DMA_TO_DEVICE);
1224 }
1225 } else {
1226 if (dma_unmap_len(tx_buf, dma_len0)) {
1227 dma_unmap_page(eth->dma_dev,
1228 dma_unmap_addr(tx_buf, dma_addr0),
1229 dma_unmap_len(tx_buf, dma_len0),
1230 DMA_TO_DEVICE);
1231 }
1232
1233 if (dma_unmap_len(tx_buf, dma_len1)) {
1234 dma_unmap_page(eth->dma_dev,
1235 dma_unmap_addr(tx_buf, dma_addr1),
1236 dma_unmap_len(tx_buf, dma_len1),
1237 DMA_TO_DEVICE);
1238 }
1239 }
1240
1241 if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
1242 if (tx_buf->type == MTK_TYPE_SKB) {
1243 struct sk_buff *skb = tx_buf->data;
1244
1245 if (napi)
1246 napi_consume_skb(skb, napi);
1247 else
1248 dev_kfree_skb_any(skb);
1249 } else {
1250 struct xdp_frame *xdpf = tx_buf->data;
1251
1252 if (napi && tx_buf->type == MTK_TYPE_XDP_TX)
1253 xdp_return_frame_rx_napi(xdpf);
1254 else if (bq)
1255 xdp_return_frame_bulk(xdpf, bq);
1256 else
1257 xdp_return_frame(xdpf);
1258 }
1259 }
1260 tx_buf->flags = 0;
1261 tx_buf->data = NULL;
1262 }
1263
setup_tx_buf(struct mtk_eth * eth,struct mtk_tx_buf * tx_buf,struct mtk_tx_dma * txd,dma_addr_t mapped_addr,size_t size,int idx)1264 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,
1265 struct mtk_tx_dma *txd, dma_addr_t mapped_addr,
1266 size_t size, int idx)
1267 {
1268 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1269 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
1270 dma_unmap_len_set(tx_buf, dma_len0, size);
1271 } else {
1272 if (idx & 1) {
1273 txd->txd3 = mapped_addr;
1274 txd->txd2 |= TX_DMA_PLEN1(size);
1275 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
1276 dma_unmap_len_set(tx_buf, dma_len1, size);
1277 } else {
1278 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
1279 txd->txd1 = mapped_addr;
1280 txd->txd2 = TX_DMA_PLEN0(size);
1281 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
1282 dma_unmap_len_set(tx_buf, dma_len0, size);
1283 }
1284 }
1285 }
1286
mtk_tx_set_dma_desc_v1(struct net_device * dev,void * txd,struct mtk_tx_dma_desc_info * info)1287 static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd,
1288 struct mtk_tx_dma_desc_info *info)
1289 {
1290 struct mtk_mac *mac = netdev_priv(dev);
1291 struct mtk_eth *eth = mac->hw;
1292 struct mtk_tx_dma *desc = txd;
1293 u32 data;
1294
1295 WRITE_ONCE(desc->txd1, info->addr);
1296
1297 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size) |
1298 FIELD_PREP(TX_DMA_PQID, info->qid);
1299 if (info->last)
1300 data |= TX_DMA_LS0;
1301 WRITE_ONCE(desc->txd3, data);
1302
1303 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */
1304 if (info->first) {
1305 if (info->gso)
1306 data |= TX_DMA_TSO;
1307 /* tx checksum offload */
1308 if (info->csum)
1309 data |= TX_DMA_CHKSUM;
1310 /* vlan header offload */
1311 if (info->vlan)
1312 data |= TX_DMA_INS_VLAN | info->vlan_tci;
1313 }
1314 WRITE_ONCE(desc->txd4, data);
1315 }
1316
mtk_tx_set_dma_desc_v2(struct net_device * dev,void * txd,struct mtk_tx_dma_desc_info * info)1317 static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd,
1318 struct mtk_tx_dma_desc_info *info)
1319 {
1320 struct mtk_mac *mac = netdev_priv(dev);
1321 struct mtk_tx_dma_v2 *desc = txd;
1322 struct mtk_eth *eth = mac->hw;
1323 u32 data;
1324
1325 WRITE_ONCE(desc->txd1, info->addr);
1326
1327 data = TX_DMA_PLEN0(info->size);
1328 if (info->last)
1329 data |= TX_DMA_LS0;
1330
1331 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
1332 data |= TX_DMA_PREP_ADDR64(info->addr);
1333
1334 WRITE_ONCE(desc->txd3, data);
1335
1336 /* set forward port */
1337 switch (mac->id) {
1338 case MTK_GMAC1_ID:
1339 data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2;
1340 break;
1341 case MTK_GMAC2_ID:
1342 data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2;
1343 break;
1344 case MTK_GMAC3_ID:
1345 data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2;
1346 break;
1347 }
1348
1349 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
1350 WRITE_ONCE(desc->txd4, data);
1351
1352 data = 0;
1353 if (info->first) {
1354 if (info->gso)
1355 data |= TX_DMA_TSO_V2;
1356 /* tx checksum offload */
1357 if (info->csum)
1358 data |= TX_DMA_CHKSUM_V2;
1359 if (mtk_is_netsys_v3_or_greater(eth) && netdev_uses_dsa(dev))
1360 data |= TX_DMA_SPTAG_V3;
1361 }
1362 WRITE_ONCE(desc->txd5, data);
1363
1364 data = 0;
1365 if (info->first && info->vlan)
1366 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci;
1367 WRITE_ONCE(desc->txd6, data);
1368
1369 WRITE_ONCE(desc->txd7, 0);
1370 WRITE_ONCE(desc->txd8, 0);
1371 }
1372
mtk_tx_set_dma_desc(struct net_device * dev,void * txd,struct mtk_tx_dma_desc_info * info)1373 static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd,
1374 struct mtk_tx_dma_desc_info *info)
1375 {
1376 struct mtk_mac *mac = netdev_priv(dev);
1377 struct mtk_eth *eth = mac->hw;
1378
1379 if (mtk_is_netsys_v2_or_greater(eth))
1380 mtk_tx_set_dma_desc_v2(dev, txd, info);
1381 else
1382 mtk_tx_set_dma_desc_v1(dev, txd, info);
1383 }
1384
mtk_tx_map(struct sk_buff * skb,struct net_device * dev,int tx_num,struct mtk_tx_ring * ring,bool gso)1385 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
1386 int tx_num, struct mtk_tx_ring *ring, bool gso)
1387 {
1388 struct mtk_tx_dma_desc_info txd_info = {
1389 .size = skb_headlen(skb),
1390 .gso = gso,
1391 .csum = skb->ip_summed == CHECKSUM_PARTIAL,
1392 .vlan = skb_vlan_tag_present(skb),
1393 .qid = skb_get_queue_mapping(skb),
1394 .vlan_tci = skb_vlan_tag_get(skb),
1395 .first = true,
1396 .last = !skb_is_nonlinear(skb),
1397 };
1398 struct netdev_queue *txq;
1399 struct mtk_mac *mac = netdev_priv(dev);
1400 struct mtk_eth *eth = mac->hw;
1401 const struct mtk_soc_data *soc = eth->soc;
1402 struct mtk_tx_dma *itxd, *txd;
1403 struct mtk_tx_dma *itxd_pdma, *txd_pdma;
1404 struct mtk_tx_buf *itx_buf, *tx_buf;
1405 int i, n_desc = 1;
1406 int queue = skb_get_queue_mapping(skb);
1407 int k = 0;
1408
1409 txq = netdev_get_tx_queue(dev, queue);
1410 itxd = ring->next_free;
1411 itxd_pdma = qdma_to_pdma(ring, itxd);
1412 if (itxd == ring->last_free)
1413 return -ENOMEM;
1414
1415 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
1416 memset(itx_buf, 0, sizeof(*itx_buf));
1417
1418 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size,
1419 DMA_TO_DEVICE);
1420 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr)))
1421 return -ENOMEM;
1422
1423 mtk_tx_set_dma_desc(dev, itxd, &txd_info);
1424
1425 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
1426 itx_buf->mac_id = mac->id;
1427 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size,
1428 k++);
1429
1430 /* TX SG offload */
1431 txd = itxd;
1432 txd_pdma = qdma_to_pdma(ring, txd);
1433
1434 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1435 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1436 unsigned int offset = 0;
1437 int frag_size = skb_frag_size(frag);
1438
1439 while (frag_size) {
1440 bool new_desc = true;
1441
1442 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) ||
1443 (i & 0x1)) {
1444 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
1445 txd_pdma = qdma_to_pdma(ring, txd);
1446 if (txd == ring->last_free)
1447 goto err_dma;
1448
1449 n_desc++;
1450 } else {
1451 new_desc = false;
1452 }
1453
1454 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
1455 txd_info.size = min_t(unsigned int, frag_size,
1456 soc->txrx.dma_max_len);
1457 txd_info.qid = queue;
1458 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
1459 !(frag_size - txd_info.size);
1460 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag,
1461 offset, txd_info.size,
1462 DMA_TO_DEVICE);
1463 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr)))
1464 goto err_dma;
1465
1466 mtk_tx_set_dma_desc(dev, txd, &txd_info);
1467
1468 tx_buf = mtk_desc_to_tx_buf(ring, txd,
1469 soc->txrx.txd_size);
1470 if (new_desc)
1471 memset(tx_buf, 0, sizeof(*tx_buf));
1472 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
1473 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
1474 tx_buf->mac_id = mac->id;
1475
1476 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr,
1477 txd_info.size, k++);
1478
1479 frag_size -= txd_info.size;
1480 offset += txd_info.size;
1481 }
1482 }
1483
1484 /* store skb to cleanup */
1485 itx_buf->type = MTK_TYPE_SKB;
1486 itx_buf->data = skb;
1487
1488 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1489 if (k & 0x1)
1490 txd_pdma->txd2 |= TX_DMA_LS0;
1491 else
1492 txd_pdma->txd2 |= TX_DMA_LS1;
1493 }
1494
1495 netdev_tx_sent_queue(txq, skb->len);
1496 skb_tx_timestamp(skb);
1497
1498 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
1499 atomic_sub(n_desc, &ring->free_count);
1500
1501 /* make sure that all changes to the dma ring are flushed before we
1502 * continue
1503 */
1504 wmb();
1505
1506 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1507 if (netif_xmit_stopped(txq) || !netdev_xmit_more())
1508 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr);
1509 } else {
1510 int next_idx;
1511
1512 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size),
1513 ring->dma_size);
1514 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
1515 }
1516
1517 return 0;
1518
1519 err_dma:
1520 do {
1521 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
1522
1523 /* unmap dma */
1524 mtk_tx_unmap(eth, tx_buf, NULL, false);
1525
1526 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1527 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA))
1528 itxd_pdma->txd2 = TX_DMA_DESP2_DEF;
1529
1530 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
1531 itxd_pdma = qdma_to_pdma(ring, itxd);
1532 } while (itxd != txd);
1533
1534 return -ENOMEM;
1535 }
1536
mtk_cal_txd_req(struct mtk_eth * eth,struct sk_buff * skb)1537 static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb)
1538 {
1539 int i, nfrags = 1;
1540 skb_frag_t *frag;
1541
1542 if (skb_is_gso(skb)) {
1543 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1544 frag = &skb_shinfo(skb)->frags[i];
1545 nfrags += DIV_ROUND_UP(skb_frag_size(frag),
1546 eth->soc->txrx.dma_max_len);
1547 }
1548 } else {
1549 nfrags += skb_shinfo(skb)->nr_frags;
1550 }
1551
1552 return nfrags;
1553 }
1554
mtk_queue_stopped(struct mtk_eth * eth)1555 static int mtk_queue_stopped(struct mtk_eth *eth)
1556 {
1557 int i;
1558
1559 for (i = 0; i < MTK_MAX_DEVS; i++) {
1560 if (!eth->netdev[i])
1561 continue;
1562 if (netif_queue_stopped(eth->netdev[i]))
1563 return 1;
1564 }
1565
1566 return 0;
1567 }
1568
mtk_wake_queue(struct mtk_eth * eth)1569 static void mtk_wake_queue(struct mtk_eth *eth)
1570 {
1571 int i;
1572
1573 for (i = 0; i < MTK_MAX_DEVS; i++) {
1574 if (!eth->netdev[i])
1575 continue;
1576 netif_tx_wake_all_queues(eth->netdev[i]);
1577 }
1578 }
1579
mtk_start_xmit(struct sk_buff * skb,struct net_device * dev)1580 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
1581 {
1582 struct mtk_mac *mac = netdev_priv(dev);
1583 struct mtk_eth *eth = mac->hw;
1584 struct mtk_tx_ring *ring = ð->tx_ring;
1585 struct net_device_stats *stats = &dev->stats;
1586 bool gso = false;
1587 int tx_num;
1588
1589 /* normally we can rely on the stack not calling this more than once,
1590 * however we have 2 queues running on the same ring so we need to lock
1591 * the ring access
1592 */
1593 spin_lock(ð->page_lock);
1594
1595 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
1596 goto drop;
1597
1598 tx_num = mtk_cal_txd_req(eth, skb);
1599 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
1600 netif_tx_stop_all_queues(dev);
1601 netif_err(eth, tx_queued, dev,
1602 "Tx Ring full when queue awake!\n");
1603 spin_unlock(ð->page_lock);
1604 return NETDEV_TX_BUSY;
1605 }
1606
1607 /* TSO: fill MSS info in tcp checksum field */
1608 if (skb_is_gso(skb)) {
1609 if (skb_cow_head(skb, 0)) {
1610 netif_warn(eth, tx_err, dev,
1611 "GSO expand head fail.\n");
1612 goto drop;
1613 }
1614
1615 if (skb_shinfo(skb)->gso_type &
1616 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1617 gso = true;
1618 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
1619 }
1620 }
1621
1622 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
1623 goto drop;
1624
1625 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
1626 netif_tx_stop_all_queues(dev);
1627
1628 spin_unlock(ð->page_lock);
1629
1630 return NETDEV_TX_OK;
1631
1632 drop:
1633 spin_unlock(ð->page_lock);
1634 stats->tx_dropped++;
1635 dev_kfree_skb_any(skb);
1636 return NETDEV_TX_OK;
1637 }
1638
mtk_get_rx_ring(struct mtk_eth * eth)1639 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
1640 {
1641 int i;
1642 struct mtk_rx_ring *ring;
1643 int idx;
1644
1645 if (!eth->hwlro)
1646 return ð->rx_ring[0];
1647
1648 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
1649 struct mtk_rx_dma *rxd;
1650
1651 ring = ð->rx_ring[i];
1652 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
1653 rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
1654 if (rxd->rxd2 & RX_DMA_DONE) {
1655 ring->calc_idx_update = true;
1656 return ring;
1657 }
1658 }
1659
1660 return NULL;
1661 }
1662
mtk_update_rx_cpu_idx(struct mtk_eth * eth)1663 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
1664 {
1665 struct mtk_rx_ring *ring;
1666 int i;
1667
1668 if (!eth->hwlro) {
1669 ring = ð->rx_ring[0];
1670 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1671 } else {
1672 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
1673 ring = ð->rx_ring[i];
1674 if (ring->calc_idx_update) {
1675 ring->calc_idx_update = false;
1676 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1677 }
1678 }
1679 }
1680 }
1681
mtk_page_pool_enabled(struct mtk_eth * eth)1682 static bool mtk_page_pool_enabled(struct mtk_eth *eth)
1683 {
1684 return mtk_is_netsys_v2_or_greater(eth);
1685 }
1686
mtk_create_page_pool(struct mtk_eth * eth,struct xdp_rxq_info * xdp_q,int id,int size)1687 static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth,
1688 struct xdp_rxq_info *xdp_q,
1689 int id, int size)
1690 {
1691 struct page_pool_params pp_params = {
1692 .order = 0,
1693 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
1694 .pool_size = size,
1695 .nid = NUMA_NO_NODE,
1696 .dev = eth->dma_dev,
1697 .offset = MTK_PP_HEADROOM,
1698 .max_len = MTK_PP_MAX_BUF_SIZE,
1699 };
1700 struct page_pool *pp;
1701 int err;
1702
1703 pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL
1704 : DMA_FROM_DEVICE;
1705 pp = page_pool_create(&pp_params);
1706 if (IS_ERR(pp))
1707 return pp;
1708
1709 err = __xdp_rxq_info_reg(xdp_q, ð->dummy_dev, id,
1710 eth->rx_napi.napi_id, PAGE_SIZE);
1711 if (err < 0)
1712 goto err_free_pp;
1713
1714 err = xdp_rxq_info_reg_mem_model(xdp_q, MEM_TYPE_PAGE_POOL, pp);
1715 if (err)
1716 goto err_unregister_rxq;
1717
1718 return pp;
1719
1720 err_unregister_rxq:
1721 xdp_rxq_info_unreg(xdp_q);
1722 err_free_pp:
1723 page_pool_destroy(pp);
1724
1725 return ERR_PTR(err);
1726 }
1727
mtk_page_pool_get_buff(struct page_pool * pp,dma_addr_t * dma_addr,gfp_t gfp_mask)1728 static void *mtk_page_pool_get_buff(struct page_pool *pp, dma_addr_t *dma_addr,
1729 gfp_t gfp_mask)
1730 {
1731 struct page *page;
1732
1733 page = page_pool_alloc_pages(pp, gfp_mask | __GFP_NOWARN);
1734 if (!page)
1735 return NULL;
1736
1737 *dma_addr = page_pool_get_dma_addr(page) + MTK_PP_HEADROOM;
1738 return page_address(page);
1739 }
1740
mtk_rx_put_buff(struct mtk_rx_ring * ring,void * data,bool napi)1741 static void mtk_rx_put_buff(struct mtk_rx_ring *ring, void *data, bool napi)
1742 {
1743 if (ring->page_pool)
1744 page_pool_put_full_page(ring->page_pool,
1745 virt_to_head_page(data), napi);
1746 else
1747 skb_free_frag(data);
1748 }
1749
mtk_xdp_frame_map(struct mtk_eth * eth,struct net_device * dev,struct mtk_tx_dma_desc_info * txd_info,struct mtk_tx_dma * txd,struct mtk_tx_buf * tx_buf,void * data,u16 headroom,int index,bool dma_map)1750 static int mtk_xdp_frame_map(struct mtk_eth *eth, struct net_device *dev,
1751 struct mtk_tx_dma_desc_info *txd_info,
1752 struct mtk_tx_dma *txd, struct mtk_tx_buf *tx_buf,
1753 void *data, u16 headroom, int index, bool dma_map)
1754 {
1755 struct mtk_tx_ring *ring = ð->tx_ring;
1756 struct mtk_mac *mac = netdev_priv(dev);
1757 struct mtk_tx_dma *txd_pdma;
1758
1759 if (dma_map) { /* ndo_xdp_xmit */
1760 txd_info->addr = dma_map_single(eth->dma_dev, data,
1761 txd_info->size, DMA_TO_DEVICE);
1762 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr)))
1763 return -ENOMEM;
1764
1765 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
1766 } else {
1767 struct page *page = virt_to_head_page(data);
1768
1769 txd_info->addr = page_pool_get_dma_addr(page) +
1770 sizeof(struct xdp_frame) + headroom;
1771 dma_sync_single_for_device(eth->dma_dev, txd_info->addr,
1772 txd_info->size, DMA_BIDIRECTIONAL);
1773 }
1774 mtk_tx_set_dma_desc(dev, txd, txd_info);
1775
1776 tx_buf->mac_id = mac->id;
1777 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX;
1778 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
1779
1780 txd_pdma = qdma_to_pdma(ring, txd);
1781 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info->addr, txd_info->size,
1782 index);
1783
1784 return 0;
1785 }
1786
mtk_xdp_submit_frame(struct mtk_eth * eth,struct xdp_frame * xdpf,struct net_device * dev,bool dma_map)1787 static int mtk_xdp_submit_frame(struct mtk_eth *eth, struct xdp_frame *xdpf,
1788 struct net_device *dev, bool dma_map)
1789 {
1790 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf);
1791 const struct mtk_soc_data *soc = eth->soc;
1792 struct mtk_tx_ring *ring = ð->tx_ring;
1793 struct mtk_mac *mac = netdev_priv(dev);
1794 struct mtk_tx_dma_desc_info txd_info = {
1795 .size = xdpf->len,
1796 .first = true,
1797 .last = !xdp_frame_has_frags(xdpf),
1798 .qid = mac->id,
1799 };
1800 int err, index = 0, n_desc = 1, nr_frags;
1801 struct mtk_tx_buf *htx_buf, *tx_buf;
1802 struct mtk_tx_dma *htxd, *txd;
1803 void *data = xdpf->data;
1804
1805 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
1806 return -EBUSY;
1807
1808 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0;
1809 if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags))
1810 return -EBUSY;
1811
1812 spin_lock(ð->page_lock);
1813
1814 txd = ring->next_free;
1815 if (txd == ring->last_free) {
1816 spin_unlock(ð->page_lock);
1817 return -ENOMEM;
1818 }
1819 htxd = txd;
1820
1821 tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size);
1822 memset(tx_buf, 0, sizeof(*tx_buf));
1823 htx_buf = tx_buf;
1824
1825 for (;;) {
1826 err = mtk_xdp_frame_map(eth, dev, &txd_info, txd, tx_buf,
1827 data, xdpf->headroom, index, dma_map);
1828 if (err < 0)
1829 goto unmap;
1830
1831 if (txd_info.last)
1832 break;
1833
1834 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) {
1835 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
1836 if (txd == ring->last_free)
1837 goto unmap;
1838
1839 tx_buf = mtk_desc_to_tx_buf(ring, txd,
1840 soc->txrx.txd_size);
1841 memset(tx_buf, 0, sizeof(*tx_buf));
1842 n_desc++;
1843 }
1844
1845 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
1846 txd_info.size = skb_frag_size(&sinfo->frags[index]);
1847 txd_info.last = index + 1 == nr_frags;
1848 txd_info.qid = mac->id;
1849 data = skb_frag_address(&sinfo->frags[index]);
1850
1851 index++;
1852 }
1853 /* store xdpf for cleanup */
1854 htx_buf->data = xdpf;
1855
1856 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1857 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, txd);
1858
1859 if (index & 1)
1860 txd_pdma->txd2 |= TX_DMA_LS0;
1861 else
1862 txd_pdma->txd2 |= TX_DMA_LS1;
1863 }
1864
1865 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
1866 atomic_sub(n_desc, &ring->free_count);
1867
1868 /* make sure that all changes to the dma ring are flushed before we
1869 * continue
1870 */
1871 wmb();
1872
1873 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1874 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr);
1875 } else {
1876 int idx;
1877
1878 idx = txd_to_idx(ring, txd, soc->txrx.txd_size);
1879 mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size),
1880 MT7628_TX_CTX_IDX0);
1881 }
1882
1883 spin_unlock(ð->page_lock);
1884
1885 return 0;
1886
1887 unmap:
1888 while (htxd != txd) {
1889 tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size);
1890 mtk_tx_unmap(eth, tx_buf, NULL, false);
1891
1892 htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1893 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1894 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, htxd);
1895
1896 txd_pdma->txd2 = TX_DMA_DESP2_DEF;
1897 }
1898
1899 htxd = mtk_qdma_phys_to_virt(ring, htxd->txd2);
1900 }
1901
1902 spin_unlock(ð->page_lock);
1903
1904 return err;
1905 }
1906
mtk_xdp_xmit(struct net_device * dev,int num_frame,struct xdp_frame ** frames,u32 flags)1907 static int mtk_xdp_xmit(struct net_device *dev, int num_frame,
1908 struct xdp_frame **frames, u32 flags)
1909 {
1910 struct mtk_mac *mac = netdev_priv(dev);
1911 struct mtk_hw_stats *hw_stats = mac->hw_stats;
1912 struct mtk_eth *eth = mac->hw;
1913 int i, nxmit = 0;
1914
1915 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
1916 return -EINVAL;
1917
1918 for (i = 0; i < num_frame; i++) {
1919 if (mtk_xdp_submit_frame(eth, frames[i], dev, true))
1920 break;
1921 nxmit++;
1922 }
1923
1924 u64_stats_update_begin(&hw_stats->syncp);
1925 hw_stats->xdp_stats.tx_xdp_xmit += nxmit;
1926 hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit;
1927 u64_stats_update_end(&hw_stats->syncp);
1928
1929 return nxmit;
1930 }
1931
mtk_xdp_run(struct mtk_eth * eth,struct mtk_rx_ring * ring,struct xdp_buff * xdp,struct net_device * dev)1932 static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring,
1933 struct xdp_buff *xdp, struct net_device *dev)
1934 {
1935 struct mtk_mac *mac = netdev_priv(dev);
1936 struct mtk_hw_stats *hw_stats = mac->hw_stats;
1937 u64 *count = &hw_stats->xdp_stats.rx_xdp_drop;
1938 struct bpf_prog *prog;
1939 u32 act = XDP_PASS;
1940
1941 rcu_read_lock();
1942
1943 prog = rcu_dereference(eth->prog);
1944 if (!prog)
1945 goto out;
1946
1947 act = bpf_prog_run_xdp(prog, xdp);
1948 switch (act) {
1949 case XDP_PASS:
1950 count = &hw_stats->xdp_stats.rx_xdp_pass;
1951 goto update_stats;
1952 case XDP_REDIRECT:
1953 if (unlikely(xdp_do_redirect(dev, xdp, prog))) {
1954 act = XDP_DROP;
1955 break;
1956 }
1957
1958 count = &hw_stats->xdp_stats.rx_xdp_redirect;
1959 goto update_stats;
1960 case XDP_TX: {
1961 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
1962
1963 if (!xdpf || mtk_xdp_submit_frame(eth, xdpf, dev, false)) {
1964 count = &hw_stats->xdp_stats.rx_xdp_tx_errors;
1965 act = XDP_DROP;
1966 break;
1967 }
1968
1969 count = &hw_stats->xdp_stats.rx_xdp_tx;
1970 goto update_stats;
1971 }
1972 default:
1973 bpf_warn_invalid_xdp_action(dev, prog, act);
1974 fallthrough;
1975 case XDP_ABORTED:
1976 trace_xdp_exception(dev, prog, act);
1977 fallthrough;
1978 case XDP_DROP:
1979 break;
1980 }
1981
1982 page_pool_put_full_page(ring->page_pool,
1983 virt_to_head_page(xdp->data), true);
1984
1985 update_stats:
1986 u64_stats_update_begin(&hw_stats->syncp);
1987 *count = *count + 1;
1988 u64_stats_update_end(&hw_stats->syncp);
1989 out:
1990 rcu_read_unlock();
1991
1992 return act;
1993 }
1994
mtk_poll_rx(struct napi_struct * napi,int budget,struct mtk_eth * eth)1995 static int mtk_poll_rx(struct napi_struct *napi, int budget,
1996 struct mtk_eth *eth)
1997 {
1998 struct dim_sample dim_sample = {};
1999 struct mtk_rx_ring *ring;
2000 bool xdp_flush = false;
2001 int idx;
2002 struct sk_buff *skb;
2003 u64 addr64 = 0;
2004 u8 *data, *new_data;
2005 struct mtk_rx_dma_v2 *rxd, trxd;
2006 int done = 0, bytes = 0;
2007 dma_addr_t dma_addr = DMA_MAPPING_ERROR;
2008
2009 while (done < budget) {
2010 unsigned int pktlen, *rxdcsum;
2011 struct net_device *netdev;
2012 u32 hash, reason;
2013 int mac = 0;
2014
2015 ring = mtk_get_rx_ring(eth);
2016 if (unlikely(!ring))
2017 goto rx_done;
2018
2019 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
2020 rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
2021 data = ring->data[idx];
2022
2023 if (!mtk_rx_get_desc(eth, &trxd, rxd))
2024 break;
2025
2026 /* find out which mac the packet come from. values start at 1 */
2027 if (mtk_is_netsys_v2_or_greater(eth)) {
2028 u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5);
2029
2030 switch (val) {
2031 case PSE_GDM1_PORT:
2032 case PSE_GDM2_PORT:
2033 mac = val - 1;
2034 break;
2035 case PSE_GDM3_PORT:
2036 mac = MTK_GMAC3_ID;
2037 break;
2038 default:
2039 break;
2040 }
2041 } else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
2042 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) {
2043 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1;
2044 }
2045
2046 if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS ||
2047 !eth->netdev[mac]))
2048 goto release_desc;
2049
2050 netdev = eth->netdev[mac];
2051
2052 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
2053 goto release_desc;
2054
2055 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
2056
2057 /* alloc new buffer */
2058 if (ring->page_pool) {
2059 struct page *page = virt_to_head_page(data);
2060 struct xdp_buff xdp;
2061 u32 ret;
2062
2063 new_data = mtk_page_pool_get_buff(ring->page_pool,
2064 &dma_addr,
2065 GFP_ATOMIC);
2066 if (unlikely(!new_data)) {
2067 netdev->stats.rx_dropped++;
2068 goto release_desc;
2069 }
2070
2071 dma_sync_single_for_cpu(eth->dma_dev,
2072 page_pool_get_dma_addr(page) + MTK_PP_HEADROOM,
2073 pktlen, page_pool_get_dma_dir(ring->page_pool));
2074
2075 xdp_init_buff(&xdp, PAGE_SIZE, &ring->xdp_q);
2076 xdp_prepare_buff(&xdp, data, MTK_PP_HEADROOM, pktlen,
2077 false);
2078 xdp_buff_clear_frags_flag(&xdp);
2079
2080 ret = mtk_xdp_run(eth, ring, &xdp, netdev);
2081 if (ret == XDP_REDIRECT)
2082 xdp_flush = true;
2083
2084 if (ret != XDP_PASS)
2085 goto skip_rx;
2086
2087 skb = build_skb(data, PAGE_SIZE);
2088 if (unlikely(!skb)) {
2089 page_pool_put_full_page(ring->page_pool,
2090 page, true);
2091 netdev->stats.rx_dropped++;
2092 goto skip_rx;
2093 }
2094
2095 skb_reserve(skb, xdp.data - xdp.data_hard_start);
2096 skb_put(skb, xdp.data_end - xdp.data);
2097 skb_mark_for_recycle(skb);
2098 } else {
2099 if (ring->frag_size <= PAGE_SIZE)
2100 new_data = napi_alloc_frag(ring->frag_size);
2101 else
2102 new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC);
2103
2104 if (unlikely(!new_data)) {
2105 netdev->stats.rx_dropped++;
2106 goto release_desc;
2107 }
2108
2109 dma_addr = dma_map_single(eth->dma_dev,
2110 new_data + NET_SKB_PAD + eth->ip_align,
2111 ring->buf_size, DMA_FROM_DEVICE);
2112 if (unlikely(dma_mapping_error(eth->dma_dev,
2113 dma_addr))) {
2114 skb_free_frag(new_data);
2115 netdev->stats.rx_dropped++;
2116 goto release_desc;
2117 }
2118
2119 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
2120 addr64 = RX_DMA_GET_ADDR64(trxd.rxd2);
2121
2122 dma_unmap_single(eth->dma_dev, ((u64)trxd.rxd1 | addr64),
2123 ring->buf_size, DMA_FROM_DEVICE);
2124
2125 skb = build_skb(data, ring->frag_size);
2126 if (unlikely(!skb)) {
2127 netdev->stats.rx_dropped++;
2128 skb_free_frag(data);
2129 goto skip_rx;
2130 }
2131
2132 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
2133 skb_put(skb, pktlen);
2134 }
2135
2136 skb->dev = netdev;
2137 bytes += skb->len;
2138
2139 if (mtk_is_netsys_v2_or_greater(eth)) {
2140 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
2141 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
2142 if (hash != MTK_RXD5_FOE_ENTRY)
2143 skb_set_hash(skb, jhash_1word(hash, 0),
2144 PKT_HASH_TYPE_L4);
2145 rxdcsum = &trxd.rxd3;
2146 } else {
2147 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4);
2148 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY;
2149 if (hash != MTK_RXD4_FOE_ENTRY)
2150 skb_set_hash(skb, jhash_1word(hash, 0),
2151 PKT_HASH_TYPE_L4);
2152 rxdcsum = &trxd.rxd4;
2153 }
2154
2155 if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid)
2156 skb->ip_summed = CHECKSUM_UNNECESSARY;
2157 else
2158 skb_checksum_none_assert(skb);
2159 skb->protocol = eth_type_trans(skb, netdev);
2160
2161 /* When using VLAN untagging in combination with DSA, the
2162 * hardware treats the MTK special tag as a VLAN and untags it.
2163 */
2164 if (mtk_is_netsys_v1(eth) && (trxd.rxd2 & RX_DMA_VTAG) &&
2165 netdev_uses_dsa(netdev)) {
2166 unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0);
2167
2168 if (port < ARRAY_SIZE(eth->dsa_meta) &&
2169 eth->dsa_meta[port])
2170 skb_dst_set_noref(skb, ð->dsa_meta[port]->dst);
2171 }
2172
2173 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)
2174 mtk_ppe_check_skb(eth->ppe[0], skb, hash);
2175
2176 skb_record_rx_queue(skb, 0);
2177 napi_gro_receive(napi, skb);
2178
2179 skip_rx:
2180 ring->data[idx] = new_data;
2181 rxd->rxd1 = (unsigned int)dma_addr;
2182 release_desc:
2183 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) {
2184 if (unlikely(dma_addr == DMA_MAPPING_ERROR))
2185 addr64 = FIELD_GET(RX_DMA_ADDR64_MASK,
2186 rxd->rxd2);
2187 else
2188 addr64 = RX_DMA_PREP_ADDR64(dma_addr);
2189 }
2190
2191 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
2192 rxd->rxd2 = RX_DMA_LSO;
2193 else
2194 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size) | addr64;
2195
2196 ring->calc_idx = idx;
2197 done++;
2198 }
2199
2200 rx_done:
2201 if (done) {
2202 /* make sure that all changes to the dma ring are flushed before
2203 * we continue
2204 */
2205 wmb();
2206 mtk_update_rx_cpu_idx(eth);
2207 }
2208
2209 eth->rx_packets += done;
2210 eth->rx_bytes += bytes;
2211 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes,
2212 &dim_sample);
2213 net_dim(ð->rx_dim, dim_sample);
2214
2215 if (xdp_flush)
2216 xdp_do_flush_map();
2217
2218 return done;
2219 }
2220
2221 struct mtk_poll_state {
2222 struct netdev_queue *txq;
2223 unsigned int total;
2224 unsigned int done;
2225 unsigned int bytes;
2226 };
2227
2228 static void
mtk_poll_tx_done(struct mtk_eth * eth,struct mtk_poll_state * state,u8 mac,struct sk_buff * skb)2229 mtk_poll_tx_done(struct mtk_eth *eth, struct mtk_poll_state *state, u8 mac,
2230 struct sk_buff *skb)
2231 {
2232 struct netdev_queue *txq;
2233 struct net_device *dev;
2234 unsigned int bytes = skb->len;
2235
2236 state->total++;
2237 eth->tx_packets++;
2238 eth->tx_bytes += bytes;
2239
2240 dev = eth->netdev[mac];
2241 if (!dev)
2242 return;
2243
2244 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
2245 if (state->txq == txq) {
2246 state->done++;
2247 state->bytes += bytes;
2248 return;
2249 }
2250
2251 if (state->txq)
2252 netdev_tx_completed_queue(state->txq, state->done, state->bytes);
2253
2254 state->txq = txq;
2255 state->done = 1;
2256 state->bytes = bytes;
2257 }
2258
mtk_poll_tx_qdma(struct mtk_eth * eth,int budget,struct mtk_poll_state * state)2259 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget,
2260 struct mtk_poll_state *state)
2261 {
2262 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2263 struct mtk_tx_ring *ring = ð->tx_ring;
2264 struct mtk_tx_buf *tx_buf;
2265 struct xdp_frame_bulk bq;
2266 struct mtk_tx_dma *desc;
2267 u32 cpu, dma;
2268
2269 cpu = ring->last_free_ptr;
2270 dma = mtk_r32(eth, reg_map->qdma.drx_ptr);
2271
2272 desc = mtk_qdma_phys_to_virt(ring, cpu);
2273 xdp_frame_bulk_init(&bq);
2274
2275 while ((cpu != dma) && budget) {
2276 u32 next_cpu = desc->txd2;
2277
2278 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
2279 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
2280 break;
2281
2282 tx_buf = mtk_desc_to_tx_buf(ring, desc,
2283 eth->soc->txrx.txd_size);
2284 if (!tx_buf->data)
2285 break;
2286
2287 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
2288 if (tx_buf->type == MTK_TYPE_SKB)
2289 mtk_poll_tx_done(eth, state, tx_buf->mac_id,
2290 tx_buf->data);
2291
2292 budget--;
2293 }
2294 mtk_tx_unmap(eth, tx_buf, &bq, true);
2295
2296 ring->last_free = desc;
2297 atomic_inc(&ring->free_count);
2298
2299 cpu = next_cpu;
2300 }
2301 xdp_flush_frame_bulk(&bq);
2302
2303 ring->last_free_ptr = cpu;
2304 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr);
2305
2306 return budget;
2307 }
2308
mtk_poll_tx_pdma(struct mtk_eth * eth,int budget,struct mtk_poll_state * state)2309 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget,
2310 struct mtk_poll_state *state)
2311 {
2312 struct mtk_tx_ring *ring = ð->tx_ring;
2313 struct mtk_tx_buf *tx_buf;
2314 struct xdp_frame_bulk bq;
2315 struct mtk_tx_dma *desc;
2316 u32 cpu, dma;
2317
2318 cpu = ring->cpu_idx;
2319 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0);
2320 xdp_frame_bulk_init(&bq);
2321
2322 while ((cpu != dma) && budget) {
2323 tx_buf = &ring->buf[cpu];
2324 if (!tx_buf->data)
2325 break;
2326
2327 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
2328 if (tx_buf->type == MTK_TYPE_SKB)
2329 mtk_poll_tx_done(eth, state, 0, tx_buf->data);
2330 budget--;
2331 }
2332 mtk_tx_unmap(eth, tx_buf, &bq, true);
2333
2334 desc = ring->dma + cpu * eth->soc->txrx.txd_size;
2335 ring->last_free = desc;
2336 atomic_inc(&ring->free_count);
2337
2338 cpu = NEXT_DESP_IDX(cpu, ring->dma_size);
2339 }
2340 xdp_flush_frame_bulk(&bq);
2341
2342 ring->cpu_idx = cpu;
2343
2344 return budget;
2345 }
2346
mtk_poll_tx(struct mtk_eth * eth,int budget)2347 static int mtk_poll_tx(struct mtk_eth *eth, int budget)
2348 {
2349 struct mtk_tx_ring *ring = ð->tx_ring;
2350 struct dim_sample dim_sample = {};
2351 struct mtk_poll_state state = {};
2352
2353 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2354 budget = mtk_poll_tx_qdma(eth, budget, &state);
2355 else
2356 budget = mtk_poll_tx_pdma(eth, budget, &state);
2357
2358 if (state.txq)
2359 netdev_tx_completed_queue(state.txq, state.done, state.bytes);
2360
2361 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes,
2362 &dim_sample);
2363 net_dim(ð->tx_dim, dim_sample);
2364
2365 if (mtk_queue_stopped(eth) &&
2366 (atomic_read(&ring->free_count) > ring->thresh))
2367 mtk_wake_queue(eth);
2368
2369 return state.total;
2370 }
2371
mtk_handle_status_irq(struct mtk_eth * eth)2372 static void mtk_handle_status_irq(struct mtk_eth *eth)
2373 {
2374 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
2375
2376 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
2377 mtk_stats_update(eth);
2378 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
2379 MTK_INT_STATUS2);
2380 }
2381 }
2382
mtk_napi_tx(struct napi_struct * napi,int budget)2383 static int mtk_napi_tx(struct napi_struct *napi, int budget)
2384 {
2385 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
2386 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2387 int tx_done = 0;
2388
2389 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2390 mtk_handle_status_irq(eth);
2391 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status);
2392 tx_done = mtk_poll_tx(eth, budget);
2393
2394 if (unlikely(netif_msg_intr(eth))) {
2395 dev_info(eth->dev,
2396 "done tx %d, intr 0x%08x/0x%x\n", tx_done,
2397 mtk_r32(eth, reg_map->tx_irq_status),
2398 mtk_r32(eth, reg_map->tx_irq_mask));
2399 }
2400
2401 if (tx_done == budget)
2402 return budget;
2403
2404 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT)
2405 return budget;
2406
2407 if (napi_complete_done(napi, tx_done))
2408 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
2409
2410 return tx_done;
2411 }
2412
mtk_napi_rx(struct napi_struct * napi,int budget)2413 static int mtk_napi_rx(struct napi_struct *napi, int budget)
2414 {
2415 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
2416 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2417 int rx_done_total = 0;
2418
2419 mtk_handle_status_irq(eth);
2420
2421 do {
2422 int rx_done;
2423
2424 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask,
2425 reg_map->pdma.irq_status);
2426 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth);
2427 rx_done_total += rx_done;
2428
2429 if (unlikely(netif_msg_intr(eth))) {
2430 dev_info(eth->dev,
2431 "done rx %d, intr 0x%08x/0x%x\n", rx_done,
2432 mtk_r32(eth, reg_map->pdma.irq_status),
2433 mtk_r32(eth, reg_map->pdma.irq_mask));
2434 }
2435
2436 if (rx_done_total == budget)
2437 return budget;
2438
2439 } while (mtk_r32(eth, reg_map->pdma.irq_status) &
2440 eth->soc->txrx.rx_irq_done_mask);
2441
2442 if (napi_complete_done(napi, rx_done_total))
2443 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
2444
2445 return rx_done_total;
2446 }
2447
mtk_tx_alloc(struct mtk_eth * eth)2448 static int mtk_tx_alloc(struct mtk_eth *eth)
2449 {
2450 const struct mtk_soc_data *soc = eth->soc;
2451 struct mtk_tx_ring *ring = ð->tx_ring;
2452 int i, sz = soc->txrx.txd_size;
2453 struct mtk_tx_dma_v2 *txd;
2454 int ring_size;
2455 u32 ofs, val;
2456
2457 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA))
2458 ring_size = MTK_QDMA_RING_SIZE;
2459 else
2460 ring_size = MTK_DMA_SIZE;
2461
2462 ring->buf = kcalloc(ring_size, sizeof(*ring->buf),
2463 GFP_KERNEL);
2464 if (!ring->buf)
2465 goto no_tx_mem;
2466
2467 if (MTK_HAS_CAPS(soc->caps, MTK_SRAM)) {
2468 ring->dma = eth->sram_base + ring_size * sz;
2469 ring->phys = eth->phy_scratch_ring + ring_size * (dma_addr_t)sz;
2470 } else {
2471 ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz,
2472 &ring->phys, GFP_KERNEL);
2473 }
2474
2475 if (!ring->dma)
2476 goto no_tx_mem;
2477
2478 for (i = 0; i < ring_size; i++) {
2479 int next = (i + 1) % ring_size;
2480 u32 next_ptr = ring->phys + next * sz;
2481
2482 txd = ring->dma + i * sz;
2483 txd->txd2 = next_ptr;
2484 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
2485 txd->txd4 = 0;
2486 if (mtk_is_netsys_v2_or_greater(eth)) {
2487 txd->txd5 = 0;
2488 txd->txd6 = 0;
2489 txd->txd7 = 0;
2490 txd->txd8 = 0;
2491 }
2492 }
2493
2494 /* On MT7688 (PDMA only) this driver uses the ring->dma structs
2495 * only as the framework. The real HW descriptors are the PDMA
2496 * descriptors in ring->dma_pdma.
2497 */
2498 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
2499 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, ring_size * sz,
2500 &ring->phys_pdma, GFP_KERNEL);
2501 if (!ring->dma_pdma)
2502 goto no_tx_mem;
2503
2504 for (i = 0; i < ring_size; i++) {
2505 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF;
2506 ring->dma_pdma[i].txd4 = 0;
2507 }
2508 }
2509
2510 ring->dma_size = ring_size;
2511 atomic_set(&ring->free_count, ring_size - 2);
2512 ring->next_free = ring->dma;
2513 ring->last_free = (void *)txd;
2514 ring->last_free_ptr = (u32)(ring->phys + ((ring_size - 1) * sz));
2515 ring->thresh = MAX_SKB_FRAGS;
2516
2517 /* make sure that all changes to the dma ring are flushed before we
2518 * continue
2519 */
2520 wmb();
2521
2522 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
2523 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr);
2524 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr);
2525 mtk_w32(eth,
2526 ring->phys + ((ring_size - 1) * sz),
2527 soc->reg_map->qdma.crx_ptr);
2528 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr);
2529
2530 for (i = 0, ofs = 0; i < MTK_QDMA_NUM_QUEUES; i++) {
2531 val = (QDMA_RES_THRES << 8) | QDMA_RES_THRES;
2532 mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs);
2533
2534 val = MTK_QTX_SCH_MIN_RATE_EN |
2535 /* minimum: 10 Mbps */
2536 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
2537 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
2538 MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
2539 if (mtk_is_netsys_v1(eth))
2540 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
2541 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
2542 ofs += MTK_QTX_OFFSET;
2543 }
2544 val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16);
2545 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate);
2546 if (mtk_is_netsys_v2_or_greater(eth))
2547 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4);
2548 } else {
2549 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
2550 mtk_w32(eth, ring_size, MT7628_TX_MAX_CNT0);
2551 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0);
2552 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx);
2553 }
2554
2555 return 0;
2556
2557 no_tx_mem:
2558 return -ENOMEM;
2559 }
2560
mtk_tx_clean(struct mtk_eth * eth)2561 static void mtk_tx_clean(struct mtk_eth *eth)
2562 {
2563 const struct mtk_soc_data *soc = eth->soc;
2564 struct mtk_tx_ring *ring = ð->tx_ring;
2565 int i;
2566
2567 if (ring->buf) {
2568 for (i = 0; i < ring->dma_size; i++)
2569 mtk_tx_unmap(eth, &ring->buf[i], NULL, false);
2570 kfree(ring->buf);
2571 ring->buf = NULL;
2572 }
2573 if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) {
2574 dma_free_coherent(eth->dma_dev,
2575 ring->dma_size * soc->txrx.txd_size,
2576 ring->dma, ring->phys);
2577 ring->dma = NULL;
2578 }
2579
2580 if (ring->dma_pdma) {
2581 dma_free_coherent(eth->dma_dev,
2582 ring->dma_size * soc->txrx.txd_size,
2583 ring->dma_pdma, ring->phys_pdma);
2584 ring->dma_pdma = NULL;
2585 }
2586 }
2587
mtk_rx_alloc(struct mtk_eth * eth,int ring_no,int rx_flag)2588 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
2589 {
2590 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2591 struct mtk_rx_ring *ring;
2592 int rx_data_len, rx_dma_size, tx_ring_size;
2593 int i;
2594
2595 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2596 tx_ring_size = MTK_QDMA_RING_SIZE;
2597 else
2598 tx_ring_size = MTK_DMA_SIZE;
2599
2600 if (rx_flag == MTK_RX_FLAGS_QDMA) {
2601 if (ring_no)
2602 return -EINVAL;
2603 ring = ð->rx_ring_qdma;
2604 } else {
2605 ring = ð->rx_ring[ring_no];
2606 }
2607
2608 if (rx_flag == MTK_RX_FLAGS_HWLRO) {
2609 rx_data_len = MTK_MAX_LRO_RX_LENGTH;
2610 rx_dma_size = MTK_HW_LRO_DMA_SIZE;
2611 } else {
2612 rx_data_len = ETH_DATA_LEN;
2613 rx_dma_size = MTK_DMA_SIZE;
2614 }
2615
2616 ring->frag_size = mtk_max_frag_size(rx_data_len);
2617 ring->buf_size = mtk_max_buf_size(ring->frag_size);
2618 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data),
2619 GFP_KERNEL);
2620 if (!ring->data)
2621 return -ENOMEM;
2622
2623 if (mtk_page_pool_enabled(eth)) {
2624 struct page_pool *pp;
2625
2626 pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no,
2627 rx_dma_size);
2628 if (IS_ERR(pp))
2629 return PTR_ERR(pp);
2630
2631 ring->page_pool = pp;
2632 }
2633
2634 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) ||
2635 rx_flag != MTK_RX_FLAGS_NORMAL) {
2636 ring->dma = dma_alloc_coherent(eth->dma_dev,
2637 rx_dma_size * eth->soc->txrx.rxd_size,
2638 &ring->phys, GFP_KERNEL);
2639 } else {
2640 struct mtk_tx_ring *tx_ring = ð->tx_ring;
2641
2642 ring->dma = tx_ring->dma + tx_ring_size *
2643 eth->soc->txrx.txd_size * (ring_no + 1);
2644 ring->phys = tx_ring->phys + tx_ring_size *
2645 eth->soc->txrx.txd_size * (ring_no + 1);
2646 }
2647
2648 if (!ring->dma)
2649 return -ENOMEM;
2650
2651 for (i = 0; i < rx_dma_size; i++) {
2652 struct mtk_rx_dma_v2 *rxd;
2653 dma_addr_t dma_addr;
2654 void *data;
2655
2656 rxd = ring->dma + i * eth->soc->txrx.rxd_size;
2657 if (ring->page_pool) {
2658 data = mtk_page_pool_get_buff(ring->page_pool,
2659 &dma_addr, GFP_KERNEL);
2660 if (!data)
2661 return -ENOMEM;
2662 } else {
2663 if (ring->frag_size <= PAGE_SIZE)
2664 data = netdev_alloc_frag(ring->frag_size);
2665 else
2666 data = mtk_max_lro_buf_alloc(GFP_KERNEL);
2667
2668 if (!data)
2669 return -ENOMEM;
2670
2671 dma_addr = dma_map_single(eth->dma_dev,
2672 data + NET_SKB_PAD + eth->ip_align,
2673 ring->buf_size, DMA_FROM_DEVICE);
2674 if (unlikely(dma_mapping_error(eth->dma_dev,
2675 dma_addr))) {
2676 skb_free_frag(data);
2677 return -ENOMEM;
2678 }
2679 }
2680 rxd->rxd1 = (unsigned int)dma_addr;
2681 ring->data[i] = data;
2682
2683 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
2684 rxd->rxd2 = RX_DMA_LSO;
2685 else
2686 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
2687
2688 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
2689 rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr);
2690
2691 rxd->rxd3 = 0;
2692 rxd->rxd4 = 0;
2693 if (mtk_is_netsys_v2_or_greater(eth)) {
2694 rxd->rxd5 = 0;
2695 rxd->rxd6 = 0;
2696 rxd->rxd7 = 0;
2697 rxd->rxd8 = 0;
2698 }
2699 }
2700
2701 ring->dma_size = rx_dma_size;
2702 ring->calc_idx_update = false;
2703 ring->calc_idx = rx_dma_size - 1;
2704 if (rx_flag == MTK_RX_FLAGS_QDMA)
2705 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr +
2706 ring_no * MTK_QRX_OFFSET;
2707 else
2708 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr +
2709 ring_no * MTK_QRX_OFFSET;
2710 /* make sure that all changes to the dma ring are flushed before we
2711 * continue
2712 */
2713 wmb();
2714
2715 if (rx_flag == MTK_RX_FLAGS_QDMA) {
2716 mtk_w32(eth, ring->phys,
2717 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET);
2718 mtk_w32(eth, rx_dma_size,
2719 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET);
2720 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no),
2721 reg_map->qdma.rst_idx);
2722 } else {
2723 mtk_w32(eth, ring->phys,
2724 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET);
2725 mtk_w32(eth, rx_dma_size,
2726 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET);
2727 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no),
2728 reg_map->pdma.rst_idx);
2729 }
2730 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
2731
2732 return 0;
2733 }
2734
mtk_rx_clean(struct mtk_eth * eth,struct mtk_rx_ring * ring,bool in_sram)2735 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram)
2736 {
2737 u64 addr64 = 0;
2738 int i;
2739
2740 if (ring->data && ring->dma) {
2741 for (i = 0; i < ring->dma_size; i++) {
2742 struct mtk_rx_dma *rxd;
2743
2744 if (!ring->data[i])
2745 continue;
2746
2747 rxd = ring->dma + i * eth->soc->txrx.rxd_size;
2748 if (!rxd->rxd1)
2749 continue;
2750
2751 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
2752 addr64 = RX_DMA_GET_ADDR64(rxd->rxd2);
2753
2754 dma_unmap_single(eth->dma_dev, ((u64)rxd->rxd1 | addr64),
2755 ring->buf_size, DMA_FROM_DEVICE);
2756 mtk_rx_put_buff(ring, ring->data[i], false);
2757 }
2758 kfree(ring->data);
2759 ring->data = NULL;
2760 }
2761
2762 if (!in_sram && ring->dma) {
2763 dma_free_coherent(eth->dma_dev,
2764 ring->dma_size * eth->soc->txrx.rxd_size,
2765 ring->dma, ring->phys);
2766 ring->dma = NULL;
2767 }
2768
2769 if (ring->page_pool) {
2770 if (xdp_rxq_info_is_reg(&ring->xdp_q))
2771 xdp_rxq_info_unreg(&ring->xdp_q);
2772 page_pool_destroy(ring->page_pool);
2773 ring->page_pool = NULL;
2774 }
2775 }
2776
mtk_hwlro_rx_init(struct mtk_eth * eth)2777 static int mtk_hwlro_rx_init(struct mtk_eth *eth)
2778 {
2779 int i;
2780 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
2781 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;
2782
2783 /* set LRO rings to auto-learn modes */
2784 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE;
2785
2786 /* validate LRO ring */
2787 ring_ctrl_dw2 |= MTK_RING_VLD;
2788
2789 /* set AGE timer (unit: 20us) */
2790 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H;
2791 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L;
2792
2793 /* set max AGG timer (unit: 20us) */
2794 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME;
2795
2796 /* set max LRO AGG count */
2797 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
2798 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H;
2799
2800 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
2801 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
2802 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
2803 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
2804 }
2805
2806 /* IPv4 checksum update enable */
2807 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN;
2808
2809 /* switch priority comparison to packet count mode */
2810 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE;
2811
2812 /* bandwidth threshold setting */
2813 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
2814
2815 /* auto-learn score delta setting */
2816 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
2817
2818 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */
2819 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
2820 MTK_PDMA_LRO_ALT_REFRESH_TIMER);
2821
2822 /* set HW LRO mode & the max aggregation count for rx packets */
2823 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
2824
2825 /* the minimal remaining room of SDL0 in RXD for lro aggregation */
2826 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
2827
2828 /* enable HW LRO */
2829 lro_ctrl_dw0 |= MTK_LRO_EN;
2830
2831 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
2832 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
2833
2834 return 0;
2835 }
2836
mtk_hwlro_rx_uninit(struct mtk_eth * eth)2837 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth)
2838 {
2839 int i;
2840 u32 val;
2841
2842 /* relinquish lro rings, flush aggregated packets */
2843 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
2844
2845 /* wait for relinquishments done */
2846 for (i = 0; i < 10; i++) {
2847 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
2848 if (val & MTK_LRO_RING_RELINQUISH_DONE) {
2849 msleep(20);
2850 continue;
2851 }
2852 break;
2853 }
2854
2855 /* invalidate lro rings */
2856 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
2857 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
2858
2859 /* disable HW LRO */
2860 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
2861 }
2862
mtk_hwlro_val_ipaddr(struct mtk_eth * eth,int idx,__be32 ip)2863 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip)
2864 {
2865 u32 reg_val;
2866
2867 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
2868
2869 /* invalidate the IP setting */
2870 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
2871
2872 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
2873
2874 /* validate the IP setting */
2875 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
2876 }
2877
mtk_hwlro_inval_ipaddr(struct mtk_eth * eth,int idx)2878 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx)
2879 {
2880 u32 reg_val;
2881
2882 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
2883
2884 /* invalidate the IP setting */
2885 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
2886
2887 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
2888 }
2889
mtk_hwlro_get_ip_cnt(struct mtk_mac * mac)2890 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac)
2891 {
2892 int cnt = 0;
2893 int i;
2894
2895 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
2896 if (mac->hwlro_ip[i])
2897 cnt++;
2898 }
2899
2900 return cnt;
2901 }
2902
mtk_hwlro_add_ipaddr(struct net_device * dev,struct ethtool_rxnfc * cmd)2903 static int mtk_hwlro_add_ipaddr(struct net_device *dev,
2904 struct ethtool_rxnfc *cmd)
2905 {
2906 struct ethtool_rx_flow_spec *fsp =
2907 (struct ethtool_rx_flow_spec *)&cmd->fs;
2908 struct mtk_mac *mac = netdev_priv(dev);
2909 struct mtk_eth *eth = mac->hw;
2910 int hwlro_idx;
2911
2912 if ((fsp->flow_type != TCP_V4_FLOW) ||
2913 (!fsp->h_u.tcp_ip4_spec.ip4dst) ||
2914 (fsp->location > 1))
2915 return -EINVAL;
2916
2917 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
2918 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
2919
2920 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
2921
2922 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]);
2923
2924 return 0;
2925 }
2926
mtk_hwlro_del_ipaddr(struct net_device * dev,struct ethtool_rxnfc * cmd)2927 static int mtk_hwlro_del_ipaddr(struct net_device *dev,
2928 struct ethtool_rxnfc *cmd)
2929 {
2930 struct ethtool_rx_flow_spec *fsp =
2931 (struct ethtool_rx_flow_spec *)&cmd->fs;
2932 struct mtk_mac *mac = netdev_priv(dev);
2933 struct mtk_eth *eth = mac->hw;
2934 int hwlro_idx;
2935
2936 if (fsp->location > 1)
2937 return -EINVAL;
2938
2939 mac->hwlro_ip[fsp->location] = 0;
2940 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
2941
2942 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
2943
2944 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
2945
2946 return 0;
2947 }
2948
mtk_hwlro_netdev_disable(struct net_device * dev)2949 static void mtk_hwlro_netdev_disable(struct net_device *dev)
2950 {
2951 struct mtk_mac *mac = netdev_priv(dev);
2952 struct mtk_eth *eth = mac->hw;
2953 int i, hwlro_idx;
2954
2955 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
2956 mac->hwlro_ip[i] = 0;
2957 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i;
2958
2959 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
2960 }
2961
2962 mac->hwlro_ip_cnt = 0;
2963 }
2964
mtk_hwlro_get_fdir_entry(struct net_device * dev,struct ethtool_rxnfc * cmd)2965 static int mtk_hwlro_get_fdir_entry(struct net_device *dev,
2966 struct ethtool_rxnfc *cmd)
2967 {
2968 struct mtk_mac *mac = netdev_priv(dev);
2969 struct ethtool_rx_flow_spec *fsp =
2970 (struct ethtool_rx_flow_spec *)&cmd->fs;
2971
2972 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip))
2973 return -EINVAL;
2974
2975 /* only tcp dst ipv4 is meaningful, others are meaningless */
2976 fsp->flow_type = TCP_V4_FLOW;
2977 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]);
2978 fsp->m_u.tcp_ip4_spec.ip4dst = 0;
2979
2980 fsp->h_u.tcp_ip4_spec.ip4src = 0;
2981 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff;
2982 fsp->h_u.tcp_ip4_spec.psrc = 0;
2983 fsp->m_u.tcp_ip4_spec.psrc = 0xffff;
2984 fsp->h_u.tcp_ip4_spec.pdst = 0;
2985 fsp->m_u.tcp_ip4_spec.pdst = 0xffff;
2986 fsp->h_u.tcp_ip4_spec.tos = 0;
2987 fsp->m_u.tcp_ip4_spec.tos = 0xff;
2988
2989 return 0;
2990 }
2991
mtk_hwlro_get_fdir_all(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)2992 static int mtk_hwlro_get_fdir_all(struct net_device *dev,
2993 struct ethtool_rxnfc *cmd,
2994 u32 *rule_locs)
2995 {
2996 struct mtk_mac *mac = netdev_priv(dev);
2997 int cnt = 0;
2998 int i;
2999
3000 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
3001 if (cnt == cmd->rule_cnt)
3002 return -EMSGSIZE;
3003
3004 if (mac->hwlro_ip[i]) {
3005 rule_locs[cnt] = i;
3006 cnt++;
3007 }
3008 }
3009
3010 cmd->rule_cnt = cnt;
3011
3012 return 0;
3013 }
3014
mtk_fix_features(struct net_device * dev,netdev_features_t features)3015 static netdev_features_t mtk_fix_features(struct net_device *dev,
3016 netdev_features_t features)
3017 {
3018 if (!(features & NETIF_F_LRO)) {
3019 struct mtk_mac *mac = netdev_priv(dev);
3020 int ip_cnt = mtk_hwlro_get_ip_cnt(mac);
3021
3022 if (ip_cnt) {
3023 netdev_info(dev, "RX flow is programmed, LRO should keep on\n");
3024
3025 features |= NETIF_F_LRO;
3026 }
3027 }
3028
3029 return features;
3030 }
3031
mtk_set_features(struct net_device * dev,netdev_features_t features)3032 static int mtk_set_features(struct net_device *dev, netdev_features_t features)
3033 {
3034 netdev_features_t diff = dev->features ^ features;
3035
3036 if ((diff & NETIF_F_LRO) && !(features & NETIF_F_LRO))
3037 mtk_hwlro_netdev_disable(dev);
3038
3039 return 0;
3040 }
3041
3042 /* wait for DMA to finish whatever it is doing before we start using it again */
mtk_dma_busy_wait(struct mtk_eth * eth)3043 static int mtk_dma_busy_wait(struct mtk_eth *eth)
3044 {
3045 unsigned int reg;
3046 int ret;
3047 u32 val;
3048
3049 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
3050 reg = eth->soc->reg_map->qdma.glo_cfg;
3051 else
3052 reg = eth->soc->reg_map->pdma.glo_cfg;
3053
3054 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val,
3055 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)),
3056 5, MTK_DMA_BUSY_TIMEOUT_US);
3057 if (ret)
3058 dev_err(eth->dev, "DMA init timeout\n");
3059
3060 return ret;
3061 }
3062
mtk_dma_init(struct mtk_eth * eth)3063 static int mtk_dma_init(struct mtk_eth *eth)
3064 {
3065 int err;
3066 u32 i;
3067
3068 if (mtk_dma_busy_wait(eth))
3069 return -EBUSY;
3070
3071 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
3072 /* QDMA needs scratch memory for internal reordering of the
3073 * descriptors
3074 */
3075 err = mtk_init_fq_dma(eth);
3076 if (err)
3077 return err;
3078 }
3079
3080 err = mtk_tx_alloc(eth);
3081 if (err)
3082 return err;
3083
3084 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
3085 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA);
3086 if (err)
3087 return err;
3088 }
3089
3090 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
3091 if (err)
3092 return err;
3093
3094 if (eth->hwlro) {
3095 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
3096 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
3097 if (err)
3098 return err;
3099 }
3100 err = mtk_hwlro_rx_init(eth);
3101 if (err)
3102 return err;
3103 }
3104
3105 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
3106 /* Enable random early drop and set drop threshold
3107 * automatically
3108 */
3109 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN |
3110 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th);
3111 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred);
3112 }
3113
3114 return 0;
3115 }
3116
mtk_dma_free(struct mtk_eth * eth)3117 static void mtk_dma_free(struct mtk_eth *eth)
3118 {
3119 const struct mtk_soc_data *soc = eth->soc;
3120 int i, j, txqs = 1;
3121
3122 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
3123 txqs = MTK_QDMA_NUM_QUEUES;
3124
3125 for (i = 0; i < MTK_MAX_DEVS; i++) {
3126 if (!eth->netdev[i])
3127 continue;
3128
3129 for (j = 0; j < txqs; j++)
3130 netdev_tx_reset_subqueue(eth->netdev[i], j);
3131 }
3132
3133 if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) {
3134 dma_free_coherent(eth->dma_dev,
3135 MTK_QDMA_RING_SIZE * soc->txrx.txd_size,
3136 eth->scratch_ring, eth->phy_scratch_ring);
3137 eth->scratch_ring = NULL;
3138 eth->phy_scratch_ring = 0;
3139 }
3140 mtk_tx_clean(eth);
3141 mtk_rx_clean(eth, ð->rx_ring[0], MTK_HAS_CAPS(soc->caps, MTK_SRAM));
3142 mtk_rx_clean(eth, ð->rx_ring_qdma, false);
3143
3144 if (eth->hwlro) {
3145 mtk_hwlro_rx_uninit(eth);
3146 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
3147 mtk_rx_clean(eth, ð->rx_ring[i], false);
3148 }
3149
3150 kfree(eth->scratch_head);
3151 }
3152
mtk_hw_reset_check(struct mtk_eth * eth)3153 static bool mtk_hw_reset_check(struct mtk_eth *eth)
3154 {
3155 u32 val = mtk_r32(eth, MTK_INT_STATUS2);
3156
3157 return (val & MTK_FE_INT_FQ_EMPTY) || (val & MTK_FE_INT_RFIFO_UF) ||
3158 (val & MTK_FE_INT_RFIFO_OV) || (val & MTK_FE_INT_TSO_FAIL) ||
3159 (val & MTK_FE_INT_TSO_ALIGN) || (val & MTK_FE_INT_TSO_ILLEGAL);
3160 }
3161
mtk_tx_timeout(struct net_device * dev,unsigned int txqueue)3162 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue)
3163 {
3164 struct mtk_mac *mac = netdev_priv(dev);
3165 struct mtk_eth *eth = mac->hw;
3166
3167 if (test_bit(MTK_RESETTING, ð->state))
3168 return;
3169
3170 if (!mtk_hw_reset_check(eth))
3171 return;
3172
3173 eth->netdev[mac->id]->stats.tx_errors++;
3174 netif_err(eth, tx_err, dev, "transmit timed out\n");
3175
3176 schedule_work(ð->pending_work);
3177 }
3178
mtk_handle_irq_rx(int irq,void * _eth)3179 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
3180 {
3181 struct mtk_eth *eth = _eth;
3182
3183 eth->rx_events++;
3184 if (likely(napi_schedule_prep(ð->rx_napi))) {
3185 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
3186 __napi_schedule(ð->rx_napi);
3187 }
3188
3189 return IRQ_HANDLED;
3190 }
3191
mtk_handle_irq_tx(int irq,void * _eth)3192 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
3193 {
3194 struct mtk_eth *eth = _eth;
3195
3196 eth->tx_events++;
3197 if (likely(napi_schedule_prep(ð->tx_napi))) {
3198 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
3199 __napi_schedule(ð->tx_napi);
3200 }
3201
3202 return IRQ_HANDLED;
3203 }
3204
mtk_handle_irq(int irq,void * _eth)3205 static irqreturn_t mtk_handle_irq(int irq, void *_eth)
3206 {
3207 struct mtk_eth *eth = _eth;
3208 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3209
3210 if (mtk_r32(eth, reg_map->pdma.irq_mask) &
3211 eth->soc->txrx.rx_irq_done_mask) {
3212 if (mtk_r32(eth, reg_map->pdma.irq_status) &
3213 eth->soc->txrx.rx_irq_done_mask)
3214 mtk_handle_irq_rx(irq, _eth);
3215 }
3216 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) {
3217 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT)
3218 mtk_handle_irq_tx(irq, _eth);
3219 }
3220
3221 return IRQ_HANDLED;
3222 }
3223
3224 #ifdef CONFIG_NET_POLL_CONTROLLER
mtk_poll_controller(struct net_device * dev)3225 static void mtk_poll_controller(struct net_device *dev)
3226 {
3227 struct mtk_mac *mac = netdev_priv(dev);
3228 struct mtk_eth *eth = mac->hw;
3229
3230 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
3231 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
3232 mtk_handle_irq_rx(eth->irq[2], dev);
3233 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
3234 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
3235 }
3236 #endif
3237
mtk_start_dma(struct mtk_eth * eth)3238 static int mtk_start_dma(struct mtk_eth *eth)
3239 {
3240 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0;
3241 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3242 int err;
3243
3244 err = mtk_dma_init(eth);
3245 if (err) {
3246 mtk_dma_free(eth);
3247 return err;
3248 }
3249
3250 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
3251 val = mtk_r32(eth, reg_map->qdma.glo_cfg);
3252 val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN |
3253 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
3254 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE;
3255
3256 if (mtk_is_netsys_v2_or_greater(eth))
3257 val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
3258 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
3259 MTK_CHK_DDONE_EN;
3260 else
3261 val |= MTK_RX_BT_32DWORDS;
3262 mtk_w32(eth, val, reg_map->qdma.glo_cfg);
3263
3264 mtk_w32(eth,
3265 MTK_RX_DMA_EN | rx_2b_offset |
3266 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
3267 reg_map->pdma.glo_cfg);
3268 } else {
3269 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN |
3270 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS,
3271 reg_map->pdma.glo_cfg);
3272 }
3273
3274 return 0;
3275 }
3276
mtk_gdm_config(struct mtk_eth * eth,u32 config)3277 static void mtk_gdm_config(struct mtk_eth *eth, u32 config)
3278 {
3279 int i;
3280
3281 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
3282 return;
3283
3284 for (i = 0; i < MTK_MAX_DEVS; i++) {
3285 u32 val;
3286
3287 if (!eth->netdev[i])
3288 continue;
3289
3290 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
3291
3292 /* default setup the forward port to send frame to PDMA */
3293 val &= ~0xffff;
3294
3295 /* Enable RX checksum */
3296 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
3297
3298 val |= config;
3299
3300 if (netdev_uses_dsa(eth->netdev[i]))
3301 val |= MTK_GDMA_SPECIAL_TAG;
3302
3303 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
3304 }
3305 /* Reset and enable PSE */
3306 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
3307 mtk_w32(eth, 0, MTK_RST_GL);
3308 }
3309
3310
mtk_uses_dsa(struct net_device * dev)3311 static bool mtk_uses_dsa(struct net_device *dev)
3312 {
3313 #if IS_ENABLED(CONFIG_NET_DSA)
3314 return netdev_uses_dsa(dev) &&
3315 dev->dsa_ptr->tag_ops->proto == DSA_TAG_PROTO_MTK;
3316 #else
3317 return false;
3318 #endif
3319 }
3320
mtk_device_event(struct notifier_block * n,unsigned long event,void * ptr)3321 static int mtk_device_event(struct notifier_block *n, unsigned long event, void *ptr)
3322 {
3323 struct mtk_mac *mac = container_of(n, struct mtk_mac, device_notifier);
3324 struct mtk_eth *eth = mac->hw;
3325 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
3326 struct ethtool_link_ksettings s;
3327 struct net_device *ldev;
3328 struct list_head *iter;
3329 struct dsa_port *dp;
3330
3331 if (event != NETDEV_CHANGE)
3332 return NOTIFY_DONE;
3333
3334 netdev_for_each_lower_dev(dev, ldev, iter) {
3335 if (netdev_priv(ldev) == mac)
3336 goto found;
3337 }
3338
3339 return NOTIFY_DONE;
3340
3341 found:
3342 if (!dsa_slave_dev_check(dev))
3343 return NOTIFY_DONE;
3344
3345 if (__ethtool_get_link_ksettings(dev, &s))
3346 return NOTIFY_DONE;
3347
3348 if (s.base.speed == 0 || s.base.speed == ((__u32)-1))
3349 return NOTIFY_DONE;
3350
3351 dp = dsa_port_from_netdev(dev);
3352 if (dp->index >= MTK_QDMA_NUM_QUEUES)
3353 return NOTIFY_DONE;
3354
3355 if (mac->speed > 0 && mac->speed <= s.base.speed)
3356 s.base.speed = 0;
3357
3358 mtk_set_queue_speed(eth, dp->index + 3, s.base.speed);
3359
3360 return NOTIFY_DONE;
3361 }
3362
mtk_open(struct net_device * dev)3363 static int mtk_open(struct net_device *dev)
3364 {
3365 struct mtk_mac *mac = netdev_priv(dev);
3366 struct mtk_eth *eth = mac->hw;
3367 int i, err;
3368
3369 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
3370 if (err) {
3371 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
3372 err);
3373 return err;
3374 }
3375
3376 /* we run 2 netdevs on the same dma ring so we only bring it up once */
3377 if (!refcount_read(ð->dma_refcnt)) {
3378 const struct mtk_soc_data *soc = eth->soc;
3379 u32 gdm_config;
3380 int i;
3381
3382 err = mtk_start_dma(eth);
3383 if (err) {
3384 phylink_disconnect_phy(mac->phylink);
3385 return err;
3386 }
3387
3388 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
3389 mtk_ppe_start(eth->ppe[i]);
3390
3391 gdm_config = soc->offload_version ? soc->reg_map->gdma_to_ppe
3392 : MTK_GDMA_TO_PDMA;
3393 mtk_gdm_config(eth, gdm_config);
3394
3395 napi_enable(ð->tx_napi);
3396 napi_enable(ð->rx_napi);
3397 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
3398 mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask);
3399 refcount_set(ð->dma_refcnt, 1);
3400 }
3401 else
3402 refcount_inc(ð->dma_refcnt);
3403
3404 phylink_start(mac->phylink);
3405 netif_tx_start_all_queues(dev);
3406
3407 if (mtk_is_netsys_v2_or_greater(eth))
3408 return 0;
3409
3410 if (mtk_uses_dsa(dev) && !eth->prog) {
3411 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) {
3412 struct metadata_dst *md_dst = eth->dsa_meta[i];
3413
3414 if (md_dst)
3415 continue;
3416
3417 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX,
3418 GFP_KERNEL);
3419 if (!md_dst)
3420 return -ENOMEM;
3421
3422 md_dst->u.port_info.port_id = i;
3423 eth->dsa_meta[i] = md_dst;
3424 }
3425 } else {
3426 /* Hardware DSA untagging and VLAN RX offloading need to be
3427 * disabled if at least one MAC does not use DSA.
3428 */
3429 u32 val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
3430
3431 val &= ~MTK_CDMP_STAG_EN;
3432 mtk_w32(eth, val, MTK_CDMP_IG_CTRL);
3433
3434 mtk_w32(eth, 0, MTK_CDMP_EG_CTRL);
3435 }
3436
3437 return 0;
3438 }
3439
mtk_stop_dma(struct mtk_eth * eth,u32 glo_cfg)3440 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
3441 {
3442 u32 val;
3443 int i;
3444
3445 /* stop the dma engine */
3446 spin_lock_bh(ð->page_lock);
3447 val = mtk_r32(eth, glo_cfg);
3448 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
3449 glo_cfg);
3450 spin_unlock_bh(ð->page_lock);
3451
3452 /* wait for dma stop */
3453 for (i = 0; i < 10; i++) {
3454 val = mtk_r32(eth, glo_cfg);
3455 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
3456 msleep(20);
3457 continue;
3458 }
3459 break;
3460 }
3461 }
3462
mtk_stop(struct net_device * dev)3463 static int mtk_stop(struct net_device *dev)
3464 {
3465 struct mtk_mac *mac = netdev_priv(dev);
3466 struct mtk_eth *eth = mac->hw;
3467 int i;
3468
3469 phylink_stop(mac->phylink);
3470
3471 netif_tx_disable(dev);
3472
3473 phylink_disconnect_phy(mac->phylink);
3474
3475 /* only shutdown DMA if this is the last user */
3476 if (!refcount_dec_and_test(ð->dma_refcnt))
3477 return 0;
3478
3479 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
3480
3481 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
3482 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
3483 napi_disable(ð->tx_napi);
3484 napi_disable(ð->rx_napi);
3485
3486 cancel_work_sync(ð->rx_dim.work);
3487 cancel_work_sync(ð->tx_dim.work);
3488
3489 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
3490 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg);
3491 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg);
3492
3493 mtk_dma_free(eth);
3494
3495 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
3496 mtk_ppe_stop(eth->ppe[i]);
3497
3498 return 0;
3499 }
3500
mtk_xdp_setup(struct net_device * dev,struct bpf_prog * prog,struct netlink_ext_ack * extack)3501 static int mtk_xdp_setup(struct net_device *dev, struct bpf_prog *prog,
3502 struct netlink_ext_ack *extack)
3503 {
3504 struct mtk_mac *mac = netdev_priv(dev);
3505 struct mtk_eth *eth = mac->hw;
3506 struct bpf_prog *old_prog;
3507 bool need_update;
3508
3509 if (eth->hwlro) {
3510 NL_SET_ERR_MSG_MOD(extack, "XDP not supported with HWLRO");
3511 return -EOPNOTSUPP;
3512 }
3513
3514 if (dev->mtu > MTK_PP_MAX_BUF_SIZE) {
3515 NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP");
3516 return -EOPNOTSUPP;
3517 }
3518
3519 need_update = !!eth->prog != !!prog;
3520 if (netif_running(dev) && need_update)
3521 mtk_stop(dev);
3522
3523 old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held());
3524 if (old_prog)
3525 bpf_prog_put(old_prog);
3526
3527 if (netif_running(dev) && need_update)
3528 return mtk_open(dev);
3529
3530 return 0;
3531 }
3532
mtk_xdp(struct net_device * dev,struct netdev_bpf * xdp)3533 static int mtk_xdp(struct net_device *dev, struct netdev_bpf *xdp)
3534 {
3535 switch (xdp->command) {
3536 case XDP_SETUP_PROG:
3537 return mtk_xdp_setup(dev, xdp->prog, xdp->extack);
3538 default:
3539 return -EINVAL;
3540 }
3541 }
3542
ethsys_reset(struct mtk_eth * eth,u32 reset_bits)3543 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
3544 {
3545 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
3546 reset_bits,
3547 reset_bits);
3548
3549 usleep_range(1000, 1100);
3550 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
3551 reset_bits,
3552 ~reset_bits);
3553 mdelay(10);
3554 }
3555
mtk_clk_disable(struct mtk_eth * eth)3556 static void mtk_clk_disable(struct mtk_eth *eth)
3557 {
3558 int clk;
3559
3560 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--)
3561 clk_disable_unprepare(eth->clks[clk]);
3562 }
3563
mtk_clk_enable(struct mtk_eth * eth)3564 static int mtk_clk_enable(struct mtk_eth *eth)
3565 {
3566 int clk, ret;
3567
3568 for (clk = 0; clk < MTK_CLK_MAX ; clk++) {
3569 ret = clk_prepare_enable(eth->clks[clk]);
3570 if (ret)
3571 goto err_disable_clks;
3572 }
3573
3574 return 0;
3575
3576 err_disable_clks:
3577 while (--clk >= 0)
3578 clk_disable_unprepare(eth->clks[clk]);
3579
3580 return ret;
3581 }
3582
mtk_dim_rx(struct work_struct * work)3583 static void mtk_dim_rx(struct work_struct *work)
3584 {
3585 struct dim *dim = container_of(work, struct dim, work);
3586 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim);
3587 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3588 struct dim_cq_moder cur_profile;
3589 u32 val, cur;
3590
3591 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode,
3592 dim->profile_ix);
3593 spin_lock_bh(ð->dim_lock);
3594
3595 val = mtk_r32(eth, reg_map->pdma.delay_irq);
3596 val &= MTK_PDMA_DELAY_TX_MASK;
3597 val |= MTK_PDMA_DELAY_RX_EN;
3598
3599 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK);
3600 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT;
3601
3602 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);
3603 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT;
3604
3605 mtk_w32(eth, val, reg_map->pdma.delay_irq);
3606 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
3607 mtk_w32(eth, val, reg_map->qdma.delay_irq);
3608
3609 spin_unlock_bh(ð->dim_lock);
3610
3611 dim->state = DIM_START_MEASURE;
3612 }
3613
mtk_dim_tx(struct work_struct * work)3614 static void mtk_dim_tx(struct work_struct *work)
3615 {
3616 struct dim *dim = container_of(work, struct dim, work);
3617 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim);
3618 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3619 struct dim_cq_moder cur_profile;
3620 u32 val, cur;
3621
3622 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode,
3623 dim->profile_ix);
3624 spin_lock_bh(ð->dim_lock);
3625
3626 val = mtk_r32(eth, reg_map->pdma.delay_irq);
3627 val &= MTK_PDMA_DELAY_RX_MASK;
3628 val |= MTK_PDMA_DELAY_TX_EN;
3629
3630 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK);
3631 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT;
3632
3633 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);
3634 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT;
3635
3636 mtk_w32(eth, val, reg_map->pdma.delay_irq);
3637 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
3638 mtk_w32(eth, val, reg_map->qdma.delay_irq);
3639
3640 spin_unlock_bh(ð->dim_lock);
3641
3642 dim->state = DIM_START_MEASURE;
3643 }
3644
mtk_set_mcr_max_rx(struct mtk_mac * mac,u32 val)3645 static void mtk_set_mcr_max_rx(struct mtk_mac *mac, u32 val)
3646 {
3647 struct mtk_eth *eth = mac->hw;
3648 u32 mcr_cur, mcr_new;
3649
3650 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
3651 return;
3652
3653 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
3654 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK;
3655
3656 if (val <= 1518)
3657 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518);
3658 else if (val <= 1536)
3659 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536);
3660 else if (val <= 1552)
3661 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552);
3662 else
3663 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048);
3664
3665 if (mcr_new != mcr_cur)
3666 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
3667 }
3668
mtk_hw_reset(struct mtk_eth * eth)3669 static void mtk_hw_reset(struct mtk_eth *eth)
3670 {
3671 u32 val;
3672
3673 if (mtk_is_netsys_v2_or_greater(eth))
3674 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
3675
3676 if (mtk_is_netsys_v3_or_greater(eth)) {
3677 val = RSTCTRL_PPE0_V3;
3678
3679 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
3680 val |= RSTCTRL_PPE1_V3;
3681
3682 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
3683 val |= RSTCTRL_PPE2;
3684
3685 val |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2;
3686 } else if (mtk_is_netsys_v2_or_greater(eth)) {
3687 val = RSTCTRL_PPE0_V2;
3688
3689 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
3690 val |= RSTCTRL_PPE1;
3691 } else {
3692 val = RSTCTRL_PPE0;
3693 }
3694
3695 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
3696
3697 if (mtk_is_netsys_v3_or_greater(eth))
3698 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
3699 0x6f8ff);
3700 else if (mtk_is_netsys_v2_or_greater(eth))
3701 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
3702 0x3ffffff);
3703 }
3704
mtk_hw_reset_read(struct mtk_eth * eth)3705 static u32 mtk_hw_reset_read(struct mtk_eth *eth)
3706 {
3707 u32 val;
3708
3709 regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val);
3710 return val;
3711 }
3712
mtk_hw_warm_reset(struct mtk_eth * eth)3713 static void mtk_hw_warm_reset(struct mtk_eth *eth)
3714 {
3715 u32 rst_mask, val;
3716
3717 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, RSTCTRL_FE,
3718 RSTCTRL_FE);
3719 if (readx_poll_timeout_atomic(mtk_hw_reset_read, eth, val,
3720 val & RSTCTRL_FE, 1, 1000)) {
3721 dev_err(eth->dev, "warm reset failed\n");
3722 mtk_hw_reset(eth);
3723 return;
3724 }
3725
3726 if (mtk_is_netsys_v3_or_greater(eth)) {
3727 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V3;
3728 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
3729 rst_mask |= RSTCTRL_PPE1_V3;
3730 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
3731 rst_mask |= RSTCTRL_PPE2;
3732
3733 rst_mask |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2;
3734 } else if (mtk_is_netsys_v2_or_greater(eth)) {
3735 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2;
3736 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
3737 rst_mask |= RSTCTRL_PPE1;
3738 } else {
3739 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0;
3740 }
3741
3742 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask);
3743
3744 udelay(1);
3745 val = mtk_hw_reset_read(eth);
3746 if (!(val & rst_mask))
3747 dev_err(eth->dev, "warm reset stage0 failed %08x (%08x)\n",
3748 val, rst_mask);
3749
3750 rst_mask |= RSTCTRL_FE;
3751 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, ~rst_mask);
3752
3753 udelay(1);
3754 val = mtk_hw_reset_read(eth);
3755 if (val & rst_mask)
3756 dev_err(eth->dev, "warm reset stage1 failed %08x (%08x)\n",
3757 val, rst_mask);
3758 }
3759
mtk_hw_check_dma_hang(struct mtk_eth * eth)3760 static bool mtk_hw_check_dma_hang(struct mtk_eth *eth)
3761 {
3762 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3763 bool gmac1_tx, gmac2_tx, gdm1_tx, gdm2_tx;
3764 bool oq_hang, cdm1_busy, adma_busy;
3765 bool wtx_busy, cdm_full, oq_free;
3766 u32 wdidx, val, gdm1_fc, gdm2_fc;
3767 bool qfsm_hang, qfwd_hang;
3768 bool ret = false;
3769
3770 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
3771 return false;
3772
3773 /* WDMA sanity checks */
3774 wdidx = mtk_r32(eth, reg_map->wdma_base[0] + 0xc);
3775
3776 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x204);
3777 wtx_busy = FIELD_GET(MTK_TX_DMA_BUSY, val);
3778
3779 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x230);
3780 cdm_full = !FIELD_GET(MTK_CDM_TXFIFO_RDY, val);
3781
3782 oq_free = (!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(24, 16)) &&
3783 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) &&
3784 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16)));
3785
3786 if (wdidx == eth->reset.wdidx && wtx_busy && cdm_full && oq_free) {
3787 if (++eth->reset.wdma_hang_count > 2) {
3788 eth->reset.wdma_hang_count = 0;
3789 ret = true;
3790 }
3791 goto out;
3792 }
3793
3794 /* QDMA sanity checks */
3795 qfsm_hang = !!mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x234);
3796 qfwd_hang = !mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x308);
3797
3798 gdm1_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM1_FSM)) > 0;
3799 gdm2_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM2_FSM)) > 0;
3800 gmac1_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(0))) != 1;
3801 gmac2_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(1))) != 1;
3802 gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24);
3803 gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64);
3804
3805 if (qfsm_hang && qfwd_hang &&
3806 ((gdm1_tx && gmac1_tx && gdm1_fc < 1) ||
3807 (gdm2_tx && gmac2_tx && gdm2_fc < 1))) {
3808 if (++eth->reset.qdma_hang_count > 2) {
3809 eth->reset.qdma_hang_count = 0;
3810 ret = true;
3811 }
3812 goto out;
3813 }
3814
3815 /* ADMA sanity checks */
3816 oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0));
3817 cdm1_busy = !!(mtk_r32(eth, MTK_FE_CDM1_FSM) & GENMASK(31, 16));
3818 adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) &&
3819 !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & BIT(6));
3820
3821 if (oq_hang && cdm1_busy && adma_busy) {
3822 if (++eth->reset.adma_hang_count > 2) {
3823 eth->reset.adma_hang_count = 0;
3824 ret = true;
3825 }
3826 goto out;
3827 }
3828
3829 eth->reset.wdma_hang_count = 0;
3830 eth->reset.qdma_hang_count = 0;
3831 eth->reset.adma_hang_count = 0;
3832 out:
3833 eth->reset.wdidx = wdidx;
3834
3835 return ret;
3836 }
3837
mtk_hw_reset_monitor_work(struct work_struct * work)3838 static void mtk_hw_reset_monitor_work(struct work_struct *work)
3839 {
3840 struct delayed_work *del_work = to_delayed_work(work);
3841 struct mtk_eth *eth = container_of(del_work, struct mtk_eth,
3842 reset.monitor_work);
3843
3844 if (test_bit(MTK_RESETTING, ð->state))
3845 goto out;
3846
3847 /* DMA stuck checks */
3848 if (mtk_hw_check_dma_hang(eth))
3849 schedule_work(ð->pending_work);
3850
3851 out:
3852 schedule_delayed_work(ð->reset.monitor_work,
3853 MTK_DMA_MONITOR_TIMEOUT);
3854 }
3855
mtk_hw_init(struct mtk_eth * eth,bool reset)3856 static int mtk_hw_init(struct mtk_eth *eth, bool reset)
3857 {
3858 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
3859 ETHSYS_DMA_AG_MAP_PPE;
3860 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3861 int i, val, ret;
3862
3863 if (!reset && test_and_set_bit(MTK_HW_INIT, ð->state))
3864 return 0;
3865
3866 if (!reset) {
3867 pm_runtime_enable(eth->dev);
3868 pm_runtime_get_sync(eth->dev);
3869
3870 ret = mtk_clk_enable(eth);
3871 if (ret)
3872 goto err_disable_pm;
3873 }
3874
3875 if (eth->ethsys)
3876 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask,
3877 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask);
3878
3879 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
3880 ret = device_reset(eth->dev);
3881 if (ret) {
3882 dev_err(eth->dev, "MAC reset failed!\n");
3883 goto err_disable_pm;
3884 }
3885
3886 /* set interrupt delays based on current Net DIM sample */
3887 mtk_dim_rx(ð->rx_dim.work);
3888 mtk_dim_tx(ð->tx_dim.work);
3889
3890 /* disable delay and normal interrupt */
3891 mtk_tx_irq_disable(eth, ~0);
3892 mtk_rx_irq_disable(eth, ~0);
3893
3894 return 0;
3895 }
3896
3897 msleep(100);
3898
3899 if (reset)
3900 mtk_hw_warm_reset(eth);
3901 else
3902 mtk_hw_reset(eth);
3903
3904 if (mtk_is_netsys_v2_or_greater(eth)) {
3905 /* Set FE to PDMAv2 if necessary */
3906 val = mtk_r32(eth, MTK_FE_GLO_MISC);
3907 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
3908 }
3909
3910 if (eth->pctl) {
3911 /* Set GE2 driving and slew rate */
3912 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
3913
3914 /* set GE2 TDSEL */
3915 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
3916
3917 /* set GE2 TUNE */
3918 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
3919 }
3920
3921 /* Set linkdown as the default for each GMAC. Its own MCR would be set
3922 * up with the more appropriate value when mtk_mac_config call is being
3923 * invoked.
3924 */
3925 for (i = 0; i < MTK_MAX_DEVS; i++) {
3926 struct net_device *dev = eth->netdev[i];
3927
3928 if (!dev)
3929 continue;
3930
3931 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i));
3932 mtk_set_mcr_max_rx(netdev_priv(dev),
3933 dev->mtu + MTK_RX_ETH_HLEN);
3934 }
3935
3936 /* Indicates CDM to parse the MTK special tag from CPU
3937 * which also is working out for untag packets.
3938 */
3939 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
3940 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
3941 if (mtk_is_netsys_v1(eth)) {
3942 val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
3943 mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
3944
3945 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
3946 }
3947
3948 /* set interrupt delays based on current Net DIM sample */
3949 mtk_dim_rx(ð->rx_dim.work);
3950 mtk_dim_tx(ð->tx_dim.work);
3951
3952 /* disable delay and normal interrupt */
3953 mtk_tx_irq_disable(eth, ~0);
3954 mtk_rx_irq_disable(eth, ~0);
3955
3956 /* FE int grouping */
3957 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp);
3958 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4);
3959 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp);
3960 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
3961 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
3962
3963 if (mtk_is_netsys_v3_or_greater(eth)) {
3964 /* PSE dummy page mechanism */
3965 mtk_w32(eth, PSE_DUMMY_WORK_GDM(1) | PSE_DUMMY_WORK_GDM(2) |
3966 PSE_DUMMY_WORK_GDM(3) | DUMMY_PAGE_THR, PSE_DUMY_REQ);
3967
3968 /* PSE free buffer drop threshold */
3969 mtk_w32(eth, 0x00600009, PSE_IQ_REV(8));
3970
3971 /* PSE should not drop port8, port9 and port13 packets from
3972 * WDMA Tx
3973 */
3974 mtk_w32(eth, 0x00002300, PSE_DROP_CFG);
3975
3976 /* PSE should drop packets to port8, port9 and port13 on WDMA Rx
3977 * ring full
3978 */
3979 mtk_w32(eth, 0x00002300, PSE_PPE_DROP(0));
3980 mtk_w32(eth, 0x00002300, PSE_PPE_DROP(1));
3981 mtk_w32(eth, 0x00002300, PSE_PPE_DROP(2));
3982
3983 /* GDM and CDM Threshold */
3984 mtk_w32(eth, 0x08000707, MTK_CDMW0_THRES);
3985 mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES);
3986
3987 /* Disable GDM1 RX CRC stripping */
3988 mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0));
3989
3990 /* PSE GDM3 MIB counter has incorrect hw default values,
3991 * so the driver ought to read clear the values beforehand
3992 * in case ethtool retrieve wrong mib values.
3993 */
3994 for (i = 0; i < 0x80; i += 0x4)
3995 mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i);
3996 } else if (!mtk_is_netsys_v1(eth)) {
3997 /* PSE should not drop port8 and port9 packets from WDMA Tx */
3998 mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
3999
4000 /* PSE should drop packets to port 8/9 on WDMA Rx ring full */
4001 mtk_w32(eth, 0x00000300, PSE_PPE_DROP(0));
4002
4003 /* PSE Free Queue Flow Control */
4004 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2);
4005
4006 /* PSE config input queue threshold */
4007 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1));
4008 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2));
4009 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3));
4010 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4));
4011 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5));
4012 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6));
4013 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7));
4014 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8));
4015
4016 /* PSE config output queue threshold */
4017 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1));
4018 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2));
4019 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3));
4020 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4));
4021 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5));
4022 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6));
4023 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7));
4024 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8));
4025
4026 /* GDM and CDM Threshold */
4027 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES);
4028 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES);
4029 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES);
4030 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES);
4031 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES);
4032 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES);
4033 }
4034
4035 return 0;
4036
4037 err_disable_pm:
4038 if (!reset) {
4039 pm_runtime_put_sync(eth->dev);
4040 pm_runtime_disable(eth->dev);
4041 }
4042
4043 return ret;
4044 }
4045
mtk_hw_deinit(struct mtk_eth * eth)4046 static int mtk_hw_deinit(struct mtk_eth *eth)
4047 {
4048 if (!test_and_clear_bit(MTK_HW_INIT, ð->state))
4049 return 0;
4050
4051 mtk_clk_disable(eth);
4052
4053 pm_runtime_put_sync(eth->dev);
4054 pm_runtime_disable(eth->dev);
4055
4056 return 0;
4057 }
4058
mtk_uninit(struct net_device * dev)4059 static void mtk_uninit(struct net_device *dev)
4060 {
4061 struct mtk_mac *mac = netdev_priv(dev);
4062 struct mtk_eth *eth = mac->hw;
4063
4064 phylink_disconnect_phy(mac->phylink);
4065 mtk_tx_irq_disable(eth, ~0);
4066 mtk_rx_irq_disable(eth, ~0);
4067 }
4068
mtk_change_mtu(struct net_device * dev,int new_mtu)4069 static int mtk_change_mtu(struct net_device *dev, int new_mtu)
4070 {
4071 int length = new_mtu + MTK_RX_ETH_HLEN;
4072 struct mtk_mac *mac = netdev_priv(dev);
4073 struct mtk_eth *eth = mac->hw;
4074
4075 if (rcu_access_pointer(eth->prog) &&
4076 length > MTK_PP_MAX_BUF_SIZE) {
4077 netdev_err(dev, "Invalid MTU for XDP mode\n");
4078 return -EINVAL;
4079 }
4080
4081 mtk_set_mcr_max_rx(mac, length);
4082 dev->mtu = new_mtu;
4083
4084 return 0;
4085 }
4086
mtk_do_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)4087 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4088 {
4089 struct mtk_mac *mac = netdev_priv(dev);
4090
4091 switch (cmd) {
4092 case SIOCGMIIPHY:
4093 case SIOCGMIIREG:
4094 case SIOCSMIIREG:
4095 return phylink_mii_ioctl(mac->phylink, ifr, cmd);
4096 default:
4097 break;
4098 }
4099
4100 return -EOPNOTSUPP;
4101 }
4102
mtk_prepare_for_reset(struct mtk_eth * eth)4103 static void mtk_prepare_for_reset(struct mtk_eth *eth)
4104 {
4105 u32 val;
4106 int i;
4107
4108 /* set FE PPE ports link down */
4109 for (i = MTK_GMAC1_ID;
4110 i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID);
4111 i += 2) {
4112 val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) | MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT);
4113 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
4114 val |= MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT);
4115 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
4116 val |= MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT);
4117 mtk_w32(eth, val, MTK_FE_GLO_CFG(i));
4118 }
4119
4120 /* adjust PPE configurations to prepare for reset */
4121 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
4122 mtk_ppe_prepare_reset(eth->ppe[i]);
4123
4124 /* disable NETSYS interrupts */
4125 mtk_w32(eth, 0, MTK_FE_INT_ENABLE);
4126
4127 /* force link down GMAC */
4128 for (i = 0; i < 2; i++) {
4129 val = mtk_r32(eth, MTK_MAC_MCR(i)) & ~MAC_MCR_FORCE_LINK;
4130 mtk_w32(eth, val, MTK_MAC_MCR(i));
4131 }
4132 }
4133
mtk_pending_work(struct work_struct * work)4134 static void mtk_pending_work(struct work_struct *work)
4135 {
4136 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
4137 unsigned long restart = 0;
4138 u32 val;
4139 int i;
4140
4141 rtnl_lock();
4142 set_bit(MTK_RESETTING, ð->state);
4143
4144 mtk_prepare_for_reset(eth);
4145 mtk_wed_fe_reset();
4146 /* Run again reset preliminary configuration in order to avoid any
4147 * possible race during FE reset since it can run releasing RTNL lock.
4148 */
4149 mtk_prepare_for_reset(eth);
4150
4151 /* stop all devices to make sure that dma is properly shut down */
4152 for (i = 0; i < MTK_MAX_DEVS; i++) {
4153 if (!eth->netdev[i] || !netif_running(eth->netdev[i]))
4154 continue;
4155
4156 mtk_stop(eth->netdev[i]);
4157 __set_bit(i, &restart);
4158 }
4159
4160 usleep_range(15000, 16000);
4161
4162 if (eth->dev->pins)
4163 pinctrl_select_state(eth->dev->pins->p,
4164 eth->dev->pins->default_state);
4165 mtk_hw_init(eth, true);
4166
4167 /* restart DMA and enable IRQs */
4168 for (i = 0; i < MTK_MAX_DEVS; i++) {
4169 if (!eth->netdev[i] || !test_bit(i, &restart))
4170 continue;
4171
4172 if (mtk_open(eth->netdev[i])) {
4173 netif_alert(eth, ifup, eth->netdev[i],
4174 "Driver up/down cycle failed\n");
4175 dev_close(eth->netdev[i]);
4176 }
4177 }
4178
4179 /* set FE PPE ports link up */
4180 for (i = MTK_GMAC1_ID;
4181 i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID);
4182 i += 2) {
4183 val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) & ~MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT);
4184 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
4185 val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT);
4186 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
4187 val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT);
4188
4189 mtk_w32(eth, val, MTK_FE_GLO_CFG(i));
4190 }
4191
4192 clear_bit(MTK_RESETTING, ð->state);
4193
4194 mtk_wed_fe_reset_complete();
4195
4196 rtnl_unlock();
4197 }
4198
mtk_free_dev(struct mtk_eth * eth)4199 static int mtk_free_dev(struct mtk_eth *eth)
4200 {
4201 int i;
4202
4203 for (i = 0; i < MTK_MAX_DEVS; i++) {
4204 if (!eth->netdev[i])
4205 continue;
4206 free_netdev(eth->netdev[i]);
4207 }
4208
4209 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) {
4210 if (!eth->dsa_meta[i])
4211 break;
4212 metadata_dst_free(eth->dsa_meta[i]);
4213 }
4214
4215 return 0;
4216 }
4217
mtk_unreg_dev(struct mtk_eth * eth)4218 static int mtk_unreg_dev(struct mtk_eth *eth)
4219 {
4220 int i;
4221
4222 for (i = 0; i < MTK_MAX_DEVS; i++) {
4223 struct mtk_mac *mac;
4224 if (!eth->netdev[i])
4225 continue;
4226 mac = netdev_priv(eth->netdev[i]);
4227 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
4228 unregister_netdevice_notifier(&mac->device_notifier);
4229 unregister_netdev(eth->netdev[i]);
4230 }
4231
4232 return 0;
4233 }
4234
mtk_sgmii_destroy(struct mtk_eth * eth)4235 static void mtk_sgmii_destroy(struct mtk_eth *eth)
4236 {
4237 int i;
4238
4239 for (i = 0; i < MTK_MAX_DEVS; i++)
4240 mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]);
4241 }
4242
mtk_cleanup(struct mtk_eth * eth)4243 static int mtk_cleanup(struct mtk_eth *eth)
4244 {
4245 mtk_sgmii_destroy(eth);
4246 mtk_unreg_dev(eth);
4247 mtk_free_dev(eth);
4248 cancel_work_sync(ð->pending_work);
4249 cancel_delayed_work_sync(ð->reset.monitor_work);
4250
4251 return 0;
4252 }
4253
mtk_get_link_ksettings(struct net_device * ndev,struct ethtool_link_ksettings * cmd)4254 static int mtk_get_link_ksettings(struct net_device *ndev,
4255 struct ethtool_link_ksettings *cmd)
4256 {
4257 struct mtk_mac *mac = netdev_priv(ndev);
4258
4259 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
4260 return -EBUSY;
4261
4262 return phylink_ethtool_ksettings_get(mac->phylink, cmd);
4263 }
4264
mtk_set_link_ksettings(struct net_device * ndev,const struct ethtool_link_ksettings * cmd)4265 static int mtk_set_link_ksettings(struct net_device *ndev,
4266 const struct ethtool_link_ksettings *cmd)
4267 {
4268 struct mtk_mac *mac = netdev_priv(ndev);
4269
4270 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
4271 return -EBUSY;
4272
4273 return phylink_ethtool_ksettings_set(mac->phylink, cmd);
4274 }
4275
mtk_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)4276 static void mtk_get_drvinfo(struct net_device *dev,
4277 struct ethtool_drvinfo *info)
4278 {
4279 struct mtk_mac *mac = netdev_priv(dev);
4280
4281 strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
4282 strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
4283 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
4284 }
4285
mtk_get_msglevel(struct net_device * dev)4286 static u32 mtk_get_msglevel(struct net_device *dev)
4287 {
4288 struct mtk_mac *mac = netdev_priv(dev);
4289
4290 return mac->hw->msg_enable;
4291 }
4292
mtk_set_msglevel(struct net_device * dev,u32 value)4293 static void mtk_set_msglevel(struct net_device *dev, u32 value)
4294 {
4295 struct mtk_mac *mac = netdev_priv(dev);
4296
4297 mac->hw->msg_enable = value;
4298 }
4299
mtk_nway_reset(struct net_device * dev)4300 static int mtk_nway_reset(struct net_device *dev)
4301 {
4302 struct mtk_mac *mac = netdev_priv(dev);
4303
4304 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
4305 return -EBUSY;
4306
4307 if (!mac->phylink)
4308 return -ENOTSUPP;
4309
4310 return phylink_ethtool_nway_reset(mac->phylink);
4311 }
4312
mtk_get_strings(struct net_device * dev,u32 stringset,u8 * data)4313 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4314 {
4315 int i;
4316
4317 switch (stringset) {
4318 case ETH_SS_STATS: {
4319 struct mtk_mac *mac = netdev_priv(dev);
4320
4321 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
4322 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
4323 data += ETH_GSTRING_LEN;
4324 }
4325 if (mtk_page_pool_enabled(mac->hw))
4326 page_pool_ethtool_stats_get_strings(data);
4327 break;
4328 }
4329 default:
4330 break;
4331 }
4332 }
4333
mtk_get_sset_count(struct net_device * dev,int sset)4334 static int mtk_get_sset_count(struct net_device *dev, int sset)
4335 {
4336 switch (sset) {
4337 case ETH_SS_STATS: {
4338 int count = ARRAY_SIZE(mtk_ethtool_stats);
4339 struct mtk_mac *mac = netdev_priv(dev);
4340
4341 if (mtk_page_pool_enabled(mac->hw))
4342 count += page_pool_ethtool_stats_get_count();
4343 return count;
4344 }
4345 default:
4346 return -EOPNOTSUPP;
4347 }
4348 }
4349
mtk_ethtool_pp_stats(struct mtk_eth * eth,u64 * data)4350 static void mtk_ethtool_pp_stats(struct mtk_eth *eth, u64 *data)
4351 {
4352 struct page_pool_stats stats = {};
4353 int i;
4354
4355 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) {
4356 struct mtk_rx_ring *ring = ð->rx_ring[i];
4357
4358 if (!ring->page_pool)
4359 continue;
4360
4361 page_pool_get_stats(ring->page_pool, &stats);
4362 }
4363 page_pool_ethtool_stats_get(data, &stats);
4364 }
4365
mtk_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)4366 static void mtk_get_ethtool_stats(struct net_device *dev,
4367 struct ethtool_stats *stats, u64 *data)
4368 {
4369 struct mtk_mac *mac = netdev_priv(dev);
4370 struct mtk_hw_stats *hwstats = mac->hw_stats;
4371 u64 *data_src, *data_dst;
4372 unsigned int start;
4373 int i;
4374
4375 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
4376 return;
4377
4378 if (netif_running(dev) && netif_device_present(dev)) {
4379 if (spin_trylock_bh(&hwstats->stats_lock)) {
4380 mtk_stats_update_mac(mac);
4381 spin_unlock_bh(&hwstats->stats_lock);
4382 }
4383 }
4384
4385 data_src = (u64 *)hwstats;
4386
4387 do {
4388 data_dst = data;
4389 start = u64_stats_fetch_begin(&hwstats->syncp);
4390
4391 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
4392 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
4393 if (mtk_page_pool_enabled(mac->hw))
4394 mtk_ethtool_pp_stats(mac->hw, data_dst);
4395 } while (u64_stats_fetch_retry(&hwstats->syncp, start));
4396 }
4397
mtk_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)4398 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
4399 u32 *rule_locs)
4400 {
4401 int ret = -EOPNOTSUPP;
4402
4403 switch (cmd->cmd) {
4404 case ETHTOOL_GRXRINGS:
4405 if (dev->hw_features & NETIF_F_LRO) {
4406 cmd->data = MTK_MAX_RX_RING_NUM;
4407 ret = 0;
4408 }
4409 break;
4410 case ETHTOOL_GRXCLSRLCNT:
4411 if (dev->hw_features & NETIF_F_LRO) {
4412 struct mtk_mac *mac = netdev_priv(dev);
4413
4414 cmd->rule_cnt = mac->hwlro_ip_cnt;
4415 ret = 0;
4416 }
4417 break;
4418 case ETHTOOL_GRXCLSRULE:
4419 if (dev->hw_features & NETIF_F_LRO)
4420 ret = mtk_hwlro_get_fdir_entry(dev, cmd);
4421 break;
4422 case ETHTOOL_GRXCLSRLALL:
4423 if (dev->hw_features & NETIF_F_LRO)
4424 ret = mtk_hwlro_get_fdir_all(dev, cmd,
4425 rule_locs);
4426 break;
4427 default:
4428 break;
4429 }
4430
4431 return ret;
4432 }
4433
mtk_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)4434 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
4435 {
4436 int ret = -EOPNOTSUPP;
4437
4438 switch (cmd->cmd) {
4439 case ETHTOOL_SRXCLSRLINS:
4440 if (dev->hw_features & NETIF_F_LRO)
4441 ret = mtk_hwlro_add_ipaddr(dev, cmd);
4442 break;
4443 case ETHTOOL_SRXCLSRLDEL:
4444 if (dev->hw_features & NETIF_F_LRO)
4445 ret = mtk_hwlro_del_ipaddr(dev, cmd);
4446 break;
4447 default:
4448 break;
4449 }
4450
4451 return ret;
4452 }
4453
mtk_select_queue(struct net_device * dev,struct sk_buff * skb,struct net_device * sb_dev)4454 static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb,
4455 struct net_device *sb_dev)
4456 {
4457 struct mtk_mac *mac = netdev_priv(dev);
4458 unsigned int queue = 0;
4459
4460 if (netdev_uses_dsa(dev))
4461 queue = skb_get_queue_mapping(skb) + 3;
4462 else
4463 queue = mac->id;
4464
4465 if (queue >= dev->num_tx_queues)
4466 queue = 0;
4467
4468 return queue;
4469 }
4470
4471 static const struct ethtool_ops mtk_ethtool_ops = {
4472 .get_link_ksettings = mtk_get_link_ksettings,
4473 .set_link_ksettings = mtk_set_link_ksettings,
4474 .get_drvinfo = mtk_get_drvinfo,
4475 .get_msglevel = mtk_get_msglevel,
4476 .set_msglevel = mtk_set_msglevel,
4477 .nway_reset = mtk_nway_reset,
4478 .get_link = ethtool_op_get_link,
4479 .get_strings = mtk_get_strings,
4480 .get_sset_count = mtk_get_sset_count,
4481 .get_ethtool_stats = mtk_get_ethtool_stats,
4482 .get_rxnfc = mtk_get_rxnfc,
4483 .set_rxnfc = mtk_set_rxnfc,
4484 };
4485
4486 static const struct net_device_ops mtk_netdev_ops = {
4487 .ndo_uninit = mtk_uninit,
4488 .ndo_open = mtk_open,
4489 .ndo_stop = mtk_stop,
4490 .ndo_start_xmit = mtk_start_xmit,
4491 .ndo_set_mac_address = mtk_set_mac_address,
4492 .ndo_validate_addr = eth_validate_addr,
4493 .ndo_eth_ioctl = mtk_do_ioctl,
4494 .ndo_change_mtu = mtk_change_mtu,
4495 .ndo_tx_timeout = mtk_tx_timeout,
4496 .ndo_get_stats64 = mtk_get_stats64,
4497 .ndo_fix_features = mtk_fix_features,
4498 .ndo_set_features = mtk_set_features,
4499 #ifdef CONFIG_NET_POLL_CONTROLLER
4500 .ndo_poll_controller = mtk_poll_controller,
4501 #endif
4502 .ndo_setup_tc = mtk_eth_setup_tc,
4503 .ndo_bpf = mtk_xdp,
4504 .ndo_xdp_xmit = mtk_xdp_xmit,
4505 .ndo_select_queue = mtk_select_queue,
4506 };
4507
mtk_add_mac(struct mtk_eth * eth,struct device_node * np)4508 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
4509 {
4510 const __be32 *_id = of_get_property(np, "reg", NULL);
4511 phy_interface_t phy_mode;
4512 struct phylink *phylink;
4513 struct mtk_mac *mac;
4514 int id, err;
4515 int txqs = 1;
4516 u32 val;
4517
4518 if (!_id) {
4519 dev_err(eth->dev, "missing mac id\n");
4520 return -EINVAL;
4521 }
4522
4523 id = be32_to_cpup(_id);
4524 if (id >= MTK_MAX_DEVS) {
4525 dev_err(eth->dev, "%d is not a valid mac id\n", id);
4526 return -EINVAL;
4527 }
4528
4529 if (eth->netdev[id]) {
4530 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
4531 return -EINVAL;
4532 }
4533
4534 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
4535 txqs = MTK_QDMA_NUM_QUEUES;
4536
4537 eth->netdev[id] = alloc_etherdev_mqs(sizeof(*mac), txqs, 1);
4538 if (!eth->netdev[id]) {
4539 dev_err(eth->dev, "alloc_etherdev failed\n");
4540 return -ENOMEM;
4541 }
4542 mac = netdev_priv(eth->netdev[id]);
4543 eth->mac[id] = mac;
4544 mac->id = id;
4545 mac->hw = eth;
4546 mac->of_node = np;
4547
4548 err = of_get_ethdev_address(mac->of_node, eth->netdev[id]);
4549 if (err == -EPROBE_DEFER)
4550 return err;
4551
4552 if (err) {
4553 /* If the mac address is invalid, use random mac address */
4554 eth_hw_addr_random(eth->netdev[id]);
4555 dev_err(eth->dev, "generated random MAC address %pM\n",
4556 eth->netdev[id]->dev_addr);
4557 }
4558
4559 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
4560 mac->hwlro_ip_cnt = 0;
4561
4562 mac->hw_stats = devm_kzalloc(eth->dev,
4563 sizeof(*mac->hw_stats),
4564 GFP_KERNEL);
4565 if (!mac->hw_stats) {
4566 dev_err(eth->dev, "failed to allocate counter memory\n");
4567 err = -ENOMEM;
4568 goto free_netdev;
4569 }
4570 spin_lock_init(&mac->hw_stats->stats_lock);
4571 u64_stats_init(&mac->hw_stats->syncp);
4572
4573 if (mtk_is_netsys_v3_or_greater(eth))
4574 mac->hw_stats->reg_offset = id * 0x80;
4575 else
4576 mac->hw_stats->reg_offset = id * 0x40;
4577
4578 /* phylink create */
4579 err = of_get_phy_mode(np, &phy_mode);
4580 if (err) {
4581 dev_err(eth->dev, "incorrect phy-mode\n");
4582 goto free_netdev;
4583 }
4584
4585 /* mac config is not set */
4586 mac->interface = PHY_INTERFACE_MODE_NA;
4587 mac->speed = SPEED_UNKNOWN;
4588
4589 mac->phylink_config.dev = ð->netdev[id]->dev;
4590 mac->phylink_config.type = PHYLINK_NETDEV;
4591 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
4592 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
4593
4594 /* MT7623 gmac0 is now missing its speed-specific PLL configuration
4595 * in its .mac_config method (since state->speed is not valid there.
4596 * Disable support for MII, GMII and RGMII.
4597 */
4598 if (!mac->hw->soc->disable_pll_modes || mac->id != 0) {
4599 __set_bit(PHY_INTERFACE_MODE_MII,
4600 mac->phylink_config.supported_interfaces);
4601 __set_bit(PHY_INTERFACE_MODE_GMII,
4602 mac->phylink_config.supported_interfaces);
4603
4604 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII))
4605 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces);
4606 }
4607
4608 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id)
4609 __set_bit(PHY_INTERFACE_MODE_TRGMII,
4610 mac->phylink_config.supported_interfaces);
4611
4612 /* TRGMII is not permitted on MT7621 if using DDR2 */
4613 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) &&
4614 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) {
4615 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val);
4616 if (val & SYSCFG_DRAM_TYPE_DDR2)
4617 __clear_bit(PHY_INTERFACE_MODE_TRGMII,
4618 mac->phylink_config.supported_interfaces);
4619 }
4620
4621 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) {
4622 __set_bit(PHY_INTERFACE_MODE_SGMII,
4623 mac->phylink_config.supported_interfaces);
4624 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
4625 mac->phylink_config.supported_interfaces);
4626 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
4627 mac->phylink_config.supported_interfaces);
4628 }
4629
4630 if (mtk_is_netsys_v3_or_greater(mac->hw) &&
4631 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW) &&
4632 id == MTK_GMAC1_ID) {
4633 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
4634 MAC_SYM_PAUSE |
4635 MAC_10000FD;
4636 phy_interface_zero(mac->phylink_config.supported_interfaces);
4637 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
4638 mac->phylink_config.supported_interfaces);
4639 }
4640
4641 phylink = phylink_create(&mac->phylink_config,
4642 of_fwnode_handle(mac->of_node),
4643 phy_mode, &mtk_phylink_ops);
4644 if (IS_ERR(phylink)) {
4645 err = PTR_ERR(phylink);
4646 goto free_netdev;
4647 }
4648
4649 mac->phylink = phylink;
4650
4651 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
4652 eth->netdev[id]->watchdog_timeo = 5 * HZ;
4653 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
4654 eth->netdev[id]->base_addr = (unsigned long)eth->base;
4655
4656 eth->netdev[id]->hw_features = eth->soc->hw_features;
4657 if (eth->hwlro)
4658 eth->netdev[id]->hw_features |= NETIF_F_LRO;
4659
4660 eth->netdev[id]->vlan_features = eth->soc->hw_features &
4661 ~NETIF_F_HW_VLAN_CTAG_TX;
4662 eth->netdev[id]->features |= eth->soc->hw_features;
4663 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
4664
4665 eth->netdev[id]->irq = eth->irq[0];
4666 eth->netdev[id]->dev.of_node = np;
4667
4668 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
4669 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
4670 else
4671 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN;
4672
4673 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
4674 mac->device_notifier.notifier_call = mtk_device_event;
4675 register_netdevice_notifier(&mac->device_notifier);
4676 }
4677
4678 if (mtk_page_pool_enabled(eth))
4679 eth->netdev[id]->xdp_features = NETDEV_XDP_ACT_BASIC |
4680 NETDEV_XDP_ACT_REDIRECT |
4681 NETDEV_XDP_ACT_NDO_XMIT |
4682 NETDEV_XDP_ACT_NDO_XMIT_SG;
4683
4684 return 0;
4685
4686 free_netdev:
4687 free_netdev(eth->netdev[id]);
4688 return err;
4689 }
4690
mtk_eth_set_dma_device(struct mtk_eth * eth,struct device * dma_dev)4691 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev)
4692 {
4693 struct net_device *dev, *tmp;
4694 LIST_HEAD(dev_list);
4695 int i;
4696
4697 rtnl_lock();
4698
4699 for (i = 0; i < MTK_MAX_DEVS; i++) {
4700 dev = eth->netdev[i];
4701
4702 if (!dev || !(dev->flags & IFF_UP))
4703 continue;
4704
4705 list_add_tail(&dev->close_list, &dev_list);
4706 }
4707
4708 dev_close_many(&dev_list, false);
4709
4710 eth->dma_dev = dma_dev;
4711
4712 list_for_each_entry_safe(dev, tmp, &dev_list, close_list) {
4713 list_del_init(&dev->close_list);
4714 dev_open(dev, NULL);
4715 }
4716
4717 rtnl_unlock();
4718 }
4719
mtk_sgmii_init(struct mtk_eth * eth)4720 static int mtk_sgmii_init(struct mtk_eth *eth)
4721 {
4722 struct device_node *np;
4723 struct regmap *regmap;
4724 u32 flags;
4725 int i;
4726
4727 for (i = 0; i < MTK_MAX_DEVS; i++) {
4728 np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i);
4729 if (!np)
4730 break;
4731
4732 regmap = syscon_node_to_regmap(np);
4733 flags = 0;
4734 if (of_property_read_bool(np, "mediatek,pnswap"))
4735 flags |= MTK_SGMII_FLAG_PN_SWAP;
4736
4737 of_node_put(np);
4738
4739 if (IS_ERR(regmap))
4740 return PTR_ERR(regmap);
4741
4742 eth->sgmii_pcs[i] = mtk_pcs_lynxi_create(eth->dev, regmap,
4743 eth->soc->ana_rgc3,
4744 flags);
4745 }
4746
4747 return 0;
4748 }
4749
mtk_probe(struct platform_device * pdev)4750 static int mtk_probe(struct platform_device *pdev)
4751 {
4752 struct resource *res = NULL, *res_sram;
4753 struct device_node *mac_np;
4754 struct mtk_eth *eth;
4755 int err, i;
4756
4757 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
4758 if (!eth)
4759 return -ENOMEM;
4760
4761 eth->soc = of_device_get_match_data(&pdev->dev);
4762
4763 eth->dev = &pdev->dev;
4764 eth->dma_dev = &pdev->dev;
4765 eth->base = devm_platform_ioremap_resource(pdev, 0);
4766 if (IS_ERR(eth->base))
4767 return PTR_ERR(eth->base);
4768
4769 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
4770 eth->ip_align = NET_IP_ALIGN;
4771
4772 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) {
4773 /* SRAM is actual memory and supports transparent access just like DRAM.
4774 * Hence we don't require __iomem being set and don't need to use accessor
4775 * functions to read from or write to SRAM.
4776 */
4777 if (mtk_is_netsys_v3_or_greater(eth)) {
4778 eth->sram_base = (void __force *)devm_platform_ioremap_resource(pdev, 1);
4779 if (IS_ERR(eth->sram_base))
4780 return PTR_ERR(eth->sram_base);
4781 } else {
4782 eth->sram_base = (void __force *)eth->base + MTK_ETH_SRAM_OFFSET;
4783 }
4784 }
4785
4786 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) {
4787 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36));
4788 if (!err)
4789 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
4790
4791 if (err) {
4792 dev_err(&pdev->dev, "Wrong DMA config\n");
4793 return -EINVAL;
4794 }
4795 }
4796
4797 spin_lock_init(ð->page_lock);
4798 spin_lock_init(ð->tx_irq_lock);
4799 spin_lock_init(ð->rx_irq_lock);
4800 spin_lock_init(ð->dim_lock);
4801
4802 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4803 INIT_WORK(ð->rx_dim.work, mtk_dim_rx);
4804 INIT_DELAYED_WORK(ð->reset.monitor_work, mtk_hw_reset_monitor_work);
4805
4806 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4807 INIT_WORK(ð->tx_dim.work, mtk_dim_tx);
4808
4809 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
4810 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4811 "mediatek,ethsys");
4812 if (IS_ERR(eth->ethsys)) {
4813 dev_err(&pdev->dev, "no ethsys regmap found\n");
4814 return PTR_ERR(eth->ethsys);
4815 }
4816 }
4817
4818 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) {
4819 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4820 "mediatek,infracfg");
4821 if (IS_ERR(eth->infra)) {
4822 dev_err(&pdev->dev, "no infracfg regmap found\n");
4823 return PTR_ERR(eth->infra);
4824 }
4825 }
4826
4827 if (of_dma_is_coherent(pdev->dev.of_node)) {
4828 struct regmap *cci;
4829
4830 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4831 "cci-control-port");
4832 /* enable CPU/bus coherency */
4833 if (!IS_ERR(cci))
4834 regmap_write(cci, 0, 3);
4835 }
4836
4837 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
4838 err = mtk_sgmii_init(eth);
4839
4840 if (err)
4841 return err;
4842 }
4843
4844 if (eth->soc->required_pctl) {
4845 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4846 "mediatek,pctl");
4847 if (IS_ERR(eth->pctl)) {
4848 dev_err(&pdev->dev, "no pctl regmap found\n");
4849 err = PTR_ERR(eth->pctl);
4850 goto err_destroy_sgmii;
4851 }
4852 }
4853
4854 if (mtk_is_netsys_v2_or_greater(eth)) {
4855 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4856 if (!res) {
4857 err = -EINVAL;
4858 goto err_destroy_sgmii;
4859 }
4860 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) {
4861 if (mtk_is_netsys_v3_or_greater(eth)) {
4862 res_sram = platform_get_resource(pdev, IORESOURCE_MEM, 1);
4863 if (!res_sram) {
4864 err = -EINVAL;
4865 goto err_destroy_sgmii;
4866 }
4867 eth->phy_scratch_ring = res_sram->start;
4868 } else {
4869 eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET;
4870 }
4871 }
4872 }
4873
4874 if (eth->soc->offload_version) {
4875 for (i = 0;; i++) {
4876 struct device_node *np;
4877 phys_addr_t wdma_phy;
4878 u32 wdma_base;
4879
4880 if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base))
4881 break;
4882
4883 np = of_parse_phandle(pdev->dev.of_node,
4884 "mediatek,wed", i);
4885 if (!np)
4886 break;
4887
4888 wdma_base = eth->soc->reg_map->wdma_base[i];
4889 wdma_phy = res ? res->start + wdma_base : 0;
4890 mtk_wed_add_hw(np, eth, eth->base + wdma_base,
4891 wdma_phy, i);
4892 }
4893 }
4894
4895 for (i = 0; i < 3; i++) {
4896 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0)
4897 eth->irq[i] = eth->irq[0];
4898 else
4899 eth->irq[i] = platform_get_irq(pdev, i);
4900 if (eth->irq[i] < 0) {
4901 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
4902 err = -ENXIO;
4903 goto err_wed_exit;
4904 }
4905 }
4906 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
4907 eth->clks[i] = devm_clk_get(eth->dev,
4908 mtk_clks_source_name[i]);
4909 if (IS_ERR(eth->clks[i])) {
4910 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) {
4911 err = -EPROBE_DEFER;
4912 goto err_wed_exit;
4913 }
4914 if (eth->soc->required_clks & BIT(i)) {
4915 dev_err(&pdev->dev, "clock %s not found\n",
4916 mtk_clks_source_name[i]);
4917 err = -EINVAL;
4918 goto err_wed_exit;
4919 }
4920 eth->clks[i] = NULL;
4921 }
4922 }
4923
4924 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
4925 INIT_WORK(ð->pending_work, mtk_pending_work);
4926
4927 err = mtk_hw_init(eth, false);
4928 if (err)
4929 goto err_wed_exit;
4930
4931 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO);
4932
4933 for_each_child_of_node(pdev->dev.of_node, mac_np) {
4934 if (!of_device_is_compatible(mac_np,
4935 "mediatek,eth-mac"))
4936 continue;
4937
4938 if (!of_device_is_available(mac_np))
4939 continue;
4940
4941 err = mtk_add_mac(eth, mac_np);
4942 if (err) {
4943 of_node_put(mac_np);
4944 goto err_deinit_hw;
4945 }
4946 }
4947
4948 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
4949 err = devm_request_irq(eth->dev, eth->irq[0],
4950 mtk_handle_irq, 0,
4951 dev_name(eth->dev), eth);
4952 } else {
4953 err = devm_request_irq(eth->dev, eth->irq[1],
4954 mtk_handle_irq_tx, 0,
4955 dev_name(eth->dev), eth);
4956 if (err)
4957 goto err_free_dev;
4958
4959 err = devm_request_irq(eth->dev, eth->irq[2],
4960 mtk_handle_irq_rx, 0,
4961 dev_name(eth->dev), eth);
4962 }
4963 if (err)
4964 goto err_free_dev;
4965
4966 /* No MT7628/88 support yet */
4967 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
4968 err = mtk_mdio_init(eth);
4969 if (err)
4970 goto err_free_dev;
4971 }
4972
4973 if (eth->soc->offload_version) {
4974 u32 num_ppe = mtk_is_netsys_v2_or_greater(eth) ? 2 : 1;
4975
4976 num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe);
4977 for (i = 0; i < num_ppe; i++) {
4978 u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
4979
4980 eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, i);
4981
4982 if (!eth->ppe[i]) {
4983 err = -ENOMEM;
4984 goto err_deinit_ppe;
4985 }
4986 }
4987
4988 err = mtk_eth_offload_init(eth);
4989 if (err)
4990 goto err_deinit_ppe;
4991 }
4992
4993 for (i = 0; i < MTK_MAX_DEVS; i++) {
4994 if (!eth->netdev[i])
4995 continue;
4996
4997 err = register_netdev(eth->netdev[i]);
4998 if (err) {
4999 dev_err(eth->dev, "error bringing up device\n");
5000 goto err_deinit_ppe;
5001 } else
5002 netif_info(eth, probe, eth->netdev[i],
5003 "mediatek frame engine at 0x%08lx, irq %d\n",
5004 eth->netdev[i]->base_addr, eth->irq[0]);
5005 }
5006
5007 /* we run 2 devices on the same DMA ring so we need a dummy device
5008 * for NAPI to work
5009 */
5010 init_dummy_netdev(ð->dummy_dev);
5011 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx);
5012 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx);
5013
5014 platform_set_drvdata(pdev, eth);
5015 schedule_delayed_work(ð->reset.monitor_work,
5016 MTK_DMA_MONITOR_TIMEOUT);
5017
5018 return 0;
5019
5020 err_deinit_ppe:
5021 mtk_ppe_deinit(eth);
5022 mtk_mdio_cleanup(eth);
5023 err_free_dev:
5024 mtk_free_dev(eth);
5025 err_deinit_hw:
5026 mtk_hw_deinit(eth);
5027 err_wed_exit:
5028 mtk_wed_exit();
5029 err_destroy_sgmii:
5030 mtk_sgmii_destroy(eth);
5031
5032 return err;
5033 }
5034
mtk_remove(struct platform_device * pdev)5035 static int mtk_remove(struct platform_device *pdev)
5036 {
5037 struct mtk_eth *eth = platform_get_drvdata(pdev);
5038 struct mtk_mac *mac;
5039 int i;
5040
5041 /* stop all devices to make sure that dma is properly shut down */
5042 for (i = 0; i < MTK_MAX_DEVS; i++) {
5043 if (!eth->netdev[i])
5044 continue;
5045 mtk_stop(eth->netdev[i]);
5046 mac = netdev_priv(eth->netdev[i]);
5047 phylink_disconnect_phy(mac->phylink);
5048 }
5049
5050 mtk_wed_exit();
5051 mtk_hw_deinit(eth);
5052
5053 netif_napi_del(ð->tx_napi);
5054 netif_napi_del(ð->rx_napi);
5055 mtk_cleanup(eth);
5056 mtk_mdio_cleanup(eth);
5057
5058 return 0;
5059 }
5060
5061 static const struct mtk_soc_data mt2701_data = {
5062 .reg_map = &mtk_reg_map,
5063 .caps = MT7623_CAPS | MTK_HWLRO,
5064 .hw_features = MTK_HW_FEATURES,
5065 .required_clks = MT7623_CLKS_BITMAP,
5066 .required_pctl = true,
5067 .version = 1,
5068 .txrx = {
5069 .txd_size = sizeof(struct mtk_tx_dma),
5070 .rxd_size = sizeof(struct mtk_rx_dma),
5071 .rx_irq_done_mask = MTK_RX_DONE_INT,
5072 .rx_dma_l4_valid = RX_DMA_L4_VALID,
5073 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5074 .dma_len_offset = 16,
5075 },
5076 };
5077
5078 static const struct mtk_soc_data mt7621_data = {
5079 .reg_map = &mtk_reg_map,
5080 .caps = MT7621_CAPS,
5081 .hw_features = MTK_HW_FEATURES,
5082 .required_clks = MT7621_CLKS_BITMAP,
5083 .required_pctl = false,
5084 .version = 1,
5085 .offload_version = 1,
5086 .hash_offset = 2,
5087 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
5088 .txrx = {
5089 .txd_size = sizeof(struct mtk_tx_dma),
5090 .rxd_size = sizeof(struct mtk_rx_dma),
5091 .rx_irq_done_mask = MTK_RX_DONE_INT,
5092 .rx_dma_l4_valid = RX_DMA_L4_VALID,
5093 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5094 .dma_len_offset = 16,
5095 },
5096 };
5097
5098 static const struct mtk_soc_data mt7622_data = {
5099 .reg_map = &mtk_reg_map,
5100 .ana_rgc3 = 0x2028,
5101 .caps = MT7622_CAPS | MTK_HWLRO,
5102 .hw_features = MTK_HW_FEATURES,
5103 .required_clks = MT7622_CLKS_BITMAP,
5104 .required_pctl = false,
5105 .version = 1,
5106 .offload_version = 2,
5107 .hash_offset = 2,
5108 .has_accounting = true,
5109 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
5110 .txrx = {
5111 .txd_size = sizeof(struct mtk_tx_dma),
5112 .rxd_size = sizeof(struct mtk_rx_dma),
5113 .rx_irq_done_mask = MTK_RX_DONE_INT,
5114 .rx_dma_l4_valid = RX_DMA_L4_VALID,
5115 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5116 .dma_len_offset = 16,
5117 },
5118 };
5119
5120 static const struct mtk_soc_data mt7623_data = {
5121 .reg_map = &mtk_reg_map,
5122 .caps = MT7623_CAPS | MTK_HWLRO,
5123 .hw_features = MTK_HW_FEATURES,
5124 .required_clks = MT7623_CLKS_BITMAP,
5125 .required_pctl = true,
5126 .version = 1,
5127 .offload_version = 1,
5128 .hash_offset = 2,
5129 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
5130 .disable_pll_modes = true,
5131 .txrx = {
5132 .txd_size = sizeof(struct mtk_tx_dma),
5133 .rxd_size = sizeof(struct mtk_rx_dma),
5134 .rx_irq_done_mask = MTK_RX_DONE_INT,
5135 .rx_dma_l4_valid = RX_DMA_L4_VALID,
5136 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5137 .dma_len_offset = 16,
5138 },
5139 };
5140
5141 static const struct mtk_soc_data mt7629_data = {
5142 .reg_map = &mtk_reg_map,
5143 .ana_rgc3 = 0x128,
5144 .caps = MT7629_CAPS | MTK_HWLRO,
5145 .hw_features = MTK_HW_FEATURES,
5146 .required_clks = MT7629_CLKS_BITMAP,
5147 .required_pctl = false,
5148 .has_accounting = true,
5149 .version = 1,
5150 .txrx = {
5151 .txd_size = sizeof(struct mtk_tx_dma),
5152 .rxd_size = sizeof(struct mtk_rx_dma),
5153 .rx_irq_done_mask = MTK_RX_DONE_INT,
5154 .rx_dma_l4_valid = RX_DMA_L4_VALID,
5155 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5156 .dma_len_offset = 16,
5157 },
5158 };
5159
5160 static const struct mtk_soc_data mt7981_data = {
5161 .reg_map = &mt7986_reg_map,
5162 .ana_rgc3 = 0x128,
5163 .caps = MT7981_CAPS,
5164 .hw_features = MTK_HW_FEATURES,
5165 .required_clks = MT7981_CLKS_BITMAP,
5166 .required_pctl = false,
5167 .version = 2,
5168 .offload_version = 2,
5169 .hash_offset = 4,
5170 .has_accounting = true,
5171 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
5172 .txrx = {
5173 .txd_size = sizeof(struct mtk_tx_dma_v2),
5174 .rxd_size = sizeof(struct mtk_rx_dma_v2),
5175 .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
5176 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
5177 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
5178 .dma_len_offset = 8,
5179 },
5180 };
5181
5182 static const struct mtk_soc_data mt7986_data = {
5183 .reg_map = &mt7986_reg_map,
5184 .ana_rgc3 = 0x128,
5185 .caps = MT7986_CAPS,
5186 .hw_features = MTK_HW_FEATURES,
5187 .required_clks = MT7986_CLKS_BITMAP,
5188 .required_pctl = false,
5189 .version = 2,
5190 .offload_version = 2,
5191 .hash_offset = 4,
5192 .has_accounting = true,
5193 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
5194 .txrx = {
5195 .txd_size = sizeof(struct mtk_tx_dma_v2),
5196 .rxd_size = sizeof(struct mtk_rx_dma_v2),
5197 .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
5198 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
5199 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
5200 .dma_len_offset = 8,
5201 },
5202 };
5203
5204 static const struct mtk_soc_data mt7988_data = {
5205 .reg_map = &mt7988_reg_map,
5206 .ana_rgc3 = 0x128,
5207 .caps = MT7988_CAPS,
5208 .hw_features = MTK_HW_FEATURES,
5209 .required_clks = MT7988_CLKS_BITMAP,
5210 .required_pctl = false,
5211 .version = 3,
5212 .offload_version = 2,
5213 .hash_offset = 4,
5214 .has_accounting = true,
5215 .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
5216 .txrx = {
5217 .txd_size = sizeof(struct mtk_tx_dma_v2),
5218 .rxd_size = sizeof(struct mtk_rx_dma_v2),
5219 .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
5220 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
5221 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
5222 .dma_len_offset = 8,
5223 },
5224 };
5225
5226 static const struct mtk_soc_data rt5350_data = {
5227 .reg_map = &mt7628_reg_map,
5228 .caps = MT7628_CAPS,
5229 .hw_features = MTK_HW_FEATURES_MT7628,
5230 .required_clks = MT7628_CLKS_BITMAP,
5231 .required_pctl = false,
5232 .version = 1,
5233 .txrx = {
5234 .txd_size = sizeof(struct mtk_tx_dma),
5235 .rxd_size = sizeof(struct mtk_rx_dma),
5236 .rx_irq_done_mask = MTK_RX_DONE_INT,
5237 .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA,
5238 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5239 .dma_len_offset = 16,
5240 },
5241 };
5242
5243 const struct of_device_id of_mtk_match[] = {
5244 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data },
5245 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data },
5246 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data },
5247 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data },
5248 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data },
5249 { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data },
5250 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data },
5251 { .compatible = "mediatek,mt7988-eth", .data = &mt7988_data },
5252 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
5253 {},
5254 };
5255 MODULE_DEVICE_TABLE(of, of_mtk_match);
5256
5257 static struct platform_driver mtk_driver = {
5258 .probe = mtk_probe,
5259 .remove = mtk_remove,
5260 .driver = {
5261 .name = "mtk_soc_eth",
5262 .of_match_table = of_mtk_match,
5263 },
5264 };
5265
5266 module_platform_driver(mtk_driver);
5267
5268 MODULE_LICENSE("GPL");
5269 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
5270 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
5271