1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: YT SHEN <yt.shen@mediatek.com>
5 */
6
7 #include <linux/component.h>
8 #include <linux/iommu.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_platform.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/dma-mapping.h>
15
16 #include <drm/drm_atomic.h>
17 #include <drm/drm_atomic_helper.h>
18 #include <drm/drm_drv.h>
19 #include <drm/drm_fbdev_generic.h>
20 #include <drm/drm_fourcc.h>
21 #include <drm/drm_gem.h>
22 #include <drm/drm_gem_framebuffer_helper.h>
23 #include <drm/drm_ioctl.h>
24 #include <drm/drm_of.h>
25 #include <drm/drm_probe_helper.h>
26 #include <drm/drm_vblank.h>
27
28 #include "mtk_drm_crtc.h"
29 #include "mtk_drm_ddp_comp.h"
30 #include "mtk_drm_drv.h"
31 #include "mtk_drm_gem.h"
32
33 #define DRIVER_NAME "mediatek"
34 #define DRIVER_DESC "Mediatek SoC DRM"
35 #define DRIVER_DATE "20150513"
36 #define DRIVER_MAJOR 1
37 #define DRIVER_MINOR 0
38
39 static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = {
40 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
41 };
42
43 static struct drm_framebuffer *
mtk_drm_mode_fb_create(struct drm_device * dev,struct drm_file * file,const struct drm_mode_fb_cmd2 * cmd)44 mtk_drm_mode_fb_create(struct drm_device *dev,
45 struct drm_file *file,
46 const struct drm_mode_fb_cmd2 *cmd)
47 {
48 const struct drm_format_info *info = drm_get_format_info(dev, cmd);
49
50 if (info->num_planes != 1)
51 return ERR_PTR(-EINVAL);
52
53 return drm_gem_fb_create(dev, file, cmd);
54 }
55
56 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
57 .fb_create = mtk_drm_mode_fb_create,
58 .atomic_check = drm_atomic_helper_check,
59 .atomic_commit = drm_atomic_helper_commit,
60 };
61
62 static const unsigned int mt2701_mtk_ddp_main[] = {
63 DDP_COMPONENT_OVL0,
64 DDP_COMPONENT_RDMA0,
65 DDP_COMPONENT_COLOR0,
66 DDP_COMPONENT_BLS,
67 DDP_COMPONENT_DSI0,
68 };
69
70 static const unsigned int mt2701_mtk_ddp_ext[] = {
71 DDP_COMPONENT_RDMA1,
72 DDP_COMPONENT_DPI0,
73 };
74
75 static const unsigned int mt7623_mtk_ddp_main[] = {
76 DDP_COMPONENT_OVL0,
77 DDP_COMPONENT_RDMA0,
78 DDP_COMPONENT_COLOR0,
79 DDP_COMPONENT_BLS,
80 DDP_COMPONENT_DPI0,
81 };
82
83 static const unsigned int mt7623_mtk_ddp_ext[] = {
84 DDP_COMPONENT_RDMA1,
85 DDP_COMPONENT_DSI0,
86 };
87
88 static const unsigned int mt2712_mtk_ddp_main[] = {
89 DDP_COMPONENT_OVL0,
90 DDP_COMPONENT_COLOR0,
91 DDP_COMPONENT_AAL0,
92 DDP_COMPONENT_OD0,
93 DDP_COMPONENT_RDMA0,
94 DDP_COMPONENT_DPI0,
95 DDP_COMPONENT_PWM0,
96 };
97
98 static const unsigned int mt2712_mtk_ddp_ext[] = {
99 DDP_COMPONENT_OVL1,
100 DDP_COMPONENT_COLOR1,
101 DDP_COMPONENT_AAL1,
102 DDP_COMPONENT_OD1,
103 DDP_COMPONENT_RDMA1,
104 DDP_COMPONENT_DPI1,
105 DDP_COMPONENT_PWM1,
106 };
107
108 static const unsigned int mt2712_mtk_ddp_third[] = {
109 DDP_COMPONENT_RDMA2,
110 DDP_COMPONENT_DSI3,
111 DDP_COMPONENT_PWM2,
112 };
113
114 static unsigned int mt8167_mtk_ddp_main[] = {
115 DDP_COMPONENT_OVL0,
116 DDP_COMPONENT_COLOR0,
117 DDP_COMPONENT_CCORR,
118 DDP_COMPONENT_AAL0,
119 DDP_COMPONENT_GAMMA,
120 DDP_COMPONENT_DITHER0,
121 DDP_COMPONENT_RDMA0,
122 DDP_COMPONENT_DSI0,
123 };
124
125 static const unsigned int mt8173_mtk_ddp_main[] = {
126 DDP_COMPONENT_OVL0,
127 DDP_COMPONENT_COLOR0,
128 DDP_COMPONENT_AAL0,
129 DDP_COMPONENT_OD0,
130 DDP_COMPONENT_RDMA0,
131 DDP_COMPONENT_UFOE,
132 DDP_COMPONENT_DSI0,
133 DDP_COMPONENT_PWM0,
134 };
135
136 static const unsigned int mt8173_mtk_ddp_ext[] = {
137 DDP_COMPONENT_OVL1,
138 DDP_COMPONENT_COLOR1,
139 DDP_COMPONENT_GAMMA,
140 DDP_COMPONENT_RDMA1,
141 DDP_COMPONENT_DPI0,
142 };
143
144 static const unsigned int mt8183_mtk_ddp_main[] = {
145 DDP_COMPONENT_OVL0,
146 DDP_COMPONENT_OVL_2L0,
147 DDP_COMPONENT_RDMA0,
148 DDP_COMPONENT_COLOR0,
149 DDP_COMPONENT_CCORR,
150 DDP_COMPONENT_AAL0,
151 DDP_COMPONENT_GAMMA,
152 DDP_COMPONENT_DITHER0,
153 DDP_COMPONENT_DSI0,
154 };
155
156 static const unsigned int mt8183_mtk_ddp_ext[] = {
157 DDP_COMPONENT_OVL_2L1,
158 DDP_COMPONENT_RDMA1,
159 DDP_COMPONENT_DPI0,
160 };
161
162 static const unsigned int mt8186_mtk_ddp_main[] = {
163 DDP_COMPONENT_OVL0,
164 DDP_COMPONENT_RDMA0,
165 DDP_COMPONENT_COLOR0,
166 DDP_COMPONENT_CCORR,
167 DDP_COMPONENT_AAL0,
168 DDP_COMPONENT_GAMMA,
169 DDP_COMPONENT_POSTMASK0,
170 DDP_COMPONENT_DITHER0,
171 DDP_COMPONENT_DSI0,
172 };
173
174 static const unsigned int mt8186_mtk_ddp_ext[] = {
175 DDP_COMPONENT_OVL_2L0,
176 DDP_COMPONENT_RDMA1,
177 DDP_COMPONENT_DPI0,
178 };
179
180 static const unsigned int mt8188_mtk_ddp_main[] = {
181 DDP_COMPONENT_OVL0,
182 DDP_COMPONENT_RDMA0,
183 DDP_COMPONENT_COLOR0,
184 DDP_COMPONENT_CCORR,
185 DDP_COMPONENT_AAL0,
186 DDP_COMPONENT_GAMMA,
187 DDP_COMPONENT_POSTMASK0,
188 DDP_COMPONENT_DITHER0,
189 DDP_COMPONENT_DP_INTF0,
190 };
191
192 static const unsigned int mt8192_mtk_ddp_main[] = {
193 DDP_COMPONENT_OVL0,
194 DDP_COMPONENT_OVL_2L0,
195 DDP_COMPONENT_RDMA0,
196 DDP_COMPONENT_COLOR0,
197 DDP_COMPONENT_CCORR,
198 DDP_COMPONENT_AAL0,
199 DDP_COMPONENT_GAMMA,
200 DDP_COMPONENT_POSTMASK0,
201 DDP_COMPONENT_DITHER0,
202 DDP_COMPONENT_DSI0,
203 };
204
205 static const unsigned int mt8192_mtk_ddp_ext[] = {
206 DDP_COMPONENT_OVL_2L2,
207 DDP_COMPONENT_RDMA4,
208 DDP_COMPONENT_DPI0,
209 };
210
211 static const unsigned int mt8195_mtk_ddp_main[] = {
212 DDP_COMPONENT_OVL0,
213 DDP_COMPONENT_RDMA0,
214 DDP_COMPONENT_COLOR0,
215 DDP_COMPONENT_CCORR,
216 DDP_COMPONENT_AAL0,
217 DDP_COMPONENT_GAMMA,
218 DDP_COMPONENT_DITHER0,
219 DDP_COMPONENT_DSC0,
220 DDP_COMPONENT_MERGE0,
221 DDP_COMPONENT_DP_INTF0,
222 };
223
224 static const unsigned int mt8195_mtk_ddp_ext[] = {
225 DDP_COMPONENT_DRM_OVL_ADAPTOR,
226 DDP_COMPONENT_MERGE5,
227 DDP_COMPONENT_DP_INTF1,
228 };
229
230 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
231 .main_path = mt2701_mtk_ddp_main,
232 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
233 .ext_path = mt2701_mtk_ddp_ext,
234 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
235 .shadow_register = true,
236 .mmsys_dev_num = 1,
237 };
238
239 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
240 .main_path = mt7623_mtk_ddp_main,
241 .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
242 .ext_path = mt7623_mtk_ddp_ext,
243 .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
244 .shadow_register = true,
245 .mmsys_dev_num = 1,
246 };
247
248 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
249 .main_path = mt2712_mtk_ddp_main,
250 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
251 .ext_path = mt2712_mtk_ddp_ext,
252 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
253 .third_path = mt2712_mtk_ddp_third,
254 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
255 .mmsys_dev_num = 1,
256 };
257
258 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
259 .main_path = mt8167_mtk_ddp_main,
260 .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
261 .mmsys_dev_num = 1,
262 };
263
264 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
265 .main_path = mt8173_mtk_ddp_main,
266 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
267 .ext_path = mt8173_mtk_ddp_ext,
268 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
269 .mmsys_dev_num = 1,
270 };
271
272 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
273 .main_path = mt8183_mtk_ddp_main,
274 .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
275 .ext_path = mt8183_mtk_ddp_ext,
276 .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
277 .mmsys_dev_num = 1,
278 };
279
280 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
281 .main_path = mt8186_mtk_ddp_main,
282 .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main),
283 .ext_path = mt8186_mtk_ddp_ext,
284 .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext),
285 .mmsys_dev_num = 1,
286 };
287
288 static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
289 .main_path = mt8188_mtk_ddp_main,
290 .main_len = ARRAY_SIZE(mt8188_mtk_ddp_main),
291 .mmsys_dev_num = 1,
292 };
293
294 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
295 .main_path = mt8192_mtk_ddp_main,
296 .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
297 .ext_path = mt8192_mtk_ddp_ext,
298 .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
299 .mmsys_dev_num = 1,
300 };
301
302 static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
303 .main_path = mt8195_mtk_ddp_main,
304 .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
305 .mmsys_dev_num = 2,
306 };
307
308 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
309 .ext_path = mt8195_mtk_ddp_ext,
310 .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
311 .mmsys_id = 1,
312 .mmsys_dev_num = 2,
313 };
314
315 static const struct of_device_id mtk_drm_of_ids[] = {
316 { .compatible = "mediatek,mt2701-mmsys",
317 .data = &mt2701_mmsys_driver_data},
318 { .compatible = "mediatek,mt7623-mmsys",
319 .data = &mt7623_mmsys_driver_data},
320 { .compatible = "mediatek,mt2712-mmsys",
321 .data = &mt2712_mmsys_driver_data},
322 { .compatible = "mediatek,mt8167-mmsys",
323 .data = &mt8167_mmsys_driver_data},
324 { .compatible = "mediatek,mt8173-mmsys",
325 .data = &mt8173_mmsys_driver_data},
326 { .compatible = "mediatek,mt8183-mmsys",
327 .data = &mt8183_mmsys_driver_data},
328 { .compatible = "mediatek,mt8186-mmsys",
329 .data = &mt8186_mmsys_driver_data},
330 { .compatible = "mediatek,mt8188-vdosys0",
331 .data = &mt8188_vdosys0_driver_data},
332 { .compatible = "mediatek,mt8192-mmsys",
333 .data = &mt8192_mmsys_driver_data},
334 { .compatible = "mediatek,mt8195-mmsys",
335 .data = &mt8195_vdosys0_driver_data},
336 { .compatible = "mediatek,mt8195-vdosys0",
337 .data = &mt8195_vdosys0_driver_data},
338 { .compatible = "mediatek,mt8195-vdosys1",
339 .data = &mt8195_vdosys1_driver_data},
340 { }
341 };
342 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
343
mtk_drm_match(struct device * dev,void * data)344 static int mtk_drm_match(struct device *dev, void *data)
345 {
346 if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1))
347 return true;
348 return false;
349 }
350
mtk_drm_get_all_drm_priv(struct device * dev)351 static bool mtk_drm_get_all_drm_priv(struct device *dev)
352 {
353 struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
354 struct mtk_drm_private *all_drm_priv[MAX_CRTC];
355 struct device_node *phandle = dev->parent->of_node;
356 const struct of_device_id *of_id;
357 struct device_node *node;
358 struct device *drm_dev;
359 unsigned int cnt = 0;
360 int i, j;
361
362 for_each_child_of_node(phandle->parent, node) {
363 struct platform_device *pdev;
364
365 of_id = of_match_node(mtk_drm_of_ids, node);
366 if (!of_id)
367 continue;
368
369 pdev = of_find_device_by_node(node);
370 if (!pdev)
371 continue;
372
373 drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match);
374 if (!drm_dev || !dev_get_drvdata(drm_dev))
375 continue;
376
377 all_drm_priv[cnt] = dev_get_drvdata(drm_dev);
378 if (all_drm_priv[cnt] && all_drm_priv[cnt]->mtk_drm_bound)
379 cnt++;
380
381 if (cnt == MAX_CRTC) {
382 of_node_put(node);
383 break;
384 }
385 }
386
387 if (drm_priv->data->mmsys_dev_num == cnt) {
388 for (i = 0; i < cnt; i++)
389 for (j = 0; j < cnt; j++)
390 all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
391
392 return true;
393 }
394
395 return false;
396 }
397
mtk_drm_find_mmsys_comp(struct mtk_drm_private * private,int comp_id)398 static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
399 {
400 const struct mtk_mmsys_driver_data *drv_data = private->data;
401 int i;
402
403 if (drv_data->main_path)
404 for (i = 0; i < drv_data->main_len; i++)
405 if (drv_data->main_path[i] == comp_id)
406 return true;
407
408 if (drv_data->ext_path)
409 for (i = 0; i < drv_data->ext_len; i++)
410 if (drv_data->ext_path[i] == comp_id)
411 return true;
412
413 if (drv_data->third_path)
414 for (i = 0; i < drv_data->third_len; i++)
415 if (drv_data->third_path[i] == comp_id)
416 return true;
417
418 return false;
419 }
420
mtk_drm_kms_init(struct drm_device * drm)421 static int mtk_drm_kms_init(struct drm_device *drm)
422 {
423 struct mtk_drm_private *private = drm->dev_private;
424 struct mtk_drm_private *priv_n;
425 struct device *dma_dev = NULL;
426 struct drm_crtc *crtc;
427 int ret, i, j;
428
429 if (drm_firmware_drivers_only())
430 return -ENODEV;
431
432 ret = drmm_mode_config_init(drm);
433 if (ret)
434 return ret;
435
436 drm->mode_config.min_width = 64;
437 drm->mode_config.min_height = 64;
438
439 /*
440 * set max width and height as default value(4096x4096).
441 * this value would be used to check framebuffer size limitation
442 * at drm_mode_addfb().
443 */
444 drm->mode_config.max_width = 4096;
445 drm->mode_config.max_height = 4096;
446 drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
447 drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
448
449 for (i = 0; i < private->data->mmsys_dev_num; i++) {
450 drm->dev_private = private->all_drm_private[i];
451 ret = component_bind_all(private->all_drm_private[i]->dev, drm);
452 if (ret) {
453 while (--i >= 0)
454 component_unbind_all(private->all_drm_private[i]->dev, drm);
455 return ret;
456 }
457 }
458
459 /*
460 * Ensure internal panels are at the top of the connector list before
461 * crtc creation.
462 */
463 drm_helper_move_panel_connectors_to_head(drm);
464
465 /*
466 * 1. We currently support two fixed data streams, each optional,
467 * and each statically assigned to a crtc:
468 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
469 * 2. For multi mmsys architecture, crtc path data are located in
470 * different drm private data structures. Loop through crtc index to
471 * create crtc from the main path and then ext_path and finally the
472 * third path.
473 */
474 for (i = 0; i < MAX_CRTC; i++) {
475 for (j = 0; j < private->data->mmsys_dev_num; j++) {
476 priv_n = private->all_drm_private[j];
477
478 if (i == 0 && priv_n->data->main_len) {
479 ret = mtk_drm_crtc_create(drm, priv_n->data->main_path,
480 priv_n->data->main_len, j);
481 if (ret)
482 goto err_component_unbind;
483
484 continue;
485 } else if (i == 1 && priv_n->data->ext_len) {
486 ret = mtk_drm_crtc_create(drm, priv_n->data->ext_path,
487 priv_n->data->ext_len, j);
488 if (ret)
489 goto err_component_unbind;
490
491 continue;
492 } else if (i == 2 && priv_n->data->third_len) {
493 ret = mtk_drm_crtc_create(drm, priv_n->data->third_path,
494 priv_n->data->third_len, j);
495 if (ret)
496 goto err_component_unbind;
497
498 continue;
499 }
500 }
501 }
502
503 /* Use OVL device for all DMA memory allocations */
504 crtc = drm_crtc_from_index(drm, 0);
505 if (crtc)
506 dma_dev = mtk_drm_crtc_dma_dev_get(crtc);
507 if (!dma_dev) {
508 ret = -ENODEV;
509 dev_err(drm->dev, "Need at least one OVL device\n");
510 goto err_component_unbind;
511 }
512
513 for (i = 0; i < private->data->mmsys_dev_num; i++)
514 private->all_drm_private[i]->dma_dev = dma_dev;
515
516 /*
517 * Configure the DMA segment size to make sure we get contiguous IOVA
518 * when importing PRIME buffers.
519 */
520 ret = dma_set_max_seg_size(dma_dev, UINT_MAX);
521 if (ret) {
522 dev_err(dma_dev, "Failed to set DMA segment size\n");
523 goto err_component_unbind;
524 }
525
526 ret = drm_vblank_init(drm, MAX_CRTC);
527 if (ret < 0)
528 goto err_component_unbind;
529
530 drm_kms_helper_poll_init(drm);
531 drm_mode_config_reset(drm);
532
533 return 0;
534
535 err_component_unbind:
536 for (i = 0; i < private->data->mmsys_dev_num; i++)
537 component_unbind_all(private->all_drm_private[i]->dev, drm);
538
539 return ret;
540 }
541
mtk_drm_kms_deinit(struct drm_device * drm)542 static void mtk_drm_kms_deinit(struct drm_device *drm)
543 {
544 drm_kms_helper_poll_fini(drm);
545 drm_atomic_helper_shutdown(drm);
546
547 component_unbind_all(drm->dev, drm);
548 }
549
550 DEFINE_DRM_GEM_FOPS(mtk_drm_fops);
551
552 /*
553 * We need to override this because the device used to import the memory is
554 * not dev->dev, as drm_gem_prime_import() expects.
555 */
mtk_drm_gem_prime_import(struct drm_device * dev,struct dma_buf * dma_buf)556 static struct drm_gem_object *mtk_drm_gem_prime_import(struct drm_device *dev,
557 struct dma_buf *dma_buf)
558 {
559 struct mtk_drm_private *private = dev->dev_private;
560
561 return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev);
562 }
563
564 static const struct drm_driver mtk_drm_driver = {
565 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
566
567 .dumb_create = mtk_drm_gem_dumb_create,
568
569 .gem_prime_import = mtk_drm_gem_prime_import,
570 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table,
571 .fops = &mtk_drm_fops,
572
573 .name = DRIVER_NAME,
574 .desc = DRIVER_DESC,
575 .date = DRIVER_DATE,
576 .major = DRIVER_MAJOR,
577 .minor = DRIVER_MINOR,
578 };
579
compare_dev(struct device * dev,void * data)580 static int compare_dev(struct device *dev, void *data)
581 {
582 return dev == (struct device *)data;
583 }
584
mtk_drm_bind(struct device * dev)585 static int mtk_drm_bind(struct device *dev)
586 {
587 struct mtk_drm_private *private = dev_get_drvdata(dev);
588 struct platform_device *pdev;
589 struct drm_device *drm;
590 int ret, i;
591
592 if (!iommu_present(&platform_bus_type))
593 return -EPROBE_DEFER;
594
595 pdev = of_find_device_by_node(private->mutex_node);
596 if (!pdev) {
597 dev_err(dev, "Waiting for disp-mutex device %pOF\n",
598 private->mutex_node);
599 of_node_put(private->mutex_node);
600 return -EPROBE_DEFER;
601 }
602
603 private->mutex_dev = &pdev->dev;
604 private->mtk_drm_bound = true;
605 private->dev = dev;
606
607 if (!mtk_drm_get_all_drm_priv(dev))
608 return 0;
609
610 drm = drm_dev_alloc(&mtk_drm_driver, dev);
611 if (IS_ERR(drm)) {
612 ret = PTR_ERR(drm);
613 goto err_put_dev;
614 }
615
616 private->drm_master = true;
617 drm->dev_private = private;
618 for (i = 0; i < private->data->mmsys_dev_num; i++)
619 private->all_drm_private[i]->drm = drm;
620
621 ret = mtk_drm_kms_init(drm);
622 if (ret < 0)
623 goto err_free;
624
625 ret = drm_dev_register(drm, 0);
626 if (ret < 0)
627 goto err_deinit;
628
629 drm_fbdev_generic_setup(drm, 32);
630
631 return 0;
632
633 err_deinit:
634 mtk_drm_kms_deinit(drm);
635 err_free:
636 private->drm = NULL;
637 drm_dev_put(drm);
638 for (i = 0; i < private->data->mmsys_dev_num; i++)
639 private->all_drm_private[i]->drm = NULL;
640 err_put_dev:
641 for (i = 0; i < private->data->mmsys_dev_num; i++) {
642 /* For device_find_child in mtk_drm_get_all_priv() */
643 put_device(private->all_drm_private[i]->dev);
644 }
645 put_device(private->mutex_dev);
646 return ret;
647 }
648
mtk_drm_unbind(struct device * dev)649 static void mtk_drm_unbind(struct device *dev)
650 {
651 struct mtk_drm_private *private = dev_get_drvdata(dev);
652 int i;
653
654 /* for multi mmsys dev, unregister drm dev in mmsys master */
655 if (private->drm_master) {
656 drm_dev_unregister(private->drm);
657 mtk_drm_kms_deinit(private->drm);
658 drm_dev_put(private->drm);
659
660 for (i = 0; i < private->data->mmsys_dev_num; i++) {
661 /* For device_find_child in mtk_drm_get_all_priv() */
662 put_device(private->all_drm_private[i]->dev);
663 }
664 put_device(private->mutex_dev);
665 }
666 private->mtk_drm_bound = false;
667 private->drm_master = false;
668 private->drm = NULL;
669 }
670
671 static const struct component_master_ops mtk_drm_ops = {
672 .bind = mtk_drm_bind,
673 .unbind = mtk_drm_unbind,
674 };
675
676 static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
677 { .compatible = "mediatek,mt8167-disp-aal",
678 .data = (void *)MTK_DISP_AAL},
679 { .compatible = "mediatek,mt8173-disp-aal",
680 .data = (void *)MTK_DISP_AAL},
681 { .compatible = "mediatek,mt8183-disp-aal",
682 .data = (void *)MTK_DISP_AAL},
683 { .compatible = "mediatek,mt8192-disp-aal",
684 .data = (void *)MTK_DISP_AAL},
685 { .compatible = "mediatek,mt8167-disp-ccorr",
686 .data = (void *)MTK_DISP_CCORR },
687 { .compatible = "mediatek,mt8183-disp-ccorr",
688 .data = (void *)MTK_DISP_CCORR },
689 { .compatible = "mediatek,mt8192-disp-ccorr",
690 .data = (void *)MTK_DISP_CCORR },
691 { .compatible = "mediatek,mt2701-disp-color",
692 .data = (void *)MTK_DISP_COLOR },
693 { .compatible = "mediatek,mt8167-disp-color",
694 .data = (void *)MTK_DISP_COLOR },
695 { .compatible = "mediatek,mt8173-disp-color",
696 .data = (void *)MTK_DISP_COLOR },
697 { .compatible = "mediatek,mt8167-disp-dither",
698 .data = (void *)MTK_DISP_DITHER },
699 { .compatible = "mediatek,mt8183-disp-dither",
700 .data = (void *)MTK_DISP_DITHER },
701 { .compatible = "mediatek,mt8195-disp-dsc",
702 .data = (void *)MTK_DISP_DSC },
703 { .compatible = "mediatek,mt8167-disp-gamma",
704 .data = (void *)MTK_DISP_GAMMA, },
705 { .compatible = "mediatek,mt8173-disp-gamma",
706 .data = (void *)MTK_DISP_GAMMA, },
707 { .compatible = "mediatek,mt8183-disp-gamma",
708 .data = (void *)MTK_DISP_GAMMA, },
709 { .compatible = "mediatek,mt8195-disp-merge",
710 .data = (void *)MTK_DISP_MERGE },
711 { .compatible = "mediatek,mt2701-disp-mutex",
712 .data = (void *)MTK_DISP_MUTEX },
713 { .compatible = "mediatek,mt2712-disp-mutex",
714 .data = (void *)MTK_DISP_MUTEX },
715 { .compatible = "mediatek,mt8167-disp-mutex",
716 .data = (void *)MTK_DISP_MUTEX },
717 { .compatible = "mediatek,mt8173-disp-mutex",
718 .data = (void *)MTK_DISP_MUTEX },
719 { .compatible = "mediatek,mt8183-disp-mutex",
720 .data = (void *)MTK_DISP_MUTEX },
721 { .compatible = "mediatek,mt8186-disp-mutex",
722 .data = (void *)MTK_DISP_MUTEX },
723 { .compatible = "mediatek,mt8188-disp-mutex",
724 .data = (void *)MTK_DISP_MUTEX },
725 { .compatible = "mediatek,mt8192-disp-mutex",
726 .data = (void *)MTK_DISP_MUTEX },
727 { .compatible = "mediatek,mt8195-disp-mutex",
728 .data = (void *)MTK_DISP_MUTEX },
729 { .compatible = "mediatek,mt8173-disp-od",
730 .data = (void *)MTK_DISP_OD },
731 { .compatible = "mediatek,mt2701-disp-ovl",
732 .data = (void *)MTK_DISP_OVL },
733 { .compatible = "mediatek,mt8167-disp-ovl",
734 .data = (void *)MTK_DISP_OVL },
735 { .compatible = "mediatek,mt8173-disp-ovl",
736 .data = (void *)MTK_DISP_OVL },
737 { .compatible = "mediatek,mt8183-disp-ovl",
738 .data = (void *)MTK_DISP_OVL },
739 { .compatible = "mediatek,mt8192-disp-ovl",
740 .data = (void *)MTK_DISP_OVL },
741 { .compatible = "mediatek,mt8195-disp-ovl",
742 .data = (void *)MTK_DISP_OVL },
743 { .compatible = "mediatek,mt8183-disp-ovl-2l",
744 .data = (void *)MTK_DISP_OVL_2L },
745 { .compatible = "mediatek,mt8192-disp-ovl-2l",
746 .data = (void *)MTK_DISP_OVL_2L },
747 { .compatible = "mediatek,mt8192-disp-postmask",
748 .data = (void *)MTK_DISP_POSTMASK },
749 { .compatible = "mediatek,mt2701-disp-pwm",
750 .data = (void *)MTK_DISP_BLS },
751 { .compatible = "mediatek,mt8167-disp-pwm",
752 .data = (void *)MTK_DISP_PWM },
753 { .compatible = "mediatek,mt8173-disp-pwm",
754 .data = (void *)MTK_DISP_PWM },
755 { .compatible = "mediatek,mt2701-disp-rdma",
756 .data = (void *)MTK_DISP_RDMA },
757 { .compatible = "mediatek,mt8167-disp-rdma",
758 .data = (void *)MTK_DISP_RDMA },
759 { .compatible = "mediatek,mt8173-disp-rdma",
760 .data = (void *)MTK_DISP_RDMA },
761 { .compatible = "mediatek,mt8183-disp-rdma",
762 .data = (void *)MTK_DISP_RDMA },
763 { .compatible = "mediatek,mt8195-disp-rdma",
764 .data = (void *)MTK_DISP_RDMA },
765 { .compatible = "mediatek,mt8173-disp-ufoe",
766 .data = (void *)MTK_DISP_UFOE },
767 { .compatible = "mediatek,mt8173-disp-wdma",
768 .data = (void *)MTK_DISP_WDMA },
769 { .compatible = "mediatek,mt2701-dpi",
770 .data = (void *)MTK_DPI },
771 { .compatible = "mediatek,mt8167-dsi",
772 .data = (void *)MTK_DSI },
773 { .compatible = "mediatek,mt8173-dpi",
774 .data = (void *)MTK_DPI },
775 { .compatible = "mediatek,mt8183-dpi",
776 .data = (void *)MTK_DPI },
777 { .compatible = "mediatek,mt8186-dpi",
778 .data = (void *)MTK_DPI },
779 { .compatible = "mediatek,mt8188-dp-intf",
780 .data = (void *)MTK_DP_INTF },
781 { .compatible = "mediatek,mt8192-dpi",
782 .data = (void *)MTK_DPI },
783 { .compatible = "mediatek,mt8195-dp-intf",
784 .data = (void *)MTK_DP_INTF },
785 { .compatible = "mediatek,mt2701-dsi",
786 .data = (void *)MTK_DSI },
787 { .compatible = "mediatek,mt8173-dsi",
788 .data = (void *)MTK_DSI },
789 { .compatible = "mediatek,mt8183-dsi",
790 .data = (void *)MTK_DSI },
791 { .compatible = "mediatek,mt8186-dsi",
792 .data = (void *)MTK_DSI },
793 { }
794 };
795
mtk_drm_probe(struct platform_device * pdev)796 static int mtk_drm_probe(struct platform_device *pdev)
797 {
798 struct device *dev = &pdev->dev;
799 struct device_node *phandle = dev->parent->of_node;
800 const struct of_device_id *of_id;
801 struct mtk_drm_private *private;
802 struct device_node *node;
803 struct component_match *match = NULL;
804 struct platform_device *ovl_adaptor;
805 int ret;
806 int i;
807
808 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
809 if (!private)
810 return -ENOMEM;
811
812 private->mmsys_dev = dev->parent;
813 if (!private->mmsys_dev) {
814 dev_err(dev, "Failed to get MMSYS device\n");
815 return -ENODEV;
816 }
817
818 of_id = of_match_node(mtk_drm_of_ids, phandle);
819 if (!of_id)
820 return -ENODEV;
821
822 private->data = of_id->data;
823
824 private->all_drm_private = devm_kmalloc_array(dev, private->data->mmsys_dev_num,
825 sizeof(*private->all_drm_private),
826 GFP_KERNEL);
827 if (!private->all_drm_private)
828 return -ENOMEM;
829
830 /* Bringup ovl_adaptor */
831 if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR)) {
832 ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor",
833 PLATFORM_DEVID_AUTO,
834 (void *)private->mmsys_dev,
835 sizeof(*private->mmsys_dev));
836 private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR].dev = &ovl_adaptor->dev;
837 mtk_ddp_comp_init(NULL, &private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR],
838 DDP_COMPONENT_DRM_OVL_ADAPTOR);
839 component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev);
840 }
841
842 /* Iterate over sibling DISP function blocks */
843 for_each_child_of_node(phandle->parent, node) {
844 const struct of_device_id *of_id;
845 enum mtk_ddp_comp_type comp_type;
846 int comp_id;
847
848 of_id = of_match_node(mtk_ddp_comp_dt_ids, node);
849 if (!of_id)
850 continue;
851
852 if (!of_device_is_available(node)) {
853 dev_dbg(dev, "Skipping disabled component %pOF\n",
854 node);
855 continue;
856 }
857
858 comp_type = (enum mtk_ddp_comp_type)(uintptr_t)of_id->data;
859
860 if (comp_type == MTK_DISP_MUTEX) {
861 int id;
862
863 id = of_alias_get_id(node, "mutex");
864 if (id < 0 || id == private->data->mmsys_id) {
865 private->mutex_node = of_node_get(node);
866 dev_dbg(dev, "get mutex for mmsys %d", private->data->mmsys_id);
867 }
868 continue;
869 }
870
871 comp_id = mtk_ddp_comp_get_id(node, comp_type);
872 if (comp_id < 0) {
873 dev_warn(dev, "Skipping unknown component %pOF\n",
874 node);
875 continue;
876 }
877
878 if (!mtk_drm_find_mmsys_comp(private, comp_id))
879 continue;
880
881 private->comp_node[comp_id] = of_node_get(node);
882
883 /*
884 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
885 * blocks have separate component platform drivers and initialize their own
886 * DDP component structure. The others are initialized here.
887 */
888 if (comp_type == MTK_DISP_AAL ||
889 comp_type == MTK_DISP_CCORR ||
890 comp_type == MTK_DISP_COLOR ||
891 comp_type == MTK_DISP_GAMMA ||
892 comp_type == MTK_DISP_MERGE ||
893 comp_type == MTK_DISP_OVL ||
894 comp_type == MTK_DISP_OVL_2L ||
895 comp_type == MTK_DISP_OVL_ADAPTOR ||
896 comp_type == MTK_DISP_RDMA ||
897 comp_type == MTK_DP_INTF ||
898 comp_type == MTK_DPI ||
899 comp_type == MTK_DSI) {
900 dev_info(dev, "Adding component match for %pOF\n",
901 node);
902 drm_of_component_match_add(dev, &match, component_compare_of,
903 node);
904 }
905
906 ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id);
907 if (ret) {
908 of_node_put(node);
909 goto err_node;
910 }
911 }
912
913 if (!private->mutex_node) {
914 dev_err(dev, "Failed to find disp-mutex node\n");
915 ret = -ENODEV;
916 goto err_node;
917 }
918
919 pm_runtime_enable(dev);
920
921 platform_set_drvdata(pdev, private);
922
923 ret = component_master_add_with_match(dev, &mtk_drm_ops, match);
924 if (ret)
925 goto err_pm;
926
927 return 0;
928
929 err_pm:
930 pm_runtime_disable(dev);
931 err_node:
932 of_node_put(private->mutex_node);
933 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++)
934 of_node_put(private->comp_node[i]);
935 return ret;
936 }
937
mtk_drm_remove(struct platform_device * pdev)938 static void mtk_drm_remove(struct platform_device *pdev)
939 {
940 struct mtk_drm_private *private = platform_get_drvdata(pdev);
941 int i;
942
943 component_master_del(&pdev->dev, &mtk_drm_ops);
944 pm_runtime_disable(&pdev->dev);
945 of_node_put(private->mutex_node);
946 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++)
947 of_node_put(private->comp_node[i]);
948 }
949
mtk_drm_shutdown(struct platform_device * pdev)950 static void mtk_drm_shutdown(struct platform_device *pdev)
951 {
952 struct mtk_drm_private *private = platform_get_drvdata(pdev);
953
954 drm_atomic_helper_shutdown(private->drm);
955 }
956
mtk_drm_sys_prepare(struct device * dev)957 static int mtk_drm_sys_prepare(struct device *dev)
958 {
959 struct mtk_drm_private *private = dev_get_drvdata(dev);
960 struct drm_device *drm = private->drm;
961
962 if (private->drm_master)
963 return drm_mode_config_helper_suspend(drm);
964 else
965 return 0;
966 }
967
mtk_drm_sys_complete(struct device * dev)968 static void mtk_drm_sys_complete(struct device *dev)
969 {
970 struct mtk_drm_private *private = dev_get_drvdata(dev);
971 struct drm_device *drm = private->drm;
972 int ret = 0;
973
974 if (private->drm_master)
975 ret = drm_mode_config_helper_resume(drm);
976 if (ret)
977 dev_err(dev, "Failed to resume\n");
978 }
979
980 static const struct dev_pm_ops mtk_drm_pm_ops = {
981 .prepare = mtk_drm_sys_prepare,
982 .complete = mtk_drm_sys_complete,
983 };
984
985 static struct platform_driver mtk_drm_platform_driver = {
986 .probe = mtk_drm_probe,
987 .remove_new = mtk_drm_remove,
988 .shutdown = mtk_drm_shutdown,
989 .driver = {
990 .name = "mediatek-drm",
991 .pm = &mtk_drm_pm_ops,
992 },
993 };
994
995 static struct platform_driver * const mtk_drm_drivers[] = {
996 &mtk_disp_aal_driver,
997 &mtk_disp_ccorr_driver,
998 &mtk_disp_color_driver,
999 &mtk_disp_gamma_driver,
1000 &mtk_disp_merge_driver,
1001 &mtk_disp_ovl_adaptor_driver,
1002 &mtk_disp_ovl_driver,
1003 &mtk_disp_rdma_driver,
1004 &mtk_dpi_driver,
1005 &mtk_drm_platform_driver,
1006 &mtk_dsi_driver,
1007 &mtk_ethdr_driver,
1008 &mtk_mdp_rdma_driver,
1009 };
1010
mtk_drm_init(void)1011 static int __init mtk_drm_init(void)
1012 {
1013 return platform_register_drivers(mtk_drm_drivers,
1014 ARRAY_SIZE(mtk_drm_drivers));
1015 }
1016
mtk_drm_exit(void)1017 static void __exit mtk_drm_exit(void)
1018 {
1019 platform_unregister_drivers(mtk_drm_drivers,
1020 ARRAY_SIZE(mtk_drm_drivers));
1021 }
1022
1023 module_init(mtk_drm_init);
1024 module_exit(mtk_drm_exit);
1025
1026 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>");
1027 MODULE_DESCRIPTION("Mediatek SoC DRM driver");
1028 MODULE_LICENSE("GPL v2");
1029