xref: /openbmc/linux/sound/soc/mediatek/mt8188/mt8188-afe-clk.c (revision 4d75f5c664195b970e1cd2fd25b65b5eff257a0a)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * mt8188-afe-clk.c  --  MediaTek 8188 afe clock ctrl
4  *
5  * Copyright (c) 2022 MediaTek Inc.
6  * Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
7  *         Trevor Wu <trevor.wu@mediatek.com>
8  *         Chun-Chia Chiu <chun-chia.chiu@mediatek.com>
9  */
10 
11 #include <linux/clk.h>
12 
13 #include "mt8188-afe-common.h"
14 #include "mt8188-afe-clk.h"
15 #include "mt8188-audsys-clk.h"
16 #include "mt8188-reg.h"
17 
18 static const char *aud_clks[MT8188_CLK_NUM] = {
19 	/* xtal */
20 	[MT8188_CLK_XTAL_26M] = "clk26m",
21 
22 	/* pll */
23 	[MT8188_CLK_APMIXED_APLL1] = "apll1",
24 	[MT8188_CLK_APMIXED_APLL2] = "apll2",
25 
26 	/* divider */
27 	[MT8188_CLK_TOP_APLL1_D4] = "apll1_d4",
28 	[MT8188_CLK_TOP_APLL2_D4] = "apll2_d4",
29 	[MT8188_CLK_TOP_APLL12_DIV0] = "apll12_div0",
30 	[MT8188_CLK_TOP_APLL12_DIV1] = "apll12_div1",
31 	[MT8188_CLK_TOP_APLL12_DIV2] = "apll12_div2",
32 	[MT8188_CLK_TOP_APLL12_DIV3] = "apll12_div3",
33 	[MT8188_CLK_TOP_APLL12_DIV4] = "apll12_div4",
34 	[MT8188_CLK_TOP_APLL12_DIV9] = "apll12_div9",
35 
36 	/* mux */
37 	[MT8188_CLK_TOP_A1SYS_HP_SEL] = "top_a1sys_hp",
38 	[MT8188_CLK_TOP_A2SYS_SEL] = "top_a2sys",
39 	[MT8188_CLK_TOP_AUD_IEC_SEL] = "top_aud_iec",
40 	[MT8188_CLK_TOP_AUD_INTBUS_SEL] = "top_aud_intbus",
41 	[MT8188_CLK_TOP_AUDIO_H_SEL] = "top_audio_h",
42 	[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL] = "top_audio_local_bus",
43 	[MT8188_CLK_TOP_DPTX_M_SEL] = "top_dptx",
44 	[MT8188_CLK_TOP_I2SO1_M_SEL] = "top_i2so1",
45 	[MT8188_CLK_TOP_I2SO2_M_SEL] = "top_i2so2",
46 	[MT8188_CLK_TOP_I2SI1_M_SEL] = "top_i2si1",
47 	[MT8188_CLK_TOP_I2SI2_M_SEL] = "top_i2si2",
48 
49 	/* clock gate */
50 	[MT8188_CLK_ADSP_AUDIO_26M] = "adsp_audio_26m",
51 	/* afe clock gate */
52 	[MT8188_CLK_AUD_AFE] = "aud_afe",
53 	[MT8188_CLK_AUD_APLL1_TUNER] = "aud_apll1_tuner",
54 	[MT8188_CLK_AUD_APLL2_TUNER] = "aud_apll2_tuner",
55 	[MT8188_CLK_AUD_APLL] = "aud_apll",
56 	[MT8188_CLK_AUD_APLL2] = "aud_apll2",
57 	[MT8188_CLK_AUD_DAC] = "aud_dac",
58 	[MT8188_CLK_AUD_ADC] = "aud_adc",
59 	[MT8188_CLK_AUD_DAC_HIRES] = "aud_dac_hires",
60 	[MT8188_CLK_AUD_A1SYS_HP] = "aud_a1sys_hp",
61 	[MT8188_CLK_AUD_AFE_DMIC1] = "aud_afe_dmic1",
62 	[MT8188_CLK_AUD_AFE_DMIC2] = "aud_afe_dmic2",
63 	[MT8188_CLK_AUD_AFE_DMIC3] = "aud_afe_dmic3",
64 	[MT8188_CLK_AUD_AFE_DMIC4] = "aud_afe_dmic4",
65 	[MT8188_CLK_AUD_ADC_HIRES] = "aud_adc_hires",
66 	[MT8188_CLK_AUD_DMIC_HIRES1] = "aud_dmic_hires1",
67 	[MT8188_CLK_AUD_DMIC_HIRES2] = "aud_dmic_hires2",
68 	[MT8188_CLK_AUD_DMIC_HIRES3] = "aud_dmic_hires3",
69 	[MT8188_CLK_AUD_DMIC_HIRES4] = "aud_dmic_hires4",
70 	[MT8188_CLK_AUD_I2SIN] = "aud_i2sin",
71 	[MT8188_CLK_AUD_TDM_IN] = "aud_tdm_in",
72 	[MT8188_CLK_AUD_I2S_OUT] = "aud_i2s_out",
73 	[MT8188_CLK_AUD_TDM_OUT] = "aud_tdm_out",
74 	[MT8188_CLK_AUD_HDMI_OUT] = "aud_hdmi_out",
75 	[MT8188_CLK_AUD_ASRC11] = "aud_asrc11",
76 	[MT8188_CLK_AUD_ASRC12] = "aud_asrc12",
77 	[MT8188_CLK_AUD_A1SYS] = "aud_a1sys",
78 	[MT8188_CLK_AUD_A2SYS] = "aud_a2sys",
79 	[MT8188_CLK_AUD_PCMIF] = "aud_pcmif",
80 	[MT8188_CLK_AUD_MEMIF_UL1] = "aud_memif_ul1",
81 	[MT8188_CLK_AUD_MEMIF_UL2] = "aud_memif_ul2",
82 	[MT8188_CLK_AUD_MEMIF_UL3] = "aud_memif_ul3",
83 	[MT8188_CLK_AUD_MEMIF_UL4] = "aud_memif_ul4",
84 	[MT8188_CLK_AUD_MEMIF_UL5] = "aud_memif_ul5",
85 	[MT8188_CLK_AUD_MEMIF_UL6] = "aud_memif_ul6",
86 	[MT8188_CLK_AUD_MEMIF_UL8] = "aud_memif_ul8",
87 	[MT8188_CLK_AUD_MEMIF_UL9] = "aud_memif_ul9",
88 	[MT8188_CLK_AUD_MEMIF_UL10] = "aud_memif_ul10",
89 	[MT8188_CLK_AUD_MEMIF_DL2] = "aud_memif_dl2",
90 	[MT8188_CLK_AUD_MEMIF_DL3] = "aud_memif_dl3",
91 	[MT8188_CLK_AUD_MEMIF_DL6] = "aud_memif_dl6",
92 	[MT8188_CLK_AUD_MEMIF_DL7] = "aud_memif_dl7",
93 	[MT8188_CLK_AUD_MEMIF_DL8] = "aud_memif_dl8",
94 	[MT8188_CLK_AUD_MEMIF_DL10] = "aud_memif_dl10",
95 	[MT8188_CLK_AUD_MEMIF_DL11] = "aud_memif_dl11",
96 };
97 
98 struct mt8188_afe_tuner_cfg {
99 	unsigned int id;
100 	int apll_div_reg;
101 	unsigned int apll_div_shift;
102 	unsigned int apll_div_maskbit;
103 	unsigned int apll_div_default;
104 	int ref_ck_sel_reg;
105 	unsigned int ref_ck_sel_shift;
106 	unsigned int ref_ck_sel_maskbit;
107 	unsigned int ref_ck_sel_default;
108 	int tuner_en_reg;
109 	unsigned int tuner_en_shift;
110 	unsigned int tuner_en_maskbit;
111 	int upper_bound_reg;
112 	unsigned int upper_bound_shift;
113 	unsigned int upper_bound_maskbit;
114 	unsigned int upper_bound_default;
115 	spinlock_t ctrl_lock; /* lock for apll tuner ctrl*/
116 	int ref_cnt;
117 };
118 
119 static struct mt8188_afe_tuner_cfg
120 	mt8188_afe_tuner_cfgs[MT8188_AUD_PLL_NUM] = {
121 	[MT8188_AUD_PLL1] = {
122 		.id = MT8188_AUD_PLL1,
123 		.apll_div_reg = AFE_APLL_TUNER_CFG,
124 		.apll_div_shift = 4,
125 		.apll_div_maskbit = 0xf,
126 		.apll_div_default = 0x7,
127 		.ref_ck_sel_reg = AFE_APLL_TUNER_CFG,
128 		.ref_ck_sel_shift = 1,
129 		.ref_ck_sel_maskbit = 0x3,
130 		.ref_ck_sel_default = 0x2,
131 		.tuner_en_reg = AFE_APLL_TUNER_CFG,
132 		.tuner_en_shift = 0,
133 		.tuner_en_maskbit = 0x1,
134 		.upper_bound_reg = AFE_APLL_TUNER_CFG,
135 		.upper_bound_shift = 8,
136 		.upper_bound_maskbit = 0xff,
137 		.upper_bound_default = 0x3,
138 	},
139 	[MT8188_AUD_PLL2] = {
140 		.id = MT8188_AUD_PLL2,
141 		.apll_div_reg = AFE_APLL_TUNER_CFG1,
142 		.apll_div_shift = 4,
143 		.apll_div_maskbit = 0xf,
144 		.apll_div_default = 0x7,
145 		.ref_ck_sel_reg = AFE_APLL_TUNER_CFG1,
146 		.ref_ck_sel_shift = 1,
147 		.ref_ck_sel_maskbit = 0x3,
148 		.ref_ck_sel_default = 0x1,
149 		.tuner_en_reg = AFE_APLL_TUNER_CFG1,
150 		.tuner_en_shift = 0,
151 		.tuner_en_maskbit = 0x1,
152 		.upper_bound_reg = AFE_APLL_TUNER_CFG1,
153 		.upper_bound_shift = 8,
154 		.upper_bound_maskbit = 0xff,
155 		.upper_bound_default = 0x3,
156 	},
157 	[MT8188_AUD_PLL3] = {
158 		.id = MT8188_AUD_PLL3,
159 		.apll_div_reg = AFE_EARC_APLL_TUNER_CFG,
160 		.apll_div_shift = 4,
161 		.apll_div_maskbit = 0x3f,
162 		.apll_div_default = 0x3,
163 		.ref_ck_sel_reg = AFE_EARC_APLL_TUNER_CFG,
164 		.ref_ck_sel_shift = 24,
165 		.ref_ck_sel_maskbit = 0x3,
166 		.ref_ck_sel_default = 0x0,
167 		.tuner_en_reg = AFE_EARC_APLL_TUNER_CFG,
168 		.tuner_en_shift = 0,
169 		.tuner_en_maskbit = 0x1,
170 		.upper_bound_reg = AFE_EARC_APLL_TUNER_CFG,
171 		.upper_bound_shift = 12,
172 		.upper_bound_maskbit = 0xff,
173 		.upper_bound_default = 0x4,
174 	},
175 	[MT8188_AUD_PLL4] = {
176 		.id = MT8188_AUD_PLL4,
177 		.apll_div_reg = AFE_SPDIFIN_APLL_TUNER_CFG,
178 		.apll_div_shift = 4,
179 		.apll_div_maskbit = 0x3f,
180 		.apll_div_default = 0x7,
181 		.ref_ck_sel_reg = AFE_SPDIFIN_APLL_TUNER_CFG1,
182 		.ref_ck_sel_shift = 8,
183 		.ref_ck_sel_maskbit = 0x1,
184 		.ref_ck_sel_default = 0,
185 		.tuner_en_reg = AFE_SPDIFIN_APLL_TUNER_CFG,
186 		.tuner_en_shift = 0,
187 		.tuner_en_maskbit = 0x1,
188 		.upper_bound_reg = AFE_SPDIFIN_APLL_TUNER_CFG,
189 		.upper_bound_shift = 12,
190 		.upper_bound_maskbit = 0xff,
191 		.upper_bound_default = 0x4,
192 	},
193 	[MT8188_AUD_PLL5] = {
194 		.id = MT8188_AUD_PLL5,
195 		.apll_div_reg = AFE_LINEIN_APLL_TUNER_CFG,
196 		.apll_div_shift = 4,
197 		.apll_div_maskbit = 0x3f,
198 		.apll_div_default = 0x3,
199 		.ref_ck_sel_reg = AFE_LINEIN_APLL_TUNER_CFG,
200 		.ref_ck_sel_shift = 24,
201 		.ref_ck_sel_maskbit = 0x1,
202 		.ref_ck_sel_default = 0,
203 		.tuner_en_reg = AFE_LINEIN_APLL_TUNER_CFG,
204 		.tuner_en_shift = 0,
205 		.tuner_en_maskbit = 0x1,
206 		.upper_bound_reg = AFE_LINEIN_APLL_TUNER_CFG,
207 		.upper_bound_shift = 12,
208 		.upper_bound_maskbit = 0xff,
209 		.upper_bound_default = 0x4,
210 	},
211 };
212 
mt8188_afe_found_apll_tuner(unsigned int id)213 static struct mt8188_afe_tuner_cfg *mt8188_afe_found_apll_tuner(unsigned int id)
214 {
215 	if (id >= MT8188_AUD_PLL_NUM)
216 		return NULL;
217 
218 	return &mt8188_afe_tuner_cfgs[id];
219 }
220 
mt8188_afe_init_apll_tuner(unsigned int id)221 static int mt8188_afe_init_apll_tuner(unsigned int id)
222 {
223 	struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id);
224 
225 	if (!cfg)
226 		return -EINVAL;
227 
228 	cfg->ref_cnt = 0;
229 	spin_lock_init(&cfg->ctrl_lock);
230 
231 	return 0;
232 }
233 
mt8188_afe_setup_apll_tuner(struct mtk_base_afe * afe,unsigned int id)234 static int mt8188_afe_setup_apll_tuner(struct mtk_base_afe *afe, unsigned int id)
235 {
236 	const struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id);
237 
238 	if (!cfg)
239 		return -EINVAL;
240 
241 	regmap_update_bits(afe->regmap,
242 			   cfg->apll_div_reg,
243 			   cfg->apll_div_maskbit << cfg->apll_div_shift,
244 			   cfg->apll_div_default << cfg->apll_div_shift);
245 
246 	regmap_update_bits(afe->regmap,
247 			   cfg->ref_ck_sel_reg,
248 			   cfg->ref_ck_sel_maskbit << cfg->ref_ck_sel_shift,
249 			   cfg->ref_ck_sel_default << cfg->ref_ck_sel_shift);
250 
251 	regmap_update_bits(afe->regmap,
252 			   cfg->upper_bound_reg,
253 			   cfg->upper_bound_maskbit << cfg->upper_bound_shift,
254 			   cfg->upper_bound_default << cfg->upper_bound_shift);
255 
256 	return 0;
257 }
258 
mt8188_afe_enable_tuner_clk(struct mtk_base_afe * afe,unsigned int id)259 static int mt8188_afe_enable_tuner_clk(struct mtk_base_afe *afe,
260 				       unsigned int id)
261 {
262 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
263 
264 	switch (id) {
265 	case MT8188_AUD_PLL1:
266 		mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL]);
267 		mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL1_TUNER]);
268 		break;
269 	case MT8188_AUD_PLL2:
270 		mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2]);
271 		mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2_TUNER]);
272 		break;
273 	default:
274 		return -EINVAL;
275 	}
276 
277 	return 0;
278 }
279 
mt8188_afe_disable_tuner_clk(struct mtk_base_afe * afe,unsigned int id)280 static int mt8188_afe_disable_tuner_clk(struct mtk_base_afe *afe,
281 					unsigned int id)
282 {
283 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
284 
285 	switch (id) {
286 	case MT8188_AUD_PLL1:
287 		mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL1_TUNER]);
288 		mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL]);
289 		break;
290 	case MT8188_AUD_PLL2:
291 		mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2_TUNER]);
292 		mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2]);
293 		break;
294 	default:
295 		return -EINVAL;
296 	}
297 
298 	return 0;
299 }
300 
mt8188_afe_enable_apll_tuner(struct mtk_base_afe * afe,unsigned int id)301 static int mt8188_afe_enable_apll_tuner(struct mtk_base_afe *afe, unsigned int id)
302 {
303 	struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id);
304 	unsigned long flags;
305 	int ret;
306 
307 	if (!cfg)
308 		return -EINVAL;
309 
310 	ret = mt8188_afe_setup_apll_tuner(afe, id);
311 	if (ret)
312 		return ret;
313 
314 	ret = mt8188_afe_enable_tuner_clk(afe, id);
315 	if (ret)
316 		return ret;
317 
318 	spin_lock_irqsave(&cfg->ctrl_lock, flags);
319 
320 	cfg->ref_cnt++;
321 	if (cfg->ref_cnt == 1)
322 		regmap_update_bits(afe->regmap,
323 				   cfg->tuner_en_reg,
324 				   cfg->tuner_en_maskbit << cfg->tuner_en_shift,
325 				   BIT(cfg->tuner_en_shift));
326 
327 	spin_unlock_irqrestore(&cfg->ctrl_lock, flags);
328 
329 	return 0;
330 }
331 
mt8188_afe_disable_apll_tuner(struct mtk_base_afe * afe,unsigned int id)332 static int mt8188_afe_disable_apll_tuner(struct mtk_base_afe *afe, unsigned int id)
333 {
334 	struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id);
335 	unsigned long flags;
336 	int ret;
337 
338 	if (!cfg)
339 		return -EINVAL;
340 
341 	spin_lock_irqsave(&cfg->ctrl_lock, flags);
342 
343 	cfg->ref_cnt--;
344 	if (cfg->ref_cnt == 0)
345 		regmap_update_bits(afe->regmap,
346 				   cfg->tuner_en_reg,
347 				   cfg->tuner_en_maskbit << cfg->tuner_en_shift,
348 				   0 << cfg->tuner_en_shift);
349 	else if (cfg->ref_cnt < 0)
350 		cfg->ref_cnt = 0;
351 
352 	spin_unlock_irqrestore(&cfg->ctrl_lock, flags);
353 
354 	ret = mt8188_afe_disable_tuner_clk(afe, id);
355 	if (ret)
356 		return ret;
357 
358 	return 0;
359 }
360 
mt8188_afe_get_mclk_source_clk_id(int sel)361 int mt8188_afe_get_mclk_source_clk_id(int sel)
362 {
363 	switch (sel) {
364 	case MT8188_MCK_SEL_26M:
365 		return MT8188_CLK_XTAL_26M;
366 	case MT8188_MCK_SEL_APLL1:
367 		return MT8188_CLK_APMIXED_APLL1;
368 	case MT8188_MCK_SEL_APLL2:
369 		return MT8188_CLK_APMIXED_APLL2;
370 	default:
371 		return -EINVAL;
372 	}
373 }
374 
mt8188_afe_get_mclk_source_rate(struct mtk_base_afe * afe,int apll)375 int mt8188_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll)
376 {
377 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
378 	int clk_id = mt8188_afe_get_mclk_source_clk_id(apll);
379 
380 	if (clk_id < 0) {
381 		dev_dbg(afe->dev, "invalid clk id\n");
382 		return 0;
383 	}
384 
385 	return clk_get_rate(afe_priv->clk[clk_id]);
386 }
387 
mt8188_afe_get_default_mclk_source_by_rate(int rate)388 int mt8188_afe_get_default_mclk_source_by_rate(int rate)
389 {
390 	return ((rate % 8000) == 0) ?
391 		MT8188_MCK_SEL_APLL1 : MT8188_MCK_SEL_APLL2;
392 }
393 
mt8188_get_apll_by_rate(struct mtk_base_afe * afe,int rate)394 int mt8188_get_apll_by_rate(struct mtk_base_afe *afe, int rate)
395 {
396 	return ((rate % 8000) == 0) ? MT8188_AUD_PLL1 : MT8188_AUD_PLL2;
397 }
398 
mt8188_get_apll_by_name(struct mtk_base_afe * afe,const char * name)399 int mt8188_get_apll_by_name(struct mtk_base_afe *afe, const char *name)
400 {
401 	if (strcmp(name, APLL1_W_NAME) == 0)
402 		return MT8188_AUD_PLL1;
403 
404 	return MT8188_AUD_PLL2;
405 }
406 
mt8188_afe_init_clock(struct mtk_base_afe * afe)407 int mt8188_afe_init_clock(struct mtk_base_afe *afe)
408 {
409 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
410 	int i, ret;
411 
412 	ret = mt8188_audsys_clk_register(afe);
413 	if (ret) {
414 		dev_err(afe->dev, "register audsys clk fail %d\n", ret);
415 		return ret;
416 	}
417 
418 	afe_priv->clk =
419 		devm_kcalloc(afe->dev, MT8188_CLK_NUM, sizeof(*afe_priv->clk),
420 			     GFP_KERNEL);
421 	if (!afe_priv->clk)
422 		return -ENOMEM;
423 
424 	for (i = 0; i < MT8188_CLK_NUM; i++) {
425 		afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
426 		if (IS_ERR(afe_priv->clk[i])) {
427 			dev_err(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
428 				__func__, aud_clks[i],
429 				PTR_ERR(afe_priv->clk[i]));
430 			return PTR_ERR(afe_priv->clk[i]);
431 		}
432 	}
433 
434 	/* initial tuner */
435 	for (i = 0; i < MT8188_AUD_PLL_NUM; i++) {
436 		ret = mt8188_afe_init_apll_tuner(i);
437 		if (ret) {
438 			dev_info(afe->dev, "%s(), init apll_tuner%d failed",
439 				 __func__, (i + 1));
440 			return -EINVAL;
441 		}
442 	}
443 
444 	return 0;
445 }
446 
mt8188_afe_enable_clk(struct mtk_base_afe * afe,struct clk * clk)447 int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)
448 {
449 	int ret;
450 
451 	if (clk) {
452 		ret = clk_prepare_enable(clk);
453 		if (ret) {
454 			dev_dbg(afe->dev, "%s(), failed to enable clk\n",
455 				__func__);
456 			return ret;
457 		}
458 	} else {
459 		dev_dbg(afe->dev, "NULL clk\n");
460 	}
461 	return 0;
462 }
463 EXPORT_SYMBOL_GPL(mt8188_afe_enable_clk);
464 
mt8188_afe_disable_clk(struct mtk_base_afe * afe,struct clk * clk)465 void mt8188_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)
466 {
467 	if (clk)
468 		clk_disable_unprepare(clk);
469 	else
470 		dev_dbg(afe->dev, "NULL clk\n");
471 }
472 EXPORT_SYMBOL_GPL(mt8188_afe_disable_clk);
473 
mt8188_afe_set_clk_rate(struct mtk_base_afe * afe,struct clk * clk,unsigned int rate)474 int mt8188_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
475 			    unsigned int rate)
476 {
477 	int ret;
478 
479 	if (clk) {
480 		ret = clk_set_rate(clk, rate);
481 		if (ret) {
482 			dev_dbg(afe->dev, "%s(), failed to set clk rate\n",
483 				__func__);
484 			return ret;
485 		}
486 	}
487 
488 	return 0;
489 }
490 
mt8188_afe_set_clk_parent(struct mtk_base_afe * afe,struct clk * clk,struct clk * parent)491 int mt8188_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
492 			      struct clk *parent)
493 {
494 	int ret;
495 
496 	if (clk && parent) {
497 		ret = clk_set_parent(clk, parent);
498 		if (ret) {
499 			dev_dbg(afe->dev, "%s(), failed to set clk parent %d\n",
500 				__func__, ret);
501 			return ret;
502 		}
503 	}
504 
505 	return 0;
506 }
507 
get_top_cg_reg(unsigned int cg_type)508 static unsigned int get_top_cg_reg(unsigned int cg_type)
509 {
510 	switch (cg_type) {
511 	case MT8188_TOP_CG_A1SYS_TIMING:
512 	case MT8188_TOP_CG_A2SYS_TIMING:
513 	case MT8188_TOP_CG_26M_TIMING:
514 		return ASYS_TOP_CON;
515 	default:
516 		return 0;
517 	}
518 }
519 
get_top_cg_mask(unsigned int cg_type)520 static unsigned int get_top_cg_mask(unsigned int cg_type)
521 {
522 	switch (cg_type) {
523 	case MT8188_TOP_CG_A1SYS_TIMING:
524 		return ASYS_TOP_CON_A1SYS_TIMING_ON;
525 	case MT8188_TOP_CG_A2SYS_TIMING:
526 		return ASYS_TOP_CON_A2SYS_TIMING_ON;
527 	case MT8188_TOP_CG_26M_TIMING:
528 		return ASYS_TOP_CON_26M_TIMING_ON;
529 	default:
530 		return 0;
531 	}
532 }
533 
get_top_cg_on_val(unsigned int cg_type)534 static unsigned int get_top_cg_on_val(unsigned int cg_type)
535 {
536 	switch (cg_type) {
537 	case MT8188_TOP_CG_A1SYS_TIMING:
538 	case MT8188_TOP_CG_A2SYS_TIMING:
539 	case MT8188_TOP_CG_26M_TIMING:
540 		return get_top_cg_mask(cg_type);
541 	default:
542 		return 0;
543 	}
544 }
545 
get_top_cg_off_val(unsigned int cg_type)546 static unsigned int get_top_cg_off_val(unsigned int cg_type)
547 {
548 	switch (cg_type) {
549 	case MT8188_TOP_CG_A1SYS_TIMING:
550 	case MT8188_TOP_CG_A2SYS_TIMING:
551 	case MT8188_TOP_CG_26M_TIMING:
552 		return 0;
553 	default:
554 		return get_top_cg_mask(cg_type);
555 	}
556 }
557 
mt8188_afe_enable_top_cg(struct mtk_base_afe * afe,unsigned int cg_type)558 static int mt8188_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
559 {
560 	unsigned int reg = get_top_cg_reg(cg_type);
561 	unsigned int mask = get_top_cg_mask(cg_type);
562 	unsigned int val = get_top_cg_on_val(cg_type);
563 
564 	regmap_update_bits(afe->regmap, reg, mask, val);
565 
566 	return 0;
567 }
568 
mt8188_afe_disable_top_cg(struct mtk_base_afe * afe,unsigned int cg_type)569 static int mt8188_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
570 {
571 	unsigned int reg = get_top_cg_reg(cg_type);
572 	unsigned int mask = get_top_cg_mask(cg_type);
573 	unsigned int val = get_top_cg_off_val(cg_type);
574 
575 	regmap_update_bits(afe->regmap, reg, mask, val);
576 
577 	return 0;
578 }
579 
mt8188_afe_enable_reg_rw_clk(struct mtk_base_afe * afe)580 int mt8188_afe_enable_reg_rw_clk(struct mtk_base_afe *afe)
581 {
582 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
583 
584 	/* bus clock for AFE external access, like DRAM */
585 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL]);
586 
587 	/* bus clock for AFE internal access, like AFE SRAM */
588 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUD_INTBUS_SEL]);
589 
590 	/* audio 26m clock source */
591 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_ADSP_AUDIO_26M]);
592 
593 	/* AFE hw clock */
594 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE]);
595 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS_HP]);
596 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
597 
598 	return 0;
599 }
600 
mt8188_afe_disable_reg_rw_clk(struct mtk_base_afe * afe)601 int mt8188_afe_disable_reg_rw_clk(struct mtk_base_afe *afe)
602 {
603 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
604 
605 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
606 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS_HP]);
607 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE]);
608 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_ADSP_AUDIO_26M]);
609 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUD_INTBUS_SEL]);
610 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL]);
611 
612 	return 0;
613 }
614 
mt8188_afe_enable_afe_on(struct mtk_base_afe * afe)615 static int mt8188_afe_enable_afe_on(struct mtk_base_afe *afe)
616 {
617 	regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
618 	return 0;
619 }
620 
mt8188_afe_disable_afe_on(struct mtk_base_afe * afe)621 static int mt8188_afe_disable_afe_on(struct mtk_base_afe *afe)
622 {
623 	regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);
624 	return 0;
625 }
626 
mt8188_afe_enable_a1sys(struct mtk_base_afe * afe)627 static int mt8188_afe_enable_a1sys(struct mtk_base_afe *afe)
628 {
629 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
630 	int ret;
631 
632 	ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
633 	if (ret)
634 		return ret;
635 
636 	return mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING);
637 }
638 
mt8188_afe_disable_a1sys(struct mtk_base_afe * afe)639 static int mt8188_afe_disable_a1sys(struct mtk_base_afe *afe)
640 {
641 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
642 
643 	mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING);
644 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
645 	return 0;
646 }
647 
mt8188_afe_enable_a2sys(struct mtk_base_afe * afe)648 static int mt8188_afe_enable_a2sys(struct mtk_base_afe *afe)
649 {
650 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
651 	int ret;
652 
653 	ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]);
654 	if (ret)
655 		return ret;
656 
657 	return mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING);
658 }
659 
mt8188_afe_disable_a2sys(struct mtk_base_afe * afe)660 static int mt8188_afe_disable_a2sys(struct mtk_base_afe *afe)
661 {
662 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
663 
664 	mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING);
665 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]);
666 	return 0;
667 }
668 
mt8188_apll1_enable(struct mtk_base_afe * afe)669 int mt8188_apll1_enable(struct mtk_base_afe *afe)
670 {
671 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
672 	int ret;
673 
674 	ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);
675 	if (ret)
676 		return ret;
677 
678 	ret = mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL],
679 					afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);
680 	if (ret)
681 		goto err_clk_parent;
682 
683 	ret = mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL1);
684 	if (ret)
685 		goto err_apll_tuner;
686 
687 	ret = mt8188_afe_enable_a1sys(afe);
688 	if (ret)
689 		goto err_a1sys;
690 
691 	return 0;
692 
693 err_a1sys:
694 	mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL1);
695 err_apll_tuner:
696 	mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL],
697 				  afe_priv->clk[MT8188_CLK_XTAL_26M]);
698 err_clk_parent:
699 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);
700 
701 	return ret;
702 }
703 
mt8188_apll1_disable(struct mtk_base_afe * afe)704 int mt8188_apll1_disable(struct mtk_base_afe *afe)
705 {
706 	struct mt8188_afe_private *afe_priv = afe->platform_priv;
707 
708 	mt8188_afe_disable_a1sys(afe);
709 	mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL1);
710 	mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL],
711 				  afe_priv->clk[MT8188_CLK_XTAL_26M]);
712 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);
713 
714 	return 0;
715 }
716 
mt8188_apll2_enable(struct mtk_base_afe * afe)717 int mt8188_apll2_enable(struct mtk_base_afe *afe)
718 {
719 	int ret;
720 
721 	ret = mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL2);
722 	if (ret)
723 		return ret;
724 
725 	ret =  mt8188_afe_enable_a2sys(afe);
726 	if (ret)
727 		goto err_a2sys;
728 
729 	return 0;
730 err_a2sys:
731 	mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL2);
732 
733 	return ret;
734 }
735 
mt8188_apll2_disable(struct mtk_base_afe * afe)736 int mt8188_apll2_disable(struct mtk_base_afe *afe)
737 {
738 	mt8188_afe_disable_a2sys(afe);
739 	mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL2);
740 	return 0;
741 }
742 
mt8188_afe_enable_main_clock(struct mtk_base_afe * afe)743 int mt8188_afe_enable_main_clock(struct mtk_base_afe *afe)
744 {
745 	mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_26M_TIMING);
746 	mt8188_afe_enable_afe_on(afe);
747 	return 0;
748 }
749 
mt8188_afe_disable_main_clock(struct mtk_base_afe * afe)750 int mt8188_afe_disable_main_clock(struct mtk_base_afe *afe)
751 {
752 	mt8188_afe_disable_afe_on(afe);
753 	mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_26M_TIMING);
754 	return 0;
755 }
756