1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "amdgpu.h"
24 #include "amdgpu_ras.h"
25 #include "mmhub_v1_7.h"
26
27 #include "mmhub/mmhub_1_7_offset.h"
28 #include "mmhub/mmhub_1_7_sh_mask.h"
29 #include "vega10_enum.h"
30
31 #include "soc15_common.h"
32 #include "soc15.h"
33
34 #define regVM_L2_CNTL3_DEFAULT 0x80100007
35 #define regVM_L2_CNTL4_DEFAULT 0x000000c1
36
mmhub_v1_7_get_fb_location(struct amdgpu_device * adev)37 static u64 mmhub_v1_7_get_fb_location(struct amdgpu_device *adev)
38 {
39 u64 base = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE);
40 u64 top = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP);
41
42 base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
43 base <<= 24;
44
45 top &= MC_VM_FB_LOCATION_TOP__FB_TOP_MASK;
46 top <<= 24;
47
48 adev->gmc.fb_start = base;
49 adev->gmc.fb_end = top;
50
51 return base;
52 }
53
mmhub_v1_7_setup_vm_pt_regs(struct amdgpu_device * adev,uint32_t vmid,uint64_t page_table_base)54 static void mmhub_v1_7_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
55 uint64_t page_table_base)
56 {
57 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
58
59 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
60 hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base));
61
62 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
63 hub->ctx_addr_distance * vmid, upper_32_bits(page_table_base));
64 }
65
mmhub_v1_7_init_gart_aperture_regs(struct amdgpu_device * adev)66 static void mmhub_v1_7_init_gart_aperture_regs(struct amdgpu_device *adev)
67 {
68 uint64_t pt_base;
69
70 if (adev->gmc.pdb0_bo)
71 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo);
72 else
73 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
74
75 mmhub_v1_7_setup_vm_pt_regs(adev, 0, pt_base);
76
77 /* If use GART for FB translation, vmid0 page table covers both
78 * vram and system memory (gart)
79 */
80 if (adev->gmc.pdb0_bo) {
81 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
82 (u32)(adev->gmc.fb_start >> 12));
83 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
84 (u32)(adev->gmc.fb_start >> 44));
85
86 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
87 (u32)(adev->gmc.gart_end >> 12));
88 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
89 (u32)(adev->gmc.gart_end >> 44));
90
91 } else {
92 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
93 (u32)(adev->gmc.gart_start >> 12));
94 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
95 (u32)(adev->gmc.gart_start >> 44));
96
97 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
98 (u32)(adev->gmc.gart_end >> 12));
99 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
100 (u32)(adev->gmc.gart_end >> 44));
101 }
102 }
103
mmhub_v1_7_init_system_aperture_regs(struct amdgpu_device * adev)104 static void mmhub_v1_7_init_system_aperture_regs(struct amdgpu_device *adev)
105 {
106 uint64_t value;
107 uint32_t tmp;
108
109 /* Program the AGP BAR */
110 WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BASE, 0);
111 WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
112 WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
113
114 if (amdgpu_sriov_vf(adev))
115 return;
116
117 /* Program the system aperture low logical page number. */
118 WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR,
119 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
120
121 WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
122 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
123
124 /* In the case squeezing vram into GART aperture, we don't use
125 * FB aperture and AGP aperture. Disable them.
126 */
127 if (adev->gmc.pdb0_bo) {
128 WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, 0xFFFFFF);
129 WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, 0);
130 WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP, 0);
131 WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);
132 WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);
133 WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);
134 }
135
136 /* Set default page address. */
137 value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
138 WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
139 (u32)(value >> 12));
140 WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
141 (u32)(value >> 44));
142
143 /* Program "protection fault". */
144 WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
145 (u32)(adev->dummy_page_addr >> 12));
146 WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
147 (u32)((u64)adev->dummy_page_addr >> 44));
148
149 tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL2);
150 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
151 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
152 WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL2, tmp);
153 }
154
mmhub_v1_7_init_tlb_regs(struct amdgpu_device * adev)155 static void mmhub_v1_7_init_tlb_regs(struct amdgpu_device *adev)
156 {
157 uint32_t tmp;
158
159 /* Setup TLB control */
160 tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);
161
162 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
163 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
164 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
165 ENABLE_ADVANCED_DRIVER_MODEL, 1);
166 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
167 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
168 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
169 MTYPE, MTYPE_UC);/* XXX for emulation. */
170 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
171
172 WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp);
173 }
174
175 /* Set snoop bit for SDMA so that SDMA writes probe-invalidates RW lines */
mmhub_v1_7_init_snoop_override_regs(struct amdgpu_device * adev)176 static void mmhub_v1_7_init_snoop_override_regs(struct amdgpu_device *adev)
177 {
178 uint32_t tmp;
179 int i;
180 uint32_t distance = regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE -
181 regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE;
182
183 for (i = 0; i < 5; i++) { /* DAGB instances */
184 tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
185 regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE, i * distance);
186 tmp |= (1 << 15); /* SDMA client is BIT15 */
187 WREG32_SOC15_OFFSET(MMHUB, 0,
188 regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE, i * distance, tmp);
189
190 tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
191 regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE, i * distance);
192 tmp |= (1 << 15);
193 WREG32_SOC15_OFFSET(MMHUB, 0,
194 regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE, i * distance, tmp);
195 }
196
197 }
198
mmhub_v1_7_init_cache_regs(struct amdgpu_device * adev)199 static void mmhub_v1_7_init_cache_regs(struct amdgpu_device *adev)
200 {
201 uint32_t tmp;
202
203 if (amdgpu_sriov_vf(adev))
204 return;
205
206 /* Setup L2 cache */
207 tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL);
208 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
209 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
210 /* XXX for emulation, Refer to closed source code.*/
211 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
212 0);
213 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
214 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
215 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
216 WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL, tmp);
217
218 tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL2);
219 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
220 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
221 WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL2, tmp);
222
223 tmp = regVM_L2_CNTL3_DEFAULT;
224 if (adev->gmc.translate_further) {
225 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
226 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
227 L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
228 } else {
229 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
230 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
231 L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
232 }
233 WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL3, tmp);
234
235 tmp = regVM_L2_CNTL4_DEFAULT;
236 if (adev->gmc.xgmi.connected_to_cpu) {
237 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
238 VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
239 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
240 VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
241 } else {
242 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
243 VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
244 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
245 VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
246 }
247 WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL4, tmp);
248 }
249
mmhub_v1_7_enable_system_domain(struct amdgpu_device * adev)250 static void mmhub_v1_7_enable_system_domain(struct amdgpu_device *adev)
251 {
252 uint32_t tmp;
253
254 tmp = RREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL);
255 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
256 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
257 adev->gmc.vmid0_page_table_depth);
258 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,
259 adev->gmc.vmid0_page_table_block_size);
260 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
261 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
262 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL, tmp);
263 }
264
mmhub_v1_7_disable_identity_aperture(struct amdgpu_device * adev)265 static void mmhub_v1_7_disable_identity_aperture(struct amdgpu_device *adev)
266 {
267 if (amdgpu_sriov_vf(adev))
268 return;
269
270 WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
271 0XFFFFFFFF);
272 WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
273 0x0000000F);
274
275 WREG32_SOC15(MMHUB, 0,
276 regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
277 WREG32_SOC15(MMHUB, 0,
278 regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
279
280 WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
281 0);
282 WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
283 0);
284 }
285
mmhub_v1_7_setup_vmid_config(struct amdgpu_device * adev)286 static void mmhub_v1_7_setup_vmid_config(struct amdgpu_device *adev)
287 {
288 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
289 unsigned num_level, block_size;
290 uint32_t tmp;
291 int i;
292
293 num_level = adev->vm_manager.num_level;
294 block_size = adev->vm_manager.block_size;
295 if (adev->gmc.translate_further)
296 num_level -= 1;
297 else
298 block_size -= 9;
299
300 for (i = 0; i <= 14; i++) {
301 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL, i);
302 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
303 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
304 num_level);
305 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
306 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
307 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
308 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
309 1);
310 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
311 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
312 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
313 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
314 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
315 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
316 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
317 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
318 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
319 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
320 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
321 PAGE_TABLE_BLOCK_SIZE,
322 block_size);
323 /* On Aldebaran, XNACK can be enabled in the SQ per-process.
324 * Retry faults need to be enabled for that to work.
325 */
326 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
327 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
328 1);
329 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL,
330 i * hub->ctx_distance, tmp);
331 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
332 i * hub->ctx_addr_distance, 0);
333 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
334 i * hub->ctx_addr_distance, 0);
335 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
336 i * hub->ctx_addr_distance,
337 lower_32_bits(adev->vm_manager.max_pfn - 1));
338 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
339 i * hub->ctx_addr_distance,
340 upper_32_bits(adev->vm_manager.max_pfn - 1));
341 }
342 }
343
mmhub_v1_7_program_invalidation(struct amdgpu_device * adev)344 static void mmhub_v1_7_program_invalidation(struct amdgpu_device *adev)
345 {
346 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
347 unsigned i;
348
349 for (i = 0; i < 18; ++i) {
350 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
351 i * hub->eng_addr_distance, 0xffffffff);
352 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
353 i * hub->eng_addr_distance, 0x1f);
354 }
355 }
356
mmhub_v1_7_gart_enable(struct amdgpu_device * adev)357 static int mmhub_v1_7_gart_enable(struct amdgpu_device *adev)
358 {
359 /* GART Enable. */
360 mmhub_v1_7_init_gart_aperture_regs(adev);
361 mmhub_v1_7_init_system_aperture_regs(adev);
362 mmhub_v1_7_init_tlb_regs(adev);
363 mmhub_v1_7_init_cache_regs(adev);
364 mmhub_v1_7_init_snoop_override_regs(adev);
365
366 mmhub_v1_7_enable_system_domain(adev);
367 mmhub_v1_7_disable_identity_aperture(adev);
368 mmhub_v1_7_setup_vmid_config(adev);
369 mmhub_v1_7_program_invalidation(adev);
370
371 return 0;
372 }
373
mmhub_v1_7_gart_disable(struct amdgpu_device * adev)374 static void mmhub_v1_7_gart_disable(struct amdgpu_device *adev)
375 {
376 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
377 u32 tmp;
378 u32 i;
379
380 /* Disable all tables */
381 for (i = 0; i < 16; i++)
382 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_CNTL,
383 i * hub->ctx_distance, 0);
384
385 /* Setup TLB control */
386 tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);
387 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
388 tmp = REG_SET_FIELD(tmp,
389 MC_VM_MX_L1_TLB_CNTL,
390 ENABLE_ADVANCED_DRIVER_MODEL,
391 0);
392 WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp);
393
394 if (!amdgpu_sriov_vf(adev)) {
395 /* Setup L2 cache */
396 tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL);
397 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
398 WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL, tmp);
399 WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL3, 0);
400 }
401 }
402
403 /**
404 * mmhub_v1_7_set_fault_enable_default - update GART/VM fault handling
405 *
406 * @adev: amdgpu_device pointer
407 * @value: true redirects VM faults to the default page
408 */
mmhub_v1_7_set_fault_enable_default(struct amdgpu_device * adev,bool value)409 static void mmhub_v1_7_set_fault_enable_default(struct amdgpu_device *adev, bool value)
410 {
411 u32 tmp;
412
413 if (amdgpu_sriov_vf(adev))
414 return;
415
416 tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL);
417 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
418 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
419 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
420 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
421 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
422 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
423 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
424 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
425 tmp = REG_SET_FIELD(tmp,
426 VM_L2_PROTECTION_FAULT_CNTL,
427 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
428 value);
429 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
430 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
431 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
432 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
433 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
434 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
435 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
436 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
437 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
438 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
439 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
440 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
441 if (!value) {
442 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
443 CRASH_ON_NO_RETRY_FAULT, 1);
444 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
445 CRASH_ON_RETRY_FAULT, 1);
446 }
447
448 WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL, tmp);
449 }
450
mmhub_v1_7_init(struct amdgpu_device * adev)451 static void mmhub_v1_7_init(struct amdgpu_device *adev)
452 {
453 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
454
455 hub->ctx0_ptb_addr_lo32 =
456 SOC15_REG_OFFSET(MMHUB, 0,
457 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
458 hub->ctx0_ptb_addr_hi32 =
459 SOC15_REG_OFFSET(MMHUB, 0,
460 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
461 hub->vm_inv_eng0_req =
462 SOC15_REG_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_REQ);
463 hub->vm_inv_eng0_ack =
464 SOC15_REG_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ACK);
465 hub->vm_context0_cntl =
466 SOC15_REG_OFFSET(MMHUB, 0, regVM_CONTEXT0_CNTL);
467 hub->vm_l2_pro_fault_status =
468 SOC15_REG_OFFSET(MMHUB, 0, regVM_L2_PROTECTION_FAULT_STATUS);
469 hub->vm_l2_pro_fault_cntl =
470 SOC15_REG_OFFSET(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL);
471
472 hub->ctx_distance = regVM_CONTEXT1_CNTL - regVM_CONTEXT0_CNTL;
473 hub->ctx_addr_distance = regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
474 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
475 hub->eng_distance = regVM_INVALIDATE_ENG1_REQ - regVM_INVALIDATE_ENG0_REQ;
476 hub->eng_addr_distance = regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
477 regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
478
479 }
480
mmhub_v1_7_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)481 static void mmhub_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
482 bool enable)
483 {
484 uint32_t def, data, def1, data1, def2 = 0, data2 = 0;
485
486 def = data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG);
487
488 def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2);
489 def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2);
490
491 if (enable) {
492 data |= ATC_L2_MISC_CG__ENABLE_MASK;
493
494 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
495 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
496 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
497 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
498 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
499 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
500
501 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
502 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
503 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
504 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
505 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
506 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
507 } else {
508 data &= ~ATC_L2_MISC_CG__ENABLE_MASK;
509
510 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
511 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
512 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
513 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
514 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
515 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
516
517 data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
518 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
519 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
520 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
521 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
522 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
523 }
524
525 if (def != data)
526 WREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG, data);
527
528 if (def1 != data1)
529 WREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2, data1);
530
531 if (def2 != data2)
532 WREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2, data2);
533 }
534
mmhub_v1_7_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)535 static void mmhub_v1_7_update_medium_grain_light_sleep(struct amdgpu_device *adev,
536 bool enable)
537 {
538 uint32_t def, data;
539
540 def = data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG);
541
542 if (enable)
543 data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
544 else
545 data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
546
547 if (def != data)
548 WREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG, data);
549 }
550
mmhub_v1_7_set_clockgating(struct amdgpu_device * adev,enum amd_clockgating_state state)551 static int mmhub_v1_7_set_clockgating(struct amdgpu_device *adev,
552 enum amd_clockgating_state state)
553 {
554 if (amdgpu_sriov_vf(adev))
555 return 0;
556
557 /* Change state only if MCCG support is enabled through driver */
558 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)
559 mmhub_v1_7_update_medium_grain_clock_gating(adev,
560 state == AMD_CG_STATE_GATE);
561
562 /* Change state only if LS support is enabled through driver */
563 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)
564 mmhub_v1_7_update_medium_grain_light_sleep(adev,
565 state == AMD_CG_STATE_GATE);
566
567 return 0;
568 }
569
mmhub_v1_7_get_clockgating(struct amdgpu_device * adev,u64 * flags)570 static void mmhub_v1_7_get_clockgating(struct amdgpu_device *adev, u64 *flags)
571 {
572 int data, data1;
573
574 if (amdgpu_sriov_vf(adev))
575 *flags = 0;
576
577 data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG);
578
579 data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2);
580
581 /* AMD_CG_SUPPORT_MC_MGCG */
582 if ((data & ATC_L2_MISC_CG__ENABLE_MASK) &&
583 !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
584 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
585 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
586 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
587 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
588 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
589 *flags |= AMD_CG_SUPPORT_MC_MGCG;
590
591 /* AMD_CG_SUPPORT_MC_LS */
592 if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
593 *flags |= AMD_CG_SUPPORT_MC_LS;
594 }
595
596 static const struct soc15_ras_field_entry mmhub_v1_7_ras_fields[] = {
597 /* MMHUB Range 0 */
598 { "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
599 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
600 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
601 },
602 { "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
603 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
604 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
605 },
606 { "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
607 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
608 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
609 },
610 { "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
611 SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
612 SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_DED_COUNT),
613 },
614 { "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
615 SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
616 SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_DED_COUNT),
617 },
618 { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
619 SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
620 SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
621 },
622 { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
623 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
624 0, 0,
625 },
626 { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
627 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
628 0, 0,
629 },
630 { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
631 SOC15_REG_FIELD(MMEA0_EDC_CNT, IORD_CMDMEM_SED_COUNT),
632 0, 0,
633 },
634 { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
635 SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
636 0, 0,
637 },
638 { "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
639 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
640 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
641 },
642 { "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
643 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
644 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
645 },
646 { "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
647 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
648 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
649 },
650 { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
651 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
652 0, 0,
653 },
654 { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
655 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
656 0, 0,
657 },
658 { "MMEA0_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
659 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_SED_COUNT),
660 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_DED_COUNT),
661 },
662 { "MMEA0_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
663 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_SED_COUNT),
664 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_DED_COUNT),
665 },
666 { "MMEA0_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
667 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_SED_COUNT),
668 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_DED_COUNT),
669 },
670 { "MMEA0_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
671 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_SED_COUNT),
672 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_DED_COUNT),
673 },
674 { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
675 0, 0,
676 SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
677 },
678 { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
679 0, 0,
680 SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
681 },
682 { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
683 0, 0,
684 SOC15_REG_FIELD(MMEA0_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
685 },
686 { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
687 0, 0,
688 SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
689 },
690 { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
691 0, 0,
692 SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
693 },
694 { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
695 0, 0,
696 SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
697 },
698
699 /* MMHUB Range 1 */
700 { "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
701 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
702 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
703 },
704 { "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
705 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
706 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
707 },
708 { "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
709 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
710 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
711 },
712 { "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
713 SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
714 SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_DED_COUNT),
715 },
716 { "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
717 SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
718 SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_DED_COUNT),
719 },
720 { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
721 SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
722 SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
723 },
724 { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
725 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
726 0, 0,
727 },
728 { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
729 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
730 0, 0,
731 },
732 { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
733 SOC15_REG_FIELD(MMEA1_EDC_CNT, IORD_CMDMEM_SED_COUNT),
734 0, 0,
735 },
736 { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
737 SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
738 0, 0,
739 },
740 { "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
741 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
742 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
743 },
744 { "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
745 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
746 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
747 },
748 { "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
749 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
750 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
751 },
752 { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
753 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
754 0, 0,
755 },
756 { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
757 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
758 0, 0,
759 },
760 { "MMEA1_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
761 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_SED_COUNT),
762 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_DED_COUNT),
763 },
764 { "MMEA1_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
765 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_SED_COUNT),
766 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_DED_COUNT),
767 },
768 { "MMEA1_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
769 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_SED_COUNT),
770 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_DED_COUNT),
771 },
772 { "MMEA1_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
773 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_SED_COUNT),
774 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_DED_COUNT),
775 },
776 { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
777 0, 0,
778 SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
779 },
780 { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
781 0, 0,
782 SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
783 },
784 { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
785 0, 0,
786 SOC15_REG_FIELD(MMEA1_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
787 },
788 { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
789 0, 0,
790 SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
791 },
792 { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
793 0, 0,
794 SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
795 },
796 { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
797 0, 0,
798 SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
799 },
800
801 /* MMHAB Range 2*/
802 { "MMEA2_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
803 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
804 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
805 },
806 { "MMEA2_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
807 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
808 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
809 },
810 { "MMEA2_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
811 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
812 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
813 },
814 { "MMEA2_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
815 SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
816 SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_DED_COUNT),
817 },
818 { "MMEA2_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
819 SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
820 SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_DED_COUNT),
821 },
822 { "MMEA2_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
823 SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
824 SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
825 },
826 { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
827 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
828 0, 0,
829 },
830 { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
831 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
832 0, 0,
833 },
834 { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
835 SOC15_REG_FIELD(MMEA2_EDC_CNT, IORD_CMDMEM_SED_COUNT),
836 0, 0,
837 },
838 { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
839 SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
840 0, 0,
841 },
842 { "MMEA2_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
843 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
844 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
845 },
846 { "MMEA2_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
847 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
848 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
849 },
850 { "MMEA2_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
851 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
852 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
853 },
854 { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
855 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
856 0, 0,
857 },
858 { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
859 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
860 0, 0,
861 },
862 { "MMEA2_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
863 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_SED_COUNT),
864 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_DED_COUNT),
865 },
866 { "MMEA2_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
867 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_SED_COUNT),
868 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_DED_COUNT),
869 },
870 { "MMEA2_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
871 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_SED_COUNT),
872 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_DED_COUNT),
873 },
874 { "MMEA2_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
875 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_SED_COUNT),
876 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_DED_COUNT),
877 },
878 { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
879 0, 0,
880 SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
881 },
882 { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
883 0, 0,
884 SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
885 },
886 { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
887 0, 0,
888 SOC15_REG_FIELD(MMEA2_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
889 },
890 { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
891 0, 0,
892 SOC15_REG_FIELD(MMEA2_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
893 },
894 { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
895 0, 0,
896 SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
897 },
898 { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
899 0, 0,
900 SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
901 },
902
903 /* MMHUB Rang 3 */
904 { "MMEA3_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
905 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
906 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
907 },
908 { "MMEA3_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
909 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
910 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
911 },
912 { "MMEA3_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
913 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
914 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
915 },
916 { "MMEA3_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
917 SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
918 SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_DED_COUNT),
919 },
920 { "MMEA3_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
921 SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
922 SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_DED_COUNT),
923 },
924 { "MMEA3_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
925 SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
926 SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
927 },
928 { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
929 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
930 0, 0,
931 },
932 { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
933 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
934 0, 0,
935 },
936 { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
937 SOC15_REG_FIELD(MMEA3_EDC_CNT, IORD_CMDMEM_SED_COUNT),
938 0, 0,
939 },
940 { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
941 SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
942 0, 0,
943 },
944 { "MMEA3_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
945 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
946 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
947 },
948 { "MMEA3_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
949 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
950 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
951 },
952 { "MMEA3_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
953 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
954 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
955 },
956 { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
957 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
958 0, 0,
959 },
960 { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
961 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
962 0, 0,
963 },
964 { "MMEA3_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
965 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_SED_COUNT),
966 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_DED_COUNT),
967 },
968 { "MMEA3_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
969 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_SED_COUNT),
970 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_DED_COUNT),
971 },
972 { "MMEA3_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
973 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_SED_COUNT),
974 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_DED_COUNT),
975 },
976 { "MMEA3_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
977 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_SED_COUNT),
978 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_DED_COUNT),
979 },
980 { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
981 0, 0,
982 SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
983 },
984 { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
985 0, 0,
986 SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
987 },
988 { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
989 0, 0,
990 SOC15_REG_FIELD(MMEA3_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
991 },
992 { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
993 0, 0,
994 SOC15_REG_FIELD(MMEA3_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
995 },
996 { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
997 0, 0,
998 SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
999 },
1000 { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
1001 0, 0,
1002 SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1003 },
1004
1005 /* MMHUB Range 4 */
1006 { "MMEA4_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1007 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1008 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1009 },
1010 { "MMEA4_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1011 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1012 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1013 },
1014 { "MMEA4_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1015 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1016 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1017 },
1018 { "MMEA4_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1019 SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1020 SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1021 },
1022 { "MMEA4_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1023 SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1024 SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1025 },
1026 { "MMEA4_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1027 SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
1028 SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
1029 },
1030 { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1031 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1032 0, 0,
1033 },
1034 { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1035 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1036 0, 0,
1037 },
1038 { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1039 SOC15_REG_FIELD(MMEA4_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1040 0, 0,
1041 },
1042 { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1043 SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1044 0, 0,
1045 },
1046 { "MMEA4_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1047 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1048 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1049 },
1050 { "MMEA4_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1051 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1052 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1053 },
1054 { "MMEA4_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1055 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1056 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1057 },
1058 { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1059 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1060 0, 0,
1061 },
1062 { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1063 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1064 0, 0,
1065 },
1066 { "MMEA4_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1067 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1068 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1069 },
1070 { "MMEA4_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1071 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1072 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1073 },
1074 { "MMEA4_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1075 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1076 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1077 },
1078 { "MMEA4_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1079 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1080 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1081 },
1082 { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1083 0, 0,
1084 SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1085 },
1086 { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1087 0, 0,
1088 SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1089 },
1090 { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1091 0, 0,
1092 SOC15_REG_FIELD(MMEA4_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1093 },
1094 { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1095 0, 0,
1096 SOC15_REG_FIELD(MMEA4_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1097 },
1098 { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1099 0, 0,
1100 SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1101 },
1102 { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1103 0, 0,
1104 SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1105 },
1106
1107 /* MMHUAB Range 5 */
1108 { "MMEA5_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1109 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1110 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1111 },
1112 { "MMEA5_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1113 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1114 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1115 },
1116 { "MMEA5_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1117 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1118 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1119 },
1120 { "MMEA5_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1121 SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1122 SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1123 },
1124 { "MMEA5_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1125 SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1126 SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1127 },
1128 { "MMEA5_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1129 SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
1130 SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
1131 },
1132 { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1133 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1134 0, 0,
1135 },
1136 { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1137 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1138 0, 0,
1139 },
1140 { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1141 SOC15_REG_FIELD(MMEA5_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1142 0, 0,
1143 },
1144 { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1145 SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1146 0, 0,
1147 },
1148 { "MMEA5_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1149 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1150 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1151 },
1152 { "MMEA5_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1153 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1154 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1155 },
1156 { "MMEA5_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1157 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1158 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1159 },
1160 { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1161 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1162 0, 0,
1163 },
1164 { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1165 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1166 0, 0,
1167 },
1168 { "MMEA5_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1169 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1170 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1171 },
1172 { "MMEA5_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1173 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1174 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1175 },
1176 { "MMEA5_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1177 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1178 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1179 },
1180 { "MMEA5_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1181 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1182 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1183 },
1184 { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1185 0, 0,
1186 SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1187 },
1188 { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1189 0, 0,
1190 SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1191 },
1192 { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1193 0, 0,
1194 SOC15_REG_FIELD(MMEA5_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1195 },
1196 { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1197 0, 0,
1198 SOC15_REG_FIELD(MMEA5_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1199 },
1200 { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1201 0, 0,
1202 SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1203 },
1204 { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1205 0, 0,
1206 SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1207 },
1208 };
1209
1210 static const struct soc15_reg_entry mmhub_v1_7_edc_cnt_regs[] = {
1211 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), 0, 0, 0 },
1212 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), 0, 0, 0 },
1213 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), 0, 0, 0 },
1214 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), 0, 0, 0 },
1215 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), 0, 0, 0 },
1216 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), 0, 0, 0 },
1217 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), 0, 0, 0 },
1218 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), 0, 0, 0 },
1219 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), 0, 0, 0 },
1220 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), 0, 0, 0 },
1221 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), 0, 0, 0 },
1222 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), 0, 0, 0 },
1223 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), 0, 0, 0 },
1224 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), 0, 0, 0 },
1225 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), 0, 0, 0 },
1226 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), 0, 0, 0 },
1227 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), 0, 0, 0 },
1228 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), 0, 0, 0 },
1229 };
1230
mmhub_v1_7_get_ras_error_count(struct amdgpu_device * adev,const struct soc15_reg_entry * reg,uint32_t value,uint32_t * sec_count,uint32_t * ded_count)1231 static int mmhub_v1_7_get_ras_error_count(struct amdgpu_device *adev,
1232 const struct soc15_reg_entry *reg,
1233 uint32_t value,
1234 uint32_t *sec_count,
1235 uint32_t *ded_count)
1236 {
1237 uint32_t i;
1238 uint32_t sec_cnt, ded_cnt;
1239
1240 for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ras_fields); i++) {
1241 if(mmhub_v1_7_ras_fields[i].reg_offset != reg->reg_offset)
1242 continue;
1243
1244 sec_cnt = (value &
1245 mmhub_v1_7_ras_fields[i].sec_count_mask) >>
1246 mmhub_v1_7_ras_fields[i].sec_count_shift;
1247 if (sec_cnt) {
1248 dev_info(adev->dev, "MMHUB SubBlock %s, SEC %d\n",
1249 mmhub_v1_7_ras_fields[i].name,
1250 sec_cnt);
1251 *sec_count += sec_cnt;
1252 }
1253
1254 ded_cnt = (value &
1255 mmhub_v1_7_ras_fields[i].ded_count_mask) >>
1256 mmhub_v1_7_ras_fields[i].ded_count_shift;
1257 if (ded_cnt) {
1258 dev_info(adev->dev, "MMHUB SubBlock %s, DED %d\n",
1259 mmhub_v1_7_ras_fields[i].name,
1260 ded_cnt);
1261 *ded_count += ded_cnt;
1262 }
1263 }
1264
1265 return 0;
1266 }
1267
mmhub_v1_7_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)1268 static void mmhub_v1_7_query_ras_error_count(struct amdgpu_device *adev,
1269 void *ras_error_status)
1270 {
1271 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
1272 uint32_t sec_count = 0, ded_count = 0;
1273 uint32_t i;
1274 uint32_t reg_value;
1275
1276 err_data->ue_count = 0;
1277 err_data->ce_count = 0;
1278
1279 for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_edc_cnt_regs); i++) {
1280 reg_value =
1281 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i]));
1282 if (reg_value)
1283 mmhub_v1_7_get_ras_error_count(adev, &mmhub_v1_7_edc_cnt_regs[i],
1284 reg_value, &sec_count, &ded_count);
1285 }
1286
1287 err_data->ce_count += sec_count;
1288 err_data->ue_count += ded_count;
1289 }
1290
mmhub_v1_7_reset_ras_error_count(struct amdgpu_device * adev)1291 static void mmhub_v1_7_reset_ras_error_count(struct amdgpu_device *adev)
1292 {
1293 uint32_t i;
1294
1295 /* write 0 to reset the edc counters */
1296 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) {
1297 for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_edc_cnt_regs); i++)
1298 WREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i]), 0);
1299 }
1300 }
1301
1302 static const struct soc15_reg_entry mmhub_v1_7_ea_err_status_regs[] = {
1303 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_ERR_STATUS), 0, 0, 0 },
1304 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_ERR_STATUS), 0, 0, 0 },
1305 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_ERR_STATUS), 0, 0, 0 },
1306 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_ERR_STATUS), 0, 0, 0 },
1307 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_ERR_STATUS), 0, 0, 0 },
1308 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_ERR_STATUS), 0, 0, 0 },
1309 };
1310
mmhub_v1_7_query_ras_error_status(struct amdgpu_device * adev)1311 static void mmhub_v1_7_query_ras_error_status(struct amdgpu_device *adev)
1312 {
1313 int i;
1314 uint32_t reg_value;
1315
1316 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB))
1317 return;
1318
1319 for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ea_err_status_regs); i++) {
1320 reg_value =
1321 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_ea_err_status_regs[i]));
1322 if (REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_STATUS) ||
1323 REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_WRRSP_STATUS) ||
1324 REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
1325 dev_warn(adev->dev, "MMHUB EA err detected at instance: %d, status: 0x%x!\n",
1326 i, reg_value);
1327 }
1328 }
1329 }
1330
mmhub_v1_7_reset_ras_error_status(struct amdgpu_device * adev)1331 static void mmhub_v1_7_reset_ras_error_status(struct amdgpu_device *adev)
1332 {
1333 int i;
1334 uint32_t reg_value;
1335
1336 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB))
1337 return;
1338
1339 for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ea_err_status_regs); i++) {
1340 reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(
1341 mmhub_v1_7_ea_err_status_regs[i]));
1342 reg_value = REG_SET_FIELD(reg_value, MMEA0_ERR_STATUS,
1343 CLEAR_ERROR_STATUS, 0x01);
1344 WREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_ea_err_status_regs[i]),
1345 reg_value);
1346 }
1347 }
1348
1349 struct amdgpu_ras_block_hw_ops mmhub_v1_7_ras_hw_ops = {
1350 .query_ras_error_count = mmhub_v1_7_query_ras_error_count,
1351 .reset_ras_error_count = mmhub_v1_7_reset_ras_error_count,
1352 .query_ras_error_status = mmhub_v1_7_query_ras_error_status,
1353 .reset_ras_error_status = mmhub_v1_7_reset_ras_error_status,
1354 };
1355
1356 struct amdgpu_mmhub_ras mmhub_v1_7_ras = {
1357 .ras_block = {
1358 .hw_ops = &mmhub_v1_7_ras_hw_ops,
1359 },
1360 };
1361
1362 const struct amdgpu_mmhub_funcs mmhub_v1_7_funcs = {
1363 .get_fb_location = mmhub_v1_7_get_fb_location,
1364 .init = mmhub_v1_7_init,
1365 .gart_enable = mmhub_v1_7_gart_enable,
1366 .set_fault_enable_default = mmhub_v1_7_set_fault_enable_default,
1367 .gart_disable = mmhub_v1_7_gart_disable,
1368 .set_clockgating = mmhub_v1_7_set_clockgating,
1369 .get_clockgating = mmhub_v1_7_get_clockgating,
1370 .setup_vm_pt_regs = mmhub_v1_7_setup_vm_pt_regs,
1371 };
1372