1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /* Copyright (c) 2017, Mellanox Technologies inc. All rights reserved. */
3
4 #include "mlx5_core.h"
5 #include "en.h"
6 #include "ipsec.h"
7 #include "lib/crypto.h"
8 #include "fs_core.h"
9 #include "eswitch.h"
10
11 enum {
12 MLX5_IPSEC_ASO_REMOVE_FLOW_PKT_CNT_OFFSET,
13 MLX5_IPSEC_ASO_REMOVE_FLOW_SOFT_LFT_OFFSET,
14 };
15
mlx5_ipsec_device_caps(struct mlx5_core_dev * mdev)16 u32 mlx5_ipsec_device_caps(struct mlx5_core_dev *mdev)
17 {
18 u32 caps = 0;
19
20 if (!MLX5_CAP_GEN(mdev, ipsec_offload))
21 return 0;
22
23 if (!MLX5_CAP_GEN(mdev, log_max_dek))
24 return 0;
25
26 if (!(MLX5_CAP_GEN_64(mdev, general_obj_types) &
27 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC))
28 return 0;
29
30 if (!MLX5_CAP_FLOWTABLE_NIC_TX(mdev, ipsec_encrypt) ||
31 !MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ipsec_decrypt))
32 return 0;
33
34 if (!MLX5_CAP_IPSEC(mdev, ipsec_crypto_esp_aes_gcm_128_encrypt) ||
35 !MLX5_CAP_IPSEC(mdev, ipsec_crypto_esp_aes_gcm_128_decrypt))
36 return 0;
37
38 if (MLX5_CAP_IPSEC(mdev, ipsec_crypto_offload) &&
39 MLX5_CAP_ETH(mdev, insert_trailer) && MLX5_CAP_ETH(mdev, swp))
40 caps |= MLX5_IPSEC_CAP_CRYPTO;
41
42 if (MLX5_CAP_IPSEC(mdev, ipsec_full_offload) &&
43 (mdev->priv.steering->mode == MLX5_FLOW_STEERING_MODE_DMFS ||
44 (mdev->priv.steering->mode == MLX5_FLOW_STEERING_MODE_SMFS &&
45 is_mdev_legacy_mode(mdev)))) {
46 if (MLX5_CAP_FLOWTABLE_NIC_TX(mdev,
47 reformat_add_esp_trasport) &&
48 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
49 reformat_del_esp_trasport) &&
50 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, decap))
51 caps |= MLX5_IPSEC_CAP_PACKET_OFFLOAD;
52
53 if (IS_ENABLED(CONFIG_MLX5_CLS_ACT) &&
54 ((MLX5_CAP_FLOWTABLE_NIC_TX(mdev, ignore_flow_level) &&
55 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ignore_flow_level)) ||
56 MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, ignore_flow_level)))
57 caps |= MLX5_IPSEC_CAP_PRIO;
58
59 if (MLX5_CAP_FLOWTABLE_NIC_TX(mdev,
60 reformat_l2_to_l3_esp_tunnel) &&
61 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
62 reformat_l3_esp_tunnel_to_l2))
63 caps |= MLX5_IPSEC_CAP_TUNNEL;
64
65 if (MLX5_CAP_FLOWTABLE_NIC_TX(mdev,
66 reformat_add_esp_transport_over_udp) &&
67 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
68 reformat_del_esp_transport_over_udp))
69 caps |= MLX5_IPSEC_CAP_ESPINUDP;
70 }
71
72 if (mlx5_get_roce_state(mdev) &&
73 MLX5_CAP_GEN_2(mdev, flow_table_type_2_type) & MLX5_FT_NIC_RX_2_NIC_RX_RDMA &&
74 MLX5_CAP_GEN_2(mdev, flow_table_type_2_type) & MLX5_FT_NIC_TX_RDMA_2_NIC_TX)
75 caps |= MLX5_IPSEC_CAP_ROCE;
76
77 if (!caps)
78 return 0;
79
80 if (MLX5_CAP_IPSEC(mdev, ipsec_esn))
81 caps |= MLX5_IPSEC_CAP_ESN;
82
83 /* We can accommodate up to 2^24 different IPsec objects
84 * because we use up to 24 bit in flow table metadata
85 * to hold the IPsec Object unique handle.
86 */
87 WARN_ON_ONCE(MLX5_CAP_IPSEC(mdev, log_max_ipsec_offload) > 24);
88 return caps;
89 }
90 EXPORT_SYMBOL_GPL(mlx5_ipsec_device_caps);
91
mlx5e_ipsec_packet_setup(void * obj,u32 pdn,struct mlx5e_ipsec_sa_entry * sa_entry)92 static void mlx5e_ipsec_packet_setup(void *obj, u32 pdn,
93 struct mlx5e_ipsec_sa_entry *sa_entry)
94 {
95 struct mlx5_accel_esp_xfrm_attrs *attrs = &sa_entry->attrs;
96 void *aso_ctx;
97
98 aso_ctx = MLX5_ADDR_OF(ipsec_obj, obj, ipsec_aso);
99 if (attrs->replay_esn.trigger) {
100 MLX5_SET(ipsec_aso, aso_ctx, esn_event_arm, 1);
101
102 if (attrs->dir == XFRM_DEV_OFFLOAD_IN) {
103 MLX5_SET(ipsec_aso, aso_ctx, window_sz,
104 attrs->replay_esn.replay_window);
105 MLX5_SET(ipsec_aso, aso_ctx, mode,
106 MLX5_IPSEC_ASO_REPLAY_PROTECTION);
107 }
108 MLX5_SET(ipsec_aso, aso_ctx, mode_parameter,
109 attrs->replay_esn.esn);
110 }
111
112 /* ASO context */
113 MLX5_SET(ipsec_obj, obj, ipsec_aso_access_pd, pdn);
114 MLX5_SET(ipsec_obj, obj, full_offload, 1);
115 MLX5_SET(ipsec_aso, aso_ctx, valid, 1);
116 /* MLX5_IPSEC_ASO_REG_C_4_5 is type C register that is used
117 * in flow steering to perform matching against. Please be
118 * aware that this register was chosen arbitrary and can't
119 * be used in other places as long as IPsec packet offload
120 * active.
121 */
122 MLX5_SET(ipsec_obj, obj, aso_return_reg, MLX5_IPSEC_ASO_REG_C_4_5);
123 if (attrs->dir == XFRM_DEV_OFFLOAD_OUT) {
124 MLX5_SET(ipsec_aso, aso_ctx, mode, MLX5_IPSEC_ASO_INC_SN);
125 if (!attrs->replay_esn.trigger)
126 MLX5_SET(ipsec_aso, aso_ctx, mode_parameter,
127 sa_entry->esn_state.esn);
128 }
129
130 if (attrs->lft.hard_packet_limit != XFRM_INF) {
131 MLX5_SET(ipsec_aso, aso_ctx, remove_flow_pkt_cnt,
132 attrs->lft.hard_packet_limit);
133 MLX5_SET(ipsec_aso, aso_ctx, hard_lft_arm, 1);
134 }
135
136 if (attrs->lft.soft_packet_limit != XFRM_INF) {
137 MLX5_SET(ipsec_aso, aso_ctx, remove_flow_soft_lft,
138 attrs->lft.soft_packet_limit);
139
140 MLX5_SET(ipsec_aso, aso_ctx, soft_lft_arm, 1);
141 }
142 }
143
mlx5_create_ipsec_obj(struct mlx5e_ipsec_sa_entry * sa_entry)144 static int mlx5_create_ipsec_obj(struct mlx5e_ipsec_sa_entry *sa_entry)
145 {
146 struct mlx5_accel_esp_xfrm_attrs *attrs = &sa_entry->attrs;
147 struct mlx5_core_dev *mdev = mlx5e_ipsec_sa2dev(sa_entry);
148 struct aes_gcm_keymat *aes_gcm = &attrs->aes_gcm;
149 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
150 u32 in[MLX5_ST_SZ_DW(create_ipsec_obj_in)] = {};
151 void *obj, *salt_p, *salt_iv_p;
152 struct mlx5e_hw_objs *res;
153 int err;
154
155 obj = MLX5_ADDR_OF(create_ipsec_obj_in, in, ipsec_object);
156
157 /* salt and seq_iv */
158 salt_p = MLX5_ADDR_OF(ipsec_obj, obj, salt);
159 memcpy(salt_p, &aes_gcm->salt, sizeof(aes_gcm->salt));
160
161 MLX5_SET(ipsec_obj, obj, icv_length, MLX5_IPSEC_OBJECT_ICV_LEN_16B);
162 salt_iv_p = MLX5_ADDR_OF(ipsec_obj, obj, implicit_iv);
163 memcpy(salt_iv_p, &aes_gcm->seq_iv, sizeof(aes_gcm->seq_iv));
164 /* esn */
165 if (attrs->replay_esn.trigger) {
166 MLX5_SET(ipsec_obj, obj, esn_en, 1);
167 MLX5_SET(ipsec_obj, obj, esn_msb, attrs->replay_esn.esn_msb);
168 MLX5_SET(ipsec_obj, obj, esn_overlap, attrs->replay_esn.overlap);
169 }
170
171 MLX5_SET(ipsec_obj, obj, dekn, sa_entry->enc_key_id);
172
173 /* general object fields set */
174 MLX5_SET(general_obj_in_cmd_hdr, in, opcode,
175 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
176 MLX5_SET(general_obj_in_cmd_hdr, in, obj_type,
177 MLX5_GENERAL_OBJECT_TYPES_IPSEC);
178
179 res = &mdev->mlx5e_res.hw_objs;
180 if (attrs->type == XFRM_DEV_OFFLOAD_PACKET)
181 mlx5e_ipsec_packet_setup(obj, res->pdn, sa_entry);
182
183 err = mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out));
184 if (!err)
185 sa_entry->ipsec_obj_id =
186 MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
187
188 return err;
189 }
190
mlx5_destroy_ipsec_obj(struct mlx5e_ipsec_sa_entry * sa_entry)191 static void mlx5_destroy_ipsec_obj(struct mlx5e_ipsec_sa_entry *sa_entry)
192 {
193 struct mlx5_core_dev *mdev = mlx5e_ipsec_sa2dev(sa_entry);
194 u32 in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {};
195 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
196
197 MLX5_SET(general_obj_in_cmd_hdr, in, opcode,
198 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT);
199 MLX5_SET(general_obj_in_cmd_hdr, in, obj_type,
200 MLX5_GENERAL_OBJECT_TYPES_IPSEC);
201 MLX5_SET(general_obj_in_cmd_hdr, in, obj_id, sa_entry->ipsec_obj_id);
202
203 mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out));
204 }
205
mlx5_ipsec_create_sa_ctx(struct mlx5e_ipsec_sa_entry * sa_entry)206 int mlx5_ipsec_create_sa_ctx(struct mlx5e_ipsec_sa_entry *sa_entry)
207 {
208 struct aes_gcm_keymat *aes_gcm = &sa_entry->attrs.aes_gcm;
209 struct mlx5_core_dev *mdev = mlx5e_ipsec_sa2dev(sa_entry);
210 int err;
211
212 /* key */
213 err = mlx5_create_encryption_key(mdev, aes_gcm->aes_key,
214 aes_gcm->key_len / BITS_PER_BYTE,
215 MLX5_ACCEL_OBJ_IPSEC_KEY,
216 &sa_entry->enc_key_id);
217 if (err) {
218 mlx5_core_dbg(mdev, "Failed to create encryption key (err = %d)\n", err);
219 return err;
220 }
221
222 err = mlx5_create_ipsec_obj(sa_entry);
223 if (err) {
224 mlx5_core_dbg(mdev, "Failed to create IPsec object (err = %d)\n", err);
225 goto err_enc_key;
226 }
227
228 return 0;
229
230 err_enc_key:
231 mlx5_destroy_encryption_key(mdev, sa_entry->enc_key_id);
232 return err;
233 }
234
mlx5_ipsec_free_sa_ctx(struct mlx5e_ipsec_sa_entry * sa_entry)235 void mlx5_ipsec_free_sa_ctx(struct mlx5e_ipsec_sa_entry *sa_entry)
236 {
237 struct mlx5_core_dev *mdev = mlx5e_ipsec_sa2dev(sa_entry);
238
239 mlx5_destroy_ipsec_obj(sa_entry);
240 mlx5_destroy_encryption_key(mdev, sa_entry->enc_key_id);
241 }
242
mlx5_modify_ipsec_obj(struct mlx5e_ipsec_sa_entry * sa_entry,const struct mlx5_accel_esp_xfrm_attrs * attrs)243 static int mlx5_modify_ipsec_obj(struct mlx5e_ipsec_sa_entry *sa_entry,
244 const struct mlx5_accel_esp_xfrm_attrs *attrs)
245 {
246 struct mlx5_core_dev *mdev = mlx5e_ipsec_sa2dev(sa_entry);
247 u32 in[MLX5_ST_SZ_DW(modify_ipsec_obj_in)] = {};
248 u32 out[MLX5_ST_SZ_DW(query_ipsec_obj_out)];
249 u64 modify_field_select = 0;
250 u64 general_obj_types;
251 void *obj;
252 int err;
253
254 general_obj_types = MLX5_CAP_GEN_64(mdev, general_obj_types);
255 if (!(general_obj_types & MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC))
256 return -EINVAL;
257
258 /* general object fields set */
259 MLX5_SET(general_obj_in_cmd_hdr, in, opcode, MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
260 MLX5_SET(general_obj_in_cmd_hdr, in, obj_type, MLX5_GENERAL_OBJECT_TYPES_IPSEC);
261 MLX5_SET(general_obj_in_cmd_hdr, in, obj_id, sa_entry->ipsec_obj_id);
262 err = mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out));
263 if (err) {
264 mlx5_core_err(mdev, "Query IPsec object failed (Object id %d), err = %d\n",
265 sa_entry->ipsec_obj_id, err);
266 return err;
267 }
268
269 obj = MLX5_ADDR_OF(query_ipsec_obj_out, out, ipsec_object);
270 modify_field_select = MLX5_GET64(ipsec_obj, obj, modify_field_select);
271
272 /* esn */
273 if (!(modify_field_select & MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP) ||
274 !(modify_field_select & MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB))
275 return -EOPNOTSUPP;
276
277 obj = MLX5_ADDR_OF(modify_ipsec_obj_in, in, ipsec_object);
278 MLX5_SET64(ipsec_obj, obj, modify_field_select,
279 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP |
280 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB);
281 MLX5_SET(ipsec_obj, obj, esn_msb, attrs->replay_esn.esn_msb);
282 MLX5_SET(ipsec_obj, obj, esn_overlap, attrs->replay_esn.overlap);
283
284 /* general object fields set */
285 MLX5_SET(general_obj_in_cmd_hdr, in, opcode, MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
286
287 return mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out));
288 }
289
mlx5_accel_esp_modify_xfrm(struct mlx5e_ipsec_sa_entry * sa_entry,const struct mlx5_accel_esp_xfrm_attrs * attrs)290 void mlx5_accel_esp_modify_xfrm(struct mlx5e_ipsec_sa_entry *sa_entry,
291 const struct mlx5_accel_esp_xfrm_attrs *attrs)
292 {
293 int err;
294
295 err = mlx5_modify_ipsec_obj(sa_entry, attrs);
296 if (err)
297 return;
298
299 memcpy(&sa_entry->attrs, attrs, sizeof(sa_entry->attrs));
300 }
301
mlx5e_ipsec_aso_update(struct mlx5e_ipsec_sa_entry * sa_entry,struct mlx5_wqe_aso_ctrl_seg * data)302 static void mlx5e_ipsec_aso_update(struct mlx5e_ipsec_sa_entry *sa_entry,
303 struct mlx5_wqe_aso_ctrl_seg *data)
304 {
305 data->data_mask_mode = MLX5_ASO_DATA_MASK_MODE_BITWISE_64BIT << 6;
306 data->condition_1_0_operand = MLX5_ASO_ALWAYS_TRUE |
307 MLX5_ASO_ALWAYS_TRUE << 4;
308
309 mlx5e_ipsec_aso_query(sa_entry, data);
310 }
311
mlx5e_ipsec_update_esn_state(struct mlx5e_ipsec_sa_entry * sa_entry,u32 mode_param)312 static void mlx5e_ipsec_update_esn_state(struct mlx5e_ipsec_sa_entry *sa_entry,
313 u32 mode_param)
314 {
315 struct mlx5_accel_esp_xfrm_attrs attrs = {};
316 struct mlx5_wqe_aso_ctrl_seg data = {};
317
318 if (mode_param < MLX5E_IPSEC_ESN_SCOPE_MID) {
319 sa_entry->esn_state.esn_msb++;
320 sa_entry->esn_state.overlap = 0;
321 } else {
322 sa_entry->esn_state.overlap = 1;
323 }
324
325 mlx5e_ipsec_build_accel_xfrm_attrs(sa_entry, &attrs);
326
327 /* It is safe to execute the modify below unlocked since the only flows
328 * that could affect this HW object, are create, destroy and this work.
329 *
330 * Creation flow can't co-exist with this modify work, the destruction
331 * flow would cancel this work, and this work is a single entity that
332 * can't conflict with it self.
333 */
334 spin_unlock_bh(&sa_entry->x->lock);
335 mlx5_accel_esp_modify_xfrm(sa_entry, &attrs);
336 spin_lock_bh(&sa_entry->x->lock);
337
338 data.data_offset_condition_operand =
339 MLX5_IPSEC_ASO_REMOVE_FLOW_PKT_CNT_OFFSET;
340 data.bitwise_data = cpu_to_be64(BIT_ULL(54));
341 data.data_mask = data.bitwise_data;
342
343 mlx5e_ipsec_aso_update(sa_entry, &data);
344 }
345
mlx5e_ipsec_aso_update_hard(struct mlx5e_ipsec_sa_entry * sa_entry)346 static void mlx5e_ipsec_aso_update_hard(struct mlx5e_ipsec_sa_entry *sa_entry)
347 {
348 struct mlx5_wqe_aso_ctrl_seg data = {};
349
350 data.data_offset_condition_operand =
351 MLX5_IPSEC_ASO_REMOVE_FLOW_PKT_CNT_OFFSET;
352 data.bitwise_data = cpu_to_be64(BIT_ULL(57) + BIT_ULL(31));
353 data.data_mask = data.bitwise_data;
354 mlx5e_ipsec_aso_update(sa_entry, &data);
355 }
356
mlx5e_ipsec_aso_update_soft(struct mlx5e_ipsec_sa_entry * sa_entry,u32 val)357 static void mlx5e_ipsec_aso_update_soft(struct mlx5e_ipsec_sa_entry *sa_entry,
358 u32 val)
359 {
360 struct mlx5_wqe_aso_ctrl_seg data = {};
361
362 data.data_offset_condition_operand =
363 MLX5_IPSEC_ASO_REMOVE_FLOW_SOFT_LFT_OFFSET;
364 data.bitwise_data = cpu_to_be64(val);
365 data.data_mask = cpu_to_be64(U32_MAX);
366 mlx5e_ipsec_aso_update(sa_entry, &data);
367 }
368
mlx5e_ipsec_handle_limits(struct mlx5e_ipsec_sa_entry * sa_entry)369 static void mlx5e_ipsec_handle_limits(struct mlx5e_ipsec_sa_entry *sa_entry)
370 {
371 struct mlx5_accel_esp_xfrm_attrs *attrs = &sa_entry->attrs;
372 struct mlx5e_ipsec *ipsec = sa_entry->ipsec;
373 struct mlx5e_ipsec_aso *aso = ipsec->aso;
374 bool soft_arm, hard_arm;
375 u64 hard_cnt;
376
377 lockdep_assert_held(&sa_entry->x->lock);
378
379 soft_arm = !MLX5_GET(ipsec_aso, aso->ctx, soft_lft_arm);
380 hard_arm = !MLX5_GET(ipsec_aso, aso->ctx, hard_lft_arm);
381 if (!soft_arm && !hard_arm)
382 /* It is not lifetime event */
383 return;
384
385 hard_cnt = MLX5_GET(ipsec_aso, aso->ctx, remove_flow_pkt_cnt);
386 if (!hard_cnt || hard_arm) {
387 /* It is possible to see packet counter equal to zero without
388 * hard limit event armed. Such situation can be if packet
389 * decreased, while we handled soft limit event.
390 *
391 * However it will be HW/FW bug if hard limit event is raised
392 * and packet counter is not zero.
393 */
394 WARN_ON_ONCE(hard_arm && hard_cnt);
395
396 /* Notify about hard limit */
397 xfrm_state_check_expire(sa_entry->x);
398 return;
399 }
400
401 /* We are in soft limit event. */
402 if (!sa_entry->limits.soft_limit_hit &&
403 sa_entry->limits.round == attrs->lft.numb_rounds_soft) {
404 sa_entry->limits.soft_limit_hit = true;
405 /* Notify about soft limit */
406 xfrm_state_check_expire(sa_entry->x);
407
408 if (sa_entry->limits.round == attrs->lft.numb_rounds_hard)
409 goto hard;
410
411 if (attrs->lft.soft_packet_limit > BIT_ULL(31)) {
412 /* We cannot avoid a soft_value that might have the high
413 * bit set. For instance soft_value=2^31+1 cannot be
414 * adjusted to the low bit clear version of soft_value=1
415 * because it is too close to 0.
416 *
417 * Thus we have this corner case where we can hit the
418 * soft_limit with the high bit set, but cannot adjust
419 * the counter. Thus we set a temporary interrupt_value
420 * at least 2^30 away from here and do the adjustment
421 * then.
422 */
423 mlx5e_ipsec_aso_update_soft(sa_entry,
424 BIT_ULL(31) - BIT_ULL(30));
425 sa_entry->limits.fix_limit = true;
426 return;
427 }
428
429 sa_entry->limits.fix_limit = true;
430 }
431
432 hard:
433 if (sa_entry->limits.round == attrs->lft.numb_rounds_hard) {
434 mlx5e_ipsec_aso_update_soft(sa_entry, 0);
435 attrs->lft.soft_packet_limit = XFRM_INF;
436 return;
437 }
438
439 mlx5e_ipsec_aso_update_hard(sa_entry);
440 sa_entry->limits.round++;
441 if (sa_entry->limits.round == attrs->lft.numb_rounds_soft)
442 mlx5e_ipsec_aso_update_soft(sa_entry,
443 attrs->lft.soft_packet_limit);
444 if (sa_entry->limits.fix_limit) {
445 sa_entry->limits.fix_limit = false;
446 mlx5e_ipsec_aso_update_soft(sa_entry, BIT_ULL(31) - 1);
447 }
448 }
449
mlx5e_ipsec_handle_event(struct work_struct * _work)450 static void mlx5e_ipsec_handle_event(struct work_struct *_work)
451 {
452 struct mlx5e_ipsec_work *work =
453 container_of(_work, struct mlx5e_ipsec_work, work);
454 struct mlx5e_ipsec_sa_entry *sa_entry = work->data;
455 struct mlx5_accel_esp_xfrm_attrs *attrs;
456 struct mlx5e_ipsec_aso *aso;
457 int ret;
458
459 aso = sa_entry->ipsec->aso;
460 attrs = &sa_entry->attrs;
461
462 spin_lock_bh(&sa_entry->x->lock);
463 ret = mlx5e_ipsec_aso_query(sa_entry, NULL);
464 if (ret)
465 goto unlock;
466
467 if (attrs->replay_esn.trigger &&
468 !MLX5_GET(ipsec_aso, aso->ctx, esn_event_arm)) {
469 u32 mode_param = MLX5_GET(ipsec_aso, aso->ctx, mode_parameter);
470
471 mlx5e_ipsec_update_esn_state(sa_entry, mode_param);
472 }
473
474 if (attrs->lft.soft_packet_limit != XFRM_INF)
475 mlx5e_ipsec_handle_limits(sa_entry);
476
477 unlock:
478 spin_unlock_bh(&sa_entry->x->lock);
479 kfree(work);
480 }
481
mlx5e_ipsec_event(struct notifier_block * nb,unsigned long event,void * data)482 static int mlx5e_ipsec_event(struct notifier_block *nb, unsigned long event,
483 void *data)
484 {
485 struct mlx5e_ipsec *ipsec = container_of(nb, struct mlx5e_ipsec, nb);
486 struct mlx5e_ipsec_sa_entry *sa_entry;
487 struct mlx5_eqe_obj_change *object;
488 struct mlx5e_ipsec_work *work;
489 struct mlx5_eqe *eqe = data;
490 u16 type;
491
492 if (event != MLX5_EVENT_TYPE_OBJECT_CHANGE)
493 return NOTIFY_DONE;
494
495 object = &eqe->data.obj_change;
496 type = be16_to_cpu(object->obj_type);
497
498 if (type != MLX5_GENERAL_OBJECT_TYPES_IPSEC)
499 return NOTIFY_DONE;
500
501 sa_entry = xa_load(&ipsec->sadb, be32_to_cpu(object->obj_id));
502 if (!sa_entry)
503 return NOTIFY_DONE;
504
505 work = kmalloc(sizeof(*work), GFP_ATOMIC);
506 if (!work)
507 return NOTIFY_DONE;
508
509 INIT_WORK(&work->work, mlx5e_ipsec_handle_event);
510 work->data = sa_entry;
511
512 queue_work(ipsec->wq, &work->work);
513 return NOTIFY_OK;
514 }
515
mlx5e_ipsec_aso_init(struct mlx5e_ipsec * ipsec)516 int mlx5e_ipsec_aso_init(struct mlx5e_ipsec *ipsec)
517 {
518 struct mlx5_core_dev *mdev = ipsec->mdev;
519 struct mlx5e_ipsec_aso *aso;
520 struct mlx5e_hw_objs *res;
521 struct device *pdev;
522 int err;
523
524 aso = kzalloc(sizeof(*ipsec->aso), GFP_KERNEL);
525 if (!aso)
526 return -ENOMEM;
527
528 res = &mdev->mlx5e_res.hw_objs;
529
530 pdev = mlx5_core_dma_dev(mdev);
531 aso->dma_addr = dma_map_single(pdev, aso->ctx, sizeof(aso->ctx),
532 DMA_BIDIRECTIONAL);
533 err = dma_mapping_error(pdev, aso->dma_addr);
534 if (err)
535 goto err_dma;
536
537 aso->aso = mlx5_aso_create(mdev, res->pdn);
538 if (IS_ERR(aso->aso)) {
539 err = PTR_ERR(aso->aso);
540 goto err_aso_create;
541 }
542
543 spin_lock_init(&aso->lock);
544 ipsec->nb.notifier_call = mlx5e_ipsec_event;
545 mlx5_notifier_register(mdev, &ipsec->nb);
546
547 ipsec->aso = aso;
548 return 0;
549
550 err_aso_create:
551 dma_unmap_single(pdev, aso->dma_addr, sizeof(aso->ctx),
552 DMA_BIDIRECTIONAL);
553 err_dma:
554 kfree(aso);
555 return err;
556 }
557
mlx5e_ipsec_aso_cleanup(struct mlx5e_ipsec * ipsec)558 void mlx5e_ipsec_aso_cleanup(struct mlx5e_ipsec *ipsec)
559 {
560 struct mlx5_core_dev *mdev = ipsec->mdev;
561 struct mlx5e_ipsec_aso *aso;
562 struct device *pdev;
563
564 aso = ipsec->aso;
565 pdev = mlx5_core_dma_dev(mdev);
566
567 mlx5_notifier_unregister(mdev, &ipsec->nb);
568 mlx5_aso_destroy(aso->aso);
569 dma_unmap_single(pdev, aso->dma_addr, sizeof(aso->ctx),
570 DMA_BIDIRECTIONAL);
571 kfree(aso);
572 ipsec->aso = NULL;
573 }
574
mlx5e_ipsec_aso_copy(struct mlx5_wqe_aso_ctrl_seg * ctrl,struct mlx5_wqe_aso_ctrl_seg * data)575 static void mlx5e_ipsec_aso_copy(struct mlx5_wqe_aso_ctrl_seg *ctrl,
576 struct mlx5_wqe_aso_ctrl_seg *data)
577 {
578 if (!data)
579 return;
580
581 ctrl->data_mask_mode = data->data_mask_mode;
582 ctrl->condition_1_0_operand = data->condition_1_0_operand;
583 ctrl->condition_1_0_offset = data->condition_1_0_offset;
584 ctrl->data_offset_condition_operand = data->data_offset_condition_operand;
585 ctrl->condition_0_data = data->condition_0_data;
586 ctrl->condition_0_mask = data->condition_0_mask;
587 ctrl->condition_1_data = data->condition_1_data;
588 ctrl->condition_1_mask = data->condition_1_mask;
589 ctrl->bitwise_data = data->bitwise_data;
590 ctrl->data_mask = data->data_mask;
591 }
592
mlx5e_ipsec_aso_query(struct mlx5e_ipsec_sa_entry * sa_entry,struct mlx5_wqe_aso_ctrl_seg * data)593 int mlx5e_ipsec_aso_query(struct mlx5e_ipsec_sa_entry *sa_entry,
594 struct mlx5_wqe_aso_ctrl_seg *data)
595 {
596 struct mlx5e_ipsec *ipsec = sa_entry->ipsec;
597 struct mlx5e_ipsec_aso *aso = ipsec->aso;
598 struct mlx5_core_dev *mdev = ipsec->mdev;
599 struct mlx5_wqe_aso_ctrl_seg *ctrl;
600 struct mlx5e_hw_objs *res;
601 struct mlx5_aso_wqe *wqe;
602 unsigned long expires;
603 u8 ds_cnt;
604 int ret;
605
606 lockdep_assert_held(&sa_entry->x->lock);
607 res = &mdev->mlx5e_res.hw_objs;
608
609 spin_lock_bh(&aso->lock);
610 memset(aso->ctx, 0, sizeof(aso->ctx));
611 wqe = mlx5_aso_get_wqe(aso->aso);
612 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
613 mlx5_aso_build_wqe(aso->aso, ds_cnt, wqe, sa_entry->ipsec_obj_id,
614 MLX5_ACCESS_ASO_OPC_MOD_IPSEC);
615
616 ctrl = &wqe->aso_ctrl;
617 ctrl->va_l =
618 cpu_to_be32(lower_32_bits(aso->dma_addr) | ASO_CTRL_READ_EN);
619 ctrl->va_h = cpu_to_be32(upper_32_bits(aso->dma_addr));
620 ctrl->l_key = cpu_to_be32(res->mkey);
621 mlx5e_ipsec_aso_copy(ctrl, data);
622
623 mlx5_aso_post_wqe(aso->aso, false, &wqe->ctrl);
624 expires = jiffies + msecs_to_jiffies(10);
625 do {
626 ret = mlx5_aso_poll_cq(aso->aso, false);
627 if (ret)
628 /* We are in atomic context */
629 udelay(10);
630 } while (ret && time_is_after_jiffies(expires));
631 spin_unlock_bh(&aso->lock);
632 return ret;
633 }
634