1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /*
3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved.
4 */
5
6 #include <linux/gfp.h>
7 #include <linux/mlx5/qp.h>
8 #include <linux/mlx5/driver.h>
9 #include "mlx5_ib.h"
10 #include "qp.h"
11
12 static int mlx5_core_drain_dct(struct mlx5_ib_dev *dev,
13 struct mlx5_core_dct *dct);
14
15 static struct mlx5_core_rsc_common *
mlx5_get_rsc(struct mlx5_qp_table * table,u32 rsn)16 mlx5_get_rsc(struct mlx5_qp_table *table, u32 rsn)
17 {
18 struct mlx5_core_rsc_common *common;
19 unsigned long flags;
20
21 spin_lock_irqsave(&table->lock, flags);
22
23 common = radix_tree_lookup(&table->tree, rsn);
24 if (common && !common->invalid)
25 refcount_inc(&common->refcount);
26 else
27 common = NULL;
28
29 spin_unlock_irqrestore(&table->lock, flags);
30
31 return common;
32 }
33
mlx5_core_put_rsc(struct mlx5_core_rsc_common * common)34 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common)
35 {
36 if (refcount_dec_and_test(&common->refcount))
37 complete(&common->free);
38 }
39
qp_allowed_event_types(void)40 static u64 qp_allowed_event_types(void)
41 {
42 u64 mask;
43
44 mask = BIT(MLX5_EVENT_TYPE_PATH_MIG) |
45 BIT(MLX5_EVENT_TYPE_COMM_EST) |
46 BIT(MLX5_EVENT_TYPE_SQ_DRAINED) |
47 BIT(MLX5_EVENT_TYPE_SRQ_LAST_WQE) |
48 BIT(MLX5_EVENT_TYPE_WQ_CATAS_ERROR) |
49 BIT(MLX5_EVENT_TYPE_PATH_MIG_FAILED) |
50 BIT(MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) |
51 BIT(MLX5_EVENT_TYPE_WQ_ACCESS_ERROR);
52
53 return mask;
54 }
55
rq_allowed_event_types(void)56 static u64 rq_allowed_event_types(void)
57 {
58 u64 mask;
59
60 mask = BIT(MLX5_EVENT_TYPE_SRQ_LAST_WQE) |
61 BIT(MLX5_EVENT_TYPE_WQ_CATAS_ERROR);
62
63 return mask;
64 }
65
sq_allowed_event_types(void)66 static u64 sq_allowed_event_types(void)
67 {
68 return BIT(MLX5_EVENT_TYPE_WQ_CATAS_ERROR);
69 }
70
dct_allowed_event_types(void)71 static u64 dct_allowed_event_types(void)
72 {
73 return BIT(MLX5_EVENT_TYPE_DCT_DRAINED);
74 }
75
is_event_type_allowed(int rsc_type,int event_type)76 static bool is_event_type_allowed(int rsc_type, int event_type)
77 {
78 switch (rsc_type) {
79 case MLX5_EVENT_QUEUE_TYPE_QP:
80 return BIT(event_type) & qp_allowed_event_types();
81 case MLX5_EVENT_QUEUE_TYPE_RQ:
82 return BIT(event_type) & rq_allowed_event_types();
83 case MLX5_EVENT_QUEUE_TYPE_SQ:
84 return BIT(event_type) & sq_allowed_event_types();
85 case MLX5_EVENT_QUEUE_TYPE_DCT:
86 return BIT(event_type) & dct_allowed_event_types();
87 default:
88 WARN(1, "Event arrived for unknown resource type");
89 return false;
90 }
91 }
92
dct_event_notifier(struct mlx5_ib_dev * dev,struct mlx5_eqe * eqe)93 static int dct_event_notifier(struct mlx5_ib_dev *dev, struct mlx5_eqe *eqe)
94 {
95 struct mlx5_core_dct *dct;
96 unsigned long flags;
97 u32 qpn;
98
99 qpn = be32_to_cpu(eqe->data.dct.dctn) & 0xFFFFFF;
100 xa_lock_irqsave(&dev->qp_table.dct_xa, flags);
101 dct = xa_load(&dev->qp_table.dct_xa, qpn);
102 if (dct)
103 complete(&dct->drained);
104 xa_unlock_irqrestore(&dev->qp_table.dct_xa, flags);
105 return NOTIFY_OK;
106 }
107
rsc_event_notifier(struct notifier_block * nb,unsigned long type,void * data)108 static int rsc_event_notifier(struct notifier_block *nb,
109 unsigned long type, void *data)
110 {
111 struct mlx5_ib_dev *dev =
112 container_of(nb, struct mlx5_ib_dev, qp_table.nb);
113 struct mlx5_core_rsc_common *common;
114 struct mlx5_eqe *eqe = data;
115 u8 event_type = (u8)type;
116 struct mlx5_core_qp *qp;
117 u32 rsn;
118
119 switch (event_type) {
120 case MLX5_EVENT_TYPE_DCT_DRAINED:
121 return dct_event_notifier(dev, eqe);
122 case MLX5_EVENT_TYPE_PATH_MIG:
123 case MLX5_EVENT_TYPE_COMM_EST:
124 case MLX5_EVENT_TYPE_SQ_DRAINED:
125 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
126 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
127 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
128 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
129 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
130 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
131 rsn |= (eqe->data.qp_srq.type << MLX5_USER_INDEX_LEN);
132 break;
133 default:
134 return NOTIFY_DONE;
135 }
136
137 common = mlx5_get_rsc(&dev->qp_table, rsn);
138 if (!common)
139 return NOTIFY_OK;
140
141 if (!is_event_type_allowed((rsn >> MLX5_USER_INDEX_LEN), event_type))
142 goto out;
143
144 switch (common->res) {
145 case MLX5_RES_QP:
146 case MLX5_RES_RQ:
147 case MLX5_RES_SQ:
148 qp = (struct mlx5_core_qp *)common;
149 qp->event(qp, event_type);
150 /* Need to put resource in event handler */
151 return NOTIFY_OK;
152 default:
153 break;
154 }
155 out:
156 mlx5_core_put_rsc(common);
157
158 return NOTIFY_OK;
159 }
160
create_resource_common(struct mlx5_ib_dev * dev,struct mlx5_core_qp * qp,int rsc_type)161 static int create_resource_common(struct mlx5_ib_dev *dev,
162 struct mlx5_core_qp *qp, int rsc_type)
163 {
164 struct mlx5_qp_table *table = &dev->qp_table;
165 int err;
166
167 qp->common.res = rsc_type;
168 spin_lock_irq(&table->lock);
169 err = radix_tree_insert(&table->tree,
170 qp->qpn | (rsc_type << MLX5_USER_INDEX_LEN),
171 qp);
172 spin_unlock_irq(&table->lock);
173 if (err)
174 return err;
175
176 refcount_set(&qp->common.refcount, 1);
177 init_completion(&qp->common.free);
178 qp->pid = current->pid;
179
180 return 0;
181 }
182
modify_resource_common_state(struct mlx5_ib_dev * dev,struct mlx5_core_qp * qp,bool invalid)183 static void modify_resource_common_state(struct mlx5_ib_dev *dev,
184 struct mlx5_core_qp *qp,
185 bool invalid)
186 {
187 struct mlx5_qp_table *table = &dev->qp_table;
188 unsigned long flags;
189
190 spin_lock_irqsave(&table->lock, flags);
191 qp->common.invalid = invalid;
192 spin_unlock_irqrestore(&table->lock, flags);
193 }
194
destroy_resource_common(struct mlx5_ib_dev * dev,struct mlx5_core_qp * qp)195 static void destroy_resource_common(struct mlx5_ib_dev *dev,
196 struct mlx5_core_qp *qp)
197 {
198 struct mlx5_qp_table *table = &dev->qp_table;
199 unsigned long flags;
200
201 spin_lock_irqsave(&table->lock, flags);
202 radix_tree_delete(&table->tree,
203 qp->qpn | (qp->common.res << MLX5_USER_INDEX_LEN));
204 spin_unlock_irqrestore(&table->lock, flags);
205 mlx5_core_put_rsc((struct mlx5_core_rsc_common *)qp);
206 wait_for_completion(&qp->common.free);
207 }
208
_mlx5_core_destroy_dct(struct mlx5_ib_dev * dev,struct mlx5_core_dct * dct)209 static int _mlx5_core_destroy_dct(struct mlx5_ib_dev *dev,
210 struct mlx5_core_dct *dct)
211 {
212 u32 in[MLX5_ST_SZ_DW(destroy_dct_in)] = {};
213 struct mlx5_core_qp *qp = &dct->mqp;
214
215 MLX5_SET(destroy_dct_in, in, opcode, MLX5_CMD_OP_DESTROY_DCT);
216 MLX5_SET(destroy_dct_in, in, dctn, qp->qpn);
217 MLX5_SET(destroy_dct_in, in, uid, qp->uid);
218 return mlx5_cmd_exec_in(dev->mdev, destroy_dct, in);
219 }
220
mlx5_core_create_dct(struct mlx5_ib_dev * dev,struct mlx5_core_dct * dct,u32 * in,int inlen,u32 * out,int outlen)221 int mlx5_core_create_dct(struct mlx5_ib_dev *dev, struct mlx5_core_dct *dct,
222 u32 *in, int inlen, u32 *out, int outlen)
223 {
224 struct mlx5_core_qp *qp = &dct->mqp;
225 int err;
226
227 init_completion(&dct->drained);
228 MLX5_SET(create_dct_in, in, opcode, MLX5_CMD_OP_CREATE_DCT);
229
230 err = mlx5_cmd_do(dev->mdev, in, inlen, out, outlen);
231 if (err)
232 return err;
233
234 qp->qpn = MLX5_GET(create_dct_out, out, dctn);
235 qp->uid = MLX5_GET(create_dct_in, in, uid);
236 err = xa_err(xa_store_irq(&dev->qp_table.dct_xa, qp->qpn, dct, GFP_KERNEL));
237 if (err)
238 goto err_cmd;
239
240 return 0;
241 err_cmd:
242 _mlx5_core_destroy_dct(dev, dct);
243 return err;
244 }
245
mlx5_qpc_create_qp(struct mlx5_ib_dev * dev,struct mlx5_core_qp * qp,u32 * in,int inlen,u32 * out)246 int mlx5_qpc_create_qp(struct mlx5_ib_dev *dev, struct mlx5_core_qp *qp,
247 u32 *in, int inlen, u32 *out)
248 {
249 u32 din[MLX5_ST_SZ_DW(destroy_qp_in)] = {};
250 int err;
251
252 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
253
254 err = mlx5_cmd_exec(dev->mdev, in, inlen, out,
255 MLX5_ST_SZ_BYTES(create_qp_out));
256 if (err)
257 return err;
258
259 qp->uid = MLX5_GET(create_qp_in, in, uid);
260 qp->qpn = MLX5_GET(create_qp_out, out, qpn);
261
262 err = create_resource_common(dev, qp, MLX5_RES_QP);
263 if (err)
264 goto err_cmd;
265
266 mlx5_debug_qp_add(dev->mdev, qp);
267
268 return 0;
269
270 err_cmd:
271 MLX5_SET(destroy_qp_in, din, opcode, MLX5_CMD_OP_DESTROY_QP);
272 MLX5_SET(destroy_qp_in, din, qpn, qp->qpn);
273 MLX5_SET(destroy_qp_in, din, uid, qp->uid);
274 mlx5_cmd_exec_in(dev->mdev, destroy_qp, din);
275 return err;
276 }
277
mlx5_core_drain_dct(struct mlx5_ib_dev * dev,struct mlx5_core_dct * dct)278 static int mlx5_core_drain_dct(struct mlx5_ib_dev *dev,
279 struct mlx5_core_dct *dct)
280 {
281 u32 in[MLX5_ST_SZ_DW(drain_dct_in)] = {};
282 struct mlx5_core_qp *qp = &dct->mqp;
283
284 MLX5_SET(drain_dct_in, in, opcode, MLX5_CMD_OP_DRAIN_DCT);
285 MLX5_SET(drain_dct_in, in, dctn, qp->qpn);
286 MLX5_SET(drain_dct_in, in, uid, qp->uid);
287 return mlx5_cmd_exec_in(dev->mdev, drain_dct, in);
288 }
289
mlx5_core_destroy_dct(struct mlx5_ib_dev * dev,struct mlx5_core_dct * dct)290 int mlx5_core_destroy_dct(struct mlx5_ib_dev *dev,
291 struct mlx5_core_dct *dct)
292 {
293 struct mlx5_qp_table *table = &dev->qp_table;
294 struct mlx5_core_dct *tmp;
295 int err;
296
297 err = mlx5_core_drain_dct(dev, dct);
298 if (err) {
299 if (dev->mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
300 goto destroy;
301
302 return err;
303 }
304 wait_for_completion(&dct->drained);
305
306 destroy:
307 tmp = xa_cmpxchg_irq(&table->dct_xa, dct->mqp.qpn, dct, XA_ZERO_ENTRY, GFP_KERNEL);
308 if (WARN_ON(tmp != dct))
309 return xa_err(tmp) ?: -EINVAL;
310
311 err = _mlx5_core_destroy_dct(dev, dct);
312 if (err) {
313 xa_cmpxchg_irq(&table->dct_xa, dct->mqp.qpn, XA_ZERO_ENTRY, dct, 0);
314 return err;
315 }
316 xa_erase_irq(&table->dct_xa, dct->mqp.qpn);
317 return 0;
318 }
319
mlx5_core_destroy_qp(struct mlx5_ib_dev * dev,struct mlx5_core_qp * qp)320 int mlx5_core_destroy_qp(struct mlx5_ib_dev *dev, struct mlx5_core_qp *qp)
321 {
322 u32 in[MLX5_ST_SZ_DW(destroy_qp_in)] = {};
323
324 mlx5_debug_qp_remove(dev->mdev, qp);
325
326 destroy_resource_common(dev, qp);
327
328 MLX5_SET(destroy_qp_in, in, opcode, MLX5_CMD_OP_DESTROY_QP);
329 MLX5_SET(destroy_qp_in, in, qpn, qp->qpn);
330 MLX5_SET(destroy_qp_in, in, uid, qp->uid);
331 return mlx5_cmd_exec_in(dev->mdev, destroy_qp, in);
332 }
333
mlx5_core_set_delay_drop(struct mlx5_ib_dev * dev,u32 timeout_usec)334 int mlx5_core_set_delay_drop(struct mlx5_ib_dev *dev,
335 u32 timeout_usec)
336 {
337 u32 in[MLX5_ST_SZ_DW(set_delay_drop_params_in)] = {};
338
339 MLX5_SET(set_delay_drop_params_in, in, opcode,
340 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS);
341 MLX5_SET(set_delay_drop_params_in, in, delay_drop_timeout,
342 timeout_usec / 100);
343 return mlx5_cmd_exec_in(dev->mdev, set_delay_drop_params, in);
344 }
345
346 struct mbox_info {
347 u32 *in;
348 u32 *out;
349 int inlen;
350 int outlen;
351 };
352
mbox_alloc(struct mbox_info * mbox,int inlen,int outlen)353 static int mbox_alloc(struct mbox_info *mbox, int inlen, int outlen)
354 {
355 mbox->inlen = inlen;
356 mbox->outlen = outlen;
357 mbox->in = kzalloc(mbox->inlen, GFP_KERNEL);
358 mbox->out = kzalloc(mbox->outlen, GFP_KERNEL);
359 if (!mbox->in || !mbox->out) {
360 kfree(mbox->in);
361 kfree(mbox->out);
362 return -ENOMEM;
363 }
364
365 return 0;
366 }
367
mbox_free(struct mbox_info * mbox)368 static void mbox_free(struct mbox_info *mbox)
369 {
370 kfree(mbox->in);
371 kfree(mbox->out);
372 }
373
get_ece_from_mbox(void * out,u16 opcode)374 static int get_ece_from_mbox(void *out, u16 opcode)
375 {
376 int ece = 0;
377
378 switch (opcode) {
379 case MLX5_CMD_OP_INIT2INIT_QP:
380 ece = MLX5_GET(init2init_qp_out, out, ece);
381 break;
382 case MLX5_CMD_OP_INIT2RTR_QP:
383 ece = MLX5_GET(init2rtr_qp_out, out, ece);
384 break;
385 case MLX5_CMD_OP_RTR2RTS_QP:
386 ece = MLX5_GET(rtr2rts_qp_out, out, ece);
387 break;
388 case MLX5_CMD_OP_RTS2RTS_QP:
389 ece = MLX5_GET(rts2rts_qp_out, out, ece);
390 break;
391 case MLX5_CMD_OP_RST2INIT_QP:
392 ece = MLX5_GET(rst2init_qp_out, out, ece);
393 break;
394 default:
395 break;
396 }
397
398 return ece;
399 }
400
modify_qp_mbox_alloc(struct mlx5_core_dev * dev,u16 opcode,int qpn,u32 opt_param_mask,void * qpc,struct mbox_info * mbox,u16 uid,u32 ece)401 static int modify_qp_mbox_alloc(struct mlx5_core_dev *dev, u16 opcode, int qpn,
402 u32 opt_param_mask, void *qpc,
403 struct mbox_info *mbox, u16 uid, u32 ece)
404 {
405 mbox->out = NULL;
406 mbox->in = NULL;
407
408 #define MBOX_ALLOC(mbox, typ) \
409 mbox_alloc(mbox, MLX5_ST_SZ_BYTES(typ##_in), MLX5_ST_SZ_BYTES(typ##_out))
410
411 #define MOD_QP_IN_SET(typ, in, _opcode, _qpn, _uid) \
412 do { \
413 MLX5_SET(typ##_in, in, opcode, _opcode); \
414 MLX5_SET(typ##_in, in, qpn, _qpn); \
415 MLX5_SET(typ##_in, in, uid, _uid); \
416 } while (0)
417
418 #define MOD_QP_IN_SET_QPC(typ, in, _opcode, _qpn, _opt_p, _qpc, _uid) \
419 do { \
420 MOD_QP_IN_SET(typ, in, _opcode, _qpn, _uid); \
421 MLX5_SET(typ##_in, in, opt_param_mask, _opt_p); \
422 memcpy(MLX5_ADDR_OF(typ##_in, in, qpc), _qpc, \
423 MLX5_ST_SZ_BYTES(qpc)); \
424 } while (0)
425
426 switch (opcode) {
427 /* 2RST & 2ERR */
428 case MLX5_CMD_OP_2RST_QP:
429 if (MBOX_ALLOC(mbox, qp_2rst))
430 return -ENOMEM;
431 MOD_QP_IN_SET(qp_2rst, mbox->in, opcode, qpn, uid);
432 break;
433 case MLX5_CMD_OP_2ERR_QP:
434 if (MBOX_ALLOC(mbox, qp_2err))
435 return -ENOMEM;
436 MOD_QP_IN_SET(qp_2err, mbox->in, opcode, qpn, uid);
437 break;
438
439 /* MODIFY with QPC */
440 case MLX5_CMD_OP_RST2INIT_QP:
441 if (MBOX_ALLOC(mbox, rst2init_qp))
442 return -ENOMEM;
443 MOD_QP_IN_SET_QPC(rst2init_qp, mbox->in, opcode, qpn,
444 opt_param_mask, qpc, uid);
445 MLX5_SET(rst2init_qp_in, mbox->in, ece, ece);
446 break;
447 case MLX5_CMD_OP_INIT2RTR_QP:
448 if (MBOX_ALLOC(mbox, init2rtr_qp))
449 return -ENOMEM;
450 MOD_QP_IN_SET_QPC(init2rtr_qp, mbox->in, opcode, qpn,
451 opt_param_mask, qpc, uid);
452 MLX5_SET(init2rtr_qp_in, mbox->in, ece, ece);
453 break;
454 case MLX5_CMD_OP_RTR2RTS_QP:
455 if (MBOX_ALLOC(mbox, rtr2rts_qp))
456 return -ENOMEM;
457 MOD_QP_IN_SET_QPC(rtr2rts_qp, mbox->in, opcode, qpn,
458 opt_param_mask, qpc, uid);
459 MLX5_SET(rtr2rts_qp_in, mbox->in, ece, ece);
460 break;
461 case MLX5_CMD_OP_RTS2RTS_QP:
462 if (MBOX_ALLOC(mbox, rts2rts_qp))
463 return -ENOMEM;
464 MOD_QP_IN_SET_QPC(rts2rts_qp, mbox->in, opcode, qpn,
465 opt_param_mask, qpc, uid);
466 MLX5_SET(rts2rts_qp_in, mbox->in, ece, ece);
467 break;
468 case MLX5_CMD_OP_SQERR2RTS_QP:
469 if (MBOX_ALLOC(mbox, sqerr2rts_qp))
470 return -ENOMEM;
471 MOD_QP_IN_SET_QPC(sqerr2rts_qp, mbox->in, opcode, qpn,
472 opt_param_mask, qpc, uid);
473 break;
474 case MLX5_CMD_OP_SQD_RTS_QP:
475 if (MBOX_ALLOC(mbox, sqd2rts_qp))
476 return -ENOMEM;
477 MOD_QP_IN_SET_QPC(sqd2rts_qp, mbox->in, opcode, qpn,
478 opt_param_mask, qpc, uid);
479 break;
480 case MLX5_CMD_OP_INIT2INIT_QP:
481 if (MBOX_ALLOC(mbox, init2init_qp))
482 return -ENOMEM;
483 MOD_QP_IN_SET_QPC(init2init_qp, mbox->in, opcode, qpn,
484 opt_param_mask, qpc, uid);
485 MLX5_SET(init2init_qp_in, mbox->in, ece, ece);
486 break;
487 default:
488 return -EINVAL;
489 }
490 return 0;
491 }
492
mlx5_core_qp_modify(struct mlx5_ib_dev * dev,u16 opcode,u32 opt_param_mask,void * qpc,struct mlx5_core_qp * qp,u32 * ece)493 int mlx5_core_qp_modify(struct mlx5_ib_dev *dev, u16 opcode, u32 opt_param_mask,
494 void *qpc, struct mlx5_core_qp *qp, u32 *ece)
495 {
496 struct mbox_info mbox;
497 int err;
498
499 err = modify_qp_mbox_alloc(dev->mdev, opcode, qp->qpn, opt_param_mask,
500 qpc, &mbox, qp->uid, (ece) ? *ece : 0);
501 if (err)
502 return err;
503
504 err = mlx5_cmd_exec(dev->mdev, mbox.in, mbox.inlen, mbox.out,
505 mbox.outlen);
506
507 if (ece)
508 *ece = get_ece_from_mbox(mbox.out, opcode);
509
510 mbox_free(&mbox);
511 return err;
512 }
513
mlx5_init_qp_table(struct mlx5_ib_dev * dev)514 int mlx5_init_qp_table(struct mlx5_ib_dev *dev)
515 {
516 struct mlx5_qp_table *table = &dev->qp_table;
517
518 spin_lock_init(&table->lock);
519 INIT_RADIX_TREE(&table->tree, GFP_ATOMIC);
520 xa_init(&table->dct_xa);
521 mlx5_qp_debugfs_init(dev->mdev);
522
523 table->nb.notifier_call = rsc_event_notifier;
524 mlx5_notifier_register(dev->mdev, &table->nb);
525
526 return 0;
527 }
528
mlx5_cleanup_qp_table(struct mlx5_ib_dev * dev)529 void mlx5_cleanup_qp_table(struct mlx5_ib_dev *dev)
530 {
531 struct mlx5_qp_table *table = &dev->qp_table;
532
533 mlx5_notifier_unregister(dev->mdev, &table->nb);
534 mlx5_qp_debugfs_cleanup(dev->mdev);
535 }
536
mlx5_core_qp_query(struct mlx5_ib_dev * dev,struct mlx5_core_qp * qp,u32 * out,int outlen,bool qpc_ext)537 int mlx5_core_qp_query(struct mlx5_ib_dev *dev, struct mlx5_core_qp *qp,
538 u32 *out, int outlen, bool qpc_ext)
539 {
540 u32 in[MLX5_ST_SZ_DW(query_qp_in)] = {};
541
542 MLX5_SET(query_qp_in, in, opcode, MLX5_CMD_OP_QUERY_QP);
543 MLX5_SET(query_qp_in, in, qpn, qp->qpn);
544 MLX5_SET(query_qp_in, in, qpc_ext, qpc_ext);
545
546 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, outlen);
547 }
548
mlx5_core_dct_query(struct mlx5_ib_dev * dev,struct mlx5_core_dct * dct,u32 * out,int outlen)549 int mlx5_core_dct_query(struct mlx5_ib_dev *dev, struct mlx5_core_dct *dct,
550 u32 *out, int outlen)
551 {
552 u32 in[MLX5_ST_SZ_DW(query_dct_in)] = {};
553 struct mlx5_core_qp *qp = &dct->mqp;
554
555 MLX5_SET(query_dct_in, in, opcode, MLX5_CMD_OP_QUERY_DCT);
556 MLX5_SET(query_dct_in, in, dctn, qp->qpn);
557
558 return mlx5_cmd_exec(dev->mdev, (void *)&in, sizeof(in), (void *)out,
559 outlen);
560 }
561
mlx5_core_xrcd_alloc(struct mlx5_ib_dev * dev,u32 * xrcdn)562 int mlx5_core_xrcd_alloc(struct mlx5_ib_dev *dev, u32 *xrcdn)
563 {
564 u32 out[MLX5_ST_SZ_DW(alloc_xrcd_out)] = {};
565 u32 in[MLX5_ST_SZ_DW(alloc_xrcd_in)] = {};
566 int err;
567
568 MLX5_SET(alloc_xrcd_in, in, opcode, MLX5_CMD_OP_ALLOC_XRCD);
569 err = mlx5_cmd_exec_inout(dev->mdev, alloc_xrcd, in, out);
570 if (!err)
571 *xrcdn = MLX5_GET(alloc_xrcd_out, out, xrcd);
572 return err;
573 }
574
mlx5_core_xrcd_dealloc(struct mlx5_ib_dev * dev,u32 xrcdn)575 int mlx5_core_xrcd_dealloc(struct mlx5_ib_dev *dev, u32 xrcdn)
576 {
577 u32 in[MLX5_ST_SZ_DW(dealloc_xrcd_in)] = {};
578
579 MLX5_SET(dealloc_xrcd_in, in, opcode, MLX5_CMD_OP_DEALLOC_XRCD);
580 MLX5_SET(dealloc_xrcd_in, in, xrcd, xrcdn);
581 return mlx5_cmd_exec_in(dev->mdev, dealloc_xrcd, in);
582 }
583
destroy_rq_tracked(struct mlx5_ib_dev * dev,u32 rqn,u16 uid)584 static int destroy_rq_tracked(struct mlx5_ib_dev *dev, u32 rqn, u16 uid)
585 {
586 u32 in[MLX5_ST_SZ_DW(destroy_rq_in)] = {};
587
588 MLX5_SET(destroy_rq_in, in, opcode, MLX5_CMD_OP_DESTROY_RQ);
589 MLX5_SET(destroy_rq_in, in, rqn, rqn);
590 MLX5_SET(destroy_rq_in, in, uid, uid);
591 return mlx5_cmd_exec_in(dev->mdev, destroy_rq, in);
592 }
593
mlx5_core_create_rq_tracked(struct mlx5_ib_dev * dev,u32 * in,int inlen,struct mlx5_core_qp * rq)594 int mlx5_core_create_rq_tracked(struct mlx5_ib_dev *dev, u32 *in, int inlen,
595 struct mlx5_core_qp *rq)
596 {
597 int err;
598 u32 rqn;
599
600 err = mlx5_core_create_rq(dev->mdev, in, inlen, &rqn);
601 if (err)
602 return err;
603
604 rq->uid = MLX5_GET(create_rq_in, in, uid);
605 rq->qpn = rqn;
606 err = create_resource_common(dev, rq, MLX5_RES_RQ);
607 if (err)
608 goto err_destroy_rq;
609
610 return 0;
611
612 err_destroy_rq:
613 destroy_rq_tracked(dev, rq->qpn, rq->uid);
614
615 return err;
616 }
617
mlx5_core_destroy_rq_tracked(struct mlx5_ib_dev * dev,struct mlx5_core_qp * rq)618 int mlx5_core_destroy_rq_tracked(struct mlx5_ib_dev *dev,
619 struct mlx5_core_qp *rq)
620 {
621 int ret;
622
623 /* The rq destruction can be called again in case it fails, hence we
624 * mark the common resource as invalid and only once FW destruction
625 * is completed successfully we actually destroy the resources.
626 */
627 modify_resource_common_state(dev, rq, true);
628 ret = destroy_rq_tracked(dev, rq->qpn, rq->uid);
629 if (ret) {
630 modify_resource_common_state(dev, rq, false);
631 return ret;
632 }
633 destroy_resource_common(dev, rq);
634 return 0;
635 }
636
destroy_sq_tracked(struct mlx5_ib_dev * dev,u32 sqn,u16 uid)637 static void destroy_sq_tracked(struct mlx5_ib_dev *dev, u32 sqn, u16 uid)
638 {
639 u32 in[MLX5_ST_SZ_DW(destroy_sq_in)] = {};
640
641 MLX5_SET(destroy_sq_in, in, opcode, MLX5_CMD_OP_DESTROY_SQ);
642 MLX5_SET(destroy_sq_in, in, sqn, sqn);
643 MLX5_SET(destroy_sq_in, in, uid, uid);
644 mlx5_cmd_exec_in(dev->mdev, destroy_sq, in);
645 }
646
mlx5_core_create_sq_tracked(struct mlx5_ib_dev * dev,u32 * in,int inlen,struct mlx5_core_qp * sq)647 int mlx5_core_create_sq_tracked(struct mlx5_ib_dev *dev, u32 *in, int inlen,
648 struct mlx5_core_qp *sq)
649 {
650 u32 out[MLX5_ST_SZ_DW(create_sq_out)] = {};
651 int err;
652
653 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
654 err = mlx5_cmd_exec(dev->mdev, in, inlen, out, sizeof(out));
655 if (err)
656 return err;
657
658 sq->qpn = MLX5_GET(create_sq_out, out, sqn);
659 sq->uid = MLX5_GET(create_sq_in, in, uid);
660 err = create_resource_common(dev, sq, MLX5_RES_SQ);
661 if (err)
662 goto err_destroy_sq;
663
664 return 0;
665
666 err_destroy_sq:
667 destroy_sq_tracked(dev, sq->qpn, sq->uid);
668
669 return err;
670 }
671
mlx5_core_destroy_sq_tracked(struct mlx5_ib_dev * dev,struct mlx5_core_qp * sq)672 void mlx5_core_destroy_sq_tracked(struct mlx5_ib_dev *dev,
673 struct mlx5_core_qp *sq)
674 {
675 destroy_resource_common(dev, sq);
676 destroy_sq_tracked(dev, sq->qpn, sq->uid);
677 }
678
mlx5_core_res_hold(struct mlx5_ib_dev * dev,int res_num,enum mlx5_res_type res_type)679 struct mlx5_core_rsc_common *mlx5_core_res_hold(struct mlx5_ib_dev *dev,
680 int res_num,
681 enum mlx5_res_type res_type)
682 {
683 u32 rsn = res_num | (res_type << MLX5_USER_INDEX_LEN);
684 struct mlx5_qp_table *table = &dev->qp_table;
685
686 return mlx5_get_rsc(table, rsn);
687 }
688
mlx5_core_res_put(struct mlx5_core_rsc_common * res)689 void mlx5_core_res_put(struct mlx5_core_rsc_common *res)
690 {
691 mlx5_core_put_rsc(res);
692 }
693