1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
4 * Intel Management Engine Interface (Intel MEI) Linux driver
5 */
6
7 #include <linux/module.h>
8 #include <linux/kernel.h>
9 #include <linux/device.h>
10 #include <linux/errno.h>
11 #include <linux/types.h>
12 #include <linux/pci.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/sched.h>
15 #include <linux/interrupt.h>
16
17 #include <linux/pm_domain.h>
18 #include <linux/pm_runtime.h>
19
20 #include <linux/mei.h>
21
22 #include "mei_dev.h"
23 #include "client.h"
24 #include "hw-me-regs.h"
25 #include "hw-me.h"
26
27 /* mei_pci_tbl - PCI Device ID Table */
28 static const struct pci_device_id mei_me_pci_tbl[] = {
29 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
30 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
31 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
32 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
33 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
34 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
35 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
36 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
37 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
38 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
39 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
40
41 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
42 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
43 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
44 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
45 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
46 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
47 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
48 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
49 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
50
51 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
52 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
54 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
55
56 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
57 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
58 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
59 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
60 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
61 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
62 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
63 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)},
64 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)},
65 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
66 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)},
67 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
68 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
69
70 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
71 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
72 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)},
73 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)},
74 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)},
75 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)},
76
77 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
78 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
79
80 {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
81
82 {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
83
84 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
85 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
86 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)},
87
88 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
89 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
90 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)},
91 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)},
92
93 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
94 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
95 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)},
96 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)},
97 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)},
98
99 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
100 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_N, MEI_ME_PCH12_CFG)},
101
102 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)},
103 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)},
104
105 {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)},
106
107 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)},
108 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},
109
110 {MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)},
111
112 {MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)},
113
114 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)},
115 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)},
116 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)},
117 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_N, MEI_ME_PCH15_CFG)},
118
119 {MEI_PCI_DEVICE(MEI_DEV_ID_RPL_S, MEI_ME_PCH15_SPS_CFG)},
120
121 {MEI_PCI_DEVICE(MEI_DEV_ID_MTL_M, MEI_ME_PCH15_CFG)},
122 {MEI_PCI_DEVICE(MEI_DEV_ID_ARL_S, MEI_ME_PCH15_CFG)},
123 {MEI_PCI_DEVICE(MEI_DEV_ID_ARL_H, MEI_ME_PCH15_CFG)},
124
125 {MEI_PCI_DEVICE(MEI_DEV_ID_LNL_M, MEI_ME_PCH15_CFG)},
126
127 {MEI_PCI_DEVICE(MEI_DEV_ID_PTL_P, MEI_ME_PCH15_CFG)},
128
129 /* required last entry */
130 {0, }
131 };
132
133 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
134
135 #ifdef CONFIG_PM
136 static inline void mei_me_set_pm_domain(struct mei_device *dev);
137 static inline void mei_me_unset_pm_domain(struct mei_device *dev);
138 #else
mei_me_set_pm_domain(struct mei_device * dev)139 static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
mei_me_unset_pm_domain(struct mei_device * dev)140 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
141 #endif /* CONFIG_PM */
142
mei_me_read_fws(const struct mei_device * dev,int where,u32 * val)143 static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val)
144 {
145 struct pci_dev *pdev = to_pci_dev(dev->dev);
146
147 return pci_read_config_dword(pdev, where, val);
148 }
149
150 /**
151 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
152 *
153 * @pdev: PCI device structure
154 * @cfg: per generation config
155 *
156 * Return: true if ME Interface is valid, false otherwise
157 */
mei_me_quirk_probe(struct pci_dev * pdev,const struct mei_cfg * cfg)158 static bool mei_me_quirk_probe(struct pci_dev *pdev,
159 const struct mei_cfg *cfg)
160 {
161 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
162 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
163 return false;
164 }
165
166 return true;
167 }
168
169 /**
170 * mei_me_probe - Device Initialization Routine
171 *
172 * @pdev: PCI device structure
173 * @ent: entry in kcs_pci_tbl
174 *
175 * Return: 0 on success, <0 on failure.
176 */
mei_me_probe(struct pci_dev * pdev,const struct pci_device_id * ent)177 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
178 {
179 const struct mei_cfg *cfg;
180 struct mei_device *dev;
181 struct mei_me_hw *hw;
182 unsigned int irqflags;
183 int err;
184
185 cfg = mei_me_get_cfg(ent->driver_data);
186 if (!cfg)
187 return -ENODEV;
188
189 if (!mei_me_quirk_probe(pdev, cfg))
190 return -ENODEV;
191
192 /* enable pci dev */
193 err = pcim_enable_device(pdev);
194 if (err) {
195 dev_err(&pdev->dev, "failed to enable pci device.\n");
196 goto end;
197 }
198 /* set PCI host mastering */
199 pci_set_master(pdev);
200 /* pci request regions and mapping IO device memory for mei driver */
201 err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
202 if (err) {
203 dev_err(&pdev->dev, "failed to get pci regions.\n");
204 goto end;
205 }
206
207 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
208 if (err) {
209 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
210 goto end;
211 }
212
213 /* allocates and initializes the mei dev structure */
214 dev = mei_me_dev_init(&pdev->dev, cfg, false);
215 if (!dev) {
216 err = -ENOMEM;
217 goto end;
218 }
219 hw = to_me_hw(dev);
220 hw->mem_addr = pcim_iomap_table(pdev)[0];
221 hw->read_fws = mei_me_read_fws;
222
223 pci_enable_msi(pdev);
224
225 hw->irq = pdev->irq;
226
227 /* request and enable interrupt */
228 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
229
230 err = request_threaded_irq(pdev->irq,
231 mei_me_irq_quick_handler,
232 mei_me_irq_thread_handler,
233 irqflags, KBUILD_MODNAME, dev);
234 if (err) {
235 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
236 pdev->irq);
237 goto end;
238 }
239
240 if (mei_start(dev)) {
241 dev_err(&pdev->dev, "init hw failure.\n");
242 err = -ENODEV;
243 goto release_irq;
244 }
245
246 pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
247 pm_runtime_use_autosuspend(&pdev->dev);
248
249 err = mei_register(dev, &pdev->dev);
250 if (err)
251 goto stop;
252
253 pci_set_drvdata(pdev, dev);
254
255 /*
256 * MEI requires to resume from runtime suspend mode
257 * in order to perform link reset flow upon system suspend.
258 */
259 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
260
261 /*
262 * ME maps runtime suspend/resume to D0i states,
263 * hence we need to go around native PCI runtime service which
264 * eventually brings the device into D3cold/hot state,
265 * but the mei device cannot wake up from D3 unlike from D0i3.
266 * To get around the PCI device native runtime pm,
267 * ME uses runtime pm domain handlers which take precedence
268 * over the driver's pm handlers.
269 */
270 mei_me_set_pm_domain(dev);
271
272 if (mei_pg_is_enabled(dev)) {
273 pm_runtime_put_noidle(&pdev->dev);
274 if (hw->d0i3_supported)
275 pm_runtime_allow(&pdev->dev);
276 }
277
278 dev_dbg(&pdev->dev, "initialization successful.\n");
279
280 return 0;
281
282 stop:
283 mei_stop(dev);
284 release_irq:
285 mei_cancel_work(dev);
286 mei_disable_interrupts(dev);
287 free_irq(pdev->irq, dev);
288 end:
289 dev_err(&pdev->dev, "initialization failed.\n");
290 return err;
291 }
292
293 /**
294 * mei_me_shutdown - Device Removal Routine
295 *
296 * @pdev: PCI device structure
297 *
298 * mei_me_shutdown is called from the reboot notifier
299 * it's a simplified version of remove so we go down
300 * faster.
301 */
mei_me_shutdown(struct pci_dev * pdev)302 static void mei_me_shutdown(struct pci_dev *pdev)
303 {
304 struct mei_device *dev;
305
306 dev = pci_get_drvdata(pdev);
307 if (!dev)
308 return;
309
310 dev_dbg(&pdev->dev, "shutdown\n");
311 mei_stop(dev);
312
313 mei_me_unset_pm_domain(dev);
314
315 mei_disable_interrupts(dev);
316 free_irq(pdev->irq, dev);
317 }
318
319 /**
320 * mei_me_remove - Device Removal Routine
321 *
322 * @pdev: PCI device structure
323 *
324 * mei_me_remove is called by the PCI subsystem to alert the driver
325 * that it should release a PCI device.
326 */
mei_me_remove(struct pci_dev * pdev)327 static void mei_me_remove(struct pci_dev *pdev)
328 {
329 struct mei_device *dev;
330
331 dev = pci_get_drvdata(pdev);
332 if (!dev)
333 return;
334
335 if (mei_pg_is_enabled(dev))
336 pm_runtime_get_noresume(&pdev->dev);
337
338 dev_dbg(&pdev->dev, "stop\n");
339 mei_stop(dev);
340
341 mei_me_unset_pm_domain(dev);
342
343 mei_disable_interrupts(dev);
344
345 free_irq(pdev->irq, dev);
346
347 mei_deregister(dev);
348 }
349
350 #ifdef CONFIG_PM_SLEEP
mei_me_pci_prepare(struct device * device)351 static int mei_me_pci_prepare(struct device *device)
352 {
353 pm_runtime_resume(device);
354 return 0;
355 }
356
mei_me_pci_suspend(struct device * device)357 static int mei_me_pci_suspend(struct device *device)
358 {
359 struct pci_dev *pdev = to_pci_dev(device);
360 struct mei_device *dev = pci_get_drvdata(pdev);
361
362 if (!dev)
363 return -ENODEV;
364
365 dev_dbg(&pdev->dev, "suspend\n");
366
367 mei_stop(dev);
368
369 mei_disable_interrupts(dev);
370
371 free_irq(pdev->irq, dev);
372 pci_disable_msi(pdev);
373
374 return 0;
375 }
376
mei_me_pci_resume(struct device * device)377 static int mei_me_pci_resume(struct device *device)
378 {
379 struct pci_dev *pdev = to_pci_dev(device);
380 struct mei_device *dev;
381 unsigned int irqflags;
382 int err;
383
384 dev = pci_get_drvdata(pdev);
385 if (!dev)
386 return -ENODEV;
387
388 pci_enable_msi(pdev);
389
390 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
391
392 /* request and enable interrupt */
393 err = request_threaded_irq(pdev->irq,
394 mei_me_irq_quick_handler,
395 mei_me_irq_thread_handler,
396 irqflags, KBUILD_MODNAME, dev);
397
398 if (err) {
399 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
400 pdev->irq);
401 return err;
402 }
403
404 err = mei_restart(dev);
405 if (err) {
406 free_irq(pdev->irq, dev);
407 return err;
408 }
409
410 /* Start timer if stopped in suspend */
411 schedule_delayed_work(&dev->timer_work, HZ);
412
413 return 0;
414 }
415
mei_me_pci_complete(struct device * device)416 static void mei_me_pci_complete(struct device *device)
417 {
418 pm_runtime_suspend(device);
419 }
420 #else /* CONFIG_PM_SLEEP */
421
422 #define mei_me_pci_prepare NULL
423 #define mei_me_pci_complete NULL
424
425 #endif /* !CONFIG_PM_SLEEP */
426
427 #ifdef CONFIG_PM
mei_me_pm_runtime_idle(struct device * device)428 static int mei_me_pm_runtime_idle(struct device *device)
429 {
430 struct mei_device *dev;
431
432 dev_dbg(device, "rpm: me: runtime_idle\n");
433
434 dev = dev_get_drvdata(device);
435 if (!dev)
436 return -ENODEV;
437 if (mei_write_is_idle(dev))
438 pm_runtime_autosuspend(device);
439
440 return -EBUSY;
441 }
442
mei_me_pm_runtime_suspend(struct device * device)443 static int mei_me_pm_runtime_suspend(struct device *device)
444 {
445 struct mei_device *dev;
446 int ret;
447
448 dev_dbg(device, "rpm: me: runtime suspend\n");
449
450 dev = dev_get_drvdata(device);
451 if (!dev)
452 return -ENODEV;
453
454 mutex_lock(&dev->device_lock);
455
456 if (mei_write_is_idle(dev))
457 ret = mei_me_pg_enter_sync(dev);
458 else
459 ret = -EAGAIN;
460
461 mutex_unlock(&dev->device_lock);
462
463 dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);
464
465 if (ret && ret != -EAGAIN)
466 schedule_work(&dev->reset_work);
467
468 return ret;
469 }
470
mei_me_pm_runtime_resume(struct device * device)471 static int mei_me_pm_runtime_resume(struct device *device)
472 {
473 struct mei_device *dev;
474 int ret;
475
476 dev_dbg(device, "rpm: me: runtime resume\n");
477
478 dev = dev_get_drvdata(device);
479 if (!dev)
480 return -ENODEV;
481
482 mutex_lock(&dev->device_lock);
483
484 ret = mei_me_pg_exit_sync(dev);
485
486 mutex_unlock(&dev->device_lock);
487
488 dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret);
489
490 if (ret)
491 schedule_work(&dev->reset_work);
492
493 return ret;
494 }
495
496 /**
497 * mei_me_set_pm_domain - fill and set pm domain structure for device
498 *
499 * @dev: mei_device
500 */
mei_me_set_pm_domain(struct mei_device * dev)501 static inline void mei_me_set_pm_domain(struct mei_device *dev)
502 {
503 struct pci_dev *pdev = to_pci_dev(dev->dev);
504
505 if (pdev->dev.bus && pdev->dev.bus->pm) {
506 dev->pg_domain.ops = *pdev->dev.bus->pm;
507
508 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
509 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
510 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
511
512 dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
513 }
514 }
515
516 /**
517 * mei_me_unset_pm_domain - clean pm domain structure for device
518 *
519 * @dev: mei_device
520 */
mei_me_unset_pm_domain(struct mei_device * dev)521 static inline void mei_me_unset_pm_domain(struct mei_device *dev)
522 {
523 /* stop using pm callbacks if any */
524 dev_pm_domain_set(dev->dev, NULL);
525 }
526
527 static const struct dev_pm_ops mei_me_pm_ops = {
528 .prepare = mei_me_pci_prepare,
529 .complete = mei_me_pci_complete,
530 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
531 mei_me_pci_resume)
532 SET_RUNTIME_PM_OPS(
533 mei_me_pm_runtime_suspend,
534 mei_me_pm_runtime_resume,
535 mei_me_pm_runtime_idle)
536 };
537
538 #define MEI_ME_PM_OPS (&mei_me_pm_ops)
539 #else
540 #define MEI_ME_PM_OPS NULL
541 #endif /* CONFIG_PM */
542 /*
543 * PCI driver structure
544 */
545 static struct pci_driver mei_me_driver = {
546 .name = KBUILD_MODNAME,
547 .id_table = mei_me_pci_tbl,
548 .probe = mei_me_probe,
549 .remove = mei_me_remove,
550 .shutdown = mei_me_shutdown,
551 .driver.pm = MEI_ME_PM_OPS,
552 .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
553 };
554
555 module_pci_driver(mei_me_driver);
556
557 MODULE_AUTHOR("Intel Corporation");
558 MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
559 MODULE_LICENSE("GPL v2");
560