1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved.
4 */
5
6 #include <linux/delay.h>
7 #include <linux/interrupt.h>
8 #include <linux/io.h>
9 #include <linux/mailbox_controller.h>
10 #include <linux/of.h>
11 #include <linux/platform_device.h>
12 #include <linux/pm.h>
13 #include <linux/slab.h>
14
15 #include <soc/tegra/fuse.h>
16
17 #include <dt-bindings/mailbox/tegra186-hsp.h>
18
19 #include "mailbox.h"
20
21 #define HSP_INT_IE(x) (0x100 + ((x) * 4))
22 #define HSP_INT_IV 0x300
23 #define HSP_INT_IR 0x304
24
25 #define HSP_INT_EMPTY_SHIFT 0
26 #define HSP_INT_EMPTY_MASK 0xff
27 #define HSP_INT_FULL_SHIFT 8
28 #define HSP_INT_FULL_MASK 0xff
29
30 #define HSP_INT_DIMENSIONING 0x380
31 #define HSP_nSM_SHIFT 0
32 #define HSP_nSS_SHIFT 4
33 #define HSP_nAS_SHIFT 8
34 #define HSP_nDB_SHIFT 12
35 #define HSP_nSI_SHIFT 16
36 #define HSP_nINT_MASK 0xf
37
38 #define HSP_DB_TRIGGER 0x0
39 #define HSP_DB_ENABLE 0x4
40 #define HSP_DB_RAW 0x8
41 #define HSP_DB_PENDING 0xc
42
43 #define HSP_SM_SHRD_MBOX 0x0
44 #define HSP_SM_SHRD_MBOX_FULL BIT(31)
45 #define HSP_SM_SHRD_MBOX_FULL_INT_IE 0x04
46 #define HSP_SM_SHRD_MBOX_EMPTY_INT_IE 0x08
47
48 #define HSP_SHRD_MBOX_TYPE1_TAG 0x40
49 #define HSP_SHRD_MBOX_TYPE1_DATA0 0x48
50 #define HSP_SHRD_MBOX_TYPE1_DATA1 0x4c
51 #define HSP_SHRD_MBOX_TYPE1_DATA2 0x50
52 #define HSP_SHRD_MBOX_TYPE1_DATA3 0x54
53
54 #define HSP_DB_CCPLEX 1
55 #define HSP_DB_BPMP 3
56 #define HSP_DB_MAX 7
57
58 #define HSP_MBOX_TYPE_MASK 0xff
59
60 struct tegra_hsp_channel;
61 struct tegra_hsp;
62
63 struct tegra_hsp_channel {
64 struct tegra_hsp *hsp;
65 struct mbox_chan *chan;
66 void __iomem *regs;
67 };
68
69 struct tegra_hsp_doorbell {
70 struct tegra_hsp_channel channel;
71 struct list_head list;
72 const char *name;
73 unsigned int master;
74 unsigned int index;
75 };
76
77 struct tegra_hsp_sm_ops {
78 void (*send)(struct tegra_hsp_channel *channel, void *data);
79 void (*recv)(struct tegra_hsp_channel *channel);
80 };
81
82 struct tegra_hsp_mailbox {
83 struct tegra_hsp_channel channel;
84 const struct tegra_hsp_sm_ops *ops;
85 unsigned int index;
86 bool producer;
87 };
88
89 struct tegra_hsp_db_map {
90 const char *name;
91 unsigned int master;
92 unsigned int index;
93 };
94
95 struct tegra_hsp_soc {
96 const struct tegra_hsp_db_map *map;
97 bool has_per_mb_ie;
98 bool has_128_bit_mb;
99 unsigned int reg_stride;
100 };
101
102 struct tegra_hsp {
103 struct device *dev;
104 const struct tegra_hsp_soc *soc;
105 struct mbox_controller mbox_db;
106 struct mbox_controller mbox_sm;
107 void __iomem *regs;
108 unsigned int doorbell_irq;
109 unsigned int *shared_irqs;
110 unsigned int shared_irq;
111 unsigned int num_sm;
112 unsigned int num_as;
113 unsigned int num_ss;
114 unsigned int num_db;
115 unsigned int num_si;
116
117 spinlock_t lock;
118 struct lock_class_key lock_key;
119
120 struct list_head doorbells;
121 struct tegra_hsp_mailbox *mailboxes;
122
123 unsigned long mask;
124 };
125
tegra_hsp_readl(struct tegra_hsp * hsp,unsigned int offset)126 static inline u32 tegra_hsp_readl(struct tegra_hsp *hsp, unsigned int offset)
127 {
128 return readl(hsp->regs + offset);
129 }
130
tegra_hsp_writel(struct tegra_hsp * hsp,u32 value,unsigned int offset)131 static inline void tegra_hsp_writel(struct tegra_hsp *hsp, u32 value,
132 unsigned int offset)
133 {
134 writel(value, hsp->regs + offset);
135 }
136
tegra_hsp_channel_readl(struct tegra_hsp_channel * channel,unsigned int offset)137 static inline u32 tegra_hsp_channel_readl(struct tegra_hsp_channel *channel,
138 unsigned int offset)
139 {
140 return readl(channel->regs + offset);
141 }
142
tegra_hsp_channel_writel(struct tegra_hsp_channel * channel,u32 value,unsigned int offset)143 static inline void tegra_hsp_channel_writel(struct tegra_hsp_channel *channel,
144 u32 value, unsigned int offset)
145 {
146 writel(value, channel->regs + offset);
147 }
148
tegra_hsp_doorbell_can_ring(struct tegra_hsp_doorbell * db)149 static bool tegra_hsp_doorbell_can_ring(struct tegra_hsp_doorbell *db)
150 {
151 u32 value;
152
153 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_ENABLE);
154
155 return (value & BIT(TEGRA_HSP_DB_MASTER_CCPLEX)) != 0;
156 }
157
158 static struct tegra_hsp_doorbell *
__tegra_hsp_doorbell_get(struct tegra_hsp * hsp,unsigned int master)159 __tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
160 {
161 struct tegra_hsp_doorbell *entry;
162
163 list_for_each_entry(entry, &hsp->doorbells, list)
164 if (entry->master == master)
165 return entry;
166
167 return NULL;
168 }
169
170 static struct tegra_hsp_doorbell *
tegra_hsp_doorbell_get(struct tegra_hsp * hsp,unsigned int master)171 tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
172 {
173 struct tegra_hsp_doorbell *db;
174 unsigned long flags;
175
176 spin_lock_irqsave(&hsp->lock, flags);
177 db = __tegra_hsp_doorbell_get(hsp, master);
178 spin_unlock_irqrestore(&hsp->lock, flags);
179
180 return db;
181 }
182
tegra_hsp_doorbell_irq(int irq,void * data)183 static irqreturn_t tegra_hsp_doorbell_irq(int irq, void *data)
184 {
185 struct tegra_hsp *hsp = data;
186 struct tegra_hsp_doorbell *db;
187 unsigned long master, value;
188
189 db = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
190 if (!db)
191 return IRQ_NONE;
192
193 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_PENDING);
194 tegra_hsp_channel_writel(&db->channel, value, HSP_DB_PENDING);
195
196 spin_lock(&hsp->lock);
197
198 for_each_set_bit(master, &value, hsp->mbox_db.num_chans) {
199 struct tegra_hsp_doorbell *db;
200
201 db = __tegra_hsp_doorbell_get(hsp, master);
202 /*
203 * Depending on the bootloader chain, the CCPLEX doorbell will
204 * have some doorbells enabled, which means that requesting an
205 * interrupt will immediately fire.
206 *
207 * In that case, db->channel.chan will still be NULL here and
208 * cause a crash if not properly guarded.
209 *
210 * It remains to be seen if ignoring the doorbell in that case
211 * is the correct solution.
212 */
213 if (db && db->channel.chan)
214 mbox_chan_received_data(db->channel.chan, NULL);
215 }
216
217 spin_unlock(&hsp->lock);
218
219 return IRQ_HANDLED;
220 }
221
tegra_hsp_shared_irq(int irq,void * data)222 static irqreturn_t tegra_hsp_shared_irq(int irq, void *data)
223 {
224 struct tegra_hsp *hsp = data;
225 unsigned long bit, mask;
226 u32 status;
227
228 status = tegra_hsp_readl(hsp, HSP_INT_IR) & hsp->mask;
229
230 /* process EMPTY interrupts first */
231 mask = (status >> HSP_INT_EMPTY_SHIFT) & HSP_INT_EMPTY_MASK;
232
233 for_each_set_bit(bit, &mask, hsp->num_sm) {
234 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
235
236 if (mb->producer) {
237 /*
238 * Disable EMPTY interrupts until data is sent with
239 * the next message. These interrupts are level-
240 * triggered, so if we kept them enabled they would
241 * constantly trigger until we next write data into
242 * the message.
243 */
244 spin_lock(&hsp->lock);
245
246 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
247 tegra_hsp_writel(hsp, hsp->mask,
248 HSP_INT_IE(hsp->shared_irq));
249
250 spin_unlock(&hsp->lock);
251
252 mbox_chan_txdone(mb->channel.chan, 0);
253 }
254 }
255
256 /* process FULL interrupts */
257 mask = (status >> HSP_INT_FULL_SHIFT) & HSP_INT_FULL_MASK;
258
259 for_each_set_bit(bit, &mask, hsp->num_sm) {
260 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
261
262 if (!mb->producer)
263 mb->ops->recv(&mb->channel);
264 }
265
266 return IRQ_HANDLED;
267 }
268
269 static struct tegra_hsp_channel *
tegra_hsp_doorbell_create(struct tegra_hsp * hsp,const char * name,unsigned int master,unsigned int index)270 tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name,
271 unsigned int master, unsigned int index)
272 {
273 struct tegra_hsp_doorbell *db;
274 unsigned int offset;
275 unsigned long flags;
276
277 db = devm_kzalloc(hsp->dev, sizeof(*db), GFP_KERNEL);
278 if (!db)
279 return ERR_PTR(-ENOMEM);
280
281 offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K;
282 offset += index * hsp->soc->reg_stride;
283
284 db->channel.regs = hsp->regs + offset;
285 db->channel.hsp = hsp;
286
287 db->name = devm_kstrdup_const(hsp->dev, name, GFP_KERNEL);
288 db->master = master;
289 db->index = index;
290
291 spin_lock_irqsave(&hsp->lock, flags);
292 list_add_tail(&db->list, &hsp->doorbells);
293 spin_unlock_irqrestore(&hsp->lock, flags);
294
295 return &db->channel;
296 }
297
tegra_hsp_doorbell_send_data(struct mbox_chan * chan,void * data)298 static int tegra_hsp_doorbell_send_data(struct mbox_chan *chan, void *data)
299 {
300 struct tegra_hsp_doorbell *db = chan->con_priv;
301
302 tegra_hsp_channel_writel(&db->channel, 1, HSP_DB_TRIGGER);
303
304 return 0;
305 }
306
tegra_hsp_doorbell_startup(struct mbox_chan * chan)307 static int tegra_hsp_doorbell_startup(struct mbox_chan *chan)
308 {
309 struct tegra_hsp_doorbell *db = chan->con_priv;
310 struct tegra_hsp *hsp = db->channel.hsp;
311 struct tegra_hsp_doorbell *ccplex;
312 unsigned long flags;
313 u32 value;
314
315 if (db->master >= chan->mbox->num_chans) {
316 dev_err(chan->mbox->dev,
317 "invalid master ID %u for HSP channel\n",
318 db->master);
319 return -EINVAL;
320 }
321
322 ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
323 if (!ccplex)
324 return -ENODEV;
325
326 /*
327 * On simulation platforms the BPMP hasn't had a chance yet to mark
328 * the doorbell as ringable by the CCPLEX, so we want to skip extra
329 * checks here.
330 */
331 if (tegra_is_silicon() && !tegra_hsp_doorbell_can_ring(db))
332 return -ENODEV;
333
334 spin_lock_irqsave(&hsp->lock, flags);
335
336 value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
337 value |= BIT(db->master);
338 tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
339
340 spin_unlock_irqrestore(&hsp->lock, flags);
341
342 return 0;
343 }
344
tegra_hsp_doorbell_shutdown(struct mbox_chan * chan)345 static void tegra_hsp_doorbell_shutdown(struct mbox_chan *chan)
346 {
347 struct tegra_hsp_doorbell *db = chan->con_priv;
348 struct tegra_hsp *hsp = db->channel.hsp;
349 struct tegra_hsp_doorbell *ccplex;
350 unsigned long flags;
351 u32 value;
352
353 ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
354 if (!ccplex)
355 return;
356
357 spin_lock_irqsave(&hsp->lock, flags);
358
359 value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
360 value &= ~BIT(db->master);
361 tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
362
363 spin_unlock_irqrestore(&hsp->lock, flags);
364 }
365
366 static const struct mbox_chan_ops tegra_hsp_db_ops = {
367 .send_data = tegra_hsp_doorbell_send_data,
368 .startup = tegra_hsp_doorbell_startup,
369 .shutdown = tegra_hsp_doorbell_shutdown,
370 };
371
tegra_hsp_sm_send32(struct tegra_hsp_channel * channel,void * data)372 static void tegra_hsp_sm_send32(struct tegra_hsp_channel *channel, void *data)
373 {
374 u32 value;
375
376 /* copy data and mark mailbox full */
377 value = (u32)(unsigned long)data;
378 value |= HSP_SM_SHRD_MBOX_FULL;
379
380 tegra_hsp_channel_writel(channel, value, HSP_SM_SHRD_MBOX);
381 }
382
tegra_hsp_sm_recv32(struct tegra_hsp_channel * channel)383 static void tegra_hsp_sm_recv32(struct tegra_hsp_channel *channel)
384 {
385 u32 value;
386 void *msg;
387
388 value = tegra_hsp_channel_readl(channel, HSP_SM_SHRD_MBOX);
389 value &= ~HSP_SM_SHRD_MBOX_FULL;
390 msg = (void *)(unsigned long)value;
391
392 /*
393 * Need to clear all bits here since some producers, such as TCU, depend
394 * on fields in the register getting cleared by the consumer.
395 *
396 * The mailbox API doesn't give the consumers a way of doing that
397 * explicitly, so we have to make sure we cover all possible cases.
398 */
399 tegra_hsp_channel_writel(channel, 0x0, HSP_SM_SHRD_MBOX);
400
401 mbox_chan_received_data(channel->chan, msg);
402 }
403
404 static const struct tegra_hsp_sm_ops tegra_hsp_sm_32bit_ops = {
405 .send = tegra_hsp_sm_send32,
406 .recv = tegra_hsp_sm_recv32,
407 };
408
tegra_hsp_sm_send128(struct tegra_hsp_channel * channel,void * data)409 static void tegra_hsp_sm_send128(struct tegra_hsp_channel *channel, void *data)
410 {
411 u32 value[4];
412
413 memcpy(value, data, sizeof(value));
414
415 /* Copy data */
416 tegra_hsp_channel_writel(channel, value[0], HSP_SHRD_MBOX_TYPE1_DATA0);
417 tegra_hsp_channel_writel(channel, value[1], HSP_SHRD_MBOX_TYPE1_DATA1);
418 tegra_hsp_channel_writel(channel, value[2], HSP_SHRD_MBOX_TYPE1_DATA2);
419 tegra_hsp_channel_writel(channel, value[3], HSP_SHRD_MBOX_TYPE1_DATA3);
420
421 /* Update tag to mark mailbox full */
422 tegra_hsp_channel_writel(channel, HSP_SM_SHRD_MBOX_FULL,
423 HSP_SHRD_MBOX_TYPE1_TAG);
424 }
425
tegra_hsp_sm_recv128(struct tegra_hsp_channel * channel)426 static void tegra_hsp_sm_recv128(struct tegra_hsp_channel *channel)
427 {
428 u32 value[4];
429 void *msg;
430
431 value[0] = tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA0);
432 value[1] = tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA1);
433 value[2] = tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA2);
434 value[3] = tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA3);
435
436 msg = (void *)(unsigned long)value;
437
438 /*
439 * Clear data registers and tag.
440 */
441 tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA0);
442 tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA1);
443 tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA2);
444 tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA3);
445 tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_TAG);
446
447 mbox_chan_received_data(channel->chan, msg);
448 }
449
450 static const struct tegra_hsp_sm_ops tegra_hsp_sm_128bit_ops = {
451 .send = tegra_hsp_sm_send128,
452 .recv = tegra_hsp_sm_recv128,
453 };
454
tegra_hsp_mailbox_send_data(struct mbox_chan * chan,void * data)455 static int tegra_hsp_mailbox_send_data(struct mbox_chan *chan, void *data)
456 {
457 struct tegra_hsp_mailbox *mb = chan->con_priv;
458 struct tegra_hsp *hsp = mb->channel.hsp;
459 unsigned long flags;
460
461 if (WARN_ON(!mb->producer))
462 return -EPERM;
463
464 mb->ops->send(&mb->channel, data);
465
466 /* enable EMPTY interrupt for the shared mailbox */
467 spin_lock_irqsave(&hsp->lock, flags);
468
469 hsp->mask |= BIT(HSP_INT_EMPTY_SHIFT + mb->index);
470 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
471
472 spin_unlock_irqrestore(&hsp->lock, flags);
473
474 return 0;
475 }
476
tegra_hsp_mailbox_flush(struct mbox_chan * chan,unsigned long timeout)477 static int tegra_hsp_mailbox_flush(struct mbox_chan *chan,
478 unsigned long timeout)
479 {
480 struct tegra_hsp_mailbox *mb = chan->con_priv;
481 struct tegra_hsp_channel *ch = &mb->channel;
482 u32 value;
483
484 timeout = jiffies + msecs_to_jiffies(timeout);
485
486 while (time_before(jiffies, timeout)) {
487 value = tegra_hsp_channel_readl(ch, HSP_SM_SHRD_MBOX);
488 if ((value & HSP_SM_SHRD_MBOX_FULL) == 0) {
489 mbox_chan_txdone(chan, 0);
490
491 /* Wait until channel is empty */
492 if (chan->active_req != NULL)
493 continue;
494
495 return 0;
496 }
497
498 udelay(1);
499 }
500
501 return -ETIME;
502 }
503
tegra_hsp_mailbox_startup(struct mbox_chan * chan)504 static int tegra_hsp_mailbox_startup(struct mbox_chan *chan)
505 {
506 struct tegra_hsp_mailbox *mb = chan->con_priv;
507 struct tegra_hsp_channel *ch = &mb->channel;
508 struct tegra_hsp *hsp = mb->channel.hsp;
509 unsigned long flags;
510
511 chan->txdone_method = TXDONE_BY_IRQ;
512
513 /*
514 * Shared mailboxes start out as consumers by default. FULL and EMPTY
515 * interrupts are coalesced at the same shared interrupt.
516 *
517 * Keep EMPTY interrupts disabled at startup and only enable them when
518 * the mailbox is actually full. This is required because the FULL and
519 * EMPTY interrupts are level-triggered, so keeping EMPTY interrupts
520 * enabled all the time would cause an interrupt storm while mailboxes
521 * are idle.
522 */
523
524 spin_lock_irqsave(&hsp->lock, flags);
525
526 if (mb->producer)
527 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
528 else
529 hsp->mask |= BIT(HSP_INT_FULL_SHIFT + mb->index);
530
531 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
532
533 spin_unlock_irqrestore(&hsp->lock, flags);
534
535 if (hsp->soc->has_per_mb_ie) {
536 if (mb->producer)
537 tegra_hsp_channel_writel(ch, 0x0,
538 HSP_SM_SHRD_MBOX_EMPTY_INT_IE);
539 else
540 tegra_hsp_channel_writel(ch, 0x1,
541 HSP_SM_SHRD_MBOX_FULL_INT_IE);
542 }
543
544 return 0;
545 }
546
tegra_hsp_mailbox_shutdown(struct mbox_chan * chan)547 static void tegra_hsp_mailbox_shutdown(struct mbox_chan *chan)
548 {
549 struct tegra_hsp_mailbox *mb = chan->con_priv;
550 struct tegra_hsp_channel *ch = &mb->channel;
551 struct tegra_hsp *hsp = mb->channel.hsp;
552 unsigned long flags;
553
554 if (hsp->soc->has_per_mb_ie) {
555 if (mb->producer)
556 tegra_hsp_channel_writel(ch, 0x0,
557 HSP_SM_SHRD_MBOX_EMPTY_INT_IE);
558 else
559 tegra_hsp_channel_writel(ch, 0x0,
560 HSP_SM_SHRD_MBOX_FULL_INT_IE);
561 }
562
563 spin_lock_irqsave(&hsp->lock, flags);
564
565 if (mb->producer)
566 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
567 else
568 hsp->mask &= ~BIT(HSP_INT_FULL_SHIFT + mb->index);
569
570 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
571
572 spin_unlock_irqrestore(&hsp->lock, flags);
573 }
574
575 static const struct mbox_chan_ops tegra_hsp_sm_ops = {
576 .send_data = tegra_hsp_mailbox_send_data,
577 .flush = tegra_hsp_mailbox_flush,
578 .startup = tegra_hsp_mailbox_startup,
579 .shutdown = tegra_hsp_mailbox_shutdown,
580 };
581
tegra_hsp_db_xlate(struct mbox_controller * mbox,const struct of_phandle_args * args)582 static struct mbox_chan *tegra_hsp_db_xlate(struct mbox_controller *mbox,
583 const struct of_phandle_args *args)
584 {
585 struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_db);
586 unsigned int type = args->args[0], master = args->args[1];
587 struct tegra_hsp_channel *channel = ERR_PTR(-ENODEV);
588 struct tegra_hsp_doorbell *db;
589 struct mbox_chan *chan;
590 unsigned long flags;
591 unsigned int i;
592
593 if (type != TEGRA_HSP_MBOX_TYPE_DB || !hsp->doorbell_irq)
594 return ERR_PTR(-ENODEV);
595
596 db = tegra_hsp_doorbell_get(hsp, master);
597 if (db)
598 channel = &db->channel;
599
600 if (IS_ERR(channel))
601 return ERR_CAST(channel);
602
603 spin_lock_irqsave(&hsp->lock, flags);
604
605 for (i = 0; i < mbox->num_chans; i++) {
606 chan = &mbox->chans[i];
607 if (!chan->con_priv) {
608 channel->chan = chan;
609 chan->con_priv = db;
610 break;
611 }
612
613 chan = NULL;
614 }
615
616 spin_unlock_irqrestore(&hsp->lock, flags);
617
618 return chan ?: ERR_PTR(-EBUSY);
619 }
620
tegra_hsp_sm_xlate(struct mbox_controller * mbox,const struct of_phandle_args * args)621 static struct mbox_chan *tegra_hsp_sm_xlate(struct mbox_controller *mbox,
622 const struct of_phandle_args *args)
623 {
624 struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_sm);
625 unsigned int type = args->args[0], index;
626 struct tegra_hsp_mailbox *mb;
627
628 index = args->args[1] & TEGRA_HSP_SM_MASK;
629
630 if ((type & HSP_MBOX_TYPE_MASK) != TEGRA_HSP_MBOX_TYPE_SM ||
631 !hsp->shared_irqs || index >= hsp->num_sm)
632 return ERR_PTR(-ENODEV);
633
634 mb = &hsp->mailboxes[index];
635
636 if (type & TEGRA_HSP_MBOX_TYPE_SM_128BIT) {
637 if (!hsp->soc->has_128_bit_mb)
638 return ERR_PTR(-ENODEV);
639
640 mb->ops = &tegra_hsp_sm_128bit_ops;
641 } else {
642 mb->ops = &tegra_hsp_sm_32bit_ops;
643 }
644
645 if ((args->args[1] & TEGRA_HSP_SM_FLAG_TX) == 0)
646 mb->producer = false;
647 else
648 mb->producer = true;
649
650 return mb->channel.chan;
651 }
652
tegra_hsp_add_doorbells(struct tegra_hsp * hsp)653 static int tegra_hsp_add_doorbells(struct tegra_hsp *hsp)
654 {
655 const struct tegra_hsp_db_map *map = hsp->soc->map;
656 struct tegra_hsp_channel *channel;
657
658 while (map->name) {
659 channel = tegra_hsp_doorbell_create(hsp, map->name,
660 map->master, map->index);
661 if (IS_ERR(channel))
662 return PTR_ERR(channel);
663
664 map++;
665 }
666
667 return 0;
668 }
669
tegra_hsp_add_mailboxes(struct tegra_hsp * hsp,struct device * dev)670 static int tegra_hsp_add_mailboxes(struct tegra_hsp *hsp, struct device *dev)
671 {
672 int i;
673
674 hsp->mailboxes = devm_kcalloc(dev, hsp->num_sm, sizeof(*hsp->mailboxes),
675 GFP_KERNEL);
676 if (!hsp->mailboxes)
677 return -ENOMEM;
678
679 for (i = 0; i < hsp->num_sm; i++) {
680 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
681
682 mb->index = i;
683
684 mb->channel.hsp = hsp;
685 mb->channel.regs = hsp->regs + SZ_64K + i * SZ_32K;
686 mb->channel.chan = &hsp->mbox_sm.chans[i];
687 mb->channel.chan->con_priv = mb;
688 }
689
690 return 0;
691 }
692
tegra_hsp_request_shared_irq(struct tegra_hsp * hsp)693 static int tegra_hsp_request_shared_irq(struct tegra_hsp *hsp)
694 {
695 unsigned int i, irq = 0;
696 int err;
697
698 for (i = 0; i < hsp->num_si; i++) {
699 irq = hsp->shared_irqs[i];
700 if (irq <= 0)
701 continue;
702
703 err = devm_request_irq(hsp->dev, irq, tegra_hsp_shared_irq, 0,
704 dev_name(hsp->dev), hsp);
705 if (err < 0) {
706 dev_err(hsp->dev, "failed to request interrupt: %d\n",
707 err);
708 continue;
709 }
710
711 hsp->shared_irq = i;
712
713 /* disable all interrupts */
714 tegra_hsp_writel(hsp, 0, HSP_INT_IE(hsp->shared_irq));
715
716 dev_dbg(hsp->dev, "interrupt requested: %u\n", irq);
717
718 break;
719 }
720
721 if (i == hsp->num_si) {
722 dev_err(hsp->dev, "failed to find available interrupt\n");
723 return -ENOENT;
724 }
725
726 return 0;
727 }
728
tegra_hsp_probe(struct platform_device * pdev)729 static int tegra_hsp_probe(struct platform_device *pdev)
730 {
731 struct tegra_hsp *hsp;
732 unsigned int i;
733 u32 value;
734 int err;
735
736 hsp = devm_kzalloc(&pdev->dev, sizeof(*hsp), GFP_KERNEL);
737 if (!hsp)
738 return -ENOMEM;
739
740 hsp->dev = &pdev->dev;
741 hsp->soc = of_device_get_match_data(&pdev->dev);
742 INIT_LIST_HEAD(&hsp->doorbells);
743 spin_lock_init(&hsp->lock);
744
745 hsp->regs = devm_platform_ioremap_resource(pdev, 0);
746 if (IS_ERR(hsp->regs))
747 return PTR_ERR(hsp->regs);
748
749 value = tegra_hsp_readl(hsp, HSP_INT_DIMENSIONING);
750 hsp->num_sm = (value >> HSP_nSM_SHIFT) & HSP_nINT_MASK;
751 hsp->num_ss = (value >> HSP_nSS_SHIFT) & HSP_nINT_MASK;
752 hsp->num_as = (value >> HSP_nAS_SHIFT) & HSP_nINT_MASK;
753 hsp->num_db = (value >> HSP_nDB_SHIFT) & HSP_nINT_MASK;
754 hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK;
755
756 err = platform_get_irq_byname_optional(pdev, "doorbell");
757 if (err >= 0)
758 hsp->doorbell_irq = err;
759
760 if (hsp->num_si > 0) {
761 unsigned int count = 0;
762
763 hsp->shared_irqs = devm_kcalloc(&pdev->dev, hsp->num_si,
764 sizeof(*hsp->shared_irqs),
765 GFP_KERNEL);
766 if (!hsp->shared_irqs)
767 return -ENOMEM;
768
769 for (i = 0; i < hsp->num_si; i++) {
770 char *name;
771
772 name = kasprintf(GFP_KERNEL, "shared%u", i);
773 if (!name)
774 return -ENOMEM;
775
776 err = platform_get_irq_byname_optional(pdev, name);
777 if (err >= 0) {
778 hsp->shared_irqs[i] = err;
779 count++;
780 }
781
782 kfree(name);
783 }
784
785 if (count == 0) {
786 devm_kfree(&pdev->dev, hsp->shared_irqs);
787 hsp->shared_irqs = NULL;
788 }
789 }
790
791 /* setup the doorbell controller */
792 hsp->mbox_db.of_xlate = tegra_hsp_db_xlate;
793 hsp->mbox_db.num_chans = 32;
794 hsp->mbox_db.dev = &pdev->dev;
795 hsp->mbox_db.ops = &tegra_hsp_db_ops;
796
797 hsp->mbox_db.chans = devm_kcalloc(&pdev->dev, hsp->mbox_db.num_chans,
798 sizeof(*hsp->mbox_db.chans),
799 GFP_KERNEL);
800 if (!hsp->mbox_db.chans)
801 return -ENOMEM;
802
803 if (hsp->doorbell_irq) {
804 err = tegra_hsp_add_doorbells(hsp);
805 if (err < 0) {
806 dev_err(&pdev->dev, "failed to add doorbells: %d\n",
807 err);
808 return err;
809 }
810 }
811
812 err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_db);
813 if (err < 0) {
814 dev_err(&pdev->dev, "failed to register doorbell mailbox: %d\n",
815 err);
816 return err;
817 }
818
819 /* setup the shared mailbox controller */
820 hsp->mbox_sm.of_xlate = tegra_hsp_sm_xlate;
821 hsp->mbox_sm.num_chans = hsp->num_sm;
822 hsp->mbox_sm.dev = &pdev->dev;
823 hsp->mbox_sm.ops = &tegra_hsp_sm_ops;
824
825 hsp->mbox_sm.chans = devm_kcalloc(&pdev->dev, hsp->mbox_sm.num_chans,
826 sizeof(*hsp->mbox_sm.chans),
827 GFP_KERNEL);
828 if (!hsp->mbox_sm.chans)
829 return -ENOMEM;
830
831 if (hsp->shared_irqs) {
832 err = tegra_hsp_add_mailboxes(hsp, &pdev->dev);
833 if (err < 0) {
834 dev_err(&pdev->dev, "failed to add mailboxes: %d\n",
835 err);
836 return err;
837 }
838 }
839
840 err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_sm);
841 if (err < 0) {
842 dev_err(&pdev->dev, "failed to register shared mailbox: %d\n",
843 err);
844 return err;
845 }
846
847 platform_set_drvdata(pdev, hsp);
848
849 if (hsp->doorbell_irq) {
850 err = devm_request_irq(&pdev->dev, hsp->doorbell_irq,
851 tegra_hsp_doorbell_irq, IRQF_NO_SUSPEND,
852 dev_name(&pdev->dev), hsp);
853 if (err < 0) {
854 dev_err(&pdev->dev,
855 "failed to request doorbell IRQ#%u: %d\n",
856 hsp->doorbell_irq, err);
857 return err;
858 }
859 }
860
861 if (hsp->shared_irqs) {
862 err = tegra_hsp_request_shared_irq(hsp);
863 if (err < 0)
864 return err;
865 }
866
867 lockdep_register_key(&hsp->lock_key);
868 lockdep_set_class(&hsp->lock, &hsp->lock_key);
869
870 return 0;
871 }
872
tegra_hsp_remove(struct platform_device * pdev)873 static int tegra_hsp_remove(struct platform_device *pdev)
874 {
875 struct tegra_hsp *hsp = platform_get_drvdata(pdev);
876
877 lockdep_unregister_key(&hsp->lock_key);
878
879 return 0;
880 }
881
tegra_hsp_resume(struct device * dev)882 static int __maybe_unused tegra_hsp_resume(struct device *dev)
883 {
884 struct tegra_hsp *hsp = dev_get_drvdata(dev);
885 unsigned int i;
886 struct tegra_hsp_doorbell *db;
887
888 list_for_each_entry(db, &hsp->doorbells, list) {
889 if (db->channel.chan)
890 tegra_hsp_doorbell_startup(db->channel.chan);
891 }
892
893 if (hsp->mailboxes) {
894 for (i = 0; i < hsp->num_sm; i++) {
895 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
896
897 if (mb->channel.chan->cl)
898 tegra_hsp_mailbox_startup(mb->channel.chan);
899 }
900 }
901
902 return 0;
903 }
904
905 static const struct dev_pm_ops tegra_hsp_pm_ops = {
906 .resume_noirq = tegra_hsp_resume,
907 };
908
909 static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = {
910 { "ccplex", TEGRA_HSP_DB_MASTER_CCPLEX, HSP_DB_CCPLEX, },
911 { "bpmp", TEGRA_HSP_DB_MASTER_BPMP, HSP_DB_BPMP, },
912 { /* sentinel */ }
913 };
914
915 static const struct tegra_hsp_soc tegra186_hsp_soc = {
916 .map = tegra186_hsp_db_map,
917 .has_per_mb_ie = false,
918 .has_128_bit_mb = false,
919 .reg_stride = 0x100,
920 };
921
922 static const struct tegra_hsp_soc tegra194_hsp_soc = {
923 .map = tegra186_hsp_db_map,
924 .has_per_mb_ie = true,
925 .has_128_bit_mb = false,
926 .reg_stride = 0x100,
927 };
928
929 static const struct tegra_hsp_soc tegra234_hsp_soc = {
930 .map = tegra186_hsp_db_map,
931 .has_per_mb_ie = false,
932 .has_128_bit_mb = true,
933 .reg_stride = 0x100,
934 };
935
936 static const struct tegra_hsp_soc tegra264_hsp_soc = {
937 .map = tegra186_hsp_db_map,
938 .has_per_mb_ie = false,
939 .has_128_bit_mb = true,
940 .reg_stride = 0x1000,
941 };
942
943 static const struct of_device_id tegra_hsp_match[] = {
944 { .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc },
945 { .compatible = "nvidia,tegra194-hsp", .data = &tegra194_hsp_soc },
946 { .compatible = "nvidia,tegra234-hsp", .data = &tegra234_hsp_soc },
947 { .compatible = "nvidia,tegra264-hsp", .data = &tegra264_hsp_soc },
948 { }
949 };
950
951 static struct platform_driver tegra_hsp_driver = {
952 .driver = {
953 .name = "tegra-hsp",
954 .of_match_table = tegra_hsp_match,
955 .pm = &tegra_hsp_pm_ops,
956 },
957 .probe = tegra_hsp_probe,
958 .remove = tegra_hsp_remove,
959 };
960
tegra_hsp_init(void)961 static int __init tegra_hsp_init(void)
962 {
963 return platform_driver_register(&tegra_hsp_driver);
964 }
965 core_initcall(tegra_hsp_init);
966