1 /*
2 * QEMU MicroBlaze CPU
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 * Copyright (c) 2012 SUSE LINUX Products GmbH
7 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
8 *
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2.1 of the License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
18 *
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see
21 * <http://www.gnu.org/licenses/lgpl-2.1.html>
22 */
23
24 #include "qemu/osdep.h"
25 #include "qemu/log.h"
26 #include "qapi/error.h"
27 #include "cpu.h"
28 #include "qemu/module.h"
29 #include "hw/qdev-properties.h"
30 #include "exec/exec-all.h"
31 #include "exec/cpu_ldst.h"
32 #include "exec/gdbstub.h"
33 #include "exec/translation-block.h"
34 #include "fpu/softfloat-helpers.h"
35 #include "tcg/tcg.h"
36
37 static const struct {
38 const char *name;
39 uint8_t version_id;
40 } mb_cpu_lookup[] = {
41 /* These key value are as per MBV field in PVR0 */
42 {"5.00.a", 0x01},
43 {"5.00.b", 0x02},
44 {"5.00.c", 0x03},
45 {"6.00.a", 0x04},
46 {"6.00.b", 0x06},
47 {"7.00.a", 0x05},
48 {"7.00.b", 0x07},
49 {"7.10.a", 0x08},
50 {"7.10.b", 0x09},
51 {"7.10.c", 0x0a},
52 {"7.10.d", 0x0b},
53 {"7.20.a", 0x0c},
54 {"7.20.b", 0x0d},
55 {"7.20.c", 0x0e},
56 {"7.20.d", 0x0f},
57 {"7.30.a", 0x10},
58 {"7.30.b", 0x11},
59 {"8.00.a", 0x12},
60 {"8.00.b", 0x13},
61 {"8.10.a", 0x14},
62 {"8.20.a", 0x15},
63 {"8.20.b", 0x16},
64 {"8.30.a", 0x17},
65 {"8.40.a", 0x18},
66 {"8.40.b", 0x19},
67 {"8.50.a", 0x1A},
68 {"9.0", 0x1B},
69 {"9.1", 0x1D},
70 {"9.2", 0x1F},
71 {"9.3", 0x20},
72 {"9.4", 0x21},
73 {"9.5", 0x22},
74 {"9.6", 0x23},
75 {"10.0", 0x24},
76 {NULL, 0},
77 };
78
79 /* If no specific version gets selected, default to the following. */
80 #define DEFAULT_CPU_VERSION "10.0"
81
mb_cpu_set_pc(CPUState * cs,vaddr value)82 static void mb_cpu_set_pc(CPUState *cs, vaddr value)
83 {
84 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
85
86 cpu->env.pc = value;
87 /* Ensure D_FLAG and IMM_FLAG are clear for the new PC */
88 cpu->env.iflags = 0;
89 }
90
mb_cpu_get_pc(CPUState * cs)91 static vaddr mb_cpu_get_pc(CPUState *cs)
92 {
93 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
94
95 return cpu->env.pc;
96 }
97
mb_cpu_synchronize_from_tb(CPUState * cs,const TranslationBlock * tb)98 static void mb_cpu_synchronize_from_tb(CPUState *cs,
99 const TranslationBlock *tb)
100 {
101 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
102
103 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
104 cpu->env.pc = tb->pc;
105 cpu->env.iflags = tb->flags & IFLAGS_TB_MASK;
106 }
107
mb_restore_state_to_opc(CPUState * cs,const TranslationBlock * tb,const uint64_t * data)108 static void mb_restore_state_to_opc(CPUState *cs,
109 const TranslationBlock *tb,
110 const uint64_t *data)
111 {
112 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
113
114 cpu->env.pc = data[0];
115 cpu->env.iflags = data[1];
116 }
117
118 #ifndef CONFIG_USER_ONLY
mb_cpu_has_work(CPUState * cs)119 static bool mb_cpu_has_work(CPUState *cs)
120 {
121 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
122 }
123 #endif /* !CONFIG_USER_ONLY */
124
mb_cpu_mmu_index(CPUState * cs,bool ifetch)125 static int mb_cpu_mmu_index(CPUState *cs, bool ifetch)
126 {
127 CPUMBState *env = cpu_env(cs);
128 MicroBlazeCPU *cpu = env_archcpu(env);
129
130 /* Are we in nommu mode?. */
131 if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) {
132 return MMU_NOMMU_IDX;
133 }
134
135 if (env->msr & MSR_UM) {
136 return MMU_USER_IDX;
137 }
138 return MMU_KERNEL_IDX;
139 }
140
141 #ifndef CONFIG_USER_ONLY
mb_cpu_ns_axi_dp(void * opaque,int irq,int level)142 static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level)
143 {
144 MicroBlazeCPU *cpu = opaque;
145 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DP_MASK;
146
147 cpu->ns_axi_dp = level & en;
148 }
149
mb_cpu_ns_axi_ip(void * opaque,int irq,int level)150 static void mb_cpu_ns_axi_ip(void *opaque, int irq, int level)
151 {
152 MicroBlazeCPU *cpu = opaque;
153 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IP_MASK;
154
155 cpu->ns_axi_ip = level & en;
156 }
157
mb_cpu_ns_axi_dc(void * opaque,int irq,int level)158 static void mb_cpu_ns_axi_dc(void *opaque, int irq, int level)
159 {
160 MicroBlazeCPU *cpu = opaque;
161 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DC_MASK;
162
163 cpu->ns_axi_dc = level & en;
164 }
165
mb_cpu_ns_axi_ic(void * opaque,int irq,int level)166 static void mb_cpu_ns_axi_ic(void *opaque, int irq, int level)
167 {
168 MicroBlazeCPU *cpu = opaque;
169 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IC_MASK;
170
171 cpu->ns_axi_ic = level & en;
172 }
173
microblaze_cpu_set_irq(void * opaque,int irq,int level)174 static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
175 {
176 MicroBlazeCPU *cpu = opaque;
177 CPUState *cs = CPU(cpu);
178 int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
179
180 if (level) {
181 cpu_interrupt(cs, type);
182 } else {
183 cpu_reset_interrupt(cs, type);
184 }
185 }
186 #endif
187
mb_cpu_reset_hold(Object * obj,ResetType type)188 static void mb_cpu_reset_hold(Object *obj, ResetType type)
189 {
190 CPUState *cs = CPU(obj);
191 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
192 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(obj);
193 CPUMBState *env = &cpu->env;
194
195 if (mcc->parent_phases.hold) {
196 mcc->parent_phases.hold(obj, type);
197 }
198
199 memset(env, 0, offsetof(CPUMBState, end_reset_fields));
200 env->res_addr = RES_ADDR_NONE;
201
202 /* Disable stack protector. */
203 env->shr = ~0;
204
205 env->pc = cpu->cfg.base_vectors;
206
207 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
208 /*
209 * TODO: this is probably not the correct NaN propagation rule for
210 * this architecture.
211 */
212 set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
213 /* Default NaN: sign bit set, most significant frac bit set */
214 set_float_default_nan_pattern(0b11000000, &env->fp_status);
215
216 #if defined(CONFIG_USER_ONLY)
217 /* start in user mode with interrupts enabled. */
218 mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM);
219 #else
220 mb_cpu_write_msr(env, 0);
221 mmu_init(&env->mmu);
222 #endif
223 }
224
mb_disas_set_info(CPUState * cpu,disassemble_info * info)225 static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
226 {
227 info->mach = bfd_arch_microblaze;
228 info->print_insn = print_insn_microblaze;
229 info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG
230 : BFD_ENDIAN_LITTLE;
231 }
232
mb_cpu_realizefn(DeviceState * dev,Error ** errp)233 static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
234 {
235 CPUState *cs = CPU(dev);
236 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
237 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
238 uint8_t version_code = 0;
239 const char *version;
240 int i = 0;
241 Error *local_err = NULL;
242
243 cpu_exec_realizefn(cs, &local_err);
244 if (local_err != NULL) {
245 error_propagate(errp, local_err);
246 return;
247 }
248
249 if (cpu->cfg.addr_size < 32 || cpu->cfg.addr_size > 64) {
250 error_setg(errp, "addr-size %d is out of range (32 - 64)",
251 cpu->cfg.addr_size);
252 return;
253 }
254
255 qemu_init_vcpu(cs);
256
257 version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION;
258 for (i = 0; mb_cpu_lookup[i].name && version; i++) {
259 if (strcmp(mb_cpu_lookup[i].name, version) == 0) {
260 version_code = mb_cpu_lookup[i].version_id;
261 break;
262 }
263 }
264
265 if (!version_code) {
266 qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
267 }
268
269 cpu->cfg.pvr_regs[0] =
270 (PVR0_USE_EXC_MASK |
271 PVR0_USE_ICACHE_MASK |
272 PVR0_USE_DCACHE_MASK |
273 (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
274 (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
275 (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) |
276 (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) |
277 (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) |
278 (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
279 (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
280 (version_code << PVR0_VERSION_SHIFT) |
281 (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
282 cpu->cfg.pvr_user1);
283
284 cpu->cfg.pvr_regs[1] = cpu->cfg.pvr_user2;
285
286 cpu->cfg.pvr_regs[2] =
287 (PVR2_D_OPB_MASK |
288 PVR2_D_LMB_MASK |
289 PVR2_I_OPB_MASK |
290 PVR2_I_LMB_MASK |
291 PVR2_FPU_EXC_MASK |
292 (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
293 (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
294 (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
295 (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) |
296 (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
297 (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
298 (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) |
299 (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) |
300 (cpu->cfg.dopb_bus_exception ? PVR2_DOPB_BUS_EXC_MASK : 0) |
301 (cpu->cfg.iopb_bus_exception ? PVR2_IOPB_BUS_EXC_MASK : 0) |
302 (cpu->cfg.div_zero_exception ? PVR2_DIV_ZERO_EXC_MASK : 0) |
303 (cpu->cfg.illegal_opcode_exception ? PVR2_ILL_OPCODE_EXC_MASK : 0) |
304 (cpu->cfg.unaligned_exceptions ? PVR2_UNALIGNED_EXC_MASK : 0) |
305 (cpu->cfg.opcode_0_illegal ? PVR2_OPCODE_0x0_ILL_MASK : 0));
306
307 cpu->cfg.pvr_regs[5] |=
308 cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0;
309
310 cpu->cfg.pvr_regs[10] =
311 (0x0c000000 | /* Default to spartan 3a dsp family. */
312 (cpu->cfg.addr_size - 32) << PVR10_ASIZE_SHIFT);
313
314 cpu->cfg.pvr_regs[11] = ((cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) |
315 16 << 17);
316
317 cpu->cfg.mmu = 3;
318 cpu->cfg.mmu_tlb_access = 3;
319 cpu->cfg.mmu_zones = 16;
320 cpu->cfg.addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size);
321
322 mcc->parent_realize(dev, errp);
323 }
324
mb_cpu_initfn(Object * obj)325 static void mb_cpu_initfn(Object *obj)
326 {
327 MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
328
329 gdb_register_coprocessor(CPU(cpu), mb_cpu_gdb_read_stack_protect,
330 mb_cpu_gdb_write_stack_protect,
331 gdb_find_static_feature("microblaze-stack-protect.xml"),
332 0);
333
334 #ifndef CONFIG_USER_ONLY
335 /* Inbound IRQ and FIR lines */
336 qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
337 qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dp, "ns_axi_dp", 1);
338 qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ip, "ns_axi_ip", 1);
339 qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1);
340 qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1);
341 #endif
342
343 /* Restricted 'endianness' property is equivalent of 'little-endian' */
344 object_property_add_alias(obj, "little-endian", obj, "endianness");
345 }
346
347 static const Property mb_properties[] = {
348 /*
349 * Following properties are used by Xilinx DTS conversion tool
350 * do not rename them.
351 */
352 DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
353 DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
354 false),
355 /*
356 * This is the C_ADDR_SIZE synth-time configuration option of the
357 * MicroBlaze cores. Supported values range between 32 and 64.
358 *
359 * When set to > 32, 32bit MicroBlaze can emit load/stores
360 * with extended addressing.
361 */
362 DEFINE_PROP_UINT8("addr-size", MicroBlazeCPU, cfg.addr_size, 32),
363 /* If use-fpu > 0 - FPU is enabled
364 * If use-fpu = 2 - Floating point conversion and square root instructions
365 * are enabled
366 */
367 DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
368 /* If use-hw-mul > 0 - Multiplier is enabled
369 * If use-hw-mul = 2 - 64-bit multiplier is enabled
370 */
371 DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2),
372 DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),
373 DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),
374 DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true),
375 DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true),
376 DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
377 /*
378 * use-non-secure enables/disables the use of the non_secure[3:0] signals.
379 * It is a bitfield where 1 = non-secure for the following bits and their
380 * corresponding interfaces:
381 * 0x1 - M_AXI_DP
382 * 0x2 - M_AXI_IP
383 * 0x4 - M_AXI_DC
384 * 0x8 - M_AXI_IC
385 */
386 DEFINE_PROP_UINT8("use-non-secure", MicroBlazeCPU, cfg.use_non_secure, 0),
387 DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
388 false),
389 DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
390 /* Enables bus exceptions on failed data accesses (load/stores). */
391 DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU,
392 cfg.dopb_bus_exception, false),
393 /* Enables bus exceptions on failed instruction fetches. */
394 DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
395 cfg.iopb_bus_exception, false),
396 DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
397 cfg.illegal_opcode_exception, false),
398 DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
399 cfg.div_zero_exception, false),
400 DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU,
401 cfg.unaligned_exceptions, false),
402 DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
403 cfg.opcode_0_illegal, false),
404 DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
405 DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
406 DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
407 DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0),
408 /*
409 * End of properties reserved by Xilinx DTS conversion tool.
410 */
411 };
412
mb_cpu_class_by_name(const char * cpu_model)413 static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
414 {
415 return object_class_by_name(TYPE_MICROBLAZE_CPU);
416 }
417
418 #ifndef CONFIG_USER_ONLY
419 #include "hw/core/sysemu-cpu-ops.h"
420
421 static const struct SysemuCPUOps mb_sysemu_ops = {
422 .has_work = mb_cpu_has_work,
423 .get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug,
424 };
425 #endif
426
427 #include "accel/tcg/cpu-ops.h"
428
429 static const TCGCPUOps mb_tcg_ops = {
430 .initialize = mb_tcg_init,
431 .translate_code = mb_translate_code,
432 .synchronize_from_tb = mb_cpu_synchronize_from_tb,
433 .restore_state_to_opc = mb_restore_state_to_opc,
434
435 #ifndef CONFIG_USER_ONLY
436 .tlb_fill = mb_cpu_tlb_fill,
437 .cpu_exec_interrupt = mb_cpu_exec_interrupt,
438 .cpu_exec_halt = mb_cpu_has_work,
439 .do_interrupt = mb_cpu_do_interrupt,
440 .do_transaction_failed = mb_cpu_transaction_failed,
441 .do_unaligned_access = mb_cpu_do_unaligned_access,
442 #endif /* !CONFIG_USER_ONLY */
443 };
444
mb_cpu_class_init(ObjectClass * oc,void * data)445 static void mb_cpu_class_init(ObjectClass *oc, void *data)
446 {
447 DeviceClass *dc = DEVICE_CLASS(oc);
448 CPUClass *cc = CPU_CLASS(oc);
449 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
450 ResettableClass *rc = RESETTABLE_CLASS(oc);
451
452 device_class_set_parent_realize(dc, mb_cpu_realizefn,
453 &mcc->parent_realize);
454 resettable_class_set_parent_phases(rc, NULL, mb_cpu_reset_hold, NULL,
455 &mcc->parent_phases);
456
457 cc->class_by_name = mb_cpu_class_by_name;
458 cc->mmu_index = mb_cpu_mmu_index;
459 cc->dump_state = mb_cpu_dump_state;
460 cc->set_pc = mb_cpu_set_pc;
461 cc->get_pc = mb_cpu_get_pc;
462 cc->gdb_read_register = mb_cpu_gdb_read_register;
463 cc->gdb_write_register = mb_cpu_gdb_write_register;
464
465 #ifndef CONFIG_USER_ONLY
466 dc->vmsd = &vmstate_mb_cpu;
467 cc->sysemu_ops = &mb_sysemu_ops;
468 #endif
469 device_class_set_props(dc, mb_properties);
470 cc->gdb_core_xml_file = "microblaze-core.xml";
471
472 cc->disas_set_info = mb_disas_set_info;
473 cc->tcg_ops = &mb_tcg_ops;
474 }
475
476 static const TypeInfo mb_cpu_type_info = {
477 .name = TYPE_MICROBLAZE_CPU,
478 .parent = TYPE_CPU,
479 .instance_size = sizeof(MicroBlazeCPU),
480 .instance_align = __alignof(MicroBlazeCPU),
481 .instance_init = mb_cpu_initfn,
482 .class_size = sizeof(MicroBlazeCPUClass),
483 .class_init = mb_cpu_class_init,
484 };
485
mb_cpu_register_types(void)486 static void mb_cpu_register_types(void)
487 {
488 type_register_static(&mb_cpu_type_info);
489 }
490
491 type_init(mb_cpu_register_types)
492