1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_HW_CATALOG_H 8 #define _DPU_HW_CATALOG_H 9 10 #include <linux/kernel.h> 11 #include <linux/bug.h> 12 #include <linux/bitmap.h> 13 #include <linux/err.h> 14 15 /** 16 * Max hardware block count: For ex: max 12 SSPP pipes or 17 * 5 ctl paths. In all cases, it can have max 12 hardware blocks 18 * based on current design 19 */ 20 #define MAX_BLOCKS 12 21 22 #define DPU_HW_BLK_NAME_LEN 16 23 24 #define MAX_IMG_WIDTH 0x3fff 25 #define MAX_IMG_HEIGHT 0x3fff 26 27 #define CRTC_DUAL_MIXERS 2 28 29 #define MAX_XIN_COUNT 16 30 31 /** 32 * MDP TOP BLOCK features 33 * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be done per pipe 34 * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats 35 * @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block results 36 * in a failure 37 * @DPU_MDP_VSYNC_SEL Enables vsync source selection via MDP_VSYNC_SEL register 38 * (moved into INTF block since DPU 5.0.0) 39 * @DPU_MDP_MAX Maximum value 40 41 */ 42 enum { 43 DPU_MDP_PANIC_PER_PIPE = 0x1, 44 DPU_MDP_10BIT_SUPPORT, 45 DPU_MDP_AUDIO_SELECT, 46 DPU_MDP_PERIPH_0_REMOVED, 47 DPU_MDP_VSYNC_SEL, 48 DPU_MDP_MAX 49 }; 50 51 /** 52 * SSPP sub-blocks/features 53 * @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support 54 * @DPU_SSPP_SCALER_QSEED3, QSEED3 alogorithm support 55 * @DPU_SSPP_SCALER_QSEED3LITE, QSEED3 Lite alogorithm support 56 * @DPU_SSPP_SCALER_QSEED4, QSEED4 algorithm support 57 * @DPU_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes 58 * @DPU_SSPP_CSC, Support of Color space converion 59 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion 60 * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer 61 * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq 62 * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control 63 * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect 64 * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support 65 * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support 66 * @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper 67 * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec 68 * @DPU_SSPP_CDP Supports client driven prefetch 69 * @DPU_SSPP_INLINE_ROTATION Support inline rotation 70 * @DPU_SSPP_MAX maximum value 71 */ 72 enum { 73 DPU_SSPP_SCALER_QSEED2 = 0x1, 74 DPU_SSPP_SCALER_QSEED3, 75 DPU_SSPP_SCALER_QSEED3LITE, 76 DPU_SSPP_SCALER_QSEED4, 77 DPU_SSPP_SCALER_RGB, 78 DPU_SSPP_CSC, 79 DPU_SSPP_CSC_10BIT, 80 DPU_SSPP_CURSOR, 81 DPU_SSPP_QOS, 82 DPU_SSPP_QOS_8LVL, 83 DPU_SSPP_EXCL_RECT, 84 DPU_SSPP_SMART_DMA_V1, 85 DPU_SSPP_SMART_DMA_V2, 86 DPU_SSPP_TS_PREFILL, 87 DPU_SSPP_TS_PREFILL_REC1, 88 DPU_SSPP_CDP, 89 DPU_SSPP_INLINE_ROTATION, 90 DPU_SSPP_MAX 91 }; 92 93 /* 94 * MIXER sub-blocks/features 95 * @DPU_MIXER_LAYER Layer mixer layer blend configuration, 96 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration 97 * @DPU_MIXER_GC Gamma correction block 98 * @DPU_DIM_LAYER Layer mixer supports dim layer 99 * @DPU_MIXER_COMBINED_ALPHA Layer mixer has combined alpha register 100 * @DPU_MIXER_MAX maximum value 101 */ 102 enum { 103 DPU_MIXER_LAYER = 0x1, 104 DPU_MIXER_SOURCESPLIT, 105 DPU_MIXER_GC, 106 DPU_DIM_LAYER, 107 DPU_MIXER_COMBINED_ALPHA, 108 DPU_MIXER_MAX 109 }; 110 111 /** 112 * DSPP sub-blocks 113 * @DPU_DSPP_PCC Panel color correction block 114 */ 115 enum { 116 DPU_DSPP_PCC = 0x1, 117 DPU_DSPP_MAX 118 }; 119 120 /** 121 * PINGPONG sub-blocks 122 * @DPU_PINGPONG_TE Tear check block 123 * @DPU_PINGPONG_TE2 Additional tear check block for split pipes 124 * @DPU_PINGPONG_SPLIT PP block supports split fifo 125 * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo 126 * @DPU_PINGPONG_DITHER Dither blocks 127 * @DPU_PINGPONG_DSC PP block supports DSC 128 * @DPU_PINGPONG_MAX 129 */ 130 enum { 131 DPU_PINGPONG_TE = 0x1, 132 DPU_PINGPONG_TE2, 133 DPU_PINGPONG_SPLIT, 134 DPU_PINGPONG_SLAVE, 135 DPU_PINGPONG_DITHER, 136 DPU_PINGPONG_DSC, 137 DPU_PINGPONG_MAX 138 }; 139 140 /** 141 * CTL sub-blocks 142 * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display 143 * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs) 144 * @DPU_CTL_VM_CFG: CTL config to support multiple VMs 145 * @DPU_CTL_HAS_LAYER_EXT4: CTL has the CTL_LAYER_EXT4 register 146 * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush 147 * @DPU_CTL_MAX 148 */ 149 enum { 150 DPU_CTL_SPLIT_DISPLAY = 0x1, 151 DPU_CTL_ACTIVE_CFG, 152 DPU_CTL_FETCH_ACTIVE, 153 DPU_CTL_VM_CFG, 154 DPU_CTL_HAS_LAYER_EXT4, 155 DPU_CTL_DSPP_SUB_BLOCK_FLUSH, 156 DPU_CTL_MAX 157 }; 158 159 /** 160 * INTF sub-blocks 161 * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which 162 * pixel data arrives to this INTF 163 * @DPU_INTF_TE INTF block has TE configuration support 164 * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate 165 * than video timing 166 * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register 167 * @DPU_INTF_MAX 168 */ 169 enum { 170 DPU_INTF_INPUT_CTRL = 0x1, 171 DPU_INTF_TE, 172 DPU_DATA_HCTL_EN, 173 DPU_INTF_STATUS_SUPPORTED, 174 DPU_INTF_MAX 175 }; 176 177 /** 178 * WB sub-blocks and features 179 * @DPU_WB_LINE_MODE Writeback module supports line/linear mode 180 * @DPU_WB_BLOCK_MODE Writeback module supports block mode read 181 * @DPU_WB_CHROMA_DOWN, Writeback chroma down block, 182 * @DPU_WB_DOWNSCALE, Writeback integer downscaler, 183 * @DPU_WB_DITHER, Dither block 184 * @DPU_WB_TRAFFIC_SHAPER, Writeback traffic shaper bloc 185 * @DPU_WB_UBWC, Writeback Universal bandwidth compression 186 * @DPU_WB_YUV_CONFIG Writeback supports output of YUV colorspace 187 * @DPU_WB_PIPE_ALPHA Writeback supports pipe alpha 188 * @DPU_WB_XY_ROI_OFFSET Writeback supports x/y-offset of out ROI in 189 * the destination image 190 * @DPU_WB_QOS, Writeback supports QoS control, danger/safe/creq 191 * @DPU_WB_QOS_8LVL, Writeback supports 8-level QoS control 192 * @DPU_WB_CDP Writeback supports client driven prefetch 193 * @DPU_WB_INPUT_CTRL Writeback supports from which pp block input pixel 194 * data arrives. 195 * @DPU_WB_CROP CWB supports cropping 196 * @DPU_WB_MAX maximum value 197 */ 198 enum { 199 DPU_WB_LINE_MODE = 0x1, 200 DPU_WB_BLOCK_MODE, 201 DPU_WB_UBWC, 202 DPU_WB_YUV_CONFIG, 203 DPU_WB_PIPE_ALPHA, 204 DPU_WB_XY_ROI_OFFSET, 205 DPU_WB_QOS, 206 DPU_WB_QOS_8LVL, 207 DPU_WB_CDP, 208 DPU_WB_INPUT_CTRL, 209 DPU_WB_CROP, 210 DPU_WB_MAX 211 }; 212 213 /** 214 * VBIF sub-blocks and features 215 * @DPU_VBIF_QOS_OTLIM VBIF supports OT Limit 216 * @DPU_VBIF_QOS_REMAP VBIF supports QoS priority remap 217 * @DPU_VBIF_MAX maximum value 218 */ 219 enum { 220 DPU_VBIF_QOS_OTLIM = 0x1, 221 DPU_VBIF_QOS_REMAP, 222 DPU_VBIF_MAX 223 }; 224 225 /** 226 * DSC sub-blocks/features 227 * @DPU_DSC_OUTPUT_CTRL Configure which PINGPONG block gets 228 * the pixel output from this DSC. 229 * @DPU_DSC_HW_REV_1_2 DSC block supports DSC 1.1 and 1.2 230 * @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN encoding 231 * @DPU_DSC_MAX 232 */ 233 enum { 234 DPU_DSC_OUTPUT_CTRL = 0x1, 235 DPU_DSC_HW_REV_1_2, 236 DPU_DSC_NATIVE_42x_EN, 237 DPU_DSC_MAX 238 }; 239 240 /** 241 * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU 242 * @name: string name for debug purposes 243 * @id: enum identifying this block 244 * @base: register base offset to mdss 245 * @len: length of hardware block 246 * @features bit mask identifying sub-blocks/features 247 */ 248 #define DPU_HW_BLK_INFO \ 249 char name[DPU_HW_BLK_NAME_LEN]; \ 250 u32 id; \ 251 u32 base; \ 252 u32 len; \ 253 unsigned long features 254 255 /** 256 * MACRO DPU_HW_SUBBLK_INFO - information of HW sub-block inside DPU 257 * @name: string name for debug purposes 258 * @id: enum identifying this sub-block 259 * @base: offset of this sub-block relative to the block 260 * offset 261 * @len register block length of this sub-block 262 */ 263 #define DPU_HW_SUBBLK_INFO \ 264 char name[DPU_HW_BLK_NAME_LEN]; \ 265 u32 id; \ 266 u32 base; \ 267 u32 len 268 269 /** 270 * struct dpu_scaler_blk: Scaler information 271 * @info: HW register and features supported by this sub-blk 272 * @version: qseed block revision, on QSEED3+ platforms this is the value of 273 * scaler_blk.base + QSEED3_HW_VERSION registers. 274 */ 275 struct dpu_scaler_blk { 276 DPU_HW_SUBBLK_INFO; 277 u32 version; 278 }; 279 280 struct dpu_csc_blk { 281 DPU_HW_SUBBLK_INFO; 282 }; 283 284 /** 285 * struct dpu_pp_blk : Pixel processing sub-blk information 286 * @info: HW register and features supported by this sub-blk 287 * @version: HW Algorithm version 288 */ 289 struct dpu_pp_blk { 290 DPU_HW_SUBBLK_INFO; 291 u32 version; 292 }; 293 294 /** 295 * struct dpu_dsc_blk - DSC Encoder sub-blk information 296 * @info: HW register and features supported by this sub-blk 297 */ 298 struct dpu_dsc_blk { 299 DPU_HW_SUBBLK_INFO; 300 }; 301 302 /** 303 * enum dpu_qos_lut_usage - define QoS LUT use cases 304 */ 305 enum dpu_qos_lut_usage { 306 DPU_QOS_LUT_USAGE_LINEAR, 307 DPU_QOS_LUT_USAGE_MACROTILE, 308 DPU_QOS_LUT_USAGE_NRT, 309 DPU_QOS_LUT_USAGE_MAX, 310 }; 311 312 /** 313 * struct dpu_qos_lut_entry - define QoS LUT table entry 314 * @fl: fill level, or zero on last entry to indicate default lut 315 * @lut: lut to use if equal to or less than fill level 316 */ 317 struct dpu_qos_lut_entry { 318 u32 fl; 319 u64 lut; 320 }; 321 322 /** 323 * struct dpu_qos_lut_tbl - define QoS LUT table 324 * @nentry: number of entry in this table 325 * @entries: Pointer to table entries 326 */ 327 struct dpu_qos_lut_tbl { 328 u32 nentry; 329 const struct dpu_qos_lut_entry *entries; 330 }; 331 332 /** 333 * struct dpu_rotation_cfg - define inline rotation config 334 * @rot_maxheight: max pre rotated height allowed for rotation 335 * @rot_num_formats: number of elements in @rot_format_list 336 * @rot_format_list: list of supported rotator formats 337 */ 338 struct dpu_rotation_cfg { 339 u32 rot_maxheight; 340 size_t rot_num_formats; 341 const u32 *rot_format_list; 342 }; 343 344 /** 345 * struct dpu_caps - define DPU capabilities 346 * @max_mixer_width max layer mixer line width support. 347 * @max_mixer_blendstages max layer mixer blend stages or 348 * supported z order 349 * @qseed_type qseed2 or qseed3 support. 350 * @has_src_split source split feature status 351 * @has_dim_layer dim layer feature status 352 * @has_idle_pc indicate if idle power collapse feature is supported 353 * @has_3d_merge indicate if 3D merge is supported 354 * @max_linewidth max linewidth for sspp 355 * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes 356 * @max_hdeci_exp max horizontal decimation supported (max is 2^value) 357 * @max_vdeci_exp max vertical decimation supported (max is 2^value) 358 */ 359 struct dpu_caps { 360 u32 max_mixer_width; 361 u32 max_mixer_blendstages; 362 u32 qseed_type; 363 bool has_src_split; 364 bool has_dim_layer; 365 bool has_idle_pc; 366 bool has_3d_merge; 367 /* SSPP limits */ 368 u32 max_linewidth; 369 u32 pixel_ram_size; 370 u32 max_hdeci_exp; 371 u32 max_vdeci_exp; 372 }; 373 374 /** 375 * struct dpu_sspp_sub_blks : SSPP sub-blocks 376 * common: Pointer to common configurations shared by sub blocks 377 * @maxdwnscale: max downscale ratio supported(without DECIMATION) 378 * @maxupscale: maxupscale ratio supported 379 * @smart_dma_priority: hw priority of rect1 of multirect pipe 380 * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps 381 * @qseed_ver: qseed version 382 * @scaler_blk: 383 * @csc_blk: 384 * @format_list: Pointer to list of supported formats 385 * @num_formats: Number of supported formats 386 * @virt_format_list: Pointer to list of supported formats for virtual planes 387 * @virt_num_formats: Number of supported formats for virtual planes 388 * @dpu_rotation_cfg: inline rotation configuration 389 */ 390 struct dpu_sspp_sub_blks { 391 u32 maxdwnscale; 392 u32 maxupscale; 393 u32 smart_dma_priority; 394 u32 max_per_pipe_bw; 395 u32 qseed_ver; 396 struct dpu_scaler_blk scaler_blk; 397 struct dpu_pp_blk csc_blk; 398 399 const u32 *format_list; 400 u32 num_formats; 401 const u32 *virt_format_list; 402 u32 virt_num_formats; 403 const struct dpu_rotation_cfg *rotation_cfg; 404 }; 405 406 /** 407 * struct dpu_lm_sub_blks: information of mixer block 408 * @maxwidth: Max pixel width supported by this mixer 409 * @maxblendstages: Max number of blend-stages supported 410 * @blendstage_base: Blend-stage register base offset 411 */ 412 struct dpu_lm_sub_blks { 413 u32 maxwidth; 414 u32 maxblendstages; 415 u32 blendstage_base[MAX_BLOCKS]; 416 }; 417 418 /** 419 * struct dpu_dspp_sub_blks: Information of DSPP block 420 * @pcc: pixel color correction block 421 */ 422 struct dpu_dspp_sub_blks { 423 struct dpu_pp_blk pcc; 424 }; 425 426 struct dpu_pingpong_sub_blks { 427 struct dpu_pp_blk te; 428 struct dpu_pp_blk te2; 429 struct dpu_pp_blk dither; 430 }; 431 432 /** 433 * struct dpu_dsc_sub_blks - DSC sub-blks 434 * @enc: DSC encoder sub-block 435 * @ctl: DSC controller sub-block 436 */ 437 struct dpu_dsc_sub_blks { 438 struct dpu_dsc_blk enc; 439 struct dpu_dsc_blk ctl; 440 }; 441 442 /** 443 * dpu_clk_ctrl_type - Defines top level clock control signals 444 */ 445 enum dpu_clk_ctrl_type { 446 DPU_CLK_CTRL_NONE, 447 DPU_CLK_CTRL_VIG0, 448 DPU_CLK_CTRL_VIG1, 449 DPU_CLK_CTRL_VIG2, 450 DPU_CLK_CTRL_VIG3, 451 DPU_CLK_CTRL_VIG4, 452 DPU_CLK_CTRL_RGB0, 453 DPU_CLK_CTRL_RGB1, 454 DPU_CLK_CTRL_RGB2, 455 DPU_CLK_CTRL_RGB3, 456 DPU_CLK_CTRL_DMA0, 457 DPU_CLK_CTRL_DMA1, 458 DPU_CLK_CTRL_DMA2, 459 DPU_CLK_CTRL_DMA3, 460 DPU_CLK_CTRL_DMA4, 461 DPU_CLK_CTRL_DMA5, 462 DPU_CLK_CTRL_CURSOR0, 463 DPU_CLK_CTRL_CURSOR1, 464 DPU_CLK_CTRL_INLINE_ROT0_SSPP, 465 DPU_CLK_CTRL_REG_DMA, 466 DPU_CLK_CTRL_WB2, 467 DPU_CLK_CTRL_MAX, 468 }; 469 470 /* struct dpu_clk_ctrl_reg : Clock control register 471 * @reg_off: register offset 472 * @bit_off: bit offset 473 */ 474 struct dpu_clk_ctrl_reg { 475 u32 reg_off; 476 u32 bit_off; 477 }; 478 479 /* struct dpu_mdp_cfg : MDP TOP-BLK instance info 480 * @id: index identifying this block 481 * @base: register base offset to mdss 482 * @features bit mask identifying sub-blocks/features 483 * @clk_ctrls clock control register definition 484 */ 485 struct dpu_mdp_cfg { 486 DPU_HW_BLK_INFO; 487 struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; 488 }; 489 490 /* struct dpu_ctl_cfg : MDP CTL instance info 491 * @id: index identifying this block 492 * @base: register base offset to mdss 493 * @features bit mask identifying sub-blocks/features 494 * @intr_start: interrupt index for CTL_START 495 */ 496 struct dpu_ctl_cfg { 497 DPU_HW_BLK_INFO; 498 s32 intr_start; 499 }; 500 501 /** 502 * struct dpu_sspp_cfg - information of source pipes 503 * @id: index identifying this block 504 * @base register offset of this block 505 * @features bit mask identifying sub-blocks/features 506 * @sblk: SSPP sub-blocks information 507 * @xin_id: bus client identifier 508 * @clk_ctrl clock control identifier 509 * @type sspp type identifier 510 */ 511 struct dpu_sspp_cfg { 512 DPU_HW_BLK_INFO; 513 const struct dpu_sspp_sub_blks *sblk; 514 u32 xin_id; 515 enum dpu_clk_ctrl_type clk_ctrl; 516 u32 type; 517 }; 518 519 /** 520 * struct dpu_lm_cfg - information of layer mixer blocks 521 * @id: index identifying this block 522 * @base register offset of this block 523 * @features bit mask identifying sub-blocks/features 524 * @sblk: LM Sub-blocks information 525 * @pingpong: ID of connected PingPong, PINGPONG_NONE if unsupported 526 * @lm_pair: ID of LM that can be controlled by same CTL 527 */ 528 struct dpu_lm_cfg { 529 DPU_HW_BLK_INFO; 530 const struct dpu_lm_sub_blks *sblk; 531 u32 pingpong; 532 u32 dspp; 533 unsigned long lm_pair; 534 }; 535 536 /** 537 * struct dpu_dspp_cfg - information of DSPP blocks 538 * @id enum identifying this block 539 * @base register offset of this block 540 * @features bit mask identifying sub-blocks/features 541 * supported by this block 542 * @sblk sub-blocks information 543 */ 544 struct dpu_dspp_cfg { 545 DPU_HW_BLK_INFO; 546 const struct dpu_dspp_sub_blks *sblk; 547 }; 548 549 /** 550 * struct dpu_pingpong_cfg - information of PING-PONG blocks 551 * @id enum identifying this block 552 * @base register offset of this block 553 * @features bit mask identifying sub-blocks/features 554 * @intr_done: index for PINGPONG done interrupt 555 * @intr_rdptr: index for PINGPONG readpointer done interrupt 556 * @sblk sub-blocks information 557 */ 558 struct dpu_pingpong_cfg { 559 DPU_HW_BLK_INFO; 560 u32 merge_3d; 561 s32 intr_done; 562 s32 intr_rdptr; 563 const struct dpu_pingpong_sub_blks *sblk; 564 }; 565 566 /** 567 * struct dpu_merge_3d_cfg - information of DSPP blocks 568 * @id enum identifying this block 569 * @base register offset of this block 570 * @features bit mask identifying sub-blocks/features 571 * supported by this block 572 * @sblk sub-blocks information 573 */ 574 struct dpu_merge_3d_cfg { 575 DPU_HW_BLK_INFO; 576 const struct dpu_merge_3d_sub_blks *sblk; 577 }; 578 579 /** 580 * struct dpu_dsc_cfg - information of DSC blocks 581 * @id enum identifying this block 582 * @base register offset of this block 583 * @len: length of hardware block 584 * @features bit mask identifying sub-blocks/features 585 * @sblk: sub-blocks information 586 */ 587 struct dpu_dsc_cfg { 588 DPU_HW_BLK_INFO; 589 const struct dpu_dsc_sub_blks *sblk; 590 }; 591 592 /** 593 * struct dpu_intf_cfg - information of timing engine blocks 594 * @id enum identifying this block 595 * @base register offset of this block 596 * @features bit mask identifying sub-blocks/features 597 * @type: Interface type(DSI, DP, HDMI) 598 * @controller_id: Controller Instance ID in case of multiple of intf type 599 * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch 600 * @intr_underrun: index for INTF underrun interrupt 601 * @intr_vsync: index for INTF VSYNC interrupt 602 * @intr_tear_rd_ptr: Index for INTF TEAR_RD_PTR interrupt 603 */ 604 struct dpu_intf_cfg { 605 DPU_HW_BLK_INFO; 606 u32 type; /* interface type*/ 607 u32 controller_id; 608 u32 prog_fetch_lines_worst_case; 609 s32 intr_underrun; 610 s32 intr_vsync; 611 s32 intr_tear_rd_ptr; 612 }; 613 614 /** 615 * struct dpu_wb_cfg - information of writeback blocks 616 * @DPU_HW_BLK_INFO: refer to the description above for DPU_HW_BLK_INFO 617 * @vbif_idx: vbif client index 618 * @maxlinewidth: max line width supported by writeback block 619 * @xin_id: bus client identifier 620 * @intr_wb_done: interrupt index for WB_DONE 621 * @format_list: list of formats supported by this writeback block 622 * @num_formats: number of formats supported by this writeback block 623 * @clk_ctrl: clock control identifier 624 */ 625 struct dpu_wb_cfg { 626 DPU_HW_BLK_INFO; 627 u8 vbif_idx; 628 u32 maxlinewidth; 629 u32 xin_id; 630 s32 intr_wb_done; 631 const u32 *format_list; 632 u32 num_formats; 633 enum dpu_clk_ctrl_type clk_ctrl; 634 }; 635 636 /** 637 * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting 638 * @pps pixel per seconds 639 * @ot_limit OT limit to use up to specified pixel per second 640 */ 641 struct dpu_vbif_dynamic_ot_cfg { 642 u64 pps; 643 u32 ot_limit; 644 }; 645 646 /** 647 * struct dpu_vbif_dynamic_ot_tbl - dynamic OT setting table 648 * @count length of cfg 649 * @cfg pointer to array of configuration settings with 650 * ascending requirements 651 */ 652 struct dpu_vbif_dynamic_ot_tbl { 653 u32 count; 654 const struct dpu_vbif_dynamic_ot_cfg *cfg; 655 }; 656 657 /** 658 * struct dpu_vbif_qos_tbl - QoS priority table 659 * @npriority_lvl num of priority level 660 * @priority_lvl pointer to array of priority level in ascending order 661 */ 662 struct dpu_vbif_qos_tbl { 663 u32 npriority_lvl; 664 const u32 *priority_lvl; 665 }; 666 667 /** 668 * struct dpu_vbif_cfg - information of VBIF blocks 669 * @id enum identifying this block 670 * @base register offset of this block 671 * @features bit mask identifying sub-blocks/features 672 * @ot_rd_limit default OT read limit 673 * @ot_wr_limit default OT write limit 674 * @xin_halt_timeout maximum time (in usec) for xin to halt 675 * @qos_rp_remap_size size of VBIF_XINL_QOS_RP_REMAP register space 676 * @dynamic_ot_rd_tbl dynamic OT read configuration table 677 * @dynamic_ot_wr_tbl dynamic OT write configuration table 678 * @qos_rt_tbl real-time QoS priority table 679 * @qos_nrt_tbl non-real-time QoS priority table 680 * @memtype_count number of defined memtypes 681 * @memtype array of xin memtype definitions 682 */ 683 struct dpu_vbif_cfg { 684 DPU_HW_BLK_INFO; 685 u32 default_ot_rd_limit; 686 u32 default_ot_wr_limit; 687 u32 xin_halt_timeout; 688 u32 qos_rp_remap_size; 689 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl; 690 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl; 691 struct dpu_vbif_qos_tbl qos_rt_tbl; 692 struct dpu_vbif_qos_tbl qos_nrt_tbl; 693 u32 memtype_count; 694 u32 memtype[MAX_XIN_COUNT]; 695 }; 696 697 /** 698 * Define CDP use cases 699 * @DPU_PERF_CDP_UDAGE_RT: real-time use cases 700 * @DPU_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD 701 */ 702 enum { 703 DPU_PERF_CDP_USAGE_RT, 704 DPU_PERF_CDP_USAGE_NRT, 705 DPU_PERF_CDP_USAGE_MAX 706 }; 707 708 /** 709 * struct dpu_perf_cdp_cfg - define CDP use case configuration 710 * @rd_enable: true if read pipe CDP is enabled 711 * @wr_enable: true if write pipe CDP is enabled 712 */ 713 struct dpu_perf_cdp_cfg { 714 bool rd_enable; 715 bool wr_enable; 716 }; 717 718 /** 719 * struct dpu_mdss_version - DPU's major and minor versions 720 * @core_major_ver: DPU core's major version 721 * @core_minor_ver: DPU core's minor version 722 */ 723 struct dpu_mdss_version { 724 u8 core_major_ver; 725 u8 core_minor_ver; 726 }; 727 728 /** 729 * struct dpu_perf_cfg - performance control settings 730 * @max_bw_low low threshold of maximum bandwidth (kbps) 731 * @max_bw_high high threshold of maximum bandwidth (kbps) 732 * @min_core_ib minimum bandwidth for core (kbps) 733 * @min_core_ib minimum mnoc ib vote in kbps 734 * @min_llcc_ib minimum llcc ib vote in kbps 735 * @min_dram_ib minimum dram ib vote in kbps 736 * @undersized_prefill_lines undersized prefill in lines 737 * @xtra_prefill_lines extra prefill latency in lines 738 * @dest_scale_prefill_lines destination scaler latency in lines 739 * @macrotile_perfill_lines macrotile latency in lines 740 * @yuv_nv12_prefill_lines yuv_nv12 latency in lines 741 * @linear_prefill_lines linear latency in lines 742 * @downscaling_prefill_lines downscaling latency in lines 743 * @amortizable_theshold minimum y position for traffic shaping prefill 744 * @min_prefill_lines minimum pipeline latency in lines 745 * @clk_inefficiency_factor DPU src clock inefficiency factor 746 * @bw_inefficiency_factor DPU axi bus bw inefficiency factor 747 * @safe_lut_tbl: LUT tables for safe signals 748 * @danger_lut_tbl: LUT tables for danger signals 749 * @qos_lut_tbl: LUT tables for QoS signals 750 * @cdp_cfg cdp use case configurations 751 */ 752 struct dpu_perf_cfg { 753 u32 max_bw_low; 754 u32 max_bw_high; 755 u32 min_core_ib; 756 u32 min_llcc_ib; 757 u32 min_dram_ib; 758 u32 undersized_prefill_lines; 759 u32 xtra_prefill_lines; 760 u32 dest_scale_prefill_lines; 761 u32 macrotile_prefill_lines; 762 u32 yuv_nv12_prefill_lines; 763 u32 linear_prefill_lines; 764 u32 downscaling_prefill_lines; 765 u32 amortizable_threshold; 766 u32 min_prefill_lines; 767 u32 clk_inefficiency_factor; 768 u32 bw_inefficiency_factor; 769 u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 770 u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 771 struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 772 struct dpu_perf_cdp_cfg cdp_cfg[DPU_PERF_CDP_USAGE_MAX]; 773 }; 774 775 /** 776 * struct dpu_mdss_cfg - information of MDSS HW 777 * This is the main catalog data structure representing 778 * this HW version. Contains dpu's major and minor versions, 779 * number of instances, register offsets, capabilities of the 780 * all MDSS HW sub-blocks. 781 * 782 * @dma_formats Supported formats for dma pipe 783 * @cursor_formats Supported formats for cursor pipe 784 * @vig_formats Supported formats for vig pipe 785 */ 786 struct dpu_mdss_cfg { 787 const struct dpu_mdss_version *mdss_ver; 788 789 const struct dpu_caps *caps; 790 791 const struct dpu_mdp_cfg *mdp; 792 793 u32 ctl_count; 794 const struct dpu_ctl_cfg *ctl; 795 796 u32 sspp_count; 797 const struct dpu_sspp_cfg *sspp; 798 799 u32 mixer_count; 800 const struct dpu_lm_cfg *mixer; 801 802 u32 pingpong_count; 803 const struct dpu_pingpong_cfg *pingpong; 804 805 u32 merge_3d_count; 806 const struct dpu_merge_3d_cfg *merge_3d; 807 808 u32 dsc_count; 809 const struct dpu_dsc_cfg *dsc; 810 811 u32 intf_count; 812 const struct dpu_intf_cfg *intf; 813 814 u32 vbif_count; 815 const struct dpu_vbif_cfg *vbif; 816 817 u32 wb_count; 818 const struct dpu_wb_cfg *wb; 819 820 u32 ad_count; 821 822 u32 dspp_count; 823 const struct dpu_dspp_cfg *dspp; 824 825 /* Add additional block data structures here */ 826 827 const struct dpu_perf_cfg *perf; 828 const struct dpu_format_extended *dma_formats; 829 const struct dpu_format_extended *cursor_formats; 830 const struct dpu_format_extended *vig_formats; 831 }; 832 833 extern const struct dpu_mdss_cfg dpu_msm8998_cfg; 834 extern const struct dpu_mdss_cfg dpu_sdm845_cfg; 835 extern const struct dpu_mdss_cfg dpu_sm8150_cfg; 836 extern const struct dpu_mdss_cfg dpu_sc8180x_cfg; 837 extern const struct dpu_mdss_cfg dpu_sm8250_cfg; 838 extern const struct dpu_mdss_cfg dpu_sc7180_cfg; 839 extern const struct dpu_mdss_cfg dpu_sm6115_cfg; 840 extern const struct dpu_mdss_cfg dpu_sm6125_cfg; 841 extern const struct dpu_mdss_cfg dpu_sm6350_cfg; 842 extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; 843 extern const struct dpu_mdss_cfg dpu_sm6375_cfg; 844 extern const struct dpu_mdss_cfg dpu_sm8350_cfg; 845 extern const struct dpu_mdss_cfg dpu_sc7280_cfg; 846 extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg; 847 extern const struct dpu_mdss_cfg dpu_sm8450_cfg; 848 extern const struct dpu_mdss_cfg dpu_sm8550_cfg; 849 850 #endif /* _DPU_HW_CATALOG_H */ 851