1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * iio/adc/max1363.c
4 * Copyright (C) 2008-2010 Jonathan Cameron
5 *
6 * based on linux/drivers/i2c/chips/max123x
7 * Copyright (C) 2002-2004 Stefan Eletzhofer
8 *
9 * based on linux/drivers/acron/char/pcf8583.c
10 * Copyright (C) 2000 Russell King
11 *
12 * Driver for max1363 and similar chips.
13 */
14
15 #include <linux/interrupt.h>
16 #include <linux/device.h>
17 #include <linux/kernel.h>
18 #include <linux/sysfs.h>
19 #include <linux/list.h>
20 #include <linux/i2c.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/slab.h>
23 #include <linux/err.h>
24 #include <linux/module.h>
25 #include <linux/mod_devicetable.h>
26 #include <linux/property.h>
27
28 #include <linux/iio/iio.h>
29 #include <linux/iio/sysfs.h>
30 #include <linux/iio/events.h>
31 #include <linux/iio/buffer.h>
32 #include <linux/iio/kfifo_buf.h>
33 #include <linux/iio/trigger_consumer.h>
34 #include <linux/iio/triggered_buffer.h>
35
36 #define MAX1363_SETUP_BYTE(a) ((a) | 0x80)
37
38 /* There is a fair bit more defined here than currently
39 * used, but the intention is to support everything these
40 * chips do in the long run */
41
42 /* see data sheets */
43 /* max1363 and max1236, max1237, max1238, max1239 */
44 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD 0x00
45 #define MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF 0x20
46 #define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT 0x40
47 #define MAX1363_SETUP_AIN3_IS_REF_REF_IS_INT 0x60
48 #define MAX1363_SETUP_POWER_UP_INT_REF 0x10
49 #define MAX1363_SETUP_POWER_DOWN_INT_REF 0x00
50
51 /* think about including max11600 etc - more settings */
52 #define MAX1363_SETUP_EXT_CLOCK 0x08
53 #define MAX1363_SETUP_INT_CLOCK 0x00
54 #define MAX1363_SETUP_UNIPOLAR 0x00
55 #define MAX1363_SETUP_BIPOLAR 0x04
56 #define MAX1363_SETUP_RESET 0x00
57 #define MAX1363_SETUP_NORESET 0x02
58 /* max1363 only - though don't care on others.
59 * For now monitor modes are not implemented as the relevant
60 * line is not connected on my test board.
61 * The definitions are here as I intend to add this soon.
62 */
63 #define MAX1363_SETUP_MONITOR_SETUP 0x01
64
65 /* Specific to the max1363 */
66 #define MAX1363_MON_RESET_CHAN(a) (1 << ((a) + 4))
67 #define MAX1363_MON_INT_ENABLE 0x01
68
69 /* defined for readability reasons */
70 /* All chips */
71 #define MAX1363_CONFIG_BYTE(a) ((a))
72
73 #define MAX1363_CONFIG_SE 0x01
74 #define MAX1363_CONFIG_DE 0x00
75 #define MAX1363_CONFIG_SCAN_TO_CS 0x00
76 #define MAX1363_CONFIG_SCAN_SINGLE_8 0x20
77 #define MAX1363_CONFIG_SCAN_MONITOR_MODE 0x40
78 #define MAX1363_CONFIG_SCAN_SINGLE_1 0x60
79 /* max123{6-9} only */
80 #define MAX1236_SCAN_MID_TO_CHANNEL 0x40
81
82 /* max1363 only - merely part of channel selects or don't care for others */
83 #define MAX1363_CONFIG_EN_MON_MODE_READ 0x18
84
85 #define MAX1363_CHANNEL_SEL(a) ((a) << 1)
86
87 /* max1363 strictly 0x06 - but doesn't matter */
88 #define MAX1363_CHANNEL_SEL_MASK 0x1E
89 #define MAX1363_SCAN_MASK 0x60
90 #define MAX1363_SE_DE_MASK 0x01
91
92 #define MAX1363_MAX_CHANNELS 25
93 /**
94 * struct max1363_mode - scan mode information
95 * @conf: The corresponding value of the configuration register
96 * @modemask: Bit mask corresponding to channels enabled in this mode
97 */
98 struct max1363_mode {
99 int8_t conf;
100 DECLARE_BITMAP(modemask, MAX1363_MAX_CHANNELS);
101 };
102
103 /* This must be maintained along side the max1363_mode_table in max1363_core */
104 enum max1363_modes {
105 /* Single read of a single channel */
106 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
107 /* Differential single read */
108 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
109 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
110 /* Scan to channel and mid to channel where overlapping */
111 s0to1, s0to2, s2to3, s0to3, s0to4, s0to5, s0to6,
112 s6to7, s0to7, s6to8, s0to8, s6to9,
113 s0to9, s6to10, s0to10, s6to11, s0to11,
114 /* Differential scan to channel and mid to channel where overlapping */
115 d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9,
116 d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2,
117 d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8,
118 d7m6to11m10, d1m0to11m10,
119 };
120
121 /**
122 * struct max1363_chip_info - chip specifc information
123 * @info: iio core function callbacks structure
124 * @channels: channel specification
125 * @num_channels: number of channels
126 * @mode_list: array of available scan modes
127 * @default_mode: the scan mode in which the chip starts up
128 * @int_vref_mv: the internal reference voltage
129 * @num_modes: number of modes
130 * @bits: accuracy of the adc in bits
131 */
132 struct max1363_chip_info {
133 const struct iio_info *info;
134 const struct iio_chan_spec *channels;
135 int num_channels;
136 const enum max1363_modes *mode_list;
137 enum max1363_modes default_mode;
138 u16 int_vref_mv;
139 u8 num_modes;
140 u8 bits;
141 };
142
143 /**
144 * struct max1363_state - driver instance specific data
145 * @client: i2c_client
146 * @setupbyte: cache of current device setup byte
147 * @configbyte: cache of current device config byte
148 * @chip_info: chip model specific constants, available modes, etc.
149 * @current_mode: the scan mode of this chip
150 * @requestedmask: a valid requested set of channels
151 * @lock: lock to ensure state is consistent
152 * @monitor_on: whether monitor mode is enabled
153 * @monitor_speed: parameter corresponding to device monitor speed setting
154 * @mask_high: bitmask for enabled high thresholds
155 * @mask_low: bitmask for enabled low thresholds
156 * @thresh_high: high threshold values
157 * @thresh_low: low threshold values
158 * @vref: Reference voltage regulator
159 * @vref_uv: Actual (external or internal) reference voltage
160 * @send: function used to send data to the chip
161 * @recv: function used to receive data from the chip
162 */
163 struct max1363_state {
164 struct i2c_client *client;
165 u8 setupbyte;
166 u8 configbyte;
167 const struct max1363_chip_info *chip_info;
168 const struct max1363_mode *current_mode;
169 u32 requestedmask;
170 struct mutex lock;
171
172 /* Using monitor modes and buffer at the same time is
173 currently not supported */
174 bool monitor_on;
175 unsigned int monitor_speed:3;
176 u8 mask_high;
177 u8 mask_low;
178 /* 4x unipolar first then the fours bipolar ones */
179 s16 thresh_high[8];
180 s16 thresh_low[8];
181 struct regulator *vref;
182 u32 vref_uv;
183 int (*send)(const struct i2c_client *client,
184 const char *buf, int count);
185 int (*recv)(const struct i2c_client *client,
186 char *buf, int count);
187 };
188
189 #define MAX1363_MODE_SINGLE(_num, _mask) { \
190 .conf = MAX1363_CHANNEL_SEL(_num) \
191 | MAX1363_CONFIG_SCAN_SINGLE_1 \
192 | MAX1363_CONFIG_SE, \
193 .modemask[0] = _mask, \
194 }
195
196 #define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \
197 .conf = MAX1363_CHANNEL_SEL(_num) \
198 | MAX1363_CONFIG_SCAN_TO_CS \
199 | MAX1363_CONFIG_SE, \
200 .modemask[0] = _mask, \
201 }
202
203 /* note not available for max1363 hence naming */
204 #define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \
205 .conf = MAX1363_CHANNEL_SEL(_num) \
206 | MAX1236_SCAN_MID_TO_CHANNEL \
207 | MAX1363_CONFIG_SE, \
208 .modemask[0] = _mask \
209 }
210
211 #define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \
212 .conf = MAX1363_CHANNEL_SEL(_nump) \
213 | MAX1363_CONFIG_SCAN_SINGLE_1 \
214 | MAX1363_CONFIG_DE, \
215 .modemask[0] = _mask \
216 }
217
218 /* Can't think how to automate naming so specify for now */
219 #define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \
220 .conf = MAX1363_CHANNEL_SEL(_num) \
221 | MAX1363_CONFIG_SCAN_TO_CS \
222 | MAX1363_CONFIG_DE, \
223 .modemask[0] = _mask \
224 }
225
226 /* note only available for max1363 hence naming */
227 #define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \
228 .conf = MAX1363_CHANNEL_SEL(_num) \
229 | MAX1236_SCAN_MID_TO_CHANNEL \
230 | MAX1363_CONFIG_SE, \
231 .modemask[0] = _mask \
232 }
233
234 static const struct max1363_mode max1363_mode_table[] = {
235 /* All of the single channel options first */
236 MAX1363_MODE_SINGLE(0, 1 << 0),
237 MAX1363_MODE_SINGLE(1, 1 << 1),
238 MAX1363_MODE_SINGLE(2, 1 << 2),
239 MAX1363_MODE_SINGLE(3, 1 << 3),
240 MAX1363_MODE_SINGLE(4, 1 << 4),
241 MAX1363_MODE_SINGLE(5, 1 << 5),
242 MAX1363_MODE_SINGLE(6, 1 << 6),
243 MAX1363_MODE_SINGLE(7, 1 << 7),
244 MAX1363_MODE_SINGLE(8, 1 << 8),
245 MAX1363_MODE_SINGLE(9, 1 << 9),
246 MAX1363_MODE_SINGLE(10, 1 << 10),
247 MAX1363_MODE_SINGLE(11, 1 << 11),
248
249 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12),
250 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13),
251 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14),
252 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15),
253 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16),
254 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
255 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18),
256 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19),
257 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20),
258 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21),
259 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22),
260 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
261
262 /* The multichannel scans next */
263 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003),
264 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007),
265 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C),
266 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F),
267 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F),
268 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F),
269 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F),
270 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0),
271 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF),
272 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0),
273 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF),
274 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0),
275 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF),
276 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
277 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
278 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0),
279 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF),
280
281 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000),
282 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000),
283 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000),
284 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000),
285 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000),
286 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
287 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
288 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000),
289 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000),
290 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000),
291 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000),
292 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000),
293 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000),
294 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000),
295 };
296
297 static const struct max1363_mode
max1363_match_mode(const unsigned long * mask,const struct max1363_chip_info * ci)298 *max1363_match_mode(const unsigned long *mask,
299 const struct max1363_chip_info *ci)
300 {
301 int i;
302 if (mask)
303 for (i = 0; i < ci->num_modes; i++)
304 if (bitmap_subset(mask,
305 max1363_mode_table[ci->mode_list[i]].
306 modemask,
307 MAX1363_MAX_CHANNELS))
308 return &max1363_mode_table[ci->mode_list[i]];
309 return NULL;
310 }
311
max1363_smbus_send(const struct i2c_client * client,const char * buf,int count)312 static int max1363_smbus_send(const struct i2c_client *client, const char *buf,
313 int count)
314 {
315 int i, err;
316
317 for (i = err = 0; err == 0 && i < count; ++i)
318 err = i2c_smbus_write_byte(client, buf[i]);
319
320 return err ? err : count;
321 }
322
max1363_smbus_recv(const struct i2c_client * client,char * buf,int count)323 static int max1363_smbus_recv(const struct i2c_client *client, char *buf,
324 int count)
325 {
326 int i, ret;
327
328 for (i = 0; i < count; ++i) {
329 ret = i2c_smbus_read_byte(client);
330 if (ret < 0)
331 return ret;
332 buf[i] = ret;
333 }
334
335 return count;
336 }
337
max1363_write_basic_config(struct max1363_state * st)338 static int max1363_write_basic_config(struct max1363_state *st)
339 {
340 u8 tx_buf[2] = { st->setupbyte, st->configbyte };
341
342 return st->send(st->client, tx_buf, 2);
343 }
344
max1363_set_scan_mode(struct max1363_state * st)345 static int max1363_set_scan_mode(struct max1363_state *st)
346 {
347 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
348 | MAX1363_SCAN_MASK
349 | MAX1363_SE_DE_MASK);
350 st->configbyte |= st->current_mode->conf;
351
352 return max1363_write_basic_config(st);
353 }
354
max1363_read_single_chan(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,long m)355 static int max1363_read_single_chan(struct iio_dev *indio_dev,
356 struct iio_chan_spec const *chan,
357 int *val,
358 long m)
359 {
360 int ret = 0;
361 s32 data;
362 u8 rxbuf[2];
363 struct max1363_state *st = iio_priv(indio_dev);
364 struct i2c_client *client = st->client;
365
366 ret = iio_device_claim_direct_mode(indio_dev);
367 if (ret)
368 return ret;
369 mutex_lock(&st->lock);
370
371 /*
372 * If monitor mode is enabled, the method for reading a single
373 * channel will have to be rather different and has not yet
374 * been implemented.
375 *
376 * Also, cannot read directly if buffered capture enabled.
377 */
378 if (st->monitor_on) {
379 ret = -EBUSY;
380 goto error_ret;
381 }
382
383 /* Check to see if current scan mode is correct */
384 if (st->current_mode != &max1363_mode_table[chan->address]) {
385 /* Update scan mode if needed */
386 st->current_mode = &max1363_mode_table[chan->address];
387 ret = max1363_set_scan_mode(st);
388 if (ret < 0)
389 goto error_ret;
390 }
391 if (st->chip_info->bits != 8) {
392 /* Get reading */
393 data = st->recv(client, rxbuf, 2);
394 if (data < 0) {
395 ret = data;
396 goto error_ret;
397 }
398 data = (rxbuf[1] | rxbuf[0] << 8) &
399 ((1 << st->chip_info->bits) - 1);
400 } else {
401 /* Get reading */
402 data = st->recv(client, rxbuf, 1);
403 if (data < 0) {
404 ret = data;
405 goto error_ret;
406 }
407 data = rxbuf[0];
408 }
409 *val = data;
410
411 error_ret:
412 mutex_unlock(&st->lock);
413 iio_device_release_direct_mode(indio_dev);
414 return ret;
415
416 }
417
max1363_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)418 static int max1363_read_raw(struct iio_dev *indio_dev,
419 struct iio_chan_spec const *chan,
420 int *val,
421 int *val2,
422 long m)
423 {
424 struct max1363_state *st = iio_priv(indio_dev);
425 int ret;
426
427 switch (m) {
428 case IIO_CHAN_INFO_RAW:
429 ret = max1363_read_single_chan(indio_dev, chan, val, m);
430 if (ret < 0)
431 return ret;
432 return IIO_VAL_INT;
433 case IIO_CHAN_INFO_SCALE:
434 *val = st->vref_uv / 1000;
435 *val2 = st->chip_info->bits;
436 return IIO_VAL_FRACTIONAL_LOG2;
437 default:
438 return -EINVAL;
439 }
440 return 0;
441 }
442
443 /* Applies to max1363 */
444 static const enum max1363_modes max1363_mode_list[] = {
445 _s0, _s1, _s2, _s3,
446 s0to1, s0to2, s0to3,
447 d0m1, d2m3, d1m0, d3m2,
448 d0m1to2m3, d1m0to3m2,
449 };
450
451 static const struct iio_event_spec max1363_events[] = {
452 {
453 .type = IIO_EV_TYPE_THRESH,
454 .dir = IIO_EV_DIR_RISING,
455 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
456 BIT(IIO_EV_INFO_ENABLE),
457 }, {
458 .type = IIO_EV_TYPE_THRESH,
459 .dir = IIO_EV_DIR_FALLING,
460 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
461 BIT(IIO_EV_INFO_ENABLE),
462 },
463 };
464
465 #define MAX1363_CHAN_U(num, addr, si, bits, ev_spec, num_ev_spec) \
466 { \
467 .type = IIO_VOLTAGE, \
468 .indexed = 1, \
469 .channel = num, \
470 .address = addr, \
471 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
472 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
473 .datasheet_name = "AIN"#num, \
474 .scan_type = { \
475 .sign = 'u', \
476 .realbits = bits, \
477 .storagebits = (bits > 8) ? 16 : 8, \
478 .endianness = IIO_BE, \
479 }, \
480 .scan_index = si, \
481 .event_spec = ev_spec, \
482 .num_event_specs = num_ev_spec, \
483 }
484
485 /* bipolar channel */
486 #define MAX1363_CHAN_B(num, num2, addr, si, bits, ev_spec, num_ev_spec) \
487 { \
488 .type = IIO_VOLTAGE, \
489 .differential = 1, \
490 .indexed = 1, \
491 .channel = num, \
492 .channel2 = num2, \
493 .address = addr, \
494 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
495 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
496 .datasheet_name = "AIN"#num"-AIN"#num2, \
497 .scan_type = { \
498 .sign = 's', \
499 .realbits = bits, \
500 .storagebits = (bits > 8) ? 16 : 8, \
501 .endianness = IIO_BE, \
502 }, \
503 .scan_index = si, \
504 .event_spec = ev_spec, \
505 .num_event_specs = num_ev_spec, \
506 }
507
508 #define MAX1363_4X_CHANS(bits, ev_spec, num_ev_spec) { \
509 MAX1363_CHAN_U(0, _s0, 0, bits, ev_spec, num_ev_spec), \
510 MAX1363_CHAN_U(1, _s1, 1, bits, ev_spec, num_ev_spec), \
511 MAX1363_CHAN_U(2, _s2, 2, bits, ev_spec, num_ev_spec), \
512 MAX1363_CHAN_U(3, _s3, 3, bits, ev_spec, num_ev_spec), \
513 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, ev_spec, num_ev_spec), \
514 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, ev_spec, num_ev_spec), \
515 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, ev_spec, num_ev_spec), \
516 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, ev_spec, num_ev_spec), \
517 IIO_CHAN_SOFT_TIMESTAMP(8) \
518 }
519
520 static const struct iio_chan_spec max1036_channels[] =
521 MAX1363_4X_CHANS(8, NULL, 0);
522 static const struct iio_chan_spec max1136_channels[] =
523 MAX1363_4X_CHANS(10, NULL, 0);
524 static const struct iio_chan_spec max1236_channels[] =
525 MAX1363_4X_CHANS(12, NULL, 0);
526 static const struct iio_chan_spec max1361_channels[] =
527 MAX1363_4X_CHANS(10, max1363_events, ARRAY_SIZE(max1363_events));
528 static const struct iio_chan_spec max1363_channels[] =
529 MAX1363_4X_CHANS(12, max1363_events, ARRAY_SIZE(max1363_events));
530
531 /* Applies to max1236, max1237 */
532 static const enum max1363_modes max1236_mode_list[] = {
533 _s0, _s1, _s2, _s3,
534 s0to1, s0to2, s2to3, s0to3,
535 d0m1, d2m3, d1m0, d3m2,
536 d0m1to2m3, d1m0to3m2,
537 };
538
539 /* Applies to max1238, max1239 */
540 static const enum max1363_modes max1238_mode_list[] = {
541 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
542 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6,
543 s6to7, s6to8, s6to9, s6to10, s6to11,
544 s0to7, s0to8, s0to9, s0to10, s0to11,
545 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
546 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
547 d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9,
548 d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2,
549 d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8,
550 d7m6to11m10, d1m0to11m10,
551 };
552
553 #define MAX1363_12X_CHANS(bits) { \
554 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
555 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
556 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \
557 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \
558 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \
559 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \
560 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \
561 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \
562 MAX1363_CHAN_U(8, _s8, 8, bits, NULL, 0), \
563 MAX1363_CHAN_U(9, _s9, 9, bits, NULL, 0), \
564 MAX1363_CHAN_U(10, _s10, 10, bits, NULL, 0), \
565 MAX1363_CHAN_U(11, _s11, 11, bits, NULL, 0), \
566 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, NULL, 0), \
567 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, NULL, 0), \
568 MAX1363_CHAN_B(4, 5, d4m5, 14, bits, NULL, 0), \
569 MAX1363_CHAN_B(6, 7, d6m7, 15, bits, NULL, 0), \
570 MAX1363_CHAN_B(8, 9, d8m9, 16, bits, NULL, 0), \
571 MAX1363_CHAN_B(10, 11, d10m11, 17, bits, NULL, 0), \
572 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, NULL, 0), \
573 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, NULL, 0), \
574 MAX1363_CHAN_B(5, 4, d5m4, 20, bits, NULL, 0), \
575 MAX1363_CHAN_B(7, 6, d7m6, 21, bits, NULL, 0), \
576 MAX1363_CHAN_B(9, 8, d9m8, 22, bits, NULL, 0), \
577 MAX1363_CHAN_B(11, 10, d11m10, 23, bits, NULL, 0), \
578 IIO_CHAN_SOFT_TIMESTAMP(24) \
579 }
580 static const struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
581 static const struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
582 static const struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
583
584 static const enum max1363_modes max11607_mode_list[] = {
585 _s0, _s1, _s2, _s3,
586 s0to1, s0to2, s2to3,
587 s0to3,
588 d0m1, d2m3, d1m0, d3m2,
589 d0m1to2m3, d1m0to3m2,
590 };
591
592 static const enum max1363_modes max11608_mode_list[] = {
593 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7,
594 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s6to7, s0to7,
595 d0m1, d2m3, d4m5, d6m7,
596 d1m0, d3m2, d5m4, d7m6,
597 d0m1to2m3, d0m1to4m5, d0m1to6m7,
598 d1m0to3m2, d1m0to5m4, d1m0to7m6,
599 };
600
601 #define MAX1363_8X_CHANS(bits) { \
602 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
603 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
604 MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0), \
605 MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0), \
606 MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0), \
607 MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0), \
608 MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0), \
609 MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0), \
610 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, NULL, 0), \
611 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, NULL, 0), \
612 MAX1363_CHAN_B(4, 5, d4m5, 14, bits, NULL, 0), \
613 MAX1363_CHAN_B(6, 7, d6m7, 15, bits, NULL, 0), \
614 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, NULL, 0), \
615 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, NULL, 0), \
616 MAX1363_CHAN_B(5, 4, d5m4, 20, bits, NULL, 0), \
617 MAX1363_CHAN_B(7, 6, d7m6, 21, bits, NULL, 0), \
618 IIO_CHAN_SOFT_TIMESTAMP(16) \
619 }
620 static const struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
621 static const struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
622 static const struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
623
624 static const enum max1363_modes max11644_mode_list[] = {
625 _s0, _s1, s0to1, d0m1, d1m0,
626 };
627
628 #define MAX1363_2X_CHANS(bits) { \
629 MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0), \
630 MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0), \
631 MAX1363_CHAN_B(0, 1, d0m1, 2, bits, NULL, 0), \
632 MAX1363_CHAN_B(1, 0, d1m0, 3, bits, NULL, 0), \
633 IIO_CHAN_SOFT_TIMESTAMP(4) \
634 }
635
636 static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
637 static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
638
639 enum { max1361,
640 max1362,
641 max1363,
642 max1364,
643 max1036,
644 max1037,
645 max1038,
646 max1039,
647 max1136,
648 max1137,
649 max1138,
650 max1139,
651 max1236,
652 max1237,
653 max1238,
654 max1239,
655 max11600,
656 max11601,
657 max11602,
658 max11603,
659 max11604,
660 max11605,
661 max11606,
662 max11607,
663 max11608,
664 max11609,
665 max11610,
666 max11611,
667 max11612,
668 max11613,
669 max11614,
670 max11615,
671 max11616,
672 max11617,
673 max11644,
674 max11645,
675 max11646,
676 max11647
677 };
678
679 static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
680 8300, 4200, 2000, 1000 };
681
max1363_monitor_show_freq(struct device * dev,struct device_attribute * attr,char * buf)682 static ssize_t max1363_monitor_show_freq(struct device *dev,
683 struct device_attribute *attr,
684 char *buf)
685 {
686 struct max1363_state *st = iio_priv(dev_to_iio_dev(dev));
687 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]);
688 }
689
max1363_monitor_store_freq(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)690 static ssize_t max1363_monitor_store_freq(struct device *dev,
691 struct device_attribute *attr,
692 const char *buf,
693 size_t len)
694 {
695 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
696 struct max1363_state *st = iio_priv(indio_dev);
697 int i, ret;
698 unsigned long val;
699 bool found = false;
700
701 ret = kstrtoul(buf, 10, &val);
702 if (ret)
703 return -EINVAL;
704 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++)
705 if (val == max1363_monitor_speeds[i]) {
706 found = true;
707 break;
708 }
709 if (!found)
710 return -EINVAL;
711
712 mutex_lock(&st->lock);
713 st->monitor_speed = i;
714 mutex_unlock(&st->lock);
715
716 return 0;
717 }
718
719 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR,
720 max1363_monitor_show_freq,
721 max1363_monitor_store_freq);
722
723 static IIO_CONST_ATTR(sampling_frequency_available,
724 "133000 665000 33300 16600 8300 4200 2000 1000");
725
max1363_read_thresh(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)726 static int max1363_read_thresh(struct iio_dev *indio_dev,
727 const struct iio_chan_spec *chan, enum iio_event_type type,
728 enum iio_event_direction dir, enum iio_event_info info, int *val,
729 int *val2)
730 {
731 struct max1363_state *st = iio_priv(indio_dev);
732 if (dir == IIO_EV_DIR_FALLING)
733 *val = st->thresh_low[chan->channel];
734 else
735 *val = st->thresh_high[chan->channel];
736 return IIO_VAL_INT;
737 }
738
max1363_write_thresh(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)739 static int max1363_write_thresh(struct iio_dev *indio_dev,
740 const struct iio_chan_spec *chan, enum iio_event_type type,
741 enum iio_event_direction dir, enum iio_event_info info, int val,
742 int val2)
743 {
744 struct max1363_state *st = iio_priv(indio_dev);
745 /* make it handle signed correctly as well */
746 switch (st->chip_info->bits) {
747 case 10:
748 if (val > 0x3FF)
749 return -EINVAL;
750 break;
751 case 12:
752 if (val > 0xFFF)
753 return -EINVAL;
754 break;
755 }
756
757 switch (dir) {
758 case IIO_EV_DIR_FALLING:
759 st->thresh_low[chan->channel] = val;
760 break;
761 case IIO_EV_DIR_RISING:
762 st->thresh_high[chan->channel] = val;
763 break;
764 default:
765 return -EINVAL;
766 }
767
768 return 0;
769 }
770
771 static const u64 max1363_event_codes[] = {
772 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
773 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
774 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
775 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
776 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
777 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
778 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
779 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
780 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
781 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
782 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
783 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
784 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
785 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
786 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
787 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
788 };
789
max1363_event_handler(int irq,void * private)790 static irqreturn_t max1363_event_handler(int irq, void *private)
791 {
792 struct iio_dev *indio_dev = private;
793 struct max1363_state *st = iio_priv(indio_dev);
794 s64 timestamp = iio_get_time_ns(indio_dev);
795 unsigned long mask, loc;
796 u8 rx;
797 u8 tx[2] = { st->setupbyte,
798 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
799
800 st->recv(st->client, &rx, 1);
801 mask = rx;
802 for_each_set_bit(loc, &mask, 8)
803 iio_push_event(indio_dev, max1363_event_codes[loc], timestamp);
804 st->send(st->client, tx, 2);
805
806 return IRQ_HANDLED;
807 }
808
max1363_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)809 static int max1363_read_event_config(struct iio_dev *indio_dev,
810 const struct iio_chan_spec *chan, enum iio_event_type type,
811 enum iio_event_direction dir)
812 {
813 struct max1363_state *st = iio_priv(indio_dev);
814 int val;
815 int number = chan->channel;
816
817 mutex_lock(&st->lock);
818 if (dir == IIO_EV_DIR_FALLING)
819 val = (1 << number) & st->mask_low;
820 else
821 val = (1 << number) & st->mask_high;
822 mutex_unlock(&st->lock);
823
824 return val;
825 }
826
max1363_monitor_mode_update(struct max1363_state * st,int enabled)827 static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
828 {
829 u8 *tx_buf;
830 int ret, i = 3, j;
831 unsigned long numelements;
832 int len;
833 const long *modemask;
834
835 if (!enabled) {
836 /* transition to buffered capture is not currently supported */
837 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP;
838 st->configbyte &= ~MAX1363_SCAN_MASK;
839 st->monitor_on = false;
840 return max1363_write_basic_config(st);
841 }
842
843 /* Ensure we are in the relevant mode */
844 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP;
845 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
846 | MAX1363_SCAN_MASK
847 | MAX1363_SE_DE_MASK);
848 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE;
849 if ((st->mask_low | st->mask_high) & 0x0F) {
850 st->configbyte |= max1363_mode_table[s0to3].conf;
851 modemask = max1363_mode_table[s0to3].modemask;
852 } else if ((st->mask_low | st->mask_high) & 0x30) {
853 st->configbyte |= max1363_mode_table[d0m1to2m3].conf;
854 modemask = max1363_mode_table[d0m1to2m3].modemask;
855 } else {
856 st->configbyte |= max1363_mode_table[d1m0to3m2].conf;
857 modemask = max1363_mode_table[d1m0to3m2].modemask;
858 }
859 numelements = bitmap_weight(modemask, MAX1363_MAX_CHANNELS);
860 len = 3 * numelements + 3;
861 tx_buf = kmalloc(len, GFP_KERNEL);
862 if (!tx_buf) {
863 ret = -ENOMEM;
864 goto error_ret;
865 }
866 tx_buf[0] = st->configbyte;
867 tx_buf[1] = st->setupbyte;
868 tx_buf[2] = (st->monitor_speed << 1);
869
870 /*
871 * So we need to do yet another bit of nefarious scan mode
872 * setup to match what we need.
873 */
874 for (j = 0; j < 8; j++)
875 if (test_bit(j, modemask)) {
876 /* Establish the mode is in the scan */
877 if (st->mask_low & (1 << j)) {
878 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF;
879 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0;
880 } else if (j < 4) {
881 tx_buf[i] = 0;
882 tx_buf[i + 1] = 0;
883 } else {
884 tx_buf[i] = 0x80;
885 tx_buf[i + 1] = 0;
886 }
887 if (st->mask_high & (1 << j)) {
888 tx_buf[i + 1] |=
889 (st->thresh_high[j] >> 8) & 0x0F;
890 tx_buf[i + 2] = st->thresh_high[j] & 0xFF;
891 } else if (j < 4) {
892 tx_buf[i + 1] |= 0x0F;
893 tx_buf[i + 2] = 0xFF;
894 } else {
895 tx_buf[i + 1] |= 0x07;
896 tx_buf[i + 2] = 0xFF;
897 }
898 i += 3;
899 }
900
901
902 ret = st->send(st->client, tx_buf, len);
903 if (ret < 0)
904 goto error_ret;
905 if (ret != len) {
906 ret = -EIO;
907 goto error_ret;
908 }
909
910 /*
911 * Now that we hopefully have sensible thresholds in place it is
912 * time to turn the interrupts on.
913 * It is unclear from the data sheet if this should be necessary
914 * (i.e. whether monitor mode setup is atomic) but it appears to
915 * be in practice.
916 */
917 tx_buf[0] = st->setupbyte;
918 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0;
919 ret = st->send(st->client, tx_buf, 2);
920 if (ret < 0)
921 goto error_ret;
922 if (ret != 2) {
923 ret = -EIO;
924 goto error_ret;
925 }
926 ret = 0;
927 st->monitor_on = true;
928 error_ret:
929
930 kfree(tx_buf);
931
932 return ret;
933 }
934
935 /*
936 * To keep this manageable we always use one of 3 scan modes.
937 * Scan 0...3, 0-1,2-3 and 1-0,3-2
938 */
939
__max1363_check_event_mask(int thismask,int checkmask)940 static inline int __max1363_check_event_mask(int thismask, int checkmask)
941 {
942 int ret = 0;
943 /* Is it unipolar */
944 if (thismask < 4) {
945 if (checkmask & ~0x0F) {
946 ret = -EBUSY;
947 goto error_ret;
948 }
949 } else if (thismask < 6) {
950 if (checkmask & ~0x30) {
951 ret = -EBUSY;
952 goto error_ret;
953 }
954 } else if (checkmask & ~0xC0)
955 ret = -EBUSY;
956 error_ret:
957 return ret;
958 }
959
max1363_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)960 static int max1363_write_event_config(struct iio_dev *indio_dev,
961 const struct iio_chan_spec *chan, enum iio_event_type type,
962 enum iio_event_direction dir, int state)
963 {
964 int ret = 0;
965 struct max1363_state *st = iio_priv(indio_dev);
966 u16 unifiedmask;
967 int number = chan->channel;
968
969 ret = iio_device_claim_direct_mode(indio_dev);
970 if (ret)
971 return ret;
972 mutex_lock(&st->lock);
973
974 unifiedmask = st->mask_low | st->mask_high;
975 if (dir == IIO_EV_DIR_FALLING) {
976
977 if (state == 0)
978 st->mask_low &= ~(1 << number);
979 else {
980 ret = __max1363_check_event_mask((1 << number),
981 unifiedmask);
982 if (ret)
983 goto error_ret;
984 st->mask_low |= (1 << number);
985 }
986 } else {
987 if (state == 0)
988 st->mask_high &= ~(1 << number);
989 else {
990 ret = __max1363_check_event_mask((1 << number),
991 unifiedmask);
992 if (ret)
993 goto error_ret;
994 st->mask_high |= (1 << number);
995 }
996 }
997
998 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low));
999 error_ret:
1000 mutex_unlock(&st->lock);
1001 iio_device_release_direct_mode(indio_dev);
1002
1003 return ret;
1004 }
1005
1006 /*
1007 * As with scan_elements, only certain sets of these can
1008 * be combined.
1009 */
1010 static struct attribute *max1363_event_attributes[] = {
1011 &iio_dev_attr_sampling_frequency.dev_attr.attr,
1012 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
1013 NULL,
1014 };
1015
1016 static const struct attribute_group max1363_event_attribute_group = {
1017 .attrs = max1363_event_attributes,
1018 };
1019
max1363_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)1020 static int max1363_update_scan_mode(struct iio_dev *indio_dev,
1021 const unsigned long *scan_mask)
1022 {
1023 struct max1363_state *st = iio_priv(indio_dev);
1024
1025 /*
1026 * Need to figure out the current mode based upon the requested
1027 * scan mask in iio_dev
1028 */
1029 st->current_mode = max1363_match_mode(scan_mask, st->chip_info);
1030 if (!st->current_mode)
1031 return -EINVAL;
1032 max1363_set_scan_mode(st);
1033 return 0;
1034 }
1035
1036 static const struct iio_info max1238_info = {
1037 .read_raw = &max1363_read_raw,
1038 .update_scan_mode = &max1363_update_scan_mode,
1039 };
1040
1041 static const struct iio_info max1363_info = {
1042 .read_event_value = &max1363_read_thresh,
1043 .write_event_value = &max1363_write_thresh,
1044 .read_event_config = &max1363_read_event_config,
1045 .write_event_config = &max1363_write_event_config,
1046 .read_raw = &max1363_read_raw,
1047 .update_scan_mode = &max1363_update_scan_mode,
1048 .event_attrs = &max1363_event_attribute_group,
1049 };
1050
1051 /* max1363 and max1368 tested - rest from data sheet */
1052 static const struct max1363_chip_info max1363_chip_info_tbl[] = {
1053 [max1361] = {
1054 .bits = 10,
1055 .int_vref_mv = 2048,
1056 .mode_list = max1363_mode_list,
1057 .num_modes = ARRAY_SIZE(max1363_mode_list),
1058 .default_mode = s0to3,
1059 .channels = max1361_channels,
1060 .num_channels = ARRAY_SIZE(max1361_channels),
1061 .info = &max1363_info,
1062 },
1063 [max1362] = {
1064 .bits = 10,
1065 .int_vref_mv = 4096,
1066 .mode_list = max1363_mode_list,
1067 .num_modes = ARRAY_SIZE(max1363_mode_list),
1068 .default_mode = s0to3,
1069 .channels = max1361_channels,
1070 .num_channels = ARRAY_SIZE(max1361_channels),
1071 .info = &max1363_info,
1072 },
1073 [max1363] = {
1074 .bits = 12,
1075 .int_vref_mv = 2048,
1076 .mode_list = max1363_mode_list,
1077 .num_modes = ARRAY_SIZE(max1363_mode_list),
1078 .default_mode = s0to3,
1079 .channels = max1363_channels,
1080 .num_channels = ARRAY_SIZE(max1363_channels),
1081 .info = &max1363_info,
1082 },
1083 [max1364] = {
1084 .bits = 12,
1085 .int_vref_mv = 4096,
1086 .mode_list = max1363_mode_list,
1087 .num_modes = ARRAY_SIZE(max1363_mode_list),
1088 .default_mode = s0to3,
1089 .channels = max1363_channels,
1090 .num_channels = ARRAY_SIZE(max1363_channels),
1091 .info = &max1363_info,
1092 },
1093 [max1036] = {
1094 .bits = 8,
1095 .int_vref_mv = 4096,
1096 .mode_list = max1236_mode_list,
1097 .num_modes = ARRAY_SIZE(max1236_mode_list),
1098 .default_mode = s0to3,
1099 .info = &max1238_info,
1100 .channels = max1036_channels,
1101 .num_channels = ARRAY_SIZE(max1036_channels),
1102 },
1103 [max1037] = {
1104 .bits = 8,
1105 .int_vref_mv = 2048,
1106 .mode_list = max1236_mode_list,
1107 .num_modes = ARRAY_SIZE(max1236_mode_list),
1108 .default_mode = s0to3,
1109 .info = &max1238_info,
1110 .channels = max1036_channels,
1111 .num_channels = ARRAY_SIZE(max1036_channels),
1112 },
1113 [max1038] = {
1114 .bits = 8,
1115 .int_vref_mv = 4096,
1116 .mode_list = max1238_mode_list,
1117 .num_modes = ARRAY_SIZE(max1238_mode_list),
1118 .default_mode = s0to11,
1119 .info = &max1238_info,
1120 .channels = max1038_channels,
1121 .num_channels = ARRAY_SIZE(max1038_channels),
1122 },
1123 [max1039] = {
1124 .bits = 8,
1125 .int_vref_mv = 2048,
1126 .mode_list = max1238_mode_list,
1127 .num_modes = ARRAY_SIZE(max1238_mode_list),
1128 .default_mode = s0to11,
1129 .info = &max1238_info,
1130 .channels = max1038_channels,
1131 .num_channels = ARRAY_SIZE(max1038_channels),
1132 },
1133 [max1136] = {
1134 .bits = 10,
1135 .int_vref_mv = 4096,
1136 .mode_list = max1236_mode_list,
1137 .num_modes = ARRAY_SIZE(max1236_mode_list),
1138 .default_mode = s0to3,
1139 .info = &max1238_info,
1140 .channels = max1136_channels,
1141 .num_channels = ARRAY_SIZE(max1136_channels),
1142 },
1143 [max1137] = {
1144 .bits = 10,
1145 .int_vref_mv = 2048,
1146 .mode_list = max1236_mode_list,
1147 .num_modes = ARRAY_SIZE(max1236_mode_list),
1148 .default_mode = s0to3,
1149 .info = &max1238_info,
1150 .channels = max1136_channels,
1151 .num_channels = ARRAY_SIZE(max1136_channels),
1152 },
1153 [max1138] = {
1154 .bits = 10,
1155 .int_vref_mv = 4096,
1156 .mode_list = max1238_mode_list,
1157 .num_modes = ARRAY_SIZE(max1238_mode_list),
1158 .default_mode = s0to11,
1159 .info = &max1238_info,
1160 .channels = max1138_channels,
1161 .num_channels = ARRAY_SIZE(max1138_channels),
1162 },
1163 [max1139] = {
1164 .bits = 10,
1165 .int_vref_mv = 2048,
1166 .mode_list = max1238_mode_list,
1167 .num_modes = ARRAY_SIZE(max1238_mode_list),
1168 .default_mode = s0to11,
1169 .info = &max1238_info,
1170 .channels = max1138_channels,
1171 .num_channels = ARRAY_SIZE(max1138_channels),
1172 },
1173 [max1236] = {
1174 .bits = 12,
1175 .int_vref_mv = 4096,
1176 .mode_list = max1236_mode_list,
1177 .num_modes = ARRAY_SIZE(max1236_mode_list),
1178 .default_mode = s0to3,
1179 .info = &max1238_info,
1180 .channels = max1236_channels,
1181 .num_channels = ARRAY_SIZE(max1236_channels),
1182 },
1183 [max1237] = {
1184 .bits = 12,
1185 .int_vref_mv = 2048,
1186 .mode_list = max1236_mode_list,
1187 .num_modes = ARRAY_SIZE(max1236_mode_list),
1188 .default_mode = s0to3,
1189 .info = &max1238_info,
1190 .channels = max1236_channels,
1191 .num_channels = ARRAY_SIZE(max1236_channels),
1192 },
1193 [max1238] = {
1194 .bits = 12,
1195 .int_vref_mv = 4096,
1196 .mode_list = max1238_mode_list,
1197 .num_modes = ARRAY_SIZE(max1238_mode_list),
1198 .default_mode = s0to11,
1199 .info = &max1238_info,
1200 .channels = max1238_channels,
1201 .num_channels = ARRAY_SIZE(max1238_channels),
1202 },
1203 [max1239] = {
1204 .bits = 12,
1205 .int_vref_mv = 2048,
1206 .mode_list = max1238_mode_list,
1207 .num_modes = ARRAY_SIZE(max1238_mode_list),
1208 .default_mode = s0to11,
1209 .info = &max1238_info,
1210 .channels = max1238_channels,
1211 .num_channels = ARRAY_SIZE(max1238_channels),
1212 },
1213 [max11600] = {
1214 .bits = 8,
1215 .int_vref_mv = 4096,
1216 .mode_list = max11607_mode_list,
1217 .num_modes = ARRAY_SIZE(max11607_mode_list),
1218 .default_mode = s0to3,
1219 .info = &max1238_info,
1220 .channels = max1036_channels,
1221 .num_channels = ARRAY_SIZE(max1036_channels),
1222 },
1223 [max11601] = {
1224 .bits = 8,
1225 .int_vref_mv = 2048,
1226 .mode_list = max11607_mode_list,
1227 .num_modes = ARRAY_SIZE(max11607_mode_list),
1228 .default_mode = s0to3,
1229 .info = &max1238_info,
1230 .channels = max1036_channels,
1231 .num_channels = ARRAY_SIZE(max1036_channels),
1232 },
1233 [max11602] = {
1234 .bits = 8,
1235 .int_vref_mv = 4096,
1236 .mode_list = max11608_mode_list,
1237 .num_modes = ARRAY_SIZE(max11608_mode_list),
1238 .default_mode = s0to7,
1239 .info = &max1238_info,
1240 .channels = max11602_channels,
1241 .num_channels = ARRAY_SIZE(max11602_channels),
1242 },
1243 [max11603] = {
1244 .bits = 8,
1245 .int_vref_mv = 2048,
1246 .mode_list = max11608_mode_list,
1247 .num_modes = ARRAY_SIZE(max11608_mode_list),
1248 .default_mode = s0to7,
1249 .info = &max1238_info,
1250 .channels = max11602_channels,
1251 .num_channels = ARRAY_SIZE(max11602_channels),
1252 },
1253 [max11604] = {
1254 .bits = 8,
1255 .int_vref_mv = 4096,
1256 .mode_list = max1238_mode_list,
1257 .num_modes = ARRAY_SIZE(max1238_mode_list),
1258 .default_mode = s0to11,
1259 .info = &max1238_info,
1260 .channels = max1038_channels,
1261 .num_channels = ARRAY_SIZE(max1038_channels),
1262 },
1263 [max11605] = {
1264 .bits = 8,
1265 .int_vref_mv = 2048,
1266 .mode_list = max1238_mode_list,
1267 .num_modes = ARRAY_SIZE(max1238_mode_list),
1268 .default_mode = s0to11,
1269 .info = &max1238_info,
1270 .channels = max1038_channels,
1271 .num_channels = ARRAY_SIZE(max1038_channels),
1272 },
1273 [max11606] = {
1274 .bits = 10,
1275 .int_vref_mv = 4096,
1276 .mode_list = max11607_mode_list,
1277 .num_modes = ARRAY_SIZE(max11607_mode_list),
1278 .default_mode = s0to3,
1279 .info = &max1238_info,
1280 .channels = max1136_channels,
1281 .num_channels = ARRAY_SIZE(max1136_channels),
1282 },
1283 [max11607] = {
1284 .bits = 10,
1285 .int_vref_mv = 2048,
1286 .mode_list = max11607_mode_list,
1287 .num_modes = ARRAY_SIZE(max11607_mode_list),
1288 .default_mode = s0to3,
1289 .info = &max1238_info,
1290 .channels = max1136_channels,
1291 .num_channels = ARRAY_SIZE(max1136_channels),
1292 },
1293 [max11608] = {
1294 .bits = 10,
1295 .int_vref_mv = 4096,
1296 .mode_list = max11608_mode_list,
1297 .num_modes = ARRAY_SIZE(max11608_mode_list),
1298 .default_mode = s0to7,
1299 .info = &max1238_info,
1300 .channels = max11608_channels,
1301 .num_channels = ARRAY_SIZE(max11608_channels),
1302 },
1303 [max11609] = {
1304 .bits = 10,
1305 .int_vref_mv = 2048,
1306 .mode_list = max11608_mode_list,
1307 .num_modes = ARRAY_SIZE(max11608_mode_list),
1308 .default_mode = s0to7,
1309 .info = &max1238_info,
1310 .channels = max11608_channels,
1311 .num_channels = ARRAY_SIZE(max11608_channels),
1312 },
1313 [max11610] = {
1314 .bits = 10,
1315 .int_vref_mv = 4096,
1316 .mode_list = max1238_mode_list,
1317 .num_modes = ARRAY_SIZE(max1238_mode_list),
1318 .default_mode = s0to11,
1319 .info = &max1238_info,
1320 .channels = max1138_channels,
1321 .num_channels = ARRAY_SIZE(max1138_channels),
1322 },
1323 [max11611] = {
1324 .bits = 10,
1325 .int_vref_mv = 2048,
1326 .mode_list = max1238_mode_list,
1327 .num_modes = ARRAY_SIZE(max1238_mode_list),
1328 .default_mode = s0to11,
1329 .info = &max1238_info,
1330 .channels = max1138_channels,
1331 .num_channels = ARRAY_SIZE(max1138_channels),
1332 },
1333 [max11612] = {
1334 .bits = 12,
1335 .int_vref_mv = 4096,
1336 .mode_list = max11607_mode_list,
1337 .num_modes = ARRAY_SIZE(max11607_mode_list),
1338 .default_mode = s0to3,
1339 .info = &max1238_info,
1340 .channels = max1363_channels,
1341 .num_channels = ARRAY_SIZE(max1363_channels),
1342 },
1343 [max11613] = {
1344 .bits = 12,
1345 .int_vref_mv = 2048,
1346 .mode_list = max11607_mode_list,
1347 .num_modes = ARRAY_SIZE(max11607_mode_list),
1348 .default_mode = s0to3,
1349 .info = &max1238_info,
1350 .channels = max1363_channels,
1351 .num_channels = ARRAY_SIZE(max1363_channels),
1352 },
1353 [max11614] = {
1354 .bits = 12,
1355 .int_vref_mv = 4096,
1356 .mode_list = max11608_mode_list,
1357 .num_modes = ARRAY_SIZE(max11608_mode_list),
1358 .default_mode = s0to7,
1359 .info = &max1238_info,
1360 .channels = max11614_channels,
1361 .num_channels = ARRAY_SIZE(max11614_channels),
1362 },
1363 [max11615] = {
1364 .bits = 12,
1365 .int_vref_mv = 2048,
1366 .mode_list = max11608_mode_list,
1367 .num_modes = ARRAY_SIZE(max11608_mode_list),
1368 .default_mode = s0to7,
1369 .info = &max1238_info,
1370 .channels = max11614_channels,
1371 .num_channels = ARRAY_SIZE(max11614_channels),
1372 },
1373 [max11616] = {
1374 .bits = 12,
1375 .int_vref_mv = 4096,
1376 .mode_list = max1238_mode_list,
1377 .num_modes = ARRAY_SIZE(max1238_mode_list),
1378 .default_mode = s0to11,
1379 .info = &max1238_info,
1380 .channels = max1238_channels,
1381 .num_channels = ARRAY_SIZE(max1238_channels),
1382 },
1383 [max11617] = {
1384 .bits = 12,
1385 .int_vref_mv = 2048,
1386 .mode_list = max1238_mode_list,
1387 .num_modes = ARRAY_SIZE(max1238_mode_list),
1388 .default_mode = s0to11,
1389 .info = &max1238_info,
1390 .channels = max1238_channels,
1391 .num_channels = ARRAY_SIZE(max1238_channels),
1392 },
1393 [max11644] = {
1394 .bits = 12,
1395 .int_vref_mv = 4096,
1396 .mode_list = max11644_mode_list,
1397 .num_modes = ARRAY_SIZE(max11644_mode_list),
1398 .default_mode = s0to1,
1399 .info = &max1238_info,
1400 .channels = max11644_channels,
1401 .num_channels = ARRAY_SIZE(max11644_channels),
1402 },
1403 [max11645] = {
1404 .bits = 12,
1405 .int_vref_mv = 2048,
1406 .mode_list = max11644_mode_list,
1407 .num_modes = ARRAY_SIZE(max11644_mode_list),
1408 .default_mode = s0to1,
1409 .info = &max1238_info,
1410 .channels = max11644_channels,
1411 .num_channels = ARRAY_SIZE(max11644_channels),
1412 },
1413 [max11646] = {
1414 .bits = 10,
1415 .int_vref_mv = 4096,
1416 .mode_list = max11644_mode_list,
1417 .num_modes = ARRAY_SIZE(max11644_mode_list),
1418 .default_mode = s0to1,
1419 .info = &max1238_info,
1420 .channels = max11646_channels,
1421 .num_channels = ARRAY_SIZE(max11646_channels),
1422 },
1423 [max11647] = {
1424 .bits = 10,
1425 .int_vref_mv = 2048,
1426 .mode_list = max11644_mode_list,
1427 .num_modes = ARRAY_SIZE(max11644_mode_list),
1428 .default_mode = s0to1,
1429 .info = &max1238_info,
1430 .channels = max11646_channels,
1431 .num_channels = ARRAY_SIZE(max11646_channels),
1432 },
1433 };
1434
max1363_initial_setup(struct max1363_state * st)1435 static int max1363_initial_setup(struct max1363_state *st)
1436 {
1437 st->setupbyte = MAX1363_SETUP_INT_CLOCK
1438 | MAX1363_SETUP_UNIPOLAR
1439 | MAX1363_SETUP_NORESET;
1440
1441 if (st->vref)
1442 st->setupbyte |= MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF;
1443 else
1444 st->setupbyte |= MAX1363_SETUP_POWER_UP_INT_REF
1445 | MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT;
1446
1447 /* Set scan mode writes the config anyway so wait until then */
1448 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte);
1449 st->current_mode = &max1363_mode_table[st->chip_info->default_mode];
1450 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte);
1451
1452 return max1363_set_scan_mode(st);
1453 }
1454
max1363_alloc_scan_masks(struct iio_dev * indio_dev)1455 static int max1363_alloc_scan_masks(struct iio_dev *indio_dev)
1456 {
1457 struct max1363_state *st = iio_priv(indio_dev);
1458 unsigned long *masks;
1459 int i;
1460
1461 masks = devm_kzalloc(&indio_dev->dev,
1462 array3_size(BITS_TO_LONGS(MAX1363_MAX_CHANNELS),
1463 sizeof(long),
1464 st->chip_info->num_modes + 1),
1465 GFP_KERNEL);
1466 if (!masks)
1467 return -ENOMEM;
1468
1469 for (i = 0; i < st->chip_info->num_modes; i++)
1470 bitmap_copy(masks + BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i,
1471 max1363_mode_table[st->chip_info->mode_list[i]]
1472 .modemask, MAX1363_MAX_CHANNELS);
1473
1474 indio_dev->available_scan_masks = masks;
1475
1476 return 0;
1477 }
1478
max1363_trigger_handler(int irq,void * p)1479 static irqreturn_t max1363_trigger_handler(int irq, void *p)
1480 {
1481 struct iio_poll_func *pf = p;
1482 struct iio_dev *indio_dev = pf->indio_dev;
1483 struct max1363_state *st = iio_priv(indio_dev);
1484 __u8 *rxbuf;
1485 int b_sent;
1486 size_t d_size;
1487 unsigned long numvals = bitmap_weight(st->current_mode->modemask,
1488 MAX1363_MAX_CHANNELS);
1489
1490 /* Ensure the timestamp is 8 byte aligned */
1491 if (st->chip_info->bits != 8)
1492 d_size = numvals*2;
1493 else
1494 d_size = numvals;
1495 if (indio_dev->scan_timestamp) {
1496 d_size += sizeof(s64);
1497 if (d_size % sizeof(s64))
1498 d_size += sizeof(s64) - (d_size % sizeof(s64));
1499 }
1500 /* Monitor mode prevents reading. Whilst not currently implemented
1501 * might as well have this test in here in the meantime as it does
1502 * no harm.
1503 */
1504 if (numvals == 0)
1505 goto done;
1506
1507 rxbuf = kmalloc(d_size, GFP_KERNEL);
1508 if (rxbuf == NULL)
1509 goto done;
1510 if (st->chip_info->bits != 8)
1511 b_sent = st->recv(st->client, rxbuf, numvals * 2);
1512 else
1513 b_sent = st->recv(st->client, rxbuf, numvals);
1514 if (b_sent < 0)
1515 goto done_free;
1516
1517 iio_push_to_buffers_with_timestamp(indio_dev, rxbuf,
1518 iio_get_time_ns(indio_dev));
1519
1520 done_free:
1521 kfree(rxbuf);
1522 done:
1523 iio_trigger_notify_done(indio_dev->trig);
1524
1525 return IRQ_HANDLED;
1526 }
1527
1528 #define MAX1363_COMPATIBLE(of_compatible, cfg) { \
1529 .compatible = of_compatible, \
1530 .data = &max1363_chip_info_tbl[cfg], \
1531 }
1532
1533 static const struct of_device_id max1363_of_match[] = {
1534 MAX1363_COMPATIBLE("maxim,max1361", max1361),
1535 MAX1363_COMPATIBLE("maxim,max1362", max1362),
1536 MAX1363_COMPATIBLE("maxim,max1363", max1363),
1537 MAX1363_COMPATIBLE("maxim,max1364", max1364),
1538 MAX1363_COMPATIBLE("maxim,max1036", max1036),
1539 MAX1363_COMPATIBLE("maxim,max1037", max1037),
1540 MAX1363_COMPATIBLE("maxim,max1038", max1038),
1541 MAX1363_COMPATIBLE("maxim,max1039", max1039),
1542 MAX1363_COMPATIBLE("maxim,max1136", max1136),
1543 MAX1363_COMPATIBLE("maxim,max1137", max1137),
1544 MAX1363_COMPATIBLE("maxim,max1138", max1138),
1545 MAX1363_COMPATIBLE("maxim,max1139", max1139),
1546 MAX1363_COMPATIBLE("maxim,max1236", max1236),
1547 MAX1363_COMPATIBLE("maxim,max1237", max1237),
1548 MAX1363_COMPATIBLE("maxim,max1238", max1238),
1549 MAX1363_COMPATIBLE("maxim,max1239", max1239),
1550 MAX1363_COMPATIBLE("maxim,max11600", max11600),
1551 MAX1363_COMPATIBLE("maxim,max11601", max11601),
1552 MAX1363_COMPATIBLE("maxim,max11602", max11602),
1553 MAX1363_COMPATIBLE("maxim,max11603", max11603),
1554 MAX1363_COMPATIBLE("maxim,max11604", max11604),
1555 MAX1363_COMPATIBLE("maxim,max11605", max11605),
1556 MAX1363_COMPATIBLE("maxim,max11606", max11606),
1557 MAX1363_COMPATIBLE("maxim,max11607", max11607),
1558 MAX1363_COMPATIBLE("maxim,max11608", max11608),
1559 MAX1363_COMPATIBLE("maxim,max11609", max11609),
1560 MAX1363_COMPATIBLE("maxim,max11610", max11610),
1561 MAX1363_COMPATIBLE("maxim,max11611", max11611),
1562 MAX1363_COMPATIBLE("maxim,max11612", max11612),
1563 MAX1363_COMPATIBLE("maxim,max11613", max11613),
1564 MAX1363_COMPATIBLE("maxim,max11614", max11614),
1565 MAX1363_COMPATIBLE("maxim,max11615", max11615),
1566 MAX1363_COMPATIBLE("maxim,max11616", max11616),
1567 MAX1363_COMPATIBLE("maxim,max11617", max11617),
1568 MAX1363_COMPATIBLE("maxim,max11644", max11644),
1569 MAX1363_COMPATIBLE("maxim,max11645", max11645),
1570 MAX1363_COMPATIBLE("maxim,max11646", max11646),
1571 MAX1363_COMPATIBLE("maxim,max11647", max11647),
1572 { /* sentinel */ }
1573 };
1574 MODULE_DEVICE_TABLE(of, max1363_of_match);
1575
max1363_reg_disable(void * reg)1576 static void max1363_reg_disable(void *reg)
1577 {
1578 regulator_disable(reg);
1579 }
1580
max1363_probe(struct i2c_client * client)1581 static int max1363_probe(struct i2c_client *client)
1582 {
1583 const struct i2c_device_id *id = i2c_client_get_device_id(client);
1584 int ret;
1585 struct max1363_state *st;
1586 struct iio_dev *indio_dev;
1587 struct regulator *vref;
1588
1589 indio_dev = devm_iio_device_alloc(&client->dev,
1590 sizeof(struct max1363_state));
1591 if (!indio_dev)
1592 return -ENOMEM;
1593
1594 st = iio_priv(indio_dev);
1595
1596 mutex_init(&st->lock);
1597 ret = devm_regulator_get_enable(&client->dev, "vcc");
1598 if (ret)
1599 return ret;
1600
1601 st->chip_info = device_get_match_data(&client->dev);
1602 if (!st->chip_info)
1603 st->chip_info = &max1363_chip_info_tbl[id->driver_data];
1604 st->client = client;
1605
1606 st->vref_uv = st->chip_info->int_vref_mv * 1000;
1607 vref = devm_regulator_get_optional(&client->dev, "vref");
1608 if (!IS_ERR(vref)) {
1609 int vref_uv;
1610
1611 ret = regulator_enable(vref);
1612 if (ret)
1613 return ret;
1614
1615 ret = devm_add_action_or_reset(&client->dev, max1363_reg_disable, vref);
1616 if (ret)
1617 return ret;
1618
1619 st->vref = vref;
1620 vref_uv = regulator_get_voltage(vref);
1621 if (vref_uv <= 0)
1622 return -EINVAL;
1623
1624 st->vref_uv = vref_uv;
1625 }
1626
1627 if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1628 st->send = i2c_master_send;
1629 st->recv = i2c_master_recv;
1630 } else if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE)
1631 && st->chip_info->bits == 8) {
1632 st->send = max1363_smbus_send;
1633 st->recv = max1363_smbus_recv;
1634 } else {
1635 return -EOPNOTSUPP;
1636 }
1637
1638 ret = max1363_alloc_scan_masks(indio_dev);
1639 if (ret)
1640 return ret;
1641
1642 indio_dev->name = id->name;
1643 indio_dev->channels = st->chip_info->channels;
1644 indio_dev->num_channels = st->chip_info->num_channels;
1645 indio_dev->info = st->chip_info->info;
1646 indio_dev->modes = INDIO_DIRECT_MODE;
1647 ret = max1363_initial_setup(st);
1648 if (ret < 0)
1649 return ret;
1650
1651 ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL,
1652 &max1363_trigger_handler, NULL);
1653 if (ret)
1654 return ret;
1655
1656 if (client->irq) {
1657 ret = devm_request_threaded_irq(&client->dev, st->client->irq,
1658 NULL,
1659 &max1363_event_handler,
1660 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1661 "max1363_event",
1662 indio_dev);
1663
1664 if (ret)
1665 return ret;
1666 }
1667
1668 return devm_iio_device_register(&client->dev, indio_dev);
1669 }
1670
1671 static const struct i2c_device_id max1363_id[] = {
1672 { "max1361", max1361 },
1673 { "max1362", max1362 },
1674 { "max1363", max1363 },
1675 { "max1364", max1364 },
1676 { "max1036", max1036 },
1677 { "max1037", max1037 },
1678 { "max1038", max1038 },
1679 { "max1039", max1039 },
1680 { "max1136", max1136 },
1681 { "max1137", max1137 },
1682 { "max1138", max1138 },
1683 { "max1139", max1139 },
1684 { "max1236", max1236 },
1685 { "max1237", max1237 },
1686 { "max1238", max1238 },
1687 { "max1239", max1239 },
1688 { "max11600", max11600 },
1689 { "max11601", max11601 },
1690 { "max11602", max11602 },
1691 { "max11603", max11603 },
1692 { "max11604", max11604 },
1693 { "max11605", max11605 },
1694 { "max11606", max11606 },
1695 { "max11607", max11607 },
1696 { "max11608", max11608 },
1697 { "max11609", max11609 },
1698 { "max11610", max11610 },
1699 { "max11611", max11611 },
1700 { "max11612", max11612 },
1701 { "max11613", max11613 },
1702 { "max11614", max11614 },
1703 { "max11615", max11615 },
1704 { "max11616", max11616 },
1705 { "max11617", max11617 },
1706 { "max11644", max11644 },
1707 { "max11645", max11645 },
1708 { "max11646", max11646 },
1709 { "max11647", max11647 },
1710 {}
1711 };
1712
1713 MODULE_DEVICE_TABLE(i2c, max1363_id);
1714
1715 static struct i2c_driver max1363_driver = {
1716 .driver = {
1717 .name = "max1363",
1718 .of_match_table = max1363_of_match,
1719 },
1720 .probe = max1363_probe,
1721 .id_table = max1363_id,
1722 };
1723 module_i2c_driver(max1363_driver);
1724
1725 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
1726 MODULE_DESCRIPTION("Maxim 1363 ADC");
1727 MODULE_LICENSE("GPL v2");
1728