1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Loongson-2K/Loongson LS7A I2C master mode driver
4 *
5 * Copyright (C) 2013 Loongson Technology Corporation Limited.
6 * Copyright (C) 2014-2017 Lemote, Inc.
7 * Copyright (C) 2018-2022 Loongson Technology Corporation Limited.
8 *
9 * Originally written by liushaozong
10 * Rewritten for mainline by Binbin Zhou <zhoubinbin@loongson.cn>
11 */
12
13 #include <linux/bitfield.h>
14 #include <linux/bits.h>
15 #include <linux/completion.h>
16 #include <linux/device.h>
17 #include <linux/iopoll.h>
18 #include <linux/i2c.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/platform_device.h>
26 #include <linux/property.h>
27 #include <linux/units.h>
28
29 /* I2C Registers */
30 #define I2C_LS2X_PRER_LO 0x0 /* Freq Division Low Byte Register */
31 #define I2C_LS2X_PRER_HI 0x1 /* Freq Division High Byte Register */
32 #define I2C_LS2X_CTR 0x2 /* Control Register */
33 #define I2C_LS2X_TXR 0x3 /* Transport Data Register */
34 #define I2C_LS2X_RXR 0x3 /* Receive Data Register */
35 #define I2C_LS2X_CR 0x4 /* Command Control Register */
36 #define I2C_LS2X_SR 0x4 /* State Register */
37
38 /* Command Control Register Bit */
39 #define LS2X_CR_START BIT(7) /* Start signal */
40 #define LS2X_CR_STOP BIT(6) /* Stop signal */
41 #define LS2X_CR_READ BIT(5) /* Read signal */
42 #define LS2X_CR_WRITE BIT(4) /* Write signal */
43 #define LS2X_CR_ACK BIT(3) /* Response signal */
44 #define LS2X_CR_IACK BIT(0) /* Interrupt response signal */
45
46 /* State Register Bit */
47 #define LS2X_SR_NOACK BIT(7) /* Receive NACK */
48 #define LS2X_SR_BUSY BIT(6) /* Bus busy state */
49 #define LS2X_SR_AL BIT(5) /* Arbitration lost */
50 #define LS2X_SR_TIP BIT(1) /* Transmission state */
51 #define LS2X_SR_IF BIT(0) /* Interrupt flag */
52
53 /* Control Register Bit */
54 #define LS2X_CTR_EN BIT(7) /* 0: I2c frequency setting 1: Normal */
55 #define LS2X_CTR_IEN BIT(6) /* Enable i2c interrupt */
56 #define LS2X_CTR_MST BIT(5) /* 0: Slave mode 1: Master mode */
57 #define CTR_FREQ_MASK GENMASK(7, 6)
58 #define CTR_READY_MASK GENMASK(7, 5)
59
60 /* The PCLK frequency from LPB */
61 #define LS2X_I2C_PCLK_FREQ (50 * HZ_PER_MHZ)
62
63 /* The default bus frequency, which is an empirical value */
64 #define LS2X_I2C_FREQ_STD (33 * HZ_PER_KHZ)
65
66 struct ls2x_i2c_priv {
67 struct i2c_adapter adapter;
68 void __iomem *base;
69 struct i2c_timings i2c_t;
70 struct completion cmd_complete;
71 };
72
73 /*
74 * Interrupt service routine.
75 * This gets called whenever an I2C interrupt occurs.
76 */
ls2x_i2c_isr(int this_irq,void * dev_id)77 static irqreturn_t ls2x_i2c_isr(int this_irq, void *dev_id)
78 {
79 struct ls2x_i2c_priv *priv = dev_id;
80
81 if (!(readb(priv->base + I2C_LS2X_SR) & LS2X_SR_IF))
82 return IRQ_NONE;
83
84 writeb(LS2X_CR_IACK, priv->base + I2C_LS2X_CR);
85 complete(&priv->cmd_complete);
86 return IRQ_HANDLED;
87 }
88
89 /*
90 * The ls2x i2c controller supports standard mode and fast mode, so the
91 * maximum bus frequency is '400kHz'.
92 * The bus frequency is set to the empirical value of '33KHz' by default,
93 * but it can also be taken from ACPI or FDT for compatibility with more
94 * devices.
95 */
ls2x_i2c_adjust_bus_speed(struct ls2x_i2c_priv * priv)96 static void ls2x_i2c_adjust_bus_speed(struct ls2x_i2c_priv *priv)
97 {
98 u16 val;
99 struct i2c_timings *t = &priv->i2c_t;
100 struct device *dev = priv->adapter.dev.parent;
101 u32 acpi_speed = i2c_acpi_find_bus_speed(dev);
102
103 i2c_parse_fw_timings(dev, t, false);
104
105 if (acpi_speed || t->bus_freq_hz)
106 t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed);
107 else
108 t->bus_freq_hz = LS2X_I2C_FREQ_STD;
109
110 /*
111 * According to the chip manual, we can only access the registers as bytes,
112 * otherwise the high bits will be truncated.
113 * So set the I2C frequency with a sequential writeb() instead of writew().
114 */
115 val = LS2X_I2C_PCLK_FREQ / (5 * t->bus_freq_hz) - 1;
116 writeb(FIELD_GET(GENMASK(7, 0), val), priv->base + I2C_LS2X_PRER_LO);
117 writeb(FIELD_GET(GENMASK(15, 8), val), priv->base + I2C_LS2X_PRER_HI);
118 }
119
ls2x_i2c_init(struct ls2x_i2c_priv * priv)120 static void ls2x_i2c_init(struct ls2x_i2c_priv *priv)
121 {
122 /* Set i2c frequency setting mode and disable interrupts. */
123 writeb(readb(priv->base + I2C_LS2X_CTR) & ~CTR_FREQ_MASK,
124 priv->base + I2C_LS2X_CTR);
125
126 ls2x_i2c_adjust_bus_speed(priv);
127
128 /* Set i2c normal operating mode and enable interrupts. */
129 writeb(readb(priv->base + I2C_LS2X_CTR) | CTR_READY_MASK,
130 priv->base + I2C_LS2X_CTR);
131 }
132
ls2x_i2c_xfer_byte(struct ls2x_i2c_priv * priv,u8 txdata,u8 * rxdatap)133 static int ls2x_i2c_xfer_byte(struct ls2x_i2c_priv *priv, u8 txdata, u8 *rxdatap)
134 {
135 u8 rxdata;
136 unsigned long time_left;
137
138 writeb(txdata, priv->base + I2C_LS2X_CR);
139
140 time_left = wait_for_completion_timeout(&priv->cmd_complete,
141 priv->adapter.timeout);
142 if (!time_left)
143 return -ETIMEDOUT;
144
145 rxdata = readb(priv->base + I2C_LS2X_SR);
146 if (rxdatap)
147 *rxdatap = rxdata;
148
149 return 0;
150 }
151
ls2x_i2c_send_byte(struct ls2x_i2c_priv * priv,u8 txdata)152 static int ls2x_i2c_send_byte(struct ls2x_i2c_priv *priv, u8 txdata)
153 {
154 int ret;
155 u8 rxdata;
156
157 ret = ls2x_i2c_xfer_byte(priv, txdata, &rxdata);
158 if (ret)
159 return ret;
160
161 if (rxdata & LS2X_SR_AL)
162 return -EAGAIN;
163
164 if (rxdata & LS2X_SR_NOACK)
165 return -ENXIO;
166
167 return 0;
168 }
169
ls2x_i2c_stop(struct ls2x_i2c_priv * priv)170 static int ls2x_i2c_stop(struct ls2x_i2c_priv *priv)
171 {
172 u8 value;
173
174 writeb(LS2X_CR_STOP, priv->base + I2C_LS2X_CR);
175 return readb_poll_timeout(priv->base + I2C_LS2X_SR, value,
176 !(value & LS2X_SR_BUSY), 100,
177 jiffies_to_usecs(priv->adapter.timeout));
178 }
179
ls2x_i2c_start(struct ls2x_i2c_priv * priv,struct i2c_msg * msgs)180 static int ls2x_i2c_start(struct ls2x_i2c_priv *priv, struct i2c_msg *msgs)
181 {
182 reinit_completion(&priv->cmd_complete);
183
184 writeb(i2c_8bit_addr_from_msg(msgs), priv->base + I2C_LS2X_TXR);
185 return ls2x_i2c_send_byte(priv, LS2X_CR_START | LS2X_CR_WRITE);
186 }
187
ls2x_i2c_rx(struct ls2x_i2c_priv * priv,struct i2c_msg * msg)188 static int ls2x_i2c_rx(struct ls2x_i2c_priv *priv, struct i2c_msg *msg)
189 {
190 int ret;
191 u8 rxdata, *buf = msg->buf;
192 u16 len = msg->len;
193
194 /* Contains steps to send start condition and address. */
195 ret = ls2x_i2c_start(priv, msg);
196 if (ret)
197 return ret;
198
199 while (len--) {
200 ret = ls2x_i2c_xfer_byte(priv,
201 LS2X_CR_READ | (len ? 0 : LS2X_CR_ACK),
202 &rxdata);
203 if (ret)
204 return ret;
205
206 *buf++ = readb(priv->base + I2C_LS2X_RXR);
207 }
208
209 return 0;
210 }
211
ls2x_i2c_tx(struct ls2x_i2c_priv * priv,struct i2c_msg * msg)212 static int ls2x_i2c_tx(struct ls2x_i2c_priv *priv, struct i2c_msg *msg)
213 {
214 int ret;
215 u8 *buf = msg->buf;
216 u16 len = msg->len;
217
218 /* Contains steps to send start condition and address. */
219 ret = ls2x_i2c_start(priv, msg);
220 if (ret)
221 return ret;
222
223 while (len--) {
224 writeb(*buf++, priv->base + I2C_LS2X_TXR);
225
226 ret = ls2x_i2c_send_byte(priv, LS2X_CR_WRITE);
227 if (ret)
228 return ret;
229 }
230
231 return 0;
232 }
233
ls2x_i2c_xfer_one(struct ls2x_i2c_priv * priv,struct i2c_msg * msg,bool stop)234 static int ls2x_i2c_xfer_one(struct ls2x_i2c_priv *priv,
235 struct i2c_msg *msg, bool stop)
236 {
237 int ret;
238
239 if (msg->flags & I2C_M_RD)
240 ret = ls2x_i2c_rx(priv, msg);
241 else
242 ret = ls2x_i2c_tx(priv, msg);
243
244 if (ret < 0) {
245 /* Fatel error. Needs reinit. */
246 if (ret == -ETIMEDOUT)
247 ls2x_i2c_init(priv);
248
249 return ret;
250 }
251
252 if (stop) {
253 /* Failed to issue STOP. Needs reinit. */
254 ret = ls2x_i2c_stop(priv);
255 if (ret)
256 ls2x_i2c_init(priv);
257 }
258
259 return ret;
260 }
261
ls2x_i2c_master_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)262 static int ls2x_i2c_master_xfer(struct i2c_adapter *adap,
263 struct i2c_msg *msgs, int num)
264 {
265 int ret;
266 struct i2c_msg *msg, *emsg = msgs + num;
267 struct ls2x_i2c_priv *priv = i2c_get_adapdata(adap);
268
269 for (msg = msgs; msg < emsg; msg++) {
270 ret = ls2x_i2c_xfer_one(priv, msg, msg == emsg - 1);
271 if (ret)
272 return ret;
273 }
274
275 return num;
276 }
277
ls2x_i2c_func(struct i2c_adapter * adap)278 static unsigned int ls2x_i2c_func(struct i2c_adapter *adap)
279 {
280 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
281 }
282
283 static const struct i2c_algorithm ls2x_i2c_algo = {
284 .master_xfer = ls2x_i2c_master_xfer,
285 .functionality = ls2x_i2c_func,
286 };
287
ls2x_i2c_probe(struct platform_device * pdev)288 static int ls2x_i2c_probe(struct platform_device *pdev)
289 {
290 int ret, irq;
291 struct i2c_adapter *adap;
292 struct ls2x_i2c_priv *priv;
293 struct device *dev = &pdev->dev;
294
295 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
296 if (!priv)
297 return -ENOMEM;
298
299 /* Map hardware registers */
300 priv->base = devm_platform_ioremap_resource(pdev, 0);
301 if (IS_ERR(priv->base))
302 return PTR_ERR(priv->base);
303
304 irq = platform_get_irq(pdev, 0);
305 if (irq < 0)
306 return irq;
307
308 /* Add the i2c adapter */
309 adap = &priv->adapter;
310 adap->retries = 5;
311 adap->nr = pdev->id;
312 adap->dev.parent = dev;
313 adap->owner = THIS_MODULE;
314 adap->algo = &ls2x_i2c_algo;
315 adap->timeout = msecs_to_jiffies(100);
316 device_set_node(&adap->dev, dev_fwnode(dev));
317 i2c_set_adapdata(adap, priv);
318 strscpy(adap->name, pdev->name, sizeof(adap->name));
319 init_completion(&priv->cmd_complete);
320 platform_set_drvdata(pdev, priv);
321
322 ls2x_i2c_init(priv);
323
324 ret = devm_request_irq(dev, irq, ls2x_i2c_isr, IRQF_SHARED, "ls2x-i2c",
325 priv);
326 if (ret < 0)
327 return dev_err_probe(dev, ret, "Unable to request irq %d\n", irq);
328
329 return devm_i2c_add_adapter(dev, adap);
330 }
331
ls2x_i2c_suspend(struct device * dev)332 static int ls2x_i2c_suspend(struct device *dev)
333 {
334 struct ls2x_i2c_priv *priv = dev_get_drvdata(dev);
335
336 /* Disable interrupts */
337 writeb(readb(priv->base + I2C_LS2X_CTR) & ~LS2X_CTR_IEN,
338 priv->base + I2C_LS2X_CTR);
339
340 return 0;
341 }
342
ls2x_i2c_resume(struct device * dev)343 static int ls2x_i2c_resume(struct device *dev)
344 {
345 ls2x_i2c_init(dev_get_drvdata(dev));
346 return 0;
347 }
348
349 static DEFINE_RUNTIME_DEV_PM_OPS(ls2x_i2c_pm_ops,
350 ls2x_i2c_suspend, ls2x_i2c_resume, NULL);
351
352 static const struct of_device_id ls2x_i2c_id_table[] = {
353 { .compatible = "loongson,ls2k-i2c" },
354 { .compatible = "loongson,ls7a-i2c" },
355 { /* sentinel */ }
356 };
357 MODULE_DEVICE_TABLE(of, ls2x_i2c_id_table);
358
359 static const struct acpi_device_id ls2x_i2c_acpi_match[] = {
360 { "LOON0004" }, /* Loongson LS7A */
361 { }
362 };
363 MODULE_DEVICE_TABLE(acpi, ls2x_i2c_acpi_match);
364
365 static struct platform_driver ls2x_i2c_driver = {
366 .probe = ls2x_i2c_probe,
367 .driver = {
368 .name = "ls2x-i2c",
369 .pm = pm_sleep_ptr(&ls2x_i2c_pm_ops),
370 .of_match_table = ls2x_i2c_id_table,
371 .acpi_match_table = ls2x_i2c_acpi_match,
372 },
373 };
374 module_platform_driver(ls2x_i2c_driver);
375
376 MODULE_DESCRIPTION("Loongson LS2X I2C Bus driver");
377 MODULE_AUTHOR("Loongson Technology Corporation Limited");
378 MODULE_LICENSE("GPL");
379