1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Loongson 3A5000 ext interrupt controller emulation
4 *
5 * Copyright (C) 2021 Loongson Technology Corporation Limited
6 */
7
8 #include "qemu/osdep.h"
9 #include "qemu/module.h"
10 #include "qemu/log.h"
11 #include "qapi/error.h"
12 #include "hw/irq.h"
13 #include "hw/sysbus.h"
14 #include "hw/loongarch/virt.h"
15 #include "hw/qdev-properties.h"
16 #include "exec/address-spaces.h"
17 #include "hw/intc/loongarch_extioi.h"
18 #include "migration/vmstate.h"
19 #include "trace.h"
20
21
extioi_update_irq(LoongArchExtIOI * s,int irq,int level)22 static void extioi_update_irq(LoongArchExtIOI *s, int irq, int level)
23 {
24 int ipnum, cpu, found, irq_index, irq_mask;
25
26 ipnum = s->sw_ipmap[irq / 32];
27 cpu = s->sw_coremap[irq];
28 irq_index = irq / 32;
29 irq_mask = 1 << (irq & 0x1f);
30
31 if (level) {
32 /* if not enable return false */
33 if (((s->enable[irq_index]) & irq_mask) == 0) {
34 return;
35 }
36 s->cpu[cpu].coreisr[irq_index] |= irq_mask;
37 found = find_first_bit(s->cpu[cpu].sw_isr[ipnum], EXTIOI_IRQS);
38 set_bit(irq, s->cpu[cpu].sw_isr[ipnum]);
39 if (found < EXTIOI_IRQS) {
40 /* other irq is handling, need not update parent irq level */
41 return;
42 }
43 } else {
44 s->cpu[cpu].coreisr[irq_index] &= ~irq_mask;
45 clear_bit(irq, s->cpu[cpu].sw_isr[ipnum]);
46 found = find_first_bit(s->cpu[cpu].sw_isr[ipnum], EXTIOI_IRQS);
47 if (found < EXTIOI_IRQS) {
48 /* other irq is handling, need not update parent irq level */
49 return;
50 }
51 }
52 qemu_set_irq(s->cpu[cpu].parent_irq[ipnum], level);
53 }
54
extioi_setirq(void * opaque,int irq,int level)55 static void extioi_setirq(void *opaque, int irq, int level)
56 {
57 LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
58 trace_loongarch_extioi_setirq(irq, level);
59 if (level) {
60 set_bit32(irq, s->isr);
61 } else {
62 clear_bit32(irq, s->isr);
63 }
64 extioi_update_irq(s, irq, level);
65 }
66
extioi_readw(void * opaque,hwaddr addr,uint64_t * data,unsigned size,MemTxAttrs attrs)67 static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data,
68 unsigned size, MemTxAttrs attrs)
69 {
70 LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
71 unsigned long offset = addr & 0xffff;
72 uint32_t index, cpu;
73
74 switch (offset) {
75 case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1:
76 index = (offset - EXTIOI_NODETYPE_START) >> 2;
77 *data = s->nodetype[index];
78 break;
79 case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1:
80 index = (offset - EXTIOI_IPMAP_START) >> 2;
81 *data = s->ipmap[index];
82 break;
83 case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1:
84 index = (offset - EXTIOI_ENABLE_START) >> 2;
85 *data = s->enable[index];
86 break;
87 case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1:
88 index = (offset - EXTIOI_BOUNCE_START) >> 2;
89 *data = s->bounce[index];
90 break;
91 case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
92 index = (offset - EXTIOI_COREISR_START) >> 2;
93 /* using attrs to get current cpu index */
94 cpu = attrs.requester_id;
95 *data = s->cpu[cpu].coreisr[index];
96 break;
97 case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:
98 index = (offset - EXTIOI_COREMAP_START) >> 2;
99 *data = s->coremap[index];
100 break;
101 default:
102 break;
103 }
104
105 trace_loongarch_extioi_readw(addr, *data);
106 return MEMTX_OK;
107 }
108
extioi_enable_irq(LoongArchExtIOI * s,int index,uint32_t mask,int level)109 static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\
110 uint32_t mask, int level)
111 {
112 uint32_t val;
113 int irq;
114
115 val = mask & s->isr[index];
116 irq = ctz32(val);
117 while (irq != 32) {
118 /*
119 * enable bit change from 0 to 1,
120 * need to update irq by pending bits
121 */
122 extioi_update_irq(s, irq + index * 32, level);
123 val &= ~(1 << irq);
124 irq = ctz32(val);
125 }
126 }
127
extioi_update_sw_coremap(LoongArchExtIOI * s,int irq,uint64_t val,bool notify)128 static inline void extioi_update_sw_coremap(LoongArchExtIOI *s, int irq,
129 uint64_t val, bool notify)
130 {
131 int i, cpu;
132
133 /*
134 * loongarch only support little endian,
135 * so we paresd the value with little endian.
136 */
137 val = cpu_to_le64(val);
138
139 for (i = 0; i < 4; i++) {
140 cpu = val & 0xff;
141 val = val >> 8;
142
143 if (!(s->status & BIT(EXTIOI_ENABLE_CPU_ENCODE))) {
144 cpu = ctz32(cpu);
145 cpu = (cpu >= 4) ? 0 : cpu;
146 }
147
148 if (s->sw_coremap[irq + i] == cpu) {
149 continue;
150 }
151
152 if (notify && test_bit32(irq + i, s->isr)) {
153 /*
154 * lower irq at old cpu and raise irq at new cpu
155 */
156 extioi_update_irq(s, irq + i, 0);
157 s->sw_coremap[irq + i] = cpu;
158 extioi_update_irq(s, irq + i, 1);
159 } else {
160 s->sw_coremap[irq + i] = cpu;
161 }
162 }
163 }
164
extioi_update_sw_ipmap(LoongArchExtIOI * s,int index,uint64_t val)165 static inline void extioi_update_sw_ipmap(LoongArchExtIOI *s, int index,
166 uint64_t val)
167 {
168 int i;
169 uint8_t ipnum;
170
171 /*
172 * loongarch only support little endian,
173 * so we paresd the value with little endian.
174 */
175 val = cpu_to_le64(val);
176 for (i = 0; i < 4; i++) {
177 ipnum = val & 0xff;
178 ipnum = ctz32(ipnum);
179 ipnum = (ipnum >= 4) ? 0 : ipnum;
180 s->sw_ipmap[index * 4 + i] = ipnum;
181 val = val >> 8;
182 }
183 }
184
extioi_writew(void * opaque,hwaddr addr,uint64_t val,unsigned size,MemTxAttrs attrs)185 static MemTxResult extioi_writew(void *opaque, hwaddr addr,
186 uint64_t val, unsigned size,
187 MemTxAttrs attrs)
188 {
189 LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
190 int cpu, index, old_data, irq;
191 uint32_t offset;
192
193 trace_loongarch_extioi_writew(addr, val);
194 offset = addr & 0xffff;
195
196 switch (offset) {
197 case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1:
198 index = (offset - EXTIOI_NODETYPE_START) >> 2;
199 s->nodetype[index] = val;
200 break;
201 case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1:
202 /*
203 * ipmap cannot be set at runtime, can be set only at the beginning
204 * of intr driver, need not update upper irq level
205 */
206 index = (offset - EXTIOI_IPMAP_START) >> 2;
207 s->ipmap[index] = val;
208 extioi_update_sw_ipmap(s, index, val);
209 break;
210 case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1:
211 index = (offset - EXTIOI_ENABLE_START) >> 2;
212 old_data = s->enable[index];
213 s->enable[index] = val;
214
215 /* unmask irq */
216 val = s->enable[index] & ~old_data;
217 extioi_enable_irq(s, index, val, 1);
218
219 /* mask irq */
220 val = ~s->enable[index] & old_data;
221 extioi_enable_irq(s, index, val, 0);
222 break;
223 case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1:
224 /* do not emulate hw bounced irq routing */
225 index = (offset - EXTIOI_BOUNCE_START) >> 2;
226 s->bounce[index] = val;
227 break;
228 case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
229 index = (offset - EXTIOI_COREISR_START) >> 2;
230 /* using attrs to get current cpu index */
231 cpu = attrs.requester_id;
232 old_data = s->cpu[cpu].coreisr[index];
233 s->cpu[cpu].coreisr[index] = old_data & ~val;
234 /* write 1 to clear interrupt */
235 old_data &= val;
236 irq = ctz32(old_data);
237 while (irq != 32) {
238 extioi_update_irq(s, irq + index * 32, 0);
239 old_data &= ~(1 << irq);
240 irq = ctz32(old_data);
241 }
242 break;
243 case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:
244 irq = offset - EXTIOI_COREMAP_START;
245 index = irq / 4;
246 s->coremap[index] = val;
247
248 extioi_update_sw_coremap(s, irq, val, true);
249 break;
250 default:
251 break;
252 }
253 return MEMTX_OK;
254 }
255
256 static const MemoryRegionOps extioi_ops = {
257 .read_with_attrs = extioi_readw,
258 .write_with_attrs = extioi_writew,
259 .impl.min_access_size = 4,
260 .impl.max_access_size = 4,
261 .valid.min_access_size = 4,
262 .valid.max_access_size = 8,
263 .endianness = DEVICE_LITTLE_ENDIAN,
264 };
265
extioi_virt_readw(void * opaque,hwaddr addr,uint64_t * data,unsigned size,MemTxAttrs attrs)266 static MemTxResult extioi_virt_readw(void *opaque, hwaddr addr, uint64_t *data,
267 unsigned size, MemTxAttrs attrs)
268 {
269 LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
270
271 switch (addr) {
272 case EXTIOI_VIRT_FEATURES:
273 *data = s->features;
274 break;
275 case EXTIOI_VIRT_CONFIG:
276 *data = s->status;
277 break;
278 default:
279 g_assert_not_reached();
280 }
281
282 return MEMTX_OK;
283 }
284
extioi_virt_writew(void * opaque,hwaddr addr,uint64_t val,unsigned size,MemTxAttrs attrs)285 static MemTxResult extioi_virt_writew(void *opaque, hwaddr addr,
286 uint64_t val, unsigned size,
287 MemTxAttrs attrs)
288 {
289 LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
290
291 switch (addr) {
292 case EXTIOI_VIRT_FEATURES:
293 return MEMTX_ACCESS_ERROR;
294
295 case EXTIOI_VIRT_CONFIG:
296 /*
297 * extioi features can only be set at disabled status
298 */
299 if ((s->status & BIT(EXTIOI_ENABLE)) && val) {
300 return MEMTX_ACCESS_ERROR;
301 }
302
303 s->status = val & s->features;
304 break;
305 default:
306 g_assert_not_reached();
307 }
308 return MEMTX_OK;
309 }
310
311 static const MemoryRegionOps extioi_virt_ops = {
312 .read_with_attrs = extioi_virt_readw,
313 .write_with_attrs = extioi_virt_writew,
314 .impl.min_access_size = 4,
315 .impl.max_access_size = 4,
316 .valid.min_access_size = 4,
317 .valid.max_access_size = 8,
318 .endianness = DEVICE_LITTLE_ENDIAN,
319 };
320
loongarch_extioi_realize(DeviceState * dev,Error ** errp)321 static void loongarch_extioi_realize(DeviceState *dev, Error **errp)
322 {
323 LoongArchExtIOI *s = LOONGARCH_EXTIOI(dev);
324 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
325 int i, pin;
326
327 if (s->num_cpu == 0) {
328 error_setg(errp, "num-cpu must be at least 1");
329 return;
330 }
331
332 for (i = 0; i < EXTIOI_IRQS; i++) {
333 sysbus_init_irq(sbd, &s->irq[i]);
334 }
335
336 qdev_init_gpio_in(dev, extioi_setirq, EXTIOI_IRQS);
337 memory_region_init_io(&s->extioi_system_mem, OBJECT(s), &extioi_ops,
338 s, "extioi_system_mem", 0x900);
339 sysbus_init_mmio(sbd, &s->extioi_system_mem);
340
341 if (s->features & BIT(EXTIOI_HAS_VIRT_EXTENSION)) {
342 memory_region_init_io(&s->virt_extend, OBJECT(s), &extioi_virt_ops,
343 s, "extioi_virt", EXTIOI_VIRT_SIZE);
344 sysbus_init_mmio(sbd, &s->virt_extend);
345 s->features |= EXTIOI_VIRT_HAS_FEATURES;
346 } else {
347 s->status |= BIT(EXTIOI_ENABLE);
348 }
349
350 s->cpu = g_new0(ExtIOICore, s->num_cpu);
351 if (s->cpu == NULL) {
352 error_setg(errp, "Memory allocation for ExtIOICore faile");
353 return;
354 }
355
356 for (i = 0; i < s->num_cpu; i++) {
357 for (pin = 0; pin < LS3A_INTC_IP; pin++) {
358 qdev_init_gpio_out(dev, &s->cpu[i].parent_irq[pin], 1);
359 }
360 }
361 }
362
loongarch_extioi_finalize(Object * obj)363 static void loongarch_extioi_finalize(Object *obj)
364 {
365 LoongArchExtIOI *s = LOONGARCH_EXTIOI(obj);
366
367 g_free(s->cpu);
368 }
369
loongarch_extioi_reset(DeviceState * d)370 static void loongarch_extioi_reset(DeviceState *d)
371 {
372 LoongArchExtIOI *s = LOONGARCH_EXTIOI(d);
373
374 s->status = 0;
375 }
376
vmstate_extioi_post_load(void * opaque,int version_id)377 static int vmstate_extioi_post_load(void *opaque, int version_id)
378 {
379 LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
380 int i, start_irq;
381
382 for (i = 0; i < (EXTIOI_IRQS / 4); i++) {
383 start_irq = i * 4;
384 extioi_update_sw_coremap(s, start_irq, s->coremap[i], false);
385 }
386
387 for (i = 0; i < (EXTIOI_IRQS_IPMAP_SIZE / 4); i++) {
388 extioi_update_sw_ipmap(s, i, s->ipmap[i]);
389 }
390
391 return 0;
392 }
393
394 static const VMStateDescription vmstate_extioi_core = {
395 .name = "extioi-core",
396 .version_id = 1,
397 .minimum_version_id = 1,
398 .fields = (const VMStateField[]) {
399 VMSTATE_UINT32_ARRAY(coreisr, ExtIOICore, EXTIOI_IRQS_GROUP_COUNT),
400 VMSTATE_END_OF_LIST()
401 }
402 };
403
404 static const VMStateDescription vmstate_loongarch_extioi = {
405 .name = TYPE_LOONGARCH_EXTIOI,
406 .version_id = 3,
407 .minimum_version_id = 3,
408 .post_load = vmstate_extioi_post_load,
409 .fields = (const VMStateField[]) {
410 VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOI, EXTIOI_IRQS_GROUP_COUNT),
411 VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOI,
412 EXTIOI_IRQS_NODETYPE_COUNT / 2),
413 VMSTATE_UINT32_ARRAY(enable, LoongArchExtIOI, EXTIOI_IRQS / 32),
414 VMSTATE_UINT32_ARRAY(isr, LoongArchExtIOI, EXTIOI_IRQS / 32),
415 VMSTATE_UINT32_ARRAY(ipmap, LoongArchExtIOI, EXTIOI_IRQS_IPMAP_SIZE / 4),
416 VMSTATE_UINT32_ARRAY(coremap, LoongArchExtIOI, EXTIOI_IRQS / 4),
417
418 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchExtIOI, num_cpu,
419 vmstate_extioi_core, ExtIOICore),
420 VMSTATE_UINT32(features, LoongArchExtIOI),
421 VMSTATE_UINT32(status, LoongArchExtIOI),
422 VMSTATE_END_OF_LIST()
423 }
424 };
425
426 static Property extioi_properties[] = {
427 DEFINE_PROP_UINT32("num-cpu", LoongArchExtIOI, num_cpu, 1),
428 DEFINE_PROP_BIT("has-virtualization-extension", LoongArchExtIOI, features,
429 EXTIOI_HAS_VIRT_EXTENSION, 0),
430 DEFINE_PROP_END_OF_LIST(),
431 };
432
loongarch_extioi_class_init(ObjectClass * klass,void * data)433 static void loongarch_extioi_class_init(ObjectClass *klass, void *data)
434 {
435 DeviceClass *dc = DEVICE_CLASS(klass);
436
437 dc->realize = loongarch_extioi_realize;
438 device_class_set_legacy_reset(dc, loongarch_extioi_reset);
439 device_class_set_props(dc, extioi_properties);
440 dc->vmsd = &vmstate_loongarch_extioi;
441 }
442
443 static const TypeInfo loongarch_extioi_info = {
444 .name = TYPE_LOONGARCH_EXTIOI,
445 .parent = TYPE_SYS_BUS_DEVICE,
446 .instance_size = sizeof(struct LoongArchExtIOI),
447 .class_init = loongarch_extioi_class_init,
448 .instance_finalize = loongarch_extioi_finalize,
449 };
450
loongarch_extioi_register_types(void)451 static void loongarch_extioi_register_types(void)
452 {
453 type_register_static(&loongarch_extioi_info);
454 }
455
456 type_init(loongarch_extioi_register_types)
457