1 #include <linux/gfp.h>
2 #include <linux/initrd.h>
3 #include <linux/ioport.h>
4 #include <linux/swap.h>
5 #include <linux/memblock.h>
6 #include <linux/swapfile.h>
7 #include <linux/swapops.h>
8 #include <linux/kmemleak.h>
9 #include <linux/sched/task.h>
10
11 #include <asm/set_memory.h>
12 #include <asm/cpu_device_id.h>
13 #include <asm/e820/api.h>
14 #include <asm/init.h>
15 #include <asm/page.h>
16 #include <asm/page_types.h>
17 #include <asm/sections.h>
18 #include <asm/setup.h>
19 #include <asm/tlbflush.h>
20 #include <asm/tlb.h>
21 #include <asm/proto.h>
22 #include <asm/dma.h> /* for MAX_DMA_PFN */
23 #include <asm/kaslr.h>
24 #include <asm/hypervisor.h>
25 #include <asm/cpufeature.h>
26 #include <asm/pti.h>
27 #include <asm/text-patching.h>
28 #include <asm/memtype.h>
29 #include <asm/paravirt.h>
30
31 /*
32 * We need to define the tracepoints somewhere, and tlb.c
33 * is only compiled when SMP=y.
34 */
35 #include <trace/events/tlb.h>
36
37 #include "mm_internal.h"
38
39 /*
40 * Tables translating between page_cache_type_t and pte encoding.
41 *
42 * The default values are defined statically as minimal supported mode;
43 * WC and WT fall back to UC-. pat_init() updates these values to support
44 * more cache modes, WC and WT, when it is safe to do so. See pat_init()
45 * for the details. Note, __early_ioremap() used during early boot-time
46 * takes pgprot_t (pte encoding) and does not use these tables.
47 *
48 * Index into __cachemode2pte_tbl[] is the cachemode.
49 *
50 * Index into __pte2cachemode_tbl[] are the caching attribute bits of the pte
51 * (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT) at index bit positions 0, 1, 2.
52 */
53 static uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {
54 [_PAGE_CACHE_MODE_WB ] = 0 | 0 ,
55 [_PAGE_CACHE_MODE_WC ] = 0 | _PAGE_PCD,
56 [_PAGE_CACHE_MODE_UC_MINUS] = 0 | _PAGE_PCD,
57 [_PAGE_CACHE_MODE_UC ] = _PAGE_PWT | _PAGE_PCD,
58 [_PAGE_CACHE_MODE_WT ] = 0 | _PAGE_PCD,
59 [_PAGE_CACHE_MODE_WP ] = 0 | _PAGE_PCD,
60 };
61
cachemode2protval(enum page_cache_mode pcm)62 unsigned long cachemode2protval(enum page_cache_mode pcm)
63 {
64 if (likely(pcm == 0))
65 return 0;
66 return __cachemode2pte_tbl[pcm];
67 }
68 EXPORT_SYMBOL(cachemode2protval);
69
70 static uint8_t __pte2cachemode_tbl[8] = {
71 [__pte2cm_idx( 0 | 0 | 0 )] = _PAGE_CACHE_MODE_WB,
72 [__pte2cm_idx(_PAGE_PWT | 0 | 0 )] = _PAGE_CACHE_MODE_UC_MINUS,
73 [__pte2cm_idx( 0 | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC_MINUS,
74 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC,
75 [__pte2cm_idx( 0 | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_WB,
76 [__pte2cm_idx(_PAGE_PWT | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS,
77 [__pte2cm_idx(0 | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS,
78 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC,
79 };
80
81 /*
82 * Check that the write-protect PAT entry is set for write-protect.
83 * To do this without making assumptions how PAT has been set up (Xen has
84 * another layout than the kernel), translate the _PAGE_CACHE_MODE_WP cache
85 * mode via the __cachemode2pte_tbl[] into protection bits (those protection
86 * bits will select a cache mode of WP or better), and then translate the
87 * protection bits back into the cache mode using __pte2cm_idx() and the
88 * __pte2cachemode_tbl[] array. This will return the really used cache mode.
89 */
x86_has_pat_wp(void)90 bool x86_has_pat_wp(void)
91 {
92 uint16_t prot = __cachemode2pte_tbl[_PAGE_CACHE_MODE_WP];
93
94 return __pte2cachemode_tbl[__pte2cm_idx(prot)] == _PAGE_CACHE_MODE_WP;
95 }
96
pgprot2cachemode(pgprot_t pgprot)97 enum page_cache_mode pgprot2cachemode(pgprot_t pgprot)
98 {
99 unsigned long masked;
100
101 masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK;
102 if (likely(masked == 0))
103 return 0;
104 return __pte2cachemode_tbl[__pte2cm_idx(masked)];
105 }
106
107 static unsigned long __initdata pgt_buf_start;
108 static unsigned long __initdata pgt_buf_end;
109 static unsigned long __initdata pgt_buf_top;
110
111 static unsigned long min_pfn_mapped;
112
113 static bool __initdata can_use_brk_pgt = true;
114
115 /*
116 * Pages returned are already directly mapped.
117 *
118 * Changing that is likely to break Xen, see commit:
119 *
120 * 279b706 x86,xen: introduce x86_init.mapping.pagetable_reserve
121 *
122 * for detailed information.
123 */
alloc_low_pages(unsigned int num)124 __ref void *alloc_low_pages(unsigned int num)
125 {
126 unsigned long pfn;
127 int i;
128
129 if (after_bootmem) {
130 unsigned int order;
131
132 order = get_order((unsigned long)num << PAGE_SHIFT);
133 return (void *)__get_free_pages(GFP_ATOMIC | __GFP_ZERO, order);
134 }
135
136 if ((pgt_buf_end + num) > pgt_buf_top || !can_use_brk_pgt) {
137 unsigned long ret = 0;
138
139 if (min_pfn_mapped < max_pfn_mapped) {
140 ret = memblock_phys_alloc_range(
141 PAGE_SIZE * num, PAGE_SIZE,
142 min_pfn_mapped << PAGE_SHIFT,
143 max_pfn_mapped << PAGE_SHIFT);
144 }
145 if (!ret && can_use_brk_pgt)
146 ret = __pa(extend_brk(PAGE_SIZE * num, PAGE_SIZE));
147
148 if (!ret)
149 panic("alloc_low_pages: can not alloc memory");
150
151 pfn = ret >> PAGE_SHIFT;
152 } else {
153 pfn = pgt_buf_end;
154 pgt_buf_end += num;
155 }
156
157 for (i = 0; i < num; i++) {
158 void *adr;
159
160 adr = __va((pfn + i) << PAGE_SHIFT);
161 clear_page(adr);
162 }
163
164 return __va(pfn << PAGE_SHIFT);
165 }
166
167 /*
168 * By default need to be able to allocate page tables below PGD firstly for
169 * the 0-ISA_END_ADDRESS range and secondly for the initial PMD_SIZE mapping.
170 * With KASLR memory randomization, depending on the machine e820 memory and the
171 * PUD alignment, twice that many pages may be needed when KASLR memory
172 * randomization is enabled.
173 */
174
175 #ifndef CONFIG_X86_5LEVEL
176 #define INIT_PGD_PAGE_TABLES 3
177 #else
178 #define INIT_PGD_PAGE_TABLES 4
179 #endif
180
181 #ifndef CONFIG_RANDOMIZE_MEMORY
182 #define INIT_PGD_PAGE_COUNT (2 * INIT_PGD_PAGE_TABLES)
183 #else
184 #define INIT_PGD_PAGE_COUNT (4 * INIT_PGD_PAGE_TABLES)
185 #endif
186
187 #define INIT_PGT_BUF_SIZE (INIT_PGD_PAGE_COUNT * PAGE_SIZE)
188 RESERVE_BRK(early_pgt_alloc, INIT_PGT_BUF_SIZE);
early_alloc_pgt_buf(void)189 void __init early_alloc_pgt_buf(void)
190 {
191 unsigned long tables = INIT_PGT_BUF_SIZE;
192 phys_addr_t base;
193
194 base = __pa(extend_brk(tables, PAGE_SIZE));
195
196 pgt_buf_start = base >> PAGE_SHIFT;
197 pgt_buf_end = pgt_buf_start;
198 pgt_buf_top = pgt_buf_start + (tables >> PAGE_SHIFT);
199 }
200
201 int after_bootmem;
202
203 early_param_on_off("gbpages", "nogbpages", direct_gbpages, CONFIG_X86_DIRECT_GBPAGES);
204
205 struct map_range {
206 unsigned long start;
207 unsigned long end;
208 unsigned page_size_mask;
209 };
210
211 static int page_size_mask;
212
213 /*
214 * Save some of cr4 feature set we're using (e.g. Pentium 4MB
215 * enable and PPro Global page enable), so that any CPU's that boot
216 * up after us can get the correct flags. Invoked on the boot CPU.
217 */
cr4_set_bits_and_update_boot(unsigned long mask)218 static inline void cr4_set_bits_and_update_boot(unsigned long mask)
219 {
220 mmu_cr4_features |= mask;
221 if (trampoline_cr4_features)
222 *trampoline_cr4_features = mmu_cr4_features;
223 cr4_set_bits(mask);
224 }
225
probe_page_size_mask(void)226 static void __init probe_page_size_mask(void)
227 {
228 /*
229 * For pagealloc debugging, identity mapping will use small pages.
230 * This will simplify cpa(), which otherwise needs to support splitting
231 * large pages into small in interrupt context, etc.
232 */
233 if (boot_cpu_has(X86_FEATURE_PSE) && !debug_pagealloc_enabled())
234 page_size_mask |= 1 << PG_LEVEL_2M;
235 else
236 direct_gbpages = 0;
237
238 /* Enable PSE if available */
239 if (boot_cpu_has(X86_FEATURE_PSE))
240 cr4_set_bits_and_update_boot(X86_CR4_PSE);
241
242 /* Enable PGE if available */
243 __supported_pte_mask &= ~_PAGE_GLOBAL;
244 if (boot_cpu_has(X86_FEATURE_PGE)) {
245 cr4_set_bits_and_update_boot(X86_CR4_PGE);
246 __supported_pte_mask |= _PAGE_GLOBAL;
247 }
248
249 /* By the default is everything supported: */
250 __default_kernel_pte_mask = __supported_pte_mask;
251 /* Except when with PTI where the kernel is mostly non-Global: */
252 if (cpu_feature_enabled(X86_FEATURE_PTI))
253 __default_kernel_pte_mask &= ~_PAGE_GLOBAL;
254
255 /* Enable 1 GB linear kernel mappings if available: */
256 if (direct_gbpages && boot_cpu_has(X86_FEATURE_GBPAGES)) {
257 printk(KERN_INFO "Using GB pages for direct mapping\n");
258 page_size_mask |= 1 << PG_LEVEL_1G;
259 } else {
260 direct_gbpages = 0;
261 }
262 }
263
264 /*
265 * INVLPG may not properly flush Global entries on
266 * these CPUs. New microcode fixes the issue.
267 */
268 static const struct x86_cpu_id invlpg_miss_ids[] = {
269 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, 0x2e),
270 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 0x42c),
271 X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, 0x11),
272 X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, 0x118),
273 X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, 0x4117),
274 X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, 0x2e),
275 {}
276 };
277
setup_pcid(void)278 static void setup_pcid(void)
279 {
280 const struct x86_cpu_id *invlpg_miss_match;
281
282 if (!IS_ENABLED(CONFIG_X86_64))
283 return;
284
285 if (!boot_cpu_has(X86_FEATURE_PCID))
286 return;
287
288 invlpg_miss_match = x86_match_cpu(invlpg_miss_ids);
289
290 if (invlpg_miss_match &&
291 boot_cpu_data.microcode < invlpg_miss_match->driver_data) {
292 pr_info("Incomplete global flushes, disabling PCID");
293 setup_clear_cpu_cap(X86_FEATURE_PCID);
294 return;
295 }
296
297 if (boot_cpu_has(X86_FEATURE_PGE)) {
298 /*
299 * This can't be cr4_set_bits_and_update_boot() -- the
300 * trampoline code can't handle CR4.PCIDE and it wouldn't
301 * do any good anyway. Despite the name,
302 * cr4_set_bits_and_update_boot() doesn't actually cause
303 * the bits in question to remain set all the way through
304 * the secondary boot asm.
305 *
306 * Instead, we brute-force it and set CR4.PCIDE manually in
307 * start_secondary().
308 */
309 cr4_set_bits(X86_CR4_PCIDE);
310 } else {
311 /*
312 * flush_tlb_all(), as currently implemented, won't work if
313 * PCID is on but PGE is not. Since that combination
314 * doesn't exist on real hardware, there's no reason to try
315 * to fully support it, but it's polite to avoid corrupting
316 * data if we're on an improperly configured VM.
317 */
318 setup_clear_cpu_cap(X86_FEATURE_PCID);
319 }
320 }
321
322 #ifdef CONFIG_X86_32
323 #define NR_RANGE_MR 3
324 #else /* CONFIG_X86_64 */
325 #define NR_RANGE_MR 5
326 #endif
327
save_mr(struct map_range * mr,int nr_range,unsigned long start_pfn,unsigned long end_pfn,unsigned long page_size_mask)328 static int __meminit save_mr(struct map_range *mr, int nr_range,
329 unsigned long start_pfn, unsigned long end_pfn,
330 unsigned long page_size_mask)
331 {
332 if (start_pfn < end_pfn) {
333 if (nr_range >= NR_RANGE_MR)
334 panic("run out of range for init_memory_mapping\n");
335 mr[nr_range].start = start_pfn<<PAGE_SHIFT;
336 mr[nr_range].end = end_pfn<<PAGE_SHIFT;
337 mr[nr_range].page_size_mask = page_size_mask;
338 nr_range++;
339 }
340
341 return nr_range;
342 }
343
344 /*
345 * adjust the page_size_mask for small range to go with
346 * big page size instead small one if nearby are ram too.
347 */
adjust_range_page_size_mask(struct map_range * mr,int nr_range)348 static void __ref adjust_range_page_size_mask(struct map_range *mr,
349 int nr_range)
350 {
351 int i;
352
353 for (i = 0; i < nr_range; i++) {
354 if ((page_size_mask & (1<<PG_LEVEL_2M)) &&
355 !(mr[i].page_size_mask & (1<<PG_LEVEL_2M))) {
356 unsigned long start = round_down(mr[i].start, PMD_SIZE);
357 unsigned long end = round_up(mr[i].end, PMD_SIZE);
358
359 #ifdef CONFIG_X86_32
360 if ((end >> PAGE_SHIFT) > max_low_pfn)
361 continue;
362 #endif
363
364 if (memblock_is_region_memory(start, end - start))
365 mr[i].page_size_mask |= 1<<PG_LEVEL_2M;
366 }
367 if ((page_size_mask & (1<<PG_LEVEL_1G)) &&
368 !(mr[i].page_size_mask & (1<<PG_LEVEL_1G))) {
369 unsigned long start = round_down(mr[i].start, PUD_SIZE);
370 unsigned long end = round_up(mr[i].end, PUD_SIZE);
371
372 if (memblock_is_region_memory(start, end - start))
373 mr[i].page_size_mask |= 1<<PG_LEVEL_1G;
374 }
375 }
376 }
377
page_size_string(struct map_range * mr)378 static const char *page_size_string(struct map_range *mr)
379 {
380 static const char str_1g[] = "1G";
381 static const char str_2m[] = "2M";
382 static const char str_4m[] = "4M";
383 static const char str_4k[] = "4k";
384
385 if (mr->page_size_mask & (1<<PG_LEVEL_1G))
386 return str_1g;
387 /*
388 * 32-bit without PAE has a 4M large page size.
389 * PG_LEVEL_2M is misnamed, but we can at least
390 * print out the right size in the string.
391 */
392 if (IS_ENABLED(CONFIG_X86_32) &&
393 !IS_ENABLED(CONFIG_X86_PAE) &&
394 mr->page_size_mask & (1<<PG_LEVEL_2M))
395 return str_4m;
396
397 if (mr->page_size_mask & (1<<PG_LEVEL_2M))
398 return str_2m;
399
400 return str_4k;
401 }
402
split_mem_range(struct map_range * mr,int nr_range,unsigned long start,unsigned long end)403 static int __meminit split_mem_range(struct map_range *mr, int nr_range,
404 unsigned long start,
405 unsigned long end)
406 {
407 unsigned long start_pfn, end_pfn, limit_pfn;
408 unsigned long pfn;
409 int i;
410
411 limit_pfn = PFN_DOWN(end);
412
413 /* head if not big page alignment ? */
414 pfn = start_pfn = PFN_DOWN(start);
415 #ifdef CONFIG_X86_32
416 /*
417 * Don't use a large page for the first 2/4MB of memory
418 * because there are often fixed size MTRRs in there
419 * and overlapping MTRRs into large pages can cause
420 * slowdowns.
421 */
422 if (pfn == 0)
423 end_pfn = PFN_DOWN(PMD_SIZE);
424 else
425 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
426 #else /* CONFIG_X86_64 */
427 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
428 #endif
429 if (end_pfn > limit_pfn)
430 end_pfn = limit_pfn;
431 if (start_pfn < end_pfn) {
432 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
433 pfn = end_pfn;
434 }
435
436 /* big page (2M) range */
437 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
438 #ifdef CONFIG_X86_32
439 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE));
440 #else /* CONFIG_X86_64 */
441 end_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE));
442 if (end_pfn > round_down(limit_pfn, PFN_DOWN(PMD_SIZE)))
443 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE));
444 #endif
445
446 if (start_pfn < end_pfn) {
447 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
448 page_size_mask & (1<<PG_LEVEL_2M));
449 pfn = end_pfn;
450 }
451
452 #ifdef CONFIG_X86_64
453 /* big page (1G) range */
454 start_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE));
455 end_pfn = round_down(limit_pfn, PFN_DOWN(PUD_SIZE));
456 if (start_pfn < end_pfn) {
457 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
458 page_size_mask &
459 ((1<<PG_LEVEL_2M)|(1<<PG_LEVEL_1G)));
460 pfn = end_pfn;
461 }
462
463 /* tail is not big page (1G) alignment */
464 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
465 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE));
466 if (start_pfn < end_pfn) {
467 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
468 page_size_mask & (1<<PG_LEVEL_2M));
469 pfn = end_pfn;
470 }
471 #endif
472
473 /* tail is not big page (2M) alignment */
474 start_pfn = pfn;
475 end_pfn = limit_pfn;
476 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
477
478 if (!after_bootmem)
479 adjust_range_page_size_mask(mr, nr_range);
480
481 /* try to merge same page size and continuous */
482 for (i = 0; nr_range > 1 && i < nr_range - 1; i++) {
483 unsigned long old_start;
484 if (mr[i].end != mr[i+1].start ||
485 mr[i].page_size_mask != mr[i+1].page_size_mask)
486 continue;
487 /* move it */
488 old_start = mr[i].start;
489 memmove(&mr[i], &mr[i+1],
490 (nr_range - 1 - i) * sizeof(struct map_range));
491 mr[i--].start = old_start;
492 nr_range--;
493 }
494
495 for (i = 0; i < nr_range; i++)
496 pr_debug(" [mem %#010lx-%#010lx] page %s\n",
497 mr[i].start, mr[i].end - 1,
498 page_size_string(&mr[i]));
499
500 return nr_range;
501 }
502
503 struct range pfn_mapped[E820_MAX_ENTRIES];
504 int nr_pfn_mapped;
505
add_pfn_range_mapped(unsigned long start_pfn,unsigned long end_pfn)506 static void add_pfn_range_mapped(unsigned long start_pfn, unsigned long end_pfn)
507 {
508 nr_pfn_mapped = add_range_with_merge(pfn_mapped, E820_MAX_ENTRIES,
509 nr_pfn_mapped, start_pfn, end_pfn);
510 nr_pfn_mapped = clean_sort_range(pfn_mapped, E820_MAX_ENTRIES);
511
512 max_pfn_mapped = max(max_pfn_mapped, end_pfn);
513
514 if (start_pfn < (1UL<<(32-PAGE_SHIFT)))
515 max_low_pfn_mapped = max(max_low_pfn_mapped,
516 min(end_pfn, 1UL<<(32-PAGE_SHIFT)));
517 }
518
pfn_range_is_mapped(unsigned long start_pfn,unsigned long end_pfn)519 bool pfn_range_is_mapped(unsigned long start_pfn, unsigned long end_pfn)
520 {
521 int i;
522
523 for (i = 0; i < nr_pfn_mapped; i++)
524 if ((start_pfn >= pfn_mapped[i].start) &&
525 (end_pfn <= pfn_mapped[i].end))
526 return true;
527
528 return false;
529 }
530
531 /*
532 * Setup the direct mapping of the physical memory at PAGE_OFFSET.
533 * This runs before bootmem is initialized and gets pages directly from
534 * the physical memory. To access them they are temporarily mapped.
535 */
init_memory_mapping(unsigned long start,unsigned long end,pgprot_t prot)536 unsigned long __ref init_memory_mapping(unsigned long start,
537 unsigned long end, pgprot_t prot)
538 {
539 struct map_range mr[NR_RANGE_MR];
540 unsigned long ret = 0;
541 int nr_range, i;
542
543 pr_debug("init_memory_mapping: [mem %#010lx-%#010lx]\n",
544 start, end - 1);
545
546 memset(mr, 0, sizeof(mr));
547 nr_range = split_mem_range(mr, 0, start, end);
548
549 for (i = 0; i < nr_range; i++)
550 ret = kernel_physical_mapping_init(mr[i].start, mr[i].end,
551 mr[i].page_size_mask,
552 prot);
553
554 add_pfn_range_mapped(start >> PAGE_SHIFT, ret >> PAGE_SHIFT);
555
556 return ret >> PAGE_SHIFT;
557 }
558
559 /*
560 * We need to iterate through the E820 memory map and create direct mappings
561 * for only E820_TYPE_RAM and E820_KERN_RESERVED regions. We cannot simply
562 * create direct mappings for all pfns from [0 to max_low_pfn) and
563 * [4GB to max_pfn) because of possible memory holes in high addresses
564 * that cannot be marked as UC by fixed/variable range MTRRs.
565 * Depending on the alignment of E820 ranges, this may possibly result
566 * in using smaller size (i.e. 4K instead of 2M or 1G) page tables.
567 *
568 * init_mem_mapping() calls init_range_memory_mapping() with big range.
569 * That range would have hole in the middle or ends, and only ram parts
570 * will be mapped in init_range_memory_mapping().
571 */
init_range_memory_mapping(unsigned long r_start,unsigned long r_end)572 static unsigned long __init init_range_memory_mapping(
573 unsigned long r_start,
574 unsigned long r_end)
575 {
576 unsigned long start_pfn, end_pfn;
577 unsigned long mapped_ram_size = 0;
578 int i;
579
580 for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) {
581 u64 start = clamp_val(PFN_PHYS(start_pfn), r_start, r_end);
582 u64 end = clamp_val(PFN_PHYS(end_pfn), r_start, r_end);
583 if (start >= end)
584 continue;
585
586 /*
587 * if it is overlapping with brk pgt, we need to
588 * alloc pgt buf from memblock instead.
589 */
590 can_use_brk_pgt = max(start, (u64)pgt_buf_end<<PAGE_SHIFT) >=
591 min(end, (u64)pgt_buf_top<<PAGE_SHIFT);
592 init_memory_mapping(start, end, PAGE_KERNEL);
593 mapped_ram_size += end - start;
594 can_use_brk_pgt = true;
595 }
596
597 return mapped_ram_size;
598 }
599
get_new_step_size(unsigned long step_size)600 static unsigned long __init get_new_step_size(unsigned long step_size)
601 {
602 /*
603 * Initial mapped size is PMD_SIZE (2M).
604 * We can not set step_size to be PUD_SIZE (1G) yet.
605 * In worse case, when we cross the 1G boundary, and
606 * PG_LEVEL_2M is not set, we will need 1+1+512 pages (2M + 8k)
607 * to map 1G range with PTE. Hence we use one less than the
608 * difference of page table level shifts.
609 *
610 * Don't need to worry about overflow in the top-down case, on 32bit,
611 * when step_size is 0, round_down() returns 0 for start, and that
612 * turns it into 0x100000000ULL.
613 * In the bottom-up case, round_up(x, 0) returns 0 though too, which
614 * needs to be taken into consideration by the code below.
615 */
616 return step_size << (PMD_SHIFT - PAGE_SHIFT - 1);
617 }
618
619 /**
620 * memory_map_top_down - Map [map_start, map_end) top down
621 * @map_start: start address of the target memory range
622 * @map_end: end address of the target memory range
623 *
624 * This function will setup direct mapping for memory range
625 * [map_start, map_end) in top-down. That said, the page tables
626 * will be allocated at the end of the memory, and we map the
627 * memory in top-down.
628 */
memory_map_top_down(unsigned long map_start,unsigned long map_end)629 static void __init memory_map_top_down(unsigned long map_start,
630 unsigned long map_end)
631 {
632 unsigned long real_end, last_start;
633 unsigned long step_size;
634 unsigned long addr;
635 unsigned long mapped_ram_size = 0;
636
637 /*
638 * Systems that have many reserved areas near top of the memory,
639 * e.g. QEMU with less than 1G RAM and EFI enabled, or Xen, will
640 * require lots of 4K mappings which may exhaust pgt_buf.
641 * Start with top-most PMD_SIZE range aligned at PMD_SIZE to ensure
642 * there is enough mapped memory that can be allocated from
643 * memblock.
644 */
645 addr = memblock_phys_alloc_range(PMD_SIZE, PMD_SIZE, map_start,
646 map_end);
647 memblock_phys_free(addr, PMD_SIZE);
648 real_end = addr + PMD_SIZE;
649
650 /* step_size need to be small so pgt_buf from BRK could cover it */
651 step_size = PMD_SIZE;
652 max_pfn_mapped = 0; /* will get exact value next */
653 min_pfn_mapped = real_end >> PAGE_SHIFT;
654 last_start = real_end;
655
656 /*
657 * We start from the top (end of memory) and go to the bottom.
658 * The memblock_find_in_range() gets us a block of RAM from the
659 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages
660 * for page table.
661 */
662 while (last_start > map_start) {
663 unsigned long start;
664
665 if (last_start > step_size) {
666 start = round_down(last_start - 1, step_size);
667 if (start < map_start)
668 start = map_start;
669 } else
670 start = map_start;
671 mapped_ram_size += init_range_memory_mapping(start,
672 last_start);
673 last_start = start;
674 min_pfn_mapped = last_start >> PAGE_SHIFT;
675 if (mapped_ram_size >= step_size)
676 step_size = get_new_step_size(step_size);
677 }
678
679 if (real_end < map_end)
680 init_range_memory_mapping(real_end, map_end);
681 }
682
683 /**
684 * memory_map_bottom_up - Map [map_start, map_end) bottom up
685 * @map_start: start address of the target memory range
686 * @map_end: end address of the target memory range
687 *
688 * This function will setup direct mapping for memory range
689 * [map_start, map_end) in bottom-up. Since we have limited the
690 * bottom-up allocation above the kernel, the page tables will
691 * be allocated just above the kernel and we map the memory
692 * in [map_start, map_end) in bottom-up.
693 */
memory_map_bottom_up(unsigned long map_start,unsigned long map_end)694 static void __init memory_map_bottom_up(unsigned long map_start,
695 unsigned long map_end)
696 {
697 unsigned long next, start;
698 unsigned long mapped_ram_size = 0;
699 /* step_size need to be small so pgt_buf from BRK could cover it */
700 unsigned long step_size = PMD_SIZE;
701
702 start = map_start;
703 min_pfn_mapped = start >> PAGE_SHIFT;
704
705 /*
706 * We start from the bottom (@map_start) and go to the top (@map_end).
707 * The memblock_find_in_range() gets us a block of RAM from the
708 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages
709 * for page table.
710 */
711 while (start < map_end) {
712 if (step_size && map_end - start > step_size) {
713 next = round_up(start + 1, step_size);
714 if (next > map_end)
715 next = map_end;
716 } else {
717 next = map_end;
718 }
719
720 mapped_ram_size += init_range_memory_mapping(start, next);
721 start = next;
722
723 if (mapped_ram_size >= step_size)
724 step_size = get_new_step_size(step_size);
725 }
726 }
727
728 /*
729 * The real mode trampoline, which is required for bootstrapping CPUs
730 * occupies only a small area under the low 1MB. See reserve_real_mode()
731 * for details.
732 *
733 * If KASLR is disabled the first PGD entry of the direct mapping is copied
734 * to map the real mode trampoline.
735 *
736 * If KASLR is enabled, copy only the PUD which covers the low 1MB
737 * area. This limits the randomization granularity to 1GB for both 4-level
738 * and 5-level paging.
739 */
init_trampoline(void)740 static void __init init_trampoline(void)
741 {
742 #ifdef CONFIG_X86_64
743 /*
744 * The code below will alias kernel page-tables in the user-range of the
745 * address space, including the Global bit. So global TLB entries will
746 * be created when using the trampoline page-table.
747 */
748 if (!kaslr_memory_enabled())
749 trampoline_pgd_entry = init_top_pgt[pgd_index(__PAGE_OFFSET)];
750 else
751 init_trampoline_kaslr();
752 #endif
753 }
754
init_mem_mapping(void)755 void __init init_mem_mapping(void)
756 {
757 unsigned long end;
758
759 pti_check_boottime_disable();
760 probe_page_size_mask();
761 setup_pcid();
762
763 #ifdef CONFIG_X86_64
764 end = max_pfn << PAGE_SHIFT;
765 #else
766 end = max_low_pfn << PAGE_SHIFT;
767 #endif
768
769 /* the ISA range is always mapped regardless of memory holes */
770 init_memory_mapping(0, ISA_END_ADDRESS, PAGE_KERNEL);
771
772 /* Init the trampoline, possibly with KASLR memory offset */
773 init_trampoline();
774
775 /*
776 * If the allocation is in bottom-up direction, we setup direct mapping
777 * in bottom-up, otherwise we setup direct mapping in top-down.
778 */
779 if (memblock_bottom_up()) {
780 unsigned long kernel_end = __pa_symbol(_end);
781
782 /*
783 * we need two separate calls here. This is because we want to
784 * allocate page tables above the kernel. So we first map
785 * [kernel_end, end) to make memory above the kernel be mapped
786 * as soon as possible. And then use page tables allocated above
787 * the kernel to map [ISA_END_ADDRESS, kernel_end).
788 */
789 memory_map_bottom_up(kernel_end, end);
790 memory_map_bottom_up(ISA_END_ADDRESS, kernel_end);
791 } else {
792 memory_map_top_down(ISA_END_ADDRESS, end);
793 }
794
795 #ifdef CONFIG_X86_64
796 if (max_pfn > max_low_pfn) {
797 /* can we preserve max_low_pfn ?*/
798 max_low_pfn = max_pfn;
799 }
800 #else
801 early_ioremap_page_table_range_init();
802 #endif
803
804 load_cr3(swapper_pg_dir);
805 __flush_tlb_all();
806
807 x86_init.hyper.init_mem_mapping();
808
809 early_memtest(0, max_pfn_mapped << PAGE_SHIFT);
810 }
811
812 /*
813 * Initialize an mm_struct to be used during poking and a pointer to be used
814 * during patching.
815 */
poking_init(void)816 void __init poking_init(void)
817 {
818 spinlock_t *ptl;
819 pte_t *ptep;
820
821 poking_mm = mm_alloc();
822 BUG_ON(!poking_mm);
823
824 /* Xen PV guests need the PGD to be pinned. */
825 paravirt_enter_mmap(poking_mm);
826
827 /*
828 * Randomize the poking address, but make sure that the following page
829 * will be mapped at the same PMD. We need 2 pages, so find space for 3,
830 * and adjust the address if the PMD ends after the first one.
831 */
832 poking_addr = TASK_UNMAPPED_BASE;
833 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE))
834 poking_addr += (kaslr_get_random_long("Poking") & PAGE_MASK) %
835 (TASK_SIZE - TASK_UNMAPPED_BASE - 3 * PAGE_SIZE);
836
837 if (((poking_addr + PAGE_SIZE) & ~PMD_MASK) == 0)
838 poking_addr += PAGE_SIZE;
839
840 /*
841 * We need to trigger the allocation of the page-tables that will be
842 * needed for poking now. Later, poking may be performed in an atomic
843 * section, which might cause allocation to fail.
844 */
845 ptep = get_locked_pte(poking_mm, poking_addr, &ptl);
846 BUG_ON(!ptep);
847 pte_unmap_unlock(ptep, ptl);
848 }
849
850 /*
851 * devmem_is_allowed() checks to see if /dev/mem access to a certain address
852 * is valid. The argument is a physical page number.
853 *
854 * On x86, access has to be given to the first megabyte of RAM because that
855 * area traditionally contains BIOS code and data regions used by X, dosemu,
856 * and similar apps. Since they map the entire memory range, the whole range
857 * must be allowed (for mapping), but any areas that would otherwise be
858 * disallowed are flagged as being "zero filled" instead of rejected.
859 * Access has to be given to non-kernel-ram areas as well, these contain the
860 * PCI mmio resources as well as potential bios/acpi data regions.
861 */
devmem_is_allowed(unsigned long pagenr)862 int devmem_is_allowed(unsigned long pagenr)
863 {
864 if (region_intersects(PFN_PHYS(pagenr), PAGE_SIZE,
865 IORESOURCE_SYSTEM_RAM, IORES_DESC_NONE)
866 != REGION_DISJOINT) {
867 /*
868 * For disallowed memory regions in the low 1MB range,
869 * request that the page be shown as all zeros.
870 */
871 if (pagenr < 256)
872 return 2;
873
874 return 0;
875 }
876
877 /*
878 * This must follow RAM test, since System RAM is considered a
879 * restricted resource under CONFIG_STRICT_DEVMEM.
880 */
881 if (iomem_is_exclusive(pagenr << PAGE_SHIFT)) {
882 /* Low 1MB bypasses iomem restrictions. */
883 if (pagenr < 256)
884 return 1;
885
886 return 0;
887 }
888
889 return 1;
890 }
891
free_init_pages(const char * what,unsigned long begin,unsigned long end)892 void free_init_pages(const char *what, unsigned long begin, unsigned long end)
893 {
894 unsigned long begin_aligned, end_aligned;
895
896 /* Make sure boundaries are page aligned */
897 begin_aligned = PAGE_ALIGN(begin);
898 end_aligned = end & PAGE_MASK;
899
900 if (WARN_ON(begin_aligned != begin || end_aligned != end)) {
901 begin = begin_aligned;
902 end = end_aligned;
903 }
904
905 if (begin >= end)
906 return;
907
908 /*
909 * If debugging page accesses then do not free this memory but
910 * mark them not present - any buggy init-section access will
911 * create a kernel page fault:
912 */
913 if (debug_pagealloc_enabled()) {
914 pr_info("debug: unmapping init [mem %#010lx-%#010lx]\n",
915 begin, end - 1);
916 /*
917 * Inform kmemleak about the hole in the memory since the
918 * corresponding pages will be unmapped.
919 */
920 kmemleak_free_part((void *)begin, end - begin);
921 set_memory_np(begin, (end - begin) >> PAGE_SHIFT);
922 } else {
923 /*
924 * We just marked the kernel text read only above, now that
925 * we are going to free part of that, we need to make that
926 * writeable and non-executable first.
927 */
928 set_memory_nx(begin, (end - begin) >> PAGE_SHIFT);
929 set_memory_rw(begin, (end - begin) >> PAGE_SHIFT);
930
931 free_reserved_area((void *)begin, (void *)end,
932 POISON_FREE_INITMEM, what);
933 }
934 }
935
936 /*
937 * begin/end can be in the direct map or the "high kernel mapping"
938 * used for the kernel image only. free_init_pages() will do the
939 * right thing for either kind of address.
940 */
free_kernel_image_pages(const char * what,void * begin,void * end)941 void free_kernel_image_pages(const char *what, void *begin, void *end)
942 {
943 unsigned long begin_ul = (unsigned long)begin;
944 unsigned long end_ul = (unsigned long)end;
945 unsigned long len_pages = (end_ul - begin_ul) >> PAGE_SHIFT;
946
947 free_init_pages(what, begin_ul, end_ul);
948
949 /*
950 * PTI maps some of the kernel into userspace. For performance,
951 * this includes some kernel areas that do not contain secrets.
952 * Those areas might be adjacent to the parts of the kernel image
953 * being freed, which may contain secrets. Remove the "high kernel
954 * image mapping" for these freed areas, ensuring they are not even
955 * potentially vulnerable to Meltdown regardless of the specific
956 * optimizations PTI is currently using.
957 *
958 * The "noalias" prevents unmapping the direct map alias which is
959 * needed to access the freed pages.
960 *
961 * This is only valid for 64bit kernels. 32bit has only one mapping
962 * which can't be treated in this way for obvious reasons.
963 */
964 if (IS_ENABLED(CONFIG_X86_64) && cpu_feature_enabled(X86_FEATURE_PTI))
965 set_memory_np_noalias(begin_ul, len_pages);
966 }
967
free_initmem(void)968 void __ref free_initmem(void)
969 {
970 e820__reallocate_tables();
971
972 mem_encrypt_free_decrypted_mem();
973
974 free_kernel_image_pages("unused kernel image (initmem)",
975 &__init_begin, &__init_end);
976 }
977
978 #ifdef CONFIG_BLK_DEV_INITRD
free_initrd_mem(unsigned long start,unsigned long end)979 void __init free_initrd_mem(unsigned long start, unsigned long end)
980 {
981 /*
982 * end could be not aligned, and We can not align that,
983 * decompressor could be confused by aligned initrd_end
984 * We already reserve the end partial page before in
985 * - i386_start_kernel()
986 * - x86_64_start_kernel()
987 * - relocate_initrd()
988 * So here We can do PAGE_ALIGN() safely to get partial page to be freed
989 */
990 free_init_pages("initrd", start, PAGE_ALIGN(end));
991 }
992 #endif
993
994 /*
995 * Calculate the precise size of the DMA zone (first 16 MB of RAM),
996 * and pass it to the MM layer - to help it set zone watermarks more
997 * accurately.
998 *
999 * Done on 64-bit systems only for the time being, although 32-bit systems
1000 * might benefit from this as well.
1001 */
memblock_find_dma_reserve(void)1002 void __init memblock_find_dma_reserve(void)
1003 {
1004 #ifdef CONFIG_X86_64
1005 u64 nr_pages = 0, nr_free_pages = 0;
1006 unsigned long start_pfn, end_pfn;
1007 phys_addr_t start_addr, end_addr;
1008 int i;
1009 u64 u;
1010
1011 /*
1012 * Iterate over all memory ranges (free and reserved ones alike),
1013 * to calculate the total number of pages in the first 16 MB of RAM:
1014 */
1015 nr_pages = 0;
1016 for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) {
1017 start_pfn = min(start_pfn, MAX_DMA_PFN);
1018 end_pfn = min(end_pfn, MAX_DMA_PFN);
1019
1020 nr_pages += end_pfn - start_pfn;
1021 }
1022
1023 /*
1024 * Iterate over free memory ranges to calculate the number of free
1025 * pages in the DMA zone, while not counting potential partial
1026 * pages at the beginning or the end of the range:
1027 */
1028 nr_free_pages = 0;
1029 for_each_free_mem_range(u, NUMA_NO_NODE, MEMBLOCK_NONE, &start_addr, &end_addr, NULL) {
1030 start_pfn = min_t(unsigned long, PFN_UP(start_addr), MAX_DMA_PFN);
1031 end_pfn = min_t(unsigned long, PFN_DOWN(end_addr), MAX_DMA_PFN);
1032
1033 if (start_pfn < end_pfn)
1034 nr_free_pages += end_pfn - start_pfn;
1035 }
1036
1037 set_dma_reserve(nr_pages - nr_free_pages);
1038 #endif
1039 }
1040
zone_sizes_init(void)1041 void __init zone_sizes_init(void)
1042 {
1043 unsigned long max_zone_pfns[MAX_NR_ZONES];
1044
1045 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1046
1047 #ifdef CONFIG_ZONE_DMA
1048 max_zone_pfns[ZONE_DMA] = min(MAX_DMA_PFN, max_low_pfn);
1049 #endif
1050 #ifdef CONFIG_ZONE_DMA32
1051 max_zone_pfns[ZONE_DMA32] = min(MAX_DMA32_PFN, max_low_pfn);
1052 #endif
1053 max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
1054 #ifdef CONFIG_HIGHMEM
1055 max_zone_pfns[ZONE_HIGHMEM] = max_pfn;
1056 #endif
1057
1058 free_area_init(max_zone_pfns);
1059 }
1060
1061 __visible DEFINE_PER_CPU_ALIGNED(struct tlb_state, cpu_tlbstate) = {
1062 .loaded_mm = &init_mm,
1063 .next_asid = 1,
1064 .cr4 = ~0UL, /* fail hard if we screw up cr4 shadow initialization */
1065 };
1066
1067 #ifdef CONFIG_ADDRESS_MASKING
1068 DEFINE_PER_CPU(u64, tlbstate_untag_mask);
1069 EXPORT_PER_CPU_SYMBOL(tlbstate_untag_mask);
1070 #endif
1071
update_cache_mode_entry(unsigned entry,enum page_cache_mode cache)1072 void update_cache_mode_entry(unsigned entry, enum page_cache_mode cache)
1073 {
1074 /* entry 0 MUST be WB (hardwired to speed up translations) */
1075 BUG_ON(!entry && cache != _PAGE_CACHE_MODE_WB);
1076
1077 __cachemode2pte_tbl[cache] = __cm_idx2pte(entry);
1078 __pte2cachemode_tbl[entry] = cache;
1079 }
1080
1081 #ifdef CONFIG_SWAP
arch_max_swapfile_size(void)1082 unsigned long arch_max_swapfile_size(void)
1083 {
1084 unsigned long pages;
1085
1086 pages = generic_max_swapfile_size();
1087
1088 if (boot_cpu_has_bug(X86_BUG_L1TF) && l1tf_mitigation != L1TF_MITIGATION_OFF) {
1089 /* Limit the swap file size to MAX_PA/2 for L1TF workaround */
1090 unsigned long long l1tf_limit = l1tf_pfn_limit();
1091 /*
1092 * We encode swap offsets also with 3 bits below those for pfn
1093 * which makes the usable limit higher.
1094 */
1095 #if CONFIG_PGTABLE_LEVELS > 2
1096 l1tf_limit <<= PAGE_SHIFT - SWP_OFFSET_FIRST_BIT;
1097 #endif
1098 pages = min_t(unsigned long long, l1tf_limit, pages);
1099 }
1100 return pages;
1101 }
1102 #endif
1103