1 /*
2 * PowerPC implementation of KVM hooks
3 *
4 * Copyright IBM Corp. 2007
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * Authors:
8 * Jerone Young <jyoung5@us.ibm.com>
9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
10 * Hollis Blanchard <hollisb@us.ibm.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2 or later.
13 * See the COPYING file in the top-level directory.
14 *
15 */
16
17 #include "qemu/osdep.h"
18 #include <dirent.h>
19 #include <sys/ioctl.h>
20 #include <sys/vfs.h>
21
22 #include <linux/kvm.h>
23
24 #include "qapi/error.h"
25 #include "qemu/error-report.h"
26 #include "cpu.h"
27 #include "cpu-models.h"
28 #include "qemu/timer.h"
29 #include "system/hw_accel.h"
30 #include "kvm_ppc.h"
31 #include "system/cpus.h"
32 #include "system/device_tree.h"
33 #include "mmu-hash64.h"
34
35 #include "hw/ppc/spapr.h"
36 #include "hw/ppc/spapr_cpu_core.h"
37 #include "hw/hw.h"
38 #include "hw/ppc/ppc.h"
39 #include "migration/qemu-file-types.h"
40 #include "system/watchdog.h"
41 #include "trace.h"
42 #include "gdbstub/enums.h"
43 #include "exec/memattrs.h"
44 #include "exec/ram_addr.h"
45 #include "system/hostmem.h"
46 #include "qemu/cutils.h"
47 #include "qemu/main-loop.h"
48 #include "qemu/mmap-alloc.h"
49 #include "elf.h"
50 #include "system/kvm_int.h"
51 #include "system/kvm.h"
52 #include "accel/accel-cpu-target.h"
53
54 #include CONFIG_DEVICES
55
56 #define PROC_DEVTREE_CPU "/proc/device-tree/cpus/"
57
58 #define DEBUG_RETURN_GUEST 0
59 #define DEBUG_RETURN_GDB 1
60
61 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
62 KVM_CAP_LAST_INFO
63 };
64
65 static int cap_interrupt_unset;
66 static int cap_segstate;
67 static int cap_booke_sregs;
68 static int cap_ppc_smt;
69 static int cap_ppc_smt_possible;
70 static int cap_spapr_tce;
71 static int cap_spapr_tce_64;
72 static int cap_spapr_multitce;
73 static int cap_spapr_vfio;
74 static int cap_hior;
75 static int cap_one_reg;
76 static int cap_epr;
77 static int cap_ppc_watchdog;
78 static int cap_htab_fd;
79 static int cap_fixup_hcalls;
80 static int cap_htm; /* Hardware transactional memory support */
81 static int cap_mmu_radix;
82 static int cap_mmu_hash_v3;
83 static int cap_xive;
84 static int cap_resize_hpt;
85 static int cap_ppc_pvr_compat;
86 static int cap_ppc_safe_cache;
87 static int cap_ppc_safe_bounds_check;
88 static int cap_ppc_safe_indirect_branch;
89 static int cap_ppc_count_cache_flush_assist;
90 static int cap_ppc_nested_kvm_hv;
91 static int cap_large_decr;
92 static int cap_fwnmi;
93 static int cap_rpt_invalidate;
94 static int cap_ail_mode_3;
95 static int cap_dawr1;
96
97 #ifdef CONFIG_PSERIES
98 static int cap_papr;
99 #else
100 #define cap_papr (0)
101 #endif
102
103 static uint32_t debug_inst_opcode;
104
105 /*
106 * Check whether we are running with KVM-PR (instead of KVM-HV). This
107 * should only be used for fallback tests - generally we should use
108 * explicit capabilities for the features we want, rather than
109 * assuming what is/isn't available depending on the KVM variant.
110 */
kvmppc_is_pr(KVMState * ks)111 static bool kvmppc_is_pr(KVMState *ks)
112 {
113 /* Assume KVM-PR if the GET_PVINFO capability is available */
114 return kvm_vm_check_extension(ks, KVM_CAP_PPC_GET_PVINFO) != 0;
115 }
116
117 static int kvm_ppc_register_host_cpu_type(void);
118 static void kvmppc_get_cpu_characteristics(KVMState *s);
119 static int kvmppc_get_dec_bits(void);
120
kvm_arch_get_default_type(MachineState * ms)121 int kvm_arch_get_default_type(MachineState *ms)
122 {
123 return 0;
124 }
125
kvm_arch_init(MachineState * ms,KVMState * s)126 int kvm_arch_init(MachineState *ms, KVMState *s)
127 {
128 cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ);
129 cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE);
130 cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS);
131 cap_ppc_smt_possible = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE);
132 cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE);
133 cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64);
134 cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE);
135 cap_spapr_vfio = kvm_vm_check_extension(s, KVM_CAP_SPAPR_TCE_VFIO);
136 cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG);
137 cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR);
138 cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR);
139 cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG);
140 /*
141 * Note: we don't set cap_papr here, because this capability is
142 * only activated after this by kvmppc_set_papr()
143 */
144 cap_htab_fd = kvm_vm_check_extension(s, KVM_CAP_PPC_HTAB_FD);
145 cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL);
146 cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT);
147 cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM);
148 cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX);
149 cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3);
150 cap_xive = kvm_vm_check_extension(s, KVM_CAP_PPC_IRQ_XIVE);
151 cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT);
152 kvmppc_get_cpu_characteristics(s);
153 cap_ppc_nested_kvm_hv = kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED_HV);
154 cap_large_decr = kvmppc_get_dec_bits();
155 cap_fwnmi = kvm_vm_check_extension(s, KVM_CAP_PPC_FWNMI);
156 cap_dawr1 = kvm_vm_check_extension(s, KVM_CAP_PPC_DAWR1);
157 /*
158 * Note: setting it to false because there is not such capability
159 * in KVM at this moment.
160 *
161 * TODO: call kvm_vm_check_extension() with the right capability
162 * after the kernel starts implementing it.
163 */
164 cap_ppc_pvr_compat = false;
165
166 if (!kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL)) {
167 error_report("KVM: Host kernel doesn't have level irq capability");
168 exit(1);
169 }
170
171 cap_rpt_invalidate = kvm_vm_check_extension(s, KVM_CAP_PPC_RPT_INVALIDATE);
172 cap_ail_mode_3 = kvm_vm_check_extension(s, KVM_CAP_PPC_AIL_MODE_3);
173 kvm_ppc_register_host_cpu_type();
174
175 return 0;
176 }
177
kvm_arch_irqchip_create(KVMState * s)178 int kvm_arch_irqchip_create(KVMState *s)
179 {
180 return 0;
181 }
182
kvm_arch_sync_sregs(PowerPCCPU * cpu)183 static int kvm_arch_sync_sregs(PowerPCCPU *cpu)
184 {
185 CPUPPCState *cenv = &cpu->env;
186 CPUState *cs = CPU(cpu);
187 struct kvm_sregs sregs;
188 int ret;
189
190 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
191 /*
192 * What we're really trying to say is "if we're on BookE, we
193 * use the native PVR for now". This is the only sane way to
194 * check it though, so we potentially confuse users that they
195 * can run BookE guests on BookS. Let's hope nobody dares
196 * enough :)
197 */
198 return 0;
199 } else {
200 if (!cap_segstate) {
201 fprintf(stderr, "kvm error: missing PVR setting capability\n");
202 return -ENOSYS;
203 }
204 }
205
206 ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs);
207 if (ret) {
208 return ret;
209 }
210
211 sregs.pvr = cenv->spr[SPR_PVR];
212 return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs);
213 }
214
215 /* Set up a shared TLB array with KVM */
kvm_booke206_tlb_init(PowerPCCPU * cpu)216 static int kvm_booke206_tlb_init(PowerPCCPU *cpu)
217 {
218 CPUPPCState *env = &cpu->env;
219 CPUState *cs = CPU(cpu);
220 struct kvm_book3e_206_tlb_params params = {};
221 struct kvm_config_tlb cfg = {};
222 unsigned int entries = 0;
223 int ret, i;
224
225 if (!kvm_enabled() ||
226 !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) {
227 return 0;
228 }
229
230 assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN);
231
232 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
233 params.tlb_sizes[i] = booke206_tlb_size(env, i);
234 params.tlb_ways[i] = booke206_tlb_ways(env, i);
235 entries += params.tlb_sizes[i];
236 }
237
238 assert(entries == env->nb_tlb);
239 assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t));
240
241 env->tlb_dirty = true;
242
243 cfg.array = (uintptr_t)env->tlb.tlbm;
244 cfg.array_len = sizeof(ppcmas_tlb_t) * entries;
245 cfg.params = (uintptr_t)¶ms;
246 cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV;
247
248 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg);
249 if (ret < 0) {
250 fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",
251 __func__, strerror(-ret));
252 return ret;
253 }
254
255 env->kvm_sw_tlb = true;
256 return 0;
257 }
258
259
260 #if defined(TARGET_PPC64)
kvm_get_smmu_info(struct kvm_ppc_smmu_info * info,Error ** errp)261 static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp)
262 {
263 int ret;
264
265 assert(kvm_state != NULL);
266
267 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) {
268 error_setg(errp, "KVM doesn't expose the MMU features it supports");
269 error_append_hint(errp, "Consider switching to a newer KVM\n");
270 return;
271 }
272
273 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_SMMU_INFO, info);
274 if (ret == 0) {
275 return;
276 }
277
278 error_setg_errno(errp, -ret,
279 "KVM failed to provide the MMU features it supports");
280 }
281
kvmppc_get_radix_page_info(void)282 static struct ppc_radix_page_info *kvmppc_get_radix_page_info(void)
283 {
284 KVMState *s = KVM_STATE(current_accel());
285 struct ppc_radix_page_info *radix_page_info;
286 struct kvm_ppc_rmmu_info rmmu_info = { };
287 int i;
288
289 if (!kvm_check_extension(s, KVM_CAP_PPC_MMU_RADIX)) {
290 return NULL;
291 }
292 if (kvm_vm_ioctl(s, KVM_PPC_GET_RMMU_INFO, &rmmu_info)) {
293 return NULL;
294 }
295 radix_page_info = g_malloc0(sizeof(*radix_page_info));
296 radix_page_info->count = 0;
297 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
298 if (rmmu_info.ap_encodings[i]) {
299 radix_page_info->entries[i] = rmmu_info.ap_encodings[i];
300 radix_page_info->count++;
301 }
302 }
303 return radix_page_info;
304 }
305
kvmppc_configure_v3_mmu(PowerPCCPU * cpu,bool radix,bool gtse,uint64_t proc_tbl)306 target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu,
307 bool radix, bool gtse,
308 uint64_t proc_tbl)
309 {
310 CPUState *cs = CPU(cpu);
311 int ret;
312 uint64_t flags = 0;
313 struct kvm_ppc_mmuv3_cfg cfg = {
314 .process_table = proc_tbl,
315 };
316
317 if (radix) {
318 flags |= KVM_PPC_MMUV3_RADIX;
319 }
320 if (gtse) {
321 flags |= KVM_PPC_MMUV3_GTSE;
322 }
323 cfg.flags = flags;
324 ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_CONFIGURE_V3_MMU, &cfg);
325 switch (ret) {
326 case 0:
327 return H_SUCCESS;
328 case -EINVAL:
329 return H_PARAMETER;
330 case -ENODEV:
331 return H_NOT_AVAILABLE;
332 default:
333 return H_HARDWARE;
334 }
335 }
336
kvmppc_hpt_needs_host_contiguous_pages(void)337 bool kvmppc_hpt_needs_host_contiguous_pages(void)
338 {
339 static struct kvm_ppc_smmu_info smmu_info;
340
341 if (!kvm_enabled()) {
342 return false;
343 }
344
345 kvm_get_smmu_info(&smmu_info, &error_fatal);
346 return !!(smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL);
347 }
348
kvm_check_mmu(PowerPCCPU * cpu,Error ** errp)349 void kvm_check_mmu(PowerPCCPU *cpu, Error **errp)
350 {
351 struct kvm_ppc_smmu_info smmu_info;
352 int iq, ik, jq, jk;
353 Error *local_err = NULL;
354
355 /* For now, we only have anything to check on hash64 MMUs */
356 if (!cpu->hash64_opts || !kvm_enabled()) {
357 return;
358 }
359
360 kvm_get_smmu_info(&smmu_info, &local_err);
361 if (local_err) {
362 error_propagate(errp, local_err);
363 return;
364 }
365
366 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)
367 && !(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
368 error_setg(errp,
369 "KVM does not support 1TiB segments which guest expects");
370 return;
371 }
372
373 if (smmu_info.slb_size < cpu->hash64_opts->slb_size) {
374 error_setg(errp, "KVM only supports %u SLB entries, but guest needs %u",
375 smmu_info.slb_size, cpu->hash64_opts->slb_size);
376 return;
377 }
378
379 /*
380 * Verify that every pagesize supported by the cpu model is
381 * supported by KVM with the same encodings
382 */
383 for (iq = 0; iq < ARRAY_SIZE(cpu->hash64_opts->sps); iq++) {
384 PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq];
385 struct kvm_ppc_one_seg_page_size *ksps;
386
387 for (ik = 0; ik < ARRAY_SIZE(smmu_info.sps); ik++) {
388 if (qsps->page_shift == smmu_info.sps[ik].page_shift) {
389 break;
390 }
391 }
392 if (ik >= ARRAY_SIZE(smmu_info.sps)) {
393 error_setg(errp, "KVM doesn't support for base page shift %u",
394 qsps->page_shift);
395 return;
396 }
397
398 ksps = &smmu_info.sps[ik];
399 if (ksps->slb_enc != qsps->slb_enc) {
400 error_setg(errp,
401 "KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x",
402 ksps->slb_enc, ksps->page_shift, qsps->slb_enc);
403 return;
404 }
405
406 for (jq = 0; jq < ARRAY_SIZE(qsps->enc); jq++) {
407 for (jk = 0; jk < ARRAY_SIZE(ksps->enc); jk++) {
408 if (qsps->enc[jq].page_shift == ksps->enc[jk].page_shift) {
409 break;
410 }
411 }
412
413 if (jk >= ARRAY_SIZE(ksps->enc)) {
414 error_setg(errp, "KVM doesn't support page shift %u/%u",
415 qsps->enc[jq].page_shift, qsps->page_shift);
416 return;
417 }
418 if (qsps->enc[jq].pte_enc != ksps->enc[jk].pte_enc) {
419 error_setg(errp,
420 "KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x",
421 ksps->enc[jk].pte_enc, qsps->enc[jq].page_shift,
422 qsps->page_shift, qsps->enc[jq].pte_enc);
423 return;
424 }
425 }
426 }
427
428 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
429 /*
430 * Mostly what guest pagesizes we can use are related to the
431 * host pages used to map guest RAM, which is handled in the
432 * platform code. Cache-Inhibited largepages (64k) however are
433 * used for I/O, so if they're mapped to the host at all it
434 * will be a normal mapping, not a special hugepage one used
435 * for RAM.
436 */
437 if (qemu_real_host_page_size() < 0x10000) {
438 error_setg(errp,
439 "KVM can't supply 64kiB CI pages, which guest expects");
440 }
441 }
442 }
443 #endif /* !defined (TARGET_PPC64) */
444
kvm_arch_vcpu_id(CPUState * cpu)445 unsigned long kvm_arch_vcpu_id(CPUState *cpu)
446 {
447 return POWERPC_CPU(cpu)->vcpu_id;
448 }
449
450 /*
451 * e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports
452 * only 1 watchpoint, so array size of 4 is sufficient for now.
453 */
454 #define MAX_HW_BKPTS 4
455
456 static struct HWBreakpoint {
457 target_ulong addr;
458 int type;
459 } hw_debug_points[MAX_HW_BKPTS];
460
461 static CPUWatchpoint hw_watchpoint;
462
463 /* Default there is no breakpoint and watchpoint supported */
464 static int max_hw_breakpoint;
465 static int max_hw_watchpoint;
466 static int nb_hw_breakpoint;
467 static int nb_hw_watchpoint;
468
kvmppc_hw_debug_points_init(CPUPPCState * cenv)469 static void kvmppc_hw_debug_points_init(CPUPPCState *cenv)
470 {
471 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
472 max_hw_breakpoint = 2;
473 max_hw_watchpoint = 2;
474 }
475
476 if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) {
477 fprintf(stderr, "Error initializing h/w breakpoints\n");
478 return;
479 }
480 }
481
kvm_arch_init_vcpu(CPUState * cs)482 int kvm_arch_init_vcpu(CPUState *cs)
483 {
484 PowerPCCPU *cpu = POWERPC_CPU(cs);
485 CPUPPCState *cenv = &cpu->env;
486 int ret;
487
488 /* Synchronize sregs with kvm */
489 ret = kvm_arch_sync_sregs(cpu);
490 if (ret) {
491 if (ret == -EINVAL) {
492 error_report("Register sync failed... If you're using kvm-hv.ko,"
493 " only \"-cpu host\" is possible");
494 }
495 return ret;
496 }
497
498 switch (cenv->mmu_model) {
499 case POWERPC_MMU_BOOKE206:
500 /* This target supports access to KVM's guest TLB */
501 ret = kvm_booke206_tlb_init(cpu);
502 break;
503 case POWERPC_MMU_2_07:
504 if (!cap_htm && !kvmppc_is_pr(cs->kvm_state)) {
505 /*
506 * KVM-HV has transactional memory on POWER8 also without
507 * the KVM_CAP_PPC_HTM extension, so enable it here
508 * instead as long as it's available to userspace on the
509 * host.
510 */
511 if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) {
512 cap_htm = true;
513 }
514 }
515 break;
516 default:
517 break;
518 }
519
520 kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode);
521 kvmppc_hw_debug_points_init(cenv);
522
523 return ret;
524 }
525
kvm_arch_destroy_vcpu(CPUState * cs)526 int kvm_arch_destroy_vcpu(CPUState *cs)
527 {
528 return 0;
529 }
530
kvm_sw_tlb_put(PowerPCCPU * cpu)531 static void kvm_sw_tlb_put(PowerPCCPU *cpu)
532 {
533 CPUPPCState *env = &cpu->env;
534 CPUState *cs = CPU(cpu);
535 struct kvm_dirty_tlb dirty_tlb;
536 unsigned char *bitmap;
537 int ret;
538
539 if (!env->kvm_sw_tlb) {
540 return;
541 }
542
543 bitmap = g_malloc((env->nb_tlb + 7) / 8);
544 memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8);
545
546 dirty_tlb.bitmap = (uintptr_t)bitmap;
547 dirty_tlb.num_dirty = env->nb_tlb;
548
549 ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb);
550 if (ret) {
551 fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n",
552 __func__, strerror(-ret));
553 }
554
555 g_free(bitmap);
556 }
557
kvm_get_one_spr(CPUState * cs,uint64_t id,int spr)558 static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr)
559 {
560 CPUPPCState *env = cpu_env(cs);
561 /* Init 'val' to avoid "uninitialised value" Valgrind warnings */
562 union {
563 uint32_t u32;
564 uint64_t u64;
565 } val = { };
566 struct kvm_one_reg reg = {
567 .id = id,
568 .addr = (uintptr_t) &val,
569 };
570 int ret;
571
572 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
573 if (ret != 0) {
574 trace_kvm_failed_spr_get(spr, strerror(errno));
575 } else {
576 switch (id & KVM_REG_SIZE_MASK) {
577 case KVM_REG_SIZE_U32:
578 env->spr[spr] = val.u32;
579 break;
580
581 case KVM_REG_SIZE_U64:
582 env->spr[spr] = val.u64;
583 break;
584
585 default:
586 /* Don't handle this size yet */
587 abort();
588 }
589 }
590 }
591
kvm_put_one_spr(CPUState * cs,uint64_t id,int spr)592 static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr)
593 {
594 CPUPPCState *env = cpu_env(cs);
595 union {
596 uint32_t u32;
597 uint64_t u64;
598 } val;
599 struct kvm_one_reg reg = {
600 .id = id,
601 .addr = (uintptr_t) &val,
602 };
603 int ret;
604
605 switch (id & KVM_REG_SIZE_MASK) {
606 case KVM_REG_SIZE_U32:
607 val.u32 = env->spr[spr];
608 break;
609
610 case KVM_REG_SIZE_U64:
611 val.u64 = env->spr[spr];
612 break;
613
614 default:
615 /* Don't handle this size yet */
616 abort();
617 }
618
619 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
620 if (ret != 0) {
621 trace_kvm_failed_spr_set(spr, strerror(errno));
622 }
623 }
624
kvm_put_fp(CPUState * cs)625 static int kvm_put_fp(CPUState *cs)
626 {
627 CPUPPCState *env = cpu_env(cs);
628 struct kvm_one_reg reg;
629 int i;
630 int ret;
631
632 if (env->insns_flags & PPC_FLOAT) {
633 uint64_t fpscr = env->fpscr;
634 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
635
636 reg.id = KVM_REG_PPC_FPSCR;
637 reg.addr = (uintptr_t)&fpscr;
638 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
639 if (ret < 0) {
640 trace_kvm_failed_fpscr_set(strerror(errno));
641 return ret;
642 }
643
644 for (i = 0; i < 32; i++) {
645 uint64_t vsr[2];
646 uint64_t *fpr = cpu_fpr_ptr(env, i);
647 uint64_t *vsrl = cpu_vsrl_ptr(env, i);
648
649 #if HOST_BIG_ENDIAN
650 vsr[0] = float64_val(*fpr);
651 vsr[1] = *vsrl;
652 #else
653 vsr[0] = *vsrl;
654 vsr[1] = float64_val(*fpr);
655 #endif
656 reg.addr = (uintptr_t) &vsr;
657 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
658
659 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
660 if (ret < 0) {
661 trace_kvm_failed_fp_set(vsx ? "VSR" : "FPR", i,
662 strerror(errno));
663 return ret;
664 }
665 }
666 }
667
668 if (env->insns_flags & PPC_ALTIVEC) {
669 reg.id = KVM_REG_PPC_VSCR;
670 reg.addr = (uintptr_t)&env->vscr;
671 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
672 if (ret < 0) {
673 trace_kvm_failed_vscr_set(strerror(errno));
674 return ret;
675 }
676
677 for (i = 0; i < 32; i++) {
678 reg.id = KVM_REG_PPC_VR(i);
679 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
680 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
681 if (ret < 0) {
682 trace_kvm_failed_vr_set(i, strerror(errno));
683 return ret;
684 }
685 }
686 }
687
688 return 0;
689 }
690
kvm_get_fp(CPUState * cs)691 static int kvm_get_fp(CPUState *cs)
692 {
693 CPUPPCState *env = cpu_env(cs);
694 struct kvm_one_reg reg;
695 int i;
696 int ret;
697
698 if (env->insns_flags & PPC_FLOAT) {
699 uint64_t fpscr;
700 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
701
702 reg.id = KVM_REG_PPC_FPSCR;
703 reg.addr = (uintptr_t)&fpscr;
704 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
705 if (ret < 0) {
706 trace_kvm_failed_fpscr_get(strerror(errno));
707 return ret;
708 } else {
709 env->fpscr = fpscr;
710 }
711
712 for (i = 0; i < 32; i++) {
713 uint64_t vsr[2];
714 uint64_t *fpr = cpu_fpr_ptr(env, i);
715 uint64_t *vsrl = cpu_vsrl_ptr(env, i);
716
717 reg.addr = (uintptr_t) &vsr;
718 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
719
720 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
721 if (ret < 0) {
722 trace_kvm_failed_fp_get(vsx ? "VSR" : "FPR", i,
723 strerror(errno));
724 return ret;
725 } else {
726 #if HOST_BIG_ENDIAN
727 *fpr = vsr[0];
728 if (vsx) {
729 *vsrl = vsr[1];
730 }
731 #else
732 *fpr = vsr[1];
733 if (vsx) {
734 *vsrl = vsr[0];
735 }
736 #endif
737 }
738 }
739 }
740
741 if (env->insns_flags & PPC_ALTIVEC) {
742 reg.id = KVM_REG_PPC_VSCR;
743 reg.addr = (uintptr_t)&env->vscr;
744 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
745 if (ret < 0) {
746 trace_kvm_failed_vscr_get(strerror(errno));
747 return ret;
748 }
749
750 for (i = 0; i < 32; i++) {
751 reg.id = KVM_REG_PPC_VR(i);
752 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
753 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
754 if (ret < 0) {
755 trace_kvm_failed_vr_get(i, strerror(errno));
756 return ret;
757 }
758 }
759 }
760
761 return 0;
762 }
763
764 #if defined(TARGET_PPC64)
kvm_get_vpa(CPUState * cs)765 static int kvm_get_vpa(CPUState *cs)
766 {
767 PowerPCCPU *cpu = POWERPC_CPU(cs);
768 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
769 struct kvm_one_reg reg;
770 int ret;
771
772 reg.id = KVM_REG_PPC_VPA_ADDR;
773 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
774 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
775 if (ret < 0) {
776 trace_kvm_failed_vpa_addr_get(strerror(errno));
777 return ret;
778 }
779
780 assert((uintptr_t)&spapr_cpu->slb_shadow_size
781 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
782 reg.id = KVM_REG_PPC_VPA_SLB;
783 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
784 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
785 if (ret < 0) {
786 trace_kvm_failed_slb_get(strerror(errno));
787 return ret;
788 }
789
790 assert((uintptr_t)&spapr_cpu->dtl_size
791 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
792 reg.id = KVM_REG_PPC_VPA_DTL;
793 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
794 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
795 if (ret < 0) {
796 trace_kvm_failed_dtl_get(strerror(errno));
797 return ret;
798 }
799
800 return 0;
801 }
802
kvm_put_vpa(CPUState * cs)803 static int kvm_put_vpa(CPUState *cs)
804 {
805 PowerPCCPU *cpu = POWERPC_CPU(cs);
806 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
807 struct kvm_one_reg reg;
808 int ret;
809
810 /*
811 * SLB shadow or DTL can't be registered unless a master VPA is
812 * registered. That means when restoring state, if a VPA *is*
813 * registered, we need to set that up first. If not, we need to
814 * deregister the others before deregistering the master VPA
815 */
816 assert(spapr_cpu->vpa_addr
817 || !(spapr_cpu->slb_shadow_addr || spapr_cpu->dtl_addr));
818
819 if (spapr_cpu->vpa_addr) {
820 reg.id = KVM_REG_PPC_VPA_ADDR;
821 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
822 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
823 if (ret < 0) {
824 trace_kvm_failed_vpa_addr_set(strerror(errno));
825 return ret;
826 }
827 }
828
829 assert((uintptr_t)&spapr_cpu->slb_shadow_size
830 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
831 reg.id = KVM_REG_PPC_VPA_SLB;
832 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
833 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
834 if (ret < 0) {
835 trace_kvm_failed_slb_set(strerror(errno));
836 return ret;
837 }
838
839 assert((uintptr_t)&spapr_cpu->dtl_size
840 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
841 reg.id = KVM_REG_PPC_VPA_DTL;
842 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
843 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
844 if (ret < 0) {
845 trace_kvm_failed_dtl_set(strerror(errno));
846 return ret;
847 }
848
849 if (!spapr_cpu->vpa_addr) {
850 reg.id = KVM_REG_PPC_VPA_ADDR;
851 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
852 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
853 if (ret < 0) {
854 trace_kvm_failed_null_vpa_addr_set(strerror(errno));
855 return ret;
856 }
857 }
858
859 return 0;
860 }
861 #endif /* TARGET_PPC64 */
862
kvmppc_put_books_sregs(PowerPCCPU * cpu)863 int kvmppc_put_books_sregs(PowerPCCPU *cpu)
864 {
865 CPUPPCState *env = &cpu->env;
866 struct kvm_sregs sregs = { };
867 int i;
868
869 sregs.pvr = env->spr[SPR_PVR];
870
871 if (cpu->vhyp) {
872 sregs.u.s.sdr1 = cpu->vhyp_class->encode_hpt_for_kvm_pr(cpu->vhyp);
873 } else {
874 sregs.u.s.sdr1 = env->spr[SPR_SDR1];
875 }
876
877 /* Sync SLB */
878 #ifdef TARGET_PPC64
879 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
880 sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid;
881 if (env->slb[i].esid & SLB_ESID_V) {
882 sregs.u.s.ppc64.slb[i].slbe |= i;
883 }
884 sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid;
885 }
886 #endif
887
888 /* Sync SRs */
889 for (i = 0; i < 16; i++) {
890 sregs.u.s.ppc32.sr[i] = env->sr[i];
891 }
892
893 /* Sync BATs */
894 for (i = 0; i < 8; i++) {
895 /* Beware. We have to swap upper and lower bits here */
896 sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32)
897 | env->DBAT[1][i];
898 sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32)
899 | env->IBAT[1][i];
900 }
901
902 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
903 }
904
kvm_arch_put_registers(CPUState * cs,int level,Error ** errp)905 int kvm_arch_put_registers(CPUState *cs, int level, Error **errp)
906 {
907 PowerPCCPU *cpu = POWERPC_CPU(cs);
908 CPUPPCState *env = &cpu->env;
909 struct kvm_regs regs;
910 int ret;
911 int i;
912
913 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s);
914 if (ret < 0) {
915 return ret;
916 }
917
918 regs.ctr = env->ctr;
919 regs.lr = env->lr;
920 regs.xer = cpu_read_xer(env);
921 regs.msr = env->msr;
922 regs.pc = env->nip;
923
924 regs.srr0 = env->spr[SPR_SRR0];
925 regs.srr1 = env->spr[SPR_SRR1];
926
927 regs.sprg0 = env->spr[SPR_SPRG0];
928 regs.sprg1 = env->spr[SPR_SPRG1];
929 regs.sprg2 = env->spr[SPR_SPRG2];
930 regs.sprg3 = env->spr[SPR_SPRG3];
931 regs.sprg4 = env->spr[SPR_SPRG4];
932 regs.sprg5 = env->spr[SPR_SPRG5];
933 regs.sprg6 = env->spr[SPR_SPRG6];
934 regs.sprg7 = env->spr[SPR_SPRG7];
935
936 regs.pid = env->spr[SPR_BOOKE_PID];
937
938 for (i = 0; i < 32; i++) {
939 regs.gpr[i] = env->gpr[i];
940 }
941
942 regs.cr = ppc_get_cr(env);
943
944 ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s);
945 if (ret < 0) {
946 return ret;
947 }
948
949 kvm_put_fp(cs);
950
951 if (env->tlb_dirty) {
952 kvm_sw_tlb_put(cpu);
953 env->tlb_dirty = false;
954 }
955
956 if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) {
957 ret = kvmppc_put_books_sregs(cpu);
958 if (ret < 0) {
959 return ret;
960 }
961 }
962
963 if (cap_hior && (level >= KVM_PUT_RESET_STATE)) {
964 kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
965 }
966
967 if (cap_one_reg) {
968 /*
969 * We deliberately ignore errors here, for kernels which have
970 * the ONE_REG calls, but don't support the specific
971 * registers, there's a reasonable chance things will still
972 * work, at least until we try to migrate.
973 */
974 for (i = 0; i < 1024; i++) {
975 uint64_t id = env->spr_cb[i].one_reg_id;
976
977 if (id != 0) {
978 kvm_put_one_spr(cs, id, i);
979 }
980 }
981
982 #ifdef TARGET_PPC64
983 if (FIELD_EX64(env->msr, MSR, TS)) {
984 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
985 kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
986 }
987 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
988 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
989 }
990 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
991 kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
992 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
993 kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
994 kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
995 kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
996 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
997 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
998 kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
999 kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
1000 }
1001
1002 if (cap_papr) {
1003 if (kvm_put_vpa(cs) < 0) {
1004 trace_kvm_failed_put_vpa();
1005 }
1006 }
1007
1008 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
1009
1010 if (level > KVM_PUT_RUNTIME_STATE) {
1011 kvm_put_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES);
1012 }
1013 #endif /* TARGET_PPC64 */
1014 }
1015
1016 return ret;
1017 }
1018
kvm_sync_excp(CPUPPCState * env,int vector,int ivor)1019 static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor)
1020 {
1021 env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR];
1022 }
1023
kvmppc_get_booke_sregs(PowerPCCPU * cpu)1024 static int kvmppc_get_booke_sregs(PowerPCCPU *cpu)
1025 {
1026 CPUPPCState *env = &cpu->env;
1027 struct kvm_sregs sregs;
1028 int ret;
1029
1030 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1031 if (ret < 0) {
1032 return ret;
1033 }
1034
1035 if (sregs.u.e.features & KVM_SREGS_E_BASE) {
1036 env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0;
1037 env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1;
1038 env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr;
1039 env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear;
1040 env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr;
1041 env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr;
1042 env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr;
1043 env->spr[SPR_DECR] = sregs.u.e.dec;
1044 env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff;
1045 env->spr[SPR_TBU] = sregs.u.e.tb >> 32;
1046 env->spr[SPR_VRSAVE] = sregs.u.e.vrsave;
1047 }
1048
1049 if (sregs.u.e.features & KVM_SREGS_E_ARCH206) {
1050 env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir;
1051 env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0;
1052 env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1;
1053 env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar;
1054 env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr;
1055 }
1056
1057 if (sregs.u.e.features & KVM_SREGS_E_64) {
1058 env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr;
1059 }
1060
1061 if (sregs.u.e.features & KVM_SREGS_E_SPRG8) {
1062 env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8;
1063 }
1064
1065 if (sregs.u.e.features & KVM_SREGS_E_IVOR) {
1066 env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0];
1067 kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0);
1068 env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1];
1069 kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1);
1070 env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2];
1071 kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2);
1072 env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3];
1073 kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3);
1074 env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4];
1075 kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4);
1076 env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5];
1077 kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5);
1078 env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6];
1079 kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6);
1080 env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7];
1081 kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7);
1082 env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8];
1083 kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8);
1084 env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9];
1085 kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9);
1086 env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10];
1087 kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10);
1088 env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11];
1089 kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11);
1090 env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12];
1091 kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12);
1092 env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13];
1093 kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13);
1094 env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14];
1095 kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14);
1096 env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15];
1097 kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15);
1098
1099 if (sregs.u.e.features & KVM_SREGS_E_SPE) {
1100 env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0];
1101 kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32);
1102 env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1];
1103 kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33);
1104 env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2];
1105 kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34);
1106 }
1107
1108 if (sregs.u.e.features & KVM_SREGS_E_PM) {
1109 env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3];
1110 kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35);
1111 }
1112
1113 if (sregs.u.e.features & KVM_SREGS_E_PC) {
1114 env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4];
1115 kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36);
1116 env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5];
1117 kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37);
1118 }
1119 }
1120
1121 if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) {
1122 env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0;
1123 env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1;
1124 env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2;
1125 env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff;
1126 env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4;
1127 env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6;
1128 env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32;
1129 env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg;
1130 env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0];
1131 env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1];
1132 }
1133
1134 if (sregs.u.e.features & KVM_SREGS_EXP) {
1135 env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr;
1136 }
1137
1138 if (sregs.u.e.features & KVM_SREGS_E_PD) {
1139 env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc;
1140 env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc;
1141 }
1142
1143 if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {
1144 env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr;
1145 env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar;
1146 env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0;
1147
1148 if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {
1149 env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1;
1150 env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2;
1151 }
1152 }
1153
1154 return 0;
1155 }
1156
kvmppc_get_books_sregs(PowerPCCPU * cpu)1157 static int kvmppc_get_books_sregs(PowerPCCPU *cpu)
1158 {
1159 CPUPPCState *env = &cpu->env;
1160 struct kvm_sregs sregs;
1161 int ret;
1162 int i;
1163
1164 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1165 if (ret < 0) {
1166 return ret;
1167 }
1168
1169 if (!cpu->vhyp) {
1170 ppc_store_sdr1(env, sregs.u.s.sdr1);
1171 }
1172
1173 /* Sync SLB */
1174 #ifdef TARGET_PPC64
1175 /*
1176 * The packed SLB array we get from KVM_GET_SREGS only contains
1177 * information about valid entries. So we flush our internal copy
1178 * to get rid of stale ones, then put all valid SLB entries back
1179 * in.
1180 */
1181 memset(env->slb, 0, sizeof(env->slb));
1182 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
1183 target_ulong rb = sregs.u.s.ppc64.slb[i].slbe;
1184 target_ulong rs = sregs.u.s.ppc64.slb[i].slbv;
1185 /*
1186 * Only restore valid entries
1187 */
1188 if (rb & SLB_ESID_V) {
1189 ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs);
1190 }
1191 }
1192 #endif
1193
1194 /* Sync SRs */
1195 for (i = 0; i < 16; i++) {
1196 env->sr[i] = sregs.u.s.ppc32.sr[i];
1197 }
1198
1199 /* Sync BATs */
1200 for (i = 0; i < 8; i++) {
1201 env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;
1202 env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;
1203 env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;
1204 env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;
1205 }
1206
1207 return 0;
1208 }
1209
kvm_arch_get_registers(CPUState * cs,Error ** errp)1210 int kvm_arch_get_registers(CPUState *cs, Error **errp)
1211 {
1212 PowerPCCPU *cpu = POWERPC_CPU(cs);
1213 CPUPPCState *env = &cpu->env;
1214 struct kvm_regs regs;
1215 int i, ret;
1216
1217 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s);
1218 if (ret < 0) {
1219 return ret;
1220 }
1221
1222 ppc_set_cr(env, regs.cr);
1223 env->ctr = regs.ctr;
1224 env->lr = regs.lr;
1225 cpu_write_xer(env, regs.xer);
1226 env->msr = regs.msr;
1227 env->nip = regs.pc;
1228
1229 env->spr[SPR_SRR0] = regs.srr0;
1230 env->spr[SPR_SRR1] = regs.srr1;
1231
1232 env->spr[SPR_SPRG0] = regs.sprg0;
1233 env->spr[SPR_SPRG1] = regs.sprg1;
1234 env->spr[SPR_SPRG2] = regs.sprg2;
1235 env->spr[SPR_SPRG3] = regs.sprg3;
1236 env->spr[SPR_SPRG4] = regs.sprg4;
1237 env->spr[SPR_SPRG5] = regs.sprg5;
1238 env->spr[SPR_SPRG6] = regs.sprg6;
1239 env->spr[SPR_SPRG7] = regs.sprg7;
1240
1241 env->spr[SPR_BOOKE_PID] = regs.pid;
1242
1243 for (i = 0; i < 32; i++) {
1244 env->gpr[i] = regs.gpr[i];
1245 }
1246
1247 kvm_get_fp(cs);
1248
1249 if (cap_booke_sregs) {
1250 ret = kvmppc_get_booke_sregs(cpu);
1251 if (ret < 0) {
1252 return ret;
1253 }
1254 }
1255
1256 if (cap_segstate) {
1257 ret = kvmppc_get_books_sregs(cpu);
1258 if (ret < 0) {
1259 return ret;
1260 }
1261 }
1262
1263 if (cap_hior) {
1264 kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
1265 }
1266
1267 if (cap_one_reg) {
1268 /*
1269 * We deliberately ignore errors here, for kernels which have
1270 * the ONE_REG calls, but don't support the specific
1271 * registers, there's a reasonable chance things will still
1272 * work, at least until we try to migrate.
1273 */
1274 for (i = 0; i < 1024; i++) {
1275 uint64_t id = env->spr_cb[i].one_reg_id;
1276
1277 if (id != 0) {
1278 kvm_get_one_spr(cs, id, i);
1279 }
1280 }
1281
1282 #ifdef TARGET_PPC64
1283 if (FIELD_EX64(env->msr, MSR, TS)) {
1284 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
1285 kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
1286 }
1287 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
1288 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
1289 }
1290 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
1291 kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
1292 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
1293 kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
1294 kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
1295 kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
1296 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
1297 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
1298 kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
1299 kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
1300 }
1301
1302 if (cap_papr) {
1303 if (kvm_get_vpa(cs) < 0) {
1304 trace_kvm_failed_get_vpa();
1305 }
1306 }
1307
1308 kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
1309 kvm_get_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES);
1310 #endif
1311 }
1312
1313 return 0;
1314 }
1315
kvmppc_set_interrupt(PowerPCCPU * cpu,int irq,int level)1316 int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level)
1317 {
1318 unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
1319
1320 if (irq != PPC_INTERRUPT_EXT) {
1321 return 0;
1322 }
1323
1324 if (!cap_interrupt_unset) {
1325 return 0;
1326 }
1327
1328 kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
1329
1330 return 0;
1331 }
1332
kvm_arch_pre_run(CPUState * cs,struct kvm_run * run)1333 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
1334 {
1335 return;
1336 }
1337
kvm_arch_post_run(CPUState * cs,struct kvm_run * run)1338 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
1339 {
1340 return MEMTXATTRS_UNSPECIFIED;
1341 }
1342
kvm_arch_process_async_events(CPUState * cs)1343 int kvm_arch_process_async_events(CPUState *cs)
1344 {
1345 return cs->halted;
1346 }
1347
kvmppc_handle_halt(PowerPCCPU * cpu)1348 static int kvmppc_handle_halt(PowerPCCPU *cpu)
1349 {
1350 CPUState *cs = CPU(cpu);
1351 CPUPPCState *env = &cpu->env;
1352
1353 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) &&
1354 FIELD_EX64(env->msr, MSR, EE)) {
1355 cs->halted = 1;
1356 cs->exception_index = EXCP_HLT;
1357 }
1358
1359 return 0;
1360 }
1361
1362 /* map dcr access to existing qemu dcr emulation */
kvmppc_handle_dcr_read(CPUPPCState * env,uint32_t dcrn,uint32_t * data)1363 static int kvmppc_handle_dcr_read(CPUPPCState *env,
1364 uint32_t dcrn, uint32_t *data)
1365 {
1366 if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) {
1367 fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
1368 }
1369
1370 return 0;
1371 }
1372
kvmppc_handle_dcr_write(CPUPPCState * env,uint32_t dcrn,uint32_t data)1373 static int kvmppc_handle_dcr_write(CPUPPCState *env,
1374 uint32_t dcrn, uint32_t data)
1375 {
1376 if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) {
1377 fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
1378 }
1379
1380 return 0;
1381 }
1382
kvm_arch_insert_sw_breakpoint(CPUState * cs,struct kvm_sw_breakpoint * bp)1383 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1384 {
1385 /* Mixed endian case is not handled */
1386 uint32_t sc = debug_inst_opcode;
1387
1388 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1389 sizeof(sc), 0) ||
1390 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) {
1391 return -EINVAL;
1392 }
1393
1394 return 0;
1395 }
1396
kvm_arch_remove_sw_breakpoint(CPUState * cs,struct kvm_sw_breakpoint * bp)1397 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1398 {
1399 uint32_t sc;
1400
1401 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) ||
1402 sc != debug_inst_opcode ||
1403 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1404 sizeof(sc), 1)) {
1405 return -EINVAL;
1406 }
1407
1408 return 0;
1409 }
1410
find_hw_breakpoint(target_ulong addr,int type)1411 static int find_hw_breakpoint(target_ulong addr, int type)
1412 {
1413 int n;
1414
1415 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1416 <= ARRAY_SIZE(hw_debug_points));
1417
1418 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1419 if (hw_debug_points[n].addr == addr &&
1420 hw_debug_points[n].type == type) {
1421 return n;
1422 }
1423 }
1424
1425 return -1;
1426 }
1427
find_hw_watchpoint(target_ulong addr,int * flag)1428 static int find_hw_watchpoint(target_ulong addr, int *flag)
1429 {
1430 int n;
1431
1432 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS);
1433 if (n >= 0) {
1434 *flag = BP_MEM_ACCESS;
1435 return n;
1436 }
1437
1438 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE);
1439 if (n >= 0) {
1440 *flag = BP_MEM_WRITE;
1441 return n;
1442 }
1443
1444 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ);
1445 if (n >= 0) {
1446 *flag = BP_MEM_READ;
1447 return n;
1448 }
1449
1450 return -1;
1451 }
1452
kvm_arch_insert_hw_breakpoint(vaddr addr,vaddr len,int type)1453 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type)
1454 {
1455 const unsigned breakpoint_index = nb_hw_breakpoint + nb_hw_watchpoint;
1456 if (breakpoint_index >= ARRAY_SIZE(hw_debug_points)) {
1457 return -ENOBUFS;
1458 }
1459
1460 hw_debug_points[breakpoint_index].addr = addr;
1461 hw_debug_points[breakpoint_index].type = type;
1462
1463 switch (type) {
1464 case GDB_BREAKPOINT_HW:
1465 if (nb_hw_breakpoint >= max_hw_breakpoint) {
1466 return -ENOBUFS;
1467 }
1468
1469 if (find_hw_breakpoint(addr, type) >= 0) {
1470 return -EEXIST;
1471 }
1472
1473 nb_hw_breakpoint++;
1474 break;
1475
1476 case GDB_WATCHPOINT_WRITE:
1477 case GDB_WATCHPOINT_READ:
1478 case GDB_WATCHPOINT_ACCESS:
1479 if (nb_hw_watchpoint >= max_hw_watchpoint) {
1480 return -ENOBUFS;
1481 }
1482
1483 if (find_hw_breakpoint(addr, type) >= 0) {
1484 return -EEXIST;
1485 }
1486
1487 nb_hw_watchpoint++;
1488 break;
1489
1490 default:
1491 return -ENOSYS;
1492 }
1493
1494 return 0;
1495 }
1496
kvm_arch_remove_hw_breakpoint(vaddr addr,vaddr len,int type)1497 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type)
1498 {
1499 int n;
1500
1501 n = find_hw_breakpoint(addr, type);
1502 if (n < 0) {
1503 return -ENOENT;
1504 }
1505
1506 switch (type) {
1507 case GDB_BREAKPOINT_HW:
1508 nb_hw_breakpoint--;
1509 break;
1510
1511 case GDB_WATCHPOINT_WRITE:
1512 case GDB_WATCHPOINT_READ:
1513 case GDB_WATCHPOINT_ACCESS:
1514 nb_hw_watchpoint--;
1515 break;
1516
1517 default:
1518 return -ENOSYS;
1519 }
1520 hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint];
1521
1522 return 0;
1523 }
1524
kvm_arch_remove_all_hw_breakpoints(void)1525 void kvm_arch_remove_all_hw_breakpoints(void)
1526 {
1527 nb_hw_breakpoint = nb_hw_watchpoint = 0;
1528 }
1529
kvm_arch_update_guest_debug(CPUState * cs,struct kvm_guest_debug * dbg)1530 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
1531 {
1532 int n;
1533
1534 /* Software Breakpoint updates */
1535 if (kvm_sw_breakpoints_active(cs)) {
1536 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1537 }
1538
1539 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1540 <= ARRAY_SIZE(hw_debug_points));
1541 assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp));
1542
1543 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1544 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1545 memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp));
1546 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1547 switch (hw_debug_points[n].type) {
1548 case GDB_BREAKPOINT_HW:
1549 dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT;
1550 break;
1551 case GDB_WATCHPOINT_WRITE:
1552 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE;
1553 break;
1554 case GDB_WATCHPOINT_READ:
1555 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ;
1556 break;
1557 case GDB_WATCHPOINT_ACCESS:
1558 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE |
1559 KVMPPC_DEBUG_WATCH_READ;
1560 break;
1561 default:
1562 cpu_abort(cs, "Unsupported breakpoint type\n");
1563 }
1564 dbg->arch.bp[n].addr = hw_debug_points[n].addr;
1565 }
1566 }
1567 }
1568
kvm_handle_hw_breakpoint(CPUState * cs,struct kvm_debug_exit_arch * arch_info)1569 static int kvm_handle_hw_breakpoint(CPUState *cs,
1570 struct kvm_debug_exit_arch *arch_info)
1571 {
1572 int handle = DEBUG_RETURN_GUEST;
1573 int n;
1574 int flag = 0;
1575
1576 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1577 if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) {
1578 n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW);
1579 if (n >= 0) {
1580 handle = DEBUG_RETURN_GDB;
1581 }
1582 } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ |
1583 KVMPPC_DEBUG_WATCH_WRITE)) {
1584 n = find_hw_watchpoint(arch_info->address, &flag);
1585 if (n >= 0) {
1586 handle = DEBUG_RETURN_GDB;
1587 cs->watchpoint_hit = &hw_watchpoint;
1588 hw_watchpoint.vaddr = hw_debug_points[n].addr;
1589 hw_watchpoint.flags = flag;
1590 }
1591 }
1592 }
1593 return handle;
1594 }
1595
kvm_handle_singlestep(void)1596 static int kvm_handle_singlestep(void)
1597 {
1598 return DEBUG_RETURN_GDB;
1599 }
1600
kvm_handle_sw_breakpoint(void)1601 static int kvm_handle_sw_breakpoint(void)
1602 {
1603 return DEBUG_RETURN_GDB;
1604 }
1605
kvm_handle_debug(PowerPCCPU * cpu,struct kvm_run * run)1606 static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run)
1607 {
1608 CPUState *cs = CPU(cpu);
1609 CPUPPCState *env = &cpu->env;
1610 struct kvm_debug_exit_arch *arch_info = &run->debug.arch;
1611
1612 if (cs->singlestep_enabled) {
1613 return kvm_handle_singlestep();
1614 }
1615
1616 if (arch_info->status) {
1617 return kvm_handle_hw_breakpoint(cs, arch_info);
1618 }
1619
1620 if (kvm_find_sw_breakpoint(cs, arch_info->address)) {
1621 return kvm_handle_sw_breakpoint();
1622 }
1623
1624 /*
1625 * QEMU is not able to handle debug exception, so inject
1626 * program exception to guest;
1627 * Yes program exception NOT debug exception !!
1628 * When QEMU is using debug resources then debug exception must
1629 * be always set. To achieve this we set MSR_DE and also set
1630 * MSRP_DEP so guest cannot change MSR_DE.
1631 * When emulating debug resource for guest we want guest
1632 * to control MSR_DE (enable/disable debug interrupt on need).
1633 * Supporting both configurations are NOT possible.
1634 * So the result is that we cannot share debug resources
1635 * between QEMU and Guest on BOOKE architecture.
1636 * In the current design QEMU gets the priority over guest,
1637 * this means that if QEMU is using debug resources then guest
1638 * cannot use them;
1639 * For software breakpoint QEMU uses a privileged instruction;
1640 * So there cannot be any reason that we are here for guest
1641 * set debug exception, only possibility is guest executed a
1642 * privileged / illegal instruction and that's why we are
1643 * injecting a program interrupt.
1644 */
1645 cpu_synchronize_state(cs);
1646 /*
1647 * env->nip is PC, so increment this by 4 to use
1648 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4.
1649 */
1650 env->nip += 4;
1651 cs->exception_index = POWERPC_EXCP_PROGRAM;
1652 env->error_code = POWERPC_EXCP_INVAL;
1653 ppc_cpu_do_interrupt(cs);
1654
1655 return DEBUG_RETURN_GUEST;
1656 }
1657
kvm_arch_handle_exit(CPUState * cs,struct kvm_run * run)1658 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
1659 {
1660 PowerPCCPU *cpu = POWERPC_CPU(cs);
1661 CPUPPCState *env = &cpu->env;
1662 int ret;
1663
1664 bql_lock();
1665
1666 switch (run->exit_reason) {
1667 case KVM_EXIT_DCR:
1668 if (run->dcr.is_write) {
1669 trace_kvm_handle_dcr_write();
1670 ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data);
1671 } else {
1672 trace_kvm_handle_dcr_read();
1673 ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data);
1674 }
1675 break;
1676 case KVM_EXIT_HLT:
1677 trace_kvm_handle_halt();
1678 ret = kvmppc_handle_halt(cpu);
1679 break;
1680 #if defined(CONFIG_PSERIES)
1681 case KVM_EXIT_PAPR_HCALL:
1682 trace_kvm_handle_papr_hcall(run->papr_hcall.nr);
1683 run->papr_hcall.ret = spapr_hypercall(cpu,
1684 run->papr_hcall.nr,
1685 run->papr_hcall.args);
1686 ret = 0;
1687 break;
1688 #endif
1689 case KVM_EXIT_EPR:
1690 trace_kvm_handle_epr();
1691 run->epr.epr = ldl_phys(cs->as, env->mpic_iack);
1692 ret = 0;
1693 break;
1694 case KVM_EXIT_WATCHDOG:
1695 trace_kvm_handle_watchdog_expiry();
1696 watchdog_perform_action();
1697 ret = 0;
1698 break;
1699
1700 case KVM_EXIT_DEBUG:
1701 trace_kvm_handle_debug_exception();
1702 if (kvm_handle_debug(cpu, run)) {
1703 ret = EXCP_DEBUG;
1704 break;
1705 }
1706 /* re-enter, this exception was guest-internal */
1707 ret = 0;
1708 break;
1709
1710 #if defined(CONFIG_PSERIES)
1711 case KVM_EXIT_NMI:
1712 trace_kvm_handle_nmi_exception();
1713 ret = kvm_handle_nmi(cpu, run);
1714 break;
1715 #endif
1716
1717 default:
1718 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1719 ret = -1;
1720 break;
1721 }
1722
1723 bql_unlock();
1724 return ret;
1725 }
1726
kvmppc_or_tsr_bits(PowerPCCPU * cpu,uint32_t tsr_bits)1727 int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1728 {
1729 CPUState *cs = CPU(cpu);
1730 uint32_t bits = tsr_bits;
1731 struct kvm_one_reg reg = {
1732 .id = KVM_REG_PPC_OR_TSR,
1733 .addr = (uintptr_t) &bits,
1734 };
1735
1736 if (!kvm_enabled()) {
1737 return 0;
1738 }
1739
1740 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
1741 }
1742
kvmppc_clear_tsr_bits(PowerPCCPU * cpu,uint32_t tsr_bits)1743 int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1744 {
1745
1746 CPUState *cs = CPU(cpu);
1747 uint32_t bits = tsr_bits;
1748 struct kvm_one_reg reg = {
1749 .id = KVM_REG_PPC_CLEAR_TSR,
1750 .addr = (uintptr_t) &bits,
1751 };
1752
1753 if (!kvm_enabled()) {
1754 return 0;
1755 }
1756
1757 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
1758 }
1759
kvmppc_set_tcr(PowerPCCPU * cpu)1760 int kvmppc_set_tcr(PowerPCCPU *cpu)
1761 {
1762 CPUState *cs = CPU(cpu);
1763 CPUPPCState *env = &cpu->env;
1764 uint32_t tcr = env->spr[SPR_BOOKE_TCR];
1765
1766 struct kvm_one_reg reg = {
1767 .id = KVM_REG_PPC_TCR,
1768 .addr = (uintptr_t) &tcr,
1769 };
1770
1771 if (!kvm_enabled()) {
1772 return 0;
1773 }
1774
1775 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
1776 }
1777
kvmppc_booke_watchdog_enable(PowerPCCPU * cpu)1778 int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu)
1779 {
1780 CPUState *cs = CPU(cpu);
1781 int ret;
1782
1783 if (!kvm_enabled()) {
1784 return -1;
1785 }
1786
1787 if (!cap_ppc_watchdog) {
1788 printf("warning: KVM does not support watchdog");
1789 return -1;
1790 }
1791
1792 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0);
1793 if (ret < 0) {
1794 fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n",
1795 __func__, strerror(-ret));
1796 return ret;
1797 }
1798
1799 return ret;
1800 }
1801
read_cpuinfo(const char * field,char * value,int len)1802 static int read_cpuinfo(const char *field, char *value, int len)
1803 {
1804 FILE *f;
1805 int ret = -1;
1806 int field_len = strlen(field);
1807 char line[512];
1808
1809 f = fopen("/proc/cpuinfo", "r");
1810 if (!f) {
1811 return -1;
1812 }
1813
1814 do {
1815 if (!fgets(line, sizeof(line), f)) {
1816 break;
1817 }
1818 if (!strncmp(line, field, field_len)) {
1819 pstrcpy(value, len, line);
1820 ret = 0;
1821 break;
1822 }
1823 } while (*line);
1824
1825 fclose(f);
1826
1827 return ret;
1828 }
1829
kvmppc_get_tbfreq_procfs(void)1830 static uint32_t kvmppc_get_tbfreq_procfs(void)
1831 {
1832 char line[512];
1833 char *ns;
1834 uint32_t tbfreq_fallback = NANOSECONDS_PER_SECOND;
1835 uint32_t tbfreq_procfs;
1836
1837 if (read_cpuinfo("timebase", line, sizeof(line))) {
1838 return tbfreq_fallback;
1839 }
1840
1841 ns = strchr(line, ':');
1842 if (!ns) {
1843 return tbfreq_fallback;
1844 }
1845
1846 tbfreq_procfs = atoi(++ns);
1847
1848 /* 0 is certainly not acceptable by the guest, return fallback value */
1849 return tbfreq_procfs ? tbfreq_procfs : tbfreq_fallback;
1850 }
1851
kvmppc_get_tbfreq(void)1852 uint32_t kvmppc_get_tbfreq(void)
1853 {
1854 static uint32_t cached_tbfreq;
1855
1856 if (!cached_tbfreq) {
1857 cached_tbfreq = kvmppc_get_tbfreq_procfs();
1858 }
1859
1860 return cached_tbfreq;
1861 }
1862
kvmppc_get_host_serial(char ** value)1863 bool kvmppc_get_host_serial(char **value)
1864 {
1865 return g_file_get_contents("/proc/device-tree/system-id", value, NULL,
1866 NULL);
1867 }
1868
kvmppc_get_host_model(char ** value)1869 bool kvmppc_get_host_model(char **value)
1870 {
1871 return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL);
1872 }
1873
1874 /* Try to find a device tree node for a CPU with clock-frequency property */
kvmppc_find_cpu_dt(char * buf,int buf_len)1875 static int kvmppc_find_cpu_dt(char *buf, int buf_len)
1876 {
1877 struct dirent *dirp;
1878 DIR *dp;
1879
1880 dp = opendir(PROC_DEVTREE_CPU);
1881 if (!dp) {
1882 printf("Can't open directory " PROC_DEVTREE_CPU "\n");
1883 return -1;
1884 }
1885
1886 buf[0] = '\0';
1887 while ((dirp = readdir(dp)) != NULL) {
1888 FILE *f;
1889
1890 /* Don't accidentally read from the current and parent directories */
1891 if (strcmp(dirp->d_name, ".") == 0 || strcmp(dirp->d_name, "..") == 0) {
1892 continue;
1893 }
1894
1895 snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU,
1896 dirp->d_name);
1897 f = fopen(buf, "r");
1898 if (f) {
1899 snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name);
1900 fclose(f);
1901 break;
1902 }
1903 buf[0] = '\0';
1904 }
1905 closedir(dp);
1906 if (buf[0] == '\0') {
1907 printf("Unknown host!\n");
1908 return -1;
1909 }
1910
1911 return 0;
1912 }
1913
kvmppc_read_int_dt(const char * filename)1914 static uint64_t kvmppc_read_int_dt(const char *filename)
1915 {
1916 union {
1917 uint32_t v32;
1918 uint64_t v64;
1919 } u;
1920 FILE *f;
1921 int len;
1922
1923 f = fopen(filename, "rb");
1924 if (!f) {
1925 return -1;
1926 }
1927
1928 len = fread(&u, 1, sizeof(u), f);
1929 fclose(f);
1930 switch (len) {
1931 case 4:
1932 /* property is a 32-bit quantity */
1933 return be32_to_cpu(u.v32);
1934 case 8:
1935 return be64_to_cpu(u.v64);
1936 }
1937
1938 return 0;
1939 }
1940
1941 /*
1942 * Read a CPU node property from the host device tree that's a single
1943 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong
1944 * (can't find or open the property, or doesn't understand the format)
1945 */
kvmppc_read_int_cpu_dt(const char * propname)1946 static uint64_t kvmppc_read_int_cpu_dt(const char *propname)
1947 {
1948 char buf[PATH_MAX], *tmp;
1949 uint64_t val;
1950
1951 if (kvmppc_find_cpu_dt(buf, sizeof(buf))) {
1952 return -1;
1953 }
1954
1955 tmp = g_strdup_printf("%s/%s", buf, propname);
1956 val = kvmppc_read_int_dt(tmp);
1957 g_free(tmp);
1958
1959 return val;
1960 }
1961
kvmppc_get_clockfreq(void)1962 uint64_t kvmppc_get_clockfreq(void)
1963 {
1964 return kvmppc_read_int_cpu_dt("clock-frequency");
1965 }
1966
kvmppc_get_dec_bits(void)1967 static int kvmppc_get_dec_bits(void)
1968 {
1969 int nr_bits = kvmppc_read_int_cpu_dt("ibm,dec-bits");
1970
1971 if (nr_bits > 0) {
1972 return nr_bits;
1973 }
1974 return 0;
1975 }
1976
kvmppc_get_pvinfo(CPUPPCState * env,struct kvm_ppc_pvinfo * pvinfo)1977 static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo)
1978 {
1979 CPUState *cs = env_cpu(env);
1980
1981 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
1982 !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) {
1983 return 0;
1984 }
1985
1986 return 1;
1987 }
1988
kvmppc_get_hasidle(CPUPPCState * env)1989 int kvmppc_get_hasidle(CPUPPCState *env)
1990 {
1991 struct kvm_ppc_pvinfo pvinfo;
1992
1993 if (!kvmppc_get_pvinfo(env, &pvinfo) &&
1994 (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) {
1995 return 1;
1996 }
1997
1998 return 0;
1999 }
2000
kvmppc_get_hypercall(CPUPPCState * env,uint8_t * buf,int buf_len)2001 int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len)
2002 {
2003 uint32_t *hc = (uint32_t *)buf;
2004 struct kvm_ppc_pvinfo pvinfo;
2005
2006 if (!kvmppc_get_pvinfo(env, &pvinfo)) {
2007 memcpy(buf, pvinfo.hcall, buf_len);
2008 return 0;
2009 }
2010
2011 /*
2012 * Fallback to always fail hypercalls regardless of endianness:
2013 *
2014 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian)
2015 * li r3, -1
2016 * b .+8 (becomes nop in wrong endian)
2017 * bswap32(li r3, -1)
2018 */
2019
2020 hc[0] = cpu_to_be32(0x08000048);
2021 hc[1] = cpu_to_be32(0x3860ffff);
2022 hc[2] = cpu_to_be32(0x48000008);
2023 hc[3] = cpu_to_be32(bswap32(0x3860ffff));
2024
2025 return 1;
2026 }
2027
kvmppc_enable_hcall(KVMState * s,target_ulong hcall)2028 static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall)
2029 {
2030 return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1);
2031 }
2032
kvmppc_enable_logical_ci_hcalls(void)2033 void kvmppc_enable_logical_ci_hcalls(void)
2034 {
2035 /*
2036 * FIXME: it would be nice if we could detect the cases where
2037 * we're using a device which requires the in kernel
2038 * implementation of these hcalls, but the kernel lacks them and
2039 * produce a warning.
2040 */
2041 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD);
2042 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE);
2043 }
2044
kvmppc_enable_set_mode_hcall(void)2045 void kvmppc_enable_set_mode_hcall(void)
2046 {
2047 kvmppc_enable_hcall(kvm_state, H_SET_MODE);
2048 }
2049
kvmppc_enable_clear_ref_mod_hcalls(void)2050 void kvmppc_enable_clear_ref_mod_hcalls(void)
2051 {
2052 kvmppc_enable_hcall(kvm_state, H_CLEAR_REF);
2053 kvmppc_enable_hcall(kvm_state, H_CLEAR_MOD);
2054 }
2055
kvmppc_enable_h_page_init(void)2056 void kvmppc_enable_h_page_init(void)
2057 {
2058 kvmppc_enable_hcall(kvm_state, H_PAGE_INIT);
2059 }
2060
kvmppc_enable_h_rpt_invalidate(void)2061 void kvmppc_enable_h_rpt_invalidate(void)
2062 {
2063 kvmppc_enable_hcall(kvm_state, H_RPT_INVALIDATE);
2064 }
2065
2066 #ifdef CONFIG_PSERIES
kvmppc_set_papr(PowerPCCPU * cpu)2067 void kvmppc_set_papr(PowerPCCPU *cpu)
2068 {
2069 CPUState *cs = CPU(cpu);
2070 int ret;
2071
2072 if (!kvm_enabled()) {
2073 return;
2074 }
2075
2076 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0);
2077 if (ret) {
2078 error_report("This vCPU type or KVM version does not support PAPR");
2079 exit(1);
2080 }
2081
2082 /*
2083 * Update the capability flag so we sync the right information
2084 * with kvm
2085 */
2086 cap_papr = 1;
2087 }
2088 #endif
2089
kvmppc_set_compat(PowerPCCPU * cpu,uint32_t compat_pvr)2090 int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr)
2091 {
2092 return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr);
2093 }
2094
kvmppc_set_mpic_proxy(PowerPCCPU * cpu,int mpic_proxy)2095 void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy)
2096 {
2097 CPUState *cs = CPU(cpu);
2098 int ret;
2099
2100 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy);
2101 if (ret && mpic_proxy) {
2102 error_report("This KVM version does not support EPR");
2103 exit(1);
2104 }
2105 }
2106
kvmppc_get_fwnmi(void)2107 bool kvmppc_get_fwnmi(void)
2108 {
2109 return cap_fwnmi;
2110 }
2111
kvmppc_set_fwnmi(PowerPCCPU * cpu)2112 int kvmppc_set_fwnmi(PowerPCCPU *cpu)
2113 {
2114 CPUState *cs = CPU(cpu);
2115
2116 return kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_FWNMI, 0);
2117 }
2118
kvmppc_has_cap_dawr1(void)2119 bool kvmppc_has_cap_dawr1(void)
2120 {
2121 return !!cap_dawr1;
2122 }
2123
kvmppc_set_cap_dawr1(int enable)2124 int kvmppc_set_cap_dawr1(int enable)
2125 {
2126 return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_DAWR1, 0, enable);
2127 }
2128
kvmppc_smt_threads(void)2129 int kvmppc_smt_threads(void)
2130 {
2131 return cap_ppc_smt ? cap_ppc_smt : 1;
2132 }
2133
kvmppc_set_smt_threads(int smt)2134 int kvmppc_set_smt_threads(int smt)
2135 {
2136 int ret;
2137
2138 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0);
2139 if (!ret) {
2140 cap_ppc_smt = smt;
2141 }
2142 return ret;
2143 }
2144
kvmppc_error_append_smt_possible_hint(Error * const * errp)2145 void kvmppc_error_append_smt_possible_hint(Error *const *errp)
2146 {
2147 int i;
2148 GString *g;
2149 char *s;
2150
2151 assert(kvm_enabled());
2152 if (cap_ppc_smt_possible) {
2153 g = g_string_new("Available VSMT modes:");
2154 for (i = 63; i >= 0; i--) {
2155 if ((1UL << i) & cap_ppc_smt_possible) {
2156 g_string_append_printf(g, " %lu", (1UL << i));
2157 }
2158 }
2159 s = g_string_free(g, false);
2160 error_append_hint(errp, "%s.\n", s);
2161 g_free(s);
2162 } else {
2163 error_append_hint(errp,
2164 "This KVM seems to be too old to support VSMT.\n");
2165 }
2166 }
2167
2168
2169 #ifdef TARGET_PPC64
kvmppc_vrma_limit(unsigned int hash_shift)2170 uint64_t kvmppc_vrma_limit(unsigned int hash_shift)
2171 {
2172 struct kvm_ppc_smmu_info info;
2173 long rampagesize, best_page_shift;
2174 int i;
2175
2176 /*
2177 * Find the largest hardware supported page size that's less than
2178 * or equal to the (logical) backing page size of guest RAM
2179 */
2180 kvm_get_smmu_info(&info, &error_fatal);
2181 rampagesize = qemu_minrampagesize();
2182 best_page_shift = 0;
2183
2184 for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) {
2185 struct kvm_ppc_one_seg_page_size *sps = &info.sps[i];
2186
2187 if (!sps->page_shift) {
2188 continue;
2189 }
2190
2191 if ((sps->page_shift > best_page_shift)
2192 && ((1UL << sps->page_shift) <= rampagesize)) {
2193 best_page_shift = sps->page_shift;
2194 }
2195 }
2196
2197 return 1ULL << (best_page_shift + hash_shift - 7);
2198 }
2199 #endif
2200
kvmppc_spapr_use_multitce(void)2201 bool kvmppc_spapr_use_multitce(void)
2202 {
2203 return cap_spapr_multitce;
2204 }
2205
kvmppc_spapr_enable_inkernel_multitce(void)2206 int kvmppc_spapr_enable_inkernel_multitce(void)
2207 {
2208 int ret;
2209
2210 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2211 H_PUT_TCE_INDIRECT, 1);
2212 if (!ret) {
2213 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2214 H_STUFF_TCE, 1);
2215 }
2216
2217 return ret;
2218 }
2219
kvmppc_create_spapr_tce(uint32_t liobn,uint32_t page_shift,uint64_t bus_offset,uint32_t nb_table,int * pfd,bool need_vfio)2220 void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift,
2221 uint64_t bus_offset, uint32_t nb_table,
2222 int *pfd, bool need_vfio)
2223 {
2224 long len;
2225 int fd;
2226 void *table;
2227
2228 /*
2229 * Must set fd to -1 so we don't try to munmap when called for
2230 * destroying the table, which the upper layers -will- do
2231 */
2232 *pfd = -1;
2233 if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) {
2234 return NULL;
2235 }
2236
2237 if (cap_spapr_tce_64) {
2238 struct kvm_create_spapr_tce_64 args = {
2239 .liobn = liobn,
2240 .page_shift = page_shift,
2241 .offset = bus_offset >> page_shift,
2242 .size = nb_table,
2243 .flags = 0
2244 };
2245 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE_64, &args);
2246 if (fd < 0) {
2247 fprintf(stderr,
2248 "KVM: Failed to create TCE64 table for liobn 0x%x\n",
2249 liobn);
2250 return NULL;
2251 }
2252 } else if (cap_spapr_tce) {
2253 uint64_t window_size = (uint64_t) nb_table << page_shift;
2254 struct kvm_create_spapr_tce args = {
2255 .liobn = liobn,
2256 .window_size = window_size,
2257 };
2258 if ((window_size != args.window_size) || bus_offset) {
2259 return NULL;
2260 }
2261 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args);
2262 if (fd < 0) {
2263 fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n",
2264 liobn);
2265 return NULL;
2266 }
2267 } else {
2268 return NULL;
2269 }
2270
2271 len = nb_table * sizeof(uint64_t);
2272 /* FIXME: round this up to page size */
2273
2274 table = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
2275 if (table == MAP_FAILED) {
2276 fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n",
2277 liobn);
2278 close(fd);
2279 return NULL;
2280 }
2281
2282 *pfd = fd;
2283 return table;
2284 }
2285
kvmppc_remove_spapr_tce(void * table,int fd,uint32_t nb_table)2286 int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table)
2287 {
2288 long len;
2289
2290 if (fd < 0) {
2291 return -1;
2292 }
2293
2294 len = nb_table * sizeof(uint64_t);
2295 if ((munmap(table, len) < 0) ||
2296 (close(fd) < 0)) {
2297 fprintf(stderr, "KVM: Unexpected error removing TCE table: %s",
2298 strerror(errno));
2299 /* Leak the table */
2300 }
2301
2302 return 0;
2303 }
2304
kvmppc_reset_htab(int shift_hint)2305 int kvmppc_reset_htab(int shift_hint)
2306 {
2307 uint32_t shift = shift_hint;
2308
2309 if (!kvm_enabled()) {
2310 /* Full emulation, tell caller to allocate htab itself */
2311 return 0;
2312 }
2313 if (kvm_vm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) {
2314 int ret;
2315 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift);
2316 if (ret == -ENOTTY) {
2317 /*
2318 * At least some versions of PR KVM advertise the
2319 * capability, but don't implement the ioctl(). Oops.
2320 * Return 0 so that we allocate the htab in qemu, as is
2321 * correct for PR.
2322 */
2323 return 0;
2324 } else if (ret < 0) {
2325 return ret;
2326 }
2327 return shift;
2328 }
2329
2330 /*
2331 * We have a kernel that predates the htab reset calls. For PR
2332 * KVM, we need to allocate the htab ourselves, for an HV KVM of
2333 * this era, it has allocated a 16MB fixed size hash table
2334 * already.
2335 */
2336 if (kvmppc_is_pr(kvm_state)) {
2337 /* PR - tell caller to allocate htab */
2338 return 0;
2339 } else {
2340 /* HV - assume 16MB kernel allocated htab */
2341 return 24;
2342 }
2343 }
2344
mfpvr(void)2345 static inline uint32_t mfpvr(void)
2346 {
2347 uint32_t pvr;
2348
2349 asm ("mfpvr %0"
2350 : "=r"(pvr));
2351 return pvr;
2352 }
2353
alter_insns(uint64_t * word,uint64_t flags,bool on)2354 static void alter_insns(uint64_t *word, uint64_t flags, bool on)
2355 {
2356 if (on) {
2357 *word |= flags;
2358 } else {
2359 *word &= ~flags;
2360 }
2361 }
2362
kvmppc_cpu_realize(CPUState * cs,Error ** errp)2363 static bool kvmppc_cpu_realize(CPUState *cs, Error **errp)
2364 {
2365 int ret;
2366 const char *vcpu_str = (cs->parent_obj.hotplugged == true) ?
2367 "hotplug" : "create";
2368 cs->cpu_index = cpu_get_free_index();
2369
2370 POWERPC_CPU(cs)->vcpu_id = cs->cpu_index;
2371
2372 /* create and park to fail gracefully in case vcpu hotplug fails */
2373 ret = kvm_create_and_park_vcpu(cs);
2374 if (ret) {
2375 /*
2376 * This causes QEMU to terminate if initial CPU creation
2377 * fails, and only CPU hotplug failure if the error happens
2378 * there.
2379 */
2380 error_setg(errp, "%s: vcpu %s failed with %d",
2381 __func__, vcpu_str, ret);
2382 return false;
2383 }
2384 return true;
2385 }
2386
kvmppc_host_cpu_class_init(ObjectClass * oc,void * data)2387 static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data)
2388 {
2389 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2390 uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size");
2391 uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size");
2392
2393 /* Now fix up the class with information we can query from the host */
2394 pcc->pvr = mfpvr();
2395
2396 alter_insns(&pcc->insns_flags, PPC_ALTIVEC,
2397 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC);
2398 alter_insns(&pcc->insns_flags2, PPC2_VSX,
2399 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX);
2400 alter_insns(&pcc->insns_flags2, PPC2_DFP,
2401 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP);
2402
2403 if (dcache_size != -1) {
2404 pcc->l1_dcache_size = dcache_size;
2405 }
2406
2407 if (icache_size != -1) {
2408 pcc->l1_icache_size = icache_size;
2409 }
2410
2411 #if defined(TARGET_PPC64)
2412 pcc->radix_page_info = kvmppc_get_radix_page_info();
2413 #endif /* defined(TARGET_PPC64) */
2414 }
2415
kvmppc_has_cap_epr(void)2416 bool kvmppc_has_cap_epr(void)
2417 {
2418 return cap_epr;
2419 }
2420
kvmppc_has_cap_fixup_hcalls(void)2421 bool kvmppc_has_cap_fixup_hcalls(void)
2422 {
2423 return cap_fixup_hcalls;
2424 }
2425
kvmppc_has_cap_htm(void)2426 bool kvmppc_has_cap_htm(void)
2427 {
2428 return cap_htm;
2429 }
2430
kvmppc_has_cap_mmu_radix(void)2431 bool kvmppc_has_cap_mmu_radix(void)
2432 {
2433 return cap_mmu_radix;
2434 }
2435
kvmppc_has_cap_mmu_hash_v3(void)2436 bool kvmppc_has_cap_mmu_hash_v3(void)
2437 {
2438 return cap_mmu_hash_v3;
2439 }
2440
kvmppc_power8_host(void)2441 static bool kvmppc_power8_host(void)
2442 {
2443 bool ret = false;
2444 #ifdef TARGET_PPC64
2445 {
2446 uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr();
2447 ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) ||
2448 (base_pvr == CPU_POWERPC_POWER8NVL_BASE) ||
2449 (base_pvr == CPU_POWERPC_POWER8_BASE);
2450 }
2451 #endif /* TARGET_PPC64 */
2452 return ret;
2453 }
2454
parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c)2455 static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c)
2456 {
2457 bool l1d_thread_priv_req = !kvmppc_power8_host();
2458
2459 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) {
2460 return 2;
2461 } else if ((!l1d_thread_priv_req ||
2462 c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) &&
2463 (c.character & c.character_mask
2464 & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) {
2465 return 1;
2466 }
2467
2468 return 0;
2469 }
2470
parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c)2471 static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c)
2472 {
2473 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR) {
2474 return 2;
2475 } else if (c.character & c.character_mask & H_CPU_CHAR_SPEC_BAR_ORI31) {
2476 return 1;
2477 }
2478
2479 return 0;
2480 }
2481
parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c)2482 static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c)
2483 {
2484 if ((~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) &&
2485 (~c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) &&
2486 (~c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED)) {
2487 return SPAPR_CAP_FIXED_NA;
2488 } else if (c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) {
2489 return SPAPR_CAP_WORKAROUND;
2490 } else if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) {
2491 return SPAPR_CAP_FIXED_CCD;
2492 } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) {
2493 return SPAPR_CAP_FIXED_IBS;
2494 }
2495
2496 return 0;
2497 }
2498
parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c)2499 static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c)
2500 {
2501 if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) {
2502 return 1;
2503 }
2504 return 0;
2505 }
2506
kvmppc_has_cap_xive(void)2507 bool kvmppc_has_cap_xive(void)
2508 {
2509 return cap_xive;
2510 }
2511
kvmppc_get_cpu_characteristics(KVMState * s)2512 static void kvmppc_get_cpu_characteristics(KVMState *s)
2513 {
2514 struct kvm_ppc_cpu_char c;
2515 int ret;
2516
2517 /* Assume broken */
2518 cap_ppc_safe_cache = 0;
2519 cap_ppc_safe_bounds_check = 0;
2520 cap_ppc_safe_indirect_branch = 0;
2521
2522 ret = kvm_vm_check_extension(s, KVM_CAP_PPC_GET_CPU_CHAR);
2523 if (!ret) {
2524 return;
2525 }
2526 ret = kvm_vm_ioctl(s, KVM_PPC_GET_CPU_CHAR, &c);
2527 if (ret < 0) {
2528 return;
2529 }
2530
2531 cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c);
2532 cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c);
2533 cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c);
2534 cap_ppc_count_cache_flush_assist =
2535 parse_cap_ppc_count_cache_flush_assist(c);
2536 }
2537
kvmppc_get_cap_safe_cache(void)2538 int kvmppc_get_cap_safe_cache(void)
2539 {
2540 return cap_ppc_safe_cache;
2541 }
2542
kvmppc_get_cap_safe_bounds_check(void)2543 int kvmppc_get_cap_safe_bounds_check(void)
2544 {
2545 return cap_ppc_safe_bounds_check;
2546 }
2547
kvmppc_get_cap_safe_indirect_branch(void)2548 int kvmppc_get_cap_safe_indirect_branch(void)
2549 {
2550 return cap_ppc_safe_indirect_branch;
2551 }
2552
kvmppc_get_cap_count_cache_flush_assist(void)2553 int kvmppc_get_cap_count_cache_flush_assist(void)
2554 {
2555 return cap_ppc_count_cache_flush_assist;
2556 }
2557
kvmppc_has_cap_nested_kvm_hv(void)2558 bool kvmppc_has_cap_nested_kvm_hv(void)
2559 {
2560 return !!cap_ppc_nested_kvm_hv;
2561 }
2562
kvmppc_set_cap_nested_kvm_hv(int enable)2563 int kvmppc_set_cap_nested_kvm_hv(int enable)
2564 {
2565 return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_NESTED_HV, 0, enable);
2566 }
2567
kvmppc_has_cap_spapr_vfio(void)2568 bool kvmppc_has_cap_spapr_vfio(void)
2569 {
2570 return cap_spapr_vfio;
2571 }
2572
kvmppc_get_cap_large_decr(void)2573 int kvmppc_get_cap_large_decr(void)
2574 {
2575 return cap_large_decr;
2576 }
2577
kvmppc_enable_cap_large_decr(PowerPCCPU * cpu,int enable)2578 int kvmppc_enable_cap_large_decr(PowerPCCPU *cpu, int enable)
2579 {
2580 CPUState *cs = CPU(cpu);
2581 uint64_t lpcr = 0;
2582
2583 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2584 /* Do we need to modify the LPCR? */
2585 if (!!(lpcr & LPCR_LD) != !!enable) {
2586 if (enable) {
2587 lpcr |= LPCR_LD;
2588 } else {
2589 lpcr &= ~LPCR_LD;
2590 }
2591 kvm_set_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2592 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2593
2594 if (!!(lpcr & LPCR_LD) != !!enable) {
2595 return -1;
2596 }
2597 }
2598
2599 return 0;
2600 }
2601
kvmppc_has_cap_rpt_invalidate(void)2602 int kvmppc_has_cap_rpt_invalidate(void)
2603 {
2604 return cap_rpt_invalidate;
2605 }
2606
kvmppc_supports_ail_3(void)2607 bool kvmppc_supports_ail_3(void)
2608 {
2609 return cap_ail_mode_3;
2610 }
2611
kvm_ppc_get_host_cpu_class(void)2612 PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void)
2613 {
2614 uint32_t host_pvr = mfpvr();
2615 PowerPCCPUClass *pvr_pcc;
2616
2617 pvr_pcc = ppc_cpu_class_by_pvr(host_pvr);
2618 if (pvr_pcc == NULL) {
2619 pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr);
2620 }
2621
2622 return pvr_pcc;
2623 }
2624
pseries_machine_class_fixup(ObjectClass * oc,void * opaque)2625 static void pseries_machine_class_fixup(ObjectClass *oc, void *opaque)
2626 {
2627 MachineClass *mc = MACHINE_CLASS(oc);
2628
2629 mc->default_cpu_type = TYPE_HOST_POWERPC_CPU;
2630 }
2631
kvm_ppc_register_host_cpu_type(void)2632 static int kvm_ppc_register_host_cpu_type(void)
2633 {
2634 TypeInfo type_info = {
2635 .name = TYPE_HOST_POWERPC_CPU,
2636 .class_init = kvmppc_host_cpu_class_init,
2637 };
2638 PowerPCCPUClass *pvr_pcc;
2639 ObjectClass *oc;
2640 DeviceClass *dc;
2641 int i;
2642
2643 pvr_pcc = kvm_ppc_get_host_cpu_class();
2644 if (pvr_pcc == NULL) {
2645 return -1;
2646 }
2647 type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc));
2648 type_register_static(&type_info);
2649 /* override TCG default cpu type with 'host' cpu model */
2650 object_class_foreach(pseries_machine_class_fixup, TYPE_SPAPR_MACHINE,
2651 false, NULL);
2652
2653 oc = object_class_by_name(type_info.name);
2654 g_assert(oc);
2655
2656 /*
2657 * Update generic CPU family class alias (e.g. on a POWER8NVL host,
2658 * we want "POWER8" to be a "family" alias that points to the current
2659 * host CPU type, too)
2660 */
2661 dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc));
2662 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
2663 if (strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) {
2664 char *suffix;
2665
2666 ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc));
2667 suffix = strstr(ppc_cpu_aliases[i].model, POWERPC_CPU_TYPE_SUFFIX);
2668 if (suffix) {
2669 *suffix = 0;
2670 }
2671 break;
2672 }
2673 }
2674
2675 return 0;
2676 }
2677
kvmppc_define_rtas_kernel_token(uint32_t token,const char * function)2678 int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function)
2679 {
2680 struct kvm_rtas_token_args args = {
2681 .token = token,
2682 };
2683
2684 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) {
2685 return -ENOENT;
2686 }
2687
2688 strncpy(args.name, function, sizeof(args.name) - 1);
2689
2690 return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args);
2691 }
2692
kvmppc_get_htab_fd(bool write,uint64_t index,Error ** errp)2693 int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp)
2694 {
2695 struct kvm_get_htab_fd s = {
2696 .flags = write ? KVM_GET_HTAB_WRITE : 0,
2697 .start_index = index,
2698 };
2699 int ret;
2700
2701 if (!cap_htab_fd) {
2702 error_setg(errp, "KVM version doesn't support %s the HPT",
2703 write ? "writing" : "reading");
2704 return -ENOTSUP;
2705 }
2706
2707 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s);
2708 if (ret < 0) {
2709 error_setg(errp, "Unable to open fd for %s HPT %s KVM: %s",
2710 write ? "writing" : "reading", write ? "to" : "from",
2711 strerror(errno));
2712 return -errno;
2713 }
2714
2715 return ret;
2716 }
2717
kvmppc_save_htab(QEMUFile * f,int fd,size_t bufsize,int64_t max_ns)2718 int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns)
2719 {
2720 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2721 g_autofree uint8_t *buf = g_malloc(bufsize);
2722 ssize_t rc;
2723
2724 do {
2725 rc = read(fd, buf, bufsize);
2726 if (rc < 0) {
2727 fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n",
2728 strerror(errno));
2729 return rc;
2730 } else if (rc) {
2731 uint8_t *buffer = buf;
2732 ssize_t n = rc;
2733 while (n) {
2734 struct kvm_get_htab_header *head =
2735 (struct kvm_get_htab_header *) buffer;
2736 size_t chunksize = sizeof(*head) +
2737 HASH_PTE_SIZE_64 * head->n_valid;
2738
2739 qemu_put_be32(f, head->index);
2740 qemu_put_be16(f, head->n_valid);
2741 qemu_put_be16(f, head->n_invalid);
2742 qemu_put_buffer(f, (void *)(head + 1),
2743 HASH_PTE_SIZE_64 * head->n_valid);
2744
2745 buffer += chunksize;
2746 n -= chunksize;
2747 }
2748 }
2749 } while ((rc != 0)
2750 && ((max_ns < 0) ||
2751 ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns)));
2752
2753 return (rc == 0) ? 1 : 0;
2754 }
2755
kvmppc_load_htab_chunk(QEMUFile * f,int fd,uint32_t index,uint16_t n_valid,uint16_t n_invalid,Error ** errp)2756 int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index,
2757 uint16_t n_valid, uint16_t n_invalid, Error **errp)
2758 {
2759 struct kvm_get_htab_header *buf;
2760 size_t chunksize = sizeof(*buf) + n_valid * HASH_PTE_SIZE_64;
2761 ssize_t rc;
2762
2763 buf = alloca(chunksize);
2764 buf->index = index;
2765 buf->n_valid = n_valid;
2766 buf->n_invalid = n_invalid;
2767
2768 qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64 * n_valid);
2769
2770 rc = write(fd, buf, chunksize);
2771 if (rc < 0) {
2772 error_setg_errno(errp, errno, "Error writing the KVM hash table");
2773 return -errno;
2774 }
2775 if (rc != chunksize) {
2776 /* We should never get a short write on a single chunk */
2777 error_setg(errp, "Short write while restoring the KVM hash table");
2778 return -ENOSPC;
2779 }
2780 return 0;
2781 }
2782
kvm_arch_stop_on_emulation_error(CPUState * cpu)2783 bool kvm_arch_stop_on_emulation_error(CPUState *cpu)
2784 {
2785 return true;
2786 }
2787
kvm_arch_init_irq_routing(KVMState * s)2788 void kvm_arch_init_irq_routing(KVMState *s)
2789 {
2790 }
2791
kvmppc_read_hptes(ppc_hash_pte64_t * hptes,hwaddr ptex,int n)2792 void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n)
2793 {
2794 int fd, rc;
2795 int i;
2796
2797 fd = kvmppc_get_htab_fd(false, ptex, &error_abort);
2798
2799 i = 0;
2800 while (i < n) {
2801 struct kvm_get_htab_header *hdr;
2802 int m = n < HPTES_PER_GROUP ? n : HPTES_PER_GROUP;
2803 char buf[sizeof(*hdr) + HPTES_PER_GROUP * HASH_PTE_SIZE_64];
2804
2805 rc = read(fd, buf, sizeof(*hdr) + m * HASH_PTE_SIZE_64);
2806 if (rc < 0) {
2807 hw_error("kvmppc_read_hptes: Unable to read HPTEs");
2808 }
2809
2810 hdr = (struct kvm_get_htab_header *)buf;
2811 while ((i < n) && ((char *)hdr < (buf + rc))) {
2812 int invalid = hdr->n_invalid, valid = hdr->n_valid;
2813
2814 if (hdr->index != (ptex + i)) {
2815 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32
2816 " != (%"HWADDR_PRIu" + %d", hdr->index, ptex, i);
2817 }
2818
2819 if (n - i < valid) {
2820 valid = n - i;
2821 }
2822 memcpy(hptes + i, hdr + 1, HASH_PTE_SIZE_64 * valid);
2823 i += valid;
2824
2825 if ((n - i) < invalid) {
2826 invalid = n - i;
2827 }
2828 memset(hptes + i, 0, invalid * HASH_PTE_SIZE_64);
2829 i += invalid;
2830
2831 hdr = (struct kvm_get_htab_header *)
2832 ((char *)(hdr + 1) + HASH_PTE_SIZE_64 * hdr->n_valid);
2833 }
2834 }
2835
2836 close(fd);
2837 }
2838
kvmppc_write_hpte(hwaddr ptex,uint64_t pte0,uint64_t pte1)2839 void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1)
2840 {
2841 int fd, rc;
2842 struct {
2843 struct kvm_get_htab_header hdr;
2844 uint64_t pte0;
2845 uint64_t pte1;
2846 } buf;
2847
2848 fd = kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort);
2849
2850 buf.hdr.n_valid = 1;
2851 buf.hdr.n_invalid = 0;
2852 buf.hdr.index = ptex;
2853 buf.pte0 = cpu_to_be64(pte0);
2854 buf.pte1 = cpu_to_be64(pte1);
2855
2856 rc = write(fd, &buf, sizeof(buf));
2857 if (rc != sizeof(buf)) {
2858 hw_error("kvmppc_write_hpte: Unable to update KVM HPT");
2859 }
2860 close(fd);
2861 }
2862
kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry * route,uint64_t address,uint32_t data,PCIDevice * dev)2863 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
2864 uint64_t address, uint32_t data, PCIDevice *dev)
2865 {
2866 return 0;
2867 }
2868
kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry * route,int vector,PCIDevice * dev)2869 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
2870 int vector, PCIDevice *dev)
2871 {
2872 return 0;
2873 }
2874
kvm_arch_release_virq_post(int virq)2875 int kvm_arch_release_virq_post(int virq)
2876 {
2877 return 0;
2878 }
2879
kvm_arch_msi_data_to_gsi(uint32_t data)2880 int kvm_arch_msi_data_to_gsi(uint32_t data)
2881 {
2882 return data & 0xffff;
2883 }
2884
2885 #if defined(CONFIG_PSERIES)
kvm_handle_nmi(PowerPCCPU * cpu,struct kvm_run * run)2886 int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run)
2887 {
2888 uint16_t flags = run->flags & KVM_RUN_PPC_NMI_DISP_MASK;
2889
2890 cpu_synchronize_state(CPU(cpu));
2891
2892 spapr_mce_req_event(cpu, flags == KVM_RUN_PPC_NMI_DISP_FULLY_RECOV);
2893
2894 return 0;
2895 }
2896 #endif
2897
kvmppc_enable_hwrng(void)2898 int kvmppc_enable_hwrng(void)
2899 {
2900 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) {
2901 return -1;
2902 }
2903
2904 return kvmppc_enable_hcall(kvm_state, H_RANDOM);
2905 }
2906
kvmppc_check_papr_resize_hpt(Error ** errp)2907 void kvmppc_check_papr_resize_hpt(Error **errp)
2908 {
2909 if (!kvm_enabled()) {
2910 return; /* No KVM, we're good */
2911 }
2912
2913 if (cap_resize_hpt) {
2914 return; /* Kernel has explicit support, we're good */
2915 }
2916
2917 /* Otherwise fallback on looking for PR KVM */
2918 if (kvmppc_is_pr(kvm_state)) {
2919 return;
2920 }
2921
2922 error_setg(errp,
2923 "Hash page table resizing not available with this KVM version");
2924 }
2925
kvmppc_resize_hpt_prepare(PowerPCCPU * cpu,target_ulong flags,int shift)2926 int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shift)
2927 {
2928 CPUState *cs = CPU(cpu);
2929 struct kvm_ppc_resize_hpt rhpt = {
2930 .flags = flags,
2931 .shift = shift,
2932 };
2933
2934 if (!cap_resize_hpt) {
2935 return -ENOSYS;
2936 }
2937
2938 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_PREPARE, &rhpt);
2939 }
2940
kvmppc_resize_hpt_commit(PowerPCCPU * cpu,target_ulong flags,int shift)2941 int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shift)
2942 {
2943 CPUState *cs = CPU(cpu);
2944 struct kvm_ppc_resize_hpt rhpt = {
2945 .flags = flags,
2946 .shift = shift,
2947 };
2948
2949 if (!cap_resize_hpt) {
2950 return -ENOSYS;
2951 }
2952
2953 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_COMMIT, &rhpt);
2954 }
2955
2956 /*
2957 * This is a helper function to detect a post migration scenario
2958 * in which a guest, running as KVM-HV, freezes in cpu_post_load because
2959 * the guest kernel can't handle a PVR value other than the actual host
2960 * PVR in KVM_SET_SREGS, even if pvr_match() returns true.
2961 *
2962 * If we don't have cap_ppc_pvr_compat and we're not running in PR
2963 * (so, we're HV), return true. The workaround itself is done in
2964 * cpu_post_load.
2965 *
2966 * The order here is important: we'll only check for KVM PR as a
2967 * fallback if the guest kernel can't handle the situation itself.
2968 * We need to avoid as much as possible querying the running KVM type
2969 * in QEMU level.
2970 */
kvmppc_pvr_workaround_required(PowerPCCPU * cpu)2971 bool kvmppc_pvr_workaround_required(PowerPCCPU *cpu)
2972 {
2973 CPUState *cs = CPU(cpu);
2974
2975 if (!kvm_enabled()) {
2976 return false;
2977 }
2978
2979 if (cap_ppc_pvr_compat) {
2980 return false;
2981 }
2982
2983 return !kvmppc_is_pr(cs->kvm_state);
2984 }
2985
kvmppc_set_reg_ppc_online(PowerPCCPU * cpu,unsigned int online)2986 void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online)
2987 {
2988 CPUState *cs = CPU(cpu);
2989
2990 if (kvm_enabled()) {
2991 kvm_set_one_reg(cs, KVM_REG_PPC_ONLINE, &online);
2992 }
2993 }
2994
kvmppc_set_reg_tb_offset(PowerPCCPU * cpu,int64_t tb_offset)2995 void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t tb_offset)
2996 {
2997 CPUState *cs = CPU(cpu);
2998
2999 if (kvm_enabled()) {
3000 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &tb_offset);
3001 }
3002 }
3003
kvm_arch_accel_class_init(ObjectClass * oc)3004 void kvm_arch_accel_class_init(ObjectClass *oc)
3005 {
3006 }
3007
kvm_cpu_accel_class_init(ObjectClass * oc,void * data)3008 static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data)
3009 {
3010 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
3011
3012 acc->cpu_target_realize = kvmppc_cpu_realize;
3013 }
3014
3015 static const TypeInfo kvm_cpu_accel_type_info = {
3016 .name = ACCEL_CPU_NAME("kvm"),
3017
3018 .parent = TYPE_ACCEL_CPU,
3019 .class_init = kvm_cpu_accel_class_init,
3020 .abstract = true,
3021 };
kvm_cpu_accel_register_types(void)3022 static void kvm_cpu_accel_register_types(void)
3023 {
3024 type_register_static(&kvm_cpu_accel_type_info);
3025 }
3026 type_init(kvm_cpu_accel_register_types);
3027