1 /*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu/timer.h"
24 #include "qemu/log.h"
25 #include "exec/page-vary.h"
26 #include "target/arm/idau.h"
27 #include "qemu/module.h"
28 #include "qapi/error.h"
29 #include "cpu.h"
30 #ifdef CONFIG_TCG
31 #include "exec/translation-block.h"
32 #include "accel/tcg/cpu-ops.h"
33 #endif /* CONFIG_TCG */
34 #include "internals.h"
35 #include "cpu-features.h"
36 #include "exec/exec-all.h"
37 #include "hw/qdev-properties.h"
38 #if !defined(CONFIG_USER_ONLY)
39 #include "hw/loader.h"
40 #include "hw/boards.h"
41 #ifdef CONFIG_TCG
42 #include "hw/intc/armv7m_nvic.h"
43 #endif /* CONFIG_TCG */
44 #endif /* !CONFIG_USER_ONLY */
45 #include "system/tcg.h"
46 #include "system/qtest.h"
47 #include "system/hw_accel.h"
48 #include "kvm_arm.h"
49 #include "disas/capstone.h"
50 #include "fpu/softfloat.h"
51 #include "cpregs.h"
52 #include "target/arm/cpu-qom.h"
53 #include "target/arm/gtimer.h"
54
arm_cpu_set_pc(CPUState * cs,vaddr value)55 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
56 {
57 ARMCPU *cpu = ARM_CPU(cs);
58 CPUARMState *env = &cpu->env;
59
60 if (is_a64(env)) {
61 env->pc = value;
62 env->thumb = false;
63 } else {
64 env->regs[15] = value & ~1;
65 env->thumb = value & 1;
66 }
67 }
68
arm_cpu_get_pc(CPUState * cs)69 static vaddr arm_cpu_get_pc(CPUState *cs)
70 {
71 ARMCPU *cpu = ARM_CPU(cs);
72 CPUARMState *env = &cpu->env;
73
74 if (is_a64(env)) {
75 return env->pc;
76 } else {
77 return env->regs[15];
78 }
79 }
80
81 #ifdef CONFIG_TCG
arm_cpu_synchronize_from_tb(CPUState * cs,const TranslationBlock * tb)82 void arm_cpu_synchronize_from_tb(CPUState *cs,
83 const TranslationBlock *tb)
84 {
85 /* The program counter is always up to date with CF_PCREL. */
86 if (!(tb_cflags(tb) & CF_PCREL)) {
87 CPUARMState *env = cpu_env(cs);
88 /*
89 * It's OK to look at env for the current mode here, because it's
90 * never possible for an AArch64 TB to chain to an AArch32 TB.
91 */
92 if (is_a64(env)) {
93 env->pc = tb->pc;
94 } else {
95 env->regs[15] = tb->pc;
96 }
97 }
98 }
99
arm_restore_state_to_opc(CPUState * cs,const TranslationBlock * tb,const uint64_t * data)100 void arm_restore_state_to_opc(CPUState *cs,
101 const TranslationBlock *tb,
102 const uint64_t *data)
103 {
104 CPUARMState *env = cpu_env(cs);
105
106 if (is_a64(env)) {
107 if (tb_cflags(tb) & CF_PCREL) {
108 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0];
109 } else {
110 env->pc = data[0];
111 }
112 env->condexec_bits = 0;
113 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
114 } else {
115 if (tb_cflags(tb) & CF_PCREL) {
116 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0];
117 } else {
118 env->regs[15] = data[0];
119 }
120 env->condexec_bits = data[1];
121 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
122 }
123 }
124 #endif /* CONFIG_TCG */
125
126 #ifndef CONFIG_USER_ONLY
127 /*
128 * With SCTLR_ELx.NMI == 0, IRQ with Superpriority is masked identically with
129 * IRQ without Superpriority. Moreover, if the GIC is configured so that
130 * FEAT_GICv3_NMI is only set if FEAT_NMI is set, then we won't ever see
131 * CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here
132 * unconditionally.
133 */
arm_cpu_has_work(CPUState * cs)134 static bool arm_cpu_has_work(CPUState *cs)
135 {
136 ARMCPU *cpu = ARM_CPU(cs);
137
138 return (cpu->power_state != PSCI_OFF)
139 && cs->interrupt_request &
140 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
141 | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VINMI | CPU_INTERRUPT_VFNMI
142 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR
143 | CPU_INTERRUPT_EXITTB);
144 }
145 #endif /* !CONFIG_USER_ONLY */
146
arm_cpu_mmu_index(CPUState * cs,bool ifetch)147 static int arm_cpu_mmu_index(CPUState *cs, bool ifetch)
148 {
149 return arm_env_mmu_index(cpu_env(cs));
150 }
151
arm_register_pre_el_change_hook(ARMCPU * cpu,ARMELChangeHookFn * hook,void * opaque)152 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
153 void *opaque)
154 {
155 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
156
157 entry->hook = hook;
158 entry->opaque = opaque;
159
160 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node);
161 }
162
arm_register_el_change_hook(ARMCPU * cpu,ARMELChangeHookFn * hook,void * opaque)163 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
164 void *opaque)
165 {
166 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
167
168 entry->hook = hook;
169 entry->opaque = opaque;
170
171 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node);
172 }
173
cp_reg_reset(gpointer key,gpointer value,gpointer opaque)174 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
175 {
176 /* Reset a single ARMCPRegInfo register */
177 ARMCPRegInfo *ri = value;
178 ARMCPU *cpu = opaque;
179
180 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) {
181 return;
182 }
183
184 if (ri->resetfn) {
185 ri->resetfn(&cpu->env, ri);
186 return;
187 }
188
189 /* A zero offset is never possible as it would be regs[0]
190 * so we use it to indicate that reset is being handled elsewhere.
191 * This is basically only used for fields in non-core coprocessors
192 * (like the pxa2xx ones).
193 */
194 if (!ri->fieldoffset) {
195 return;
196 }
197
198 if (cpreg_field_is_64bit(ri)) {
199 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
200 } else {
201 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
202 }
203 }
204
cp_reg_check_reset(gpointer key,gpointer value,gpointer opaque)205 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
206 {
207 /* Purely an assertion check: we've already done reset once,
208 * so now check that running the reset for the cpreg doesn't
209 * change its value. This traps bugs where two different cpregs
210 * both try to reset the same state field but to different values.
211 */
212 ARMCPRegInfo *ri = value;
213 ARMCPU *cpu = opaque;
214 uint64_t oldvalue, newvalue;
215
216 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
217 return;
218 }
219
220 oldvalue = read_raw_cp_reg(&cpu->env, ri);
221 cp_reg_reset(key, value, opaque);
222 newvalue = read_raw_cp_reg(&cpu->env, ri);
223 assert(oldvalue == newvalue);
224 }
225
arm_cpu_reset_hold(Object * obj,ResetType type)226 static void arm_cpu_reset_hold(Object *obj, ResetType type)
227 {
228 CPUState *cs = CPU(obj);
229 ARMCPU *cpu = ARM_CPU(cs);
230 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
231 CPUARMState *env = &cpu->env;
232
233 if (acc->parent_phases.hold) {
234 acc->parent_phases.hold(obj, type);
235 }
236
237 memset(env, 0, offsetof(CPUARMState, end_reset_fields));
238
239 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
240 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
241
242 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
243 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0;
244 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1;
245 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2;
246
247 cpu->power_state = cs->start_powered_off ? PSCI_OFF : PSCI_ON;
248
249 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
250 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
251 }
252
253 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
254 /* 64 bit CPUs always start in 64 bit mode */
255 env->aarch64 = true;
256 #if defined(CONFIG_USER_ONLY)
257 env->pstate = PSTATE_MODE_EL0t;
258 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
259 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
260 /* Enable all PAC keys. */
261 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
262 SCTLR_EnDA | SCTLR_EnDB);
263 /* Trap on btype=3 for PACIxSP. */
264 env->cp15.sctlr_el[1] |= SCTLR_BT0;
265 /* Trap on implementation defined registers. */
266 if (cpu_isar_feature(aa64_tidcp1, cpu)) {
267 env->cp15.sctlr_el[1] |= SCTLR_TIDCP;
268 }
269 /* and to the FP/Neon instructions */
270 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
271 CPACR_EL1, FPEN, 3);
272 /* and to the SVE instructions, with default vector length */
273 if (cpu_isar_feature(aa64_sve, cpu)) {
274 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
275 CPACR_EL1, ZEN, 3);
276 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1;
277 }
278 /* and for SME instructions, with default vector length, and TPIDR2 */
279 if (cpu_isar_feature(aa64_sme, cpu)) {
280 env->cp15.sctlr_el[1] |= SCTLR_EnTP2;
281 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
282 CPACR_EL1, SMEN, 3);
283 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1;
284 if (cpu_isar_feature(aa64_sme_fa64, cpu)) {
285 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1],
286 SMCR, FA64, 1);
287 }
288 }
289 /*
290 * Enable 48-bit address space (TODO: take reserved_va into account).
291 * Enable TBI0 but not TBI1.
292 * Note that this must match useronly_clean_ptr.
293 */
294 env->cp15.tcr_el[1] = 5 | (1ULL << 37);
295
296 /* Enable MTE */
297 if (cpu_isar_feature(aa64_mte, cpu)) {
298 /* Enable tag access, but leave TCF0 as No Effect (0). */
299 env->cp15.sctlr_el[1] |= SCTLR_ATA0;
300 /*
301 * Exclude all tags, so that tag 0 is always used.
302 * This corresponds to Linux current->thread.gcr_incl = 0.
303 *
304 * Set RRND, so that helper_irg() will generate a seed later.
305 * Here in cpu_reset(), the crypto subsystem has not yet been
306 * initialized.
307 */
308 env->cp15.gcr_el1 = 0x1ffff;
309 }
310 /*
311 * Disable access to SCXTNUM_EL0 from CSV2_1p2.
312 * This is not yet exposed from the Linux kernel in any way.
313 */
314 env->cp15.sctlr_el[1] |= SCTLR_TSCXT;
315 /* Disable access to Debug Communication Channel (DCC). */
316 env->cp15.mdscr_el1 |= 1 << 12;
317 /* Enable FEAT_MOPS */
318 env->cp15.sctlr_el[1] |= SCTLR_MSCEN;
319 #else
320 /* Reset into the highest available EL */
321 if (arm_feature(env, ARM_FEATURE_EL3)) {
322 env->pstate = PSTATE_MODE_EL3h;
323 } else if (arm_feature(env, ARM_FEATURE_EL2)) {
324 env->pstate = PSTATE_MODE_EL2h;
325 } else {
326 env->pstate = PSTATE_MODE_EL1h;
327 }
328
329 /* Sample rvbar at reset. */
330 env->cp15.rvbar = cpu->rvbar_prop;
331 env->pc = env->cp15.rvbar;
332 #endif
333 } else {
334 #if defined(CONFIG_USER_ONLY)
335 /* Userspace expects access to cp10 and cp11 for FP/Neon */
336 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
337 CPACR, CP10, 3);
338 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
339 CPACR, CP11, 3);
340 #endif
341 if (arm_feature(env, ARM_FEATURE_V8)) {
342 env->cp15.rvbar = cpu->rvbar_prop;
343 env->regs[15] = cpu->rvbar_prop;
344 }
345 }
346
347 #if defined(CONFIG_USER_ONLY)
348 env->uncached_cpsr = ARM_CPU_MODE_USR;
349 /* For user mode we must enable access to coprocessors */
350 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
351 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
352 env->cp15.c15_cpar = 3;
353 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
354 env->cp15.c15_cpar = 1;
355 }
356 #else
357
358 /*
359 * If the highest available EL is EL2, AArch32 will start in Hyp
360 * mode; otherwise it starts in SVC. Note that if we start in
361 * AArch64 then these values in the uncached_cpsr will be ignored.
362 */
363 if (arm_feature(env, ARM_FEATURE_EL2) &&
364 !arm_feature(env, ARM_FEATURE_EL3)) {
365 env->uncached_cpsr = ARM_CPU_MODE_HYP;
366 } else {
367 env->uncached_cpsr = ARM_CPU_MODE_SVC;
368 }
369 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
370
371 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
372 * executing as AArch32 then check if highvecs are enabled and
373 * adjust the PC accordingly.
374 */
375 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
376 env->regs[15] = 0xFFFF0000;
377 }
378
379 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
380 #endif
381
382 if (arm_feature(env, ARM_FEATURE_M)) {
383 #ifndef CONFIG_USER_ONLY
384 uint32_t initial_msp; /* Loaded from 0x0 */
385 uint32_t initial_pc; /* Loaded from 0x4 */
386 uint8_t *rom;
387 uint32_t vecbase;
388 #endif
389
390 if (cpu_isar_feature(aa32_lob, cpu)) {
391 /*
392 * LTPSIZE is constant 4 if MVE not implemented, and resets
393 * to an UNKNOWN value if MVE is implemented. We choose to
394 * always reset to 4.
395 */
396 env->v7m.ltpsize = 4;
397 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */
398 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT;
399 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT;
400 }
401
402 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
403 env->v7m.secure = true;
404 } else {
405 /* This bit resets to 0 if security is supported, but 1 if
406 * it is not. The bit is not present in v7M, but we set it
407 * here so we can avoid having to make checks on it conditional
408 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
409 */
410 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
411 /*
412 * Set NSACR to indicate "NS access permitted to everything";
413 * this avoids having to have all the tests of it being
414 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
415 * v8.1M the guest-visible value of NSACR in a CPU without the
416 * Security Extension is 0xcff.
417 */
418 env->v7m.nsacr = 0xcff;
419 }
420
421 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
422 * that it resets to 1, so QEMU always does that rather than making
423 * it dependent on CPU model. In v8M it is RES1.
424 */
425 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK;
426 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK;
427 if (arm_feature(env, ARM_FEATURE_V8)) {
428 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
429 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK;
430 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK;
431 }
432 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
433 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK;
434 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
435 }
436
437 if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
438 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK;
439 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
440 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;
441 }
442
443 #ifndef CONFIG_USER_ONLY
444 /* Unlike A/R profile, M profile defines the reset LR value */
445 env->regs[14] = 0xffffffff;
446
447 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80;
448 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80;
449
450 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
451 vecbase = env->v7m.vecbase[env->v7m.secure];
452 rom = rom_ptr_for_as(cs->as, vecbase, 8);
453 if (rom) {
454 /* Address zero is covered by ROM which hasn't yet been
455 * copied into physical memory.
456 */
457 initial_msp = ldl_p(rom);
458 initial_pc = ldl_p(rom + 4);
459 } else {
460 /* Address zero not covered by a ROM blob, or the ROM blob
461 * is in non-modifiable memory and this is a second reset after
462 * it got copied into memory. In the latter case, rom_ptr
463 * will return a NULL pointer and we should use ldl_phys instead.
464 */
465 initial_msp = ldl_phys(cs->as, vecbase);
466 initial_pc = ldl_phys(cs->as, vecbase + 4);
467 }
468
469 qemu_log_mask(CPU_LOG_INT,
470 "Loaded reset SP 0x%x PC 0x%x from vector table\n",
471 initial_msp, initial_pc);
472
473 env->regs[13] = initial_msp & 0xFFFFFFFC;
474 env->regs[15] = initial_pc & ~1;
475 env->thumb = initial_pc & 1;
476 #else
477 /*
478 * For user mode we run non-secure and with access to the FPU.
479 * The FPU context is active (ie does not need further setup)
480 * and is owned by non-secure.
481 */
482 env->v7m.secure = false;
483 env->v7m.nsacr = 0xcff;
484 env->v7m.cpacr[M_REG_NS] = 0xf0ffff;
485 env->v7m.fpccr[M_REG_S] &=
486 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK);
487 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK;
488 #endif
489 }
490
491 /* M profile requires that reset clears the exclusive monitor;
492 * A profile does not, but clearing it makes more sense than having it
493 * set with an exclusive access on address zero.
494 */
495 arm_clear_exclusive(env);
496
497 if (arm_feature(env, ARM_FEATURE_PMSA)) {
498 if (cpu->pmsav7_dregion > 0) {
499 if (arm_feature(env, ARM_FEATURE_V8)) {
500 memset(env->pmsav8.rbar[M_REG_NS], 0,
501 sizeof(*env->pmsav8.rbar[M_REG_NS])
502 * cpu->pmsav7_dregion);
503 memset(env->pmsav8.rlar[M_REG_NS], 0,
504 sizeof(*env->pmsav8.rlar[M_REG_NS])
505 * cpu->pmsav7_dregion);
506 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
507 memset(env->pmsav8.rbar[M_REG_S], 0,
508 sizeof(*env->pmsav8.rbar[M_REG_S])
509 * cpu->pmsav7_dregion);
510 memset(env->pmsav8.rlar[M_REG_S], 0,
511 sizeof(*env->pmsav8.rlar[M_REG_S])
512 * cpu->pmsav7_dregion);
513 }
514 } else if (arm_feature(env, ARM_FEATURE_V7)) {
515 memset(env->pmsav7.drbar, 0,
516 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
517 memset(env->pmsav7.drsr, 0,
518 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
519 memset(env->pmsav7.dracr, 0,
520 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
521 }
522 }
523
524 if (cpu->pmsav8r_hdregion > 0) {
525 memset(env->pmsav8.hprbar, 0,
526 sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion);
527 memset(env->pmsav8.hprlar, 0,
528 sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion);
529 }
530
531 env->pmsav7.rnr[M_REG_NS] = 0;
532 env->pmsav7.rnr[M_REG_S] = 0;
533 env->pmsav8.mair0[M_REG_NS] = 0;
534 env->pmsav8.mair0[M_REG_S] = 0;
535 env->pmsav8.mair1[M_REG_NS] = 0;
536 env->pmsav8.mair1[M_REG_S] = 0;
537 }
538
539 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
540 if (cpu->sau_sregion > 0) {
541 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion);
542 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion);
543 }
544 env->sau.rnr = 0;
545 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
546 * the Cortex-M33 does.
547 */
548 env->sau.ctrl = 0;
549 }
550
551 set_flush_to_zero(1, &env->vfp.fp_status[FPST_STD]);
552 set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_STD]);
553 set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD]);
554 set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD_F16]);
555 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32]);
556 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64]);
557 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD]);
558 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32_F16]);
559 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]);
560 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD_F16]);
561 arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH]);
562 set_flush_to_zero(1, &env->vfp.fp_status[FPST_AH]);
563 set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_AH]);
564 arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH_F16]);
565
566 #ifndef CONFIG_USER_ONLY
567 if (kvm_enabled()) {
568 kvm_arm_reset_vcpu(cpu);
569 }
570 #endif
571
572 if (tcg_enabled()) {
573 hw_breakpoint_update_all(cpu);
574 hw_watchpoint_update_all(cpu);
575
576 arm_rebuild_hflags(env);
577 }
578 }
579
arm_emulate_firmware_reset(CPUState * cpustate,int target_el)580 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el)
581 {
582 ARMCPU *cpu = ARM_CPU(cpustate);
583 CPUARMState *env = &cpu->env;
584 bool have_el3 = arm_feature(env, ARM_FEATURE_EL3);
585 bool have_el2 = arm_feature(env, ARM_FEATURE_EL2);
586
587 /*
588 * Check we have the EL we're aiming for. If that is the
589 * highest implemented EL, then cpu_reset has already done
590 * all the work.
591 */
592 switch (target_el) {
593 case 3:
594 assert(have_el3);
595 return;
596 case 2:
597 assert(have_el2);
598 if (!have_el3) {
599 return;
600 }
601 break;
602 case 1:
603 if (!have_el3 && !have_el2) {
604 return;
605 }
606 break;
607 default:
608 g_assert_not_reached();
609 }
610
611 if (have_el3) {
612 /*
613 * Set the EL3 state so code can run at EL2. This should match
614 * the requirements set by Linux in its booting spec.
615 */
616 if (env->aarch64) {
617 env->cp15.scr_el3 |= SCR_RW;
618 if (cpu_isar_feature(aa64_pauth, cpu)) {
619 env->cp15.scr_el3 |= SCR_API | SCR_APK;
620 }
621 if (cpu_isar_feature(aa64_mte, cpu)) {
622 env->cp15.scr_el3 |= SCR_ATA;
623 }
624 if (cpu_isar_feature(aa64_sve, cpu)) {
625 env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK;
626 env->vfp.zcr_el[3] = 0xf;
627 }
628 if (cpu_isar_feature(aa64_sme, cpu)) {
629 env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK;
630 env->cp15.scr_el3 |= SCR_ENTP2;
631 env->vfp.smcr_el[3] = 0xf;
632 }
633 if (cpu_isar_feature(aa64_hcx, cpu)) {
634 env->cp15.scr_el3 |= SCR_HXEN;
635 }
636 if (cpu_isar_feature(aa64_fgt, cpu)) {
637 env->cp15.scr_el3 |= SCR_FGTEN;
638 }
639 }
640
641 if (target_el == 2) {
642 /* If the guest is at EL2 then Linux expects the HVC insn to work */
643 env->cp15.scr_el3 |= SCR_HCE;
644 }
645
646 /* Put CPU into non-secure state */
647 env->cp15.scr_el3 |= SCR_NS;
648 /* Set NSACR.{CP11,CP10} so NS can access the FPU */
649 env->cp15.nsacr |= 3 << 10;
650 }
651
652 if (have_el2 && target_el < 2) {
653 /* Set EL2 state so code can run at EL1. */
654 if (env->aarch64) {
655 env->cp15.hcr_el2 |= HCR_RW;
656 }
657 }
658
659 /* Set the CPU to the desired state */
660 if (env->aarch64) {
661 env->pstate = aarch64_pstate_mode(target_el, true);
662 } else {
663 static const uint32_t mode_for_el[] = {
664 0,
665 ARM_CPU_MODE_SVC,
666 ARM_CPU_MODE_HYP,
667 ARM_CPU_MODE_SVC,
668 };
669
670 cpsr_write(env, mode_for_el[target_el], CPSR_M, CPSRWriteRaw);
671 }
672 }
673
674
675 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
676
arm_excp_unmasked(CPUState * cs,unsigned int excp_idx,unsigned int target_el,unsigned int cur_el,bool secure,uint64_t hcr_el2)677 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
678 unsigned int target_el,
679 unsigned int cur_el, bool secure,
680 uint64_t hcr_el2)
681 {
682 CPUARMState *env = cpu_env(cs);
683 bool pstate_unmasked;
684 bool unmasked = false;
685 bool allIntMask = false;
686
687 /*
688 * Don't take exceptions if they target a lower EL.
689 * This check should catch any exceptions that would not be taken
690 * but left pending.
691 */
692 if (cur_el > target_el) {
693 return false;
694 }
695
696 if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) &&
697 env->cp15.sctlr_el[target_el] & SCTLR_NMI && cur_el == target_el) {
698 allIntMask = env->pstate & PSTATE_ALLINT ||
699 ((env->cp15.sctlr_el[target_el] & SCTLR_SPINTMASK) &&
700 (env->pstate & PSTATE_SP));
701 }
702
703 switch (excp_idx) {
704 case EXCP_NMI:
705 pstate_unmasked = !allIntMask;
706 break;
707
708 case EXCP_VINMI:
709 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
710 /* VINMIs are only taken when hypervized. */
711 return false;
712 }
713 return !allIntMask;
714 case EXCP_VFNMI:
715 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
716 /* VFNMIs are only taken when hypervized. */
717 return false;
718 }
719 return !allIntMask;
720 case EXCP_FIQ:
721 pstate_unmasked = (!(env->daif & PSTATE_F)) && (!allIntMask);
722 break;
723
724 case EXCP_IRQ:
725 pstate_unmasked = (!(env->daif & PSTATE_I)) && (!allIntMask);
726 break;
727
728 case EXCP_VFIQ:
729 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
730 /* VFIQs are only taken when hypervized. */
731 return false;
732 }
733 return !(env->daif & PSTATE_F) && (!allIntMask);
734 case EXCP_VIRQ:
735 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
736 /* VIRQs are only taken when hypervized. */
737 return false;
738 }
739 return !(env->daif & PSTATE_I) && (!allIntMask);
740 case EXCP_VSERR:
741 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) {
742 /* VIRQs are only taken when hypervized. */
743 return false;
744 }
745 return !(env->daif & PSTATE_A);
746 default:
747 g_assert_not_reached();
748 }
749
750 /*
751 * Use the target EL, current execution state and SCR/HCR settings to
752 * determine whether the corresponding CPSR bit is used to mask the
753 * interrupt.
754 */
755 if ((target_el > cur_el) && (target_el != 1)) {
756 /* Exceptions targeting a higher EL may not be maskable */
757 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
758 switch (target_el) {
759 case 2:
760 /*
761 * According to ARM DDI 0487H.a, an interrupt can be masked
762 * when HCR_E2H and HCR_TGE are both set regardless of the
763 * current Security state. Note that we need to revisit this
764 * part again once we need to support NMI.
765 */
766 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
767 unmasked = true;
768 }
769 break;
770 case 3:
771 /* Interrupt cannot be masked when the target EL is 3 */
772 unmasked = true;
773 break;
774 default:
775 g_assert_not_reached();
776 }
777 } else {
778 /*
779 * The old 32-bit-only environment has a more complicated
780 * masking setup. HCR and SCR bits not only affect interrupt
781 * routing but also change the behaviour of masking.
782 */
783 bool hcr, scr;
784
785 switch (excp_idx) {
786 case EXCP_FIQ:
787 /*
788 * If FIQs are routed to EL3 or EL2 then there are cases where
789 * we override the CPSR.F in determining if the exception is
790 * masked or not. If neither of these are set then we fall back
791 * to the CPSR.F setting otherwise we further assess the state
792 * below.
793 */
794 hcr = hcr_el2 & HCR_FMO;
795 scr = (env->cp15.scr_el3 & SCR_FIQ);
796
797 /*
798 * When EL3 is 32-bit, the SCR.FW bit controls whether the
799 * CPSR.F bit masks FIQ interrupts when taken in non-secure
800 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
801 * when non-secure but only when FIQs are only routed to EL3.
802 */
803 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
804 break;
805 case EXCP_IRQ:
806 /*
807 * When EL3 execution state is 32-bit, if HCR.IMO is set then
808 * we may override the CPSR.I masking when in non-secure state.
809 * The SCR.IRQ setting has already been taken into consideration
810 * when setting the target EL, so it does not have a further
811 * affect here.
812 */
813 hcr = hcr_el2 & HCR_IMO;
814 scr = false;
815 break;
816 default:
817 g_assert_not_reached();
818 }
819
820 if ((scr || hcr) && !secure) {
821 unmasked = true;
822 }
823 }
824 }
825
826 /*
827 * The PSTATE bits only mask the interrupt if we have not overridden the
828 * ability above.
829 */
830 return unmasked || pstate_unmasked;
831 }
832
arm_cpu_exec_interrupt(CPUState * cs,int interrupt_request)833 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
834 {
835 CPUARMState *env = cpu_env(cs);
836 uint32_t cur_el = arm_current_el(env);
837 bool secure = arm_is_secure(env);
838 uint64_t hcr_el2 = arm_hcr_el2_eff(env);
839 uint32_t target_el;
840 uint32_t excp_idx;
841
842 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
843
844 if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) &&
845 (arm_sctlr(env, cur_el) & SCTLR_NMI)) {
846 if (interrupt_request & CPU_INTERRUPT_NMI) {
847 excp_idx = EXCP_NMI;
848 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
849 if (arm_excp_unmasked(cs, excp_idx, target_el,
850 cur_el, secure, hcr_el2)) {
851 goto found;
852 }
853 }
854 if (interrupt_request & CPU_INTERRUPT_VINMI) {
855 excp_idx = EXCP_VINMI;
856 target_el = 1;
857 if (arm_excp_unmasked(cs, excp_idx, target_el,
858 cur_el, secure, hcr_el2)) {
859 goto found;
860 }
861 }
862 if (interrupt_request & CPU_INTERRUPT_VFNMI) {
863 excp_idx = EXCP_VFNMI;
864 target_el = 1;
865 if (arm_excp_unmasked(cs, excp_idx, target_el,
866 cur_el, secure, hcr_el2)) {
867 goto found;
868 }
869 }
870 } else {
871 /*
872 * NMI disabled: interrupts with superpriority are handled
873 * as if they didn't have it
874 */
875 if (interrupt_request & CPU_INTERRUPT_NMI) {
876 interrupt_request |= CPU_INTERRUPT_HARD;
877 }
878 if (interrupt_request & CPU_INTERRUPT_VINMI) {
879 interrupt_request |= CPU_INTERRUPT_VIRQ;
880 }
881 if (interrupt_request & CPU_INTERRUPT_VFNMI) {
882 interrupt_request |= CPU_INTERRUPT_VFIQ;
883 }
884 }
885
886 if (interrupt_request & CPU_INTERRUPT_FIQ) {
887 excp_idx = EXCP_FIQ;
888 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
889 if (arm_excp_unmasked(cs, excp_idx, target_el,
890 cur_el, secure, hcr_el2)) {
891 goto found;
892 }
893 }
894 if (interrupt_request & CPU_INTERRUPT_HARD) {
895 excp_idx = EXCP_IRQ;
896 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
897 if (arm_excp_unmasked(cs, excp_idx, target_el,
898 cur_el, secure, hcr_el2)) {
899 goto found;
900 }
901 }
902 if (interrupt_request & CPU_INTERRUPT_VIRQ) {
903 excp_idx = EXCP_VIRQ;
904 target_el = 1;
905 if (arm_excp_unmasked(cs, excp_idx, target_el,
906 cur_el, secure, hcr_el2)) {
907 goto found;
908 }
909 }
910 if (interrupt_request & CPU_INTERRUPT_VFIQ) {
911 excp_idx = EXCP_VFIQ;
912 target_el = 1;
913 if (arm_excp_unmasked(cs, excp_idx, target_el,
914 cur_el, secure, hcr_el2)) {
915 goto found;
916 }
917 }
918 if (interrupt_request & CPU_INTERRUPT_VSERR) {
919 excp_idx = EXCP_VSERR;
920 target_el = 1;
921 if (arm_excp_unmasked(cs, excp_idx, target_el,
922 cur_el, secure, hcr_el2)) {
923 /* Taking a virtual abort clears HCR_EL2.VSE */
924 env->cp15.hcr_el2 &= ~HCR_VSE;
925 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
926 goto found;
927 }
928 }
929 return false;
930
931 found:
932 cs->exception_index = excp_idx;
933 env->exception.target_el = target_el;
934 cs->cc->tcg_ops->do_interrupt(cs);
935 return true;
936 }
937
938 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
939
arm_cpu_update_virq(ARMCPU * cpu)940 void arm_cpu_update_virq(ARMCPU *cpu)
941 {
942 /*
943 * Update the interrupt level for VIRQ, which is the logical OR of
944 * the HCR_EL2.VI bit and the input line level from the GIC.
945 */
946 CPUARMState *env = &cpu->env;
947 CPUState *cs = CPU(cpu);
948
949 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) &&
950 !(arm_hcrx_el2_eff(env) & HCRX_VINMI)) ||
951 (env->irq_line_state & CPU_INTERRUPT_VIRQ);
952
953 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) {
954 if (new_state) {
955 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ);
956 } else {
957 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ);
958 }
959 }
960 }
961
arm_cpu_update_vfiq(ARMCPU * cpu)962 void arm_cpu_update_vfiq(ARMCPU *cpu)
963 {
964 /*
965 * Update the interrupt level for VFIQ, which is the logical OR of
966 * the HCR_EL2.VF bit and the input line level from the GIC.
967 */
968 CPUARMState *env = &cpu->env;
969 CPUState *cs = CPU(cpu);
970
971 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VF) &&
972 !(arm_hcrx_el2_eff(env) & HCRX_VFNMI)) ||
973 (env->irq_line_state & CPU_INTERRUPT_VFIQ);
974
975 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) {
976 if (new_state) {
977 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ);
978 } else {
979 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ);
980 }
981 }
982 }
983
arm_cpu_update_vinmi(ARMCPU * cpu)984 void arm_cpu_update_vinmi(ARMCPU *cpu)
985 {
986 /*
987 * Update the interrupt level for VINMI, which is the logical OR of
988 * the HCRX_EL2.VINMI bit and the input line level from the GIC.
989 */
990 CPUARMState *env = &cpu->env;
991 CPUState *cs = CPU(cpu);
992
993 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) &&
994 (arm_hcrx_el2_eff(env) & HCRX_VINMI)) ||
995 (env->irq_line_state & CPU_INTERRUPT_VINMI);
996
997 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VINMI) != 0)) {
998 if (new_state) {
999 cpu_interrupt(cs, CPU_INTERRUPT_VINMI);
1000 } else {
1001 cpu_reset_interrupt(cs, CPU_INTERRUPT_VINMI);
1002 }
1003 }
1004 }
1005
arm_cpu_update_vfnmi(ARMCPU * cpu)1006 void arm_cpu_update_vfnmi(ARMCPU *cpu)
1007 {
1008 /*
1009 * Update the interrupt level for VFNMI, which is the HCRX_EL2.VFNMI bit.
1010 */
1011 CPUARMState *env = &cpu->env;
1012 CPUState *cs = CPU(cpu);
1013
1014 bool new_state = (arm_hcr_el2_eff(env) & HCR_VF) &&
1015 (arm_hcrx_el2_eff(env) & HCRX_VFNMI);
1016
1017 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFNMI) != 0)) {
1018 if (new_state) {
1019 cpu_interrupt(cs, CPU_INTERRUPT_VFNMI);
1020 } else {
1021 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFNMI);
1022 }
1023 }
1024 }
1025
arm_cpu_update_vserr(ARMCPU * cpu)1026 void arm_cpu_update_vserr(ARMCPU *cpu)
1027 {
1028 /*
1029 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit.
1030 */
1031 CPUARMState *env = &cpu->env;
1032 CPUState *cs = CPU(cpu);
1033
1034 bool new_state = env->cp15.hcr_el2 & HCR_VSE;
1035
1036 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) {
1037 if (new_state) {
1038 cpu_interrupt(cs, CPU_INTERRUPT_VSERR);
1039 } else {
1040 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
1041 }
1042 }
1043 }
1044
1045 #ifndef CONFIG_USER_ONLY
arm_cpu_set_irq(void * opaque,int irq,int level)1046 static void arm_cpu_set_irq(void *opaque, int irq, int level)
1047 {
1048 ARMCPU *cpu = opaque;
1049 CPUARMState *env = &cpu->env;
1050 CPUState *cs = CPU(cpu);
1051 static const int mask[] = {
1052 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
1053 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
1054 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
1055 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ,
1056 [ARM_CPU_NMI] = CPU_INTERRUPT_NMI,
1057 [ARM_CPU_VINMI] = CPU_INTERRUPT_VINMI,
1058 };
1059
1060 if (!arm_feature(env, ARM_FEATURE_EL2) &&
1061 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) {
1062 /*
1063 * The GIC might tell us about VIRQ and VFIQ state, but if we don't
1064 * have EL2 support we don't care. (Unless the guest is doing something
1065 * silly this will only be calls saying "level is still 0".)
1066 */
1067 return;
1068 }
1069
1070 if (level) {
1071 env->irq_line_state |= mask[irq];
1072 } else {
1073 env->irq_line_state &= ~mask[irq];
1074 }
1075
1076 switch (irq) {
1077 case ARM_CPU_VIRQ:
1078 arm_cpu_update_virq(cpu);
1079 break;
1080 case ARM_CPU_VFIQ:
1081 arm_cpu_update_vfiq(cpu);
1082 break;
1083 case ARM_CPU_VINMI:
1084 arm_cpu_update_vinmi(cpu);
1085 break;
1086 case ARM_CPU_IRQ:
1087 case ARM_CPU_FIQ:
1088 case ARM_CPU_NMI:
1089 if (level) {
1090 cpu_interrupt(cs, mask[irq]);
1091 } else {
1092 cpu_reset_interrupt(cs, mask[irq]);
1093 }
1094 break;
1095 default:
1096 g_assert_not_reached();
1097 }
1098 }
1099
arm_cpu_kvm_set_irq(void * opaque,int irq,int level)1100 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
1101 {
1102 #ifdef CONFIG_KVM
1103 ARMCPU *cpu = opaque;
1104 CPUARMState *env = &cpu->env;
1105 CPUState *cs = CPU(cpu);
1106 uint32_t linestate_bit;
1107 int irq_id;
1108
1109 switch (irq) {
1110 case ARM_CPU_IRQ:
1111 irq_id = KVM_ARM_IRQ_CPU_IRQ;
1112 linestate_bit = CPU_INTERRUPT_HARD;
1113 break;
1114 case ARM_CPU_FIQ:
1115 irq_id = KVM_ARM_IRQ_CPU_FIQ;
1116 linestate_bit = CPU_INTERRUPT_FIQ;
1117 break;
1118 default:
1119 g_assert_not_reached();
1120 }
1121
1122 if (level) {
1123 env->irq_line_state |= linestate_bit;
1124 } else {
1125 env->irq_line_state &= ~linestate_bit;
1126 }
1127 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level);
1128 #endif
1129 }
1130
arm_cpu_virtio_is_big_endian(CPUState * cs)1131 static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
1132 {
1133 ARMCPU *cpu = ARM_CPU(cs);
1134 CPUARMState *env = &cpu->env;
1135
1136 cpu_synchronize_state(cs);
1137 return arm_cpu_data_is_big_endian(env);
1138 }
1139
1140 #ifdef CONFIG_TCG
arm_cpu_exec_halt(CPUState * cs)1141 bool arm_cpu_exec_halt(CPUState *cs)
1142 {
1143 bool leave_halt = cpu_has_work(cs);
1144
1145 if (leave_halt) {
1146 /* We're about to come out of WFI/WFE: disable the WFxT timer */
1147 ARMCPU *cpu = ARM_CPU(cs);
1148 if (cpu->wfxt_timer) {
1149 timer_del(cpu->wfxt_timer);
1150 }
1151 }
1152 return leave_halt;
1153 }
1154 #endif
1155
arm_wfxt_timer_cb(void * opaque)1156 static void arm_wfxt_timer_cb(void *opaque)
1157 {
1158 ARMCPU *cpu = opaque;
1159 CPUState *cs = CPU(cpu);
1160
1161 /*
1162 * We expect the CPU to be halted; this will cause arm_cpu_is_work()
1163 * to return true (so we will come out of halt even with no other
1164 * pending interrupt), and the TCG accelerator's cpu_exec_interrupt()
1165 * function auto-clears the CPU_INTERRUPT_EXITTB flag for us.
1166 */
1167 cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
1168 }
1169 #endif
1170
arm_disas_set_info(CPUState * cpu,disassemble_info * info)1171 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
1172 {
1173 ARMCPU *ac = ARM_CPU(cpu);
1174 CPUARMState *env = &ac->env;
1175 bool sctlr_b = arm_sctlr_b(env);
1176
1177 if (is_a64(env)) {
1178 info->cap_arch = CS_ARCH_ARM64;
1179 info->cap_insn_unit = 4;
1180 info->cap_insn_split = 4;
1181 } else {
1182 int cap_mode;
1183 if (env->thumb) {
1184 info->cap_insn_unit = 2;
1185 info->cap_insn_split = 4;
1186 cap_mode = CS_MODE_THUMB;
1187 } else {
1188 info->cap_insn_unit = 4;
1189 info->cap_insn_split = 4;
1190 cap_mode = CS_MODE_ARM;
1191 }
1192 if (arm_feature(env, ARM_FEATURE_V8)) {
1193 cap_mode |= CS_MODE_V8;
1194 }
1195 if (arm_feature(env, ARM_FEATURE_M)) {
1196 cap_mode |= CS_MODE_MCLASS;
1197 }
1198 info->cap_arch = CS_ARCH_ARM;
1199 info->cap_mode = cap_mode;
1200 }
1201
1202 info->endian = BFD_ENDIAN_LITTLE;
1203 if (bswap_code(sctlr_b)) {
1204 info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
1205 }
1206 info->flags &= ~INSN_ARM_BE32;
1207 #ifndef CONFIG_USER_ONLY
1208 if (sctlr_b) {
1209 info->flags |= INSN_ARM_BE32;
1210 }
1211 #endif
1212 }
1213
1214 #ifdef TARGET_AARCH64
1215
aarch64_cpu_dump_state(CPUState * cs,FILE * f,int flags)1216 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
1217 {
1218 ARMCPU *cpu = ARM_CPU(cs);
1219 CPUARMState *env = &cpu->env;
1220 uint32_t psr = pstate_read(env);
1221 int i, j;
1222 int el = arm_current_el(env);
1223 uint64_t hcr = arm_hcr_el2_eff(env);
1224 const char *ns_status;
1225 bool sve;
1226
1227 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
1228 for (i = 0; i < 32; i++) {
1229 if (i == 31) {
1230 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
1231 } else {
1232 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
1233 (i + 2) % 3 ? " " : "\n");
1234 }
1235 }
1236
1237 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
1238 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
1239 } else {
1240 ns_status = "";
1241 }
1242 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
1243 psr,
1244 psr & PSTATE_N ? 'N' : '-',
1245 psr & PSTATE_Z ? 'Z' : '-',
1246 psr & PSTATE_C ? 'C' : '-',
1247 psr & PSTATE_V ? 'V' : '-',
1248 ns_status,
1249 el,
1250 psr & PSTATE_SP ? 'h' : 't');
1251
1252 if (cpu_isar_feature(aa64_sme, cpu)) {
1253 qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c",
1254 env->svcr,
1255 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'),
1256 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-'));
1257 }
1258 if (cpu_isar_feature(aa64_bti, cpu)) {
1259 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
1260 }
1261 qemu_fprintf(f, "%s%s%s",
1262 (hcr & HCR_NV) ? " NV" : "",
1263 (hcr & HCR_NV1) ? " NV1" : "",
1264 (hcr & HCR_NV2) ? " NV2" : "");
1265 if (!(flags & CPU_DUMP_FPU)) {
1266 qemu_fprintf(f, "\n");
1267 return;
1268 }
1269 if (fp_exception_el(env, el) != 0) {
1270 qemu_fprintf(f, " FPU disabled\n");
1271 return;
1272 }
1273 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
1274 vfp_get_fpcr(env), vfp_get_fpsr(env));
1275
1276 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) {
1277 sve = sme_exception_el(env, el) == 0;
1278 } else if (cpu_isar_feature(aa64_sve, cpu)) {
1279 sve = sve_exception_el(env, el) == 0;
1280 } else {
1281 sve = false;
1282 }
1283
1284 if (sve) {
1285 int zcr_len = sve_vqm1_for_el(env, el);
1286
1287 for (i = 0; i <= FFR_PRED_NUM; i++) {
1288 bool eol;
1289 if (i == FFR_PRED_NUM) {
1290 qemu_fprintf(f, "FFR=");
1291 /* It's last, so end the line. */
1292 eol = true;
1293 } else {
1294 qemu_fprintf(f, "P%02d=", i);
1295 switch (zcr_len) {
1296 case 0:
1297 eol = i % 8 == 7;
1298 break;
1299 case 1:
1300 eol = i % 6 == 5;
1301 break;
1302 case 2:
1303 case 3:
1304 eol = i % 3 == 2;
1305 break;
1306 default:
1307 /* More than one quadword per predicate. */
1308 eol = true;
1309 break;
1310 }
1311 }
1312 for (j = zcr_len / 4; j >= 0; j--) {
1313 int digits;
1314 if (j * 4 + 4 <= zcr_len + 1) {
1315 digits = 16;
1316 } else {
1317 digits = (zcr_len % 4 + 1) * 4;
1318 }
1319 qemu_fprintf(f, "%0*" PRIx64 "%s", digits,
1320 env->vfp.pregs[i].p[j],
1321 j ? ":" : eol ? "\n" : " ");
1322 }
1323 }
1324
1325 if (zcr_len == 0) {
1326 /*
1327 * With vl=16, there are only 37 columns per register,
1328 * so output two registers per line.
1329 */
1330 for (i = 0; i < 32; i++) {
1331 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
1332 i, env->vfp.zregs[i].d[1],
1333 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
1334 }
1335 } else {
1336 for (i = 0; i < 32; i++) {
1337 qemu_fprintf(f, "Z%02d=", i);
1338 for (j = zcr_len; j >= 0; j--) {
1339 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
1340 env->vfp.zregs[i].d[j * 2 + 1],
1341 env->vfp.zregs[i].d[j * 2 + 0],
1342 j ? ":" : "\n");
1343 }
1344 }
1345 }
1346 } else {
1347 for (i = 0; i < 32; i++) {
1348 uint64_t *q = aa64_vfp_qreg(env, i);
1349 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
1350 i, q[1], q[0], (i & 1 ? "\n" : " "));
1351 }
1352 }
1353
1354 if (cpu_isar_feature(aa64_sme, cpu) &&
1355 FIELD_EX64(env->svcr, SVCR, ZA) &&
1356 sme_exception_el(env, el) == 0) {
1357 int zcr_len = sve_vqm1_for_el_sm(env, el, true);
1358 int svl = (zcr_len + 1) * 16;
1359 int svl_lg10 = svl < 100 ? 2 : 3;
1360
1361 for (i = 0; i < svl; i++) {
1362 qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i);
1363 for (j = zcr_len; j >= 0; --j) {
1364 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c",
1365 env->zarray[i].d[2 * j + 1],
1366 env->zarray[i].d[2 * j],
1367 j ? ':' : '\n');
1368 }
1369 }
1370 }
1371 }
1372
1373 #else
1374
aarch64_cpu_dump_state(CPUState * cs,FILE * f,int flags)1375 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
1376 {
1377 g_assert_not_reached();
1378 }
1379
1380 #endif
1381
arm_cpu_dump_state(CPUState * cs,FILE * f,int flags)1382 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
1383 {
1384 ARMCPU *cpu = ARM_CPU(cs);
1385 CPUARMState *env = &cpu->env;
1386 int i;
1387
1388 if (is_a64(env)) {
1389 aarch64_cpu_dump_state(cs, f, flags);
1390 return;
1391 }
1392
1393 for (i = 0; i < 16; i++) {
1394 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
1395 if ((i % 4) == 3) {
1396 qemu_fprintf(f, "\n");
1397 } else {
1398 qemu_fprintf(f, " ");
1399 }
1400 }
1401
1402 if (arm_feature(env, ARM_FEATURE_M)) {
1403 uint32_t xpsr = xpsr_read(env);
1404 const char *mode;
1405 const char *ns_status = "";
1406
1407 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1408 ns_status = env->v7m.secure ? "S " : "NS ";
1409 }
1410
1411 if (xpsr & XPSR_EXCP) {
1412 mode = "handler";
1413 } else {
1414 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
1415 mode = "unpriv-thread";
1416 } else {
1417 mode = "priv-thread";
1418 }
1419 }
1420
1421 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
1422 xpsr,
1423 xpsr & XPSR_N ? 'N' : '-',
1424 xpsr & XPSR_Z ? 'Z' : '-',
1425 xpsr & XPSR_C ? 'C' : '-',
1426 xpsr & XPSR_V ? 'V' : '-',
1427 xpsr & XPSR_T ? 'T' : 'A',
1428 ns_status,
1429 mode);
1430 } else {
1431 uint32_t psr = cpsr_read(env);
1432 const char *ns_status = "";
1433
1434 if (arm_feature(env, ARM_FEATURE_EL3) &&
1435 (psr & CPSR_M) != ARM_CPU_MODE_MON) {
1436 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
1437 }
1438
1439 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
1440 psr,
1441 psr & CPSR_N ? 'N' : '-',
1442 psr & CPSR_Z ? 'Z' : '-',
1443 psr & CPSR_C ? 'C' : '-',
1444 psr & CPSR_V ? 'V' : '-',
1445 psr & CPSR_T ? 'T' : 'A',
1446 ns_status,
1447 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
1448 }
1449
1450 if (flags & CPU_DUMP_FPU) {
1451 int numvfpregs = 0;
1452 if (cpu_isar_feature(aa32_simd_r32, cpu)) {
1453 numvfpregs = 32;
1454 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
1455 numvfpregs = 16;
1456 }
1457 for (i = 0; i < numvfpregs; i++) {
1458 uint64_t v = *aa32_vfp_dreg(env, i);
1459 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
1460 i * 2, (uint32_t)v,
1461 i * 2 + 1, (uint32_t)(v >> 32),
1462 i, v);
1463 }
1464 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
1465 if (cpu_isar_feature(aa32_mve, cpu)) {
1466 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr);
1467 }
1468 }
1469 }
1470
arm_build_mp_affinity(int idx,uint8_t clustersz)1471 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz)
1472 {
1473 uint32_t Aff1 = idx / clustersz;
1474 uint32_t Aff0 = idx % clustersz;
1475 return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
1476 }
1477
arm_cpu_mp_affinity(ARMCPU * cpu)1478 uint64_t arm_cpu_mp_affinity(ARMCPU *cpu)
1479 {
1480 return cpu->mp_affinity;
1481 }
1482
arm_cpu_initfn(Object * obj)1483 static void arm_cpu_initfn(Object *obj)
1484 {
1485 ARMCPU *cpu = ARM_CPU(obj);
1486
1487 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal,
1488 NULL, g_free);
1489
1490 QLIST_INIT(&cpu->pre_el_change_hooks);
1491 QLIST_INIT(&cpu->el_change_hooks);
1492
1493 #ifdef CONFIG_USER_ONLY
1494 # ifdef TARGET_AARCH64
1495 /*
1496 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME.
1497 * These values were chosen to fit within the default signal frame.
1498 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length,
1499 * and our corresponding cpu property.
1500 */
1501 cpu->sve_default_vq = 4;
1502 cpu->sme_default_vq = 2;
1503 # endif
1504 #else
1505 /* Our inbound IRQ and FIQ lines */
1506 if (kvm_enabled()) {
1507 /*
1508 * VIRQ, VFIQ, NMI, VINMI are unused with KVM but we add
1509 * them to maintain the same interface as non-KVM CPUs.
1510 */
1511 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 6);
1512 } else {
1513 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 6);
1514 }
1515
1516 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
1517 ARRAY_SIZE(cpu->gt_timer_outputs));
1518
1519 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
1520 "gicv3-maintenance-interrupt", 1);
1521 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,
1522 "pmu-interrupt", 1);
1523 #endif
1524
1525 /* DTB consumers generally don't in fact care what the 'compatible'
1526 * string is, so always provide some string and trust that a hypothetical
1527 * picky DTB consumer will also provide a helpful error message.
1528 */
1529 cpu->dtb_compatible = "qemu,unknown";
1530 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */
1531 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
1532
1533 if (tcg_enabled() || hvf_enabled()) {
1534 /* TCG and HVF implement PSCI 1.1 */
1535 cpu->psci_version = QEMU_PSCI_VERSION_1_1;
1536 }
1537 }
1538
1539 /*
1540 * 0 means "unset, use the default value". That default might vary depending
1541 * on the CPU type, and is set in the realize fn.
1542 */
1543 static const Property arm_cpu_gt_cntfrq_property =
1544 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 0);
1545
1546 static const Property arm_cpu_reset_cbar_property =
1547 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
1548
1549 static const Property arm_cpu_reset_hivecs_property =
1550 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
1551
1552 #ifndef CONFIG_USER_ONLY
1553 static const Property arm_cpu_has_el2_property =
1554 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
1555
1556 static const Property arm_cpu_has_el3_property =
1557 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
1558 #endif
1559
1560 static const Property arm_cpu_cfgend_property =
1561 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
1562
1563 static const Property arm_cpu_has_vfp_property =
1564 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
1565
1566 static const Property arm_cpu_has_vfp_d32_property =
1567 DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true);
1568
1569 static const Property arm_cpu_has_neon_property =
1570 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true);
1571
1572 static const Property arm_cpu_has_dsp_property =
1573 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true);
1574
1575 static const Property arm_cpu_has_mpu_property =
1576 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
1577
1578 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1579 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1580 * the right value for that particular CPU type, and we don't want
1581 * to override that with an incorrect constant value.
1582 */
1583 static const Property arm_cpu_pmsav7_dregion_property =
1584 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU,
1585 pmsav7_dregion,
1586 qdev_prop_uint32, uint32_t);
1587
arm_get_pmu(Object * obj,Error ** errp)1588 static bool arm_get_pmu(Object *obj, Error **errp)
1589 {
1590 ARMCPU *cpu = ARM_CPU(obj);
1591
1592 return cpu->has_pmu;
1593 }
1594
arm_set_pmu(Object * obj,bool value,Error ** errp)1595 static void arm_set_pmu(Object *obj, bool value, Error **errp)
1596 {
1597 ARMCPU *cpu = ARM_CPU(obj);
1598
1599 if (value) {
1600 if (kvm_enabled() && !kvm_arm_pmu_supported()) {
1601 error_setg(errp, "'pmu' feature not supported by KVM on this host");
1602 return;
1603 }
1604 set_feature(&cpu->env, ARM_FEATURE_PMU);
1605 } else {
1606 unset_feature(&cpu->env, ARM_FEATURE_PMU);
1607 }
1608 cpu->has_pmu = value;
1609 }
1610
gt_cntfrq_period_ns(ARMCPU * cpu)1611 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
1612 {
1613 /*
1614 * The exact approach to calculating guest ticks is:
1615 *
1616 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1617 * NANOSECONDS_PER_SECOND);
1618 *
1619 * We don't do that. Rather we intentionally use integer division
1620 * truncation below and in the caller for the conversion of host monotonic
1621 * time to guest ticks to provide the exact inverse for the semantics of
1622 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1623 * it loses precision when representing frequencies where
1624 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1625 * provide an exact inverse leads to scheduling timers with negative
1626 * periods, which in turn leads to sticky behaviour in the guest.
1627 *
1628 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1629 * cannot become zero.
1630 */
1631 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ?
1632 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
1633 }
1634
arm_cpu_propagate_feature_implications(ARMCPU * cpu)1635 static void arm_cpu_propagate_feature_implications(ARMCPU *cpu)
1636 {
1637 CPUARMState *env = &cpu->env;
1638 bool no_aa32 = false;
1639
1640 /*
1641 * Some features automatically imply others: set the feature
1642 * bits explicitly for these cases.
1643 */
1644
1645 if (arm_feature(env, ARM_FEATURE_M)) {
1646 set_feature(env, ARM_FEATURE_PMSA);
1647 }
1648
1649 if (arm_feature(env, ARM_FEATURE_V8)) {
1650 if (arm_feature(env, ARM_FEATURE_M)) {
1651 set_feature(env, ARM_FEATURE_V7);
1652 } else {
1653 set_feature(env, ARM_FEATURE_V7VE);
1654 }
1655 }
1656
1657 /*
1658 * There exist AArch64 cpus without AArch32 support. When KVM
1659 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1660 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1661 * As a general principle, we also do not make ID register
1662 * consistency checks anywhere unless using TCG, because only
1663 * for TCG would a consistency-check failure be a QEMU bug.
1664 */
1665 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1666 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
1667 }
1668
1669 if (arm_feature(env, ARM_FEATURE_V7VE)) {
1670 /*
1671 * v7 Virtualization Extensions. In real hardware this implies
1672 * EL2 and also the presence of the Security Extensions.
1673 * For QEMU, for backwards-compatibility we implement some
1674 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1675 * include the various other features that V7VE implies.
1676 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1677 * Security Extensions is ARM_FEATURE_EL3.
1678 */
1679 assert(!tcg_enabled() || no_aa32 ||
1680 cpu_isar_feature(aa32_arm_div, cpu));
1681 set_feature(env, ARM_FEATURE_LPAE);
1682 set_feature(env, ARM_FEATURE_V7);
1683 }
1684 if (arm_feature(env, ARM_FEATURE_V7)) {
1685 set_feature(env, ARM_FEATURE_VAPA);
1686 set_feature(env, ARM_FEATURE_THUMB2);
1687 set_feature(env, ARM_FEATURE_MPIDR);
1688 if (!arm_feature(env, ARM_FEATURE_M)) {
1689 set_feature(env, ARM_FEATURE_V6K);
1690 } else {
1691 set_feature(env, ARM_FEATURE_V6);
1692 }
1693
1694 /*
1695 * Always define VBAR for V7 CPUs even if it doesn't exist in
1696 * non-EL3 configs. This is needed by some legacy boards.
1697 */
1698 set_feature(env, ARM_FEATURE_VBAR);
1699 }
1700 if (arm_feature(env, ARM_FEATURE_V6K)) {
1701 set_feature(env, ARM_FEATURE_V6);
1702 set_feature(env, ARM_FEATURE_MVFR);
1703 }
1704 if (arm_feature(env, ARM_FEATURE_V6)) {
1705 set_feature(env, ARM_FEATURE_V5);
1706 if (!arm_feature(env, ARM_FEATURE_M)) {
1707 assert(!tcg_enabled() || no_aa32 ||
1708 cpu_isar_feature(aa32_jazelle, cpu));
1709 set_feature(env, ARM_FEATURE_AUXCR);
1710 }
1711 }
1712 if (arm_feature(env, ARM_FEATURE_V5)) {
1713 set_feature(env, ARM_FEATURE_V4T);
1714 }
1715 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1716 set_feature(env, ARM_FEATURE_V7MP);
1717 }
1718 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
1719 set_feature(env, ARM_FEATURE_CBAR);
1720 }
1721 if (arm_feature(env, ARM_FEATURE_THUMB2) &&
1722 !arm_feature(env, ARM_FEATURE_M)) {
1723 set_feature(env, ARM_FEATURE_THUMB_DSP);
1724 }
1725 }
1726
arm_cpu_post_init(Object * obj)1727 void arm_cpu_post_init(Object *obj)
1728 {
1729 ARMCPU *cpu = ARM_CPU(obj);
1730
1731 /*
1732 * Some features imply others. Figure this out now, because we
1733 * are going to look at the feature bits in deciding which
1734 * properties to add.
1735 */
1736 arm_cpu_propagate_feature_implications(cpu);
1737
1738 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
1739 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
1740 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property);
1741 }
1742
1743 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
1744 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property);
1745 }
1746
1747 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1748 object_property_add_uint64_ptr(obj, "rvbar",
1749 &cpu->rvbar_prop,
1750 OBJ_PROP_FLAG_READWRITE);
1751 }
1752
1753 #ifndef CONFIG_USER_ONLY
1754 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
1755 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1756 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1757 */
1758 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property);
1759
1760 object_property_add_link(obj, "secure-memory",
1761 TYPE_MEMORY_REGION,
1762 (Object **)&cpu->secure_memory,
1763 qdev_prop_allow_set_link_before_realize,
1764 OBJ_PROP_LINK_STRONG);
1765 }
1766
1767 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
1768 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property);
1769 }
1770 #endif
1771
1772 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
1773 cpu->has_pmu = true;
1774 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu);
1775 }
1776
1777 /*
1778 * Allow user to turn off VFP and Neon support, but only for TCG --
1779 * KVM does not currently allow us to lie to the guest about its
1780 * ID/feature registers, so the guest always sees what the host has.
1781 */
1782 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1783 if (cpu_isar_feature(aa64_fp_simd, cpu)) {
1784 cpu->has_vfp = true;
1785 cpu->has_vfp_d32 = true;
1786 if (tcg_enabled() || qtest_enabled()) {
1787 qdev_property_add_static(DEVICE(obj),
1788 &arm_cpu_has_vfp_property);
1789 }
1790 }
1791 } else if (cpu_isar_feature(aa32_vfp, cpu)) {
1792 cpu->has_vfp = true;
1793 if (tcg_enabled() || qtest_enabled()) {
1794 qdev_property_add_static(DEVICE(obj),
1795 &arm_cpu_has_vfp_property);
1796 }
1797 if (cpu_isar_feature(aa32_simd_r32, cpu)) {
1798 cpu->has_vfp_d32 = true;
1799 /*
1800 * The permitted values of the SIMDReg bits [3:0] on
1801 * Armv8-A are either 0b0000 and 0b0010. On such CPUs,
1802 * make sure that has_vfp_d32 can not be set to false.
1803 */
1804 if ((tcg_enabled() || qtest_enabled())
1805 && !(arm_feature(&cpu->env, ARM_FEATURE_V8)
1806 && !arm_feature(&cpu->env, ARM_FEATURE_M))) {
1807 qdev_property_add_static(DEVICE(obj),
1808 &arm_cpu_has_vfp_d32_property);
1809 }
1810 }
1811 }
1812
1813 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) {
1814 cpu->has_neon = true;
1815 if (!kvm_enabled()) {
1816 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property);
1817 }
1818 }
1819
1820 if (arm_feature(&cpu->env, ARM_FEATURE_M) &&
1821 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) {
1822 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property);
1823 }
1824
1825 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
1826 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property);
1827 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1828 qdev_property_add_static(DEVICE(obj),
1829 &arm_cpu_pmsav7_dregion_property);
1830 }
1831 }
1832
1833 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) {
1834 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau,
1835 qdev_prop_allow_set_link_before_realize,
1836 OBJ_PROP_LINK_STRONG);
1837 /*
1838 * M profile: initial value of the Secure VTOR. We can't just use
1839 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1840 * the property to be set after realize.
1841 */
1842 object_property_add_uint32_ptr(obj, "init-svtor",
1843 &cpu->init_svtor,
1844 OBJ_PROP_FLAG_READWRITE);
1845 }
1846 if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
1847 /*
1848 * Initial value of the NS VTOR (for cores without the Security
1849 * extension, this is the only VTOR)
1850 */
1851 object_property_add_uint32_ptr(obj, "init-nsvtor",
1852 &cpu->init_nsvtor,
1853 OBJ_PROP_FLAG_READWRITE);
1854 }
1855
1856 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */
1857 object_property_add_uint32_ptr(obj, "psci-conduit",
1858 &cpu->psci_conduit,
1859 OBJ_PROP_FLAG_READWRITE);
1860
1861 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property);
1862
1863 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) {
1864 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property);
1865 }
1866
1867 if (kvm_enabled()) {
1868 kvm_arm_add_vcpu_properties(cpu);
1869 }
1870
1871 #ifndef CONFIG_USER_ONLY
1872 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) &&
1873 cpu_isar_feature(aa64_mte, cpu)) {
1874 object_property_add_link(obj, "tag-memory",
1875 TYPE_MEMORY_REGION,
1876 (Object **)&cpu->tag_memory,
1877 qdev_prop_allow_set_link_before_realize,
1878 OBJ_PROP_LINK_STRONG);
1879
1880 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
1881 object_property_add_link(obj, "secure-tag-memory",
1882 TYPE_MEMORY_REGION,
1883 (Object **)&cpu->secure_tag_memory,
1884 qdev_prop_allow_set_link_before_realize,
1885 OBJ_PROP_LINK_STRONG);
1886 }
1887 }
1888 #endif
1889 }
1890
arm_cpu_finalizefn(Object * obj)1891 static void arm_cpu_finalizefn(Object *obj)
1892 {
1893 ARMCPU *cpu = ARM_CPU(obj);
1894 ARMELChangeHook *hook, *next;
1895
1896 g_hash_table_destroy(cpu->cp_regs);
1897
1898 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
1899 QLIST_REMOVE(hook, node);
1900 g_free(hook);
1901 }
1902 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
1903 QLIST_REMOVE(hook, node);
1904 g_free(hook);
1905 }
1906 #ifndef CONFIG_USER_ONLY
1907 if (cpu->pmu_timer) {
1908 timer_free(cpu->pmu_timer);
1909 }
1910 if (cpu->wfxt_timer) {
1911 timer_free(cpu->wfxt_timer);
1912 }
1913 #endif
1914 }
1915
arm_cpu_finalize_features(ARMCPU * cpu,Error ** errp)1916 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
1917 {
1918 Error *local_err = NULL;
1919
1920 #ifdef TARGET_AARCH64
1921 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1922 arm_cpu_sve_finalize(cpu, &local_err);
1923 if (local_err != NULL) {
1924 error_propagate(errp, local_err);
1925 return;
1926 }
1927
1928 /*
1929 * FEAT_SME is not architecturally dependent on FEAT_SVE (unless
1930 * FEAT_SME_FA64 is present). However our implementation currently
1931 * assumes it, so if the user asked for sve=off then turn off SME also.
1932 * (KVM doesn't currently support SME at all.)
1933 */
1934 if (cpu_isar_feature(aa64_sme, cpu) && !cpu_isar_feature(aa64_sve, cpu)) {
1935 object_property_set_bool(OBJECT(cpu), "sme", false, &error_abort);
1936 }
1937
1938 arm_cpu_sme_finalize(cpu, &local_err);
1939 if (local_err != NULL) {
1940 error_propagate(errp, local_err);
1941 return;
1942 }
1943
1944 arm_cpu_pauth_finalize(cpu, &local_err);
1945 if (local_err != NULL) {
1946 error_propagate(errp, local_err);
1947 return;
1948 }
1949
1950 arm_cpu_lpa2_finalize(cpu, &local_err);
1951 if (local_err != NULL) {
1952 error_propagate(errp, local_err);
1953 return;
1954 }
1955 }
1956 #endif
1957
1958 if (kvm_enabled()) {
1959 kvm_arm_steal_time_finalize(cpu, &local_err);
1960 if (local_err != NULL) {
1961 error_propagate(errp, local_err);
1962 return;
1963 }
1964 }
1965 }
1966
arm_cpu_realizefn(DeviceState * dev,Error ** errp)1967 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
1968 {
1969 CPUState *cs = CPU(dev);
1970 ARMCPU *cpu = ARM_CPU(dev);
1971 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
1972 CPUARMState *env = &cpu->env;
1973 Error *local_err = NULL;
1974
1975 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
1976 /* Use pc-relative instructions in system-mode */
1977 tcg_cflags_set(cs, CF_PCREL);
1978 #endif
1979
1980 /* If we needed to query the host kernel for the CPU features
1981 * then it's possible that might have failed in the initfn, but
1982 * this is the first point where we can report it.
1983 */
1984 if (cpu->host_cpu_probe_failed) {
1985 if (!kvm_enabled() && !hvf_enabled()) {
1986 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF");
1987 } else {
1988 error_setg(errp, "Failed to retrieve host CPU features");
1989 }
1990 return;
1991 }
1992
1993 if (!cpu->gt_cntfrq_hz) {
1994 /*
1995 * 0 means "the board didn't set a value, use the default". (We also
1996 * get here for the CONFIG_USER_ONLY case.)
1997 * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before
1998 * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz,
1999 * which gives a 16ns tick period.
2000 *
2001 * We will use the back-compat value:
2002 * - for QEMU CPU types added before we standardized on 1GHz
2003 * - for versioned machine types with a version of 9.0 or earlier
2004 */
2005 if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) ||
2006 cpu->backcompat_cntfrq) {
2007 cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ;
2008 } else {
2009 cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
2010 }
2011 }
2012
2013 #ifndef CONFIG_USER_ONLY
2014 /* The NVIC and M-profile CPU are two halves of a single piece of
2015 * hardware; trying to use one without the other is a command line
2016 * error and will result in segfaults if not caught here.
2017 */
2018 if (arm_feature(env, ARM_FEATURE_M)) {
2019 if (!env->nvic) {
2020 error_setg(errp, "This board cannot be used with Cortex-M CPUs");
2021 return;
2022 }
2023 } else {
2024 if (env->nvic) {
2025 error_setg(errp, "This board can only be used with Cortex-M CPUs");
2026 return;
2027 }
2028 }
2029
2030 if (!tcg_enabled() && !qtest_enabled()) {
2031 /*
2032 * We assume that no accelerator except TCG (and the "not really an
2033 * accelerator" qtest) can handle these features, because Arm hardware
2034 * virtualization can't virtualize them.
2035 *
2036 * Catch all the cases which might cause us to create more than one
2037 * address space for the CPU (otherwise we will assert() later in
2038 * cpu_address_space_init()).
2039 */
2040 if (arm_feature(env, ARM_FEATURE_M)) {
2041 error_setg(errp,
2042 "Cannot enable %s when using an M-profile guest CPU",
2043 current_accel_name());
2044 return;
2045 }
2046 if (cpu->has_el3) {
2047 error_setg(errp,
2048 "Cannot enable %s when guest CPU has EL3 enabled",
2049 current_accel_name());
2050 return;
2051 }
2052 if (cpu->tag_memory) {
2053 error_setg(errp,
2054 "Cannot enable %s when guest CPUs has MTE enabled",
2055 current_accel_name());
2056 return;
2057 }
2058 }
2059
2060 {
2061 uint64_t scale = gt_cntfrq_period_ns(cpu);
2062
2063 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
2064 arm_gt_ptimer_cb, cpu);
2065 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
2066 arm_gt_vtimer_cb, cpu);
2067 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
2068 arm_gt_htimer_cb, cpu);
2069 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
2070 arm_gt_stimer_cb, cpu);
2071 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
2072 arm_gt_hvtimer_cb, cpu);
2073 cpu->gt_timer[GTIMER_S_EL2_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
2074 arm_gt_sel2timer_cb, cpu);
2075 cpu->gt_timer[GTIMER_S_EL2_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
2076 arm_gt_sel2vtimer_cb, cpu);
2077 }
2078 #endif
2079
2080 cpu_exec_realizefn(cs, &local_err);
2081 if (local_err != NULL) {
2082 error_propagate(errp, local_err);
2083 return;
2084 }
2085
2086 arm_cpu_finalize_features(cpu, &local_err);
2087 if (local_err != NULL) {
2088 error_propagate(errp, local_err);
2089 return;
2090 }
2091
2092 #ifdef CONFIG_USER_ONLY
2093 /*
2094 * User mode relies on IC IVAU instructions to catch modification of
2095 * dual-mapped code.
2096 *
2097 * Clear CTR_EL0.DIC to ensure that software that honors these flags uses
2098 * IC IVAU even if the emulated processor does not normally require it.
2099 */
2100 cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0);
2101 #endif
2102
2103 if (arm_feature(env, ARM_FEATURE_AARCH64) &&
2104 cpu->has_vfp != cpu->has_neon) {
2105 /*
2106 * This is an architectural requirement for AArch64; AArch32 is
2107 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
2108 */
2109 error_setg(errp,
2110 "AArch64 CPUs must have both VFP and Neon or neither");
2111 return;
2112 }
2113
2114 if (cpu->has_vfp_d32 != cpu->has_neon) {
2115 error_setg(errp, "ARM CPUs must have both VFP-D32 and Neon or neither");
2116 return;
2117 }
2118
2119 if (!cpu->has_vfp_d32) {
2120 uint32_t u;
2121
2122 u = cpu->isar.mvfr0;
2123 u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */
2124 cpu->isar.mvfr0 = u;
2125 }
2126
2127 if (!cpu->has_vfp) {
2128 uint64_t t;
2129 uint32_t u;
2130
2131 t = cpu->isar.id_aa64isar1;
2132 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0);
2133 cpu->isar.id_aa64isar1 = t;
2134
2135 t = cpu->isar.id_aa64pfr0;
2136 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf);
2137 cpu->isar.id_aa64pfr0 = t;
2138
2139 u = cpu->isar.id_isar6;
2140 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0);
2141 u = FIELD_DP32(u, ID_ISAR6, BF16, 0);
2142 cpu->isar.id_isar6 = u;
2143
2144 u = cpu->isar.mvfr0;
2145 u = FIELD_DP32(u, MVFR0, FPSP, 0);
2146 u = FIELD_DP32(u, MVFR0, FPDP, 0);
2147 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0);
2148 u = FIELD_DP32(u, MVFR0, FPSQRT, 0);
2149 u = FIELD_DP32(u, MVFR0, FPROUND, 0);
2150 if (!arm_feature(env, ARM_FEATURE_M)) {
2151 u = FIELD_DP32(u, MVFR0, FPTRAP, 0);
2152 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0);
2153 }
2154 cpu->isar.mvfr0 = u;
2155
2156 u = cpu->isar.mvfr1;
2157 u = FIELD_DP32(u, MVFR1, FPFTZ, 0);
2158 u = FIELD_DP32(u, MVFR1, FPDNAN, 0);
2159 u = FIELD_DP32(u, MVFR1, FPHP, 0);
2160 if (arm_feature(env, ARM_FEATURE_M)) {
2161 u = FIELD_DP32(u, MVFR1, FP16, 0);
2162 }
2163 cpu->isar.mvfr1 = u;
2164
2165 u = cpu->isar.mvfr2;
2166 u = FIELD_DP32(u, MVFR2, FPMISC, 0);
2167 cpu->isar.mvfr2 = u;
2168 }
2169
2170 if (!cpu->has_neon) {
2171 uint64_t t;
2172 uint32_t u;
2173
2174 unset_feature(env, ARM_FEATURE_NEON);
2175
2176 t = cpu->isar.id_aa64isar0;
2177 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0);
2178 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0);
2179 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0);
2180 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0);
2181 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0);
2182 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0);
2183 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
2184 cpu->isar.id_aa64isar0 = t;
2185
2186 t = cpu->isar.id_aa64isar1;
2187 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0);
2188 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0);
2189 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0);
2190 cpu->isar.id_aa64isar1 = t;
2191
2192 t = cpu->isar.id_aa64pfr0;
2193 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf);
2194 cpu->isar.id_aa64pfr0 = t;
2195
2196 u = cpu->isar.id_isar5;
2197 u = FIELD_DP32(u, ID_ISAR5, AES, 0);
2198 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0);
2199 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0);
2200 u = FIELD_DP32(u, ID_ISAR5, RDM, 0);
2201 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0);
2202 cpu->isar.id_isar5 = u;
2203
2204 u = cpu->isar.id_isar6;
2205 u = FIELD_DP32(u, ID_ISAR6, DP, 0);
2206 u = FIELD_DP32(u, ID_ISAR6, FHM, 0);
2207 u = FIELD_DP32(u, ID_ISAR6, BF16, 0);
2208 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0);
2209 cpu->isar.id_isar6 = u;
2210
2211 if (!arm_feature(env, ARM_FEATURE_M)) {
2212 u = cpu->isar.mvfr1;
2213 u = FIELD_DP32(u, MVFR1, SIMDLS, 0);
2214 u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
2215 u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
2216 u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
2217 cpu->isar.mvfr1 = u;
2218
2219 u = cpu->isar.mvfr2;
2220 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0);
2221 cpu->isar.mvfr2 = u;
2222 }
2223 }
2224
2225 if (!cpu->has_neon && !cpu->has_vfp) {
2226 uint64_t t;
2227 uint32_t u;
2228
2229 t = cpu->isar.id_aa64isar0;
2230 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0);
2231 cpu->isar.id_aa64isar0 = t;
2232
2233 t = cpu->isar.id_aa64isar1;
2234 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0);
2235 cpu->isar.id_aa64isar1 = t;
2236
2237 u = cpu->isar.mvfr0;
2238 u = FIELD_DP32(u, MVFR0, SIMDREG, 0);
2239 cpu->isar.mvfr0 = u;
2240
2241 /* Despite the name, this field covers both VFP and Neon */
2242 u = cpu->isar.mvfr1;
2243 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0);
2244 cpu->isar.mvfr1 = u;
2245 }
2246
2247 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) {
2248 uint32_t u;
2249
2250 unset_feature(env, ARM_FEATURE_THUMB_DSP);
2251
2252 u = cpu->isar.id_isar1;
2253 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1);
2254 cpu->isar.id_isar1 = u;
2255
2256 u = cpu->isar.id_isar2;
2257 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1);
2258 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1);
2259 cpu->isar.id_isar2 = u;
2260
2261 u = cpu->isar.id_isar3;
2262 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1);
2263 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0);
2264 cpu->isar.id_isar3 = u;
2265 }
2266
2267
2268 /*
2269 * We rely on no XScale CPU having VFP so we can use the same bits in the
2270 * TB flags field for VECSTRIDE and XSCALE_CPAR.
2271 */
2272 assert(arm_feature(env, ARM_FEATURE_AARCH64) ||
2273 !cpu_isar_feature(aa32_vfp_simd, cpu) ||
2274 !arm_feature(env, ARM_FEATURE_XSCALE));
2275
2276 #ifndef CONFIG_USER_ONLY
2277 {
2278 int pagebits;
2279 if (arm_feature(env, ARM_FEATURE_V7) &&
2280 !arm_feature(env, ARM_FEATURE_M) &&
2281 !arm_feature(env, ARM_FEATURE_PMSA)) {
2282 /*
2283 * v7VMSA drops support for the old ARMv5 tiny pages,
2284 * so we can use 4K pages.
2285 */
2286 pagebits = 12;
2287 } else {
2288 /*
2289 * For CPUs which might have tiny 1K pages, or which have an
2290 * MPU and might have small region sizes, stick with 1K pages.
2291 */
2292 pagebits = 10;
2293 }
2294 if (!set_preferred_target_page_bits(pagebits)) {
2295 /*
2296 * This can only ever happen for hotplugging a CPU, or if
2297 * the board code incorrectly creates a CPU which it has
2298 * promised via minimum_page_size that it will not.
2299 */
2300 error_setg(errp, "This CPU requires a smaller page size "
2301 "than the system is using");
2302 return;
2303 }
2304 }
2305 #endif
2306
2307 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
2308 * We don't support setting cluster ID ([16..23]) (known as Aff2
2309 * in later ARM ARM versions), or any of the higher affinity level fields,
2310 * so these bits always RAZ.
2311 */
2312 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
2313 cpu->mp_affinity = arm_build_mp_affinity(cs->cpu_index,
2314 ARM_DEFAULT_CPUS_PER_CLUSTER);
2315 }
2316
2317 if (cpu->reset_hivecs) {
2318 cpu->reset_sctlr |= (1 << 13);
2319 }
2320
2321 if (cpu->cfgend) {
2322 if (arm_feature(env, ARM_FEATURE_V7)) {
2323 cpu->reset_sctlr |= SCTLR_EE;
2324 } else {
2325 cpu->reset_sctlr |= SCTLR_B;
2326 }
2327 }
2328
2329 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) {
2330 /* If the has_el3 CPU property is disabled then we need to disable the
2331 * feature.
2332 */
2333 unset_feature(env, ARM_FEATURE_EL3);
2334
2335 /*
2336 * Disable the security extension feature bits in the processor
2337 * feature registers as well.
2338 */
2339 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
2340 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
2341 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
2342 ID_AA64PFR0, EL3, 0);
2343
2344 /* Disable the realm management extension, which requires EL3. */
2345 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
2346 ID_AA64PFR0, RME, 0);
2347 }
2348
2349 if (!cpu->has_el2) {
2350 unset_feature(env, ARM_FEATURE_EL2);
2351 }
2352
2353 if (!cpu->has_pmu) {
2354 unset_feature(env, ARM_FEATURE_PMU);
2355 }
2356 if (arm_feature(env, ARM_FEATURE_PMU)) {
2357 pmu_init(cpu);
2358
2359 if (!kvm_enabled()) {
2360 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
2361 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
2362 }
2363
2364 #ifndef CONFIG_USER_ONLY
2365 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb,
2366 cpu);
2367 #endif
2368 } else {
2369 cpu->isar.id_aa64dfr0 =
2370 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
2371 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0);
2372 cpu->pmceid0 = 0;
2373 cpu->pmceid1 = 0;
2374 }
2375
2376 if (!arm_feature(env, ARM_FEATURE_EL2)) {
2377 /*
2378 * Disable the hypervisor feature bits in the processor feature
2379 * registers if we don't have EL2.
2380 */
2381 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
2382 ID_AA64PFR0, EL2, 0);
2383 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
2384 ID_PFR1, VIRTUALIZATION, 0);
2385 }
2386
2387 if (cpu_isar_feature(aa64_mte, cpu)) {
2388 /*
2389 * The architectural range of GM blocksize is 2-6, however qemu
2390 * doesn't support blocksize of 2 (see HELPER(ldgm)).
2391 */
2392 if (tcg_enabled()) {
2393 assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6);
2394 }
2395
2396 #ifndef CONFIG_USER_ONLY
2397 /*
2398 * If we run with TCG and do not have tag-memory provided by
2399 * the machine, then reduce MTE support to instructions enabled at EL0.
2400 * This matches Cortex-A710 BROADCASTMTE input being LOW.
2401 */
2402 if (tcg_enabled() && cpu->tag_memory == NULL) {
2403 cpu->isar.id_aa64pfr1 =
2404 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
2405 }
2406
2407 /*
2408 * If MTE is supported by the host, however it should not be
2409 * enabled on the guest (i.e mte=off), clear guest's MTE bits."
2410 */
2411 if (kvm_enabled() && !cpu->kvm_mte) {
2412 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
2413 }
2414 #endif
2415 }
2416
2417 #ifndef CONFIG_USER_ONLY
2418 if (tcg_enabled() && cpu_isar_feature(aa64_wfxt, cpu)) {
2419 cpu->wfxt_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
2420 arm_wfxt_timer_cb, cpu);
2421 }
2422 #endif
2423
2424 if (tcg_enabled()) {
2425 /*
2426 * Don't report some architectural features in the ID registers
2427 * where TCG does not yet implement it (not even a minimal
2428 * stub version). This avoids guests falling over when they
2429 * try to access the non-existent system registers for them.
2430 */
2431 /* FEAT_SPE (Statistical Profiling Extension) */
2432 cpu->isar.id_aa64dfr0 =
2433 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
2434 /* FEAT_TRBE (Trace Buffer Extension) */
2435 cpu->isar.id_aa64dfr0 =
2436 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0);
2437 /* FEAT_TRF (Self-hosted Trace Extension) */
2438 cpu->isar.id_aa64dfr0 =
2439 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0);
2440 cpu->isar.id_dfr0 =
2441 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0);
2442 /* Trace Macrocell system register access */
2443 cpu->isar.id_aa64dfr0 =
2444 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0);
2445 cpu->isar.id_dfr0 =
2446 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0);
2447 /* Memory mapped trace */
2448 cpu->isar.id_dfr0 =
2449 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0);
2450 /* FEAT_AMU (Activity Monitors Extension) */
2451 cpu->isar.id_aa64pfr0 =
2452 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, AMU, 0);
2453 cpu->isar.id_pfr0 =
2454 FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0);
2455 /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */
2456 cpu->isar.id_aa64pfr0 =
2457 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0);
2458 }
2459
2460 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
2461 * to false or by setting pmsav7-dregion to 0.
2462 */
2463 if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) {
2464 cpu->has_mpu = false;
2465 cpu->pmsav7_dregion = 0;
2466 cpu->pmsav8r_hdregion = 0;
2467 }
2468
2469 if (arm_feature(env, ARM_FEATURE_PMSA) &&
2470 arm_feature(env, ARM_FEATURE_V7)) {
2471 uint32_t nr = cpu->pmsav7_dregion;
2472
2473 if (nr > 0xff) {
2474 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
2475 return;
2476 }
2477
2478 if (nr) {
2479 if (arm_feature(env, ARM_FEATURE_V8)) {
2480 /* PMSAv8 */
2481 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr);
2482 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr);
2483 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
2484 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr);
2485 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
2486 }
2487 } else {
2488 env->pmsav7.drbar = g_new0(uint32_t, nr);
2489 env->pmsav7.drsr = g_new0(uint32_t, nr);
2490 env->pmsav7.dracr = g_new0(uint32_t, nr);
2491 }
2492 }
2493
2494 if (cpu->pmsav8r_hdregion > 0xff) {
2495 error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32,
2496 cpu->pmsav8r_hdregion);
2497 return;
2498 }
2499
2500 if (cpu->pmsav8r_hdregion) {
2501 env->pmsav8.hprbar = g_new0(uint32_t,
2502 cpu->pmsav8r_hdregion);
2503 env->pmsav8.hprlar = g_new0(uint32_t,
2504 cpu->pmsav8r_hdregion);
2505 }
2506 }
2507
2508 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
2509 uint32_t nr = cpu->sau_sregion;
2510
2511 if (nr > 0xff) {
2512 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr);
2513 return;
2514 }
2515
2516 if (nr) {
2517 env->sau.rbar = g_new0(uint32_t, nr);
2518 env->sau.rlar = g_new0(uint32_t, nr);
2519 }
2520 }
2521
2522 if (arm_feature(env, ARM_FEATURE_EL3)) {
2523 set_feature(env, ARM_FEATURE_VBAR);
2524 }
2525
2526 #ifndef CONFIG_USER_ONLY
2527 if (tcg_enabled() && cpu_isar_feature(aa64_rme, cpu)) {
2528 arm_register_el_change_hook(cpu, >_rme_post_el_change, 0);
2529 }
2530 #endif
2531
2532 register_cp_regs_for_features(cpu);
2533 arm_cpu_register_gdb_regs_for_features(cpu);
2534 arm_cpu_register_gdb_commands(cpu);
2535
2536 init_cpreg_list(cpu);
2537
2538 #ifndef CONFIG_USER_ONLY
2539 MachineState *ms = MACHINE(qdev_get_machine());
2540 unsigned int smp_cpus = ms->smp.cpus;
2541 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY);
2542
2543 /*
2544 * We must set cs->num_ases to the final value before
2545 * the first call to cpu_address_space_init.
2546 */
2547 if (cpu->tag_memory != NULL) {
2548 cs->num_ases = 3 + has_secure;
2549 } else {
2550 cs->num_ases = 1 + has_secure;
2551 }
2552
2553 if (has_secure) {
2554 if (!cpu->secure_memory) {
2555 cpu->secure_memory = cs->memory;
2556 }
2557 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory",
2558 cpu->secure_memory);
2559 }
2560
2561 if (cpu->tag_memory != NULL) {
2562 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory",
2563 cpu->tag_memory);
2564 if (has_secure) {
2565 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory",
2566 cpu->secure_tag_memory);
2567 }
2568 }
2569
2570 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
2571
2572 /* No core_count specified, default to smp_cpus. */
2573 if (cpu->core_count == -1) {
2574 cpu->core_count = smp_cpus;
2575 }
2576 #endif
2577
2578 if (tcg_enabled()) {
2579 int dcz_blocklen = 4 << cpu->dcz_blocksize;
2580
2581 /*
2582 * We only support DCZ blocklen that fits on one page.
2583 *
2584 * Architectually this is always true. However TARGET_PAGE_SIZE
2585 * is variable and, for compatibility with -machine virt-2.7,
2586 * is only 1KiB, as an artifact of legacy ARMv5 subpage support.
2587 * But even then, while the largest architectural DCZ blocklen
2588 * is 2KiB, no cpu actually uses such a large blocklen.
2589 */
2590 assert(dcz_blocklen <= TARGET_PAGE_SIZE);
2591
2592 /*
2593 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say
2594 * both nibbles of each byte storing tag data may be written at once.
2595 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32.
2596 */
2597 if (cpu_isar_feature(aa64_mte, cpu)) {
2598 assert(dcz_blocklen >= 2 * TAG_GRANULE);
2599 }
2600 }
2601
2602 qemu_init_vcpu(cs);
2603 cpu_reset(cs);
2604
2605 acc->parent_realize(dev, errp);
2606 }
2607
arm_cpu_class_by_name(const char * cpu_model)2608 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
2609 {
2610 ObjectClass *oc;
2611 char *typename;
2612 char **cpuname;
2613 const char *cpunamestr;
2614
2615 cpuname = g_strsplit(cpu_model, ",", 1);
2616 cpunamestr = cpuname[0];
2617 #ifdef CONFIG_USER_ONLY
2618 /* For backwards compatibility usermode emulation allows "-cpu any",
2619 * which has the same semantics as "-cpu max".
2620 */
2621 if (!strcmp(cpunamestr, "any")) {
2622 cpunamestr = "max";
2623 }
2624 #endif
2625 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr);
2626 oc = object_class_by_name(typename);
2627 g_strfreev(cpuname);
2628 g_free(typename);
2629
2630 return oc;
2631 }
2632
2633 static const Property arm_cpu_properties[] = {
2634 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0),
2635 DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
2636 mp_affinity, ARM64_AFFINITY_INVALID),
2637 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
2638 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
2639 /* True to default to the backward-compat old CNTFRQ rather than 1Ghz */
2640 DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false),
2641 DEFINE_PROP_BOOL("backcompat-pauth-default-use-qarma5", ARMCPU,
2642 backcompat_pauth_default_use_qarma5, false),
2643 };
2644
arm_gdb_arch_name(CPUState * cs)2645 static const gchar *arm_gdb_arch_name(CPUState *cs)
2646 {
2647 ARMCPU *cpu = ARM_CPU(cs);
2648 CPUARMState *env = &cpu->env;
2649
2650 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
2651 return "iwmmxt";
2652 }
2653 return "arm";
2654 }
2655
2656 #ifndef CONFIG_USER_ONLY
2657 #include "hw/core/sysemu-cpu-ops.h"
2658
2659 static const struct SysemuCPUOps arm_sysemu_ops = {
2660 .has_work = arm_cpu_has_work,
2661 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug,
2662 .asidx_from_attrs = arm_asidx_from_attrs,
2663 .write_elf32_note = arm_cpu_write_elf32_note,
2664 .write_elf64_note = arm_cpu_write_elf64_note,
2665 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
2666 .legacy_vmsd = &vmstate_arm_cpu,
2667 };
2668 #endif
2669
2670 #ifdef CONFIG_TCG
2671 static const TCGCPUOps arm_tcg_ops = {
2672 .initialize = arm_translate_init,
2673 .translate_code = arm_translate_code,
2674 .synchronize_from_tb = arm_cpu_synchronize_from_tb,
2675 .debug_excp_handler = arm_debug_excp_handler,
2676 .restore_state_to_opc = arm_restore_state_to_opc,
2677
2678 #ifdef CONFIG_USER_ONLY
2679 .record_sigsegv = arm_cpu_record_sigsegv,
2680 .record_sigbus = arm_cpu_record_sigbus,
2681 #else
2682 .tlb_fill_align = arm_cpu_tlb_fill_align,
2683 .cpu_exec_interrupt = arm_cpu_exec_interrupt,
2684 .cpu_exec_halt = arm_cpu_exec_halt,
2685 .do_interrupt = arm_cpu_do_interrupt,
2686 .do_transaction_failed = arm_cpu_do_transaction_failed,
2687 .do_unaligned_access = arm_cpu_do_unaligned_access,
2688 .adjust_watchpoint_address = arm_adjust_watchpoint_address,
2689 .debug_check_watchpoint = arm_debug_check_watchpoint,
2690 .debug_check_breakpoint = arm_debug_check_breakpoint,
2691 #endif /* !CONFIG_USER_ONLY */
2692 };
2693 #endif /* CONFIG_TCG */
2694
arm_cpu_class_init(ObjectClass * oc,void * data)2695 static void arm_cpu_class_init(ObjectClass *oc, void *data)
2696 {
2697 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2698 CPUClass *cc = CPU_CLASS(acc);
2699 DeviceClass *dc = DEVICE_CLASS(oc);
2700 ResettableClass *rc = RESETTABLE_CLASS(oc);
2701
2702 device_class_set_parent_realize(dc, arm_cpu_realizefn,
2703 &acc->parent_realize);
2704
2705 device_class_set_props(dc, arm_cpu_properties);
2706
2707 resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL,
2708 &acc->parent_phases);
2709
2710 cc->class_by_name = arm_cpu_class_by_name;
2711 cc->mmu_index = arm_cpu_mmu_index;
2712 cc->dump_state = arm_cpu_dump_state;
2713 cc->set_pc = arm_cpu_set_pc;
2714 cc->get_pc = arm_cpu_get_pc;
2715 cc->gdb_read_register = arm_cpu_gdb_read_register;
2716 cc->gdb_write_register = arm_cpu_gdb_write_register;
2717 #ifndef CONFIG_USER_ONLY
2718 cc->sysemu_ops = &arm_sysemu_ops;
2719 #endif
2720 cc->gdb_arch_name = arm_gdb_arch_name;
2721 cc->gdb_stop_before_watchpoint = true;
2722 cc->disas_set_info = arm_disas_set_info;
2723
2724 #ifdef CONFIG_TCG
2725 cc->tcg_ops = &arm_tcg_ops;
2726 #endif /* CONFIG_TCG */
2727 }
2728
arm_cpu_instance_init(Object * obj)2729 static void arm_cpu_instance_init(Object *obj)
2730 {
2731 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
2732
2733 acc->info->initfn(obj);
2734 arm_cpu_post_init(obj);
2735 }
2736
cpu_register_class_init(ObjectClass * oc,void * data)2737 static void cpu_register_class_init(ObjectClass *oc, void *data)
2738 {
2739 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2740 CPUClass *cc = CPU_CLASS(acc);
2741
2742 acc->info = data;
2743 cc->gdb_core_xml_file = "arm-core.xml";
2744 if (acc->info->deprecation_note) {
2745 cc->deprecation_note = acc->info->deprecation_note;
2746 }
2747 }
2748
arm_cpu_register(const ARMCPUInfo * info)2749 void arm_cpu_register(const ARMCPUInfo *info)
2750 {
2751 TypeInfo type_info = {
2752 .parent = TYPE_ARM_CPU,
2753 .instance_init = arm_cpu_instance_init,
2754 .class_init = info->class_init ?: cpu_register_class_init,
2755 .class_data = (void *)info,
2756 };
2757
2758 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
2759 type_register_static(&type_info);
2760 g_free((void *)type_info.name);
2761 }
2762
2763 static const TypeInfo arm_cpu_type_info = {
2764 .name = TYPE_ARM_CPU,
2765 .parent = TYPE_CPU,
2766 .instance_size = sizeof(ARMCPU),
2767 .instance_align = __alignof__(ARMCPU),
2768 .instance_init = arm_cpu_initfn,
2769 .instance_finalize = arm_cpu_finalizefn,
2770 .abstract = true,
2771 .class_size = sizeof(ARMCPUClass),
2772 .class_init = arm_cpu_class_init,
2773 };
2774
arm_cpu_register_types(void)2775 static void arm_cpu_register_types(void)
2776 {
2777 type_register_static(&arm_cpu_type_info);
2778 }
2779
2780 type_init(arm_cpu_register_types)
2781