1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2019 NXP.
4 */
5
6 #include <linux/init.h>
7 #include <linux/io.h>
8 #include <linux/of_address.h>
9 #include <linux/slab.h>
10 #include <linux/sys_soc.h>
11 #include <linux/platform_device.h>
12 #include <linux/arm-smccc.h>
13 #include <linux/of.h>
14 #include <linux/clk.h>
15
16 #define REV_B1 0x21
17
18 #define IMX8MQ_SW_INFO_B1 0x40
19 #define IMX8MQ_SW_MAGIC_B1 0xff0055aa
20
21 #define IMX_SIP_GET_SOC_INFO 0xc2000006
22
23 #define OCOTP_UID_LOW 0x410
24 #define OCOTP_UID_HIGH 0x420
25
26 #define IMX8MP_OCOTP_UID_OFFSET 0x10
27
28 /* Same as ANADIG_DIGPROG_IMX7D */
29 #define ANADIG_DIGPROG_IMX8MM 0x800
30
31 struct imx8_soc_data {
32 char *name;
33 int (*soc_revision)(u32 *socrev);
34 };
35
36 static u64 soc_uid;
37
38 #ifdef CONFIG_HAVE_ARM_SMCCC
imx8mq_soc_revision_from_atf(void)39 static u32 imx8mq_soc_revision_from_atf(void)
40 {
41 struct arm_smccc_res res;
42
43 arm_smccc_smc(IMX_SIP_GET_SOC_INFO, 0, 0, 0, 0, 0, 0, 0, &res);
44
45 if (res.a0 == SMCCC_RET_NOT_SUPPORTED)
46 return 0;
47 else
48 return res.a0 & 0xff;
49 }
50 #else
imx8mq_soc_revision_from_atf(void)51 static inline u32 imx8mq_soc_revision_from_atf(void) { return 0; };
52 #endif
53
imx8mq_soc_revision(u32 * socrev)54 static int imx8mq_soc_revision(u32 *socrev)
55 {
56 struct device_node *np;
57 void __iomem *ocotp_base;
58 u32 magic;
59 u32 rev;
60 struct clk *clk;
61 int ret;
62
63 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-ocotp");
64 if (!np)
65 return -EINVAL;
66
67 ocotp_base = of_iomap(np, 0);
68 if (!ocotp_base) {
69 ret = -EINVAL;
70 goto err_iomap;
71 }
72
73 clk = of_clk_get_by_name(np, NULL);
74 if (IS_ERR(clk)) {
75 ret = PTR_ERR(clk);
76 goto err_clk;
77 }
78
79 clk_prepare_enable(clk);
80
81 /*
82 * SOC revision on older imx8mq is not available in fuses so query
83 * the value from ATF instead.
84 */
85 rev = imx8mq_soc_revision_from_atf();
86 if (!rev) {
87 magic = readl_relaxed(ocotp_base + IMX8MQ_SW_INFO_B1);
88 if (magic == IMX8MQ_SW_MAGIC_B1)
89 rev = REV_B1;
90 }
91
92 soc_uid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH);
93 soc_uid <<= 32;
94 soc_uid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW);
95
96 *socrev = rev;
97
98 clk_disable_unprepare(clk);
99 clk_put(clk);
100 iounmap(ocotp_base);
101 of_node_put(np);
102
103 return 0;
104
105 err_clk:
106 iounmap(ocotp_base);
107 err_iomap:
108 of_node_put(np);
109 return ret;
110 }
111
imx8mm_soc_uid(void)112 static int imx8mm_soc_uid(void)
113 {
114 void __iomem *ocotp_base;
115 struct device_node *np;
116 struct clk *clk;
117 int ret = 0;
118 u32 offset = of_machine_is_compatible("fsl,imx8mp") ?
119 IMX8MP_OCOTP_UID_OFFSET : 0;
120
121 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-ocotp");
122 if (!np)
123 return -EINVAL;
124
125 ocotp_base = of_iomap(np, 0);
126 if (!ocotp_base) {
127 ret = -EINVAL;
128 goto err_iomap;
129 }
130
131 clk = of_clk_get_by_name(np, NULL);
132 if (IS_ERR(clk)) {
133 ret = PTR_ERR(clk);
134 goto err_clk;
135 }
136
137 clk_prepare_enable(clk);
138
139 soc_uid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH + offset);
140 soc_uid <<= 32;
141 soc_uid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW + offset);
142
143 clk_disable_unprepare(clk);
144 clk_put(clk);
145
146 err_clk:
147 iounmap(ocotp_base);
148 err_iomap:
149 of_node_put(np);
150
151 return ret;
152 }
153
imx8mm_soc_revision(u32 * socrev)154 static int imx8mm_soc_revision(u32 *socrev)
155 {
156 struct device_node *np;
157 void __iomem *anatop_base;
158 int ret;
159
160 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");
161 if (!np)
162 return -EINVAL;
163
164 anatop_base = of_iomap(np, 0);
165 if (!anatop_base) {
166 ret = -EINVAL;
167 goto err_iomap;
168 }
169
170 *socrev = readl_relaxed(anatop_base + ANADIG_DIGPROG_IMX8MM);
171
172 iounmap(anatop_base);
173 of_node_put(np);
174
175 return imx8mm_soc_uid();
176
177 err_iomap:
178 of_node_put(np);
179 return ret;
180 }
181
182 static const struct imx8_soc_data imx8mq_soc_data = {
183 .name = "i.MX8MQ",
184 .soc_revision = imx8mq_soc_revision,
185 };
186
187 static const struct imx8_soc_data imx8mm_soc_data = {
188 .name = "i.MX8MM",
189 .soc_revision = imx8mm_soc_revision,
190 };
191
192 static const struct imx8_soc_data imx8mn_soc_data = {
193 .name = "i.MX8MN",
194 .soc_revision = imx8mm_soc_revision,
195 };
196
197 static const struct imx8_soc_data imx8mp_soc_data = {
198 .name = "i.MX8MP",
199 .soc_revision = imx8mm_soc_revision,
200 };
201
202 static __maybe_unused const struct of_device_id imx8_soc_match[] = {
203 { .compatible = "fsl,imx8mq", .data = &imx8mq_soc_data, },
204 { .compatible = "fsl,imx8mm", .data = &imx8mm_soc_data, },
205 { .compatible = "fsl,imx8mn", .data = &imx8mn_soc_data, },
206 { .compatible = "fsl,imx8mp", .data = &imx8mp_soc_data, },
207 { }
208 };
209
210 #define imx8_revision(soc_rev) \
211 soc_rev ? \
212 kasprintf(GFP_KERNEL, "%d.%d", (soc_rev >> 4) & 0xf, soc_rev & 0xf) : \
213 "unknown"
214
imx8m_soc_probe(struct platform_device * pdev)215 static int imx8m_soc_probe(struct platform_device *pdev)
216 {
217 struct soc_device_attribute *soc_dev_attr;
218 struct soc_device *soc_dev;
219 const struct of_device_id *id;
220 u32 soc_rev = 0;
221 const struct imx8_soc_data *data;
222 int ret;
223
224 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
225 if (!soc_dev_attr)
226 return -ENOMEM;
227
228 soc_dev_attr->family = "Freescale i.MX";
229
230 ret = of_property_read_string(of_root, "model", &soc_dev_attr->machine);
231 if (ret)
232 goto free_soc;
233
234 id = of_match_node(imx8_soc_match, of_root);
235 if (!id) {
236 ret = -ENODEV;
237 goto free_soc;
238 }
239
240 data = id->data;
241 if (data) {
242 soc_dev_attr->soc_id = data->name;
243 if (data->soc_revision) {
244 ret = data->soc_revision(&soc_rev);
245 if (ret)
246 goto free_soc;
247 }
248 }
249
250 soc_dev_attr->revision = imx8_revision(soc_rev);
251 if (!soc_dev_attr->revision) {
252 ret = -ENOMEM;
253 goto free_soc;
254 }
255
256 soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid);
257 if (!soc_dev_attr->serial_number) {
258 ret = -ENOMEM;
259 goto free_rev;
260 }
261
262 soc_dev = soc_device_register(soc_dev_attr);
263 if (IS_ERR(soc_dev)) {
264 ret = PTR_ERR(soc_dev);
265 goto free_serial_number;
266 }
267
268 pr_info("SoC: %s revision %s\n", soc_dev_attr->soc_id,
269 soc_dev_attr->revision);
270
271 if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT))
272 platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0);
273
274 return 0;
275
276 free_serial_number:
277 kfree(soc_dev_attr->serial_number);
278 free_rev:
279 if (strcmp(soc_dev_attr->revision, "unknown"))
280 kfree(soc_dev_attr->revision);
281 free_soc:
282 kfree(soc_dev_attr);
283 return ret;
284 }
285
286 static struct platform_driver imx8m_soc_driver = {
287 .probe = imx8m_soc_probe,
288 .driver = {
289 .name = "imx8m-soc",
290 },
291 };
292
imx8_soc_init(void)293 static int __init imx8_soc_init(void)
294 {
295 struct platform_device *pdev;
296 int ret;
297
298 /* No match means this is non-i.MX8M hardware, do nothing. */
299 if (!of_match_node(imx8_soc_match, of_root))
300 return 0;
301
302 ret = platform_driver_register(&imx8m_soc_driver);
303 if (ret) {
304 pr_err("Failed to register imx8m-soc platform driver: %d\n", ret);
305 return ret;
306 }
307
308 pdev = platform_device_register_simple("imx8m-soc", -1, NULL, 0);
309 if (IS_ERR(pdev)) {
310 pr_err("Failed to register imx8m-soc platform device: %ld\n", PTR_ERR(pdev));
311 platform_driver_unregister(&imx8m_soc_driver);
312 return PTR_ERR(pdev);
313 }
314
315 return 0;
316 }
317 device_initcall(imx8_soc_init);
318 MODULE_LICENSE("GPL");
319