1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2021 HiSilicon Ltd. */ 3 4 #ifndef HISI_ACC_VFIO_PCI_H 5 #define HISI_ACC_VFIO_PCI_H 6 7 #include <linux/hisi_acc_qm.h> 8 9 #define MB_POLL_PERIOD_US 10 10 #define MB_POLL_TIMEOUT_US 1000 11 #define QM_CACHE_WB_START 0x204 12 #define QM_CACHE_WB_DONE 0x208 13 #define QM_MB_CMD_PAUSE_QM 0xe 14 #define QM_ABNORMAL_INT_STATUS 0x100008 15 #define QM_IFC_INT_STATUS 0x0028 16 #define SEC_CORE_INT_STATUS 0x301008 17 #define HPRE_HAC_INT_STATUS 0x301800 18 #define HZIP_CORE_INT_STATUS 0x3010AC 19 20 #define QM_VFT_CFG_RDY 0x10006c 21 #define QM_VFT_CFG_OP_WR 0x100058 22 #define QM_VFT_CFG_TYPE 0x10005c 23 #define QM_VFT_CFG 0x100060 24 #define QM_VFT_CFG_OP_ENABLE 0x100054 25 #define QM_VFT_CFG_DATA_L 0x100064 26 #define QM_VFT_CFG_DATA_H 0x100068 27 28 #define ERROR_CHECK_TIMEOUT 100 29 #define CHECK_DELAY_TIME 100 30 31 #define QM_SQC_VFT_BASE_SHIFT_V2 28 32 #define QM_SQC_VFT_BASE_MASK_V2 GENMASK(15, 0) 33 #define QM_SQC_VFT_NUM_SHIFT_V2 45 34 #define QM_SQC_VFT_NUM_MASK_V2 GENMASK(9, 0) 35 36 /* RW regs */ 37 #define QM_REGS_MAX_LEN 7 38 #define QM_REG_ADDR_OFFSET 0x0004 39 40 #define QM_XQC_ADDR_OFFSET 32U 41 #define QM_XQC_ADDR_LOW 0x1 42 #define QM_XQC_ADDR_HIGH 0x2 43 44 #define QM_VF_AEQ_INT_MASK 0x0004 45 #define QM_VF_EQ_INT_MASK 0x000c 46 #define QM_IFC_INT_SOURCE_V 0x0020 47 #define QM_IFC_INT_MASK 0x0024 48 #define QM_IFC_INT_SET_V 0x002c 49 #define QM_QUE_ISO_CFG_V 0x0030 50 #define QM_PAGE_SIZE 0x0034 51 52 #define QM_EQC_DW0 0X8000 53 #define QM_AEQC_DW0 0X8020 54 55 #define ACC_DRV_MAJOR_VER 1 56 #define ACC_DRV_MINOR_VER 0 57 58 #define ACC_DEV_MAGIC_V1 0XCDCDCDCDFEEDAACC 59 #define ACC_DEV_MAGIC_V2 0xAACCFEEDDECADEDE 60 61 struct acc_vf_data { 62 #define QM_MATCH_SIZE offsetofend(struct acc_vf_data, qm_rsv_state) 63 /* QM match information */ 64 u64 acc_magic; 65 u32 qp_num; 66 u32 dev_id; 67 u32 que_iso_cfg; 68 u32 qp_base; 69 u32 vf_qm_state; 70 /* QM reserved match information */ 71 u16 major_ver; 72 u16 minor_ver; 73 u32 qm_rsv_state[2]; 74 75 /* QM RW regs */ 76 u32 aeq_int_mask; 77 u32 eq_int_mask; 78 u32 ifc_int_source; 79 u32 ifc_int_mask; 80 u32 ifc_int_set; 81 u32 page_size; 82 83 /* QM_EQC_DW has 7 regs */ 84 u32 qm_eqc_dw[7]; 85 86 /* QM_AEQC_DW has 7 regs */ 87 u32 qm_aeqc_dw[7]; 88 89 /* QM reserved 5 regs */ 90 u32 qm_rsv_regs[5]; 91 u32 padding; 92 /* QM memory init information */ 93 u64 eqe_dma; 94 u64 aeqe_dma; 95 u64 sqc_dma; 96 u64 cqc_dma; 97 }; 98 99 struct hisi_acc_vf_migration_file { 100 struct file *filp; 101 struct mutex lock; 102 bool disabled; 103 104 struct hisi_acc_vf_core_device *hisi_acc_vdev; 105 struct acc_vf_data vf_data; 106 size_t total_length; 107 }; 108 109 struct hisi_acc_vf_core_device { 110 struct vfio_pci_core_device core_device; 111 u8 match_done:1; 112 u8 deferred_reset:1; 113 /* For migration state */ 114 struct mutex state_mutex; 115 enum vfio_device_mig_state mig_state; 116 struct pci_dev *pf_dev; 117 struct pci_dev *vf_dev; 118 struct hisi_qm *pf_qm; 119 struct hisi_qm vf_qm; 120 u32 vf_qm_state; 121 int vf_id; 122 /* For reset handler */ 123 spinlock_t reset_lock; 124 struct hisi_acc_vf_migration_file *resuming_migf; 125 struct hisi_acc_vf_migration_file *saving_migf; 126 }; 127 #endif /* HISI_ACC_VFIO_PCI_H */ 128