1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2021 Intel Corporation. */
3
4 #include <linux/avf/virtchnl.h>
5 #include <linux/bitfield.h>
6 #include <linux/delay.h>
7 #include <linux/etherdevice.h>
8 #include <linux/pci.h>
9 #include "i40e_adminq_cmd.h"
10 #include "i40e_devids.h"
11 #include "i40e_prototype.h"
12 #include "i40e_register.h"
13
14 /**
15 * i40e_set_mac_type - Sets MAC type
16 * @hw: pointer to the HW structure
17 *
18 * This function sets the mac type of the adapter based on the
19 * vendor ID and device ID stored in the hw structure.
20 **/
i40e_set_mac_type(struct i40e_hw * hw)21 int i40e_set_mac_type(struct i40e_hw *hw)
22 {
23 int status = 0;
24
25 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
26 switch (hw->device_id) {
27 case I40E_DEV_ID_SFP_XL710:
28 case I40E_DEV_ID_QEMU:
29 case I40E_DEV_ID_KX_B:
30 case I40E_DEV_ID_KX_C:
31 case I40E_DEV_ID_QSFP_A:
32 case I40E_DEV_ID_QSFP_B:
33 case I40E_DEV_ID_QSFP_C:
34 case I40E_DEV_ID_1G_BASE_T_BC:
35 case I40E_DEV_ID_5G_BASE_T_BC:
36 case I40E_DEV_ID_10G_BASE_T:
37 case I40E_DEV_ID_10G_BASE_T4:
38 case I40E_DEV_ID_10G_BASE_T_BC:
39 case I40E_DEV_ID_10G_B:
40 case I40E_DEV_ID_10G_SFP:
41 case I40E_DEV_ID_20G_KR2:
42 case I40E_DEV_ID_20G_KR2_A:
43 case I40E_DEV_ID_25G_B:
44 case I40E_DEV_ID_25G_SFP28:
45 case I40E_DEV_ID_X710_N3000:
46 case I40E_DEV_ID_XXV710_N3000:
47 hw->mac.type = I40E_MAC_XL710;
48 break;
49 case I40E_DEV_ID_KX_X722:
50 case I40E_DEV_ID_QSFP_X722:
51 case I40E_DEV_ID_SFP_X722:
52 case I40E_DEV_ID_1G_BASE_T_X722:
53 case I40E_DEV_ID_10G_BASE_T_X722:
54 case I40E_DEV_ID_SFP_I_X722:
55 case I40E_DEV_ID_SFP_X722_A:
56 hw->mac.type = I40E_MAC_X722;
57 break;
58 default:
59 hw->mac.type = I40E_MAC_GENERIC;
60 break;
61 }
62 } else {
63 status = -ENODEV;
64 }
65
66 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
67 hw->mac.type, status);
68 return status;
69 }
70
71 /**
72 * i40e_aq_str - convert AQ err code to a string
73 * @hw: pointer to the HW structure
74 * @aq_err: the AQ error code to convert
75 **/
i40e_aq_str(struct i40e_hw * hw,enum i40e_admin_queue_err aq_err)76 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
77 {
78 switch (aq_err) {
79 case I40E_AQ_RC_OK:
80 return "OK";
81 case I40E_AQ_RC_EPERM:
82 return "I40E_AQ_RC_EPERM";
83 case I40E_AQ_RC_ENOENT:
84 return "I40E_AQ_RC_ENOENT";
85 case I40E_AQ_RC_ESRCH:
86 return "I40E_AQ_RC_ESRCH";
87 case I40E_AQ_RC_EINTR:
88 return "I40E_AQ_RC_EINTR";
89 case I40E_AQ_RC_EIO:
90 return "I40E_AQ_RC_EIO";
91 case I40E_AQ_RC_ENXIO:
92 return "I40E_AQ_RC_ENXIO";
93 case I40E_AQ_RC_E2BIG:
94 return "I40E_AQ_RC_E2BIG";
95 case I40E_AQ_RC_EAGAIN:
96 return "I40E_AQ_RC_EAGAIN";
97 case I40E_AQ_RC_ENOMEM:
98 return "I40E_AQ_RC_ENOMEM";
99 case I40E_AQ_RC_EACCES:
100 return "I40E_AQ_RC_EACCES";
101 case I40E_AQ_RC_EFAULT:
102 return "I40E_AQ_RC_EFAULT";
103 case I40E_AQ_RC_EBUSY:
104 return "I40E_AQ_RC_EBUSY";
105 case I40E_AQ_RC_EEXIST:
106 return "I40E_AQ_RC_EEXIST";
107 case I40E_AQ_RC_EINVAL:
108 return "I40E_AQ_RC_EINVAL";
109 case I40E_AQ_RC_ENOTTY:
110 return "I40E_AQ_RC_ENOTTY";
111 case I40E_AQ_RC_ENOSPC:
112 return "I40E_AQ_RC_ENOSPC";
113 case I40E_AQ_RC_ENOSYS:
114 return "I40E_AQ_RC_ENOSYS";
115 case I40E_AQ_RC_ERANGE:
116 return "I40E_AQ_RC_ERANGE";
117 case I40E_AQ_RC_EFLUSHED:
118 return "I40E_AQ_RC_EFLUSHED";
119 case I40E_AQ_RC_BAD_ADDR:
120 return "I40E_AQ_RC_BAD_ADDR";
121 case I40E_AQ_RC_EMODE:
122 return "I40E_AQ_RC_EMODE";
123 case I40E_AQ_RC_EFBIG:
124 return "I40E_AQ_RC_EFBIG";
125 }
126
127 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
128 return hw->err_str;
129 }
130
131 /**
132 * i40e_debug_aq
133 * @hw: debug mask related to admin queue
134 * @mask: debug mask
135 * @desc: pointer to admin queue descriptor
136 * @buffer: pointer to command buffer
137 * @buf_len: max length of buffer
138 *
139 * Dumps debug log about adminq command with descriptor contents.
140 **/
i40e_debug_aq(struct i40e_hw * hw,enum i40e_debug_mask mask,void * desc,void * buffer,u16 buf_len)141 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
142 void *buffer, u16 buf_len)
143 {
144 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
145 u32 effective_mask = hw->debug_mask & mask;
146 char prefix[27];
147 u16 len;
148 u8 *buf = (u8 *)buffer;
149
150 if (!effective_mask || !desc)
151 return;
152
153 len = le16_to_cpu(aq_desc->datalen);
154
155 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
156 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
157 le16_to_cpu(aq_desc->opcode),
158 le16_to_cpu(aq_desc->flags),
159 le16_to_cpu(aq_desc->datalen),
160 le16_to_cpu(aq_desc->retval));
161 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
162 "\tcookie (h,l) 0x%08X 0x%08X\n",
163 le32_to_cpu(aq_desc->cookie_high),
164 le32_to_cpu(aq_desc->cookie_low));
165 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
166 "\tparam (0,1) 0x%08X 0x%08X\n",
167 le32_to_cpu(aq_desc->params.internal.param0),
168 le32_to_cpu(aq_desc->params.internal.param1));
169 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
170 "\taddr (h,l) 0x%08X 0x%08X\n",
171 le32_to_cpu(aq_desc->params.external.addr_high),
172 le32_to_cpu(aq_desc->params.external.addr_low));
173
174 if (buffer && buf_len != 0 && len != 0 &&
175 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) {
176 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
177 if (buf_len < len)
178 len = buf_len;
179
180 snprintf(prefix, sizeof(prefix),
181 "i40e %02x:%02x.%x: \t0x",
182 hw->bus.bus_id,
183 hw->bus.device,
184 hw->bus.func);
185
186 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET,
187 16, 1, buf, len, false);
188 }
189 }
190
191 /**
192 * i40e_check_asq_alive
193 * @hw: pointer to the hw struct
194 *
195 * Returns true if Queue is enabled else false.
196 **/
i40e_check_asq_alive(struct i40e_hw * hw)197 bool i40e_check_asq_alive(struct i40e_hw *hw)
198 {
199 if (hw->aq.asq.len)
200 return !!(rd32(hw, hw->aq.asq.len) &
201 I40E_PF_ATQLEN_ATQENABLE_MASK);
202 else
203 return false;
204 }
205
206 /**
207 * i40e_aq_queue_shutdown
208 * @hw: pointer to the hw struct
209 * @unloading: is the driver unloading itself
210 *
211 * Tell the Firmware that we're shutting down the AdminQ and whether
212 * or not the driver is unloading as well.
213 **/
i40e_aq_queue_shutdown(struct i40e_hw * hw,bool unloading)214 int i40e_aq_queue_shutdown(struct i40e_hw *hw,
215 bool unloading)
216 {
217 struct i40e_aq_desc desc;
218 struct i40e_aqc_queue_shutdown *cmd =
219 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
220 int status;
221
222 i40e_fill_default_direct_cmd_desc(&desc,
223 i40e_aqc_opc_queue_shutdown);
224
225 if (unloading)
226 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
227 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
228
229 return status;
230 }
231
232 /**
233 * i40e_aq_get_set_rss_lut
234 * @hw: pointer to the hardware structure
235 * @vsi_id: vsi fw index
236 * @pf_lut: for PF table set true, for VSI table set false
237 * @lut: pointer to the lut buffer provided by the caller
238 * @lut_size: size of the lut buffer
239 * @set: set true to set the table, false to get the table
240 *
241 * Internal function to get or set RSS look up table
242 **/
i40e_aq_get_set_rss_lut(struct i40e_hw * hw,u16 vsi_id,bool pf_lut,u8 * lut,u16 lut_size,bool set)243 static int i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
244 u16 vsi_id, bool pf_lut,
245 u8 *lut, u16 lut_size,
246 bool set)
247 {
248 struct i40e_aq_desc desc;
249 struct i40e_aqc_get_set_rss_lut *cmd_resp =
250 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
251 int status;
252
253 if (set)
254 i40e_fill_default_direct_cmd_desc(&desc,
255 i40e_aqc_opc_set_rss_lut);
256 else
257 i40e_fill_default_direct_cmd_desc(&desc,
258 i40e_aqc_opc_get_rss_lut);
259
260 /* Indirect command */
261 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
262 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
263
264 cmd_resp->vsi_id =
265 cpu_to_le16((u16)((vsi_id <<
266 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
267 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
268 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
269
270 if (pf_lut)
271 cmd_resp->flags |= cpu_to_le16((u16)
272 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
273 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
274 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
275 else
276 cmd_resp->flags |= cpu_to_le16((u16)
277 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
278 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
279 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
280
281 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
282
283 return status;
284 }
285
286 /**
287 * i40e_aq_get_rss_lut
288 * @hw: pointer to the hardware structure
289 * @vsi_id: vsi fw index
290 * @pf_lut: for PF table set true, for VSI table set false
291 * @lut: pointer to the lut buffer provided by the caller
292 * @lut_size: size of the lut buffer
293 *
294 * get the RSS lookup table, PF or VSI type
295 **/
i40e_aq_get_rss_lut(struct i40e_hw * hw,u16 vsi_id,bool pf_lut,u8 * lut,u16 lut_size)296 int i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
297 bool pf_lut, u8 *lut, u16 lut_size)
298 {
299 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
300 false);
301 }
302
303 /**
304 * i40e_aq_set_rss_lut
305 * @hw: pointer to the hardware structure
306 * @vsi_id: vsi fw index
307 * @pf_lut: for PF table set true, for VSI table set false
308 * @lut: pointer to the lut buffer provided by the caller
309 * @lut_size: size of the lut buffer
310 *
311 * set the RSS lookup table, PF or VSI type
312 **/
i40e_aq_set_rss_lut(struct i40e_hw * hw,u16 vsi_id,bool pf_lut,u8 * lut,u16 lut_size)313 int i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
314 bool pf_lut, u8 *lut, u16 lut_size)
315 {
316 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
317 }
318
319 /**
320 * i40e_aq_get_set_rss_key
321 * @hw: pointer to the hw struct
322 * @vsi_id: vsi fw index
323 * @key: pointer to key info struct
324 * @set: set true to set the key, false to get the key
325 *
326 * get the RSS key per VSI
327 **/
i40e_aq_get_set_rss_key(struct i40e_hw * hw,u16 vsi_id,struct i40e_aqc_get_set_rss_key_data * key,bool set)328 static int i40e_aq_get_set_rss_key(struct i40e_hw *hw,
329 u16 vsi_id,
330 struct i40e_aqc_get_set_rss_key_data *key,
331 bool set)
332 {
333 struct i40e_aq_desc desc;
334 struct i40e_aqc_get_set_rss_key *cmd_resp =
335 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
336 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
337 int status;
338
339 if (set)
340 i40e_fill_default_direct_cmd_desc(&desc,
341 i40e_aqc_opc_set_rss_key);
342 else
343 i40e_fill_default_direct_cmd_desc(&desc,
344 i40e_aqc_opc_get_rss_key);
345
346 /* Indirect command */
347 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
348 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
349
350 cmd_resp->vsi_id =
351 cpu_to_le16((u16)((vsi_id <<
352 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
353 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
354 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
355
356 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
357
358 return status;
359 }
360
361 /**
362 * i40e_aq_get_rss_key
363 * @hw: pointer to the hw struct
364 * @vsi_id: vsi fw index
365 * @key: pointer to key info struct
366 *
367 **/
i40e_aq_get_rss_key(struct i40e_hw * hw,u16 vsi_id,struct i40e_aqc_get_set_rss_key_data * key)368 int i40e_aq_get_rss_key(struct i40e_hw *hw,
369 u16 vsi_id,
370 struct i40e_aqc_get_set_rss_key_data *key)
371 {
372 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
373 }
374
375 /**
376 * i40e_aq_set_rss_key
377 * @hw: pointer to the hw struct
378 * @vsi_id: vsi fw index
379 * @key: pointer to key info struct
380 *
381 * set the RSS key per VSI
382 **/
i40e_aq_set_rss_key(struct i40e_hw * hw,u16 vsi_id,struct i40e_aqc_get_set_rss_key_data * key)383 int i40e_aq_set_rss_key(struct i40e_hw *hw,
384 u16 vsi_id,
385 struct i40e_aqc_get_set_rss_key_data *key)
386 {
387 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
388 }
389
390 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
391 * hardware to a bit-field that can be used by SW to more easily determine the
392 * packet type.
393 *
394 * Macros are used to shorten the table lines and make this table human
395 * readable.
396 *
397 * We store the PTYPE in the top byte of the bit field - this is just so that
398 * we can check that the table doesn't have a row missing, as the index into
399 * the table should be the PTYPE.
400 *
401 * Typical work flow:
402 *
403 * IF NOT i40e_ptype_lookup[ptype].known
404 * THEN
405 * Packet is unknown
406 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
407 * Use the rest of the fields to look at the tunnels, inner protocols, etc
408 * ELSE
409 * Use the enum i40e_rx_l2_ptype to decode the packet type
410 * ENDIF
411 */
412
413 /* macro to make the table lines short, use explicit indexing with [PTYPE] */
414 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
415 [PTYPE] = { \
416 1, \
417 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
418 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
419 I40E_RX_PTYPE_##OUTER_FRAG, \
420 I40E_RX_PTYPE_TUNNEL_##T, \
421 I40E_RX_PTYPE_TUNNEL_END_##TE, \
422 I40E_RX_PTYPE_##TEF, \
423 I40E_RX_PTYPE_INNER_PROT_##I, \
424 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
425
426 #define I40E_PTT_UNUSED_ENTRY(PTYPE) [PTYPE] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 }
427
428 /* shorter macros makes the table fit but are terse */
429 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
430 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
431 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
432
433 /* Lookup table mapping in the 8-bit HW PTYPE to the bit field for decoding */
434 struct i40e_rx_ptype_decoded i40e_ptype_lookup[BIT(8)] = {
435 /* L2 Packet types */
436 I40E_PTT_UNUSED_ENTRY(0),
437 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
438 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
439 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
440 I40E_PTT_UNUSED_ENTRY(4),
441 I40E_PTT_UNUSED_ENTRY(5),
442 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
443 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
444 I40E_PTT_UNUSED_ENTRY(8),
445 I40E_PTT_UNUSED_ENTRY(9),
446 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
447 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
448 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
449 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
450 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
451 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
452 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
453 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
454 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
455 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
456 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
457 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
458
459 /* Non Tunneled IPv4 */
460 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
461 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
462 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
463 I40E_PTT_UNUSED_ENTRY(25),
464 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
465 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
466 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
467
468 /* IPv4 --> IPv4 */
469 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
470 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
471 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
472 I40E_PTT_UNUSED_ENTRY(32),
473 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
474 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
475 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
476
477 /* IPv4 --> IPv6 */
478 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
479 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
480 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
481 I40E_PTT_UNUSED_ENTRY(39),
482 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
483 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
484 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
485
486 /* IPv4 --> GRE/NAT */
487 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
488
489 /* IPv4 --> GRE/NAT --> IPv4 */
490 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
491 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
492 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
493 I40E_PTT_UNUSED_ENTRY(47),
494 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
495 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
496 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
497
498 /* IPv4 --> GRE/NAT --> IPv6 */
499 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
500 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
501 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
502 I40E_PTT_UNUSED_ENTRY(54),
503 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
504 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
505 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
506
507 /* IPv4 --> GRE/NAT --> MAC */
508 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
509
510 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
511 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
512 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
513 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
514 I40E_PTT_UNUSED_ENTRY(62),
515 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
516 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
517 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
518
519 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
520 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
521 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
522 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
523 I40E_PTT_UNUSED_ENTRY(69),
524 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
525 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
526 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
527
528 /* IPv4 --> GRE/NAT --> MAC/VLAN */
529 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
530
531 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
532 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
533 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
534 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
535 I40E_PTT_UNUSED_ENTRY(77),
536 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
537 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
538 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
539
540 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
541 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
542 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
543 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
544 I40E_PTT_UNUSED_ENTRY(84),
545 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
546 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
547 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
548
549 /* Non Tunneled IPv6 */
550 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
551 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
552 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
553 I40E_PTT_UNUSED_ENTRY(91),
554 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
555 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
556 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
557
558 /* IPv6 --> IPv4 */
559 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
560 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
561 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
562 I40E_PTT_UNUSED_ENTRY(98),
563 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
564 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
565 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
566
567 /* IPv6 --> IPv6 */
568 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
569 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
570 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
571 I40E_PTT_UNUSED_ENTRY(105),
572 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
573 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
574 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
575
576 /* IPv6 --> GRE/NAT */
577 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
578
579 /* IPv6 --> GRE/NAT -> IPv4 */
580 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
581 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
582 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
583 I40E_PTT_UNUSED_ENTRY(113),
584 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
585 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
586 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
587
588 /* IPv6 --> GRE/NAT -> IPv6 */
589 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
590 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
591 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
592 I40E_PTT_UNUSED_ENTRY(120),
593 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
594 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
595 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
596
597 /* IPv6 --> GRE/NAT -> MAC */
598 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
599
600 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
601 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
602 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
603 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
604 I40E_PTT_UNUSED_ENTRY(128),
605 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
606 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
607 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
608
609 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
610 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
611 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
612 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
613 I40E_PTT_UNUSED_ENTRY(135),
614 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
615 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
616 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
617
618 /* IPv6 --> GRE/NAT -> MAC/VLAN */
619 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
620
621 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
622 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
623 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
624 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
625 I40E_PTT_UNUSED_ENTRY(143),
626 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
627 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
628 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
629
630 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
631 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
632 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
633 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
634 I40E_PTT_UNUSED_ENTRY(150),
635 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
636 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
637 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
638
639 /* unused entries */
640 [154 ... 255] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 }
641 };
642
643 /**
644 * i40e_init_shared_code - Initialize the shared code
645 * @hw: pointer to hardware structure
646 *
647 * This assigns the MAC type and PHY code and inits the NVM.
648 * Does not touch the hardware. This function must be called prior to any
649 * other function in the shared code. The i40e_hw structure should be
650 * memset to 0 prior to calling this function. The following fields in
651 * hw structure should be filled in prior to calling this function:
652 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
653 * subsystem_vendor_id, and revision_id
654 **/
i40e_init_shared_code(struct i40e_hw * hw)655 int i40e_init_shared_code(struct i40e_hw *hw)
656 {
657 u32 port, ari, func_rid;
658 int status = 0;
659
660 i40e_set_mac_type(hw);
661
662 switch (hw->mac.type) {
663 case I40E_MAC_XL710:
664 case I40E_MAC_X722:
665 break;
666 default:
667 return -ENODEV;
668 }
669
670 hw->phy.get_link_info = true;
671
672 /* Determine port number and PF number*/
673 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
674 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
675 hw->port = (u8)port;
676 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
677 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
678 func_rid = rd32(hw, I40E_PF_FUNC_RID);
679 if (ari)
680 hw->pf_id = (u8)(func_rid & 0xff);
681 else
682 hw->pf_id = (u8)(func_rid & 0x7);
683
684 status = i40e_init_nvm(hw);
685 return status;
686 }
687
688 /**
689 * i40e_aq_mac_address_read - Retrieve the MAC addresses
690 * @hw: pointer to the hw struct
691 * @flags: a return indicator of what addresses were added to the addr store
692 * @addrs: the requestor's mac addr store
693 * @cmd_details: pointer to command details structure or NULL
694 **/
695 static int
i40e_aq_mac_address_read(struct i40e_hw * hw,u16 * flags,struct i40e_aqc_mac_address_read_data * addrs,struct i40e_asq_cmd_details * cmd_details)696 i40e_aq_mac_address_read(struct i40e_hw *hw,
697 u16 *flags,
698 struct i40e_aqc_mac_address_read_data *addrs,
699 struct i40e_asq_cmd_details *cmd_details)
700 {
701 struct i40e_aq_desc desc;
702 struct i40e_aqc_mac_address_read *cmd_data =
703 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
704 int status;
705
706 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
707 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
708
709 status = i40e_asq_send_command(hw, &desc, addrs,
710 sizeof(*addrs), cmd_details);
711 *flags = le16_to_cpu(cmd_data->command_flags);
712
713 return status;
714 }
715
716 /**
717 * i40e_aq_mac_address_write - Change the MAC addresses
718 * @hw: pointer to the hw struct
719 * @flags: indicates which MAC to be written
720 * @mac_addr: address to write
721 * @cmd_details: pointer to command details structure or NULL
722 **/
i40e_aq_mac_address_write(struct i40e_hw * hw,u16 flags,u8 * mac_addr,struct i40e_asq_cmd_details * cmd_details)723 int i40e_aq_mac_address_write(struct i40e_hw *hw,
724 u16 flags, u8 *mac_addr,
725 struct i40e_asq_cmd_details *cmd_details)
726 {
727 struct i40e_aq_desc desc;
728 struct i40e_aqc_mac_address_write *cmd_data =
729 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
730 int status;
731
732 i40e_fill_default_direct_cmd_desc(&desc,
733 i40e_aqc_opc_mac_address_write);
734 cmd_data->command_flags = cpu_to_le16(flags);
735 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
736 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
737 ((u32)mac_addr[3] << 16) |
738 ((u32)mac_addr[4] << 8) |
739 mac_addr[5]);
740
741 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
742
743 return status;
744 }
745
746 /**
747 * i40e_get_mac_addr - get MAC address
748 * @hw: pointer to the HW structure
749 * @mac_addr: pointer to MAC address
750 *
751 * Reads the adapter's MAC address from register
752 **/
i40e_get_mac_addr(struct i40e_hw * hw,u8 * mac_addr)753 int i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
754 {
755 struct i40e_aqc_mac_address_read_data addrs;
756 u16 flags = 0;
757 int status;
758
759 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
760
761 if (flags & I40E_AQC_LAN_ADDR_VALID)
762 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
763
764 return status;
765 }
766
767 /**
768 * i40e_get_port_mac_addr - get Port MAC address
769 * @hw: pointer to the HW structure
770 * @mac_addr: pointer to Port MAC address
771 *
772 * Reads the adapter's Port MAC address
773 **/
i40e_get_port_mac_addr(struct i40e_hw * hw,u8 * mac_addr)774 int i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
775 {
776 struct i40e_aqc_mac_address_read_data addrs;
777 u16 flags = 0;
778 int status;
779
780 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
781 if (status)
782 return status;
783
784 if (flags & I40E_AQC_PORT_ADDR_VALID)
785 ether_addr_copy(mac_addr, addrs.port_mac);
786 else
787 status = -EINVAL;
788
789 return status;
790 }
791
792 /**
793 * i40e_pre_tx_queue_cfg - pre tx queue configure
794 * @hw: pointer to the HW structure
795 * @queue: target PF queue index
796 * @enable: state change request
797 *
798 * Handles hw requirement to indicate intention to enable
799 * or disable target queue.
800 **/
i40e_pre_tx_queue_cfg(struct i40e_hw * hw,u32 queue,bool enable)801 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
802 {
803 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
804 u32 reg_block = 0;
805 u32 reg_val;
806
807 if (abs_queue_idx >= 128) {
808 reg_block = abs_queue_idx / 128;
809 abs_queue_idx %= 128;
810 }
811
812 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
813 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
814 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
815
816 if (enable)
817 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
818 else
819 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
820
821 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
822 }
823
824 /**
825 * i40e_read_pba_string - Reads part number string from EEPROM
826 * @hw: pointer to hardware structure
827 * @pba_num: stores the part number string from the EEPROM
828 * @pba_num_size: part number string buffer length
829 *
830 * Reads the part number string from the EEPROM.
831 **/
i40e_read_pba_string(struct i40e_hw * hw,u8 * pba_num,u32 pba_num_size)832 int i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
833 u32 pba_num_size)
834 {
835 u16 pba_word = 0;
836 u16 pba_size = 0;
837 u16 pba_ptr = 0;
838 int status = 0;
839 u16 i = 0;
840
841 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
842 if (status || (pba_word != 0xFAFA)) {
843 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
844 return status;
845 }
846
847 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
848 if (status) {
849 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
850 return status;
851 }
852
853 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
854 if (status) {
855 hw_dbg(hw, "Failed to read PBA Block size.\n");
856 return status;
857 }
858
859 /* Subtract one to get PBA word count (PBA Size word is included in
860 * total size)
861 */
862 pba_size--;
863 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
864 hw_dbg(hw, "Buffer too small for PBA data.\n");
865 return -EINVAL;
866 }
867
868 for (i = 0; i < pba_size; i++) {
869 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
870 if (status) {
871 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
872 return status;
873 }
874
875 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
876 pba_num[(i * 2) + 1] = pba_word & 0xFF;
877 }
878 pba_num[(pba_size * 2)] = '\0';
879
880 return status;
881 }
882
883 /**
884 * i40e_get_media_type - Gets media type
885 * @hw: pointer to the hardware structure
886 **/
i40e_get_media_type(struct i40e_hw * hw)887 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
888 {
889 enum i40e_media_type media;
890
891 switch (hw->phy.link_info.phy_type) {
892 case I40E_PHY_TYPE_10GBASE_SR:
893 case I40E_PHY_TYPE_10GBASE_LR:
894 case I40E_PHY_TYPE_1000BASE_SX:
895 case I40E_PHY_TYPE_1000BASE_LX:
896 case I40E_PHY_TYPE_40GBASE_SR4:
897 case I40E_PHY_TYPE_40GBASE_LR4:
898 case I40E_PHY_TYPE_25GBASE_LR:
899 case I40E_PHY_TYPE_25GBASE_SR:
900 media = I40E_MEDIA_TYPE_FIBER;
901 break;
902 case I40E_PHY_TYPE_100BASE_TX:
903 case I40E_PHY_TYPE_1000BASE_T:
904 case I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS:
905 case I40E_PHY_TYPE_5GBASE_T_LINK_STATUS:
906 case I40E_PHY_TYPE_10GBASE_T:
907 media = I40E_MEDIA_TYPE_BASET;
908 break;
909 case I40E_PHY_TYPE_10GBASE_CR1_CU:
910 case I40E_PHY_TYPE_40GBASE_CR4_CU:
911 case I40E_PHY_TYPE_10GBASE_CR1:
912 case I40E_PHY_TYPE_40GBASE_CR4:
913 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
914 case I40E_PHY_TYPE_40GBASE_AOC:
915 case I40E_PHY_TYPE_10GBASE_AOC:
916 case I40E_PHY_TYPE_25GBASE_CR:
917 case I40E_PHY_TYPE_25GBASE_AOC:
918 case I40E_PHY_TYPE_25GBASE_ACC:
919 media = I40E_MEDIA_TYPE_DA;
920 break;
921 case I40E_PHY_TYPE_1000BASE_KX:
922 case I40E_PHY_TYPE_10GBASE_KX4:
923 case I40E_PHY_TYPE_10GBASE_KR:
924 case I40E_PHY_TYPE_40GBASE_KR4:
925 case I40E_PHY_TYPE_20GBASE_KR2:
926 case I40E_PHY_TYPE_25GBASE_KR:
927 media = I40E_MEDIA_TYPE_BACKPLANE;
928 break;
929 case I40E_PHY_TYPE_SGMII:
930 case I40E_PHY_TYPE_XAUI:
931 case I40E_PHY_TYPE_XFI:
932 case I40E_PHY_TYPE_XLAUI:
933 case I40E_PHY_TYPE_XLPPI:
934 default:
935 media = I40E_MEDIA_TYPE_UNKNOWN;
936 break;
937 }
938
939 return media;
940 }
941
942 /**
943 * i40e_poll_globr - Poll for Global Reset completion
944 * @hw: pointer to the hardware structure
945 * @retry_limit: how many times to retry before failure
946 **/
i40e_poll_globr(struct i40e_hw * hw,u32 retry_limit)947 static int i40e_poll_globr(struct i40e_hw *hw,
948 u32 retry_limit)
949 {
950 u32 cnt, reg = 0;
951
952 for (cnt = 0; cnt < retry_limit; cnt++) {
953 reg = rd32(hw, I40E_GLGEN_RSTAT);
954 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
955 return 0;
956 msleep(100);
957 }
958
959 hw_dbg(hw, "Global reset failed.\n");
960 hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg);
961
962 return -EIO;
963 }
964
965 #define I40E_PF_RESET_WAIT_COUNT_A0 200
966 #define I40E_PF_RESET_WAIT_COUNT 200
967 /**
968 * i40e_pf_reset - Reset the PF
969 * @hw: pointer to the hardware structure
970 *
971 * Assuming someone else has triggered a global reset,
972 * assure the global reset is complete and then reset the PF
973 **/
i40e_pf_reset(struct i40e_hw * hw)974 int i40e_pf_reset(struct i40e_hw *hw)
975 {
976 u32 cnt = 0;
977 u32 cnt1 = 0;
978 u32 reg = 0;
979 u32 grst_del;
980
981 /* Poll for Global Reset steady state in case of recent GRST.
982 * The grst delay value is in 100ms units, and we'll wait a
983 * couple counts longer to be sure we don't just miss the end.
984 */
985 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
986 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
987 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
988
989 /* It can take upto 15 secs for GRST steady state.
990 * Bump it to 16 secs max to be safe.
991 */
992 grst_del = grst_del * 20;
993
994 for (cnt = 0; cnt < grst_del; cnt++) {
995 reg = rd32(hw, I40E_GLGEN_RSTAT);
996 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
997 break;
998 msleep(100);
999 }
1000 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1001 hw_dbg(hw, "Global reset polling failed to complete.\n");
1002 return -EIO;
1003 }
1004
1005 /* Now Wait for the FW to be ready */
1006 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1007 reg = rd32(hw, I40E_GLNVM_ULD);
1008 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1009 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1010 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1011 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1012 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1013 break;
1014 }
1015 usleep_range(10000, 20000);
1016 }
1017 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1018 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1019 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1020 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
1021 return -EIO;
1022 }
1023
1024 /* If there was a Global Reset in progress when we got here,
1025 * we don't need to do the PF Reset
1026 */
1027 if (!cnt) {
1028 u32 reg2 = 0;
1029 if (hw->revision_id == 0)
1030 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1031 else
1032 cnt = I40E_PF_RESET_WAIT_COUNT;
1033 reg = rd32(hw, I40E_PFGEN_CTRL);
1034 wr32(hw, I40E_PFGEN_CTRL,
1035 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1036 for (; cnt; cnt--) {
1037 reg = rd32(hw, I40E_PFGEN_CTRL);
1038 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1039 break;
1040 reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1041 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1042 break;
1043 usleep_range(1000, 2000);
1044 }
1045 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1046 if (i40e_poll_globr(hw, grst_del))
1047 return -EIO;
1048 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1049 hw_dbg(hw, "PF reset polling failed to complete.\n");
1050 return -EIO;
1051 }
1052 }
1053
1054 i40e_clear_pxe_mode(hw);
1055
1056 return 0;
1057 }
1058
1059 /**
1060 * i40e_clear_hw - clear out any left over hw state
1061 * @hw: pointer to the hw struct
1062 *
1063 * Clear queues and interrupts, typically called at init time,
1064 * but after the capabilities have been found so we know how many
1065 * queues and msix vectors have been allocated.
1066 **/
i40e_clear_hw(struct i40e_hw * hw)1067 void i40e_clear_hw(struct i40e_hw *hw)
1068 {
1069 u32 num_queues, base_queue;
1070 s32 num_pf_int;
1071 s32 num_vf_int;
1072 u32 num_vfs;
1073 s32 i;
1074 u32 j;
1075 u32 val;
1076 u32 eol = 0x7ff;
1077
1078 /* get number of interrupts, queues, and VFs */
1079 val = rd32(hw, I40E_GLPCI_CNF2);
1080 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1081 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1082 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1083 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1084
1085 val = rd32(hw, I40E_PFLAN_QALLOC);
1086 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1087 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1088 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1089 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1090 if (val & I40E_PFLAN_QALLOC_VALID_MASK && j >= base_queue)
1091 num_queues = (j - base_queue) + 1;
1092 else
1093 num_queues = 0;
1094
1095 val = rd32(hw, I40E_PF_VT_PFALLOC);
1096 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1097 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1098 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1099 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1100 if (val & I40E_PF_VT_PFALLOC_VALID_MASK && j >= i)
1101 num_vfs = (j - i) + 1;
1102 else
1103 num_vfs = 0;
1104
1105 /* stop all the interrupts */
1106 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1107 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1108 for (i = 0; i < num_pf_int - 2; i++)
1109 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1110
1111 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1112 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1113 wr32(hw, I40E_PFINT_LNKLST0, val);
1114 for (i = 0; i < num_pf_int - 2; i++)
1115 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1116 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1117 for (i = 0; i < num_vfs; i++)
1118 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1119 for (i = 0; i < num_vf_int - 2; i++)
1120 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1121
1122 /* warn the HW of the coming Tx disables */
1123 for (i = 0; i < num_queues; i++) {
1124 u32 abs_queue_idx = base_queue + i;
1125 u32 reg_block = 0;
1126
1127 if (abs_queue_idx >= 128) {
1128 reg_block = abs_queue_idx / 128;
1129 abs_queue_idx %= 128;
1130 }
1131
1132 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1133 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1134 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1135 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1136
1137 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1138 }
1139 udelay(400);
1140
1141 /* stop all the queues */
1142 for (i = 0; i < num_queues; i++) {
1143 wr32(hw, I40E_QINT_TQCTL(i), 0);
1144 wr32(hw, I40E_QTX_ENA(i), 0);
1145 wr32(hw, I40E_QINT_RQCTL(i), 0);
1146 wr32(hw, I40E_QRX_ENA(i), 0);
1147 }
1148
1149 /* short wait for all queue disables to settle */
1150 udelay(50);
1151 }
1152
1153 /**
1154 * i40e_clear_pxe_mode - clear pxe operations mode
1155 * @hw: pointer to the hw struct
1156 *
1157 * Make sure all PXE mode settings are cleared, including things
1158 * like descriptor fetch/write-back mode.
1159 **/
i40e_clear_pxe_mode(struct i40e_hw * hw)1160 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1161 {
1162 u32 reg;
1163
1164 if (i40e_check_asq_alive(hw))
1165 i40e_aq_clear_pxe_mode(hw, NULL);
1166
1167 /* Clear single descriptor fetch/write-back mode */
1168 reg = rd32(hw, I40E_GLLAN_RCTL_0);
1169
1170 if (hw->revision_id == 0) {
1171 /* As a work around clear PXE_MODE instead of setting it */
1172 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1173 } else {
1174 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1175 }
1176 }
1177
1178 /**
1179 * i40e_led_is_mine - helper to find matching led
1180 * @hw: pointer to the hw struct
1181 * @idx: index into GPIO registers
1182 *
1183 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1184 */
i40e_led_is_mine(struct i40e_hw * hw,int idx)1185 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1186 {
1187 u32 gpio_val = 0;
1188 u32 port;
1189
1190 if (!I40E_IS_X710TL_DEVICE(hw->device_id) &&
1191 !hw->func_caps.led[idx])
1192 return 0;
1193 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1194 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1195 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1196
1197 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1198 * if it is not our port then ignore
1199 */
1200 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1201 (port != hw->port))
1202 return 0;
1203
1204 return gpio_val;
1205 }
1206
1207 #define I40E_FW_LED BIT(4)
1208 #define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \
1209 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
1210
1211 #define I40E_LED0 22
1212
1213 #define I40E_PIN_FUNC_SDP 0x0
1214 #define I40E_PIN_FUNC_LED 0x1
1215
1216 /**
1217 * i40e_led_get - return current on/off mode
1218 * @hw: pointer to the hw struct
1219 *
1220 * The value returned is the 'mode' field as defined in the
1221 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1222 * values are variations of possible behaviors relating to
1223 * blink, link, and wire.
1224 **/
i40e_led_get(struct i40e_hw * hw)1225 u32 i40e_led_get(struct i40e_hw *hw)
1226 {
1227 u32 mode = 0;
1228 int i;
1229
1230 /* as per the documentation GPIO 22-29 are the LED
1231 * GPIO pins named LED0..LED7
1232 */
1233 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1234 u32 gpio_val = i40e_led_is_mine(hw, i);
1235
1236 if (!gpio_val)
1237 continue;
1238
1239 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1240 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1241 break;
1242 }
1243
1244 return mode;
1245 }
1246
1247 /**
1248 * i40e_led_set - set new on/off mode
1249 * @hw: pointer to the hw struct
1250 * @mode: 0=off, 0xf=on (else see manual for mode details)
1251 * @blink: true if the LED should blink when on, false if steady
1252 *
1253 * if this function is used to turn on the blink it should
1254 * be used to disable the blink when restoring the original state.
1255 **/
i40e_led_set(struct i40e_hw * hw,u32 mode,bool blink)1256 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1257 {
1258 int i;
1259
1260 if (mode & ~I40E_LED_MODE_VALID) {
1261 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1262 return;
1263 }
1264
1265 /* as per the documentation GPIO 22-29 are the LED
1266 * GPIO pins named LED0..LED7
1267 */
1268 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1269 u32 gpio_val = i40e_led_is_mine(hw, i);
1270
1271 if (!gpio_val)
1272 continue;
1273
1274 if (I40E_IS_X710TL_DEVICE(hw->device_id)) {
1275 u32 pin_func = 0;
1276
1277 if (mode & I40E_FW_LED)
1278 pin_func = I40E_PIN_FUNC_SDP;
1279 else
1280 pin_func = I40E_PIN_FUNC_LED;
1281
1282 gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK;
1283 gpio_val |= ((pin_func <<
1284 I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) &
1285 I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK);
1286 }
1287 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1288 /* this & is a bit of paranoia, but serves as a range check */
1289 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1290 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1291
1292 if (blink)
1293 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1294 else
1295 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1296
1297 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1298 break;
1299 }
1300 }
1301
1302 /* Admin command wrappers */
1303
1304 /**
1305 * i40e_aq_get_phy_capabilities
1306 * @hw: pointer to the hw struct
1307 * @abilities: structure for PHY capabilities to be filled
1308 * @qualified_modules: report Qualified Modules
1309 * @report_init: report init capabilities (active are default)
1310 * @cmd_details: pointer to command details structure or NULL
1311 *
1312 * Returns the various PHY abilities supported on the Port.
1313 **/
1314 int
i40e_aq_get_phy_capabilities(struct i40e_hw * hw,bool qualified_modules,bool report_init,struct i40e_aq_get_phy_abilities_resp * abilities,struct i40e_asq_cmd_details * cmd_details)1315 i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1316 bool qualified_modules, bool report_init,
1317 struct i40e_aq_get_phy_abilities_resp *abilities,
1318 struct i40e_asq_cmd_details *cmd_details)
1319 {
1320 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1321 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1322 struct i40e_aq_desc desc;
1323 int status;
1324
1325 if (!abilities)
1326 return -EINVAL;
1327
1328 do {
1329 i40e_fill_default_direct_cmd_desc(&desc,
1330 i40e_aqc_opc_get_phy_abilities);
1331
1332 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1333 if (abilities_size > I40E_AQ_LARGE_BUF)
1334 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1335
1336 if (qualified_modules)
1337 desc.params.external.param0 |=
1338 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1339
1340 if (report_init)
1341 desc.params.external.param0 |=
1342 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1343
1344 status = i40e_asq_send_command(hw, &desc, abilities,
1345 abilities_size, cmd_details);
1346
1347 switch (hw->aq.asq_last_status) {
1348 case I40E_AQ_RC_EIO:
1349 status = -EIO;
1350 break;
1351 case I40E_AQ_RC_EAGAIN:
1352 usleep_range(1000, 2000);
1353 total_delay++;
1354 status = -EIO;
1355 break;
1356 /* also covers I40E_AQ_RC_OK */
1357 default:
1358 break;
1359 }
1360
1361 } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) &&
1362 (total_delay < max_delay));
1363
1364 if (status)
1365 return status;
1366
1367 if (report_init) {
1368 if (hw->mac.type == I40E_MAC_XL710 &&
1369 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1370 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1371 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1372 } else {
1373 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1374 hw->phy.phy_types |=
1375 ((u64)abilities->phy_type_ext << 32);
1376 }
1377 }
1378
1379 return status;
1380 }
1381
1382 /**
1383 * i40e_aq_set_phy_config
1384 * @hw: pointer to the hw struct
1385 * @config: structure with PHY configuration to be set
1386 * @cmd_details: pointer to command details structure or NULL
1387 *
1388 * Set the various PHY configuration parameters
1389 * supported on the Port.One or more of the Set PHY config parameters may be
1390 * ignored in an MFP mode as the PF may not have the privilege to set some
1391 * of the PHY Config parameters. This status will be indicated by the
1392 * command response.
1393 **/
i40e_aq_set_phy_config(struct i40e_hw * hw,struct i40e_aq_set_phy_config * config,struct i40e_asq_cmd_details * cmd_details)1394 int i40e_aq_set_phy_config(struct i40e_hw *hw,
1395 struct i40e_aq_set_phy_config *config,
1396 struct i40e_asq_cmd_details *cmd_details)
1397 {
1398 struct i40e_aq_desc desc;
1399 struct i40e_aq_set_phy_config *cmd =
1400 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1401 int status;
1402
1403 if (!config)
1404 return -EINVAL;
1405
1406 i40e_fill_default_direct_cmd_desc(&desc,
1407 i40e_aqc_opc_set_phy_config);
1408
1409 *cmd = *config;
1410
1411 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1412
1413 return status;
1414 }
1415
1416 static noinline_for_stack int
i40e_set_fc_status(struct i40e_hw * hw,struct i40e_aq_get_phy_abilities_resp * abilities,bool atomic_restart)1417 i40e_set_fc_status(struct i40e_hw *hw,
1418 struct i40e_aq_get_phy_abilities_resp *abilities,
1419 bool atomic_restart)
1420 {
1421 struct i40e_aq_set_phy_config config;
1422 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1423 u8 pause_mask = 0x0;
1424
1425 switch (fc_mode) {
1426 case I40E_FC_FULL:
1427 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1428 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1429 break;
1430 case I40E_FC_RX_PAUSE:
1431 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1432 break;
1433 case I40E_FC_TX_PAUSE:
1434 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1435 break;
1436 default:
1437 break;
1438 }
1439
1440 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1441 /* clear the old pause settings */
1442 config.abilities = abilities->abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1443 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1444 /* set the new abilities */
1445 config.abilities |= pause_mask;
1446 /* If the abilities have changed, then set the new config */
1447 if (config.abilities == abilities->abilities)
1448 return 0;
1449
1450 /* Auto restart link so settings take effect */
1451 if (atomic_restart)
1452 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1453 /* Copy over all the old settings */
1454 config.phy_type = abilities->phy_type;
1455 config.phy_type_ext = abilities->phy_type_ext;
1456 config.link_speed = abilities->link_speed;
1457 config.eee_capability = abilities->eee_capability;
1458 config.eeer = abilities->eeer_val;
1459 config.low_power_ctrl = abilities->d3_lpan;
1460 config.fec_config = abilities->fec_cfg_curr_mod_ext_info &
1461 I40E_AQ_PHY_FEC_CONFIG_MASK;
1462
1463 return i40e_aq_set_phy_config(hw, &config, NULL);
1464 }
1465
1466 /**
1467 * i40e_set_fc
1468 * @hw: pointer to the hw struct
1469 * @aq_failures: buffer to return AdminQ failure information
1470 * @atomic_restart: whether to enable atomic link restart
1471 *
1472 * Set the requested flow control mode using set_phy_config.
1473 **/
i40e_set_fc(struct i40e_hw * hw,u8 * aq_failures,bool atomic_restart)1474 int i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1475 bool atomic_restart)
1476 {
1477 struct i40e_aq_get_phy_abilities_resp abilities;
1478 int status;
1479
1480 *aq_failures = 0x0;
1481
1482 /* Get the current phy config */
1483 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1484 NULL);
1485 if (status) {
1486 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1487 return status;
1488 }
1489
1490 status = i40e_set_fc_status(hw, &abilities, atomic_restart);
1491 if (status)
1492 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1493
1494 /* Update the link info */
1495 status = i40e_update_link_info(hw);
1496 if (status) {
1497 /* Wait a little bit (on 40G cards it sometimes takes a really
1498 * long time for link to come back from the atomic reset)
1499 * and try once more
1500 */
1501 msleep(1000);
1502 status = i40e_update_link_info(hw);
1503 }
1504 if (status)
1505 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1506
1507 return status;
1508 }
1509
1510 /**
1511 * i40e_aq_clear_pxe_mode
1512 * @hw: pointer to the hw struct
1513 * @cmd_details: pointer to command details structure or NULL
1514 *
1515 * Tell the firmware that the driver is taking over from PXE
1516 **/
i40e_aq_clear_pxe_mode(struct i40e_hw * hw,struct i40e_asq_cmd_details * cmd_details)1517 int i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1518 struct i40e_asq_cmd_details *cmd_details)
1519 {
1520 struct i40e_aq_desc desc;
1521 struct i40e_aqc_clear_pxe *cmd =
1522 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1523 int status;
1524
1525 i40e_fill_default_direct_cmd_desc(&desc,
1526 i40e_aqc_opc_clear_pxe_mode);
1527
1528 cmd->rx_cnt = 0x2;
1529
1530 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1531
1532 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1533
1534 return status;
1535 }
1536
1537 /**
1538 * i40e_aq_set_link_restart_an
1539 * @hw: pointer to the hw struct
1540 * @enable_link: if true: enable link, if false: disable link
1541 * @cmd_details: pointer to command details structure or NULL
1542 *
1543 * Sets up the link and restarts the Auto-Negotiation over the link.
1544 **/
i40e_aq_set_link_restart_an(struct i40e_hw * hw,bool enable_link,struct i40e_asq_cmd_details * cmd_details)1545 int i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1546 bool enable_link,
1547 struct i40e_asq_cmd_details *cmd_details)
1548 {
1549 struct i40e_aq_desc desc;
1550 struct i40e_aqc_set_link_restart_an *cmd =
1551 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1552 int status;
1553
1554 i40e_fill_default_direct_cmd_desc(&desc,
1555 i40e_aqc_opc_set_link_restart_an);
1556
1557 cmd->command = I40E_AQ_PHY_RESTART_AN;
1558 if (enable_link)
1559 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1560 else
1561 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1562
1563 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1564
1565 return status;
1566 }
1567
1568 /**
1569 * i40e_aq_get_link_info
1570 * @hw: pointer to the hw struct
1571 * @enable_lse: enable/disable LinkStatusEvent reporting
1572 * @link: pointer to link status structure - optional
1573 * @cmd_details: pointer to command details structure or NULL
1574 *
1575 * Returns the link status of the adapter.
1576 **/
i40e_aq_get_link_info(struct i40e_hw * hw,bool enable_lse,struct i40e_link_status * link,struct i40e_asq_cmd_details * cmd_details)1577 int i40e_aq_get_link_info(struct i40e_hw *hw,
1578 bool enable_lse, struct i40e_link_status *link,
1579 struct i40e_asq_cmd_details *cmd_details)
1580 {
1581 struct i40e_aq_desc desc;
1582 struct i40e_aqc_get_link_status *resp =
1583 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1584 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1585 bool tx_pause, rx_pause;
1586 u16 command_flags;
1587 int status;
1588
1589 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1590
1591 if (enable_lse)
1592 command_flags = I40E_AQ_LSE_ENABLE;
1593 else
1594 command_flags = I40E_AQ_LSE_DISABLE;
1595 resp->command_flags = cpu_to_le16(command_flags);
1596
1597 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1598
1599 if (status)
1600 goto aq_get_link_info_exit;
1601
1602 /* save off old link status information */
1603 hw->phy.link_info_old = *hw_link_info;
1604
1605 /* update link status */
1606 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1607 hw->phy.media_type = i40e_get_media_type(hw);
1608 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1609 hw_link_info->link_info = resp->link_info;
1610 hw_link_info->an_info = resp->an_info;
1611 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1612 I40E_AQ_CONFIG_FEC_RS_ENA);
1613 hw_link_info->ext_info = resp->ext_info;
1614 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1615 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1616 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1617
1618 /* update fc info */
1619 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1620 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1621 if (tx_pause & rx_pause)
1622 hw->fc.current_mode = I40E_FC_FULL;
1623 else if (tx_pause)
1624 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1625 else if (rx_pause)
1626 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1627 else
1628 hw->fc.current_mode = I40E_FC_NONE;
1629
1630 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1631 hw_link_info->crc_enable = true;
1632 else
1633 hw_link_info->crc_enable = false;
1634
1635 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED))
1636 hw_link_info->lse_enable = true;
1637 else
1638 hw_link_info->lse_enable = false;
1639
1640 if ((hw->mac.type == I40E_MAC_XL710) &&
1641 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1642 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1643 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1644
1645 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE &&
1646 hw->mac.type != I40E_MAC_X722) {
1647 __le32 tmp;
1648
1649 memcpy(&tmp, resp->link_type, sizeof(tmp));
1650 hw->phy.phy_types = le32_to_cpu(tmp);
1651 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
1652 }
1653
1654 /* save link status information */
1655 if (link)
1656 *link = *hw_link_info;
1657
1658 /* flag cleared so helper functions don't call AQ again */
1659 hw->phy.get_link_info = false;
1660
1661 aq_get_link_info_exit:
1662 return status;
1663 }
1664
1665 /**
1666 * i40e_aq_set_phy_int_mask
1667 * @hw: pointer to the hw struct
1668 * @mask: interrupt mask to be set
1669 * @cmd_details: pointer to command details structure or NULL
1670 *
1671 * Set link interrupt mask.
1672 **/
i40e_aq_set_phy_int_mask(struct i40e_hw * hw,u16 mask,struct i40e_asq_cmd_details * cmd_details)1673 int i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1674 u16 mask,
1675 struct i40e_asq_cmd_details *cmd_details)
1676 {
1677 struct i40e_aq_desc desc;
1678 struct i40e_aqc_set_phy_int_mask *cmd =
1679 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1680 int status;
1681
1682 i40e_fill_default_direct_cmd_desc(&desc,
1683 i40e_aqc_opc_set_phy_int_mask);
1684
1685 cmd->event_mask = cpu_to_le16(mask);
1686
1687 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1688
1689 return status;
1690 }
1691
1692 /**
1693 * i40e_aq_set_mac_loopback
1694 * @hw: pointer to the HW struct
1695 * @ena_lpbk: Enable or Disable loopback
1696 * @cmd_details: pointer to command details structure or NULL
1697 *
1698 * Enable/disable loopback on a given port
1699 */
i40e_aq_set_mac_loopback(struct i40e_hw * hw,bool ena_lpbk,struct i40e_asq_cmd_details * cmd_details)1700 int i40e_aq_set_mac_loopback(struct i40e_hw *hw, bool ena_lpbk,
1701 struct i40e_asq_cmd_details *cmd_details)
1702 {
1703 struct i40e_aq_desc desc;
1704 struct i40e_aqc_set_lb_mode *cmd =
1705 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1706
1707 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_lb_modes);
1708 if (ena_lpbk) {
1709 if (hw->nvm.version <= I40E_LEGACY_LOOPBACK_NVM_VER)
1710 cmd->lb_mode = cpu_to_le16(I40E_AQ_LB_MAC_LOCAL_LEGACY);
1711 else
1712 cmd->lb_mode = cpu_to_le16(I40E_AQ_LB_MAC_LOCAL);
1713 }
1714
1715 return i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1716 }
1717
1718 /**
1719 * i40e_aq_set_phy_debug
1720 * @hw: pointer to the hw struct
1721 * @cmd_flags: debug command flags
1722 * @cmd_details: pointer to command details structure or NULL
1723 *
1724 * Reset the external PHY.
1725 **/
i40e_aq_set_phy_debug(struct i40e_hw * hw,u8 cmd_flags,struct i40e_asq_cmd_details * cmd_details)1726 int i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1727 struct i40e_asq_cmd_details *cmd_details)
1728 {
1729 struct i40e_aq_desc desc;
1730 struct i40e_aqc_set_phy_debug *cmd =
1731 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1732 int status;
1733
1734 i40e_fill_default_direct_cmd_desc(&desc,
1735 i40e_aqc_opc_set_phy_debug);
1736
1737 cmd->command_flags = cmd_flags;
1738
1739 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1740
1741 return status;
1742 }
1743
1744 /**
1745 * i40e_is_aq_api_ver_ge
1746 * @aq: pointer to AdminQ info containing HW API version to compare
1747 * @maj: API major value
1748 * @min: API minor value
1749 *
1750 * Assert whether current HW API version is greater/equal than provided.
1751 **/
i40e_is_aq_api_ver_ge(struct i40e_adminq_info * aq,u16 maj,u16 min)1752 static bool i40e_is_aq_api_ver_ge(struct i40e_adminq_info *aq, u16 maj,
1753 u16 min)
1754 {
1755 return (aq->api_maj_ver > maj ||
1756 (aq->api_maj_ver == maj && aq->api_min_ver >= min));
1757 }
1758
1759 /**
1760 * i40e_aq_add_vsi
1761 * @hw: pointer to the hw struct
1762 * @vsi_ctx: pointer to a vsi context struct
1763 * @cmd_details: pointer to command details structure or NULL
1764 *
1765 * Add a VSI context to the hardware.
1766 **/
i40e_aq_add_vsi(struct i40e_hw * hw,struct i40e_vsi_context * vsi_ctx,struct i40e_asq_cmd_details * cmd_details)1767 int i40e_aq_add_vsi(struct i40e_hw *hw,
1768 struct i40e_vsi_context *vsi_ctx,
1769 struct i40e_asq_cmd_details *cmd_details)
1770 {
1771 struct i40e_aq_desc desc;
1772 struct i40e_aqc_add_get_update_vsi *cmd =
1773 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1774 struct i40e_aqc_add_get_update_vsi_completion *resp =
1775 (struct i40e_aqc_add_get_update_vsi_completion *)
1776 &desc.params.raw;
1777 int status;
1778
1779 i40e_fill_default_direct_cmd_desc(&desc,
1780 i40e_aqc_opc_add_vsi);
1781
1782 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1783 cmd->connection_type = vsi_ctx->connection_type;
1784 cmd->vf_id = vsi_ctx->vf_num;
1785 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1786
1787 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1788
1789 status = i40e_asq_send_command_atomic(hw, &desc, &vsi_ctx->info,
1790 sizeof(vsi_ctx->info),
1791 cmd_details, true);
1792
1793 if (status)
1794 goto aq_add_vsi_exit;
1795
1796 vsi_ctx->seid = le16_to_cpu(resp->seid);
1797 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1798 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1799 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1800
1801 aq_add_vsi_exit:
1802 return status;
1803 }
1804
1805 /**
1806 * i40e_aq_set_default_vsi
1807 * @hw: pointer to the hw struct
1808 * @seid: vsi number
1809 * @cmd_details: pointer to command details structure or NULL
1810 **/
i40e_aq_set_default_vsi(struct i40e_hw * hw,u16 seid,struct i40e_asq_cmd_details * cmd_details)1811 int i40e_aq_set_default_vsi(struct i40e_hw *hw,
1812 u16 seid,
1813 struct i40e_asq_cmd_details *cmd_details)
1814 {
1815 struct i40e_aq_desc desc;
1816 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1817 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1818 &desc.params.raw;
1819 int status;
1820
1821 i40e_fill_default_direct_cmd_desc(&desc,
1822 i40e_aqc_opc_set_vsi_promiscuous_modes);
1823
1824 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
1825 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
1826 cmd->seid = cpu_to_le16(seid);
1827
1828 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1829
1830 return status;
1831 }
1832
1833 /**
1834 * i40e_aq_clear_default_vsi
1835 * @hw: pointer to the hw struct
1836 * @seid: vsi number
1837 * @cmd_details: pointer to command details structure or NULL
1838 **/
i40e_aq_clear_default_vsi(struct i40e_hw * hw,u16 seid,struct i40e_asq_cmd_details * cmd_details)1839 int i40e_aq_clear_default_vsi(struct i40e_hw *hw,
1840 u16 seid,
1841 struct i40e_asq_cmd_details *cmd_details)
1842 {
1843 struct i40e_aq_desc desc;
1844 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1845 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1846 &desc.params.raw;
1847 int status;
1848
1849 i40e_fill_default_direct_cmd_desc(&desc,
1850 i40e_aqc_opc_set_vsi_promiscuous_modes);
1851
1852 cmd->promiscuous_flags = cpu_to_le16(0);
1853 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
1854 cmd->seid = cpu_to_le16(seid);
1855
1856 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1857
1858 return status;
1859 }
1860
1861 /**
1862 * i40e_aq_set_vsi_unicast_promiscuous
1863 * @hw: pointer to the hw struct
1864 * @seid: vsi number
1865 * @set: set unicast promiscuous enable/disable
1866 * @cmd_details: pointer to command details structure or NULL
1867 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
1868 **/
i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw * hw,u16 seid,bool set,struct i40e_asq_cmd_details * cmd_details,bool rx_only_promisc)1869 int i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1870 u16 seid, bool set,
1871 struct i40e_asq_cmd_details *cmd_details,
1872 bool rx_only_promisc)
1873 {
1874 struct i40e_aq_desc desc;
1875 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1876 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1877 u16 flags = 0;
1878 int status;
1879
1880 i40e_fill_default_direct_cmd_desc(&desc,
1881 i40e_aqc_opc_set_vsi_promiscuous_modes);
1882
1883 if (set) {
1884 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1885 if (rx_only_promisc && i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
1886 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
1887 }
1888
1889 cmd->promiscuous_flags = cpu_to_le16(flags);
1890
1891 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1892 if (i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
1893 cmd->valid_flags |=
1894 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
1895
1896 cmd->seid = cpu_to_le16(seid);
1897 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1898
1899 return status;
1900 }
1901
1902 /**
1903 * i40e_aq_set_vsi_multicast_promiscuous
1904 * @hw: pointer to the hw struct
1905 * @seid: vsi number
1906 * @set: set multicast promiscuous enable/disable
1907 * @cmd_details: pointer to command details structure or NULL
1908 **/
i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw * hw,u16 seid,bool set,struct i40e_asq_cmd_details * cmd_details)1909 int i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1910 u16 seid, bool set,
1911 struct i40e_asq_cmd_details *cmd_details)
1912 {
1913 struct i40e_aq_desc desc;
1914 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1915 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1916 u16 flags = 0;
1917 int status;
1918
1919 i40e_fill_default_direct_cmd_desc(&desc,
1920 i40e_aqc_opc_set_vsi_promiscuous_modes);
1921
1922 if (set)
1923 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1924
1925 cmd->promiscuous_flags = cpu_to_le16(flags);
1926
1927 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1928
1929 cmd->seid = cpu_to_le16(seid);
1930 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1931
1932 return status;
1933 }
1934
1935 /**
1936 * i40e_aq_set_vsi_mc_promisc_on_vlan
1937 * @hw: pointer to the hw struct
1938 * @seid: vsi number
1939 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
1940 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
1941 * @cmd_details: pointer to command details structure or NULL
1942 **/
i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw * hw,u16 seid,bool enable,u16 vid,struct i40e_asq_cmd_details * cmd_details)1943 int i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
1944 u16 seid, bool enable,
1945 u16 vid,
1946 struct i40e_asq_cmd_details *cmd_details)
1947 {
1948 struct i40e_aq_desc desc;
1949 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1950 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1951 u16 flags = 0;
1952 int status;
1953
1954 i40e_fill_default_direct_cmd_desc(&desc,
1955 i40e_aqc_opc_set_vsi_promiscuous_modes);
1956
1957 if (enable)
1958 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1959
1960 cmd->promiscuous_flags = cpu_to_le16(flags);
1961 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1962 cmd->seid = cpu_to_le16(seid);
1963 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
1964
1965 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0,
1966 cmd_details, true);
1967
1968 return status;
1969 }
1970
1971 /**
1972 * i40e_aq_set_vsi_uc_promisc_on_vlan
1973 * @hw: pointer to the hw struct
1974 * @seid: vsi number
1975 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
1976 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
1977 * @cmd_details: pointer to command details structure or NULL
1978 **/
i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw * hw,u16 seid,bool enable,u16 vid,struct i40e_asq_cmd_details * cmd_details)1979 int i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
1980 u16 seid, bool enable,
1981 u16 vid,
1982 struct i40e_asq_cmd_details *cmd_details)
1983 {
1984 struct i40e_aq_desc desc;
1985 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1986 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1987 u16 flags = 0;
1988 int status;
1989
1990 i40e_fill_default_direct_cmd_desc(&desc,
1991 i40e_aqc_opc_set_vsi_promiscuous_modes);
1992
1993 if (enable) {
1994 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1995 if (i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
1996 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
1997 }
1998
1999 cmd->promiscuous_flags = cpu_to_le16(flags);
2000 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2001 if (i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
2002 cmd->valid_flags |=
2003 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
2004 cmd->seid = cpu_to_le16(seid);
2005 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2006
2007 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0,
2008 cmd_details, true);
2009
2010 return status;
2011 }
2012
2013 /**
2014 * i40e_aq_set_vsi_bc_promisc_on_vlan
2015 * @hw: pointer to the hw struct
2016 * @seid: vsi number
2017 * @enable: set broadcast promiscuous enable/disable for a given VLAN
2018 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2019 * @cmd_details: pointer to command details structure or NULL
2020 **/
i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw * hw,u16 seid,bool enable,u16 vid,struct i40e_asq_cmd_details * cmd_details)2021 int i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2022 u16 seid, bool enable, u16 vid,
2023 struct i40e_asq_cmd_details *cmd_details)
2024 {
2025 struct i40e_aq_desc desc;
2026 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2027 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2028 u16 flags = 0;
2029 int status;
2030
2031 i40e_fill_default_direct_cmd_desc(&desc,
2032 i40e_aqc_opc_set_vsi_promiscuous_modes);
2033
2034 if (enable)
2035 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2036
2037 cmd->promiscuous_flags = cpu_to_le16(flags);
2038 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2039 cmd->seid = cpu_to_le16(seid);
2040 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2041
2042 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2043
2044 return status;
2045 }
2046
2047 /**
2048 * i40e_aq_set_vsi_broadcast
2049 * @hw: pointer to the hw struct
2050 * @seid: vsi number
2051 * @set_filter: true to set filter, false to clear filter
2052 * @cmd_details: pointer to command details structure or NULL
2053 *
2054 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2055 **/
i40e_aq_set_vsi_broadcast(struct i40e_hw * hw,u16 seid,bool set_filter,struct i40e_asq_cmd_details * cmd_details)2056 int i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2057 u16 seid, bool set_filter,
2058 struct i40e_asq_cmd_details *cmd_details)
2059 {
2060 struct i40e_aq_desc desc;
2061 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2062 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2063 int status;
2064
2065 i40e_fill_default_direct_cmd_desc(&desc,
2066 i40e_aqc_opc_set_vsi_promiscuous_modes);
2067
2068 if (set_filter)
2069 cmd->promiscuous_flags
2070 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2071 else
2072 cmd->promiscuous_flags
2073 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2074
2075 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2076 cmd->seid = cpu_to_le16(seid);
2077 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2078
2079 return status;
2080 }
2081
2082 /**
2083 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2084 * @hw: pointer to the hw struct
2085 * @seid: vsi number
2086 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2087 * @cmd_details: pointer to command details structure or NULL
2088 **/
i40e_aq_set_vsi_vlan_promisc(struct i40e_hw * hw,u16 seid,bool enable,struct i40e_asq_cmd_details * cmd_details)2089 int i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2090 u16 seid, bool enable,
2091 struct i40e_asq_cmd_details *cmd_details)
2092 {
2093 struct i40e_aq_desc desc;
2094 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2095 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2096 u16 flags = 0;
2097 int status;
2098
2099 i40e_fill_default_direct_cmd_desc(&desc,
2100 i40e_aqc_opc_set_vsi_promiscuous_modes);
2101 if (enable)
2102 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2103
2104 cmd->promiscuous_flags = cpu_to_le16(flags);
2105 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2106 cmd->seid = cpu_to_le16(seid);
2107
2108 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2109
2110 return status;
2111 }
2112
2113 /**
2114 * i40e_aq_get_vsi_params - get VSI configuration info
2115 * @hw: pointer to the hw struct
2116 * @vsi_ctx: pointer to a vsi context struct
2117 * @cmd_details: pointer to command details structure or NULL
2118 **/
i40e_aq_get_vsi_params(struct i40e_hw * hw,struct i40e_vsi_context * vsi_ctx,struct i40e_asq_cmd_details * cmd_details)2119 int i40e_aq_get_vsi_params(struct i40e_hw *hw,
2120 struct i40e_vsi_context *vsi_ctx,
2121 struct i40e_asq_cmd_details *cmd_details)
2122 {
2123 struct i40e_aq_desc desc;
2124 struct i40e_aqc_add_get_update_vsi *cmd =
2125 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2126 struct i40e_aqc_add_get_update_vsi_completion *resp =
2127 (struct i40e_aqc_add_get_update_vsi_completion *)
2128 &desc.params.raw;
2129 int status;
2130
2131 i40e_fill_default_direct_cmd_desc(&desc,
2132 i40e_aqc_opc_get_vsi_parameters);
2133
2134 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2135
2136 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2137
2138 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2139 sizeof(vsi_ctx->info), NULL);
2140
2141 if (status)
2142 goto aq_get_vsi_params_exit;
2143
2144 vsi_ctx->seid = le16_to_cpu(resp->seid);
2145 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2146 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2147 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2148
2149 aq_get_vsi_params_exit:
2150 return status;
2151 }
2152
2153 /**
2154 * i40e_aq_update_vsi_params
2155 * @hw: pointer to the hw struct
2156 * @vsi_ctx: pointer to a vsi context struct
2157 * @cmd_details: pointer to command details structure or NULL
2158 *
2159 * Update a VSI context.
2160 **/
i40e_aq_update_vsi_params(struct i40e_hw * hw,struct i40e_vsi_context * vsi_ctx,struct i40e_asq_cmd_details * cmd_details)2161 int i40e_aq_update_vsi_params(struct i40e_hw *hw,
2162 struct i40e_vsi_context *vsi_ctx,
2163 struct i40e_asq_cmd_details *cmd_details)
2164 {
2165 struct i40e_aq_desc desc;
2166 struct i40e_aqc_add_get_update_vsi *cmd =
2167 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2168 struct i40e_aqc_add_get_update_vsi_completion *resp =
2169 (struct i40e_aqc_add_get_update_vsi_completion *)
2170 &desc.params.raw;
2171 int status;
2172
2173 i40e_fill_default_direct_cmd_desc(&desc,
2174 i40e_aqc_opc_update_vsi_parameters);
2175 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2176
2177 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2178
2179 status = i40e_asq_send_command_atomic(hw, &desc, &vsi_ctx->info,
2180 sizeof(vsi_ctx->info),
2181 cmd_details, true);
2182
2183 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2184 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2185
2186 return status;
2187 }
2188
2189 /**
2190 * i40e_aq_get_switch_config
2191 * @hw: pointer to the hardware structure
2192 * @buf: pointer to the result buffer
2193 * @buf_size: length of input buffer
2194 * @start_seid: seid to start for the report, 0 == beginning
2195 * @cmd_details: pointer to command details structure or NULL
2196 *
2197 * Fill the buf with switch configuration returned from AdminQ command
2198 **/
i40e_aq_get_switch_config(struct i40e_hw * hw,struct i40e_aqc_get_switch_config_resp * buf,u16 buf_size,u16 * start_seid,struct i40e_asq_cmd_details * cmd_details)2199 int i40e_aq_get_switch_config(struct i40e_hw *hw,
2200 struct i40e_aqc_get_switch_config_resp *buf,
2201 u16 buf_size, u16 *start_seid,
2202 struct i40e_asq_cmd_details *cmd_details)
2203 {
2204 struct i40e_aq_desc desc;
2205 struct i40e_aqc_switch_seid *scfg =
2206 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2207 int status;
2208
2209 i40e_fill_default_direct_cmd_desc(&desc,
2210 i40e_aqc_opc_get_switch_config);
2211 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2212 if (buf_size > I40E_AQ_LARGE_BUF)
2213 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2214 scfg->seid = cpu_to_le16(*start_seid);
2215
2216 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2217 *start_seid = le16_to_cpu(scfg->seid);
2218
2219 return status;
2220 }
2221
2222 /**
2223 * i40e_aq_set_switch_config
2224 * @hw: pointer to the hardware structure
2225 * @flags: bit flag values to set
2226 * @mode: cloud filter mode
2227 * @valid_flags: which bit flags to set
2228 * @mode: cloud filter mode
2229 * @cmd_details: pointer to command details structure or NULL
2230 *
2231 * Set switch configuration bits
2232 **/
i40e_aq_set_switch_config(struct i40e_hw * hw,u16 flags,u16 valid_flags,u8 mode,struct i40e_asq_cmd_details * cmd_details)2233 int i40e_aq_set_switch_config(struct i40e_hw *hw,
2234 u16 flags,
2235 u16 valid_flags, u8 mode,
2236 struct i40e_asq_cmd_details *cmd_details)
2237 {
2238 struct i40e_aq_desc desc;
2239 struct i40e_aqc_set_switch_config *scfg =
2240 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2241 int status;
2242
2243 i40e_fill_default_direct_cmd_desc(&desc,
2244 i40e_aqc_opc_set_switch_config);
2245 scfg->flags = cpu_to_le16(flags);
2246 scfg->valid_flags = cpu_to_le16(valid_flags);
2247 scfg->mode = mode;
2248 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2249 scfg->switch_tag = cpu_to_le16(hw->switch_tag);
2250 scfg->first_tag = cpu_to_le16(hw->first_tag);
2251 scfg->second_tag = cpu_to_le16(hw->second_tag);
2252 }
2253 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2254
2255 return status;
2256 }
2257
2258 /**
2259 * i40e_aq_get_firmware_version
2260 * @hw: pointer to the hw struct
2261 * @fw_major_version: firmware major version
2262 * @fw_minor_version: firmware minor version
2263 * @fw_build: firmware build number
2264 * @api_major_version: major queue version
2265 * @api_minor_version: minor queue version
2266 * @cmd_details: pointer to command details structure or NULL
2267 *
2268 * Get the firmware version from the admin queue commands
2269 **/
i40e_aq_get_firmware_version(struct i40e_hw * hw,u16 * fw_major_version,u16 * fw_minor_version,u32 * fw_build,u16 * api_major_version,u16 * api_minor_version,struct i40e_asq_cmd_details * cmd_details)2270 int i40e_aq_get_firmware_version(struct i40e_hw *hw,
2271 u16 *fw_major_version, u16 *fw_minor_version,
2272 u32 *fw_build,
2273 u16 *api_major_version, u16 *api_minor_version,
2274 struct i40e_asq_cmd_details *cmd_details)
2275 {
2276 struct i40e_aq_desc desc;
2277 struct i40e_aqc_get_version *resp =
2278 (struct i40e_aqc_get_version *)&desc.params.raw;
2279 int status;
2280
2281 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2282
2283 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2284
2285 if (!status) {
2286 if (fw_major_version)
2287 *fw_major_version = le16_to_cpu(resp->fw_major);
2288 if (fw_minor_version)
2289 *fw_minor_version = le16_to_cpu(resp->fw_minor);
2290 if (fw_build)
2291 *fw_build = le32_to_cpu(resp->fw_build);
2292 if (api_major_version)
2293 *api_major_version = le16_to_cpu(resp->api_major);
2294 if (api_minor_version)
2295 *api_minor_version = le16_to_cpu(resp->api_minor);
2296 }
2297
2298 return status;
2299 }
2300
2301 /**
2302 * i40e_aq_send_driver_version
2303 * @hw: pointer to the hw struct
2304 * @dv: driver's major, minor version
2305 * @cmd_details: pointer to command details structure or NULL
2306 *
2307 * Send the driver version to the firmware
2308 **/
i40e_aq_send_driver_version(struct i40e_hw * hw,struct i40e_driver_version * dv,struct i40e_asq_cmd_details * cmd_details)2309 int i40e_aq_send_driver_version(struct i40e_hw *hw,
2310 struct i40e_driver_version *dv,
2311 struct i40e_asq_cmd_details *cmd_details)
2312 {
2313 struct i40e_aq_desc desc;
2314 struct i40e_aqc_driver_version *cmd =
2315 (struct i40e_aqc_driver_version *)&desc.params.raw;
2316 int status;
2317 u16 len;
2318
2319 if (dv == NULL)
2320 return -EINVAL;
2321
2322 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2323
2324 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2325 cmd->driver_major_ver = dv->major_version;
2326 cmd->driver_minor_ver = dv->minor_version;
2327 cmd->driver_build_ver = dv->build_version;
2328 cmd->driver_subbuild_ver = dv->subbuild_version;
2329
2330 len = 0;
2331 while (len < sizeof(dv->driver_string) &&
2332 (dv->driver_string[len] < 0x80) &&
2333 dv->driver_string[len])
2334 len++;
2335 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2336 len, cmd_details);
2337
2338 return status;
2339 }
2340
2341 /**
2342 * i40e_get_link_status - get status of the HW network link
2343 * @hw: pointer to the hw struct
2344 * @link_up: pointer to bool (true/false = linkup/linkdown)
2345 *
2346 * Variable link_up true if link is up, false if link is down.
2347 * The variable link_up is invalid if returned value of status != 0
2348 *
2349 * Side effect: LinkStatusEvent reporting becomes enabled
2350 **/
i40e_get_link_status(struct i40e_hw * hw,bool * link_up)2351 int i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2352 {
2353 int status = 0;
2354
2355 if (hw->phy.get_link_info) {
2356 status = i40e_update_link_info(hw);
2357
2358 if (status)
2359 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2360 status);
2361 }
2362
2363 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2364
2365 return status;
2366 }
2367
2368 /**
2369 * i40e_update_link_info - update status of the HW network link
2370 * @hw: pointer to the hw struct
2371 **/
i40e_update_link_info(struct i40e_hw * hw)2372 noinline_for_stack int i40e_update_link_info(struct i40e_hw *hw)
2373 {
2374 struct i40e_aq_get_phy_abilities_resp abilities;
2375 int status = 0;
2376
2377 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2378 if (status)
2379 return status;
2380
2381 /* extra checking needed to ensure link info to user is timely */
2382 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2383 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2384 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2385 status = i40e_aq_get_phy_capabilities(hw, false, false,
2386 &abilities, NULL);
2387 if (status)
2388 return status;
2389
2390 if (abilities.fec_cfg_curr_mod_ext_info &
2391 I40E_AQ_ENABLE_FEC_AUTO)
2392 hw->phy.link_info.req_fec_info =
2393 (I40E_AQ_REQUEST_FEC_KR |
2394 I40E_AQ_REQUEST_FEC_RS);
2395 else
2396 hw->phy.link_info.req_fec_info =
2397 abilities.fec_cfg_curr_mod_ext_info &
2398 (I40E_AQ_REQUEST_FEC_KR |
2399 I40E_AQ_REQUEST_FEC_RS);
2400
2401 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2402 sizeof(hw->phy.link_info.module_type));
2403 }
2404
2405 return status;
2406 }
2407
2408 /**
2409 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2410 * @hw: pointer to the hw struct
2411 * @uplink_seid: the MAC or other gizmo SEID
2412 * @downlink_seid: the VSI SEID
2413 * @enabled_tc: bitmap of TCs to be enabled
2414 * @default_port: true for default port VSI, false for control port
2415 * @veb_seid: pointer to where to put the resulting VEB SEID
2416 * @enable_stats: true to turn on VEB stats
2417 * @cmd_details: pointer to command details structure or NULL
2418 *
2419 * This asks the FW to add a VEB between the uplink and downlink
2420 * elements. If the uplink SEID is 0, this will be a floating VEB.
2421 **/
i40e_aq_add_veb(struct i40e_hw * hw,u16 uplink_seid,u16 downlink_seid,u8 enabled_tc,bool default_port,u16 * veb_seid,bool enable_stats,struct i40e_asq_cmd_details * cmd_details)2422 int i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2423 u16 downlink_seid, u8 enabled_tc,
2424 bool default_port, u16 *veb_seid,
2425 bool enable_stats,
2426 struct i40e_asq_cmd_details *cmd_details)
2427 {
2428 struct i40e_aq_desc desc;
2429 struct i40e_aqc_add_veb *cmd =
2430 (struct i40e_aqc_add_veb *)&desc.params.raw;
2431 struct i40e_aqc_add_veb_completion *resp =
2432 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2433 u16 veb_flags = 0;
2434 int status;
2435
2436 /* SEIDs need to either both be set or both be 0 for floating VEB */
2437 if (!!uplink_seid != !!downlink_seid)
2438 return -EINVAL;
2439
2440 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2441
2442 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2443 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2444 cmd->enable_tcs = enabled_tc;
2445 if (!uplink_seid)
2446 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2447 if (default_port)
2448 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2449 else
2450 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2451
2452 /* reverse logic here: set the bitflag to disable the stats */
2453 if (!enable_stats)
2454 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2455
2456 cmd->veb_flags = cpu_to_le16(veb_flags);
2457
2458 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2459
2460 if (!status && veb_seid)
2461 *veb_seid = le16_to_cpu(resp->veb_seid);
2462
2463 return status;
2464 }
2465
2466 /**
2467 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2468 * @hw: pointer to the hw struct
2469 * @veb_seid: the SEID of the VEB to query
2470 * @switch_id: the uplink switch id
2471 * @floating: set to true if the VEB is floating
2472 * @statistic_index: index of the stats counter block for this VEB
2473 * @vebs_used: number of VEB's used by function
2474 * @vebs_free: total VEB's not reserved by any function
2475 * @cmd_details: pointer to command details structure or NULL
2476 *
2477 * This retrieves the parameters for a particular VEB, specified by
2478 * uplink_seid, and returns them to the caller.
2479 **/
i40e_aq_get_veb_parameters(struct i40e_hw * hw,u16 veb_seid,u16 * switch_id,bool * floating,u16 * statistic_index,u16 * vebs_used,u16 * vebs_free,struct i40e_asq_cmd_details * cmd_details)2480 int i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2481 u16 veb_seid, u16 *switch_id,
2482 bool *floating, u16 *statistic_index,
2483 u16 *vebs_used, u16 *vebs_free,
2484 struct i40e_asq_cmd_details *cmd_details)
2485 {
2486 struct i40e_aq_desc desc;
2487 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2488 (struct i40e_aqc_get_veb_parameters_completion *)
2489 &desc.params.raw;
2490 int status;
2491
2492 if (veb_seid == 0)
2493 return -EINVAL;
2494
2495 i40e_fill_default_direct_cmd_desc(&desc,
2496 i40e_aqc_opc_get_veb_parameters);
2497 cmd_resp->seid = cpu_to_le16(veb_seid);
2498
2499 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2500 if (status)
2501 goto get_veb_exit;
2502
2503 if (switch_id)
2504 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2505 if (statistic_index)
2506 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2507 if (vebs_used)
2508 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2509 if (vebs_free)
2510 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2511 if (floating) {
2512 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2513
2514 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2515 *floating = true;
2516 else
2517 *floating = false;
2518 }
2519
2520 get_veb_exit:
2521 return status;
2522 }
2523
2524 /**
2525 * i40e_prepare_add_macvlan
2526 * @mv_list: list of macvlans to be added
2527 * @desc: pointer to AQ descriptor structure
2528 * @count: length of the list
2529 * @seid: VSI for the mac address
2530 *
2531 * Internal helper function that prepares the add macvlan request
2532 * and returns the buffer size.
2533 **/
2534 static u16
i40e_prepare_add_macvlan(struct i40e_aqc_add_macvlan_element_data * mv_list,struct i40e_aq_desc * desc,u16 count,u16 seid)2535 i40e_prepare_add_macvlan(struct i40e_aqc_add_macvlan_element_data *mv_list,
2536 struct i40e_aq_desc *desc, u16 count, u16 seid)
2537 {
2538 struct i40e_aqc_macvlan *cmd =
2539 (struct i40e_aqc_macvlan *)&desc->params.raw;
2540 u16 buf_size;
2541 int i;
2542
2543 buf_size = count * sizeof(*mv_list);
2544
2545 /* prep the rest of the request */
2546 i40e_fill_default_direct_cmd_desc(desc, i40e_aqc_opc_add_macvlan);
2547 cmd->num_addresses = cpu_to_le16(count);
2548 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2549 cmd->seid[1] = 0;
2550 cmd->seid[2] = 0;
2551
2552 for (i = 0; i < count; i++)
2553 if (is_multicast_ether_addr(mv_list[i].mac_addr))
2554 mv_list[i].flags |=
2555 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2556
2557 desc->flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2558 if (buf_size > I40E_AQ_LARGE_BUF)
2559 desc->flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2560
2561 return buf_size;
2562 }
2563
2564 /**
2565 * i40e_aq_add_macvlan
2566 * @hw: pointer to the hw struct
2567 * @seid: VSI for the mac address
2568 * @mv_list: list of macvlans to be added
2569 * @count: length of the list
2570 * @cmd_details: pointer to command details structure or NULL
2571 *
2572 * Add MAC/VLAN addresses to the HW filtering
2573 **/
2574 int
i40e_aq_add_macvlan(struct i40e_hw * hw,u16 seid,struct i40e_aqc_add_macvlan_element_data * mv_list,u16 count,struct i40e_asq_cmd_details * cmd_details)2575 i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2576 struct i40e_aqc_add_macvlan_element_data *mv_list,
2577 u16 count, struct i40e_asq_cmd_details *cmd_details)
2578 {
2579 struct i40e_aq_desc desc;
2580 u16 buf_size;
2581
2582 if (count == 0 || !mv_list || !hw)
2583 return -EINVAL;
2584
2585 buf_size = i40e_prepare_add_macvlan(mv_list, &desc, count, seid);
2586
2587 return i40e_asq_send_command_atomic(hw, &desc, mv_list, buf_size,
2588 cmd_details, true);
2589 }
2590
2591 /**
2592 * i40e_aq_add_macvlan_v2
2593 * @hw: pointer to the hw struct
2594 * @seid: VSI for the mac address
2595 * @mv_list: list of macvlans to be added
2596 * @count: length of the list
2597 * @cmd_details: pointer to command details structure or NULL
2598 * @aq_status: pointer to Admin Queue status return value
2599 *
2600 * Add MAC/VLAN addresses to the HW filtering.
2601 * The _v2 version returns the last Admin Queue status in aq_status
2602 * to avoid race conditions in access to hw->aq.asq_last_status.
2603 * It also calls _v2 versions of asq_send_command functions to
2604 * get the aq_status on the stack.
2605 **/
2606 int
i40e_aq_add_macvlan_v2(struct i40e_hw * hw,u16 seid,struct i40e_aqc_add_macvlan_element_data * mv_list,u16 count,struct i40e_asq_cmd_details * cmd_details,enum i40e_admin_queue_err * aq_status)2607 i40e_aq_add_macvlan_v2(struct i40e_hw *hw, u16 seid,
2608 struct i40e_aqc_add_macvlan_element_data *mv_list,
2609 u16 count, struct i40e_asq_cmd_details *cmd_details,
2610 enum i40e_admin_queue_err *aq_status)
2611 {
2612 struct i40e_aq_desc desc;
2613 u16 buf_size;
2614
2615 if (count == 0 || !mv_list || !hw)
2616 return -EINVAL;
2617
2618 buf_size = i40e_prepare_add_macvlan(mv_list, &desc, count, seid);
2619
2620 return i40e_asq_send_command_atomic_v2(hw, &desc, mv_list, buf_size,
2621 cmd_details, true, aq_status);
2622 }
2623
2624 /**
2625 * i40e_aq_remove_macvlan
2626 * @hw: pointer to the hw struct
2627 * @seid: VSI for the mac address
2628 * @mv_list: list of macvlans to be removed
2629 * @count: length of the list
2630 * @cmd_details: pointer to command details structure or NULL
2631 *
2632 * Remove MAC/VLAN addresses from the HW filtering
2633 **/
2634 int
i40e_aq_remove_macvlan(struct i40e_hw * hw,u16 seid,struct i40e_aqc_remove_macvlan_element_data * mv_list,u16 count,struct i40e_asq_cmd_details * cmd_details)2635 i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2636 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2637 u16 count, struct i40e_asq_cmd_details *cmd_details)
2638 {
2639 struct i40e_aq_desc desc;
2640 struct i40e_aqc_macvlan *cmd =
2641 (struct i40e_aqc_macvlan *)&desc.params.raw;
2642 u16 buf_size;
2643 int status;
2644
2645 if (count == 0 || !mv_list || !hw)
2646 return -EINVAL;
2647
2648 buf_size = count * sizeof(*mv_list);
2649
2650 /* prep the rest of the request */
2651 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2652 cmd->num_addresses = cpu_to_le16(count);
2653 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2654 cmd->seid[1] = 0;
2655 cmd->seid[2] = 0;
2656
2657 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2658 if (buf_size > I40E_AQ_LARGE_BUF)
2659 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2660
2661 status = i40e_asq_send_command_atomic(hw, &desc, mv_list, buf_size,
2662 cmd_details, true);
2663
2664 return status;
2665 }
2666
2667 /**
2668 * i40e_aq_remove_macvlan_v2
2669 * @hw: pointer to the hw struct
2670 * @seid: VSI for the mac address
2671 * @mv_list: list of macvlans to be removed
2672 * @count: length of the list
2673 * @cmd_details: pointer to command details structure or NULL
2674 * @aq_status: pointer to Admin Queue status return value
2675 *
2676 * Remove MAC/VLAN addresses from the HW filtering.
2677 * The _v2 version returns the last Admin Queue status in aq_status
2678 * to avoid race conditions in access to hw->aq.asq_last_status.
2679 * It also calls _v2 versions of asq_send_command functions to
2680 * get the aq_status on the stack.
2681 **/
2682 int
i40e_aq_remove_macvlan_v2(struct i40e_hw * hw,u16 seid,struct i40e_aqc_remove_macvlan_element_data * mv_list,u16 count,struct i40e_asq_cmd_details * cmd_details,enum i40e_admin_queue_err * aq_status)2683 i40e_aq_remove_macvlan_v2(struct i40e_hw *hw, u16 seid,
2684 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2685 u16 count, struct i40e_asq_cmd_details *cmd_details,
2686 enum i40e_admin_queue_err *aq_status)
2687 {
2688 struct i40e_aqc_macvlan *cmd;
2689 struct i40e_aq_desc desc;
2690 u16 buf_size;
2691
2692 if (count == 0 || !mv_list || !hw)
2693 return -EINVAL;
2694
2695 buf_size = count * sizeof(*mv_list);
2696
2697 /* prep the rest of the request */
2698 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2699 cmd = (struct i40e_aqc_macvlan *)&desc.params.raw;
2700 cmd->num_addresses = cpu_to_le16(count);
2701 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2702 cmd->seid[1] = 0;
2703 cmd->seid[2] = 0;
2704
2705 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2706 if (buf_size > I40E_AQ_LARGE_BUF)
2707 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2708
2709 return i40e_asq_send_command_atomic_v2(hw, &desc, mv_list, buf_size,
2710 cmd_details, true, aq_status);
2711 }
2712
2713 /**
2714 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2715 * @hw: pointer to the hw struct
2716 * @opcode: AQ opcode for add or delete mirror rule
2717 * @sw_seid: Switch SEID (to which rule refers)
2718 * @rule_type: Rule Type (ingress/egress/VLAN)
2719 * @id: Destination VSI SEID or Rule ID
2720 * @count: length of the list
2721 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2722 * @cmd_details: pointer to command details structure or NULL
2723 * @rule_id: Rule ID returned from FW
2724 * @rules_used: Number of rules used in internal switch
2725 * @rules_free: Number of rules free in internal switch
2726 *
2727 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2728 * VEBs/VEPA elements only
2729 **/
i40e_mirrorrule_op(struct i40e_hw * hw,u16 opcode,u16 sw_seid,u16 rule_type,u16 id,u16 count,__le16 * mr_list,struct i40e_asq_cmd_details * cmd_details,u16 * rule_id,u16 * rules_used,u16 * rules_free)2730 static int i40e_mirrorrule_op(struct i40e_hw *hw,
2731 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2732 u16 count, __le16 *mr_list,
2733 struct i40e_asq_cmd_details *cmd_details,
2734 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2735 {
2736 struct i40e_aq_desc desc;
2737 struct i40e_aqc_add_delete_mirror_rule *cmd =
2738 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2739 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2740 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2741 u16 buf_size;
2742 int status;
2743
2744 buf_size = count * sizeof(*mr_list);
2745
2746 /* prep the rest of the request */
2747 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2748 cmd->seid = cpu_to_le16(sw_seid);
2749 cmd->rule_type = cpu_to_le16(rule_type &
2750 I40E_AQC_MIRROR_RULE_TYPE_MASK);
2751 cmd->num_entries = cpu_to_le16(count);
2752 /* Dest VSI for add, rule_id for delete */
2753 cmd->destination = cpu_to_le16(id);
2754 if (mr_list) {
2755 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2756 I40E_AQ_FLAG_RD));
2757 if (buf_size > I40E_AQ_LARGE_BUF)
2758 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2759 }
2760
2761 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2762 cmd_details);
2763 if (!status ||
2764 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2765 if (rule_id)
2766 *rule_id = le16_to_cpu(resp->rule_id);
2767 if (rules_used)
2768 *rules_used = le16_to_cpu(resp->mirror_rules_used);
2769 if (rules_free)
2770 *rules_free = le16_to_cpu(resp->mirror_rules_free);
2771 }
2772 return status;
2773 }
2774
2775 /**
2776 * i40e_aq_add_mirrorrule - add a mirror rule
2777 * @hw: pointer to the hw struct
2778 * @sw_seid: Switch SEID (to which rule refers)
2779 * @rule_type: Rule Type (ingress/egress/VLAN)
2780 * @dest_vsi: SEID of VSI to which packets will be mirrored
2781 * @count: length of the list
2782 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2783 * @cmd_details: pointer to command details structure or NULL
2784 * @rule_id: Rule ID returned from FW
2785 * @rules_used: Number of rules used in internal switch
2786 * @rules_free: Number of rules free in internal switch
2787 *
2788 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2789 **/
i40e_aq_add_mirrorrule(struct i40e_hw * hw,u16 sw_seid,u16 rule_type,u16 dest_vsi,u16 count,__le16 * mr_list,struct i40e_asq_cmd_details * cmd_details,u16 * rule_id,u16 * rules_used,u16 * rules_free)2790 int i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2791 u16 rule_type, u16 dest_vsi, u16 count,
2792 __le16 *mr_list,
2793 struct i40e_asq_cmd_details *cmd_details,
2794 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2795 {
2796 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2797 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2798 if (count == 0 || !mr_list)
2799 return -EINVAL;
2800 }
2801
2802 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2803 rule_type, dest_vsi, count, mr_list,
2804 cmd_details, rule_id, rules_used, rules_free);
2805 }
2806
2807 /**
2808 * i40e_aq_delete_mirrorrule - delete a mirror rule
2809 * @hw: pointer to the hw struct
2810 * @sw_seid: Switch SEID (to which rule refers)
2811 * @rule_type: Rule Type (ingress/egress/VLAN)
2812 * @count: length of the list
2813 * @rule_id: Rule ID that is returned in the receive desc as part of
2814 * add_mirrorrule.
2815 * @mr_list: list of mirrored VLAN IDs to be removed
2816 * @cmd_details: pointer to command details structure or NULL
2817 * @rules_used: Number of rules used in internal switch
2818 * @rules_free: Number of rules free in internal switch
2819 *
2820 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2821 **/
i40e_aq_delete_mirrorrule(struct i40e_hw * hw,u16 sw_seid,u16 rule_type,u16 rule_id,u16 count,__le16 * mr_list,struct i40e_asq_cmd_details * cmd_details,u16 * rules_used,u16 * rules_free)2822 int i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2823 u16 rule_type, u16 rule_id, u16 count,
2824 __le16 *mr_list,
2825 struct i40e_asq_cmd_details *cmd_details,
2826 u16 *rules_used, u16 *rules_free)
2827 {
2828 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
2829 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
2830 /* count and mr_list shall be valid for rule_type INGRESS VLAN
2831 * mirroring. For other rule_type, count and rule_type should
2832 * not matter.
2833 */
2834 if (count == 0 || !mr_list)
2835 return -EINVAL;
2836 }
2837
2838 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2839 rule_type, rule_id, count, mr_list,
2840 cmd_details, NULL, rules_used, rules_free);
2841 }
2842
2843 /**
2844 * i40e_aq_send_msg_to_vf
2845 * @hw: pointer to the hardware structure
2846 * @vfid: VF id to send msg
2847 * @v_opcode: opcodes for VF-PF communication
2848 * @v_retval: return error code
2849 * @msg: pointer to the msg buffer
2850 * @msglen: msg length
2851 * @cmd_details: pointer to command details
2852 *
2853 * send msg to vf
2854 **/
i40e_aq_send_msg_to_vf(struct i40e_hw * hw,u16 vfid,u32 v_opcode,u32 v_retval,u8 * msg,u16 msglen,struct i40e_asq_cmd_details * cmd_details)2855 int i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2856 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2857 struct i40e_asq_cmd_details *cmd_details)
2858 {
2859 struct i40e_aq_desc desc;
2860 struct i40e_aqc_pf_vf_message *cmd =
2861 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2862 int status;
2863
2864 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2865 cmd->id = cpu_to_le32(vfid);
2866 desc.cookie_high = cpu_to_le32(v_opcode);
2867 desc.cookie_low = cpu_to_le32(v_retval);
2868 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2869 if (msglen) {
2870 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2871 I40E_AQ_FLAG_RD));
2872 if (msglen > I40E_AQ_LARGE_BUF)
2873 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2874 desc.datalen = cpu_to_le16(msglen);
2875 }
2876 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2877
2878 return status;
2879 }
2880
2881 /**
2882 * i40e_aq_debug_read_register
2883 * @hw: pointer to the hw struct
2884 * @reg_addr: register address
2885 * @reg_val: register value
2886 * @cmd_details: pointer to command details structure or NULL
2887 *
2888 * Read the register using the admin queue commands
2889 **/
i40e_aq_debug_read_register(struct i40e_hw * hw,u32 reg_addr,u64 * reg_val,struct i40e_asq_cmd_details * cmd_details)2890 int i40e_aq_debug_read_register(struct i40e_hw *hw,
2891 u32 reg_addr, u64 *reg_val,
2892 struct i40e_asq_cmd_details *cmd_details)
2893 {
2894 struct i40e_aq_desc desc;
2895 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2896 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2897 int status;
2898
2899 if (reg_val == NULL)
2900 return -EINVAL;
2901
2902 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2903
2904 cmd_resp->address = cpu_to_le32(reg_addr);
2905
2906 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2907
2908 if (!status) {
2909 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2910 (u64)le32_to_cpu(cmd_resp->value_low);
2911 }
2912
2913 return status;
2914 }
2915
2916 /**
2917 * i40e_aq_debug_write_register
2918 * @hw: pointer to the hw struct
2919 * @reg_addr: register address
2920 * @reg_val: register value
2921 * @cmd_details: pointer to command details structure or NULL
2922 *
2923 * Write to a register using the admin queue commands
2924 **/
i40e_aq_debug_write_register(struct i40e_hw * hw,u32 reg_addr,u64 reg_val,struct i40e_asq_cmd_details * cmd_details)2925 int i40e_aq_debug_write_register(struct i40e_hw *hw,
2926 u32 reg_addr, u64 reg_val,
2927 struct i40e_asq_cmd_details *cmd_details)
2928 {
2929 struct i40e_aq_desc desc;
2930 struct i40e_aqc_debug_reg_read_write *cmd =
2931 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2932 int status;
2933
2934 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2935
2936 cmd->address = cpu_to_le32(reg_addr);
2937 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2938 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2939
2940 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2941
2942 return status;
2943 }
2944
2945 /**
2946 * i40e_aq_request_resource
2947 * @hw: pointer to the hw struct
2948 * @resource: resource id
2949 * @access: access type
2950 * @sdp_number: resource number
2951 * @timeout: the maximum time in ms that the driver may hold the resource
2952 * @cmd_details: pointer to command details structure or NULL
2953 *
2954 * requests common resource using the admin queue commands
2955 **/
i40e_aq_request_resource(struct i40e_hw * hw,enum i40e_aq_resources_ids resource,enum i40e_aq_resource_access_type access,u8 sdp_number,u64 * timeout,struct i40e_asq_cmd_details * cmd_details)2956 int i40e_aq_request_resource(struct i40e_hw *hw,
2957 enum i40e_aq_resources_ids resource,
2958 enum i40e_aq_resource_access_type access,
2959 u8 sdp_number, u64 *timeout,
2960 struct i40e_asq_cmd_details *cmd_details)
2961 {
2962 struct i40e_aq_desc desc;
2963 struct i40e_aqc_request_resource *cmd_resp =
2964 (struct i40e_aqc_request_resource *)&desc.params.raw;
2965 int status;
2966
2967 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2968
2969 cmd_resp->resource_id = cpu_to_le16(resource);
2970 cmd_resp->access_type = cpu_to_le16(access);
2971 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2972
2973 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2974 /* The completion specifies the maximum time in ms that the driver
2975 * may hold the resource in the Timeout field.
2976 * If the resource is held by someone else, the command completes with
2977 * busy return value and the timeout field indicates the maximum time
2978 * the current owner of the resource has to free it.
2979 */
2980 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2981 *timeout = le32_to_cpu(cmd_resp->timeout);
2982
2983 return status;
2984 }
2985
2986 /**
2987 * i40e_aq_release_resource
2988 * @hw: pointer to the hw struct
2989 * @resource: resource id
2990 * @sdp_number: resource number
2991 * @cmd_details: pointer to command details structure or NULL
2992 *
2993 * release common resource using the admin queue commands
2994 **/
i40e_aq_release_resource(struct i40e_hw * hw,enum i40e_aq_resources_ids resource,u8 sdp_number,struct i40e_asq_cmd_details * cmd_details)2995 int i40e_aq_release_resource(struct i40e_hw *hw,
2996 enum i40e_aq_resources_ids resource,
2997 u8 sdp_number,
2998 struct i40e_asq_cmd_details *cmd_details)
2999 {
3000 struct i40e_aq_desc desc;
3001 struct i40e_aqc_request_resource *cmd =
3002 (struct i40e_aqc_request_resource *)&desc.params.raw;
3003 int status;
3004
3005 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3006
3007 cmd->resource_id = cpu_to_le16(resource);
3008 cmd->resource_number = cpu_to_le32(sdp_number);
3009
3010 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3011
3012 return status;
3013 }
3014
3015 /**
3016 * i40e_aq_read_nvm
3017 * @hw: pointer to the hw struct
3018 * @module_pointer: module pointer location in words from the NVM beginning
3019 * @offset: byte offset from the module beginning
3020 * @length: length of the section to be read (in bytes from the offset)
3021 * @data: command buffer (size [bytes] = length)
3022 * @last_command: tells if this is the last command in a series
3023 * @cmd_details: pointer to command details structure or NULL
3024 *
3025 * Read the NVM using the admin queue commands
3026 **/
i40e_aq_read_nvm(struct i40e_hw * hw,u8 module_pointer,u32 offset,u16 length,void * data,bool last_command,struct i40e_asq_cmd_details * cmd_details)3027 int i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3028 u32 offset, u16 length, void *data,
3029 bool last_command,
3030 struct i40e_asq_cmd_details *cmd_details)
3031 {
3032 struct i40e_aq_desc desc;
3033 struct i40e_aqc_nvm_update *cmd =
3034 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3035 int status;
3036
3037 /* In offset the highest byte must be zeroed. */
3038 if (offset & 0xFF000000) {
3039 status = -EINVAL;
3040 goto i40e_aq_read_nvm_exit;
3041 }
3042
3043 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3044
3045 /* If this is the last command in a series, set the proper flag. */
3046 if (last_command)
3047 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3048 cmd->module_pointer = module_pointer;
3049 cmd->offset = cpu_to_le32(offset);
3050 cmd->length = cpu_to_le16(length);
3051
3052 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3053 if (length > I40E_AQ_LARGE_BUF)
3054 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3055
3056 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3057
3058 i40e_aq_read_nvm_exit:
3059 return status;
3060 }
3061
3062 /**
3063 * i40e_aq_erase_nvm
3064 * @hw: pointer to the hw struct
3065 * @module_pointer: module pointer location in words from the NVM beginning
3066 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3067 * @length: length of the section to be erased (expressed in 4 KB)
3068 * @last_command: tells if this is the last command in a series
3069 * @cmd_details: pointer to command details structure or NULL
3070 *
3071 * Erase the NVM sector using the admin queue commands
3072 **/
i40e_aq_erase_nvm(struct i40e_hw * hw,u8 module_pointer,u32 offset,u16 length,bool last_command,struct i40e_asq_cmd_details * cmd_details)3073 int i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3074 u32 offset, u16 length, bool last_command,
3075 struct i40e_asq_cmd_details *cmd_details)
3076 {
3077 struct i40e_aq_desc desc;
3078 struct i40e_aqc_nvm_update *cmd =
3079 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3080 int status;
3081
3082 /* In offset the highest byte must be zeroed. */
3083 if (offset & 0xFF000000) {
3084 status = -EINVAL;
3085 goto i40e_aq_erase_nvm_exit;
3086 }
3087
3088 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3089
3090 /* If this is the last command in a series, set the proper flag. */
3091 if (last_command)
3092 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3093 cmd->module_pointer = module_pointer;
3094 cmd->offset = cpu_to_le32(offset);
3095 cmd->length = cpu_to_le16(length);
3096
3097 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3098
3099 i40e_aq_erase_nvm_exit:
3100 return status;
3101 }
3102
3103 /**
3104 * i40e_parse_discover_capabilities
3105 * @hw: pointer to the hw struct
3106 * @buff: pointer to a buffer containing device/function capability records
3107 * @cap_count: number of capability records in the list
3108 * @list_type_opc: type of capabilities list to parse
3109 *
3110 * Parse the device/function capabilities list.
3111 **/
i40e_parse_discover_capabilities(struct i40e_hw * hw,void * buff,u32 cap_count,enum i40e_admin_queue_opc list_type_opc)3112 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3113 u32 cap_count,
3114 enum i40e_admin_queue_opc list_type_opc)
3115 {
3116 struct i40e_aqc_list_capabilities_element_resp *cap;
3117 u32 valid_functions, num_functions;
3118 u32 number, logical_id, phys_id;
3119 struct i40e_hw_capabilities *p;
3120 u16 id, ocp_cfg_word0;
3121 u8 major_rev;
3122 int status;
3123 u32 i = 0;
3124
3125 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3126
3127 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3128 p = &hw->dev_caps;
3129 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3130 p = &hw->func_caps;
3131 else
3132 return;
3133
3134 for (i = 0; i < cap_count; i++, cap++) {
3135 id = le16_to_cpu(cap->id);
3136 number = le32_to_cpu(cap->number);
3137 logical_id = le32_to_cpu(cap->logical_id);
3138 phys_id = le32_to_cpu(cap->phys_id);
3139 major_rev = cap->major_rev;
3140
3141 switch (id) {
3142 case I40E_AQ_CAP_ID_SWITCH_MODE:
3143 p->switch_mode = number;
3144 break;
3145 case I40E_AQ_CAP_ID_MNG_MODE:
3146 p->management_mode = number;
3147 if (major_rev > 1) {
3148 p->mng_protocols_over_mctp = logical_id;
3149 i40e_debug(hw, I40E_DEBUG_INIT,
3150 "HW Capability: Protocols over MCTP = %d\n",
3151 p->mng_protocols_over_mctp);
3152 } else {
3153 p->mng_protocols_over_mctp = 0;
3154 }
3155 break;
3156 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3157 p->npar_enable = number;
3158 break;
3159 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3160 p->os2bmc = number;
3161 break;
3162 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3163 p->valid_functions = number;
3164 break;
3165 case I40E_AQ_CAP_ID_SRIOV:
3166 if (number == 1)
3167 p->sr_iov_1_1 = true;
3168 break;
3169 case I40E_AQ_CAP_ID_VF:
3170 p->num_vfs = number;
3171 p->vf_base_id = logical_id;
3172 break;
3173 case I40E_AQ_CAP_ID_VMDQ:
3174 if (number == 1)
3175 p->vmdq = true;
3176 break;
3177 case I40E_AQ_CAP_ID_8021QBG:
3178 if (number == 1)
3179 p->evb_802_1_qbg = true;
3180 break;
3181 case I40E_AQ_CAP_ID_8021QBR:
3182 if (number == 1)
3183 p->evb_802_1_qbh = true;
3184 break;
3185 case I40E_AQ_CAP_ID_VSI:
3186 p->num_vsis = number;
3187 break;
3188 case I40E_AQ_CAP_ID_DCB:
3189 if (number == 1) {
3190 p->dcb = true;
3191 p->enabled_tcmap = logical_id;
3192 p->maxtc = phys_id;
3193 }
3194 break;
3195 case I40E_AQ_CAP_ID_FCOE:
3196 if (number == 1)
3197 p->fcoe = true;
3198 break;
3199 case I40E_AQ_CAP_ID_ISCSI:
3200 if (number == 1)
3201 p->iscsi = true;
3202 break;
3203 case I40E_AQ_CAP_ID_RSS:
3204 p->rss = true;
3205 p->rss_table_size = number;
3206 p->rss_table_entry_width = logical_id;
3207 break;
3208 case I40E_AQ_CAP_ID_RXQ:
3209 p->num_rx_qp = number;
3210 p->base_queue = phys_id;
3211 break;
3212 case I40E_AQ_CAP_ID_TXQ:
3213 p->num_tx_qp = number;
3214 p->base_queue = phys_id;
3215 break;
3216 case I40E_AQ_CAP_ID_MSIX:
3217 p->num_msix_vectors = number;
3218 i40e_debug(hw, I40E_DEBUG_INIT,
3219 "HW Capability: MSIX vector count = %d\n",
3220 p->num_msix_vectors);
3221 break;
3222 case I40E_AQ_CAP_ID_VF_MSIX:
3223 p->num_msix_vectors_vf = number;
3224 break;
3225 case I40E_AQ_CAP_ID_FLEX10:
3226 if (major_rev == 1) {
3227 if (number == 1) {
3228 p->flex10_enable = true;
3229 p->flex10_capable = true;
3230 }
3231 } else {
3232 /* Capability revision >= 2 */
3233 if (number & 1)
3234 p->flex10_enable = true;
3235 if (number & 2)
3236 p->flex10_capable = true;
3237 }
3238 p->flex10_mode = logical_id;
3239 p->flex10_status = phys_id;
3240 break;
3241 case I40E_AQ_CAP_ID_CEM:
3242 if (number == 1)
3243 p->mgmt_cem = true;
3244 break;
3245 case I40E_AQ_CAP_ID_IWARP:
3246 if (number == 1)
3247 p->iwarp = true;
3248 break;
3249 case I40E_AQ_CAP_ID_LED:
3250 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3251 p->led[phys_id] = true;
3252 break;
3253 case I40E_AQ_CAP_ID_SDP:
3254 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3255 p->sdp[phys_id] = true;
3256 break;
3257 case I40E_AQ_CAP_ID_MDIO:
3258 if (number == 1) {
3259 p->mdio_port_num = phys_id;
3260 p->mdio_port_mode = logical_id;
3261 }
3262 break;
3263 case I40E_AQ_CAP_ID_1588:
3264 if (number == 1)
3265 p->ieee_1588 = true;
3266 break;
3267 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3268 p->fd = true;
3269 p->fd_filters_guaranteed = number;
3270 p->fd_filters_best_effort = logical_id;
3271 break;
3272 case I40E_AQ_CAP_ID_WSR_PROT:
3273 p->wr_csr_prot = (u64)number;
3274 p->wr_csr_prot |= (u64)logical_id << 32;
3275 break;
3276 case I40E_AQ_CAP_ID_NVM_MGMT:
3277 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3278 p->sec_rev_disabled = true;
3279 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3280 p->update_disabled = true;
3281 break;
3282 default:
3283 break;
3284 }
3285 }
3286
3287 if (p->fcoe)
3288 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3289
3290 /* Software override ensuring FCoE is disabled if npar or mfp
3291 * mode because it is not supported in these modes.
3292 */
3293 if (p->npar_enable || p->flex10_enable)
3294 p->fcoe = false;
3295
3296 /* count the enabled ports (aka the "not disabled" ports) */
3297 hw->num_ports = 0;
3298 for (i = 0; i < 4; i++) {
3299 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3300 u64 port_cfg = 0;
3301
3302 /* use AQ read to get the physical register offset instead
3303 * of the port relative offset
3304 */
3305 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3306 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3307 hw->num_ports++;
3308 }
3309
3310 /* OCP cards case: if a mezz is removed the Ethernet port is at
3311 * disabled state in PRTGEN_CNF register. Additional NVM read is
3312 * needed in order to check if we are dealing with OCP card.
3313 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
3314 * physical ports results in wrong partition id calculation and thus
3315 * not supporting WoL.
3316 */
3317 if (hw->mac.type == I40E_MAC_X722) {
3318 if (!i40e_acquire_nvm(hw, I40E_RESOURCE_READ)) {
3319 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
3320 2 * I40E_SR_OCP_CFG_WORD0,
3321 sizeof(ocp_cfg_word0),
3322 &ocp_cfg_word0, true, NULL);
3323 if (!status &&
3324 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
3325 hw->num_ports = 4;
3326 i40e_release_nvm(hw);
3327 }
3328 }
3329
3330 valid_functions = p->valid_functions;
3331 num_functions = 0;
3332 while (valid_functions) {
3333 if (valid_functions & 1)
3334 num_functions++;
3335 valid_functions >>= 1;
3336 }
3337
3338 /* partition id is 1-based, and functions are evenly spread
3339 * across the ports as partitions
3340 */
3341 if (hw->num_ports != 0) {
3342 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3343 hw->num_partitions = num_functions / hw->num_ports;
3344 }
3345
3346 /* additional HW specific goodies that might
3347 * someday be HW version specific
3348 */
3349 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3350 }
3351
3352 /**
3353 * i40e_aq_discover_capabilities
3354 * @hw: pointer to the hw struct
3355 * @buff: a virtual buffer to hold the capabilities
3356 * @buff_size: Size of the virtual buffer
3357 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3358 * @list_type_opc: capabilities type to discover - pass in the command opcode
3359 * @cmd_details: pointer to command details structure or NULL
3360 *
3361 * Get the device capabilities descriptions from the firmware
3362 **/
i40e_aq_discover_capabilities(struct i40e_hw * hw,void * buff,u16 buff_size,u16 * data_size,enum i40e_admin_queue_opc list_type_opc,struct i40e_asq_cmd_details * cmd_details)3363 int i40e_aq_discover_capabilities(struct i40e_hw *hw,
3364 void *buff, u16 buff_size, u16 *data_size,
3365 enum i40e_admin_queue_opc list_type_opc,
3366 struct i40e_asq_cmd_details *cmd_details)
3367 {
3368 struct i40e_aqc_list_capabilites *cmd;
3369 struct i40e_aq_desc desc;
3370 int status = 0;
3371
3372 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3373
3374 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3375 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3376 status = -EINVAL;
3377 goto exit;
3378 }
3379
3380 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3381
3382 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3383 if (buff_size > I40E_AQ_LARGE_BUF)
3384 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3385
3386 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3387 *data_size = le16_to_cpu(desc.datalen);
3388
3389 if (status)
3390 goto exit;
3391
3392 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3393 list_type_opc);
3394
3395 exit:
3396 return status;
3397 }
3398
3399 /**
3400 * i40e_aq_update_nvm
3401 * @hw: pointer to the hw struct
3402 * @module_pointer: module pointer location in words from the NVM beginning
3403 * @offset: byte offset from the module beginning
3404 * @length: length of the section to be written (in bytes from the offset)
3405 * @data: command buffer (size [bytes] = length)
3406 * @last_command: tells if this is the last command in a series
3407 * @preservation_flags: Preservation mode flags
3408 * @cmd_details: pointer to command details structure or NULL
3409 *
3410 * Update the NVM using the admin queue commands
3411 **/
i40e_aq_update_nvm(struct i40e_hw * hw,u8 module_pointer,u32 offset,u16 length,void * data,bool last_command,u8 preservation_flags,struct i40e_asq_cmd_details * cmd_details)3412 int i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3413 u32 offset, u16 length, void *data,
3414 bool last_command, u8 preservation_flags,
3415 struct i40e_asq_cmd_details *cmd_details)
3416 {
3417 struct i40e_aq_desc desc;
3418 struct i40e_aqc_nvm_update *cmd =
3419 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3420 int status;
3421
3422 /* In offset the highest byte must be zeroed. */
3423 if (offset & 0xFF000000) {
3424 status = -EINVAL;
3425 goto i40e_aq_update_nvm_exit;
3426 }
3427
3428 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3429
3430 /* If this is the last command in a series, set the proper flag. */
3431 if (last_command)
3432 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3433 if (hw->mac.type == I40E_MAC_X722) {
3434 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
3435 cmd->command_flags |=
3436 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
3437 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
3438 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
3439 cmd->command_flags |=
3440 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
3441 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
3442 }
3443 cmd->module_pointer = module_pointer;
3444 cmd->offset = cpu_to_le32(offset);
3445 cmd->length = cpu_to_le16(length);
3446
3447 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3448 if (length > I40E_AQ_LARGE_BUF)
3449 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3450
3451 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3452
3453 i40e_aq_update_nvm_exit:
3454 return status;
3455 }
3456
3457 /**
3458 * i40e_aq_rearrange_nvm
3459 * @hw: pointer to the hw struct
3460 * @rearrange_nvm: defines direction of rearrangement
3461 * @cmd_details: pointer to command details structure or NULL
3462 *
3463 * Rearrange NVM structure, available only for transition FW
3464 **/
i40e_aq_rearrange_nvm(struct i40e_hw * hw,u8 rearrange_nvm,struct i40e_asq_cmd_details * cmd_details)3465 int i40e_aq_rearrange_nvm(struct i40e_hw *hw,
3466 u8 rearrange_nvm,
3467 struct i40e_asq_cmd_details *cmd_details)
3468 {
3469 struct i40e_aqc_nvm_update *cmd;
3470 struct i40e_aq_desc desc;
3471 int status;
3472
3473 cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
3474
3475 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3476
3477 rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
3478 I40E_AQ_NVM_REARRANGE_TO_STRUCT);
3479
3480 if (!rearrange_nvm) {
3481 status = -EINVAL;
3482 goto i40e_aq_rearrange_nvm_exit;
3483 }
3484
3485 cmd->command_flags |= rearrange_nvm;
3486 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3487
3488 i40e_aq_rearrange_nvm_exit:
3489 return status;
3490 }
3491
3492 /**
3493 * i40e_aq_get_lldp_mib
3494 * @hw: pointer to the hw struct
3495 * @bridge_type: type of bridge requested
3496 * @mib_type: Local, Remote or both Local and Remote MIBs
3497 * @buff: pointer to a user supplied buffer to store the MIB block
3498 * @buff_size: size of the buffer (in bytes)
3499 * @local_len : length of the returned Local LLDP MIB
3500 * @remote_len: length of the returned Remote LLDP MIB
3501 * @cmd_details: pointer to command details structure or NULL
3502 *
3503 * Requests the complete LLDP MIB (entire packet).
3504 **/
i40e_aq_get_lldp_mib(struct i40e_hw * hw,u8 bridge_type,u8 mib_type,void * buff,u16 buff_size,u16 * local_len,u16 * remote_len,struct i40e_asq_cmd_details * cmd_details)3505 int i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3506 u8 mib_type, void *buff, u16 buff_size,
3507 u16 *local_len, u16 *remote_len,
3508 struct i40e_asq_cmd_details *cmd_details)
3509 {
3510 struct i40e_aq_desc desc;
3511 struct i40e_aqc_lldp_get_mib *cmd =
3512 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3513 struct i40e_aqc_lldp_get_mib *resp =
3514 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3515 int status;
3516
3517 if (buff_size == 0 || !buff)
3518 return -EINVAL;
3519
3520 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3521 /* Indirect Command */
3522 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3523
3524 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3525 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3526 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3527
3528 desc.datalen = cpu_to_le16(buff_size);
3529
3530 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3531 if (buff_size > I40E_AQ_LARGE_BUF)
3532 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3533
3534 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3535 if (!status) {
3536 if (local_len != NULL)
3537 *local_len = le16_to_cpu(resp->local_len);
3538 if (remote_len != NULL)
3539 *remote_len = le16_to_cpu(resp->remote_len);
3540 }
3541
3542 return status;
3543 }
3544
3545 /**
3546 * i40e_aq_set_lldp_mib - Set the LLDP MIB
3547 * @hw: pointer to the hw struct
3548 * @mib_type: Local, Remote or both Local and Remote MIBs
3549 * @buff: pointer to a user supplied buffer to store the MIB block
3550 * @buff_size: size of the buffer (in bytes)
3551 * @cmd_details: pointer to command details structure or NULL
3552 *
3553 * Set the LLDP MIB.
3554 **/
3555 int
i40e_aq_set_lldp_mib(struct i40e_hw * hw,u8 mib_type,void * buff,u16 buff_size,struct i40e_asq_cmd_details * cmd_details)3556 i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3557 u8 mib_type, void *buff, u16 buff_size,
3558 struct i40e_asq_cmd_details *cmd_details)
3559 {
3560 struct i40e_aqc_lldp_set_local_mib *cmd;
3561 struct i40e_aq_desc desc;
3562 int status;
3563
3564 cmd = (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3565 if (buff_size == 0 || !buff)
3566 return -EINVAL;
3567
3568 i40e_fill_default_direct_cmd_desc(&desc,
3569 i40e_aqc_opc_lldp_set_local_mib);
3570 /* Indirect Command */
3571 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3572 if (buff_size > I40E_AQ_LARGE_BUF)
3573 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3574 desc.datalen = cpu_to_le16(buff_size);
3575
3576 cmd->type = mib_type;
3577 cmd->length = cpu_to_le16(buff_size);
3578 cmd->address_high = cpu_to_le32(upper_32_bits((uintptr_t)buff));
3579 cmd->address_low = cpu_to_le32(lower_32_bits((uintptr_t)buff));
3580
3581 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3582 return status;
3583 }
3584
3585 /**
3586 * i40e_aq_cfg_lldp_mib_change_event
3587 * @hw: pointer to the hw struct
3588 * @enable_update: Enable or Disable event posting
3589 * @cmd_details: pointer to command details structure or NULL
3590 *
3591 * Enable or Disable posting of an event on ARQ when LLDP MIB
3592 * associated with the interface changes
3593 **/
i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw * hw,bool enable_update,struct i40e_asq_cmd_details * cmd_details)3594 int i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3595 bool enable_update,
3596 struct i40e_asq_cmd_details *cmd_details)
3597 {
3598 struct i40e_aq_desc desc;
3599 struct i40e_aqc_lldp_update_mib *cmd =
3600 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3601 int status;
3602
3603 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3604
3605 if (!enable_update)
3606 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3607
3608 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3609
3610 return status;
3611 }
3612
3613 /**
3614 * i40e_aq_restore_lldp
3615 * @hw: pointer to the hw struct
3616 * @setting: pointer to factory setting variable or NULL
3617 * @restore: True if factory settings should be restored
3618 * @cmd_details: pointer to command details structure or NULL
3619 *
3620 * Restore LLDP Agent factory settings if @restore set to True. In other case
3621 * only returns factory setting in AQ response.
3622 **/
3623 int
i40e_aq_restore_lldp(struct i40e_hw * hw,u8 * setting,bool restore,struct i40e_asq_cmd_details * cmd_details)3624 i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,
3625 struct i40e_asq_cmd_details *cmd_details)
3626 {
3627 struct i40e_aq_desc desc;
3628 struct i40e_aqc_lldp_restore *cmd =
3629 (struct i40e_aqc_lldp_restore *)&desc.params.raw;
3630 int status;
3631
3632 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) {
3633 i40e_debug(hw, I40E_DEBUG_ALL,
3634 "Restore LLDP not supported by current FW version.\n");
3635 return -ENODEV;
3636 }
3637
3638 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore);
3639
3640 if (restore)
3641 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE;
3642
3643 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3644
3645 if (setting)
3646 *setting = cmd->command & 1;
3647
3648 return status;
3649 }
3650
3651 /**
3652 * i40e_aq_stop_lldp
3653 * @hw: pointer to the hw struct
3654 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3655 * @persist: True if stop of LLDP should be persistent across power cycles
3656 * @cmd_details: pointer to command details structure or NULL
3657 *
3658 * Stop or Shutdown the embedded LLDP Agent
3659 **/
i40e_aq_stop_lldp(struct i40e_hw * hw,bool shutdown_agent,bool persist,struct i40e_asq_cmd_details * cmd_details)3660 int i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3661 bool persist,
3662 struct i40e_asq_cmd_details *cmd_details)
3663 {
3664 struct i40e_aq_desc desc;
3665 struct i40e_aqc_lldp_stop *cmd =
3666 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3667 int status;
3668
3669 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3670
3671 if (shutdown_agent)
3672 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3673
3674 if (persist) {
3675 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
3676 cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST;
3677 else
3678 i40e_debug(hw, I40E_DEBUG_ALL,
3679 "Persistent Stop LLDP not supported by current FW version.\n");
3680 }
3681
3682 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3683
3684 return status;
3685 }
3686
3687 /**
3688 * i40e_aq_start_lldp
3689 * @hw: pointer to the hw struct
3690 * @persist: True if start of LLDP should be persistent across power cycles
3691 * @cmd_details: pointer to command details structure or NULL
3692 *
3693 * Start the embedded LLDP Agent on all ports.
3694 **/
i40e_aq_start_lldp(struct i40e_hw * hw,bool persist,struct i40e_asq_cmd_details * cmd_details)3695 int i40e_aq_start_lldp(struct i40e_hw *hw, bool persist,
3696 struct i40e_asq_cmd_details *cmd_details)
3697 {
3698 struct i40e_aq_desc desc;
3699 struct i40e_aqc_lldp_start *cmd =
3700 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3701 int status;
3702
3703 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3704
3705 cmd->command = I40E_AQ_LLDP_AGENT_START;
3706
3707 if (persist) {
3708 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
3709 cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST;
3710 else
3711 i40e_debug(hw, I40E_DEBUG_ALL,
3712 "Persistent Start LLDP not supported by current FW version.\n");
3713 }
3714
3715 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3716
3717 return status;
3718 }
3719
3720 /**
3721 * i40e_aq_set_dcb_parameters
3722 * @hw: pointer to the hw struct
3723 * @cmd_details: pointer to command details structure or NULL
3724 * @dcb_enable: True if DCB configuration needs to be applied
3725 *
3726 **/
3727 int
i40e_aq_set_dcb_parameters(struct i40e_hw * hw,bool dcb_enable,struct i40e_asq_cmd_details * cmd_details)3728 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
3729 struct i40e_asq_cmd_details *cmd_details)
3730 {
3731 struct i40e_aq_desc desc;
3732 struct i40e_aqc_set_dcb_parameters *cmd =
3733 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
3734 int status;
3735
3736 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE))
3737 return -ENODEV;
3738
3739 i40e_fill_default_direct_cmd_desc(&desc,
3740 i40e_aqc_opc_set_dcb_parameters);
3741
3742 if (dcb_enable) {
3743 cmd->valid_flags = I40E_DCB_VALID;
3744 cmd->command = I40E_AQ_DCB_SET_AGENT;
3745 }
3746 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3747
3748 return status;
3749 }
3750
3751 /**
3752 * i40e_aq_get_cee_dcb_config
3753 * @hw: pointer to the hw struct
3754 * @buff: response buffer that stores CEE operational configuration
3755 * @buff_size: size of the buffer passed
3756 * @cmd_details: pointer to command details structure or NULL
3757 *
3758 * Get CEE DCBX mode operational configuration from firmware
3759 **/
i40e_aq_get_cee_dcb_config(struct i40e_hw * hw,void * buff,u16 buff_size,struct i40e_asq_cmd_details * cmd_details)3760 int i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3761 void *buff, u16 buff_size,
3762 struct i40e_asq_cmd_details *cmd_details)
3763 {
3764 struct i40e_aq_desc desc;
3765 int status;
3766
3767 if (buff_size == 0 || !buff)
3768 return -EINVAL;
3769
3770 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3771
3772 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3773 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3774 cmd_details);
3775
3776 return status;
3777 }
3778
3779 /**
3780 * i40e_aq_add_udp_tunnel
3781 * @hw: pointer to the hw struct
3782 * @udp_port: the UDP port to add in Host byte order
3783 * @protocol_index: protocol index type
3784 * @filter_index: pointer to filter index
3785 * @cmd_details: pointer to command details structure or NULL
3786 *
3787 * Note: Firmware expects the udp_port value to be in Little Endian format,
3788 * and this function will call cpu_to_le16 to convert from Host byte order to
3789 * Little Endian order.
3790 **/
i40e_aq_add_udp_tunnel(struct i40e_hw * hw,u16 udp_port,u8 protocol_index,u8 * filter_index,struct i40e_asq_cmd_details * cmd_details)3791 int i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3792 u16 udp_port, u8 protocol_index,
3793 u8 *filter_index,
3794 struct i40e_asq_cmd_details *cmd_details)
3795 {
3796 struct i40e_aq_desc desc;
3797 struct i40e_aqc_add_udp_tunnel *cmd =
3798 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3799 struct i40e_aqc_del_udp_tunnel_completion *resp =
3800 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3801 int status;
3802
3803 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3804
3805 cmd->udp_port = cpu_to_le16(udp_port);
3806 cmd->protocol_type = protocol_index;
3807
3808 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3809
3810 if (!status && filter_index)
3811 *filter_index = resp->index;
3812
3813 return status;
3814 }
3815
3816 /**
3817 * i40e_aq_del_udp_tunnel
3818 * @hw: pointer to the hw struct
3819 * @index: filter index
3820 * @cmd_details: pointer to command details structure or NULL
3821 **/
i40e_aq_del_udp_tunnel(struct i40e_hw * hw,u8 index,struct i40e_asq_cmd_details * cmd_details)3822 int i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3823 struct i40e_asq_cmd_details *cmd_details)
3824 {
3825 struct i40e_aq_desc desc;
3826 struct i40e_aqc_remove_udp_tunnel *cmd =
3827 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3828 int status;
3829
3830 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3831
3832 cmd->index = index;
3833
3834 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3835
3836 return status;
3837 }
3838
3839 /**
3840 * i40e_aq_delete_element - Delete switch element
3841 * @hw: pointer to the hw struct
3842 * @seid: the SEID to delete from the switch
3843 * @cmd_details: pointer to command details structure or NULL
3844 *
3845 * This deletes a switch element from the switch.
3846 **/
i40e_aq_delete_element(struct i40e_hw * hw,u16 seid,struct i40e_asq_cmd_details * cmd_details)3847 int i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3848 struct i40e_asq_cmd_details *cmd_details)
3849 {
3850 struct i40e_aq_desc desc;
3851 struct i40e_aqc_switch_seid *cmd =
3852 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3853 int status;
3854
3855 if (seid == 0)
3856 return -EINVAL;
3857
3858 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3859
3860 cmd->seid = cpu_to_le16(seid);
3861
3862 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0,
3863 cmd_details, true);
3864
3865 return status;
3866 }
3867
3868 /**
3869 * i40e_aq_dcb_updated - DCB Updated Command
3870 * @hw: pointer to the hw struct
3871 * @cmd_details: pointer to command details structure or NULL
3872 *
3873 * EMP will return when the shared RPB settings have been
3874 * recomputed and modified. The retval field in the descriptor
3875 * will be set to 0 when RPB is modified.
3876 **/
i40e_aq_dcb_updated(struct i40e_hw * hw,struct i40e_asq_cmd_details * cmd_details)3877 int i40e_aq_dcb_updated(struct i40e_hw *hw,
3878 struct i40e_asq_cmd_details *cmd_details)
3879 {
3880 struct i40e_aq_desc desc;
3881 int status;
3882
3883 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3884
3885 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3886
3887 return status;
3888 }
3889
3890 /**
3891 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3892 * @hw: pointer to the hw struct
3893 * @seid: seid for the physical port/switching component/vsi
3894 * @buff: Indirect buffer to hold data parameters and response
3895 * @buff_size: Indirect buffer size
3896 * @opcode: Tx scheduler AQ command opcode
3897 * @cmd_details: pointer to command details structure or NULL
3898 *
3899 * Generic command handler for Tx scheduler AQ commands
3900 **/
i40e_aq_tx_sched_cmd(struct i40e_hw * hw,u16 seid,void * buff,u16 buff_size,enum i40e_admin_queue_opc opcode,struct i40e_asq_cmd_details * cmd_details)3901 static int i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3902 void *buff, u16 buff_size,
3903 enum i40e_admin_queue_opc opcode,
3904 struct i40e_asq_cmd_details *cmd_details)
3905 {
3906 struct i40e_aq_desc desc;
3907 struct i40e_aqc_tx_sched_ind *cmd =
3908 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3909 int status;
3910 bool cmd_param_flag = false;
3911
3912 switch (opcode) {
3913 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3914 case i40e_aqc_opc_configure_vsi_tc_bw:
3915 case i40e_aqc_opc_enable_switching_comp_ets:
3916 case i40e_aqc_opc_modify_switching_comp_ets:
3917 case i40e_aqc_opc_disable_switching_comp_ets:
3918 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3919 case i40e_aqc_opc_configure_switching_comp_bw_config:
3920 cmd_param_flag = true;
3921 break;
3922 case i40e_aqc_opc_query_vsi_bw_config:
3923 case i40e_aqc_opc_query_vsi_ets_sla_config:
3924 case i40e_aqc_opc_query_switching_comp_ets_config:
3925 case i40e_aqc_opc_query_port_ets_config:
3926 case i40e_aqc_opc_query_switching_comp_bw_config:
3927 cmd_param_flag = false;
3928 break;
3929 default:
3930 return -EINVAL;
3931 }
3932
3933 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3934
3935 /* Indirect command */
3936 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3937 if (cmd_param_flag)
3938 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3939 if (buff_size > I40E_AQ_LARGE_BUF)
3940 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3941
3942 desc.datalen = cpu_to_le16(buff_size);
3943
3944 cmd->vsi_seid = cpu_to_le16(seid);
3945
3946 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3947
3948 return status;
3949 }
3950
3951 /**
3952 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3953 * @hw: pointer to the hw struct
3954 * @seid: VSI seid
3955 * @credit: BW limit credits (0 = disabled)
3956 * @max_credit: Max BW limit credits
3957 * @cmd_details: pointer to command details structure or NULL
3958 **/
i40e_aq_config_vsi_bw_limit(struct i40e_hw * hw,u16 seid,u16 credit,u8 max_credit,struct i40e_asq_cmd_details * cmd_details)3959 int i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3960 u16 seid, u16 credit, u8 max_credit,
3961 struct i40e_asq_cmd_details *cmd_details)
3962 {
3963 struct i40e_aq_desc desc;
3964 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3965 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3966 int status;
3967
3968 i40e_fill_default_direct_cmd_desc(&desc,
3969 i40e_aqc_opc_configure_vsi_bw_limit);
3970
3971 cmd->vsi_seid = cpu_to_le16(seid);
3972 cmd->credit = cpu_to_le16(credit);
3973 cmd->max_credit = max_credit;
3974
3975 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3976
3977 return status;
3978 }
3979
3980 /**
3981 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3982 * @hw: pointer to the hw struct
3983 * @seid: VSI seid
3984 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3985 * @cmd_details: pointer to command details structure or NULL
3986 **/
i40e_aq_config_vsi_tc_bw(struct i40e_hw * hw,u16 seid,struct i40e_aqc_configure_vsi_tc_bw_data * bw_data,struct i40e_asq_cmd_details * cmd_details)3987 int i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3988 u16 seid,
3989 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3990 struct i40e_asq_cmd_details *cmd_details)
3991 {
3992 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3993 i40e_aqc_opc_configure_vsi_tc_bw,
3994 cmd_details);
3995 }
3996
3997 /**
3998 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3999 * @hw: pointer to the hw struct
4000 * @seid: seid of the switching component connected to Physical Port
4001 * @ets_data: Buffer holding ETS parameters
4002 * @opcode: Tx scheduler AQ command opcode
4003 * @cmd_details: pointer to command details structure or NULL
4004 **/
4005 int
i40e_aq_config_switch_comp_ets(struct i40e_hw * hw,u16 seid,struct i40e_aqc_configure_switching_comp_ets_data * ets_data,enum i40e_admin_queue_opc opcode,struct i40e_asq_cmd_details * cmd_details)4006 i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
4007 u16 seid,
4008 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
4009 enum i40e_admin_queue_opc opcode,
4010 struct i40e_asq_cmd_details *cmd_details)
4011 {
4012 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
4013 sizeof(*ets_data), opcode, cmd_details);
4014 }
4015
4016 /**
4017 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
4018 * @hw: pointer to the hw struct
4019 * @seid: seid of the switching component
4020 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
4021 * @cmd_details: pointer to command details structure or NULL
4022 **/
4023 int
i40e_aq_config_switch_comp_bw_config(struct i40e_hw * hw,u16 seid,struct i40e_aqc_configure_switching_comp_bw_config_data * bw_data,struct i40e_asq_cmd_details * cmd_details)4024 i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
4025 u16 seid,
4026 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
4027 struct i40e_asq_cmd_details *cmd_details)
4028 {
4029 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4030 i40e_aqc_opc_configure_switching_comp_bw_config,
4031 cmd_details);
4032 }
4033
4034 /**
4035 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4036 * @hw: pointer to the hw struct
4037 * @seid: seid of the VSI
4038 * @bw_data: Buffer to hold VSI BW configuration
4039 * @cmd_details: pointer to command details structure or NULL
4040 **/
4041 int
i40e_aq_query_vsi_bw_config(struct i40e_hw * hw,u16 seid,struct i40e_aqc_query_vsi_bw_config_resp * bw_data,struct i40e_asq_cmd_details * cmd_details)4042 i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4043 u16 seid,
4044 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4045 struct i40e_asq_cmd_details *cmd_details)
4046 {
4047 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4048 i40e_aqc_opc_query_vsi_bw_config,
4049 cmd_details);
4050 }
4051
4052 /**
4053 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4054 * @hw: pointer to the hw struct
4055 * @seid: seid of the VSI
4056 * @bw_data: Buffer to hold VSI BW configuration per TC
4057 * @cmd_details: pointer to command details structure or NULL
4058 **/
4059 int
i40e_aq_query_vsi_ets_sla_config(struct i40e_hw * hw,u16 seid,struct i40e_aqc_query_vsi_ets_sla_config_resp * bw_data,struct i40e_asq_cmd_details * cmd_details)4060 i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4061 u16 seid,
4062 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4063 struct i40e_asq_cmd_details *cmd_details)
4064 {
4065 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4066 i40e_aqc_opc_query_vsi_ets_sla_config,
4067 cmd_details);
4068 }
4069
4070 /**
4071 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4072 * @hw: pointer to the hw struct
4073 * @seid: seid of the switching component
4074 * @bw_data: Buffer to hold switching component's per TC BW config
4075 * @cmd_details: pointer to command details structure or NULL
4076 **/
4077 int
i40e_aq_query_switch_comp_ets_config(struct i40e_hw * hw,u16 seid,struct i40e_aqc_query_switching_comp_ets_config_resp * bw_data,struct i40e_asq_cmd_details * cmd_details)4078 i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4079 u16 seid,
4080 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4081 struct i40e_asq_cmd_details *cmd_details)
4082 {
4083 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4084 i40e_aqc_opc_query_switching_comp_ets_config,
4085 cmd_details);
4086 }
4087
4088 /**
4089 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4090 * @hw: pointer to the hw struct
4091 * @seid: seid of the VSI or switching component connected to Physical Port
4092 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4093 * @cmd_details: pointer to command details structure or NULL
4094 **/
4095 int
i40e_aq_query_port_ets_config(struct i40e_hw * hw,u16 seid,struct i40e_aqc_query_port_ets_config_resp * bw_data,struct i40e_asq_cmd_details * cmd_details)4096 i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4097 u16 seid,
4098 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4099 struct i40e_asq_cmd_details *cmd_details)
4100 {
4101 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4102 i40e_aqc_opc_query_port_ets_config,
4103 cmd_details);
4104 }
4105
4106 /**
4107 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4108 * @hw: pointer to the hw struct
4109 * @seid: seid of the switching component
4110 * @bw_data: Buffer to hold switching component's BW configuration
4111 * @cmd_details: pointer to command details structure or NULL
4112 **/
4113 int
i40e_aq_query_switch_comp_bw_config(struct i40e_hw * hw,u16 seid,struct i40e_aqc_query_switching_comp_bw_config_resp * bw_data,struct i40e_asq_cmd_details * cmd_details)4114 i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4115 u16 seid,
4116 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4117 struct i40e_asq_cmd_details *cmd_details)
4118 {
4119 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4120 i40e_aqc_opc_query_switching_comp_bw_config,
4121 cmd_details);
4122 }
4123
4124 /**
4125 * i40e_validate_filter_settings
4126 * @hw: pointer to the hardware structure
4127 * @settings: Filter control settings
4128 *
4129 * Check and validate the filter control settings passed.
4130 * The function checks for the valid filter/context sizes being
4131 * passed for FCoE and PE.
4132 *
4133 * Returns 0 if the values passed are valid and within
4134 * range else returns an error.
4135 **/
4136 static int
i40e_validate_filter_settings(struct i40e_hw * hw,struct i40e_filter_control_settings * settings)4137 i40e_validate_filter_settings(struct i40e_hw *hw,
4138 struct i40e_filter_control_settings *settings)
4139 {
4140 u32 fcoe_cntx_size, fcoe_filt_size;
4141 u32 fcoe_fmax;
4142 u32 val;
4143
4144 /* Validate FCoE settings passed */
4145 switch (settings->fcoe_filt_num) {
4146 case I40E_HASH_FILTER_SIZE_1K:
4147 case I40E_HASH_FILTER_SIZE_2K:
4148 case I40E_HASH_FILTER_SIZE_4K:
4149 case I40E_HASH_FILTER_SIZE_8K:
4150 case I40E_HASH_FILTER_SIZE_16K:
4151 case I40E_HASH_FILTER_SIZE_32K:
4152 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4153 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4154 break;
4155 default:
4156 return -EINVAL;
4157 }
4158
4159 switch (settings->fcoe_cntx_num) {
4160 case I40E_DMA_CNTX_SIZE_512:
4161 case I40E_DMA_CNTX_SIZE_1K:
4162 case I40E_DMA_CNTX_SIZE_2K:
4163 case I40E_DMA_CNTX_SIZE_4K:
4164 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4165 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4166 break;
4167 default:
4168 return -EINVAL;
4169 }
4170
4171 /* Validate PE settings passed */
4172 switch (settings->pe_filt_num) {
4173 case I40E_HASH_FILTER_SIZE_1K:
4174 case I40E_HASH_FILTER_SIZE_2K:
4175 case I40E_HASH_FILTER_SIZE_4K:
4176 case I40E_HASH_FILTER_SIZE_8K:
4177 case I40E_HASH_FILTER_SIZE_16K:
4178 case I40E_HASH_FILTER_SIZE_32K:
4179 case I40E_HASH_FILTER_SIZE_64K:
4180 case I40E_HASH_FILTER_SIZE_128K:
4181 case I40E_HASH_FILTER_SIZE_256K:
4182 case I40E_HASH_FILTER_SIZE_512K:
4183 case I40E_HASH_FILTER_SIZE_1M:
4184 break;
4185 default:
4186 return -EINVAL;
4187 }
4188
4189 switch (settings->pe_cntx_num) {
4190 case I40E_DMA_CNTX_SIZE_512:
4191 case I40E_DMA_CNTX_SIZE_1K:
4192 case I40E_DMA_CNTX_SIZE_2K:
4193 case I40E_DMA_CNTX_SIZE_4K:
4194 case I40E_DMA_CNTX_SIZE_8K:
4195 case I40E_DMA_CNTX_SIZE_16K:
4196 case I40E_DMA_CNTX_SIZE_32K:
4197 case I40E_DMA_CNTX_SIZE_64K:
4198 case I40E_DMA_CNTX_SIZE_128K:
4199 case I40E_DMA_CNTX_SIZE_256K:
4200 break;
4201 default:
4202 return -EINVAL;
4203 }
4204
4205 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4206 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4207 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4208 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4209 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4210 return -EINVAL;
4211
4212 return 0;
4213 }
4214
4215 /**
4216 * i40e_set_filter_control
4217 * @hw: pointer to the hardware structure
4218 * @settings: Filter control settings
4219 *
4220 * Set the Queue Filters for PE/FCoE and enable filters required
4221 * for a single PF. It is expected that these settings are programmed
4222 * at the driver initialization time.
4223 **/
i40e_set_filter_control(struct i40e_hw * hw,struct i40e_filter_control_settings * settings)4224 int i40e_set_filter_control(struct i40e_hw *hw,
4225 struct i40e_filter_control_settings *settings)
4226 {
4227 u32 hash_lut_size = 0;
4228 int ret = 0;
4229 u32 val;
4230
4231 if (!settings)
4232 return -EINVAL;
4233
4234 /* Validate the input settings */
4235 ret = i40e_validate_filter_settings(hw, settings);
4236 if (ret)
4237 return ret;
4238
4239 /* Read the PF Queue Filter control register */
4240 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
4241
4242 /* Program required PE hash buckets for the PF */
4243 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4244 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4245 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4246 /* Program required PE contexts for the PF */
4247 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4248 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4249 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4250
4251 /* Program required FCoE hash buckets for the PF */
4252 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4253 val |= ((u32)settings->fcoe_filt_num <<
4254 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4255 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4256 /* Program required FCoE DDP contexts for the PF */
4257 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4258 val |= ((u32)settings->fcoe_cntx_num <<
4259 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4260 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4261
4262 /* Program Hash LUT size for the PF */
4263 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4264 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4265 hash_lut_size = 1;
4266 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4267 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4268
4269 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4270 if (settings->enable_fdir)
4271 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4272 if (settings->enable_ethtype)
4273 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4274 if (settings->enable_macvlan)
4275 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4276
4277 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
4278
4279 return 0;
4280 }
4281
4282 /**
4283 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4284 * @hw: pointer to the hw struct
4285 * @mac_addr: MAC address to use in the filter
4286 * @ethtype: Ethertype to use in the filter
4287 * @flags: Flags that needs to be applied to the filter
4288 * @vsi_seid: seid of the control VSI
4289 * @queue: VSI queue number to send the packet to
4290 * @is_add: Add control packet filter if True else remove
4291 * @stats: Structure to hold information on control filter counts
4292 * @cmd_details: pointer to command details structure or NULL
4293 *
4294 * This command will Add or Remove control packet filter for a control VSI.
4295 * In return it will update the total number of perfect filter count in
4296 * the stats member.
4297 **/
i40e_aq_add_rem_control_packet_filter(struct i40e_hw * hw,u8 * mac_addr,u16 ethtype,u16 flags,u16 vsi_seid,u16 queue,bool is_add,struct i40e_control_filter_stats * stats,struct i40e_asq_cmd_details * cmd_details)4298 int i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4299 u8 *mac_addr, u16 ethtype, u16 flags,
4300 u16 vsi_seid, u16 queue, bool is_add,
4301 struct i40e_control_filter_stats *stats,
4302 struct i40e_asq_cmd_details *cmd_details)
4303 {
4304 struct i40e_aq_desc desc;
4305 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4306 (struct i40e_aqc_add_remove_control_packet_filter *)
4307 &desc.params.raw;
4308 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4309 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4310 &desc.params.raw;
4311 int status;
4312
4313 if (vsi_seid == 0)
4314 return -EINVAL;
4315
4316 if (is_add) {
4317 i40e_fill_default_direct_cmd_desc(&desc,
4318 i40e_aqc_opc_add_control_packet_filter);
4319 cmd->queue = cpu_to_le16(queue);
4320 } else {
4321 i40e_fill_default_direct_cmd_desc(&desc,
4322 i40e_aqc_opc_remove_control_packet_filter);
4323 }
4324
4325 if (mac_addr)
4326 ether_addr_copy(cmd->mac, mac_addr);
4327
4328 cmd->etype = cpu_to_le16(ethtype);
4329 cmd->flags = cpu_to_le16(flags);
4330 cmd->seid = cpu_to_le16(vsi_seid);
4331
4332 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4333
4334 if (!status && stats) {
4335 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
4336 stats->etype_used = le16_to_cpu(resp->etype_used);
4337 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
4338 stats->etype_free = le16_to_cpu(resp->etype_free);
4339 }
4340
4341 return status;
4342 }
4343
4344 /**
4345 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4346 * @hw: pointer to the hw struct
4347 * @seid: VSI seid to add ethertype filter from
4348 **/
i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw * hw,u16 seid)4349 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4350 u16 seid)
4351 {
4352 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4353 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4354 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4355 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4356 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4357 int status;
4358
4359 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
4360 seid, 0, true, NULL,
4361 NULL);
4362 if (status)
4363 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4364 }
4365
4366 /**
4367 * i40e_aq_alternate_read
4368 * @hw: pointer to the hardware structure
4369 * @reg_addr0: address of first dword to be read
4370 * @reg_val0: pointer for data read from 'reg_addr0'
4371 * @reg_addr1: address of second dword to be read
4372 * @reg_val1: pointer for data read from 'reg_addr1'
4373 *
4374 * Read one or two dwords from alternate structure. Fields are indicated
4375 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4376 * is not passed then only register at 'reg_addr0' is read.
4377 *
4378 **/
i40e_aq_alternate_read(struct i40e_hw * hw,u32 reg_addr0,u32 * reg_val0,u32 reg_addr1,u32 * reg_val1)4379 static int i40e_aq_alternate_read(struct i40e_hw *hw,
4380 u32 reg_addr0, u32 *reg_val0,
4381 u32 reg_addr1, u32 *reg_val1)
4382 {
4383 struct i40e_aq_desc desc;
4384 struct i40e_aqc_alternate_write *cmd_resp =
4385 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4386 int status;
4387
4388 if (!reg_val0)
4389 return -EINVAL;
4390
4391 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4392 cmd_resp->address0 = cpu_to_le32(reg_addr0);
4393 cmd_resp->address1 = cpu_to_le32(reg_addr1);
4394
4395 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4396
4397 if (!status) {
4398 *reg_val0 = le32_to_cpu(cmd_resp->data0);
4399
4400 if (reg_val1)
4401 *reg_val1 = le32_to_cpu(cmd_resp->data1);
4402 }
4403
4404 return status;
4405 }
4406
4407 /**
4408 * i40e_aq_suspend_port_tx
4409 * @hw: pointer to the hardware structure
4410 * @seid: port seid
4411 * @cmd_details: pointer to command details structure or NULL
4412 *
4413 * Suspend port's Tx traffic
4414 **/
i40e_aq_suspend_port_tx(struct i40e_hw * hw,u16 seid,struct i40e_asq_cmd_details * cmd_details)4415 int i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid,
4416 struct i40e_asq_cmd_details *cmd_details)
4417 {
4418 struct i40e_aqc_tx_sched_ind *cmd;
4419 struct i40e_aq_desc desc;
4420 int status;
4421
4422 cmd = (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4423 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_suspend_port_tx);
4424 cmd->vsi_seid = cpu_to_le16(seid);
4425 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4426
4427 return status;
4428 }
4429
4430 /**
4431 * i40e_aq_resume_port_tx
4432 * @hw: pointer to the hardware structure
4433 * @cmd_details: pointer to command details structure or NULL
4434 *
4435 * Resume port's Tx traffic
4436 **/
i40e_aq_resume_port_tx(struct i40e_hw * hw,struct i40e_asq_cmd_details * cmd_details)4437 int i40e_aq_resume_port_tx(struct i40e_hw *hw,
4438 struct i40e_asq_cmd_details *cmd_details)
4439 {
4440 struct i40e_aq_desc desc;
4441 int status;
4442
4443 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4444
4445 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4446
4447 return status;
4448 }
4449
4450 /**
4451 * i40e_set_pci_config_data - store PCI bus info
4452 * @hw: pointer to hardware structure
4453 * @link_status: the link status word from PCI config space
4454 *
4455 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4456 **/
i40e_set_pci_config_data(struct i40e_hw * hw,u16 link_status)4457 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4458 {
4459 hw->bus.type = i40e_bus_type_pci_express;
4460
4461 switch (link_status & PCI_EXP_LNKSTA_NLW) {
4462 case PCI_EXP_LNKSTA_NLW_X1:
4463 hw->bus.width = i40e_bus_width_pcie_x1;
4464 break;
4465 case PCI_EXP_LNKSTA_NLW_X2:
4466 hw->bus.width = i40e_bus_width_pcie_x2;
4467 break;
4468 case PCI_EXP_LNKSTA_NLW_X4:
4469 hw->bus.width = i40e_bus_width_pcie_x4;
4470 break;
4471 case PCI_EXP_LNKSTA_NLW_X8:
4472 hw->bus.width = i40e_bus_width_pcie_x8;
4473 break;
4474 default:
4475 hw->bus.width = i40e_bus_width_unknown;
4476 break;
4477 }
4478
4479 switch (link_status & PCI_EXP_LNKSTA_CLS) {
4480 case PCI_EXP_LNKSTA_CLS_2_5GB:
4481 hw->bus.speed = i40e_bus_speed_2500;
4482 break;
4483 case PCI_EXP_LNKSTA_CLS_5_0GB:
4484 hw->bus.speed = i40e_bus_speed_5000;
4485 break;
4486 case PCI_EXP_LNKSTA_CLS_8_0GB:
4487 hw->bus.speed = i40e_bus_speed_8000;
4488 break;
4489 default:
4490 hw->bus.speed = i40e_bus_speed_unknown;
4491 break;
4492 }
4493 }
4494
4495 /**
4496 * i40e_aq_debug_dump
4497 * @hw: pointer to the hardware structure
4498 * @cluster_id: specific cluster to dump
4499 * @table_id: table id within cluster
4500 * @start_index: index of line in the block to read
4501 * @buff_size: dump buffer size
4502 * @buff: dump buffer
4503 * @ret_buff_size: actual buffer size returned
4504 * @ret_next_table: next block to read
4505 * @ret_next_index: next index to read
4506 * @cmd_details: pointer to command details structure or NULL
4507 *
4508 * Dump internal FW/HW data for debug purposes.
4509 *
4510 **/
i40e_aq_debug_dump(struct i40e_hw * hw,u8 cluster_id,u8 table_id,u32 start_index,u16 buff_size,void * buff,u16 * ret_buff_size,u8 * ret_next_table,u32 * ret_next_index,struct i40e_asq_cmd_details * cmd_details)4511 int i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4512 u8 table_id, u32 start_index, u16 buff_size,
4513 void *buff, u16 *ret_buff_size,
4514 u8 *ret_next_table, u32 *ret_next_index,
4515 struct i40e_asq_cmd_details *cmd_details)
4516 {
4517 struct i40e_aq_desc desc;
4518 struct i40e_aqc_debug_dump_internals *cmd =
4519 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4520 struct i40e_aqc_debug_dump_internals *resp =
4521 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4522 int status;
4523
4524 if (buff_size == 0 || !buff)
4525 return -EINVAL;
4526
4527 i40e_fill_default_direct_cmd_desc(&desc,
4528 i40e_aqc_opc_debug_dump_internals);
4529 /* Indirect Command */
4530 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4531 if (buff_size > I40E_AQ_LARGE_BUF)
4532 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4533
4534 cmd->cluster_id = cluster_id;
4535 cmd->table_id = table_id;
4536 cmd->idx = cpu_to_le32(start_index);
4537
4538 desc.datalen = cpu_to_le16(buff_size);
4539
4540 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4541 if (!status) {
4542 if (ret_buff_size)
4543 *ret_buff_size = le16_to_cpu(desc.datalen);
4544 if (ret_next_table)
4545 *ret_next_table = resp->table_id;
4546 if (ret_next_index)
4547 *ret_next_index = le32_to_cpu(resp->idx);
4548 }
4549
4550 return status;
4551 }
4552
4553 /**
4554 * i40e_read_bw_from_alt_ram
4555 * @hw: pointer to the hardware structure
4556 * @max_bw: pointer for max_bw read
4557 * @min_bw: pointer for min_bw read
4558 * @min_valid: pointer for bool that is true if min_bw is a valid value
4559 * @max_valid: pointer for bool that is true if max_bw is a valid value
4560 *
4561 * Read bw from the alternate ram for the given pf
4562 **/
i40e_read_bw_from_alt_ram(struct i40e_hw * hw,u32 * max_bw,u32 * min_bw,bool * min_valid,bool * max_valid)4563 int i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4564 u32 *max_bw, u32 *min_bw,
4565 bool *min_valid, bool *max_valid)
4566 {
4567 u32 max_bw_addr, min_bw_addr;
4568 int status;
4569
4570 /* Calculate the address of the min/max bw registers */
4571 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4572 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4573 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4574 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4575 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4576 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4577
4578 /* Read the bandwidths from alt ram */
4579 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4580 min_bw_addr, min_bw);
4581
4582 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4583 *min_valid = true;
4584 else
4585 *min_valid = false;
4586
4587 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4588 *max_valid = true;
4589 else
4590 *max_valid = false;
4591
4592 return status;
4593 }
4594
4595 /**
4596 * i40e_aq_configure_partition_bw
4597 * @hw: pointer to the hardware structure
4598 * @bw_data: Buffer holding valid pfs and bw limits
4599 * @cmd_details: pointer to command details
4600 *
4601 * Configure partitions guaranteed/max bw
4602 **/
4603 int
i40e_aq_configure_partition_bw(struct i40e_hw * hw,struct i40e_aqc_configure_partition_bw_data * bw_data,struct i40e_asq_cmd_details * cmd_details)4604 i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4605 struct i40e_aqc_configure_partition_bw_data *bw_data,
4606 struct i40e_asq_cmd_details *cmd_details)
4607 {
4608 u16 bwd_size = sizeof(*bw_data);
4609 struct i40e_aq_desc desc;
4610 int status;
4611
4612 i40e_fill_default_direct_cmd_desc(&desc,
4613 i40e_aqc_opc_configure_partition_bw);
4614
4615 /* Indirect command */
4616 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4617 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4618
4619 if (bwd_size > I40E_AQ_LARGE_BUF)
4620 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4621
4622 desc.datalen = cpu_to_le16(bwd_size);
4623
4624 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4625 cmd_details);
4626
4627 return status;
4628 }
4629
4630 /**
4631 * i40e_read_phy_register_clause22
4632 * @hw: pointer to the HW structure
4633 * @reg: register address in the page
4634 * @phy_addr: PHY address on MDIO interface
4635 * @value: PHY register value
4636 *
4637 * Reads specified PHY register value
4638 **/
i40e_read_phy_register_clause22(struct i40e_hw * hw,u16 reg,u8 phy_addr,u16 * value)4639 int i40e_read_phy_register_clause22(struct i40e_hw *hw,
4640 u16 reg, u8 phy_addr, u16 *value)
4641 {
4642 u8 port_num = (u8)hw->func_caps.mdio_port_num;
4643 int status = -EIO;
4644 u32 command = 0;
4645 u16 retry = 1000;
4646
4647 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4648 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4649 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
4650 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4651 (I40E_GLGEN_MSCA_MDICMD_MASK);
4652 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4653 do {
4654 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4655 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4656 status = 0;
4657 break;
4658 }
4659 udelay(10);
4660 retry--;
4661 } while (retry);
4662
4663 if (status) {
4664 i40e_debug(hw, I40E_DEBUG_PHY,
4665 "PHY: Can't write command to external PHY.\n");
4666 } else {
4667 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4668 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4669 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4670 }
4671
4672 return status;
4673 }
4674
4675 /**
4676 * i40e_write_phy_register_clause22
4677 * @hw: pointer to the HW structure
4678 * @reg: register address in the page
4679 * @phy_addr: PHY address on MDIO interface
4680 * @value: PHY register value
4681 *
4682 * Writes specified PHY register value
4683 **/
i40e_write_phy_register_clause22(struct i40e_hw * hw,u16 reg,u8 phy_addr,u16 value)4684 int i40e_write_phy_register_clause22(struct i40e_hw *hw,
4685 u16 reg, u8 phy_addr, u16 value)
4686 {
4687 u8 port_num = (u8)hw->func_caps.mdio_port_num;
4688 int status = -EIO;
4689 u32 command = 0;
4690 u16 retry = 1000;
4691
4692 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4693 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4694
4695 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4696 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4697 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
4698 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4699 (I40E_GLGEN_MSCA_MDICMD_MASK);
4700
4701 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4702 do {
4703 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4704 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4705 status = 0;
4706 break;
4707 }
4708 udelay(10);
4709 retry--;
4710 } while (retry);
4711
4712 return status;
4713 }
4714
4715 /**
4716 * i40e_read_phy_register_clause45
4717 * @hw: pointer to the HW structure
4718 * @page: registers page number
4719 * @reg: register address in the page
4720 * @phy_addr: PHY address on MDIO interface
4721 * @value: PHY register value
4722 *
4723 * Reads specified PHY register value
4724 **/
i40e_read_phy_register_clause45(struct i40e_hw * hw,u8 page,u16 reg,u8 phy_addr,u16 * value)4725 int i40e_read_phy_register_clause45(struct i40e_hw *hw,
4726 u8 page, u16 reg, u8 phy_addr, u16 *value)
4727 {
4728 u8 port_num = hw->func_caps.mdio_port_num;
4729 int status = -EIO;
4730 u32 command = 0;
4731 u16 retry = 1000;
4732
4733 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4734 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4735 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4736 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4737 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4738 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4739 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4740 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4741 do {
4742 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4743 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4744 status = 0;
4745 break;
4746 }
4747 usleep_range(10, 20);
4748 retry--;
4749 } while (retry);
4750
4751 if (status) {
4752 i40e_debug(hw, I40E_DEBUG_PHY,
4753 "PHY: Can't write command to external PHY.\n");
4754 goto phy_read_end;
4755 }
4756
4757 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4758 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4759 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
4760 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4761 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4762 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4763 status = -EIO;
4764 retry = 1000;
4765 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4766 do {
4767 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4768 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4769 status = 0;
4770 break;
4771 }
4772 usleep_range(10, 20);
4773 retry--;
4774 } while (retry);
4775
4776 if (!status) {
4777 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4778 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4779 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4780 } else {
4781 i40e_debug(hw, I40E_DEBUG_PHY,
4782 "PHY: Can't read register value from external PHY.\n");
4783 }
4784
4785 phy_read_end:
4786 return status;
4787 }
4788
4789 /**
4790 * i40e_write_phy_register_clause45
4791 * @hw: pointer to the HW structure
4792 * @page: registers page number
4793 * @reg: register address in the page
4794 * @phy_addr: PHY address on MDIO interface
4795 * @value: PHY register value
4796 *
4797 * Writes value to specified PHY register
4798 **/
i40e_write_phy_register_clause45(struct i40e_hw * hw,u8 page,u16 reg,u8 phy_addr,u16 value)4799 int i40e_write_phy_register_clause45(struct i40e_hw *hw,
4800 u8 page, u16 reg, u8 phy_addr, u16 value)
4801 {
4802 u8 port_num = hw->func_caps.mdio_port_num;
4803 int status = -EIO;
4804 u16 retry = 1000;
4805 u32 command = 0;
4806
4807 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4808 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4809 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4810 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4811 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4812 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4813 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4814 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4815 do {
4816 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4817 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4818 status = 0;
4819 break;
4820 }
4821 usleep_range(10, 20);
4822 retry--;
4823 } while (retry);
4824 if (status) {
4825 i40e_debug(hw, I40E_DEBUG_PHY,
4826 "PHY: Can't write command to external PHY.\n");
4827 goto phy_write_end;
4828 }
4829
4830 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4831 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4832
4833 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4834 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4835 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
4836 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4837 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4838 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4839 status = -EIO;
4840 retry = 1000;
4841 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4842 do {
4843 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4844 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4845 status = 0;
4846 break;
4847 }
4848 usleep_range(10, 20);
4849 retry--;
4850 } while (retry);
4851
4852 phy_write_end:
4853 return status;
4854 }
4855
4856 /**
4857 * i40e_write_phy_register
4858 * @hw: pointer to the HW structure
4859 * @page: registers page number
4860 * @reg: register address in the page
4861 * @phy_addr: PHY address on MDIO interface
4862 * @value: PHY register value
4863 *
4864 * Writes value to specified PHY register
4865 **/
i40e_write_phy_register(struct i40e_hw * hw,u8 page,u16 reg,u8 phy_addr,u16 value)4866 int i40e_write_phy_register(struct i40e_hw *hw,
4867 u8 page, u16 reg, u8 phy_addr, u16 value)
4868 {
4869 int status;
4870
4871 switch (hw->device_id) {
4872 case I40E_DEV_ID_1G_BASE_T_X722:
4873 status = i40e_write_phy_register_clause22(hw, reg, phy_addr,
4874 value);
4875 break;
4876 case I40E_DEV_ID_1G_BASE_T_BC:
4877 case I40E_DEV_ID_5G_BASE_T_BC:
4878 case I40E_DEV_ID_10G_BASE_T:
4879 case I40E_DEV_ID_10G_BASE_T4:
4880 case I40E_DEV_ID_10G_BASE_T_BC:
4881 case I40E_DEV_ID_10G_BASE_T_X722:
4882 case I40E_DEV_ID_25G_B:
4883 case I40E_DEV_ID_25G_SFP28:
4884 status = i40e_write_phy_register_clause45(hw, page, reg,
4885 phy_addr, value);
4886 break;
4887 default:
4888 status = -EIO;
4889 break;
4890 }
4891
4892 return status;
4893 }
4894
4895 /**
4896 * i40e_read_phy_register
4897 * @hw: pointer to the HW structure
4898 * @page: registers page number
4899 * @reg: register address in the page
4900 * @phy_addr: PHY address on MDIO interface
4901 * @value: PHY register value
4902 *
4903 * Reads specified PHY register value
4904 **/
i40e_read_phy_register(struct i40e_hw * hw,u8 page,u16 reg,u8 phy_addr,u16 * value)4905 int i40e_read_phy_register(struct i40e_hw *hw,
4906 u8 page, u16 reg, u8 phy_addr, u16 *value)
4907 {
4908 int status;
4909
4910 switch (hw->device_id) {
4911 case I40E_DEV_ID_1G_BASE_T_X722:
4912 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
4913 value);
4914 break;
4915 case I40E_DEV_ID_1G_BASE_T_BC:
4916 case I40E_DEV_ID_5G_BASE_T_BC:
4917 case I40E_DEV_ID_10G_BASE_T:
4918 case I40E_DEV_ID_10G_BASE_T4:
4919 case I40E_DEV_ID_10G_BASE_T_BC:
4920 case I40E_DEV_ID_10G_BASE_T_X722:
4921 case I40E_DEV_ID_25G_B:
4922 case I40E_DEV_ID_25G_SFP28:
4923 status = i40e_read_phy_register_clause45(hw, page, reg,
4924 phy_addr, value);
4925 break;
4926 default:
4927 status = -EIO;
4928 break;
4929 }
4930
4931 return status;
4932 }
4933
4934 /**
4935 * i40e_get_phy_address
4936 * @hw: pointer to the HW structure
4937 * @dev_num: PHY port num that address we want
4938 *
4939 * Gets PHY address for current port
4940 **/
i40e_get_phy_address(struct i40e_hw * hw,u8 dev_num)4941 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
4942 {
4943 u8 port_num = hw->func_caps.mdio_port_num;
4944 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
4945
4946 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
4947 }
4948
4949 /**
4950 * i40e_blink_phy_link_led
4951 * @hw: pointer to the HW structure
4952 * @time: time how long led will blinks in secs
4953 * @interval: gap between LED on and off in msecs
4954 *
4955 * Blinks PHY link LED
4956 **/
i40e_blink_phy_link_led(struct i40e_hw * hw,u32 time,u32 interval)4957 int i40e_blink_phy_link_led(struct i40e_hw *hw,
4958 u32 time, u32 interval)
4959 {
4960 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
4961 u16 gpio_led_port;
4962 u8 phy_addr = 0;
4963 int status = 0;
4964 u16 led_ctl;
4965 u8 port_num;
4966 u16 led_reg;
4967 u32 i;
4968
4969 i = rd32(hw, I40E_PFGEN_PORTNUM);
4970 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4971 phy_addr = i40e_get_phy_address(hw, port_num);
4972
4973 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4974 led_addr++) {
4975 status = i40e_read_phy_register_clause45(hw,
4976 I40E_PHY_COM_REG_PAGE,
4977 led_addr, phy_addr,
4978 &led_reg);
4979 if (status)
4980 goto phy_blinking_end;
4981 led_ctl = led_reg;
4982 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4983 led_reg = 0;
4984 status = i40e_write_phy_register_clause45(hw,
4985 I40E_PHY_COM_REG_PAGE,
4986 led_addr, phy_addr,
4987 led_reg);
4988 if (status)
4989 goto phy_blinking_end;
4990 break;
4991 }
4992 }
4993
4994 if (time > 0 && interval > 0) {
4995 for (i = 0; i < time * 1000; i += interval) {
4996 status = i40e_read_phy_register_clause45(hw,
4997 I40E_PHY_COM_REG_PAGE,
4998 led_addr, phy_addr, &led_reg);
4999 if (status)
5000 goto restore_config;
5001 if (led_reg & I40E_PHY_LED_MANUAL_ON)
5002 led_reg = 0;
5003 else
5004 led_reg = I40E_PHY_LED_MANUAL_ON;
5005 status = i40e_write_phy_register_clause45(hw,
5006 I40E_PHY_COM_REG_PAGE,
5007 led_addr, phy_addr, led_reg);
5008 if (status)
5009 goto restore_config;
5010 msleep(interval);
5011 }
5012 }
5013
5014 restore_config:
5015 status = i40e_write_phy_register_clause45(hw,
5016 I40E_PHY_COM_REG_PAGE,
5017 led_addr, phy_addr, led_ctl);
5018
5019 phy_blinking_end:
5020 return status;
5021 }
5022
5023 /**
5024 * i40e_led_get_reg - read LED register
5025 * @hw: pointer to the HW structure
5026 * @led_addr: LED register address
5027 * @reg_val: read register value
5028 **/
i40e_led_get_reg(struct i40e_hw * hw,u16 led_addr,u32 * reg_val)5029 static int i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
5030 u32 *reg_val)
5031 {
5032 u8 phy_addr = 0;
5033 u8 port_num;
5034 int status;
5035 u32 i;
5036
5037 *reg_val = 0;
5038 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5039 status =
5040 i40e_aq_get_phy_register(hw,
5041 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5042 I40E_PHY_COM_REG_PAGE, true,
5043 I40E_PHY_LED_PROV_REG_1,
5044 reg_val, NULL);
5045 } else {
5046 i = rd32(hw, I40E_PFGEN_PORTNUM);
5047 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5048 phy_addr = i40e_get_phy_address(hw, port_num);
5049 status = i40e_read_phy_register_clause45(hw,
5050 I40E_PHY_COM_REG_PAGE,
5051 led_addr, phy_addr,
5052 (u16 *)reg_val);
5053 }
5054 return status;
5055 }
5056
5057 /**
5058 * i40e_led_set_reg - write LED register
5059 * @hw: pointer to the HW structure
5060 * @led_addr: LED register address
5061 * @reg_val: register value to write
5062 **/
i40e_led_set_reg(struct i40e_hw * hw,u16 led_addr,u32 reg_val)5063 static int i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
5064 u32 reg_val)
5065 {
5066 u8 phy_addr = 0;
5067 u8 port_num;
5068 int status;
5069 u32 i;
5070
5071 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5072 status =
5073 i40e_aq_set_phy_register(hw,
5074 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5075 I40E_PHY_COM_REG_PAGE, true,
5076 I40E_PHY_LED_PROV_REG_1,
5077 reg_val, NULL);
5078 } else {
5079 i = rd32(hw, I40E_PFGEN_PORTNUM);
5080 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5081 phy_addr = i40e_get_phy_address(hw, port_num);
5082 status = i40e_write_phy_register_clause45(hw,
5083 I40E_PHY_COM_REG_PAGE,
5084 led_addr, phy_addr,
5085 (u16)reg_val);
5086 }
5087
5088 return status;
5089 }
5090
5091 /**
5092 * i40e_led_get_phy - return current on/off mode
5093 * @hw: pointer to the hw struct
5094 * @led_addr: address of led register to use
5095 * @val: original value of register to use
5096 *
5097 **/
i40e_led_get_phy(struct i40e_hw * hw,u16 * led_addr,u16 * val)5098 int i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
5099 u16 *val)
5100 {
5101 u16 gpio_led_port;
5102 u8 phy_addr = 0;
5103 u32 reg_val_aq;
5104 int status = 0;
5105 u16 temp_addr;
5106 u16 reg_val;
5107 u8 port_num;
5108 u32 i;
5109
5110 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5111 status =
5112 i40e_aq_get_phy_register(hw,
5113 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5114 I40E_PHY_COM_REG_PAGE, true,
5115 I40E_PHY_LED_PROV_REG_1,
5116 ®_val_aq, NULL);
5117 if (status == 0)
5118 *val = (u16)reg_val_aq;
5119 return status;
5120 }
5121 temp_addr = I40E_PHY_LED_PROV_REG_1;
5122 i = rd32(hw, I40E_PFGEN_PORTNUM);
5123 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5124 phy_addr = i40e_get_phy_address(hw, port_num);
5125
5126 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
5127 temp_addr++) {
5128 status = i40e_read_phy_register_clause45(hw,
5129 I40E_PHY_COM_REG_PAGE,
5130 temp_addr, phy_addr,
5131 ®_val);
5132 if (status)
5133 return status;
5134 *val = reg_val;
5135 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
5136 *led_addr = temp_addr;
5137 break;
5138 }
5139 }
5140 return status;
5141 }
5142
5143 /**
5144 * i40e_led_set_phy
5145 * @hw: pointer to the HW structure
5146 * @on: true or false
5147 * @led_addr: address of led register to use
5148 * @mode: original val plus bit for set or ignore
5149 *
5150 * Set led's on or off when controlled by the PHY
5151 *
5152 **/
i40e_led_set_phy(struct i40e_hw * hw,bool on,u16 led_addr,u32 mode)5153 int i40e_led_set_phy(struct i40e_hw *hw, bool on,
5154 u16 led_addr, u32 mode)
5155 {
5156 u32 led_ctl = 0;
5157 u32 led_reg = 0;
5158 int status = 0;
5159
5160 status = i40e_led_get_reg(hw, led_addr, &led_reg);
5161 if (status)
5162 return status;
5163 led_ctl = led_reg;
5164 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
5165 led_reg = 0;
5166 status = i40e_led_set_reg(hw, led_addr, led_reg);
5167 if (status)
5168 return status;
5169 }
5170 status = i40e_led_get_reg(hw, led_addr, &led_reg);
5171 if (status)
5172 goto restore_config;
5173 if (on)
5174 led_reg = I40E_PHY_LED_MANUAL_ON;
5175 else
5176 led_reg = 0;
5177
5178 status = i40e_led_set_reg(hw, led_addr, led_reg);
5179 if (status)
5180 goto restore_config;
5181 if (mode & I40E_PHY_LED_MODE_ORIG) {
5182 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
5183 status = i40e_led_set_reg(hw, led_addr, led_ctl);
5184 }
5185 return status;
5186
5187 restore_config:
5188 status = i40e_led_set_reg(hw, led_addr, led_ctl);
5189 return status;
5190 }
5191
5192 /**
5193 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
5194 * @hw: pointer to the hw struct
5195 * @reg_addr: register address
5196 * @reg_val: ptr to register value
5197 * @cmd_details: pointer to command details structure or NULL
5198 *
5199 * Use the firmware to read the Rx control register,
5200 * especially useful if the Rx unit is under heavy pressure
5201 **/
i40e_aq_rx_ctl_read_register(struct i40e_hw * hw,u32 reg_addr,u32 * reg_val,struct i40e_asq_cmd_details * cmd_details)5202 int i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
5203 u32 reg_addr, u32 *reg_val,
5204 struct i40e_asq_cmd_details *cmd_details)
5205 {
5206 struct i40e_aq_desc desc;
5207 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
5208 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
5209 int status;
5210
5211 if (!reg_val)
5212 return -EINVAL;
5213
5214 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
5215
5216 cmd_resp->address = cpu_to_le32(reg_addr);
5217
5218 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5219
5220 if (status == 0)
5221 *reg_val = le32_to_cpu(cmd_resp->value);
5222
5223 return status;
5224 }
5225
5226 /**
5227 * i40e_read_rx_ctl - read from an Rx control register
5228 * @hw: pointer to the hw struct
5229 * @reg_addr: register address
5230 **/
i40e_read_rx_ctl(struct i40e_hw * hw,u32 reg_addr)5231 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
5232 {
5233 bool use_register;
5234 int status = 0;
5235 int retry = 5;
5236 u32 val = 0;
5237
5238 use_register = (((hw->aq.api_maj_ver == 1) &&
5239 (hw->aq.api_min_ver < 5)) ||
5240 (hw->mac.type == I40E_MAC_X722));
5241 if (!use_register) {
5242 do_retry:
5243 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
5244 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
5245 usleep_range(1000, 2000);
5246 retry--;
5247 goto do_retry;
5248 }
5249 }
5250
5251 /* if the AQ access failed, try the old-fashioned way */
5252 if (status || use_register)
5253 val = rd32(hw, reg_addr);
5254
5255 return val;
5256 }
5257
5258 /**
5259 * i40e_aq_rx_ctl_write_register
5260 * @hw: pointer to the hw struct
5261 * @reg_addr: register address
5262 * @reg_val: register value
5263 * @cmd_details: pointer to command details structure or NULL
5264 *
5265 * Use the firmware to write to an Rx control register,
5266 * especially useful if the Rx unit is under heavy pressure
5267 **/
i40e_aq_rx_ctl_write_register(struct i40e_hw * hw,u32 reg_addr,u32 reg_val,struct i40e_asq_cmd_details * cmd_details)5268 int i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
5269 u32 reg_addr, u32 reg_val,
5270 struct i40e_asq_cmd_details *cmd_details)
5271 {
5272 struct i40e_aq_desc desc;
5273 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
5274 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
5275 int status;
5276
5277 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
5278
5279 cmd->address = cpu_to_le32(reg_addr);
5280 cmd->value = cpu_to_le32(reg_val);
5281
5282 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5283
5284 return status;
5285 }
5286
5287 /**
5288 * i40e_write_rx_ctl - write to an Rx control register
5289 * @hw: pointer to the hw struct
5290 * @reg_addr: register address
5291 * @reg_val: register value
5292 **/
i40e_write_rx_ctl(struct i40e_hw * hw,u32 reg_addr,u32 reg_val)5293 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
5294 {
5295 bool use_register;
5296 int status = 0;
5297 int retry = 5;
5298
5299 use_register = (((hw->aq.api_maj_ver == 1) &&
5300 (hw->aq.api_min_ver < 5)) ||
5301 (hw->mac.type == I40E_MAC_X722));
5302 if (!use_register) {
5303 do_retry:
5304 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
5305 reg_val, NULL);
5306 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
5307 usleep_range(1000, 2000);
5308 retry--;
5309 goto do_retry;
5310 }
5311 }
5312
5313 /* if the AQ access failed, try the old-fashioned way */
5314 if (status || use_register)
5315 wr32(hw, reg_addr, reg_val);
5316 }
5317
5318 /**
5319 * i40e_mdio_if_number_selection - MDIO I/F number selection
5320 * @hw: pointer to the hw struct
5321 * @set_mdio: use MDIO I/F number specified by mdio_num
5322 * @mdio_num: MDIO I/F number
5323 * @cmd: pointer to PHY Register command structure
5324 **/
i40e_mdio_if_number_selection(struct i40e_hw * hw,bool set_mdio,u8 mdio_num,struct i40e_aqc_phy_register_access * cmd)5325 static void i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio,
5326 u8 mdio_num,
5327 struct i40e_aqc_phy_register_access *cmd)
5328 {
5329 if (set_mdio && cmd->phy_interface == I40E_AQ_PHY_REG_ACCESS_EXTERNAL) {
5330 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED)
5331 cmd->cmd_flags |=
5332 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER |
5333 ((mdio_num <<
5334 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) &
5335 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK);
5336 else
5337 i40e_debug(hw, I40E_DEBUG_PHY,
5338 "MDIO I/F number selection not supported by current FW version.\n");
5339 }
5340 }
5341
5342 /**
5343 * i40e_aq_set_phy_register_ext
5344 * @hw: pointer to the hw struct
5345 * @phy_select: select which phy should be accessed
5346 * @dev_addr: PHY device address
5347 * @page_change: flag to indicate if phy page should be updated
5348 * @set_mdio: use MDIO I/F number specified by mdio_num
5349 * @mdio_num: MDIO I/F number
5350 * @reg_addr: PHY register address
5351 * @reg_val: new register value
5352 * @cmd_details: pointer to command details structure or NULL
5353 *
5354 * Write the external PHY register.
5355 * NOTE: In common cases MDIO I/F number should not be changed, thats why you
5356 * may use simple wrapper i40e_aq_set_phy_register.
5357 **/
i40e_aq_set_phy_register_ext(struct i40e_hw * hw,u8 phy_select,u8 dev_addr,bool page_change,bool set_mdio,u8 mdio_num,u32 reg_addr,u32 reg_val,struct i40e_asq_cmd_details * cmd_details)5358 int i40e_aq_set_phy_register_ext(struct i40e_hw *hw,
5359 u8 phy_select, u8 dev_addr, bool page_change,
5360 bool set_mdio, u8 mdio_num,
5361 u32 reg_addr, u32 reg_val,
5362 struct i40e_asq_cmd_details *cmd_details)
5363 {
5364 struct i40e_aq_desc desc;
5365 struct i40e_aqc_phy_register_access *cmd =
5366 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
5367 int status;
5368
5369 i40e_fill_default_direct_cmd_desc(&desc,
5370 i40e_aqc_opc_set_phy_register);
5371
5372 cmd->phy_interface = phy_select;
5373 cmd->dev_address = dev_addr;
5374 cmd->reg_address = cpu_to_le32(reg_addr);
5375 cmd->reg_value = cpu_to_le32(reg_val);
5376
5377 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
5378
5379 if (!page_change)
5380 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
5381
5382 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5383
5384 return status;
5385 }
5386
5387 /**
5388 * i40e_aq_get_phy_register_ext
5389 * @hw: pointer to the hw struct
5390 * @phy_select: select which phy should be accessed
5391 * @dev_addr: PHY device address
5392 * @page_change: flag to indicate if phy page should be updated
5393 * @set_mdio: use MDIO I/F number specified by mdio_num
5394 * @mdio_num: MDIO I/F number
5395 * @reg_addr: PHY register address
5396 * @reg_val: read register value
5397 * @cmd_details: pointer to command details structure or NULL
5398 *
5399 * Read the external PHY register.
5400 * NOTE: In common cases MDIO I/F number should not be changed, thats why you
5401 * may use simple wrapper i40e_aq_get_phy_register.
5402 **/
i40e_aq_get_phy_register_ext(struct i40e_hw * hw,u8 phy_select,u8 dev_addr,bool page_change,bool set_mdio,u8 mdio_num,u32 reg_addr,u32 * reg_val,struct i40e_asq_cmd_details * cmd_details)5403 int i40e_aq_get_phy_register_ext(struct i40e_hw *hw,
5404 u8 phy_select, u8 dev_addr, bool page_change,
5405 bool set_mdio, u8 mdio_num,
5406 u32 reg_addr, u32 *reg_val,
5407 struct i40e_asq_cmd_details *cmd_details)
5408 {
5409 struct i40e_aq_desc desc;
5410 struct i40e_aqc_phy_register_access *cmd =
5411 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
5412 int status;
5413
5414 i40e_fill_default_direct_cmd_desc(&desc,
5415 i40e_aqc_opc_get_phy_register);
5416
5417 cmd->phy_interface = phy_select;
5418 cmd->dev_address = dev_addr;
5419 cmd->reg_address = cpu_to_le32(reg_addr);
5420
5421 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
5422
5423 if (!page_change)
5424 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
5425
5426 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5427 if (!status)
5428 *reg_val = le32_to_cpu(cmd->reg_value);
5429
5430 return status;
5431 }
5432
5433 /**
5434 * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
5435 * @hw: pointer to the hw struct
5436 * @buff: command buffer (size in bytes = buff_size)
5437 * @buff_size: buffer size in bytes
5438 * @track_id: package tracking id
5439 * @error_offset: returns error offset
5440 * @error_info: returns error information
5441 * @cmd_details: pointer to command details structure or NULL
5442 **/
i40e_aq_write_ddp(struct i40e_hw * hw,void * buff,u16 buff_size,u32 track_id,u32 * error_offset,u32 * error_info,struct i40e_asq_cmd_details * cmd_details)5443 int i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
5444 u16 buff_size, u32 track_id,
5445 u32 *error_offset, u32 *error_info,
5446 struct i40e_asq_cmd_details *cmd_details)
5447 {
5448 struct i40e_aq_desc desc;
5449 struct i40e_aqc_write_personalization_profile *cmd =
5450 (struct i40e_aqc_write_personalization_profile *)
5451 &desc.params.raw;
5452 struct i40e_aqc_write_ddp_resp *resp;
5453 int status;
5454
5455 i40e_fill_default_direct_cmd_desc(&desc,
5456 i40e_aqc_opc_write_personalization_profile);
5457
5458 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
5459 if (buff_size > I40E_AQ_LARGE_BUF)
5460 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5461
5462 desc.datalen = cpu_to_le16(buff_size);
5463
5464 cmd->profile_track_id = cpu_to_le32(track_id);
5465
5466 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5467 if (!status) {
5468 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
5469 if (error_offset)
5470 *error_offset = le32_to_cpu(resp->error_offset);
5471 if (error_info)
5472 *error_info = le32_to_cpu(resp->error_info);
5473 }
5474
5475 return status;
5476 }
5477
5478 /**
5479 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
5480 * @hw: pointer to the hw struct
5481 * @buff: command buffer (size in bytes = buff_size)
5482 * @buff_size: buffer size in bytes
5483 * @flags: AdminQ command flags
5484 * @cmd_details: pointer to command details structure or NULL
5485 **/
i40e_aq_get_ddp_list(struct i40e_hw * hw,void * buff,u16 buff_size,u8 flags,struct i40e_asq_cmd_details * cmd_details)5486 int i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
5487 u16 buff_size, u8 flags,
5488 struct i40e_asq_cmd_details *cmd_details)
5489 {
5490 struct i40e_aq_desc desc;
5491 struct i40e_aqc_get_applied_profiles *cmd =
5492 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
5493 int status;
5494
5495 i40e_fill_default_direct_cmd_desc(&desc,
5496 i40e_aqc_opc_get_personalization_profile_list);
5497
5498 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
5499 if (buff_size > I40E_AQ_LARGE_BUF)
5500 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5501 desc.datalen = cpu_to_le16(buff_size);
5502
5503 cmd->flags = flags;
5504
5505 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5506
5507 return status;
5508 }
5509
5510 /**
5511 * i40e_find_segment_in_package
5512 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
5513 * @pkg_hdr: pointer to the package header to be searched
5514 *
5515 * This function searches a package file for a particular segment type. On
5516 * success it returns a pointer to the segment header, otherwise it will
5517 * return NULL.
5518 **/
5519 struct i40e_generic_seg_header *
i40e_find_segment_in_package(u32 segment_type,struct i40e_package_header * pkg_hdr)5520 i40e_find_segment_in_package(u32 segment_type,
5521 struct i40e_package_header *pkg_hdr)
5522 {
5523 struct i40e_generic_seg_header *segment;
5524 u32 i;
5525
5526 /* Search all package segments for the requested segment type */
5527 for (i = 0; i < pkg_hdr->segment_count; i++) {
5528 segment =
5529 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
5530 pkg_hdr->segment_offset[i]);
5531
5532 if (segment->type == segment_type)
5533 return segment;
5534 }
5535
5536 return NULL;
5537 }
5538
5539 /* Get section table in profile */
5540 #define I40E_SECTION_TABLE(profile, sec_tbl) \
5541 do { \
5542 struct i40e_profile_segment *p = (profile); \
5543 u32 count; \
5544 u32 *nvm; \
5545 count = p->device_table_count; \
5546 nvm = (u32 *)&p->device_table[count]; \
5547 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
5548 } while (0)
5549
5550 /* Get section header in profile */
5551 #define I40E_SECTION_HEADER(profile, offset) \
5552 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
5553
5554 /**
5555 * i40e_find_section_in_profile
5556 * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
5557 * @profile: pointer to the i40e segment header to be searched
5558 *
5559 * This function searches i40e segment for a particular section type. On
5560 * success it returns a pointer to the section header, otherwise it will
5561 * return NULL.
5562 **/
5563 struct i40e_profile_section_header *
i40e_find_section_in_profile(u32 section_type,struct i40e_profile_segment * profile)5564 i40e_find_section_in_profile(u32 section_type,
5565 struct i40e_profile_segment *profile)
5566 {
5567 struct i40e_profile_section_header *sec;
5568 struct i40e_section_table *sec_tbl;
5569 u32 sec_off;
5570 u32 i;
5571
5572 if (profile->header.type != SEGMENT_TYPE_I40E)
5573 return NULL;
5574
5575 I40E_SECTION_TABLE(profile, sec_tbl);
5576
5577 for (i = 0; i < sec_tbl->section_count; i++) {
5578 sec_off = sec_tbl->section_offset[i];
5579 sec = I40E_SECTION_HEADER(profile, sec_off);
5580 if (sec->section.type == section_type)
5581 return sec;
5582 }
5583
5584 return NULL;
5585 }
5586
5587 /**
5588 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
5589 * @hw: pointer to the hw struct
5590 * @aq: command buffer containing all data to execute AQ
5591 **/
i40e_ddp_exec_aq_section(struct i40e_hw * hw,struct i40e_profile_aq_section * aq)5592 static int i40e_ddp_exec_aq_section(struct i40e_hw *hw,
5593 struct i40e_profile_aq_section *aq)
5594 {
5595 struct i40e_aq_desc desc;
5596 u8 *msg = NULL;
5597 u16 msglen;
5598 int status;
5599
5600 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
5601 desc.flags |= cpu_to_le16(aq->flags);
5602 memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw));
5603
5604 msglen = aq->datalen;
5605 if (msglen) {
5606 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
5607 I40E_AQ_FLAG_RD));
5608 if (msglen > I40E_AQ_LARGE_BUF)
5609 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5610 desc.datalen = cpu_to_le16(msglen);
5611 msg = &aq->data[0];
5612 }
5613
5614 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
5615
5616 if (status) {
5617 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5618 "unable to exec DDP AQ opcode %u, error %d\n",
5619 aq->opcode, status);
5620 return status;
5621 }
5622
5623 /* copy returned desc to aq_buf */
5624 memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw));
5625
5626 return 0;
5627 }
5628
5629 /**
5630 * i40e_validate_profile
5631 * @hw: pointer to the hardware structure
5632 * @profile: pointer to the profile segment of the package to be validated
5633 * @track_id: package tracking id
5634 * @rollback: flag if the profile is for rollback.
5635 *
5636 * Validates supported devices and profile's sections.
5637 */
5638 static int
i40e_validate_profile(struct i40e_hw * hw,struct i40e_profile_segment * profile,u32 track_id,bool rollback)5639 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5640 u32 track_id, bool rollback)
5641 {
5642 struct i40e_profile_section_header *sec = NULL;
5643 struct i40e_section_table *sec_tbl;
5644 u32 vendor_dev_id;
5645 int status = 0;
5646 u32 dev_cnt;
5647 u32 sec_off;
5648 u32 i;
5649
5650 if (track_id == I40E_DDP_TRACKID_INVALID) {
5651 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
5652 return -EOPNOTSUPP;
5653 }
5654
5655 dev_cnt = profile->device_table_count;
5656 for (i = 0; i < dev_cnt; i++) {
5657 vendor_dev_id = profile->device_table[i].vendor_dev_id;
5658 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL &&
5659 hw->device_id == (vendor_dev_id & 0xFFFF))
5660 break;
5661 }
5662 if (dev_cnt && i == dev_cnt) {
5663 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5664 "Device doesn't support DDP\n");
5665 return -ENODEV;
5666 }
5667
5668 I40E_SECTION_TABLE(profile, sec_tbl);
5669
5670 /* Validate sections types */
5671 for (i = 0; i < sec_tbl->section_count; i++) {
5672 sec_off = sec_tbl->section_offset[i];
5673 sec = I40E_SECTION_HEADER(profile, sec_off);
5674 if (rollback) {
5675 if (sec->section.type == SECTION_TYPE_MMIO ||
5676 sec->section.type == SECTION_TYPE_AQ ||
5677 sec->section.type == SECTION_TYPE_RB_AQ) {
5678 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5679 "Not a roll-back package\n");
5680 return -EOPNOTSUPP;
5681 }
5682 } else {
5683 if (sec->section.type == SECTION_TYPE_RB_AQ ||
5684 sec->section.type == SECTION_TYPE_RB_MMIO) {
5685 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5686 "Not an original package\n");
5687 return -EOPNOTSUPP;
5688 }
5689 }
5690 }
5691
5692 return status;
5693 }
5694
5695 /**
5696 * i40e_write_profile
5697 * @hw: pointer to the hardware structure
5698 * @profile: pointer to the profile segment of the package to be downloaded
5699 * @track_id: package tracking id
5700 *
5701 * Handles the download of a complete package.
5702 */
5703 int
i40e_write_profile(struct i40e_hw * hw,struct i40e_profile_segment * profile,u32 track_id)5704 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5705 u32 track_id)
5706 {
5707 struct i40e_profile_section_header *sec = NULL;
5708 struct i40e_profile_aq_section *ddp_aq;
5709 struct i40e_section_table *sec_tbl;
5710 u32 offset = 0, info = 0;
5711 u32 section_size = 0;
5712 int status = 0;
5713 u32 sec_off;
5714 u32 i;
5715
5716 status = i40e_validate_profile(hw, profile, track_id, false);
5717 if (status)
5718 return status;
5719
5720 I40E_SECTION_TABLE(profile, sec_tbl);
5721
5722 for (i = 0; i < sec_tbl->section_count; i++) {
5723 sec_off = sec_tbl->section_offset[i];
5724 sec = I40E_SECTION_HEADER(profile, sec_off);
5725 /* Process generic admin command */
5726 if (sec->section.type == SECTION_TYPE_AQ) {
5727 ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
5728 status = i40e_ddp_exec_aq_section(hw, ddp_aq);
5729 if (status) {
5730 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5731 "Failed to execute aq: section %d, opcode %u\n",
5732 i, ddp_aq->opcode);
5733 break;
5734 }
5735 sec->section.type = SECTION_TYPE_RB_AQ;
5736 }
5737
5738 /* Skip any non-mmio sections */
5739 if (sec->section.type != SECTION_TYPE_MMIO)
5740 continue;
5741
5742 section_size = sec->section.size +
5743 sizeof(struct i40e_profile_section_header);
5744
5745 /* Write MMIO section */
5746 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
5747 track_id, &offset, &info, NULL);
5748 if (status) {
5749 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5750 "Failed to write profile: section %d, offset %d, info %d\n",
5751 i, offset, info);
5752 break;
5753 }
5754 }
5755 return status;
5756 }
5757
5758 /**
5759 * i40e_rollback_profile
5760 * @hw: pointer to the hardware structure
5761 * @profile: pointer to the profile segment of the package to be removed
5762 * @track_id: package tracking id
5763 *
5764 * Rolls back previously loaded package.
5765 */
5766 int
i40e_rollback_profile(struct i40e_hw * hw,struct i40e_profile_segment * profile,u32 track_id)5767 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5768 u32 track_id)
5769 {
5770 struct i40e_profile_section_header *sec = NULL;
5771 struct i40e_section_table *sec_tbl;
5772 u32 offset = 0, info = 0;
5773 u32 section_size = 0;
5774 int status = 0;
5775 u32 sec_off;
5776 int i;
5777
5778 status = i40e_validate_profile(hw, profile, track_id, true);
5779 if (status)
5780 return status;
5781
5782 I40E_SECTION_TABLE(profile, sec_tbl);
5783
5784 /* For rollback write sections in reverse */
5785 for (i = sec_tbl->section_count - 1; i >= 0; i--) {
5786 sec_off = sec_tbl->section_offset[i];
5787 sec = I40E_SECTION_HEADER(profile, sec_off);
5788
5789 /* Skip any non-rollback sections */
5790 if (sec->section.type != SECTION_TYPE_RB_MMIO)
5791 continue;
5792
5793 section_size = sec->section.size +
5794 sizeof(struct i40e_profile_section_header);
5795
5796 /* Write roll-back MMIO section */
5797 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
5798 track_id, &offset, &info, NULL);
5799 if (status) {
5800 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5801 "Failed to write profile: section %d, offset %d, info %d\n",
5802 i, offset, info);
5803 break;
5804 }
5805 }
5806 return status;
5807 }
5808
5809 /**
5810 * i40e_add_pinfo_to_list
5811 * @hw: pointer to the hardware structure
5812 * @profile: pointer to the profile segment of the package
5813 * @profile_info_sec: buffer for information section
5814 * @track_id: package tracking id
5815 *
5816 * Register a profile to the list of loaded profiles.
5817 */
5818 int
i40e_add_pinfo_to_list(struct i40e_hw * hw,struct i40e_profile_segment * profile,u8 * profile_info_sec,u32 track_id)5819 i40e_add_pinfo_to_list(struct i40e_hw *hw,
5820 struct i40e_profile_segment *profile,
5821 u8 *profile_info_sec, u32 track_id)
5822 {
5823 struct i40e_profile_section_header *sec = NULL;
5824 struct i40e_profile_info *pinfo;
5825 u32 offset = 0, info = 0;
5826 int status = 0;
5827
5828 sec = (struct i40e_profile_section_header *)profile_info_sec;
5829 sec->tbl_size = 1;
5830 sec->data_end = sizeof(struct i40e_profile_section_header) +
5831 sizeof(struct i40e_profile_info);
5832 sec->section.type = SECTION_TYPE_INFO;
5833 sec->section.offset = sizeof(struct i40e_profile_section_header);
5834 sec->section.size = sizeof(struct i40e_profile_info);
5835 pinfo = (struct i40e_profile_info *)(profile_info_sec +
5836 sec->section.offset);
5837 pinfo->track_id = track_id;
5838 pinfo->version = profile->version;
5839 pinfo->op = I40E_DDP_ADD_TRACKID;
5840 memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);
5841
5842 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
5843 track_id, &offset, &info, NULL);
5844
5845 return status;
5846 }
5847
5848 /**
5849 * i40e_aq_add_cloud_filters
5850 * @hw: pointer to the hardware structure
5851 * @seid: VSI seid to add cloud filters from
5852 * @filters: Buffer which contains the filters to be added
5853 * @filter_count: number of filters contained in the buffer
5854 *
5855 * Set the cloud filters for a given VSI. The contents of the
5856 * i40e_aqc_cloud_filters_element_data are filled in by the caller
5857 * of the function.
5858 *
5859 **/
5860 int
i40e_aq_add_cloud_filters(struct i40e_hw * hw,u16 seid,struct i40e_aqc_cloud_filters_element_data * filters,u8 filter_count)5861 i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid,
5862 struct i40e_aqc_cloud_filters_element_data *filters,
5863 u8 filter_count)
5864 {
5865 struct i40e_aq_desc desc;
5866 struct i40e_aqc_add_remove_cloud_filters *cmd =
5867 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5868 u16 buff_len;
5869 int status;
5870
5871 i40e_fill_default_direct_cmd_desc(&desc,
5872 i40e_aqc_opc_add_cloud_filters);
5873
5874 buff_len = filter_count * sizeof(*filters);
5875 desc.datalen = cpu_to_le16(buff_len);
5876 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5877 cmd->num_filters = filter_count;
5878 cmd->seid = cpu_to_le16(seid);
5879
5880 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5881
5882 return status;
5883 }
5884
5885 /**
5886 * i40e_aq_add_cloud_filters_bb
5887 * @hw: pointer to the hardware structure
5888 * @seid: VSI seid to add cloud filters from
5889 * @filters: Buffer which contains the filters in big buffer to be added
5890 * @filter_count: number of filters contained in the buffer
5891 *
5892 * Set the big buffer cloud filters for a given VSI. The contents of the
5893 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5894 * function.
5895 *
5896 **/
5897 int
i40e_aq_add_cloud_filters_bb(struct i40e_hw * hw,u16 seid,struct i40e_aqc_cloud_filters_element_bb * filters,u8 filter_count)5898 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5899 struct i40e_aqc_cloud_filters_element_bb *filters,
5900 u8 filter_count)
5901 {
5902 struct i40e_aq_desc desc;
5903 struct i40e_aqc_add_remove_cloud_filters *cmd =
5904 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5905 u16 buff_len;
5906 int status;
5907 int i;
5908
5909 i40e_fill_default_direct_cmd_desc(&desc,
5910 i40e_aqc_opc_add_cloud_filters);
5911
5912 buff_len = filter_count * sizeof(*filters);
5913 desc.datalen = cpu_to_le16(buff_len);
5914 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5915 cmd->num_filters = filter_count;
5916 cmd->seid = cpu_to_le16(seid);
5917 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5918
5919 for (i = 0; i < filter_count; i++) {
5920 u16 tnl_type;
5921 u32 ti;
5922
5923 tnl_type = (le16_to_cpu(filters[i].element.flags) &
5924 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5925 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5926
5927 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5928 * one more byte further than normally used for Tenant ID in
5929 * other tunnel types.
5930 */
5931 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5932 ti = le32_to_cpu(filters[i].element.tenant_id);
5933 filters[i].element.tenant_id = cpu_to_le32(ti << 8);
5934 }
5935 }
5936
5937 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5938
5939 return status;
5940 }
5941
5942 /**
5943 * i40e_aq_rem_cloud_filters
5944 * @hw: pointer to the hardware structure
5945 * @seid: VSI seid to remove cloud filters from
5946 * @filters: Buffer which contains the filters to be removed
5947 * @filter_count: number of filters contained in the buffer
5948 *
5949 * Remove the cloud filters for a given VSI. The contents of the
5950 * i40e_aqc_cloud_filters_element_data are filled in by the caller
5951 * of the function.
5952 *
5953 **/
5954 int
i40e_aq_rem_cloud_filters(struct i40e_hw * hw,u16 seid,struct i40e_aqc_cloud_filters_element_data * filters,u8 filter_count)5955 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5956 struct i40e_aqc_cloud_filters_element_data *filters,
5957 u8 filter_count)
5958 {
5959 struct i40e_aq_desc desc;
5960 struct i40e_aqc_add_remove_cloud_filters *cmd =
5961 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5962 u16 buff_len;
5963 int status;
5964
5965 i40e_fill_default_direct_cmd_desc(&desc,
5966 i40e_aqc_opc_remove_cloud_filters);
5967
5968 buff_len = filter_count * sizeof(*filters);
5969 desc.datalen = cpu_to_le16(buff_len);
5970 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5971 cmd->num_filters = filter_count;
5972 cmd->seid = cpu_to_le16(seid);
5973
5974 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5975
5976 return status;
5977 }
5978
5979 /**
5980 * i40e_aq_rem_cloud_filters_bb
5981 * @hw: pointer to the hardware structure
5982 * @seid: VSI seid to remove cloud filters from
5983 * @filters: Buffer which contains the filters in big buffer to be removed
5984 * @filter_count: number of filters contained in the buffer
5985 *
5986 * Remove the big buffer cloud filters for a given VSI. The contents of the
5987 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5988 * function.
5989 *
5990 **/
5991 int
i40e_aq_rem_cloud_filters_bb(struct i40e_hw * hw,u16 seid,struct i40e_aqc_cloud_filters_element_bb * filters,u8 filter_count)5992 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5993 struct i40e_aqc_cloud_filters_element_bb *filters,
5994 u8 filter_count)
5995 {
5996 struct i40e_aq_desc desc;
5997 struct i40e_aqc_add_remove_cloud_filters *cmd =
5998 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5999 u16 buff_len;
6000 int status;
6001 int i;
6002
6003 i40e_fill_default_direct_cmd_desc(&desc,
6004 i40e_aqc_opc_remove_cloud_filters);
6005
6006 buff_len = filter_count * sizeof(*filters);
6007 desc.datalen = cpu_to_le16(buff_len);
6008 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
6009 cmd->num_filters = filter_count;
6010 cmd->seid = cpu_to_le16(seid);
6011 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
6012
6013 for (i = 0; i < filter_count; i++) {
6014 u16 tnl_type;
6015 u32 ti;
6016
6017 tnl_type = (le16_to_cpu(filters[i].element.flags) &
6018 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
6019 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
6020
6021 /* Due to hardware eccentricities, the VNI for Geneve is shifted
6022 * one more byte further than normally used for Tenant ID in
6023 * other tunnel types.
6024 */
6025 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
6026 ti = le32_to_cpu(filters[i].element.tenant_id);
6027 filters[i].element.tenant_id = cpu_to_le32(ti << 8);
6028 }
6029 }
6030
6031 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
6032
6033 return status;
6034 }
6035