1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2002 Motorola GSG-China
4 *
5 * Author:
6 * Darius Augulis, Teltonika Inc.
7 *
8 * Desc.:
9 * Implementation of I2C Adapter/Algorithm Driver
10 * for I2C Bus integrated in Freescale i.MX/MXC processors
11 *
12 * Derived from Motorola GSG China I2C example driver
13 *
14 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
15 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
16 * Copyright (C) 2007 RightHand Technologies, Inc.
17 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
18 *
19 * Copyright 2013 Freescale Semiconductor, Inc.
20 * Copyright 2020 NXP
21 *
22 */
23
24 #include <linux/acpi.h>
25 #include <linux/clk.h>
26 #include <linux/completion.h>
27 #include <linux/delay.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/dmaengine.h>
30 #include <linux/dmapool.h>
31 #include <linux/err.h>
32 #include <linux/errno.h>
33 #include <linux/gpio/consumer.h>
34 #include <linux/i2c.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/io.h>
38 #include <linux/iopoll.h>
39 #include <linux/kernel.h>
40 #include <linux/spinlock.h>
41 #include <linux/hrtimer.h>
42 #include <linux/module.h>
43 #include <linux/of.h>
44 #include <linux/of_dma.h>
45 #include <linux/pinctrl/consumer.h>
46 #include <linux/platform_data/i2c-imx.h>
47 #include <linux/platform_device.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/sched.h>
50 #include <linux/slab.h>
51
52 /* This will be the driver name the kernel reports */
53 #define DRIVER_NAME "imx-i2c"
54
55 #define I2C_IMX_CHECK_DELAY 30000 /* Time to check for bus idle, in NS */
56
57 /*
58 * Enable DMA if transfer byte size is bigger than this threshold.
59 * As the hardware request, it must bigger than 4 bytes.\
60 * I have set '16' here, maybe it's not the best but I think it's
61 * the appropriate.
62 */
63 #define DMA_THRESHOLD 16
64 #define DMA_TIMEOUT 1000
65
66 /* IMX I2C registers:
67 * the I2C register offset is different between SoCs,
68 * to provide support for all these chips, split the
69 * register offset into a fixed base address and a
70 * variable shift value, then the full register offset
71 * will be calculated by
72 * reg_off = ( reg_base_addr << reg_shift)
73 */
74 #define IMX_I2C_IADR 0x00 /* i2c slave address */
75 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */
76 #define IMX_I2C_I2CR 0x02 /* i2c control */
77 #define IMX_I2C_I2SR 0x03 /* i2c status */
78 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */
79
80 /*
81 * All of the layerscape series SoCs support IBIC register.
82 */
83 #define IMX_I2C_IBIC 0x05 /* i2c bus interrupt config */
84
85 #define IMX_I2C_REGSHIFT 2
86 #define VF610_I2C_REGSHIFT 0
87
88 /* Bits of IMX I2C registers */
89 #define I2SR_RXAK 0x01
90 #define I2SR_IIF 0x02
91 #define I2SR_SRW 0x04
92 #define I2SR_IAL 0x10
93 #define I2SR_IBB 0x20
94 #define I2SR_IAAS 0x40
95 #define I2SR_ICF 0x80
96 #define I2CR_DMAEN 0x02
97 #define I2CR_RSTA 0x04
98 #define I2CR_TXAK 0x08
99 #define I2CR_MTX 0x10
100 #define I2CR_MSTA 0x20
101 #define I2CR_IIEN 0x40
102 #define I2CR_IEN 0x80
103 #define IBIC_BIIE 0x80 /* Bus idle interrupt enable */
104
105 /* register bits different operating codes definition:
106 * 1) I2SR: Interrupt flags clear operation differ between SoCs:
107 * - write zero to clear(w0c) INT flag on i.MX,
108 * - but write one to clear(w1c) INT flag on Vybrid.
109 * 2) I2CR: I2C module enable operation also differ between SoCs:
110 * - set I2CR_IEN bit enable the module on i.MX,
111 * - but clear I2CR_IEN bit enable the module on Vybrid.
112 */
113 #define I2SR_CLR_OPCODE_W0C 0x0
114 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF)
115 #define I2CR_IEN_OPCODE_0 0x0
116 #define I2CR_IEN_OPCODE_1 I2CR_IEN
117
118 #define I2C_PM_TIMEOUT 10 /* ms */
119
120 /*
121 * sorted list of clock divider, register value pairs
122 * taken from table 26-5, p.26-9, Freescale i.MX
123 * Integrated Portable System Processor Reference Manual
124 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
125 *
126 * Duplicated divider values removed from list
127 */
128 struct imx_i2c_clk_pair {
129 u16 div;
130 u16 val;
131 };
132
133 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
134 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
135 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
136 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
137 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
138 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
139 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
140 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
141 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
142 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
143 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
144 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
145 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
146 { 3072, 0x1E }, { 3840, 0x1F }
147 };
148
149 /* Vybrid VF610 clock divider, register value pairs */
150 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
151 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
152 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
153 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
154 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
155 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
156 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
157 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
158 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
159 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
160 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
161 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
162 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
163 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
164 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
165 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
166 };
167
168 enum imx_i2c_type {
169 IMX1_I2C,
170 IMX21_I2C,
171 VF610_I2C,
172 };
173
174 struct imx_i2c_hwdata {
175 enum imx_i2c_type devtype;
176 unsigned int regshift;
177 struct imx_i2c_clk_pair *clk_div;
178 unsigned int ndivs;
179 unsigned int i2sr_clr_opcode;
180 unsigned int i2cr_ien_opcode;
181 /*
182 * Errata ERR007805 or e7805:
183 * I2C: When the I2C clock speed is configured for 400 kHz,
184 * the SCL low period violates the I2C spec of 1.3 uS min.
185 */
186 bool has_err007805;
187 };
188
189 struct imx_i2c_dma {
190 struct dma_chan *chan_tx;
191 struct dma_chan *chan_rx;
192 struct dma_chan *chan_using;
193 struct completion cmd_complete;
194 dma_addr_t dma_buf;
195 unsigned int dma_len;
196 enum dma_transfer_direction dma_transfer_dir;
197 enum dma_data_direction dma_data_dir;
198 };
199
200 struct imx_i2c_struct {
201 struct i2c_adapter adapter;
202 struct clk *clk;
203 struct notifier_block clk_change_nb;
204 void __iomem *base;
205 wait_queue_head_t queue;
206 unsigned long i2csr;
207 unsigned int disable_delay;
208 int stopped;
209 unsigned int ifdr; /* IMX_I2C_IFDR */
210 unsigned int cur_clk;
211 unsigned int bitrate;
212 const struct imx_i2c_hwdata *hwdata;
213 struct i2c_bus_recovery_info rinfo;
214
215 struct pinctrl *pinctrl;
216 struct pinctrl_state *pinctrl_pins_default;
217 struct pinctrl_state *pinctrl_pins_gpio;
218
219 struct imx_i2c_dma *dma;
220 struct i2c_client *slave;
221 enum i2c_slave_event last_slave_event;
222
223 /* For checking slave events. */
224 spinlock_t slave_lock;
225 struct hrtimer slave_timer;
226 };
227
228 static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
229 .devtype = IMX1_I2C,
230 .regshift = IMX_I2C_REGSHIFT,
231 .clk_div = imx_i2c_clk_div,
232 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
233 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
234 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
235
236 };
237
238 static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
239 .devtype = IMX21_I2C,
240 .regshift = IMX_I2C_REGSHIFT,
241 .clk_div = imx_i2c_clk_div,
242 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
243 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
244 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
245
246 };
247
248 static const struct imx_i2c_hwdata imx6_i2c_hwdata = {
249 .devtype = IMX21_I2C,
250 .regshift = IMX_I2C_REGSHIFT,
251 .clk_div = imx_i2c_clk_div,
252 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
253 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
254 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
255 .has_err007805 = true,
256 };
257
258 static struct imx_i2c_hwdata vf610_i2c_hwdata = {
259 .devtype = VF610_I2C,
260 .regshift = VF610_I2C_REGSHIFT,
261 .clk_div = vf610_i2c_clk_div,
262 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div),
263 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C,
264 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0,
265
266 };
267
268 static const struct platform_device_id imx_i2c_devtype[] = {
269 {
270 .name = "imx1-i2c",
271 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
272 }, {
273 .name = "imx21-i2c",
274 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
275 }, {
276 /* sentinel */
277 }
278 };
279 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
280
281 static const struct of_device_id i2c_imx_dt_ids[] = {
282 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
283 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
284 { .compatible = "fsl,imx6q-i2c", .data = &imx6_i2c_hwdata, },
285 { .compatible = "fsl,imx6sl-i2c", .data = &imx6_i2c_hwdata, },
286 { .compatible = "fsl,imx6sll-i2c", .data = &imx6_i2c_hwdata, },
287 { .compatible = "fsl,imx6sx-i2c", .data = &imx6_i2c_hwdata, },
288 { .compatible = "fsl,imx6ul-i2c", .data = &imx6_i2c_hwdata, },
289 { .compatible = "fsl,imx7d-i2c", .data = &imx6_i2c_hwdata, },
290 { .compatible = "fsl,imx7s-i2c", .data = &imx6_i2c_hwdata, },
291 { .compatible = "fsl,imx8mm-i2c", .data = &imx6_i2c_hwdata, },
292 { .compatible = "fsl,imx8mn-i2c", .data = &imx6_i2c_hwdata, },
293 { .compatible = "fsl,imx8mp-i2c", .data = &imx6_i2c_hwdata, },
294 { .compatible = "fsl,imx8mq-i2c", .data = &imx6_i2c_hwdata, },
295 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
296 { /* sentinel */ }
297 };
298 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
299
300 static const struct acpi_device_id i2c_imx_acpi_ids[] = {
301 {"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata},
302 { }
303 };
304 MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids);
305
is_imx1_i2c(struct imx_i2c_struct * i2c_imx)306 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
307 {
308 return i2c_imx->hwdata->devtype == IMX1_I2C;
309 }
310
is_vf610_i2c(struct imx_i2c_struct * i2c_imx)311 static inline int is_vf610_i2c(struct imx_i2c_struct *i2c_imx)
312 {
313 return i2c_imx->hwdata->devtype == VF610_I2C;
314 }
315
imx_i2c_write_reg(unsigned int val,struct imx_i2c_struct * i2c_imx,unsigned int reg)316 static inline void imx_i2c_write_reg(unsigned int val,
317 struct imx_i2c_struct *i2c_imx, unsigned int reg)
318 {
319 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
320 }
321
imx_i2c_read_reg(struct imx_i2c_struct * i2c_imx,unsigned int reg)322 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
323 unsigned int reg)
324 {
325 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
326 }
327
i2c_imx_clear_irq(struct imx_i2c_struct * i2c_imx,unsigned int bits)328 static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits)
329 {
330 unsigned int temp;
331
332 /*
333 * i2sr_clr_opcode is the value to clear all interrupts. Here we want to
334 * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits>
335 * toggled. This is required because i.MX needs W0C and Vybrid uses W1C.
336 */
337 temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits;
338 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
339 }
340
341 /* Set up i2c controller register and i2c status register to default value. */
i2c_imx_reset_regs(struct imx_i2c_struct * i2c_imx)342 static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx)
343 {
344 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
345 i2c_imx, IMX_I2C_I2CR);
346 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL);
347 }
348
349 /* Functions for DMA support */
i2c_imx_dma_request(struct imx_i2c_struct * i2c_imx,dma_addr_t phy_addr)350 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
351 dma_addr_t phy_addr)
352 {
353 struct imx_i2c_dma *dma;
354 struct dma_slave_config dma_sconfig;
355 struct device *dev = &i2c_imx->adapter.dev;
356 int ret;
357
358 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
359 if (!dma)
360 return;
361
362 dma->chan_tx = dma_request_chan(dev, "tx");
363 if (IS_ERR(dma->chan_tx)) {
364 ret = PTR_ERR(dma->chan_tx);
365 if (ret != -ENODEV && ret != -EPROBE_DEFER)
366 dev_err(dev, "can't request DMA tx channel (%d)\n", ret);
367 goto fail_al;
368 }
369
370 dma_sconfig.dst_addr = phy_addr +
371 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
372 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
373 dma_sconfig.dst_maxburst = 1;
374 dma_sconfig.direction = DMA_MEM_TO_DEV;
375 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
376 if (ret < 0) {
377 dev_err(dev, "can't configure tx channel (%d)\n", ret);
378 goto fail_tx;
379 }
380
381 dma->chan_rx = dma_request_chan(dev, "rx");
382 if (IS_ERR(dma->chan_rx)) {
383 ret = PTR_ERR(dma->chan_rx);
384 if (ret != -ENODEV && ret != -EPROBE_DEFER)
385 dev_err(dev, "can't request DMA rx channel (%d)\n", ret);
386 goto fail_tx;
387 }
388
389 dma_sconfig.src_addr = phy_addr +
390 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
391 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
392 dma_sconfig.src_maxburst = 1;
393 dma_sconfig.direction = DMA_DEV_TO_MEM;
394 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
395 if (ret < 0) {
396 dev_err(dev, "can't configure rx channel (%d)\n", ret);
397 goto fail_rx;
398 }
399
400 i2c_imx->dma = dma;
401 init_completion(&dma->cmd_complete);
402 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
403 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
404
405 return;
406
407 fail_rx:
408 dma_release_channel(dma->chan_rx);
409 fail_tx:
410 dma_release_channel(dma->chan_tx);
411 fail_al:
412 devm_kfree(dev, dma);
413 }
414
i2c_imx_dma_callback(void * arg)415 static void i2c_imx_dma_callback(void *arg)
416 {
417 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;
418 struct imx_i2c_dma *dma = i2c_imx->dma;
419
420 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
421 dma->dma_len, dma->dma_data_dir);
422 complete(&dma->cmd_complete);
423 }
424
i2c_imx_dma_xfer(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs)425 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,
426 struct i2c_msg *msgs)
427 {
428 struct imx_i2c_dma *dma = i2c_imx->dma;
429 struct dma_async_tx_descriptor *txdesc;
430 struct device *dev = &i2c_imx->adapter.dev;
431 struct device *chan_dev = dma->chan_using->device->dev;
432
433 dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
434 dma->dma_len, dma->dma_data_dir);
435 if (dma_mapping_error(chan_dev, dma->dma_buf)) {
436 dev_err(dev, "DMA mapping failed\n");
437 goto err_map;
438 }
439
440 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
441 dma->dma_len, dma->dma_transfer_dir,
442 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
443 if (!txdesc) {
444 dev_err(dev, "Not able to get desc for DMA xfer\n");
445 goto err_desc;
446 }
447
448 reinit_completion(&dma->cmd_complete);
449 txdesc->callback = i2c_imx_dma_callback;
450 txdesc->callback_param = i2c_imx;
451 if (dma_submit_error(dmaengine_submit(txdesc))) {
452 dev_err(dev, "DMA submit failed\n");
453 goto err_submit;
454 }
455
456 dma_async_issue_pending(dma->chan_using);
457 return 0;
458
459 err_submit:
460 dmaengine_terminate_sync(dma->chan_using);
461 err_desc:
462 dma_unmap_single(chan_dev, dma->dma_buf,
463 dma->dma_len, dma->dma_data_dir);
464 err_map:
465 return -EINVAL;
466 }
467
i2c_imx_dma_free(struct imx_i2c_struct * i2c_imx)468 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
469 {
470 struct imx_i2c_dma *dma = i2c_imx->dma;
471
472 dma->dma_buf = 0;
473 dma->dma_len = 0;
474
475 dma_release_channel(dma->chan_tx);
476 dma->chan_tx = NULL;
477
478 dma_release_channel(dma->chan_rx);
479 dma->chan_rx = NULL;
480
481 dma->chan_using = NULL;
482 }
483
i2c_imx_bus_busy(struct imx_i2c_struct * i2c_imx,int for_busy,bool atomic)484 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic)
485 {
486 unsigned long orig_jiffies = jiffies;
487 unsigned int temp;
488
489 while (1) {
490 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
491
492 /* check for arbitration lost */
493 if (temp & I2SR_IAL) {
494 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
495 return -EAGAIN;
496 }
497
498 if (for_busy && (temp & I2SR_IBB)) {
499 i2c_imx->stopped = 0;
500 break;
501 }
502 if (!for_busy && !(temp & I2SR_IBB)) {
503 i2c_imx->stopped = 1;
504 break;
505 }
506 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
507 dev_dbg(&i2c_imx->adapter.dev,
508 "<%s> I2C bus is busy\n", __func__);
509 return -ETIMEDOUT;
510 }
511 if (atomic)
512 udelay(100);
513 else
514 schedule();
515 }
516
517 return 0;
518 }
519
i2c_imx_trx_complete(struct imx_i2c_struct * i2c_imx,bool atomic)520 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic)
521 {
522 if (atomic) {
523 void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift);
524 unsigned int regval;
525
526 /*
527 * The formula for the poll timeout is documented in the RM
528 * Rev.5 on page 1878:
529 * T_min = 10/F_scl
530 * Set the value hard as it is done for the non-atomic use-case.
531 * Use 10 kHz for the calculation since this is the minimum
532 * allowed SMBus frequency. Also add an offset of 100us since it
533 * turned out that the I2SR_IIF bit isn't set correctly within
534 * the minimum timeout in polling mode.
535 */
536 readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100);
537 i2c_imx->i2csr = regval;
538 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL);
539 } else {
540 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
541 }
542
543 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
544 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
545 return -ETIMEDOUT;
546 }
547
548 /* check for arbitration lost */
549 if (i2c_imx->i2csr & I2SR_IAL) {
550 dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__);
551 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
552
553 i2c_imx->i2csr = 0;
554 return -EAGAIN;
555 }
556
557 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
558 i2c_imx->i2csr = 0;
559 return 0;
560 }
561
i2c_imx_acked(struct imx_i2c_struct * i2c_imx)562 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
563 {
564 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
565 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
566 return -ENXIO; /* No ACK */
567 }
568
569 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
570 return 0;
571 }
572
i2c_imx_set_clk(struct imx_i2c_struct * i2c_imx,unsigned int i2c_clk_rate)573 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
574 unsigned int i2c_clk_rate)
575 {
576 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
577 unsigned int div;
578 int i;
579
580 if (i2c_imx->hwdata->has_err007805 && i2c_imx->bitrate > 384000) {
581 dev_dbg(&i2c_imx->adapter.dev,
582 "SoC errata ERR007805 or e7805 applies, bus frequency limited from %d Hz to 384000 Hz.\n",
583 i2c_imx->bitrate);
584 i2c_imx->bitrate = 384000;
585 }
586
587 /* Divider value calculation */
588 if (i2c_imx->cur_clk == i2c_clk_rate)
589 return;
590
591 i2c_imx->cur_clk = i2c_clk_rate;
592
593 div = DIV_ROUND_UP(i2c_clk_rate, i2c_imx->bitrate);
594 if (div < i2c_clk_div[0].div)
595 i = 0;
596 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
597 i = i2c_imx->hwdata->ndivs - 1;
598 else
599 for (i = 0; i2c_clk_div[i].div < div; i++)
600 ;
601
602 /* Store divider value */
603 i2c_imx->ifdr = i2c_clk_div[i].val;
604
605 /*
606 * There dummy delay is calculated.
607 * It should be about one I2C clock period long.
608 * This delay is used in I2C bus disable function
609 * to fix chip hardware bug.
610 */
611 i2c_imx->disable_delay = DIV_ROUND_UP(500000U * i2c_clk_div[i].div,
612 i2c_clk_rate / 2);
613
614 #ifdef CONFIG_I2C_DEBUG_BUS
615 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
616 i2c_clk_rate, div);
617 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
618 i2c_clk_div[i].val, i2c_clk_div[i].div);
619 #endif
620 }
621
i2c_imx_clk_notifier_call(struct notifier_block * nb,unsigned long action,void * data)622 static int i2c_imx_clk_notifier_call(struct notifier_block *nb,
623 unsigned long action, void *data)
624 {
625 struct clk_notifier_data *ndata = data;
626 struct imx_i2c_struct *i2c_imx = container_of(nb,
627 struct imx_i2c_struct,
628 clk_change_nb);
629
630 if (action & POST_RATE_CHANGE)
631 i2c_imx_set_clk(i2c_imx, ndata->new_rate);
632
633 return NOTIFY_OK;
634 }
635
i2c_imx_start(struct imx_i2c_struct * i2c_imx,bool atomic)636 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic)
637 {
638 unsigned int temp = 0;
639 int result;
640
641 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
642 /* Enable I2C controller */
643 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
644 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
645
646 /* Wait controller to be stable */
647 if (atomic)
648 udelay(50);
649 else
650 usleep_range(50, 150);
651
652 /* Start I2C transaction */
653 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
654 temp |= I2CR_MSTA;
655 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
656 result = i2c_imx_bus_busy(i2c_imx, 1, atomic);
657 if (result)
658 return result;
659
660 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
661 if (atomic)
662 temp &= ~I2CR_IIEN; /* Disable interrupt */
663
664 temp &= ~I2CR_DMAEN;
665 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
666 return result;
667 }
668
i2c_imx_stop(struct imx_i2c_struct * i2c_imx,bool atomic)669 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic)
670 {
671 unsigned int temp = 0;
672
673 if (!i2c_imx->stopped) {
674 /* Stop I2C transaction */
675 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
676 if (!(temp & I2CR_MSTA))
677 i2c_imx->stopped = 1;
678 temp &= ~(I2CR_MSTA | I2CR_MTX);
679 if (i2c_imx->dma)
680 temp &= ~I2CR_DMAEN;
681 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
682 }
683 if (is_imx1_i2c(i2c_imx)) {
684 /*
685 * This delay caused by an i.MXL hardware bug.
686 * If no (or too short) delay, no "STOP" bit will be generated.
687 */
688 udelay(i2c_imx->disable_delay);
689 }
690
691 if (!i2c_imx->stopped)
692 i2c_imx_bus_busy(i2c_imx, 0, atomic);
693
694 /* Disable I2C controller */
695 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
696 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
697 }
698
699 /*
700 * Enable bus idle interrupts
701 * Note: IBIC register will be cleared after disabled i2c module.
702 * All of layerscape series SoCs support IBIC register.
703 */
i2c_imx_enable_bus_idle(struct imx_i2c_struct * i2c_imx)704 static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx)
705 {
706 if (is_vf610_i2c(i2c_imx)) {
707 unsigned int temp;
708
709 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC);
710 temp |= IBIC_BIIE;
711 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC);
712 }
713 }
714
i2c_imx_slave_event(struct imx_i2c_struct * i2c_imx,enum i2c_slave_event event,u8 * val)715 static void i2c_imx_slave_event(struct imx_i2c_struct *i2c_imx,
716 enum i2c_slave_event event, u8 *val)
717 {
718 i2c_slave_event(i2c_imx->slave, event, val);
719 i2c_imx->last_slave_event = event;
720 }
721
i2c_imx_slave_finish_op(struct imx_i2c_struct * i2c_imx)722 static void i2c_imx_slave_finish_op(struct imx_i2c_struct *i2c_imx)
723 {
724 u8 val = 0;
725
726 while (i2c_imx->last_slave_event != I2C_SLAVE_STOP) {
727 switch (i2c_imx->last_slave_event) {
728 case I2C_SLAVE_READ_REQUESTED:
729 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_READ_PROCESSED,
730 &val);
731 break;
732
733 case I2C_SLAVE_WRITE_REQUESTED:
734 case I2C_SLAVE_READ_PROCESSED:
735 case I2C_SLAVE_WRITE_RECEIVED:
736 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_STOP, &val);
737 break;
738
739 case I2C_SLAVE_STOP:
740 break;
741 }
742 }
743 }
744
745 /* Returns true if the timer should be restarted, false if not. */
i2c_imx_slave_handle(struct imx_i2c_struct * i2c_imx,unsigned int status,unsigned int ctl)746 static irqreturn_t i2c_imx_slave_handle(struct imx_i2c_struct *i2c_imx,
747 unsigned int status, unsigned int ctl)
748 {
749 u8 value = 0;
750
751 if (status & I2SR_IAL) { /* Arbitration lost */
752 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
753 if (!(status & I2SR_IAAS))
754 return IRQ_HANDLED;
755 }
756
757 if (!(status & I2SR_IBB)) {
758 /* No master on the bus, that could mean a stop condition. */
759 i2c_imx_slave_finish_op(i2c_imx);
760 return IRQ_HANDLED;
761 }
762
763 if (!(status & I2SR_ICF))
764 /* Data transfer still in progress, ignore this. */
765 goto out;
766
767 if (status & I2SR_IAAS) { /* Addressed as a slave */
768 i2c_imx_slave_finish_op(i2c_imx);
769 if (status & I2SR_SRW) { /* Master wants to read from us*/
770 dev_dbg(&i2c_imx->adapter.dev, "read requested");
771 i2c_imx_slave_event(i2c_imx,
772 I2C_SLAVE_READ_REQUESTED, &value);
773
774 /* Slave transmit */
775 ctl |= I2CR_MTX;
776 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
777
778 /* Send data */
779 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
780 } else { /* Master wants to write to us */
781 dev_dbg(&i2c_imx->adapter.dev, "write requested");
782 i2c_imx_slave_event(i2c_imx,
783 I2C_SLAVE_WRITE_REQUESTED, &value);
784
785 /* Slave receive */
786 ctl &= ~I2CR_MTX;
787 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
788 /* Dummy read */
789 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
790 }
791 } else if (!(ctl & I2CR_MTX)) { /* Receive mode */
792 value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
793 i2c_imx_slave_event(i2c_imx,
794 I2C_SLAVE_WRITE_RECEIVED, &value);
795 } else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */
796 ctl |= I2CR_MTX;
797 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
798
799 i2c_imx_slave_event(i2c_imx,
800 I2C_SLAVE_READ_PROCESSED, &value);
801
802 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
803 } else { /* Transmit mode received NAK, operation is done */
804 ctl &= ~I2CR_MTX;
805 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
806 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
807
808 /* flag the last byte as processed */
809 i2c_imx_slave_event(i2c_imx,
810 I2C_SLAVE_READ_PROCESSED, &value);
811
812 i2c_imx_slave_finish_op(i2c_imx);
813 return IRQ_HANDLED;
814 }
815
816 out:
817 /*
818 * No need to check the return value here. If it returns 0 or
819 * 1, then everything is fine. If it returns -1, then the
820 * timer is running in the handler. This will still work,
821 * though it may be redone (or already have been done) by the
822 * timer function.
823 */
824 hrtimer_try_to_cancel(&i2c_imx->slave_timer);
825 hrtimer_forward_now(&i2c_imx->slave_timer, I2C_IMX_CHECK_DELAY);
826 hrtimer_restart(&i2c_imx->slave_timer);
827 return IRQ_HANDLED;
828 }
829
i2c_imx_slave_timeout(struct hrtimer * t)830 static enum hrtimer_restart i2c_imx_slave_timeout(struct hrtimer *t)
831 {
832 struct imx_i2c_struct *i2c_imx = container_of(t, struct imx_i2c_struct,
833 slave_timer);
834 unsigned int ctl, status;
835 unsigned long flags;
836
837 spin_lock_irqsave(&i2c_imx->slave_lock, flags);
838 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
839 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
840 i2c_imx_slave_handle(i2c_imx, status, ctl);
841 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags);
842 return HRTIMER_NORESTART;
843 }
844
i2c_imx_slave_init(struct imx_i2c_struct * i2c_imx)845 static void i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx)
846 {
847 int temp;
848
849 /* Set slave addr. */
850 imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR);
851
852 i2c_imx_reset_regs(i2c_imx);
853
854 /* Enable module */
855 temp = i2c_imx->hwdata->i2cr_ien_opcode;
856 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
857
858 /* Enable interrupt from i2c module */
859 temp |= I2CR_IIEN;
860 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
861
862 i2c_imx_enable_bus_idle(i2c_imx);
863 }
864
i2c_imx_reg_slave(struct i2c_client * client)865 static int i2c_imx_reg_slave(struct i2c_client *client)
866 {
867 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter);
868 int ret;
869
870 if (i2c_imx->slave)
871 return -EBUSY;
872
873 i2c_imx->slave = client;
874 i2c_imx->last_slave_event = I2C_SLAVE_STOP;
875
876 /* Resume */
877 ret = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent);
878 if (ret < 0) {
879 dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller");
880 return ret;
881 }
882
883 i2c_imx_slave_init(i2c_imx);
884
885 return 0;
886 }
887
i2c_imx_unreg_slave(struct i2c_client * client)888 static int i2c_imx_unreg_slave(struct i2c_client *client)
889 {
890 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter);
891 int ret;
892
893 if (!i2c_imx->slave)
894 return -EINVAL;
895
896 /* Reset slave address. */
897 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
898
899 i2c_imx_reset_regs(i2c_imx);
900
901 i2c_imx->slave = NULL;
902
903 /* Suspend */
904 ret = pm_runtime_put_sync(i2c_imx->adapter.dev.parent);
905 if (ret < 0)
906 dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller");
907
908 return ret;
909 }
910
i2c_imx_master_isr(struct imx_i2c_struct * i2c_imx,unsigned int status)911 static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx, unsigned int status)
912 {
913 /* save status register */
914 i2c_imx->i2csr = status;
915 wake_up(&i2c_imx->queue);
916
917 return IRQ_HANDLED;
918 }
919
i2c_imx_isr(int irq,void * dev_id)920 static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
921 {
922 struct imx_i2c_struct *i2c_imx = dev_id;
923 unsigned int ctl, status;
924 unsigned long flags;
925
926 spin_lock_irqsave(&i2c_imx->slave_lock, flags);
927 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
928 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
929
930 if (status & I2SR_IIF) {
931 i2c_imx_clear_irq(i2c_imx, I2SR_IIF);
932 if (i2c_imx->slave) {
933 if (!(ctl & I2CR_MSTA)) {
934 irqreturn_t ret;
935
936 ret = i2c_imx_slave_handle(i2c_imx,
937 status, ctl);
938 spin_unlock_irqrestore(&i2c_imx->slave_lock,
939 flags);
940 return ret;
941 }
942 i2c_imx_slave_finish_op(i2c_imx);
943 }
944 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags);
945 return i2c_imx_master_isr(i2c_imx, status);
946 }
947 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags);
948
949 return IRQ_NONE;
950 }
951
i2c_imx_dma_write(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs)952 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
953 struct i2c_msg *msgs)
954 {
955 int result;
956 unsigned long time_left;
957 unsigned int temp = 0;
958 unsigned long orig_jiffies = jiffies;
959 struct imx_i2c_dma *dma = i2c_imx->dma;
960 struct device *dev = &i2c_imx->adapter.dev;
961
962 dma->chan_using = dma->chan_tx;
963 dma->dma_transfer_dir = DMA_MEM_TO_DEV;
964 dma->dma_data_dir = DMA_TO_DEVICE;
965 dma->dma_len = msgs->len - 1;
966 result = i2c_imx_dma_xfer(i2c_imx, msgs);
967 if (result)
968 return result;
969
970 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
971 temp |= I2CR_DMAEN;
972 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
973
974 /*
975 * Write slave address.
976 * The first byte must be transmitted by the CPU.
977 */
978 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
979 time_left = wait_for_completion_timeout(
980 &i2c_imx->dma->cmd_complete,
981 msecs_to_jiffies(DMA_TIMEOUT));
982 if (time_left == 0) {
983 dmaengine_terminate_sync(dma->chan_using);
984 return -ETIMEDOUT;
985 }
986
987 /* Waiting for transfer complete. */
988 while (1) {
989 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
990 if (temp & I2SR_ICF)
991 break;
992 if (time_after(jiffies, orig_jiffies +
993 msecs_to_jiffies(DMA_TIMEOUT))) {
994 dev_dbg(dev, "<%s> Timeout\n", __func__);
995 return -ETIMEDOUT;
996 }
997 schedule();
998 }
999
1000 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1001 temp &= ~I2CR_DMAEN;
1002 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1003
1004 /* The last data byte must be transferred by the CPU. */
1005 imx_i2c_write_reg(msgs->buf[msgs->len-1],
1006 i2c_imx, IMX_I2C_I2DR);
1007 result = i2c_imx_trx_complete(i2c_imx, false);
1008 if (result)
1009 return result;
1010
1011 return i2c_imx_acked(i2c_imx);
1012 }
1013
i2c_imx_dma_read(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs,bool is_lastmsg)1014 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
1015 struct i2c_msg *msgs, bool is_lastmsg)
1016 {
1017 int result;
1018 unsigned long time_left;
1019 unsigned int temp;
1020 unsigned long orig_jiffies = jiffies;
1021 struct imx_i2c_dma *dma = i2c_imx->dma;
1022 struct device *dev = &i2c_imx->adapter.dev;
1023
1024
1025 dma->chan_using = dma->chan_rx;
1026 dma->dma_transfer_dir = DMA_DEV_TO_MEM;
1027 dma->dma_data_dir = DMA_FROM_DEVICE;
1028 /* The last two data bytes must be transferred by the CPU. */
1029 dma->dma_len = msgs->len - 2;
1030 result = i2c_imx_dma_xfer(i2c_imx, msgs);
1031 if (result)
1032 return result;
1033
1034 time_left = wait_for_completion_timeout(
1035 &i2c_imx->dma->cmd_complete,
1036 msecs_to_jiffies(DMA_TIMEOUT));
1037 if (time_left == 0) {
1038 dmaengine_terminate_sync(dma->chan_using);
1039 return -ETIMEDOUT;
1040 }
1041
1042 /* waiting for transfer complete. */
1043 while (1) {
1044 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
1045 if (temp & I2SR_ICF)
1046 break;
1047 if (time_after(jiffies, orig_jiffies +
1048 msecs_to_jiffies(DMA_TIMEOUT))) {
1049 dev_dbg(dev, "<%s> Timeout\n", __func__);
1050 return -ETIMEDOUT;
1051 }
1052 schedule();
1053 }
1054
1055 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1056 temp &= ~I2CR_DMAEN;
1057 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1058
1059 /* read n-1 byte data */
1060 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1061 temp |= I2CR_TXAK;
1062 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1063
1064 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1065 /* read n byte data */
1066 result = i2c_imx_trx_complete(i2c_imx, false);
1067 if (result)
1068 return result;
1069
1070 if (is_lastmsg) {
1071 /*
1072 * It must generate STOP before read I2DR to prevent
1073 * controller from generating another clock cycle
1074 */
1075 dev_dbg(dev, "<%s> clear MSTA\n", __func__);
1076 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1077 if (!(temp & I2CR_MSTA))
1078 i2c_imx->stopped = 1;
1079 temp &= ~(I2CR_MSTA | I2CR_MTX);
1080 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1081 if (!i2c_imx->stopped)
1082 i2c_imx_bus_busy(i2c_imx, 0, false);
1083 } else {
1084 /*
1085 * For i2c master receiver repeat restart operation like:
1086 * read -> repeat MSTA -> read/write
1087 * The controller must set MTX before read the last byte in
1088 * the first read operation, otherwise the first read cost
1089 * one extra clock cycle.
1090 */
1091 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1092 temp |= I2CR_MTX;
1093 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1094 }
1095 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1096
1097 return 0;
1098 }
1099
i2c_imx_write(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs,bool atomic)1100 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
1101 bool atomic)
1102 {
1103 int i, result;
1104
1105 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
1106 __func__, i2c_8bit_addr_from_msg(msgs));
1107
1108 /* write slave address */
1109 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
1110 result = i2c_imx_trx_complete(i2c_imx, atomic);
1111 if (result)
1112 return result;
1113 result = i2c_imx_acked(i2c_imx);
1114 if (result)
1115 return result;
1116 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
1117
1118 /* write data */
1119 for (i = 0; i < msgs->len; i++) {
1120 dev_dbg(&i2c_imx->adapter.dev,
1121 "<%s> write byte: B%d=0x%X\n",
1122 __func__, i, msgs->buf[i]);
1123 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
1124 result = i2c_imx_trx_complete(i2c_imx, atomic);
1125 if (result)
1126 return result;
1127 result = i2c_imx_acked(i2c_imx);
1128 if (result)
1129 return result;
1130 }
1131 return 0;
1132 }
1133
i2c_imx_read(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs,bool is_lastmsg,bool atomic)1134 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
1135 bool is_lastmsg, bool atomic)
1136 {
1137 int i, result;
1138 unsigned int temp;
1139 int block_data = msgs->flags & I2C_M_RECV_LEN;
1140 int use_dma = i2c_imx->dma && msgs->flags & I2C_M_DMA_SAFE &&
1141 msgs->len >= DMA_THRESHOLD && !block_data;
1142
1143 dev_dbg(&i2c_imx->adapter.dev,
1144 "<%s> write slave address: addr=0x%x\n",
1145 __func__, i2c_8bit_addr_from_msg(msgs));
1146
1147 /* write slave address */
1148 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
1149 result = i2c_imx_trx_complete(i2c_imx, atomic);
1150 if (result)
1151 return result;
1152 result = i2c_imx_acked(i2c_imx);
1153 if (result)
1154 return result;
1155
1156 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
1157
1158 /* setup bus to read data */
1159 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1160 temp &= ~I2CR_MTX;
1161
1162 /*
1163 * Reset the I2CR_TXAK flag initially for SMBus block read since the
1164 * length is unknown
1165 */
1166 if ((msgs->len - 1) || block_data)
1167 temp &= ~I2CR_TXAK;
1168 if (use_dma)
1169 temp |= I2CR_DMAEN;
1170 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1171 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
1172
1173 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
1174
1175 if (use_dma)
1176 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg);
1177
1178 /* read data */
1179 for (i = 0; i < msgs->len; i++) {
1180 u8 len = 0;
1181
1182 result = i2c_imx_trx_complete(i2c_imx, atomic);
1183 if (result)
1184 return result;
1185 /*
1186 * First byte is the length of remaining packet
1187 * in the SMBus block data read. Add it to
1188 * msgs->len.
1189 */
1190 if ((!i) && block_data) {
1191 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1192 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))
1193 return -EPROTO;
1194 dev_dbg(&i2c_imx->adapter.dev,
1195 "<%s> read length: 0x%X\n",
1196 __func__, len);
1197 msgs->len += len;
1198 }
1199 if (i == (msgs->len - 1)) {
1200 if (is_lastmsg) {
1201 /*
1202 * It must generate STOP before read I2DR to prevent
1203 * controller from generating another clock cycle
1204 */
1205 dev_dbg(&i2c_imx->adapter.dev,
1206 "<%s> clear MSTA\n", __func__);
1207 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1208 if (!(temp & I2CR_MSTA))
1209 i2c_imx->stopped = 1;
1210 temp &= ~(I2CR_MSTA | I2CR_MTX);
1211 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1212 if (!i2c_imx->stopped)
1213 i2c_imx_bus_busy(i2c_imx, 0, atomic);
1214 } else {
1215 /*
1216 * For i2c master receiver repeat restart operation like:
1217 * read -> repeat MSTA -> read/write
1218 * The controller must set MTX before read the last byte in
1219 * the first read operation, otherwise the first read cost
1220 * one extra clock cycle.
1221 */
1222 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1223 temp |= I2CR_MTX;
1224 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1225 }
1226 } else if (i == (msgs->len - 2)) {
1227 dev_dbg(&i2c_imx->adapter.dev,
1228 "<%s> set TXAK\n", __func__);
1229 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1230 temp |= I2CR_TXAK;
1231 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1232 }
1233 if ((!i) && block_data)
1234 msgs->buf[0] = len;
1235 else
1236 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1237 dev_dbg(&i2c_imx->adapter.dev,
1238 "<%s> read byte: B%d=0x%X\n",
1239 __func__, i, msgs->buf[i]);
1240 }
1241 return 0;
1242 }
1243
i2c_imx_xfer_common(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num,bool atomic)1244 static int i2c_imx_xfer_common(struct i2c_adapter *adapter,
1245 struct i2c_msg *msgs, int num, bool atomic)
1246 {
1247 unsigned int i, temp;
1248 int result;
1249 bool is_lastmsg = false;
1250 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
1251
1252 /* Start I2C transfer */
1253 result = i2c_imx_start(i2c_imx, atomic);
1254 if (result) {
1255 /*
1256 * Bus recovery uses gpiod_get_value_cansleep() which is not
1257 * allowed within atomic context.
1258 */
1259 if (!atomic && i2c_imx->adapter.bus_recovery_info) {
1260 i2c_recover_bus(&i2c_imx->adapter);
1261 result = i2c_imx_start(i2c_imx, atomic);
1262 }
1263 }
1264
1265 if (result)
1266 goto fail0;
1267
1268 /* read/write data */
1269 for (i = 0; i < num; i++) {
1270 if (i == num - 1)
1271 is_lastmsg = true;
1272
1273 if (i) {
1274 dev_dbg(&i2c_imx->adapter.dev,
1275 "<%s> repeated start\n", __func__);
1276 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1277 temp |= I2CR_RSTA;
1278 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1279 result = i2c_imx_bus_busy(i2c_imx, 1, atomic);
1280 if (result)
1281 goto fail0;
1282 }
1283 dev_dbg(&i2c_imx->adapter.dev,
1284 "<%s> transfer message: %d\n", __func__, i);
1285 /* write/read data */
1286 #ifdef CONFIG_I2C_DEBUG_BUS
1287 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1288 dev_dbg(&i2c_imx->adapter.dev,
1289 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n",
1290 __func__,
1291 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
1292 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
1293 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
1294 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
1295 dev_dbg(&i2c_imx->adapter.dev,
1296 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n",
1297 __func__,
1298 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
1299 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
1300 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
1301 (temp & I2SR_RXAK ? 1 : 0));
1302 #endif
1303 if (msgs[i].flags & I2C_M_RD) {
1304 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg, atomic);
1305 } else {
1306 if (!atomic &&
1307 i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD &&
1308 msgs[i].flags & I2C_M_DMA_SAFE)
1309 result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
1310 else
1311 result = i2c_imx_write(i2c_imx, &msgs[i], atomic);
1312 }
1313 if (result)
1314 goto fail0;
1315 }
1316
1317 fail0:
1318 /* Stop I2C transfer */
1319 i2c_imx_stop(i2c_imx, atomic);
1320
1321 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
1322 (result < 0) ? "error" : "success msg",
1323 (result < 0) ? result : num);
1324 /* After data is transferred, switch to slave mode(as a receiver) */
1325 if (i2c_imx->slave)
1326 i2c_imx_slave_init(i2c_imx);
1327
1328 return (result < 0) ? result : num;
1329 }
1330
i2c_imx_xfer(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)1331 static int i2c_imx_xfer(struct i2c_adapter *adapter,
1332 struct i2c_msg *msgs, int num)
1333 {
1334 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
1335 int result;
1336
1337 result = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent);
1338 if (result < 0)
1339 return result;
1340
1341 result = i2c_imx_xfer_common(adapter, msgs, num, false);
1342
1343 pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent);
1344 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent);
1345
1346 return result;
1347 }
1348
i2c_imx_xfer_atomic(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)1349 static int i2c_imx_xfer_atomic(struct i2c_adapter *adapter,
1350 struct i2c_msg *msgs, int num)
1351 {
1352 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
1353 int result;
1354
1355 result = clk_enable(i2c_imx->clk);
1356 if (result)
1357 return result;
1358
1359 result = i2c_imx_xfer_common(adapter, msgs, num, true);
1360
1361 clk_disable(i2c_imx->clk);
1362
1363 return result;
1364 }
1365
i2c_imx_prepare_recovery(struct i2c_adapter * adap)1366 static void i2c_imx_prepare_recovery(struct i2c_adapter *adap)
1367 {
1368 struct imx_i2c_struct *i2c_imx;
1369
1370 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
1371
1372 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio);
1373 }
1374
i2c_imx_unprepare_recovery(struct i2c_adapter * adap)1375 static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap)
1376 {
1377 struct imx_i2c_struct *i2c_imx;
1378
1379 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
1380
1381 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default);
1382 }
1383
1384 /*
1385 * We switch SCL and SDA to their GPIO function and do some bitbanging
1386 * for bus recovery. These alternative pinmux settings can be
1387 * described in the device tree by a separate pinctrl state "gpio". If
1388 * this is missing this is not a big problem, the only implication is
1389 * that we can't do bus recovery.
1390 */
i2c_imx_init_recovery_info(struct imx_i2c_struct * i2c_imx,struct platform_device * pdev)1391 static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx,
1392 struct platform_device *pdev)
1393 {
1394 struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo;
1395
1396 i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
1397 if (!i2c_imx->pinctrl) {
1398 dev_info(&pdev->dev, "pinctrl unavailable, bus recovery not supported\n");
1399 return 0;
1400 }
1401 if (IS_ERR(i2c_imx->pinctrl)) {
1402 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n");
1403 return PTR_ERR(i2c_imx->pinctrl);
1404 }
1405
1406 i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl,
1407 PINCTRL_STATE_DEFAULT);
1408 i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl,
1409 "gpio");
1410 rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN);
1411 rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN);
1412
1413 if (PTR_ERR(rinfo->sda_gpiod) == -EPROBE_DEFER ||
1414 PTR_ERR(rinfo->scl_gpiod) == -EPROBE_DEFER) {
1415 return -EPROBE_DEFER;
1416 } else if (IS_ERR(rinfo->sda_gpiod) ||
1417 IS_ERR(rinfo->scl_gpiod) ||
1418 IS_ERR(i2c_imx->pinctrl_pins_default) ||
1419 IS_ERR(i2c_imx->pinctrl_pins_gpio)) {
1420 dev_dbg(&pdev->dev, "recovery information incomplete\n");
1421 return 0;
1422 }
1423
1424 dev_dbg(&pdev->dev, "using scl%s for recovery\n",
1425 rinfo->sda_gpiod ? ",sda" : "");
1426
1427 rinfo->prepare_recovery = i2c_imx_prepare_recovery;
1428 rinfo->unprepare_recovery = i2c_imx_unprepare_recovery;
1429 rinfo->recover_bus = i2c_generic_scl_recovery;
1430 i2c_imx->adapter.bus_recovery_info = rinfo;
1431
1432 return 0;
1433 }
1434
i2c_imx_func(struct i2c_adapter * adapter)1435 static u32 i2c_imx_func(struct i2c_adapter *adapter)
1436 {
1437 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
1438 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
1439 }
1440
1441 static const struct i2c_algorithm i2c_imx_algo = {
1442 .master_xfer = i2c_imx_xfer,
1443 .master_xfer_atomic = i2c_imx_xfer_atomic,
1444 .functionality = i2c_imx_func,
1445 .reg_slave = i2c_imx_reg_slave,
1446 .unreg_slave = i2c_imx_unreg_slave,
1447 };
1448
i2c_imx_probe(struct platform_device * pdev)1449 static int i2c_imx_probe(struct platform_device *pdev)
1450 {
1451 struct imx_i2c_struct *i2c_imx;
1452 struct resource *res;
1453 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
1454 void __iomem *base;
1455 int irq, ret;
1456 dma_addr_t phy_addr;
1457 const struct imx_i2c_hwdata *match;
1458
1459 irq = platform_get_irq(pdev, 0);
1460 if (irq < 0)
1461 return irq;
1462
1463 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1464 if (IS_ERR(base))
1465 return PTR_ERR(base);
1466
1467 phy_addr = (dma_addr_t)res->start;
1468 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
1469 if (!i2c_imx)
1470 return -ENOMEM;
1471
1472 spin_lock_init(&i2c_imx->slave_lock);
1473 hrtimer_init(&i2c_imx->slave_timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
1474 i2c_imx->slave_timer.function = i2c_imx_slave_timeout;
1475
1476 match = device_get_match_data(&pdev->dev);
1477 if (match)
1478 i2c_imx->hwdata = match;
1479 else
1480 i2c_imx->hwdata = (struct imx_i2c_hwdata *)
1481 platform_get_device_id(pdev)->driver_data;
1482
1483 /* Setup i2c_imx driver structure */
1484 strscpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
1485 i2c_imx->adapter.owner = THIS_MODULE;
1486 i2c_imx->adapter.algo = &i2c_imx_algo;
1487 i2c_imx->adapter.dev.parent = &pdev->dev;
1488 i2c_imx->adapter.nr = pdev->id;
1489 i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
1490 i2c_imx->base = base;
1491 ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev));
1492
1493 /* Get I2C clock */
1494 i2c_imx->clk = devm_clk_get_enabled(&pdev->dev, NULL);
1495 if (IS_ERR(i2c_imx->clk))
1496 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_imx->clk),
1497 "can't get I2C clock\n");
1498
1499 /* Init queue */
1500 init_waitqueue_head(&i2c_imx->queue);
1501
1502 /* Set up adapter data */
1503 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
1504
1505 /* Set up platform driver data */
1506 platform_set_drvdata(pdev, i2c_imx);
1507
1508 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT);
1509 pm_runtime_use_autosuspend(&pdev->dev);
1510 pm_runtime_set_active(&pdev->dev);
1511 pm_runtime_enable(&pdev->dev);
1512
1513 ret = pm_runtime_get_sync(&pdev->dev);
1514 if (ret < 0)
1515 goto rpm_disable;
1516
1517 /* Request IRQ */
1518 ret = request_irq(irq, i2c_imx_isr, IRQF_SHARED, pdev->name, i2c_imx);
1519 if (ret) {
1520 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
1521 goto rpm_disable;
1522 }
1523
1524 /* Set up clock divider */
1525 i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ;
1526 ret = of_property_read_u32(pdev->dev.of_node,
1527 "clock-frequency", &i2c_imx->bitrate);
1528 if (ret < 0 && pdata && pdata->bitrate)
1529 i2c_imx->bitrate = pdata->bitrate;
1530 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call;
1531 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb);
1532 i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk));
1533
1534 i2c_imx_reset_regs(i2c_imx);
1535
1536 /* Init optional bus recovery function */
1537 ret = i2c_imx_init_recovery_info(i2c_imx, pdev);
1538 /* Give it another chance if pinctrl used is not ready yet */
1539 if (ret == -EPROBE_DEFER)
1540 goto clk_notifier_unregister;
1541
1542 /* Add I2C adapter */
1543 ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
1544 if (ret < 0)
1545 goto clk_notifier_unregister;
1546
1547 pm_runtime_mark_last_busy(&pdev->dev);
1548 pm_runtime_put_autosuspend(&pdev->dev);
1549
1550 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
1551 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
1552 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
1553 i2c_imx->adapter.name);
1554 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
1555
1556 /* Init DMA config if supported */
1557 i2c_imx_dma_request(i2c_imx, phy_addr);
1558
1559 return 0; /* Return OK */
1560
1561 clk_notifier_unregister:
1562 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1563 free_irq(irq, i2c_imx);
1564 rpm_disable:
1565 pm_runtime_put_noidle(&pdev->dev);
1566 pm_runtime_disable(&pdev->dev);
1567 pm_runtime_set_suspended(&pdev->dev);
1568 pm_runtime_dont_use_autosuspend(&pdev->dev);
1569 return ret;
1570 }
1571
i2c_imx_remove(struct platform_device * pdev)1572 static void i2c_imx_remove(struct platform_device *pdev)
1573 {
1574 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
1575 int irq, ret;
1576
1577 ret = pm_runtime_get_sync(&pdev->dev);
1578
1579 hrtimer_cancel(&i2c_imx->slave_timer);
1580
1581 /* remove adapter */
1582 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
1583 i2c_del_adapter(&i2c_imx->adapter);
1584
1585 if (i2c_imx->dma)
1586 i2c_imx_dma_free(i2c_imx);
1587
1588 if (ret >= 0) {
1589 /* setup chip registers to defaults */
1590 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
1591 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
1592 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
1593 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
1594 }
1595
1596 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1597 irq = platform_get_irq(pdev, 0);
1598 if (irq >= 0)
1599 free_irq(irq, i2c_imx);
1600
1601 pm_runtime_put_noidle(&pdev->dev);
1602 pm_runtime_disable(&pdev->dev);
1603 }
1604
i2c_imx_runtime_suspend(struct device * dev)1605 static int __maybe_unused i2c_imx_runtime_suspend(struct device *dev)
1606 {
1607 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1608
1609 clk_disable(i2c_imx->clk);
1610
1611 return 0;
1612 }
1613
i2c_imx_runtime_resume(struct device * dev)1614 static int __maybe_unused i2c_imx_runtime_resume(struct device *dev)
1615 {
1616 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1617 int ret;
1618
1619 ret = clk_enable(i2c_imx->clk);
1620 if (ret)
1621 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret);
1622
1623 return ret;
1624 }
1625
1626 static const struct dev_pm_ops i2c_imx_pm_ops = {
1627 SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend,
1628 i2c_imx_runtime_resume, NULL)
1629 };
1630
1631 static struct platform_driver i2c_imx_driver = {
1632 .probe = i2c_imx_probe,
1633 .remove_new = i2c_imx_remove,
1634 .driver = {
1635 .name = DRIVER_NAME,
1636 .pm = &i2c_imx_pm_ops,
1637 .of_match_table = i2c_imx_dt_ids,
1638 .acpi_match_table = i2c_imx_acpi_ids,
1639 },
1640 .id_table = imx_i2c_devtype,
1641 };
1642
i2c_adap_imx_init(void)1643 static int __init i2c_adap_imx_init(void)
1644 {
1645 return platform_driver_register(&i2c_imx_driver);
1646 }
1647 subsys_initcall(i2c_adap_imx_init);
1648
i2c_adap_imx_exit(void)1649 static void __exit i2c_adap_imx_exit(void)
1650 {
1651 platform_driver_unregister(&i2c_imx_driver);
1652 }
1653 module_exit(i2c_adap_imx_exit);
1654
1655 MODULE_LICENSE("GPL");
1656 MODULE_AUTHOR("Darius Augulis");
1657 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
1658 MODULE_ALIAS("platform:" DRIVER_NAME);
1659