1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 // Copyright 2018 NXP
3
4 #include <linux/bitfield.h>
5 #include <linux/clk.h>
6 #include <linux/device.h>
7 #include <linux/interrupt.h>
8 #include <linux/kobject.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13 #include <linux/of_irq.h>
14 #include <linux/of_platform.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/sysfs.h>
18 #include <linux/types.h>
19 #include <linux/dma/imx-dma.h>
20 #include <sound/dmaengine_pcm.h>
21 #include <sound/pcm.h>
22 #include <sound/soc.h>
23 #include <sound/tlv.h>
24 #include <sound/core.h>
25
26 #include "fsl_micfil.h"
27 #include "fsl_utils.h"
28
29 #define MICFIL_OSR_DEFAULT 16
30
31 #define MICFIL_NUM_RATES 7
32 #define MICFIL_CLK_SRC_NUM 3
33 /* clock source ids */
34 #define MICFIL_AUDIO_PLL1 0
35 #define MICFIL_AUDIO_PLL2 1
36 #define MICFIL_CLK_EXT3 2
37
38 enum quality {
39 QUALITY_HIGH,
40 QUALITY_MEDIUM,
41 QUALITY_LOW,
42 QUALITY_VLOW0,
43 QUALITY_VLOW1,
44 QUALITY_VLOW2,
45 };
46
47 struct fsl_micfil {
48 struct platform_device *pdev;
49 struct regmap *regmap;
50 const struct fsl_micfil_soc_data *soc;
51 struct clk *busclk;
52 struct clk *mclk;
53 struct clk *pll8k_clk;
54 struct clk *pll11k_clk;
55 struct clk *clk_src[MICFIL_CLK_SRC_NUM];
56 struct snd_dmaengine_dai_dma_data dma_params_rx;
57 struct sdma_peripheral_config sdmacfg;
58 struct snd_soc_card *card;
59 struct snd_pcm_hw_constraint_list constraint_rates;
60 unsigned int constraint_rates_list[MICFIL_NUM_RATES];
61 unsigned int dataline;
62 char name[32];
63 int irq[MICFIL_IRQ_LINES];
64 enum quality quality;
65 int dc_remover;
66 int vad_init_mode;
67 int vad_enabled;
68 int vad_detected;
69 struct fsl_micfil_verid verid;
70 struct fsl_micfil_param param;
71 };
72
73 struct fsl_micfil_soc_data {
74 unsigned int fifos;
75 unsigned int fifo_depth;
76 unsigned int dataline;
77 bool imx;
78 bool use_edma;
79 bool use_verid;
80 bool volume_sx;
81 u64 formats;
82 };
83
84 static struct fsl_micfil_soc_data fsl_micfil_imx8mm = {
85 .imx = true,
86 .fifos = 8,
87 .fifo_depth = 8,
88 .dataline = 0xf,
89 .formats = SNDRV_PCM_FMTBIT_S16_LE,
90 .volume_sx = true,
91 };
92
93 static struct fsl_micfil_soc_data fsl_micfil_imx8mp = {
94 .imx = true,
95 .fifos = 8,
96 .fifo_depth = 32,
97 .dataline = 0xf,
98 .formats = SNDRV_PCM_FMTBIT_S32_LE,
99 .volume_sx = false,
100 };
101
102 static struct fsl_micfil_soc_data fsl_micfil_imx93 = {
103 .imx = true,
104 .fifos = 8,
105 .fifo_depth = 32,
106 .dataline = 0xf,
107 .formats = SNDRV_PCM_FMTBIT_S32_LE,
108 .use_edma = true,
109 .use_verid = true,
110 .volume_sx = false,
111 };
112
113 static const struct of_device_id fsl_micfil_dt_ids[] = {
114 { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },
115 { .compatible = "fsl,imx8mp-micfil", .data = &fsl_micfil_imx8mp },
116 { .compatible = "fsl,imx93-micfil", .data = &fsl_micfil_imx93 },
117 {}
118 };
119 MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
120
121 static const char * const micfil_quality_select_texts[] = {
122 [QUALITY_HIGH] = "High",
123 [QUALITY_MEDIUM] = "Medium",
124 [QUALITY_LOW] = "Low",
125 [QUALITY_VLOW0] = "VLow0",
126 [QUALITY_VLOW1] = "Vlow1",
127 [QUALITY_VLOW2] = "Vlow2",
128 };
129
130 static const struct soc_enum fsl_micfil_quality_enum =
131 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_quality_select_texts),
132 micfil_quality_select_texts);
133
134 static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0);
135
micfil_set_quality(struct fsl_micfil * micfil)136 static int micfil_set_quality(struct fsl_micfil *micfil)
137 {
138 u32 qsel;
139
140 switch (micfil->quality) {
141 case QUALITY_HIGH:
142 qsel = MICFIL_QSEL_HIGH_QUALITY;
143 break;
144 case QUALITY_MEDIUM:
145 qsel = MICFIL_QSEL_MEDIUM_QUALITY;
146 break;
147 case QUALITY_LOW:
148 qsel = MICFIL_QSEL_LOW_QUALITY;
149 break;
150 case QUALITY_VLOW0:
151 qsel = MICFIL_QSEL_VLOW0_QUALITY;
152 break;
153 case QUALITY_VLOW1:
154 qsel = MICFIL_QSEL_VLOW1_QUALITY;
155 break;
156 case QUALITY_VLOW2:
157 qsel = MICFIL_QSEL_VLOW2_QUALITY;
158 break;
159 default:
160 return -EINVAL;
161 }
162
163 return regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
164 MICFIL_CTRL2_QSEL,
165 FIELD_PREP(MICFIL_CTRL2_QSEL, qsel));
166 }
167
micfil_quality_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)168 static int micfil_quality_get(struct snd_kcontrol *kcontrol,
169 struct snd_ctl_elem_value *ucontrol)
170 {
171 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
172 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
173
174 ucontrol->value.integer.value[0] = micfil->quality;
175
176 return 0;
177 }
178
micfil_quality_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)179 static int micfil_quality_set(struct snd_kcontrol *kcontrol,
180 struct snd_ctl_elem_value *ucontrol)
181 {
182 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
183 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
184
185 micfil->quality = ucontrol->value.integer.value[0];
186
187 return micfil_set_quality(micfil);
188 }
189
190 static const char * const micfil_hwvad_enable[] = {
191 "Disable (Record only)",
192 "Enable (Record with Vad)",
193 };
194
195 static const char * const micfil_hwvad_init_mode[] = {
196 "Envelope mode", "Energy mode",
197 };
198
199 static const char * const micfil_hwvad_hpf_texts[] = {
200 "Filter bypass",
201 "Cut-off @1750Hz",
202 "Cut-off @215Hz",
203 "Cut-off @102Hz",
204 };
205
206 /*
207 * DC Remover Control
208 * Filter Bypassed 1 1
209 * Cut-off @21Hz 0 0
210 * Cut-off @83Hz 0 1
211 * Cut-off @152HZ 1 0
212 */
213 static const char * const micfil_dc_remover_texts[] = {
214 "Cut-off @21Hz", "Cut-off @83Hz",
215 "Cut-off @152Hz", "Bypass",
216 };
217
218 static const struct soc_enum hwvad_enable_enum =
219 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_enable),
220 micfil_hwvad_enable);
221 static const struct soc_enum hwvad_init_mode_enum =
222 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_init_mode),
223 micfil_hwvad_init_mode);
224 static const struct soc_enum hwvad_hpf_enum =
225 SOC_ENUM_SINGLE(REG_MICFIL_VAD0_CTRL2, 0,
226 ARRAY_SIZE(micfil_hwvad_hpf_texts),
227 micfil_hwvad_hpf_texts);
228 static const struct soc_enum fsl_micfil_dc_remover_enum =
229 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_dc_remover_texts),
230 micfil_dc_remover_texts);
231
micfil_put_dc_remover_state(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)232 static int micfil_put_dc_remover_state(struct snd_kcontrol *kcontrol,
233 struct snd_ctl_elem_value *ucontrol)
234 {
235 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
236 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
237 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
238 unsigned int *item = ucontrol->value.enumerated.item;
239 int val = snd_soc_enum_item_to_val(e, item[0]);
240 int i = 0, ret = 0;
241 u32 reg_val = 0;
242
243 if (val < 0 || val > 3)
244 return -EINVAL;
245
246 micfil->dc_remover = val;
247
248 /* Calculate total value for all channels */
249 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
250 reg_val |= val << MICFIL_DC_CHX_SHIFT(i);
251
252 /* Update DC Remover mode for all channels */
253 ret = snd_soc_component_update_bits(comp, REG_MICFIL_DC_CTRL,
254 MICFIL_DC_CTRL_CONFIG, reg_val);
255 if (ret < 0)
256 return ret;
257
258 return 0;
259 }
260
micfil_get_dc_remover_state(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)261 static int micfil_get_dc_remover_state(struct snd_kcontrol *kcontrol,
262 struct snd_ctl_elem_value *ucontrol)
263 {
264 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
265 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
266
267 ucontrol->value.enumerated.item[0] = micfil->dc_remover;
268
269 return 0;
270 }
271
hwvad_put_enable(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)272 static int hwvad_put_enable(struct snd_kcontrol *kcontrol,
273 struct snd_ctl_elem_value *ucontrol)
274 {
275 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
276 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
277 unsigned int *item = ucontrol->value.enumerated.item;
278 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
279 int val = snd_soc_enum_item_to_val(e, item[0]);
280
281 micfil->vad_enabled = val;
282
283 return 0;
284 }
285
hwvad_get_enable(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)286 static int hwvad_get_enable(struct snd_kcontrol *kcontrol,
287 struct snd_ctl_elem_value *ucontrol)
288 {
289 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
290 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
291
292 ucontrol->value.enumerated.item[0] = micfil->vad_enabled;
293
294 return 0;
295 }
296
hwvad_put_init_mode(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)297 static int hwvad_put_init_mode(struct snd_kcontrol *kcontrol,
298 struct snd_ctl_elem_value *ucontrol)
299 {
300 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
301 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
302 unsigned int *item = ucontrol->value.enumerated.item;
303 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
304 int val = snd_soc_enum_item_to_val(e, item[0]);
305
306 /* 0 - Envelope-based Mode
307 * 1 - Energy-based Mode
308 */
309 micfil->vad_init_mode = val;
310
311 return 0;
312 }
313
hwvad_get_init_mode(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)314 static int hwvad_get_init_mode(struct snd_kcontrol *kcontrol,
315 struct snd_ctl_elem_value *ucontrol)
316 {
317 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
318 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
319
320 ucontrol->value.enumerated.item[0] = micfil->vad_init_mode;
321
322 return 0;
323 }
324
hwvad_detected(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)325 static int hwvad_detected(struct snd_kcontrol *kcontrol,
326 struct snd_ctl_elem_value *ucontrol)
327 {
328 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
329 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
330
331 ucontrol->value.enumerated.item[0] = micfil->vad_detected;
332
333 return 0;
334 }
335
336 static const struct snd_kcontrol_new fsl_micfil_volume_controls[] = {
337 SOC_SINGLE_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
338 MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0, gain_tlv),
339 SOC_SINGLE_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,
340 MICFIL_OUTGAIN_CHX_SHIFT(1), 0xF, 0, gain_tlv),
341 SOC_SINGLE_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,
342 MICFIL_OUTGAIN_CHX_SHIFT(2), 0xF, 0, gain_tlv),
343 SOC_SINGLE_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,
344 MICFIL_OUTGAIN_CHX_SHIFT(3), 0xF, 0, gain_tlv),
345 SOC_SINGLE_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,
346 MICFIL_OUTGAIN_CHX_SHIFT(4), 0xF, 0, gain_tlv),
347 SOC_SINGLE_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,
348 MICFIL_OUTGAIN_CHX_SHIFT(5), 0xF, 0, gain_tlv),
349 SOC_SINGLE_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,
350 MICFIL_OUTGAIN_CHX_SHIFT(6), 0xF, 0, gain_tlv),
351 SOC_SINGLE_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,
352 MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0, gain_tlv),
353 };
354
355 static const struct snd_kcontrol_new fsl_micfil_volume_sx_controls[] = {
356 SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
357 MICFIL_OUTGAIN_CHX_SHIFT(0), 0x8, 0xF, gain_tlv),
358 SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,
359 MICFIL_OUTGAIN_CHX_SHIFT(1), 0x8, 0xF, gain_tlv),
360 SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,
361 MICFIL_OUTGAIN_CHX_SHIFT(2), 0x8, 0xF, gain_tlv),
362 SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,
363 MICFIL_OUTGAIN_CHX_SHIFT(3), 0x8, 0xF, gain_tlv),
364 SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,
365 MICFIL_OUTGAIN_CHX_SHIFT(4), 0x8, 0xF, gain_tlv),
366 SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,
367 MICFIL_OUTGAIN_CHX_SHIFT(5), 0x8, 0xF, gain_tlv),
368 SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,
369 MICFIL_OUTGAIN_CHX_SHIFT(6), 0x8, 0xF, gain_tlv),
370 SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,
371 MICFIL_OUTGAIN_CHX_SHIFT(7), 0x8, 0xF, gain_tlv),
372 };
373
374 static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
375 SOC_ENUM_EXT("MICFIL Quality Select",
376 fsl_micfil_quality_enum,
377 micfil_quality_get, micfil_quality_set),
378 SOC_ENUM_EXT("HWVAD Enablement Switch", hwvad_enable_enum,
379 hwvad_get_enable, hwvad_put_enable),
380 SOC_ENUM_EXT("HWVAD Initialization Mode", hwvad_init_mode_enum,
381 hwvad_get_init_mode, hwvad_put_init_mode),
382 SOC_ENUM("HWVAD High-Pass Filter", hwvad_hpf_enum),
383 SOC_SINGLE("HWVAD ZCD Switch", REG_MICFIL_VAD0_ZCD, 0, 1, 0),
384 SOC_SINGLE("HWVAD ZCD Auto Threshold Switch",
385 REG_MICFIL_VAD0_ZCD, 2, 1, 0),
386 SOC_ENUM_EXT("MICFIL DC Remover Control", fsl_micfil_dc_remover_enum,
387 micfil_get_dc_remover_state, micfil_put_dc_remover_state),
388 SOC_SINGLE("HWVAD Input Gain", REG_MICFIL_VAD0_CTRL2, 8, 15, 0),
389 SOC_SINGLE("HWVAD Sound Gain", REG_MICFIL_VAD0_SCONFIG, 0, 15, 0),
390 SOC_SINGLE("HWVAD Noise Gain", REG_MICFIL_VAD0_NCONFIG, 0, 15, 0),
391 SOC_SINGLE_RANGE("HWVAD Detector Frame Time", REG_MICFIL_VAD0_CTRL2, 16, 0, 63, 0),
392 SOC_SINGLE("HWVAD Detector Initialization Time", REG_MICFIL_VAD0_CTRL1, 8, 31, 0),
393 SOC_SINGLE("HWVAD Noise Filter Adjustment", REG_MICFIL_VAD0_NCONFIG, 8, 31, 0),
394 SOC_SINGLE("HWVAD ZCD Threshold", REG_MICFIL_VAD0_ZCD, 16, 1023, 0),
395 SOC_SINGLE("HWVAD ZCD Adjustment", REG_MICFIL_VAD0_ZCD, 8, 15, 0),
396 SOC_SINGLE("HWVAD ZCD And Behavior Switch",
397 REG_MICFIL_VAD0_ZCD, 4, 1, 0),
398 SOC_SINGLE_BOOL_EXT("VAD Detected", 0, hwvad_detected, NULL),
399 };
400
fsl_micfil_use_verid(struct device * dev)401 static int fsl_micfil_use_verid(struct device *dev)
402 {
403 struct fsl_micfil *micfil = dev_get_drvdata(dev);
404 unsigned int val;
405 int ret;
406
407 if (!micfil->soc->use_verid)
408 return 0;
409
410 ret = regmap_read(micfil->regmap, REG_MICFIL_VERID, &val);
411 if (ret < 0)
412 return ret;
413
414 dev_dbg(dev, "VERID: 0x%016X\n", val);
415
416 micfil->verid.version = val &
417 (MICFIL_VERID_MAJOR_MASK | MICFIL_VERID_MINOR_MASK);
418 micfil->verid.version >>= MICFIL_VERID_MINOR_SHIFT;
419 micfil->verid.feature = val & MICFIL_VERID_FEATURE_MASK;
420
421 ret = regmap_read(micfil->regmap, REG_MICFIL_PARAM, &val);
422 if (ret < 0)
423 return ret;
424
425 dev_dbg(dev, "PARAM: 0x%016X\n", val);
426
427 micfil->param.hwvad_num = (val & MICFIL_PARAM_NUM_HWVAD_MASK) >>
428 MICFIL_PARAM_NUM_HWVAD_SHIFT;
429 micfil->param.hwvad_zcd = val & MICFIL_PARAM_HWVAD_ZCD;
430 micfil->param.hwvad_energy_mode = val & MICFIL_PARAM_HWVAD_ENERGY_MODE;
431 micfil->param.hwvad = val & MICFIL_PARAM_HWVAD;
432 micfil->param.dc_out_bypass = val & MICFIL_PARAM_DC_OUT_BYPASS;
433 micfil->param.dc_in_bypass = val & MICFIL_PARAM_DC_IN_BYPASS;
434 micfil->param.low_power = val & MICFIL_PARAM_LOW_POWER;
435 micfil->param.fil_out_width = val & MICFIL_PARAM_FIL_OUT_WIDTH;
436 micfil->param.fifo_ptrwid = (val & MICFIL_PARAM_FIFO_PTRWID_MASK) >>
437 MICFIL_PARAM_FIFO_PTRWID_SHIFT;
438 micfil->param.npair = (val & MICFIL_PARAM_NPAIR_MASK) >>
439 MICFIL_PARAM_NPAIR_SHIFT;
440
441 return 0;
442 }
443
444 /* The SRES is a self-negated bit which provides the CPU with the
445 * capability to initialize the PDM Interface module through the
446 * slave-bus interface. This bit always reads as zero, and this
447 * bit is only effective when MDIS is cleared
448 */
fsl_micfil_reset(struct device * dev)449 static int fsl_micfil_reset(struct device *dev)
450 {
451 struct fsl_micfil *micfil = dev_get_drvdata(dev);
452 int ret;
453
454 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
455 MICFIL_CTRL1_MDIS);
456 if (ret)
457 return ret;
458
459 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
460 MICFIL_CTRL1_SRES);
461 if (ret)
462 return ret;
463
464 /*
465 * SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined
466 * as non-volatile register, so SRES still remain in regmap
467 * cache after set, that every update of REG_MICFIL_CTRL1,
468 * software reset happens. so clear it explicitly.
469 */
470 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
471 MICFIL_CTRL1_SRES);
472 if (ret)
473 return ret;
474
475 /*
476 * Set SRES should clear CHnF flags, But even add delay here
477 * the CHnF may not be cleared sometimes, so clear CHnF explicitly.
478 */
479 ret = regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 0xFF, 0xFF);
480 if (ret)
481 return ret;
482
483 return 0;
484 }
485
fsl_micfil_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)486 static int fsl_micfil_startup(struct snd_pcm_substream *substream,
487 struct snd_soc_dai *dai)
488 {
489 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
490 unsigned int rates[MICFIL_NUM_RATES] = {8000, 11025, 16000, 22050, 32000, 44100, 48000};
491 int i, j, k = 0;
492 u64 clk_rate;
493
494 if (!micfil) {
495 dev_err(dai->dev, "micfil dai priv_data not set\n");
496 return -EINVAL;
497 }
498
499 micfil->constraint_rates.list = micfil->constraint_rates_list;
500 micfil->constraint_rates.count = 0;
501
502 for (j = 0; j < MICFIL_NUM_RATES; j++) {
503 for (i = 0; i < MICFIL_CLK_SRC_NUM; i++) {
504 clk_rate = clk_get_rate(micfil->clk_src[i]);
505 if (clk_rate != 0 && do_div(clk_rate, rates[j]) == 0) {
506 micfil->constraint_rates_list[k++] = rates[j];
507 micfil->constraint_rates.count++;
508 break;
509 }
510 }
511 }
512
513 if (micfil->constraint_rates.count > 0)
514 snd_pcm_hw_constraint_list(substream->runtime, 0,
515 SNDRV_PCM_HW_PARAM_RATE,
516 &micfil->constraint_rates);
517
518 return 0;
519 }
520
521 /* Enable/disable hwvad interrupts */
fsl_micfil_configure_hwvad_interrupts(struct fsl_micfil * micfil,int enable)522 static int fsl_micfil_configure_hwvad_interrupts(struct fsl_micfil *micfil, int enable)
523 {
524 u32 vadie_reg = enable ? MICFIL_VAD0_CTRL1_IE : 0;
525 u32 vaderie_reg = enable ? MICFIL_VAD0_CTRL1_ERIE : 0;
526
527 /* Voice Activity Detector Error Interruption */
528 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
529 MICFIL_VAD0_CTRL1_ERIE, vaderie_reg);
530
531 /* Voice Activity Detector Interruption */
532 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
533 MICFIL_VAD0_CTRL1_IE, vadie_reg);
534
535 return 0;
536 }
537
538 /* Configuration done only in energy-based initialization mode */
fsl_micfil_init_hwvad_energy_mode(struct fsl_micfil * micfil)539 static int fsl_micfil_init_hwvad_energy_mode(struct fsl_micfil *micfil)
540 {
541 /* Keep the VADFRENDIS bitfield cleared. */
542 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
543 MICFIL_VAD0_CTRL2_FRENDIS);
544
545 /* Keep the VADPREFEN bitfield cleared. */
546 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
547 MICFIL_VAD0_CTRL2_PREFEN);
548
549 /* Keep the VADSFILEN bitfield cleared. */
550 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
551 MICFIL_VAD0_SCONFIG_SFILEN);
552
553 /* Keep the VADSMAXEN bitfield cleared. */
554 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
555 MICFIL_VAD0_SCONFIG_SMAXEN);
556
557 /* Keep the VADNFILAUTO bitfield asserted. */
558 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
559 MICFIL_VAD0_NCONFIG_NFILAUT);
560
561 /* Keep the VADNMINEN bitfield cleared. */
562 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
563 MICFIL_VAD0_NCONFIG_NMINEN);
564
565 /* Keep the VADNDECEN bitfield cleared. */
566 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
567 MICFIL_VAD0_NCONFIG_NDECEN);
568
569 /* Keep the VADNOREN bitfield cleared. */
570 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
571 MICFIL_VAD0_NCONFIG_NOREN);
572
573 return 0;
574 }
575
576 /* Configuration done only in envelope-based initialization mode */
fsl_micfil_init_hwvad_envelope_mode(struct fsl_micfil * micfil)577 static int fsl_micfil_init_hwvad_envelope_mode(struct fsl_micfil *micfil)
578 {
579 /* Assert the VADFRENDIS bitfield */
580 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
581 MICFIL_VAD0_CTRL2_FRENDIS);
582
583 /* Assert the VADPREFEN bitfield. */
584 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
585 MICFIL_VAD0_CTRL2_PREFEN);
586
587 /* Assert the VADSFILEN bitfield. */
588 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
589 MICFIL_VAD0_SCONFIG_SFILEN);
590
591 /* Assert the VADSMAXEN bitfield. */
592 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
593 MICFIL_VAD0_SCONFIG_SMAXEN);
594
595 /* Clear the VADNFILAUTO bitfield */
596 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
597 MICFIL_VAD0_NCONFIG_NFILAUT);
598
599 /* Assert the VADNMINEN bitfield. */
600 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
601 MICFIL_VAD0_NCONFIG_NMINEN);
602
603 /* Assert the VADNDECEN bitfield. */
604 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
605 MICFIL_VAD0_NCONFIG_NDECEN);
606
607 /* Assert VADNOREN bitfield. */
608 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
609 MICFIL_VAD0_NCONFIG_NOREN);
610
611 return 0;
612 }
613
614 /*
615 * Hardware Voice Active Detection: The HWVAD takes data from the input
616 * of a selected PDM microphone to detect if there is any
617 * voice activity. When a voice activity is detected, an interrupt could
618 * be delivered to the system. Initialization in section 8.4:
619 * Can work in two modes:
620 * -> Eneveope-based mode (section 8.4.1)
621 * -> Energy-based mode (section 8.4.2)
622 *
623 * It is important to remark that the HWVAD detector could be enabled
624 * or reset only when the MICFIL isn't running i.e. when the BSY_FIL
625 * bit in STAT register is cleared
626 */
fsl_micfil_hwvad_enable(struct fsl_micfil * micfil)627 static int fsl_micfil_hwvad_enable(struct fsl_micfil *micfil)
628 {
629 int ret;
630
631 micfil->vad_detected = 0;
632
633 /* envelope-based specific initialization */
634 if (micfil->vad_init_mode == MICFIL_HWVAD_ENVELOPE_MODE)
635 ret = fsl_micfil_init_hwvad_envelope_mode(micfil);
636 else
637 ret = fsl_micfil_init_hwvad_energy_mode(micfil);
638 if (ret)
639 return ret;
640
641 /* Voice Activity Detector Internal Filters Initialization*/
642 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
643 MICFIL_VAD0_CTRL1_ST10);
644
645 /* Voice Activity Detector Internal Filter */
646 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
647 MICFIL_VAD0_CTRL1_ST10);
648
649 /* Enable Interrupts */
650 ret = fsl_micfil_configure_hwvad_interrupts(micfil, 1);
651 if (ret)
652 return ret;
653
654 /* Voice Activity Detector Reset */
655 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
656 MICFIL_VAD0_CTRL1_RST);
657
658 /* Voice Activity Detector Enabled */
659 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
660 MICFIL_VAD0_CTRL1_EN);
661
662 return 0;
663 }
664
fsl_micfil_hwvad_disable(struct fsl_micfil * micfil)665 static int fsl_micfil_hwvad_disable(struct fsl_micfil *micfil)
666 {
667 struct device *dev = &micfil->pdev->dev;
668 int ret = 0;
669
670 /* Disable HWVAD */
671 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
672 MICFIL_VAD0_CTRL1_EN);
673
674 /* Disable hwvad interrupts */
675 ret = fsl_micfil_configure_hwvad_interrupts(micfil, 0);
676 if (ret)
677 dev_err(dev, "Failed to disable interrupts\n");
678
679 return ret;
680 }
681
fsl_micfil_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)682 static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
683 struct snd_soc_dai *dai)
684 {
685 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
686 struct device *dev = &micfil->pdev->dev;
687 int ret;
688
689 switch (cmd) {
690 case SNDRV_PCM_TRIGGER_START:
691 case SNDRV_PCM_TRIGGER_RESUME:
692 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
693 ret = fsl_micfil_reset(dev);
694 if (ret) {
695 dev_err(dev, "failed to soft reset\n");
696 return ret;
697 }
698
699 /* DMA Interrupt Selection - DISEL bits
700 * 00 - DMA and IRQ disabled
701 * 01 - DMA req enabled
702 * 10 - IRQ enabled
703 * 11 - reserved
704 */
705 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
706 MICFIL_CTRL1_DISEL,
707 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA));
708 if (ret)
709 return ret;
710
711 /* Enable the module */
712 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
713 MICFIL_CTRL1_PDMIEN);
714 if (ret)
715 return ret;
716
717 if (micfil->vad_enabled)
718 fsl_micfil_hwvad_enable(micfil);
719
720 break;
721 case SNDRV_PCM_TRIGGER_STOP:
722 case SNDRV_PCM_TRIGGER_SUSPEND:
723 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
724 if (micfil->vad_enabled)
725 fsl_micfil_hwvad_disable(micfil);
726
727 /* Disable the module */
728 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
729 MICFIL_CTRL1_PDMIEN);
730 if (ret)
731 return ret;
732
733 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
734 MICFIL_CTRL1_DISEL,
735 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE));
736 if (ret)
737 return ret;
738 break;
739 default:
740 return -EINVAL;
741 }
742 return 0;
743 }
744
fsl_micfil_reparent_rootclk(struct fsl_micfil * micfil,unsigned int sample_rate)745 static int fsl_micfil_reparent_rootclk(struct fsl_micfil *micfil, unsigned int sample_rate)
746 {
747 struct device *dev = &micfil->pdev->dev;
748 u64 ratio = sample_rate;
749 struct clk *clk;
750 int ret;
751
752 /* Get root clock */
753 clk = micfil->mclk;
754
755 /* Disable clock first, for it was enabled by pm_runtime */
756 clk_disable_unprepare(clk);
757 fsl_asoc_reparent_pll_clocks(dev, clk, micfil->pll8k_clk,
758 micfil->pll11k_clk, ratio);
759 ret = clk_prepare_enable(clk);
760 if (ret)
761 return ret;
762
763 return 0;
764 }
765
fsl_micfil_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)766 static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
767 struct snd_pcm_hw_params *params,
768 struct snd_soc_dai *dai)
769 {
770 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
771 unsigned int channels = params_channels(params);
772 unsigned int rate = params_rate(params);
773 int clk_div = 8;
774 int osr = MICFIL_OSR_DEFAULT;
775 int ret;
776
777 /* 1. Disable the module */
778 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
779 MICFIL_CTRL1_PDMIEN);
780 if (ret)
781 return ret;
782
783 /* enable channels */
784 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
785 0xFF, ((1 << channels) - 1));
786 if (ret)
787 return ret;
788
789 ret = fsl_micfil_reparent_rootclk(micfil, rate);
790 if (ret)
791 return ret;
792
793 ret = clk_set_rate(micfil->mclk, rate * clk_div * osr * 8);
794 if (ret)
795 return ret;
796
797 ret = micfil_set_quality(micfil);
798 if (ret)
799 return ret;
800
801 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
802 MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR,
803 FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) |
804 FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - osr));
805
806 /* Configure CIC OSR in VADCICOSR */
807 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
808 MICFIL_VAD0_CTRL1_CICOSR,
809 FIELD_PREP(MICFIL_VAD0_CTRL1_CICOSR, 16 - osr));
810
811 /* Configure source channel in VADCHSEL */
812 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
813 MICFIL_VAD0_CTRL1_CHSEL,
814 FIELD_PREP(MICFIL_VAD0_CTRL1_CHSEL, (channels - 1)));
815
816 micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg;
817 micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg);
818 micfil->sdmacfg.n_fifos_src = channels;
819 micfil->sdmacfg.sw_done = true;
820 micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;
821 if (micfil->soc->use_edma)
822 micfil->dma_params_rx.maxburst = channels;
823
824 return 0;
825 }
826
fsl_micfil_dai_probe(struct snd_soc_dai * cpu_dai)827 static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
828 {
829 struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
830 struct device *dev = cpu_dai->dev;
831 unsigned int val = 0;
832 int ret, i;
833
834 micfil->quality = QUALITY_VLOW0;
835 micfil->card = cpu_dai->component->card;
836
837 /* set default gain to 2 */
838 regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x22222222);
839
840 /* set DC Remover in bypass mode*/
841 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
842 val |= MICFIL_DC_BYPASS << MICFIL_DC_CHX_SHIFT(i);
843 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_DC_CTRL,
844 MICFIL_DC_CTRL_CONFIG, val);
845 if (ret) {
846 dev_err(dev, "failed to set DC Remover mode bits\n");
847 return ret;
848 }
849 micfil->dc_remover = MICFIL_DC_BYPASS;
850
851 snd_soc_dai_init_dma_data(cpu_dai, NULL,
852 &micfil->dma_params_rx);
853
854 /* FIFO Watermark Control - FIFOWMK*/
855 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
856 MICFIL_FIFO_CTRL_FIFOWMK,
857 FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1));
858 if (ret)
859 return ret;
860
861 return 0;
862 }
863
fsl_micfil_component_probe(struct snd_soc_component * component)864 static int fsl_micfil_component_probe(struct snd_soc_component *component)
865 {
866 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(component);
867
868 if (micfil->soc->volume_sx)
869 snd_soc_add_component_controls(component, fsl_micfil_volume_sx_controls,
870 ARRAY_SIZE(fsl_micfil_volume_sx_controls));
871 else
872 snd_soc_add_component_controls(component, fsl_micfil_volume_controls,
873 ARRAY_SIZE(fsl_micfil_volume_controls));
874
875 return 0;
876 }
877
878 static const struct snd_soc_dai_ops fsl_micfil_dai_ops = {
879 .probe = fsl_micfil_dai_probe,
880 .startup = fsl_micfil_startup,
881 .trigger = fsl_micfil_trigger,
882 .hw_params = fsl_micfil_hw_params,
883 };
884
885 static struct snd_soc_dai_driver fsl_micfil_dai = {
886 .capture = {
887 .stream_name = "CPU-Capture",
888 .channels_min = 1,
889 .channels_max = 8,
890 .rates = SNDRV_PCM_RATE_8000_48000,
891 .formats = SNDRV_PCM_FMTBIT_S16_LE,
892 },
893 .ops = &fsl_micfil_dai_ops,
894 };
895
896 static const struct snd_soc_component_driver fsl_micfil_component = {
897 .name = "fsl-micfil-dai",
898 .probe = fsl_micfil_component_probe,
899 .controls = fsl_micfil_snd_controls,
900 .num_controls = ARRAY_SIZE(fsl_micfil_snd_controls),
901 .legacy_dai_naming = 1,
902 };
903
904 /* REGMAP */
905 static const struct reg_default fsl_micfil_reg_defaults[] = {
906 {REG_MICFIL_CTRL1, 0x00000000},
907 {REG_MICFIL_CTRL2, 0x00000000},
908 {REG_MICFIL_STAT, 0x00000000},
909 {REG_MICFIL_FIFO_CTRL, 0x00000007},
910 {REG_MICFIL_FIFO_STAT, 0x00000000},
911 {REG_MICFIL_DATACH0, 0x00000000},
912 {REG_MICFIL_DATACH1, 0x00000000},
913 {REG_MICFIL_DATACH2, 0x00000000},
914 {REG_MICFIL_DATACH3, 0x00000000},
915 {REG_MICFIL_DATACH4, 0x00000000},
916 {REG_MICFIL_DATACH5, 0x00000000},
917 {REG_MICFIL_DATACH6, 0x00000000},
918 {REG_MICFIL_DATACH7, 0x00000000},
919 {REG_MICFIL_DC_CTRL, 0x00000000},
920 {REG_MICFIL_OUT_CTRL, 0x00000000},
921 {REG_MICFIL_OUT_STAT, 0x00000000},
922 {REG_MICFIL_VAD0_CTRL1, 0x00000000},
923 {REG_MICFIL_VAD0_CTRL2, 0x000A0000},
924 {REG_MICFIL_VAD0_STAT, 0x00000000},
925 {REG_MICFIL_VAD0_SCONFIG, 0x00000000},
926 {REG_MICFIL_VAD0_NCONFIG, 0x80000000},
927 {REG_MICFIL_VAD0_NDATA, 0x00000000},
928 {REG_MICFIL_VAD0_ZCD, 0x00000004},
929 };
930
fsl_micfil_readable_reg(struct device * dev,unsigned int reg)931 static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)
932 {
933 switch (reg) {
934 case REG_MICFIL_CTRL1:
935 case REG_MICFIL_CTRL2:
936 case REG_MICFIL_STAT:
937 case REG_MICFIL_FIFO_CTRL:
938 case REG_MICFIL_FIFO_STAT:
939 case REG_MICFIL_DATACH0:
940 case REG_MICFIL_DATACH1:
941 case REG_MICFIL_DATACH2:
942 case REG_MICFIL_DATACH3:
943 case REG_MICFIL_DATACH4:
944 case REG_MICFIL_DATACH5:
945 case REG_MICFIL_DATACH6:
946 case REG_MICFIL_DATACH7:
947 case REG_MICFIL_DC_CTRL:
948 case REG_MICFIL_OUT_CTRL:
949 case REG_MICFIL_OUT_STAT:
950 case REG_MICFIL_FSYNC_CTRL:
951 case REG_MICFIL_VERID:
952 case REG_MICFIL_PARAM:
953 case REG_MICFIL_VAD0_CTRL1:
954 case REG_MICFIL_VAD0_CTRL2:
955 case REG_MICFIL_VAD0_STAT:
956 case REG_MICFIL_VAD0_SCONFIG:
957 case REG_MICFIL_VAD0_NCONFIG:
958 case REG_MICFIL_VAD0_NDATA:
959 case REG_MICFIL_VAD0_ZCD:
960 return true;
961 default:
962 return false;
963 }
964 }
965
fsl_micfil_writeable_reg(struct device * dev,unsigned int reg)966 static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg)
967 {
968 switch (reg) {
969 case REG_MICFIL_CTRL1:
970 case REG_MICFIL_CTRL2:
971 case REG_MICFIL_STAT: /* Write 1 to Clear */
972 case REG_MICFIL_FIFO_CTRL:
973 case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */
974 case REG_MICFIL_DC_CTRL:
975 case REG_MICFIL_OUT_CTRL:
976 case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */
977 case REG_MICFIL_FSYNC_CTRL:
978 case REG_MICFIL_VAD0_CTRL1:
979 case REG_MICFIL_VAD0_CTRL2:
980 case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */
981 case REG_MICFIL_VAD0_SCONFIG:
982 case REG_MICFIL_VAD0_NCONFIG:
983 case REG_MICFIL_VAD0_ZCD:
984 return true;
985 default:
986 return false;
987 }
988 }
989
fsl_micfil_volatile_reg(struct device * dev,unsigned int reg)990 static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg)
991 {
992 switch (reg) {
993 case REG_MICFIL_STAT:
994 case REG_MICFIL_DATACH0:
995 case REG_MICFIL_DATACH1:
996 case REG_MICFIL_DATACH2:
997 case REG_MICFIL_DATACH3:
998 case REG_MICFIL_DATACH4:
999 case REG_MICFIL_DATACH5:
1000 case REG_MICFIL_DATACH6:
1001 case REG_MICFIL_DATACH7:
1002 case REG_MICFIL_VERID:
1003 case REG_MICFIL_PARAM:
1004 case REG_MICFIL_VAD0_STAT:
1005 case REG_MICFIL_VAD0_NDATA:
1006 return true;
1007 default:
1008 return false;
1009 }
1010 }
1011
1012 static const struct regmap_config fsl_micfil_regmap_config = {
1013 .reg_bits = 32,
1014 .reg_stride = 4,
1015 .val_bits = 32,
1016
1017 .max_register = REG_MICFIL_VAD0_ZCD,
1018 .reg_defaults = fsl_micfil_reg_defaults,
1019 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults),
1020 .readable_reg = fsl_micfil_readable_reg,
1021 .volatile_reg = fsl_micfil_volatile_reg,
1022 .writeable_reg = fsl_micfil_writeable_reg,
1023 .cache_type = REGCACHE_RBTREE,
1024 };
1025
1026 /* END OF REGMAP */
1027
micfil_isr(int irq,void * devid)1028 static irqreturn_t micfil_isr(int irq, void *devid)
1029 {
1030 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1031 struct platform_device *pdev = micfil->pdev;
1032 u32 stat_reg;
1033 u32 fifo_stat_reg;
1034 u32 ctrl1_reg;
1035 bool dma_enabled;
1036 int i;
1037
1038 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
1039 regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
1040 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
1041
1042 dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA;
1043
1044 /* Channel 0-7 Output Data Flags */
1045 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
1046 if (stat_reg & MICFIL_STAT_CHXF(i))
1047 dev_dbg(&pdev->dev,
1048 "Data available in Data Channel %d\n", i);
1049 /* if DMA is not enabled, field must be written with 1
1050 * to clear
1051 */
1052 if (!dma_enabled)
1053 regmap_write_bits(micfil->regmap,
1054 REG_MICFIL_STAT,
1055 MICFIL_STAT_CHXF(i),
1056 MICFIL_STAT_CHXF(i));
1057 }
1058
1059 for (i = 0; i < MICFIL_FIFO_NUM; i++) {
1060 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i))
1061 dev_dbg(&pdev->dev,
1062 "FIFO Overflow Exception flag for channel %d\n",
1063 i);
1064
1065 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i))
1066 dev_dbg(&pdev->dev,
1067 "FIFO Underflow Exception flag for channel %d\n",
1068 i);
1069 }
1070
1071 return IRQ_HANDLED;
1072 }
1073
micfil_err_isr(int irq,void * devid)1074 static irqreturn_t micfil_err_isr(int irq, void *devid)
1075 {
1076 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1077 struct platform_device *pdev = micfil->pdev;
1078 u32 stat_reg;
1079
1080 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
1081
1082 if (stat_reg & MICFIL_STAT_BSY_FIL)
1083 dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");
1084
1085 if (stat_reg & MICFIL_STAT_FIR_RDY)
1086 dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");
1087
1088 if (stat_reg & MICFIL_STAT_LOWFREQF) {
1089 dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");
1090 regmap_write_bits(micfil->regmap, REG_MICFIL_STAT,
1091 MICFIL_STAT_LOWFREQF, MICFIL_STAT_LOWFREQF);
1092 }
1093
1094 return IRQ_HANDLED;
1095 }
1096
voice_detected_fn(int irq,void * devid)1097 static irqreturn_t voice_detected_fn(int irq, void *devid)
1098 {
1099 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1100 struct snd_kcontrol *kctl;
1101
1102 if (!micfil->card)
1103 return IRQ_HANDLED;
1104
1105 kctl = snd_soc_card_get_kcontrol(micfil->card, "VAD Detected");
1106 if (!kctl)
1107 return IRQ_HANDLED;
1108
1109 if (micfil->vad_detected)
1110 snd_ctl_notify(micfil->card->snd_card,
1111 SNDRV_CTL_EVENT_MASK_VALUE,
1112 &kctl->id);
1113
1114 return IRQ_HANDLED;
1115 }
1116
hwvad_isr(int irq,void * devid)1117 static irqreturn_t hwvad_isr(int irq, void *devid)
1118 {
1119 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1120 struct device *dev = &micfil->pdev->dev;
1121 u32 vad0_reg;
1122 int ret;
1123
1124 regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg);
1125
1126 /*
1127 * The only difference between MICFIL_VAD0_STAT_EF and
1128 * MICFIL_VAD0_STAT_IF is that the former requires Write
1129 * 1 to Clear. Since both flags are set, it is enough
1130 * to only read one of them
1131 */
1132 if (vad0_reg & MICFIL_VAD0_STAT_IF) {
1133 /* Write 1 to clear */
1134 regmap_write_bits(micfil->regmap, REG_MICFIL_VAD0_STAT,
1135 MICFIL_VAD0_STAT_IF,
1136 MICFIL_VAD0_STAT_IF);
1137
1138 micfil->vad_detected = 1;
1139 }
1140
1141 ret = fsl_micfil_hwvad_disable(micfil);
1142 if (ret)
1143 dev_err(dev, "Failed to disable hwvad\n");
1144
1145 return IRQ_WAKE_THREAD;
1146 }
1147
hwvad_err_isr(int irq,void * devid)1148 static irqreturn_t hwvad_err_isr(int irq, void *devid)
1149 {
1150 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
1151 struct device *dev = &micfil->pdev->dev;
1152 u32 vad0_reg;
1153
1154 regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg);
1155
1156 if (vad0_reg & MICFIL_VAD0_STAT_INSATF)
1157 dev_dbg(dev, "voice activity input overflow/underflow detected\n");
1158
1159 return IRQ_HANDLED;
1160 }
1161
1162 static int fsl_micfil_runtime_suspend(struct device *dev);
1163 static int fsl_micfil_runtime_resume(struct device *dev);
1164
fsl_micfil_probe(struct platform_device * pdev)1165 static int fsl_micfil_probe(struct platform_device *pdev)
1166 {
1167 struct device_node *np = pdev->dev.of_node;
1168 struct fsl_micfil *micfil;
1169 struct resource *res;
1170 void __iomem *regs;
1171 int ret, i;
1172
1173 micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);
1174 if (!micfil)
1175 return -ENOMEM;
1176
1177 micfil->pdev = pdev;
1178 strscpy(micfil->name, np->name, sizeof(micfil->name));
1179
1180 micfil->soc = of_device_get_match_data(&pdev->dev);
1181
1182 /* ipg_clk is used to control the registers
1183 * ipg_clk_app is used to operate the filter
1184 */
1185 micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app");
1186 if (IS_ERR(micfil->mclk)) {
1187 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
1188 PTR_ERR(micfil->mclk));
1189 return PTR_ERR(micfil->mclk);
1190 }
1191
1192 micfil->busclk = devm_clk_get(&pdev->dev, "ipg_clk");
1193 if (IS_ERR(micfil->busclk)) {
1194 dev_err(&pdev->dev, "failed to get ipg clock: %ld\n",
1195 PTR_ERR(micfil->busclk));
1196 return PTR_ERR(micfil->busclk);
1197 }
1198
1199 fsl_asoc_get_pll_clocks(&pdev->dev, &micfil->pll8k_clk,
1200 &micfil->pll11k_clk);
1201
1202 micfil->clk_src[MICFIL_AUDIO_PLL1] = micfil->pll8k_clk;
1203 micfil->clk_src[MICFIL_AUDIO_PLL2] = micfil->pll11k_clk;
1204 micfil->clk_src[MICFIL_CLK_EXT3] = devm_clk_get(&pdev->dev, "clkext3");
1205 if (IS_ERR(micfil->clk_src[MICFIL_CLK_EXT3]))
1206 micfil->clk_src[MICFIL_CLK_EXT3] = NULL;
1207
1208 /* init regmap */
1209 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1210 if (IS_ERR(regs))
1211 return PTR_ERR(regs);
1212
1213 micfil->regmap = devm_regmap_init_mmio(&pdev->dev,
1214 regs,
1215 &fsl_micfil_regmap_config);
1216 if (IS_ERR(micfil->regmap)) {
1217 dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n",
1218 PTR_ERR(micfil->regmap));
1219 return PTR_ERR(micfil->regmap);
1220 }
1221
1222 /* dataline mask for RX */
1223 ret = of_property_read_u32_index(np,
1224 "fsl,dataline",
1225 0,
1226 &micfil->dataline);
1227 if (ret)
1228 micfil->dataline = 1;
1229
1230 if (micfil->dataline & ~micfil->soc->dataline) {
1231 dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n",
1232 micfil->soc->dataline);
1233 return -EINVAL;
1234 }
1235
1236 /* get IRQs */
1237 for (i = 0; i < MICFIL_IRQ_LINES; i++) {
1238 micfil->irq[i] = platform_get_irq(pdev, i);
1239 if (micfil->irq[i] < 0)
1240 return micfil->irq[i];
1241 }
1242
1243 /* Digital Microphone interface interrupt */
1244 ret = devm_request_irq(&pdev->dev, micfil->irq[0],
1245 micfil_isr, IRQF_SHARED,
1246 micfil->name, micfil);
1247 if (ret) {
1248 dev_err(&pdev->dev, "failed to claim mic interface irq %u\n",
1249 micfil->irq[0]);
1250 return ret;
1251 }
1252
1253 /* Digital Microphone interface error interrupt */
1254 ret = devm_request_irq(&pdev->dev, micfil->irq[1],
1255 micfil_err_isr, IRQF_SHARED,
1256 micfil->name, micfil);
1257 if (ret) {
1258 dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n",
1259 micfil->irq[1]);
1260 return ret;
1261 }
1262
1263 /* Digital Microphone interface voice activity detector event */
1264 ret = devm_request_threaded_irq(&pdev->dev, micfil->irq[2],
1265 hwvad_isr, voice_detected_fn,
1266 IRQF_SHARED, micfil->name, micfil);
1267 if (ret) {
1268 dev_err(&pdev->dev, "failed to claim hwvad event irq %u\n",
1269 micfil->irq[0]);
1270 return ret;
1271 }
1272
1273 /* Digital Microphone interface voice activity detector error */
1274 ret = devm_request_irq(&pdev->dev, micfil->irq[3],
1275 hwvad_err_isr, IRQF_SHARED,
1276 micfil->name, micfil);
1277 if (ret) {
1278 dev_err(&pdev->dev, "failed to claim hwvad error irq %u\n",
1279 micfil->irq[1]);
1280 return ret;
1281 }
1282
1283 micfil->dma_params_rx.chan_name = "rx";
1284 micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0;
1285 micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
1286
1287 platform_set_drvdata(pdev, micfil);
1288
1289 pm_runtime_enable(&pdev->dev);
1290 if (!pm_runtime_enabled(&pdev->dev)) {
1291 ret = fsl_micfil_runtime_resume(&pdev->dev);
1292 if (ret)
1293 goto err_pm_disable;
1294 }
1295
1296 ret = pm_runtime_resume_and_get(&pdev->dev);
1297 if (ret < 0)
1298 goto err_pm_get_sync;
1299
1300 /* Get micfil version */
1301 ret = fsl_micfil_use_verid(&pdev->dev);
1302 if (ret < 0)
1303 dev_warn(&pdev->dev, "Error reading MICFIL version: %d\n", ret);
1304
1305 ret = pm_runtime_put_sync(&pdev->dev);
1306 if (ret < 0 && ret != -ENOSYS)
1307 goto err_pm_get_sync;
1308
1309 regcache_cache_only(micfil->regmap, true);
1310
1311 /*
1312 * Register platform component before registering cpu dai for there
1313 * is not defer probe for platform component in snd_soc_add_pcm_runtime().
1314 */
1315 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1316 if (ret) {
1317 dev_err(&pdev->dev, "failed to pcm register\n");
1318 goto err_pm_disable;
1319 }
1320
1321 fsl_micfil_dai.capture.formats = micfil->soc->formats;
1322
1323 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component,
1324 &fsl_micfil_dai, 1);
1325 if (ret) {
1326 dev_err(&pdev->dev, "failed to register component %s\n",
1327 fsl_micfil_component.name);
1328 goto err_pm_disable;
1329 }
1330
1331 return ret;
1332
1333 err_pm_get_sync:
1334 if (!pm_runtime_status_suspended(&pdev->dev))
1335 fsl_micfil_runtime_suspend(&pdev->dev);
1336 err_pm_disable:
1337 pm_runtime_disable(&pdev->dev);
1338
1339 return ret;
1340 }
1341
fsl_micfil_remove(struct platform_device * pdev)1342 static void fsl_micfil_remove(struct platform_device *pdev)
1343 {
1344 pm_runtime_disable(&pdev->dev);
1345 }
1346
fsl_micfil_runtime_suspend(struct device * dev)1347 static int fsl_micfil_runtime_suspend(struct device *dev)
1348 {
1349 struct fsl_micfil *micfil = dev_get_drvdata(dev);
1350
1351 regcache_cache_only(micfil->regmap, true);
1352
1353 clk_disable_unprepare(micfil->mclk);
1354 clk_disable_unprepare(micfil->busclk);
1355
1356 return 0;
1357 }
1358
fsl_micfil_runtime_resume(struct device * dev)1359 static int fsl_micfil_runtime_resume(struct device *dev)
1360 {
1361 struct fsl_micfil *micfil = dev_get_drvdata(dev);
1362 int ret;
1363
1364 ret = clk_prepare_enable(micfil->busclk);
1365 if (ret < 0)
1366 return ret;
1367
1368 ret = clk_prepare_enable(micfil->mclk);
1369 if (ret < 0) {
1370 clk_disable_unprepare(micfil->busclk);
1371 return ret;
1372 }
1373
1374 regcache_cache_only(micfil->regmap, false);
1375 regcache_mark_dirty(micfil->regmap);
1376 regcache_sync(micfil->regmap);
1377
1378 return 0;
1379 }
1380
1381 static const struct dev_pm_ops fsl_micfil_pm_ops = {
1382 SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend,
1383 fsl_micfil_runtime_resume,
1384 NULL)
1385 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1386 pm_runtime_force_resume)
1387 };
1388
1389 static struct platform_driver fsl_micfil_driver = {
1390 .probe = fsl_micfil_probe,
1391 .remove_new = fsl_micfil_remove,
1392 .driver = {
1393 .name = "fsl-micfil-dai",
1394 .pm = &fsl_micfil_pm_ops,
1395 .of_match_table = fsl_micfil_dt_ids,
1396 },
1397 };
1398 module_platform_driver(fsl_micfil_driver);
1399
1400 MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>");
1401 MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver");
1402 MODULE_LICENSE("Dual BSD/GPL");
1403