1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/qapi-events-run-state.h"
17 #include "qapi/error.h"
18 #include "qapi/visitor.h"
19 #include <math.h>
20 #include <sys/ioctl.h>
21 #include <sys/utsname.h>
22 #include <sys/syscall.h>
23 #include <sys/resource.h>
24 #include <sys/time.h>
25
26 #include <linux/kvm.h>
27 #include <linux/kvm_para.h>
28 #include "standard-headers/asm-x86/kvm_para.h"
29 #include "hw/xen/interface/arch-x86/cpuid.h"
30
31 #include "cpu.h"
32 #include "host-cpu.h"
33 #include "vmsr_energy.h"
34 #include "system/system.h"
35 #include "system/hw_accel.h"
36 #include "system/kvm_int.h"
37 #include "system/runstate.h"
38 #include "kvm_i386.h"
39 #include "../confidential-guest.h"
40 #include "sev.h"
41 #include "xen-emu.h"
42 #include "hyperv.h"
43 #include "hyperv-proto.h"
44
45 #include "gdbstub/enums.h"
46 #include "qemu/host-utils.h"
47 #include "qemu/main-loop.h"
48 #include "qemu/ratelimit.h"
49 #include "qemu/config-file.h"
50 #include "qemu/error-report.h"
51 #include "qemu/memalign.h"
52 #include "hw/i386/x86.h"
53 #include "hw/i386/kvm/xen_evtchn.h"
54 #include "hw/i386/pc.h"
55 #include "hw/i386/apic.h"
56 #include "hw/i386/apic_internal.h"
57 #include "hw/i386/apic-msidef.h"
58 #include "hw/i386/intel_iommu.h"
59 #include "hw/i386/topology.h"
60 #include "hw/i386/x86-iommu.h"
61 #include "hw/i386/e820_memory_layout.h"
62
63 #include "hw/xen/xen.h"
64
65 #include "hw/pci/pci.h"
66 #include "hw/pci/msi.h"
67 #include "hw/pci/msix.h"
68 #include "migration/blocker.h"
69 #include "exec/memattrs.h"
70 #include "trace.h"
71
72 #include CONFIG_DEVICES
73
74 //#define DEBUG_KVM
75
76 #ifdef DEBUG_KVM
77 #define DPRINTF(fmt, ...) \
78 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
79 #else
80 #define DPRINTF(fmt, ...) \
81 do { } while (0)
82 #endif
83
84 /*
85 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
86 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
87 * Since these must be part of guest physical memory, we need to allocate
88 * them, both by setting their start addresses in the kernel and by
89 * creating a corresponding e820 entry. We need 4 pages before the BIOS,
90 * so this value allows up to 16M BIOSes.
91 */
92 #define KVM_IDENTITY_BASE 0xfeffc000
93
94 /* From arch/x86/kvm/lapic.h */
95 #define KVM_APIC_BUS_CYCLE_NS 1
96 #define KVM_APIC_BUS_FREQUENCY (1000000000ULL / KVM_APIC_BUS_CYCLE_NS)
97
98 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
99 * 255 kvm_msr_entry structs */
100 #define MSR_BUF_SIZE 4096
101
102 typedef bool QEMURDMSRHandler(X86CPU *cpu, uint32_t msr, uint64_t *val);
103 typedef bool QEMUWRMSRHandler(X86CPU *cpu, uint32_t msr, uint64_t val);
104 typedef struct {
105 uint32_t msr;
106 QEMURDMSRHandler *rdmsr;
107 QEMUWRMSRHandler *wrmsr;
108 } KVMMSRHandlers;
109
110 static void kvm_init_msrs(X86CPU *cpu);
111 static int kvm_filter_msr(KVMState *s, uint32_t msr, QEMURDMSRHandler *rdmsr,
112 QEMUWRMSRHandler *wrmsr);
113
114 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
115 KVM_CAP_INFO(SET_TSS_ADDR),
116 KVM_CAP_INFO(EXT_CPUID),
117 KVM_CAP_INFO(MP_STATE),
118 KVM_CAP_INFO(SIGNAL_MSI),
119 KVM_CAP_INFO(IRQ_ROUTING),
120 KVM_CAP_INFO(DEBUGREGS),
121 KVM_CAP_INFO(XSAVE),
122 KVM_CAP_INFO(VCPU_EVENTS),
123 KVM_CAP_INFO(X86_ROBUST_SINGLESTEP),
124 KVM_CAP_INFO(MCE),
125 KVM_CAP_INFO(ADJUST_CLOCK),
126 KVM_CAP_INFO(SET_IDENTITY_MAP_ADDR),
127 KVM_CAP_LAST_INFO
128 };
129
130 static bool has_msr_star;
131 static bool has_msr_hsave_pa;
132 static bool has_msr_tsc_aux;
133 static bool has_msr_tsc_adjust;
134 static bool has_msr_tsc_deadline;
135 static bool has_msr_feature_control;
136 static bool has_msr_misc_enable;
137 static bool has_msr_smbase;
138 static bool has_msr_bndcfgs;
139 static int lm_capable_kernel;
140 static bool has_msr_hv_hypercall;
141 static bool has_msr_hv_crash;
142 static bool has_msr_hv_reset;
143 static bool has_msr_hv_vpindex;
144 static bool hv_vpindex_settable;
145 static bool has_msr_hv_runtime;
146 static bool has_msr_hv_synic;
147 static bool has_msr_hv_stimer;
148 static bool has_msr_hv_frequencies;
149 static bool has_msr_hv_reenlightenment;
150 static bool has_msr_hv_syndbg_options;
151 static bool has_msr_xss;
152 static bool has_msr_umwait;
153 static bool has_msr_spec_ctrl;
154 static bool has_tsc_scale_msr;
155 static bool has_msr_tsx_ctrl;
156 static bool has_msr_virt_ssbd;
157 static bool has_msr_smi_count;
158 static bool has_msr_arch_capabs;
159 static bool has_msr_core_capabs;
160 static bool has_msr_vmx_vmfunc;
161 static bool has_msr_ucode_rev;
162 static bool has_msr_vmx_procbased_ctls2;
163 static bool has_msr_perf_capabs;
164 static bool has_msr_pkrs;
165 static bool has_msr_hwcr;
166
167 static uint32_t has_architectural_pmu_version;
168 static uint32_t num_architectural_pmu_gp_counters;
169 static uint32_t num_architectural_pmu_fixed_counters;
170
171 static int has_xsave2;
172 static int has_xcrs;
173 static int has_sregs2;
174 static int has_exception_payload;
175 static int has_triple_fault_event;
176
177 static bool has_msr_mcg_ext_ctl;
178
179 static struct kvm_cpuid2 *cpuid_cache;
180 static struct kvm_cpuid2 *hv_cpuid_cache;
181 static struct kvm_msr_list *kvm_feature_msrs;
182
183 static KVMMSRHandlers msr_handlers[KVM_MSR_FILTER_MAX_RANGES];
184
185 #define BUS_LOCK_SLICE_TIME 1000000000ULL /* ns */
186 static RateLimit bus_lock_ratelimit_ctrl;
187 static int kvm_get_one_msr(X86CPU *cpu, int index, uint64_t *value);
188
189 static const char *vm_type_name[] = {
190 [KVM_X86_DEFAULT_VM] = "default",
191 [KVM_X86_SEV_VM] = "SEV",
192 [KVM_X86_SEV_ES_VM] = "SEV-ES",
193 [KVM_X86_SNP_VM] = "SEV-SNP",
194 };
195
kvm_is_vm_type_supported(int type)196 bool kvm_is_vm_type_supported(int type)
197 {
198 uint32_t machine_types;
199
200 /*
201 * old KVM doesn't support KVM_CAP_VM_TYPES but KVM_X86_DEFAULT_VM
202 * is always supported
203 */
204 if (type == KVM_X86_DEFAULT_VM) {
205 return true;
206 }
207
208 machine_types = kvm_check_extension(KVM_STATE(current_machine->accelerator),
209 KVM_CAP_VM_TYPES);
210 return !!(machine_types & BIT(type));
211 }
212
kvm_get_vm_type(MachineState * ms)213 int kvm_get_vm_type(MachineState *ms)
214 {
215 int kvm_type = KVM_X86_DEFAULT_VM;
216
217 if (ms->cgs) {
218 if (!object_dynamic_cast(OBJECT(ms->cgs), TYPE_X86_CONFIDENTIAL_GUEST)) {
219 error_report("configuration type %s not supported for x86 guests",
220 object_get_typename(OBJECT(ms->cgs)));
221 exit(1);
222 }
223 kvm_type = x86_confidential_guest_kvm_type(
224 X86_CONFIDENTIAL_GUEST(ms->cgs));
225 }
226
227 if (!kvm_is_vm_type_supported(kvm_type)) {
228 error_report("vm-type %s not supported by KVM", vm_type_name[kvm_type]);
229 exit(1);
230 }
231
232 return kvm_type;
233 }
234
kvm_enable_hypercall(uint64_t enable_mask)235 bool kvm_enable_hypercall(uint64_t enable_mask)
236 {
237 KVMState *s = KVM_STATE(current_accel());
238
239 return !kvm_vm_enable_cap(s, KVM_CAP_EXIT_HYPERCALL, 0, enable_mask);
240 }
241
kvm_has_smm(void)242 bool kvm_has_smm(void)
243 {
244 return kvm_vm_check_extension(kvm_state, KVM_CAP_X86_SMM);
245 }
246
kvm_has_adjust_clock_stable(void)247 bool kvm_has_adjust_clock_stable(void)
248 {
249 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
250
251 return (ret & KVM_CLOCK_TSC_STABLE);
252 }
253
kvm_has_exception_payload(void)254 bool kvm_has_exception_payload(void)
255 {
256 return has_exception_payload;
257 }
258
kvm_x2apic_api_set_flags(uint64_t flags)259 static bool kvm_x2apic_api_set_flags(uint64_t flags)
260 {
261 KVMState *s = KVM_STATE(current_accel());
262
263 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
264 }
265
266 #define MEMORIZE(fn, _result) \
267 ({ \
268 static bool _memorized; \
269 \
270 if (_memorized) { \
271 return _result; \
272 } \
273 _memorized = true; \
274 _result = fn; \
275 })
276
277 static bool has_x2apic_api;
278
kvm_has_x2apic_api(void)279 bool kvm_has_x2apic_api(void)
280 {
281 return has_x2apic_api;
282 }
283
kvm_enable_x2apic(void)284 bool kvm_enable_x2apic(void)
285 {
286 return MEMORIZE(
287 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
288 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
289 has_x2apic_api);
290 }
291
kvm_hv_vpindex_settable(void)292 bool kvm_hv_vpindex_settable(void)
293 {
294 return hv_vpindex_settable;
295 }
296
kvm_get_tsc(CPUState * cs)297 static int kvm_get_tsc(CPUState *cs)
298 {
299 X86CPU *cpu = X86_CPU(cs);
300 CPUX86State *env = &cpu->env;
301 uint64_t value;
302 int ret;
303
304 if (env->tsc_valid) {
305 return 0;
306 }
307
308 env->tsc_valid = !runstate_is_running();
309
310 ret = kvm_get_one_msr(cpu, MSR_IA32_TSC, &value);
311 if (ret < 0) {
312 return ret;
313 }
314
315 env->tsc = value;
316 return 0;
317 }
318
do_kvm_synchronize_tsc(CPUState * cpu,run_on_cpu_data arg)319 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
320 {
321 kvm_get_tsc(cpu);
322 }
323
kvm_synchronize_all_tsc(void)324 void kvm_synchronize_all_tsc(void)
325 {
326 CPUState *cpu;
327
328 if (kvm_enabled()) {
329 CPU_FOREACH(cpu) {
330 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
331 }
332 }
333 }
334
try_get_cpuid(KVMState * s,int max)335 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
336 {
337 struct kvm_cpuid2 *cpuid;
338 int r, size;
339
340 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
341 cpuid = g_malloc0(size);
342 cpuid->nent = max;
343 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
344 if (r == 0 && cpuid->nent >= max) {
345 r = -E2BIG;
346 }
347 if (r < 0) {
348 if (r == -E2BIG) {
349 g_free(cpuid);
350 return NULL;
351 } else {
352 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
353 strerror(-r));
354 exit(1);
355 }
356 }
357 return cpuid;
358 }
359
360 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
361 * for all entries.
362 */
get_supported_cpuid(KVMState * s)363 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
364 {
365 struct kvm_cpuid2 *cpuid;
366 int max = 1;
367
368 if (cpuid_cache != NULL) {
369 return cpuid_cache;
370 }
371 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
372 max *= 2;
373 }
374 cpuid_cache = cpuid;
375 return cpuid;
376 }
377
host_tsx_broken(void)378 static bool host_tsx_broken(void)
379 {
380 int family, model, stepping;\
381 char vendor[CPUID_VENDOR_SZ + 1];
382
383 host_cpu_vendor_fms(vendor, &family, &model, &stepping);
384
385 /* Check if we are running on a Haswell host known to have broken TSX */
386 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
387 (family == 6) &&
388 ((model == 63 && stepping < 4) ||
389 model == 60 || model == 69 || model == 70);
390 }
391
392 /* Returns the value for a specific register on the cpuid entry
393 */
cpuid_entry_get_reg(struct kvm_cpuid_entry2 * entry,int reg)394 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
395 {
396 uint32_t ret = 0;
397 switch (reg) {
398 case R_EAX:
399 ret = entry->eax;
400 break;
401 case R_EBX:
402 ret = entry->ebx;
403 break;
404 case R_ECX:
405 ret = entry->ecx;
406 break;
407 case R_EDX:
408 ret = entry->edx;
409 break;
410 }
411 return ret;
412 }
413
414 /* Find matching entry for function/index on kvm_cpuid2 struct
415 */
cpuid_find_entry(struct kvm_cpuid2 * cpuid,uint32_t function,uint32_t index)416 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
417 uint32_t function,
418 uint32_t index)
419 {
420 int i;
421 for (i = 0; i < cpuid->nent; ++i) {
422 if (cpuid->entries[i].function == function &&
423 cpuid->entries[i].index == index) {
424 return &cpuid->entries[i];
425 }
426 }
427 /* not found: */
428 return NULL;
429 }
430
kvm_arch_get_supported_cpuid(KVMState * s,uint32_t function,uint32_t index,int reg)431 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
432 uint32_t index, int reg)
433 {
434 struct kvm_cpuid2 *cpuid;
435 uint32_t ret = 0;
436 uint32_t cpuid_1_edx, unused;
437 uint64_t bitmask;
438
439 cpuid = get_supported_cpuid(s);
440
441 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
442 if (entry) {
443 ret = cpuid_entry_get_reg(entry, reg);
444 }
445
446 /* Fixups for the data returned by KVM, below */
447
448 if (function == 1 && reg == R_EDX) {
449 /* KVM before 2.6.30 misreports the following features */
450 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
451 /* KVM never reports CPUID_HT but QEMU can support when vcpus > 1 */
452 ret |= CPUID_HT;
453 } else if (function == 1 && reg == R_ECX) {
454 /* We can set the hypervisor flag, even if KVM does not return it on
455 * GET_SUPPORTED_CPUID
456 */
457 ret |= CPUID_EXT_HYPERVISOR;
458 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
459 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
460 * and the irqchip is in the kernel.
461 */
462 if (kvm_irqchip_in_kernel() &&
463 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
464 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
465 }
466
467 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
468 * without the in-kernel irqchip
469 */
470 if (!kvm_irqchip_in_kernel()) {
471 ret &= ~CPUID_EXT_X2APIC;
472 }
473
474 if (enable_cpu_pm) {
475 int disable_exits = kvm_check_extension(s,
476 KVM_CAP_X86_DISABLE_EXITS);
477
478 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
479 ret |= CPUID_EXT_MONITOR;
480 }
481 }
482 } else if (function == 6 && reg == R_EAX) {
483 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
484 } else if (function == 7 && index == 0 && reg == R_EBX) {
485 /* Not new instructions, just an optimization. */
486 uint32_t ebx;
487 host_cpuid(7, 0, &unused, &ebx, &unused, &unused);
488 ret |= ebx & CPUID_7_0_EBX_ERMS;
489
490 if (host_tsx_broken()) {
491 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
492 }
493 } else if (function == 7 && index == 0 && reg == R_EDX) {
494 /* Not new instructions, just an optimization. */
495 uint32_t edx;
496 host_cpuid(7, 0, &unused, &unused, &unused, &edx);
497 ret |= edx & CPUID_7_0_EDX_FSRM;
498
499 /*
500 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
501 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
502 * returned by KVM_GET_MSR_INDEX_LIST.
503 *
504 * But also, because Windows does not like ARCH_CAPABILITIES on AMD
505 * mcahines at all, do not show the fake ARCH_CAPABILITIES MSR that
506 * KVM sets up.
507 */
508 if (!has_msr_arch_capabs || !(edx & CPUID_7_0_EDX_ARCH_CAPABILITIES)) {
509 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
510 }
511 } else if (function == 7 && index == 1 && reg == R_EAX) {
512 /* Not new instructions, just an optimization. */
513 uint32_t eax;
514 host_cpuid(7, 1, &eax, &unused, &unused, &unused);
515 ret |= eax & (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC);
516 } else if (function == 7 && index == 2 && reg == R_EDX) {
517 uint32_t edx;
518 host_cpuid(7, 2, &unused, &unused, &unused, &edx);
519 ret |= edx & CPUID_7_2_EDX_MCDT_NO;
520 } else if (function == 0xd && index == 0 &&
521 (reg == R_EAX || reg == R_EDX)) {
522 /*
523 * The value returned by KVM_GET_SUPPORTED_CPUID does not include
524 * features that still have to be enabled with the arch_prctl
525 * system call. QEMU needs the full value, which is retrieved
526 * with KVM_GET_DEVICE_ATTR.
527 */
528 struct kvm_device_attr attr = {
529 .group = 0,
530 .attr = KVM_X86_XCOMP_GUEST_SUPP,
531 .addr = (unsigned long) &bitmask
532 };
533
534 bool sys_attr = kvm_check_extension(s, KVM_CAP_SYS_ATTRIBUTES);
535 if (!sys_attr) {
536 return ret;
537 }
538
539 int rc = kvm_ioctl(s, KVM_GET_DEVICE_ATTR, &attr);
540 if (rc < 0) {
541 if (rc != -ENXIO) {
542 warn_report("KVM_GET_DEVICE_ATTR(0, KVM_X86_XCOMP_GUEST_SUPP) "
543 "error: %d", rc);
544 }
545 return ret;
546 }
547 ret = (reg == R_EAX) ? bitmask : bitmask >> 32;
548 } else if (function == 0x80000001 && reg == R_ECX) {
549 /*
550 * It's safe to enable TOPOEXT even if it's not returned by
551 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
552 * us to keep CPU models including TOPOEXT runnable on older kernels.
553 */
554 ret |= CPUID_EXT3_TOPOEXT;
555 } else if (function == 0x80000001 && reg == R_EDX) {
556 /* On Intel, kvm returns cpuid according to the Intel spec,
557 * so add missing bits according to the AMD spec:
558 */
559 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
560 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
561 } else if (function == 0x80000007 && reg == R_EBX) {
562 ret |= CPUID_8000_0007_EBX_OVERFLOW_RECOV | CPUID_8000_0007_EBX_SUCCOR;
563 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
564 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
565 * be enabled without the in-kernel irqchip
566 */
567 if (!kvm_irqchip_in_kernel()) {
568 ret &= ~CPUID_KVM_PV_UNHALT;
569 }
570 if (kvm_irqchip_is_split()) {
571 ret |= CPUID_KVM_MSI_EXT_DEST_ID;
572 }
573 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
574 ret |= CPUID_KVM_HINTS_REALTIME;
575 }
576
577 if (current_machine->cgs) {
578 ret = x86_confidential_guest_mask_cpuid_features(
579 X86_CONFIDENTIAL_GUEST(current_machine->cgs),
580 function, index, reg, ret);
581 }
582 return ret;
583 }
584
kvm_arch_get_supported_msr_feature(KVMState * s,uint32_t index)585 uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
586 {
587 struct {
588 struct kvm_msrs info;
589 struct kvm_msr_entry entries[1];
590 } msr_data = {};
591 uint64_t value;
592 uint32_t ret, can_be_one, must_be_one;
593
594 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
595 return 0;
596 }
597
598 /* Check if requested MSR is supported feature MSR */
599 int i;
600 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
601 if (kvm_feature_msrs->indices[i] == index) {
602 break;
603 }
604 if (i == kvm_feature_msrs->nmsrs) {
605 return 0; /* if the feature MSR is not supported, simply return 0 */
606 }
607
608 msr_data.info.nmsrs = 1;
609 msr_data.entries[0].index = index;
610
611 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
612 if (ret != 1) {
613 error_report("KVM get MSR (index=0x%x) feature failed, %s",
614 index, strerror(-ret));
615 exit(1);
616 }
617
618 value = msr_data.entries[0].data;
619 switch (index) {
620 case MSR_IA32_VMX_PROCBASED_CTLS2:
621 if (!has_msr_vmx_procbased_ctls2) {
622 /* KVM forgot to add these bits for some time, do this ourselves. */
623 if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) &
624 CPUID_XSAVE_XSAVES) {
625 value |= (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32;
626 }
627 if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) &
628 CPUID_EXT_RDRAND) {
629 value |= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32;
630 }
631 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
632 CPUID_7_0_EBX_INVPCID) {
633 value |= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32;
634 }
635 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
636 CPUID_7_0_EBX_RDSEED) {
637 value |= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32;
638 }
639 if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) &
640 CPUID_EXT2_RDTSCP) {
641 value |= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32;
642 }
643 }
644 /* fall through */
645 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
646 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
647 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
648 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
649 /*
650 * Return true for bits that can be one, but do not have to be one.
651 * The SDM tells us which bits could have a "must be one" setting,
652 * so we can do the opposite transformation in make_vmx_msr_value.
653 */
654 must_be_one = (uint32_t)value;
655 can_be_one = (uint32_t)(value >> 32);
656 return can_be_one & ~must_be_one;
657
658 default:
659 return value;
660 }
661 }
662
kvm_get_mce_cap_supported(KVMState * s,uint64_t * mce_cap,int * max_banks)663 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
664 int *max_banks)
665 {
666 *max_banks = kvm_check_extension(s, KVM_CAP_MCE);
667 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
668 }
669
kvm_mce_inject(X86CPU * cpu,hwaddr paddr,int code)670 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
671 {
672 CPUState *cs = CPU(cpu);
673 CPUX86State *env = &cpu->env;
674 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_EN | MCI_STATUS_MISCV |
675 MCI_STATUS_ADDRV;
676 uint64_t mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV;
677 int flags = 0;
678
679 if (!IS_AMD_CPU(env)) {
680 status |= MCI_STATUS_S | MCI_STATUS_UC;
681 if (code == BUS_MCEERR_AR) {
682 status |= MCI_STATUS_AR | 0x134;
683 mcg_status |= MCG_STATUS_EIPV;
684 } else {
685 status |= 0xc0;
686 }
687 } else {
688 if (code == BUS_MCEERR_AR) {
689 status |= MCI_STATUS_UC | MCI_STATUS_POISON;
690 mcg_status |= MCG_STATUS_EIPV;
691 } else {
692 /* Setting the POISON bit for deferred errors indicates to the
693 * guest kernel that the address provided by the MCE is valid
694 * and usable which will ensure that the guest kernel will send
695 * a SIGBUS_AO signal to the guest process. This allows for
696 * more desirable behavior in the case that the guest process
697 * with poisoned memory has set the MCE_KILL_EARLY prctl flag
698 * which indicates that the process would prefer to handle or
699 * shutdown due to the poisoned memory condition before the
700 * memory has been accessed.
701 *
702 * While the POISON bit would not be set in a deferred error
703 * sent from hardware, the bit is not meaningful for deferred
704 * errors and can be reused in this scenario.
705 */
706 status |= MCI_STATUS_DEFERRED | MCI_STATUS_POISON;
707 }
708 }
709
710 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
711 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
712 * guest kernel back into env->mcg_ext_ctl.
713 */
714 cpu_synchronize_state(cs);
715 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
716 mcg_status |= MCG_STATUS_LMCE;
717 flags = 0;
718 }
719
720 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
721 (MCM_ADDR_PHYS << 6) | 0xc, flags);
722 }
723
emit_hypervisor_memory_failure(MemoryFailureAction action,bool ar)724 static void emit_hypervisor_memory_failure(MemoryFailureAction action, bool ar)
725 {
726 MemoryFailureFlags mff = {.action_required = ar, .recursive = false};
727
728 qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_HYPERVISOR, action,
729 &mff);
730 }
731
hardware_memory_error(void * host_addr)732 static void hardware_memory_error(void *host_addr)
733 {
734 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_FATAL, true);
735 error_report("QEMU got Hardware memory error at addr %p", host_addr);
736 exit(1);
737 }
738
kvm_arch_on_sigbus_vcpu(CPUState * c,int code,void * addr)739 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
740 {
741 X86CPU *cpu = X86_CPU(c);
742 CPUX86State *env = &cpu->env;
743 ram_addr_t ram_addr;
744 hwaddr paddr;
745
746 /* If we get an action required MCE, it has been injected by KVM
747 * while the VM was running. An action optional MCE instead should
748 * be coming from the main thread, which qemu_init_sigbus identifies
749 * as the "early kill" thread.
750 */
751 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
752
753 if ((env->mcg_cap & MCG_SER_P) && addr) {
754 ram_addr = qemu_ram_addr_from_host(addr);
755 if (ram_addr != RAM_ADDR_INVALID &&
756 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
757 kvm_hwpoison_page_add(ram_addr);
758 kvm_mce_inject(cpu, paddr, code);
759
760 /*
761 * Use different logging severity based on error type.
762 * If there is additional MCE reporting on the hypervisor, QEMU VA
763 * could be another source to identify the PA and MCE details.
764 */
765 if (code == BUS_MCEERR_AR) {
766 error_report("Guest MCE Memory Error at QEMU addr %p and "
767 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
768 addr, paddr, "BUS_MCEERR_AR");
769 } else {
770 warn_report("Guest MCE Memory Error at QEMU addr %p and "
771 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
772 addr, paddr, "BUS_MCEERR_AO");
773 }
774
775 return;
776 }
777
778 if (code == BUS_MCEERR_AO) {
779 warn_report("Hardware memory error at addr %p of type %s "
780 "for memory used by QEMU itself instead of guest system!",
781 addr, "BUS_MCEERR_AO");
782 }
783 }
784
785 if (code == BUS_MCEERR_AR) {
786 hardware_memory_error(addr);
787 }
788
789 /* Hope we are lucky for AO MCE, just notify a event */
790 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, false);
791 }
792
kvm_queue_exception(CPUX86State * env,int32_t exception_nr,uint8_t exception_has_payload,uint64_t exception_payload)793 static void kvm_queue_exception(CPUX86State *env,
794 int32_t exception_nr,
795 uint8_t exception_has_payload,
796 uint64_t exception_payload)
797 {
798 assert(env->exception_nr == -1);
799 assert(!env->exception_pending);
800 assert(!env->exception_injected);
801 assert(!env->exception_has_payload);
802
803 env->exception_nr = exception_nr;
804
805 if (has_exception_payload) {
806 env->exception_pending = 1;
807
808 env->exception_has_payload = exception_has_payload;
809 env->exception_payload = exception_payload;
810 } else {
811 env->exception_injected = 1;
812
813 if (exception_nr == EXCP01_DB) {
814 assert(exception_has_payload);
815 env->dr[6] = exception_payload;
816 } else if (exception_nr == EXCP0E_PAGE) {
817 assert(exception_has_payload);
818 env->cr[2] = exception_payload;
819 } else {
820 assert(!exception_has_payload);
821 }
822 }
823 }
824
cpu_update_state(void * opaque,bool running,RunState state)825 static void cpu_update_state(void *opaque, bool running, RunState state)
826 {
827 CPUX86State *env = opaque;
828
829 if (running) {
830 env->tsc_valid = false;
831 }
832 }
833
kvm_arch_vcpu_id(CPUState * cs)834 unsigned long kvm_arch_vcpu_id(CPUState *cs)
835 {
836 X86CPU *cpu = X86_CPU(cs);
837 return cpu->apic_id;
838 }
839
840 #ifndef KVM_CPUID_SIGNATURE_NEXT
841 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
842 #endif
843
hyperv_enabled(X86CPU * cpu)844 static bool hyperv_enabled(X86CPU *cpu)
845 {
846 return kvm_check_extension(kvm_state, KVM_CAP_HYPERV) > 0 &&
847 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) ||
848 cpu->hyperv_features || cpu->hyperv_passthrough);
849 }
850
851 /*
852 * Check whether target_freq is within conservative
853 * ntp correctable bounds (250ppm) of freq
854 */
freq_within_bounds(int freq,int target_freq)855 static inline bool freq_within_bounds(int freq, int target_freq)
856 {
857 int max_freq = freq + (freq * 250 / 1000000);
858 int min_freq = freq - (freq * 250 / 1000000);
859
860 if (target_freq >= min_freq && target_freq <= max_freq) {
861 return true;
862 }
863
864 return false;
865 }
866
kvm_arch_set_tsc_khz(CPUState * cs)867 static int kvm_arch_set_tsc_khz(CPUState *cs)
868 {
869 X86CPU *cpu = X86_CPU(cs);
870 CPUX86State *env = &cpu->env;
871 int r, cur_freq;
872 bool set_ioctl = false;
873
874 if (!env->tsc_khz) {
875 return 0;
876 }
877
878 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
879 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : -ENOTSUP;
880
881 /*
882 * If TSC scaling is supported, attempt to set TSC frequency.
883 */
884 if (kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL)) {
885 set_ioctl = true;
886 }
887
888 /*
889 * If desired TSC frequency is within bounds of NTP correction,
890 * attempt to set TSC frequency.
891 */
892 if (cur_freq != -ENOTSUP && freq_within_bounds(cur_freq, env->tsc_khz)) {
893 set_ioctl = true;
894 }
895
896 r = set_ioctl ?
897 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
898 -ENOTSUP;
899
900 if (r < 0) {
901 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
902 * TSC frequency doesn't match the one we want.
903 */
904 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
905 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
906 -ENOTSUP;
907 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
908 warn_report("TSC frequency mismatch between "
909 "VM (%" PRId64 " kHz) and host (%d kHz), "
910 "and TSC scaling unavailable",
911 env->tsc_khz, cur_freq);
912 return r;
913 }
914 }
915
916 return 0;
917 }
918
tsc_is_stable_and_known(CPUX86State * env)919 static bool tsc_is_stable_and_known(CPUX86State *env)
920 {
921 if (!env->tsc_khz) {
922 return false;
923 }
924 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
925 || env->user_tsc_khz;
926 }
927
928 #define DEFAULT_EVMCS_VERSION ((1 << 8) | 1)
929
930 static struct {
931 const char *desc;
932 struct {
933 uint32_t func;
934 int reg;
935 uint32_t bits;
936 } flags[2];
937 uint64_t dependencies;
938 bool skip_passthrough;
939 } kvm_hyperv_properties[] = {
940 [HYPERV_FEAT_RELAXED] = {
941 .desc = "relaxed timing (hv-relaxed)",
942 .flags = {
943 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
944 .bits = HV_RELAXED_TIMING_RECOMMENDED}
945 }
946 },
947 [HYPERV_FEAT_VAPIC] = {
948 .desc = "virtual APIC (hv-vapic)",
949 .flags = {
950 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
951 .bits = HV_APIC_ACCESS_AVAILABLE}
952 }
953 },
954 [HYPERV_FEAT_TIME] = {
955 .desc = "clocksources (hv-time)",
956 .flags = {
957 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
958 .bits = HV_TIME_REF_COUNT_AVAILABLE | HV_REFERENCE_TSC_AVAILABLE}
959 }
960 },
961 [HYPERV_FEAT_CRASH] = {
962 .desc = "crash MSRs (hv-crash)",
963 .flags = {
964 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
965 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
966 }
967 },
968 [HYPERV_FEAT_RESET] = {
969 .desc = "reset MSR (hv-reset)",
970 .flags = {
971 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
972 .bits = HV_RESET_AVAILABLE}
973 }
974 },
975 [HYPERV_FEAT_VPINDEX] = {
976 .desc = "VP_INDEX MSR (hv-vpindex)",
977 .flags = {
978 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
979 .bits = HV_VP_INDEX_AVAILABLE}
980 }
981 },
982 [HYPERV_FEAT_RUNTIME] = {
983 .desc = "VP_RUNTIME MSR (hv-runtime)",
984 .flags = {
985 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
986 .bits = HV_VP_RUNTIME_AVAILABLE}
987 }
988 },
989 [HYPERV_FEAT_SYNIC] = {
990 .desc = "synthetic interrupt controller (hv-synic)",
991 .flags = {
992 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
993 .bits = HV_SYNIC_AVAILABLE}
994 }
995 },
996 [HYPERV_FEAT_STIMER] = {
997 .desc = "synthetic timers (hv-stimer)",
998 .flags = {
999 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
1000 .bits = HV_SYNTIMERS_AVAILABLE}
1001 },
1002 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
1003 },
1004 [HYPERV_FEAT_FREQUENCIES] = {
1005 .desc = "frequency MSRs (hv-frequencies)",
1006 .flags = {
1007 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
1008 .bits = HV_ACCESS_FREQUENCY_MSRS},
1009 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1010 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
1011 }
1012 },
1013 [HYPERV_FEAT_REENLIGHTENMENT] = {
1014 .desc = "reenlightenment MSRs (hv-reenlightenment)",
1015 .flags = {
1016 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
1017 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
1018 }
1019 },
1020 [HYPERV_FEAT_TLBFLUSH] = {
1021 .desc = "paravirtualized TLB flush (hv-tlbflush)",
1022 .flags = {
1023 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
1024 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
1025 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
1026 },
1027 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
1028 },
1029 [HYPERV_FEAT_EVMCS] = {
1030 .desc = "enlightened VMCS (hv-evmcs)",
1031 .flags = {
1032 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
1033 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
1034 },
1035 .dependencies = BIT(HYPERV_FEAT_VAPIC)
1036 },
1037 [HYPERV_FEAT_IPI] = {
1038 .desc = "paravirtualized IPI (hv-ipi)",
1039 .flags = {
1040 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
1041 .bits = HV_CLUSTER_IPI_RECOMMENDED |
1042 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
1043 },
1044 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
1045 },
1046 [HYPERV_FEAT_STIMER_DIRECT] = {
1047 .desc = "direct mode synthetic timers (hv-stimer-direct)",
1048 .flags = {
1049 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1050 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
1051 },
1052 .dependencies = BIT(HYPERV_FEAT_STIMER)
1053 },
1054 [HYPERV_FEAT_AVIC] = {
1055 .desc = "AVIC/APICv support (hv-avic/hv-apicv)",
1056 .flags = {
1057 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
1058 .bits = HV_DEPRECATING_AEOI_RECOMMENDED}
1059 }
1060 },
1061 [HYPERV_FEAT_SYNDBG] = {
1062 .desc = "Enable synthetic kernel debugger channel (hv-syndbg)",
1063 .flags = {
1064 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1065 .bits = HV_FEATURE_DEBUG_MSRS_AVAILABLE}
1066 },
1067 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_RELAXED),
1068 .skip_passthrough = true,
1069 },
1070 [HYPERV_FEAT_MSR_BITMAP] = {
1071 .desc = "enlightened MSR-Bitmap (hv-emsr-bitmap)",
1072 .flags = {
1073 {.func = HV_CPUID_NESTED_FEATURES, .reg = R_EAX,
1074 .bits = HV_NESTED_MSR_BITMAP}
1075 }
1076 },
1077 [HYPERV_FEAT_XMM_INPUT] = {
1078 .desc = "XMM fast hypercall input (hv-xmm-input)",
1079 .flags = {
1080 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1081 .bits = HV_HYPERCALL_XMM_INPUT_AVAILABLE}
1082 }
1083 },
1084 [HYPERV_FEAT_TLBFLUSH_EXT] = {
1085 .desc = "Extended gva ranges for TLB flush hypercalls (hv-tlbflush-ext)",
1086 .flags = {
1087 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1088 .bits = HV_EXT_GVA_RANGES_FLUSH_AVAILABLE}
1089 },
1090 .dependencies = BIT(HYPERV_FEAT_TLBFLUSH)
1091 },
1092 [HYPERV_FEAT_TLBFLUSH_DIRECT] = {
1093 .desc = "direct TLB flush (hv-tlbflush-direct)",
1094 .flags = {
1095 {.func = HV_CPUID_NESTED_FEATURES, .reg = R_EAX,
1096 .bits = HV_NESTED_DIRECT_FLUSH}
1097 },
1098 .dependencies = BIT(HYPERV_FEAT_VAPIC)
1099 },
1100 };
1101
try_get_hv_cpuid(CPUState * cs,int max,bool do_sys_ioctl)1102 static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max,
1103 bool do_sys_ioctl)
1104 {
1105 struct kvm_cpuid2 *cpuid;
1106 int r, size;
1107
1108 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
1109 cpuid = g_malloc0(size);
1110 cpuid->nent = max;
1111
1112 if (do_sys_ioctl) {
1113 r = kvm_ioctl(kvm_state, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
1114 } else {
1115 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
1116 }
1117 if (r == 0 && cpuid->nent >= max) {
1118 r = -E2BIG;
1119 }
1120 if (r < 0) {
1121 if (r == -E2BIG) {
1122 g_free(cpuid);
1123 return NULL;
1124 } else {
1125 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
1126 strerror(-r));
1127 exit(1);
1128 }
1129 }
1130 return cpuid;
1131 }
1132
1133 /*
1134 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
1135 * for all entries.
1136 */
get_supported_hv_cpuid(CPUState * cs)1137 static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
1138 {
1139 struct kvm_cpuid2 *cpuid;
1140 /* 0x40000000..0x40000005, 0x4000000A, 0x40000080..0x40000082 leaves */
1141 int max = 11;
1142 int i;
1143 bool do_sys_ioctl;
1144
1145 do_sys_ioctl =
1146 kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID) > 0;
1147
1148 /*
1149 * Non-empty KVM context is needed when KVM_CAP_SYS_HYPERV_CPUID is
1150 * unsupported, kvm_hyperv_expand_features() checks for that.
1151 */
1152 assert(do_sys_ioctl || cs->kvm_state);
1153
1154 /*
1155 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
1156 * -E2BIG, however, it doesn't report back the right size. Keep increasing
1157 * it and re-trying until we succeed.
1158 */
1159 while ((cpuid = try_get_hv_cpuid(cs, max, do_sys_ioctl)) == NULL) {
1160 max++;
1161 }
1162
1163 /*
1164 * KVM_GET_SUPPORTED_HV_CPUID does not set EVMCS CPUID bit before
1165 * KVM_CAP_HYPERV_ENLIGHTENED_VMCS is enabled but we want to get the
1166 * information early, just check for the capability and set the bit
1167 * manually.
1168 */
1169 if (!do_sys_ioctl && kvm_check_extension(cs->kvm_state,
1170 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1171 for (i = 0; i < cpuid->nent; i++) {
1172 if (cpuid->entries[i].function == HV_CPUID_ENLIGHTMENT_INFO) {
1173 cpuid->entries[i].eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
1174 }
1175 }
1176 }
1177
1178 return cpuid;
1179 }
1180
1181 /*
1182 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
1183 * leaves from KVM_CAP_HYPERV* and present MSRs data.
1184 */
get_supported_hv_cpuid_legacy(CPUState * cs)1185 static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
1186 {
1187 X86CPU *cpu = X86_CPU(cs);
1188 struct kvm_cpuid2 *cpuid;
1189 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
1190
1191 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
1192 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
1193 cpuid->nent = 2;
1194
1195 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
1196 entry_feat = &cpuid->entries[0];
1197 entry_feat->function = HV_CPUID_FEATURES;
1198
1199 entry_recomm = &cpuid->entries[1];
1200 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
1201 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
1202
1203 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
1204 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
1205 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
1206 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1207 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
1208 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
1209 }
1210
1211 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
1212 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
1213 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
1214 }
1215
1216 if (has_msr_hv_frequencies) {
1217 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
1218 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
1219 }
1220
1221 if (has_msr_hv_crash) {
1222 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
1223 }
1224
1225 if (has_msr_hv_reenlightenment) {
1226 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
1227 }
1228
1229 if (has_msr_hv_reset) {
1230 entry_feat->eax |= HV_RESET_AVAILABLE;
1231 }
1232
1233 if (has_msr_hv_vpindex) {
1234 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
1235 }
1236
1237 if (has_msr_hv_runtime) {
1238 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
1239 }
1240
1241 if (has_msr_hv_synic) {
1242 unsigned int cap = cpu->hyperv_synic_kvm_only ?
1243 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1244
1245 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
1246 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1247 }
1248 }
1249
1250 if (has_msr_hv_stimer) {
1251 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
1252 }
1253
1254 if (has_msr_hv_syndbg_options) {
1255 entry_feat->edx |= HV_GUEST_DEBUGGING_AVAILABLE;
1256 entry_feat->edx |= HV_FEATURE_DEBUG_MSRS_AVAILABLE;
1257 entry_feat->ebx |= HV_PARTITION_DEBUGGING_ALLOWED;
1258 }
1259
1260 if (kvm_check_extension(cs->kvm_state,
1261 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
1262 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
1263 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1264 }
1265
1266 if (kvm_check_extension(cs->kvm_state,
1267 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1268 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
1269 }
1270
1271 if (kvm_check_extension(cs->kvm_state,
1272 KVM_CAP_HYPERV_SEND_IPI) > 0) {
1273 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
1274 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1275 }
1276
1277 return cpuid;
1278 }
1279
hv_cpuid_get_host(CPUState * cs,uint32_t func,int reg)1280 static uint32_t hv_cpuid_get_host(CPUState *cs, uint32_t func, int reg)
1281 {
1282 struct kvm_cpuid_entry2 *entry;
1283 struct kvm_cpuid2 *cpuid;
1284
1285 if (hv_cpuid_cache) {
1286 cpuid = hv_cpuid_cache;
1287 } else {
1288 if (kvm_check_extension(kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1289 cpuid = get_supported_hv_cpuid(cs);
1290 } else {
1291 /*
1292 * 'cs->kvm_state' may be NULL when Hyper-V features are expanded
1293 * before KVM context is created but this is only done when
1294 * KVM_CAP_SYS_HYPERV_CPUID is supported and it implies
1295 * KVM_CAP_HYPERV_CPUID.
1296 */
1297 assert(cs->kvm_state);
1298
1299 cpuid = get_supported_hv_cpuid_legacy(cs);
1300 }
1301 hv_cpuid_cache = cpuid;
1302 }
1303
1304 if (!cpuid) {
1305 return 0;
1306 }
1307
1308 entry = cpuid_find_entry(cpuid, func, 0);
1309 if (!entry) {
1310 return 0;
1311 }
1312
1313 return cpuid_entry_get_reg(entry, reg);
1314 }
1315
hyperv_feature_supported(CPUState * cs,int feature)1316 static bool hyperv_feature_supported(CPUState *cs, int feature)
1317 {
1318 uint32_t func, bits;
1319 int i, reg;
1320
1321 /*
1322 * kvm_hyperv_properties needs to define at least one CPUID flag which
1323 * must be used to detect the feature, it's hard to say whether it is
1324 * supported or not otherwise.
1325 */
1326 assert(kvm_hyperv_properties[feature].flags[0].func);
1327
1328 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
1329
1330 func = kvm_hyperv_properties[feature].flags[i].func;
1331 reg = kvm_hyperv_properties[feature].flags[i].reg;
1332 bits = kvm_hyperv_properties[feature].flags[i].bits;
1333
1334 if (!func) {
1335 continue;
1336 }
1337
1338 if ((hv_cpuid_get_host(cs, func, reg) & bits) != bits) {
1339 return false;
1340 }
1341 }
1342
1343 return true;
1344 }
1345
1346 /* Checks that all feature dependencies are enabled */
hv_feature_check_deps(X86CPU * cpu,int feature,Error ** errp)1347 static bool hv_feature_check_deps(X86CPU *cpu, int feature, Error **errp)
1348 {
1349 uint64_t deps;
1350 int dep_feat;
1351
1352 deps = kvm_hyperv_properties[feature].dependencies;
1353 while (deps) {
1354 dep_feat = ctz64(deps);
1355 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
1356 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1357 kvm_hyperv_properties[feature].desc,
1358 kvm_hyperv_properties[dep_feat].desc);
1359 return false;
1360 }
1361 deps &= ~(1ull << dep_feat);
1362 }
1363
1364 return true;
1365 }
1366
hv_build_cpuid_leaf(CPUState * cs,uint32_t func,int reg)1367 static uint32_t hv_build_cpuid_leaf(CPUState *cs, uint32_t func, int reg)
1368 {
1369 X86CPU *cpu = X86_CPU(cs);
1370 uint32_t r = 0;
1371 int i, j;
1372
1373 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties); i++) {
1374 if (!hyperv_feat_enabled(cpu, i)) {
1375 continue;
1376 }
1377
1378 for (j = 0; j < ARRAY_SIZE(kvm_hyperv_properties[i].flags); j++) {
1379 if (kvm_hyperv_properties[i].flags[j].func != func) {
1380 continue;
1381 }
1382 if (kvm_hyperv_properties[i].flags[j].reg != reg) {
1383 continue;
1384 }
1385
1386 r |= kvm_hyperv_properties[i].flags[j].bits;
1387 }
1388 }
1389
1390 /* HV_CPUID_NESTED_FEATURES.EAX also encodes the supported eVMCS range */
1391 if (func == HV_CPUID_NESTED_FEATURES && reg == R_EAX) {
1392 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1393 r |= DEFAULT_EVMCS_VERSION;
1394 }
1395 }
1396
1397 return r;
1398 }
1399
1400 /*
1401 * Expand Hyper-V CPU features. In partucular, check that all the requested
1402 * features are supported by the host and the sanity of the configuration
1403 * (that all the required dependencies are included). Also, this takes care
1404 * of 'hv_passthrough' mode and fills the environment with all supported
1405 * Hyper-V features.
1406 */
kvm_hyperv_expand_features(X86CPU * cpu,Error ** errp)1407 bool kvm_hyperv_expand_features(X86CPU *cpu, Error **errp)
1408 {
1409 CPUState *cs = CPU(cpu);
1410 Error *local_err = NULL;
1411 int feat;
1412
1413 if (!hyperv_enabled(cpu))
1414 return true;
1415
1416 /*
1417 * When kvm_hyperv_expand_features is called at CPU feature expansion
1418 * time per-CPU kvm_state is not available yet so we can only proceed
1419 * when KVM_CAP_SYS_HYPERV_CPUID is supported.
1420 */
1421 if (!cs->kvm_state &&
1422 !kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID))
1423 return true;
1424
1425 if (cpu->hyperv_passthrough) {
1426 cpu->hyperv_vendor_id[0] =
1427 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EBX);
1428 cpu->hyperv_vendor_id[1] =
1429 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_ECX);
1430 cpu->hyperv_vendor_id[2] =
1431 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EDX);
1432 cpu->hyperv_vendor = g_realloc(cpu->hyperv_vendor,
1433 sizeof(cpu->hyperv_vendor_id) + 1);
1434 memcpy(cpu->hyperv_vendor, cpu->hyperv_vendor_id,
1435 sizeof(cpu->hyperv_vendor_id));
1436 cpu->hyperv_vendor[sizeof(cpu->hyperv_vendor_id)] = 0;
1437
1438 cpu->hyperv_interface_id[0] =
1439 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EAX);
1440 cpu->hyperv_interface_id[1] =
1441 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EBX);
1442 cpu->hyperv_interface_id[2] =
1443 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_ECX);
1444 cpu->hyperv_interface_id[3] =
1445 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EDX);
1446
1447 cpu->hyperv_ver_id_build =
1448 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EAX);
1449 cpu->hyperv_ver_id_major =
1450 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) >> 16;
1451 cpu->hyperv_ver_id_minor =
1452 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) & 0xffff;
1453 cpu->hyperv_ver_id_sp =
1454 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_ECX);
1455 cpu->hyperv_ver_id_sb =
1456 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) >> 24;
1457 cpu->hyperv_ver_id_sn =
1458 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) & 0xffffff;
1459
1460 cpu->hv_max_vps = hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS,
1461 R_EAX);
1462 cpu->hyperv_limits[0] =
1463 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EBX);
1464 cpu->hyperv_limits[1] =
1465 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_ECX);
1466 cpu->hyperv_limits[2] =
1467 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EDX);
1468
1469 cpu->hyperv_spinlock_attempts =
1470 hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EBX);
1471
1472 /*
1473 * Mark feature as enabled in 'cpu->hyperv_features' as
1474 * hv_build_cpuid_leaf() uses this info to build guest CPUIDs.
1475 */
1476 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) {
1477 if (hyperv_feature_supported(cs, feat) &&
1478 !kvm_hyperv_properties[feat].skip_passthrough) {
1479 cpu->hyperv_features |= BIT(feat);
1480 }
1481 }
1482 } else {
1483 /* Check features availability and dependencies */
1484 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) {
1485 /* If the feature was not requested skip it. */
1486 if (!hyperv_feat_enabled(cpu, feat)) {
1487 continue;
1488 }
1489
1490 /* Check if the feature is supported by KVM */
1491 if (!hyperv_feature_supported(cs, feat)) {
1492 error_setg(errp, "Hyper-V %s is not supported by kernel",
1493 kvm_hyperv_properties[feat].desc);
1494 return false;
1495 }
1496
1497 /* Check dependencies */
1498 if (!hv_feature_check_deps(cpu, feat, &local_err)) {
1499 error_propagate(errp, local_err);
1500 return false;
1501 }
1502 }
1503 }
1504
1505 /* Additional dependencies not covered by kvm_hyperv_properties[] */
1506 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1507 !cpu->hyperv_synic_kvm_only &&
1508 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
1509 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1510 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1511 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
1512 return false;
1513 }
1514
1515 return true;
1516 }
1517
1518 /*
1519 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent.
1520 */
hyperv_fill_cpuids(CPUState * cs,struct kvm_cpuid_entry2 * cpuid_ent)1521 static int hyperv_fill_cpuids(CPUState *cs,
1522 struct kvm_cpuid_entry2 *cpuid_ent)
1523 {
1524 X86CPU *cpu = X86_CPU(cs);
1525 struct kvm_cpuid_entry2 *c;
1526 uint32_t signature[3];
1527 uint32_t cpuid_i = 0, max_cpuid_leaf = 0;
1528 uint32_t nested_eax =
1529 hv_build_cpuid_leaf(cs, HV_CPUID_NESTED_FEATURES, R_EAX);
1530
1531 max_cpuid_leaf = nested_eax ? HV_CPUID_NESTED_FEATURES :
1532 HV_CPUID_IMPLEMENT_LIMITS;
1533
1534 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG)) {
1535 max_cpuid_leaf =
1536 MAX(max_cpuid_leaf, HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES);
1537 }
1538
1539 c = &cpuid_ent[cpuid_i++];
1540 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1541 c->eax = max_cpuid_leaf;
1542 c->ebx = cpu->hyperv_vendor_id[0];
1543 c->ecx = cpu->hyperv_vendor_id[1];
1544 c->edx = cpu->hyperv_vendor_id[2];
1545
1546 c = &cpuid_ent[cpuid_i++];
1547 c->function = HV_CPUID_INTERFACE;
1548 c->eax = cpu->hyperv_interface_id[0];
1549 c->ebx = cpu->hyperv_interface_id[1];
1550 c->ecx = cpu->hyperv_interface_id[2];
1551 c->edx = cpu->hyperv_interface_id[3];
1552
1553 c = &cpuid_ent[cpuid_i++];
1554 c->function = HV_CPUID_VERSION;
1555 c->eax = cpu->hyperv_ver_id_build;
1556 c->ebx = (uint32_t)cpu->hyperv_ver_id_major << 16 |
1557 cpu->hyperv_ver_id_minor;
1558 c->ecx = cpu->hyperv_ver_id_sp;
1559 c->edx = (uint32_t)cpu->hyperv_ver_id_sb << 24 |
1560 (cpu->hyperv_ver_id_sn & 0xffffff);
1561
1562 c = &cpuid_ent[cpuid_i++];
1563 c->function = HV_CPUID_FEATURES;
1564 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EAX);
1565 c->ebx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EBX);
1566 c->edx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EDX);
1567
1568 /* Unconditionally required with any Hyper-V enlightenment */
1569 c->eax |= HV_HYPERCALL_AVAILABLE;
1570
1571 /* SynIC and Vmbus devices require messages/signals hypercalls */
1572 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1573 !cpu->hyperv_synic_kvm_only) {
1574 c->ebx |= HV_POST_MESSAGES | HV_SIGNAL_EVENTS;
1575 }
1576
1577
1578 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1579 c->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1580
1581 c = &cpuid_ent[cpuid_i++];
1582 c->function = HV_CPUID_ENLIGHTMENT_INFO;
1583 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX);
1584 c->ebx = cpu->hyperv_spinlock_attempts;
1585
1586 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC) &&
1587 !hyperv_feat_enabled(cpu, HYPERV_FEAT_AVIC)) {
1588 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
1589 }
1590
1591 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_ON) {
1592 c->eax |= HV_NO_NONARCH_CORESHARING;
1593 } else if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO) {
1594 c->eax |= hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX) &
1595 HV_NO_NONARCH_CORESHARING;
1596 }
1597
1598 c = &cpuid_ent[cpuid_i++];
1599 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1600 c->eax = cpu->hv_max_vps;
1601 c->ebx = cpu->hyperv_limits[0];
1602 c->ecx = cpu->hyperv_limits[1];
1603 c->edx = cpu->hyperv_limits[2];
1604
1605 if (nested_eax) {
1606 uint32_t function;
1607
1608 /* Create zeroed 0x40000006..0x40000009 leaves */
1609 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1610 function < HV_CPUID_NESTED_FEATURES; function++) {
1611 c = &cpuid_ent[cpuid_i++];
1612 c->function = function;
1613 }
1614
1615 c = &cpuid_ent[cpuid_i++];
1616 c->function = HV_CPUID_NESTED_FEATURES;
1617 c->eax = nested_eax;
1618 }
1619
1620 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG)) {
1621 c = &cpuid_ent[cpuid_i++];
1622 c->function = HV_CPUID_SYNDBG_VENDOR_AND_MAX_FUNCTIONS;
1623 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1624 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1625 memcpy(signature, "Microsoft VS", 12);
1626 c->eax = 0;
1627 c->ebx = signature[0];
1628 c->ecx = signature[1];
1629 c->edx = signature[2];
1630
1631 c = &cpuid_ent[cpuid_i++];
1632 c->function = HV_CPUID_SYNDBG_INTERFACE;
1633 memcpy(signature, "VS#1\0\0\0\0\0\0\0\0", 12);
1634 c->eax = signature[0];
1635 c->ebx = 0;
1636 c->ecx = 0;
1637 c->edx = 0;
1638
1639 c = &cpuid_ent[cpuid_i++];
1640 c->function = HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES;
1641 c->eax = HV_SYNDBG_CAP_ALLOW_KERNEL_DEBUGGING;
1642 c->ebx = 0;
1643 c->ecx = 0;
1644 c->edx = 0;
1645 }
1646
1647 return cpuid_i;
1648 }
1649
1650 static Error *hv_passthrough_mig_blocker;
1651 static Error *hv_no_nonarch_cs_mig_blocker;
1652
1653 /* Checks that the exposed eVMCS version range is supported by KVM */
evmcs_version_supported(uint16_t evmcs_version,uint16_t supported_evmcs_version)1654 static bool evmcs_version_supported(uint16_t evmcs_version,
1655 uint16_t supported_evmcs_version)
1656 {
1657 uint8_t min_version = evmcs_version & 0xff;
1658 uint8_t max_version = evmcs_version >> 8;
1659 uint8_t min_supported_version = supported_evmcs_version & 0xff;
1660 uint8_t max_supported_version = supported_evmcs_version >> 8;
1661
1662 return (min_version >= min_supported_version) &&
1663 (max_version <= max_supported_version);
1664 }
1665
hyperv_init_vcpu(X86CPU * cpu)1666 static int hyperv_init_vcpu(X86CPU *cpu)
1667 {
1668 CPUState *cs = CPU(cpu);
1669 Error *local_err = NULL;
1670 int ret;
1671
1672 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1673 error_setg(&hv_passthrough_mig_blocker,
1674 "'hv-passthrough' CPU flag prevents migration, use explicit"
1675 " set of hv-* flags instead");
1676 ret = migrate_add_blocker(&hv_passthrough_mig_blocker, &local_err);
1677 if (ret < 0) {
1678 error_report_err(local_err);
1679 return ret;
1680 }
1681 }
1682
1683 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO &&
1684 hv_no_nonarch_cs_mig_blocker == NULL) {
1685 error_setg(&hv_no_nonarch_cs_mig_blocker,
1686 "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration"
1687 " use explicit 'hv-no-nonarch-coresharing=on' instead (but"
1688 " make sure SMT is disabled and/or that vCPUs are properly"
1689 " pinned)");
1690 ret = migrate_add_blocker(&hv_no_nonarch_cs_mig_blocker, &local_err);
1691 if (ret < 0) {
1692 error_report_err(local_err);
1693 return ret;
1694 }
1695 }
1696
1697 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
1698 /*
1699 * the kernel doesn't support setting vp_index; assert that its value
1700 * is in sync
1701 */
1702 uint64_t value;
1703
1704 ret = kvm_get_one_msr(cpu, HV_X64_MSR_VP_INDEX, &value);
1705 if (ret < 0) {
1706 return ret;
1707 }
1708
1709 if (value != hyperv_vp_index(CPU(cpu))) {
1710 error_report("kernel's vp_index != QEMU's vp_index");
1711 return -ENXIO;
1712 }
1713 }
1714
1715 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
1716 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1717 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1718 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
1719 if (ret < 0) {
1720 error_report("failed to turn on HyperV SynIC in KVM: %s",
1721 strerror(-ret));
1722 return ret;
1723 }
1724
1725 if (!cpu->hyperv_synic_kvm_only) {
1726 ret = hyperv_x86_synic_add(cpu);
1727 if (ret < 0) {
1728 error_report("failed to create HyperV SynIC: %s",
1729 strerror(-ret));
1730 return ret;
1731 }
1732 }
1733 }
1734
1735 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1736 uint16_t evmcs_version = DEFAULT_EVMCS_VERSION;
1737 uint16_t supported_evmcs_version;
1738
1739 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1740 (uintptr_t)&supported_evmcs_version);
1741
1742 /*
1743 * KVM is required to support EVMCS ver.1. as that's what 'hv-evmcs'
1744 * option sets. Note: we hardcode the maximum supported eVMCS version
1745 * to '1' as well so 'hv-evmcs' feature is migratable even when (and if)
1746 * ver.2 is implemented. A new option (e.g. 'hv-evmcs=2') will then have
1747 * to be added.
1748 */
1749 if (ret < 0) {
1750 error_report("Hyper-V %s is not supported by kernel",
1751 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
1752 return ret;
1753 }
1754
1755 if (!evmcs_version_supported(evmcs_version, supported_evmcs_version)) {
1756 error_report("eVMCS version range [%d..%d] is not supported by "
1757 "kernel (supported: [%d..%d])", evmcs_version & 0xff,
1758 evmcs_version >> 8, supported_evmcs_version & 0xff,
1759 supported_evmcs_version >> 8);
1760 return -ENOTSUP;
1761 }
1762 }
1763
1764 if (cpu->hyperv_enforce_cpuid) {
1765 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENFORCE_CPUID, 0, 1);
1766 if (ret < 0) {
1767 error_report("failed to enable KVM_CAP_HYPERV_ENFORCE_CPUID: %s",
1768 strerror(-ret));
1769 return ret;
1770 }
1771 }
1772
1773 /* Skip SynIC and VP_INDEX since they are hard deps already */
1774 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_STIMER) &&
1775 hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC) &&
1776 hyperv_feat_enabled(cpu, HYPERV_FEAT_RUNTIME)) {
1777 hyperv_x86_set_vmbus_recommended_features_enabled();
1778 }
1779
1780 return 0;
1781 }
1782
1783 static Error *invtsc_mig_blocker;
1784
1785 #define KVM_MAX_CPUID_ENTRIES 100
1786
kvm_init_xsave(CPUX86State * env)1787 static void kvm_init_xsave(CPUX86State *env)
1788 {
1789 if (has_xsave2) {
1790 env->xsave_buf_len = QEMU_ALIGN_UP(has_xsave2, 4096);
1791 } else {
1792 env->xsave_buf_len = sizeof(struct kvm_xsave);
1793 }
1794
1795 env->xsave_buf = qemu_memalign(4096, env->xsave_buf_len);
1796 memset(env->xsave_buf, 0, env->xsave_buf_len);
1797 /*
1798 * The allocated storage must be large enough for all of the
1799 * possible XSAVE state components.
1800 */
1801 assert(kvm_arch_get_supported_cpuid(kvm_state, 0xd, 0, R_ECX) <=
1802 env->xsave_buf_len);
1803 }
1804
kvm_init_nested_state(CPUX86State * env)1805 static void kvm_init_nested_state(CPUX86State *env)
1806 {
1807 struct kvm_vmx_nested_state_hdr *vmx_hdr;
1808 uint32_t size;
1809
1810 if (!env->nested_state) {
1811 return;
1812 }
1813
1814 size = env->nested_state->size;
1815
1816 memset(env->nested_state, 0, size);
1817 env->nested_state->size = size;
1818
1819 if (cpu_has_vmx(env)) {
1820 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
1821 vmx_hdr = &env->nested_state->hdr.vmx;
1822 vmx_hdr->vmxon_pa = -1ull;
1823 vmx_hdr->vmcs12_pa = -1ull;
1824 } else if (cpu_has_svm(env)) {
1825 env->nested_state->format = KVM_STATE_NESTED_FORMAT_SVM;
1826 }
1827 }
1828
kvm_x86_build_cpuid(CPUX86State * env,struct kvm_cpuid_entry2 * entries,uint32_t cpuid_i)1829 static uint32_t kvm_x86_build_cpuid(CPUX86State *env,
1830 struct kvm_cpuid_entry2 *entries,
1831 uint32_t cpuid_i)
1832 {
1833 uint32_t limit, i, j;
1834 uint32_t unused;
1835 struct kvm_cpuid_entry2 *c;
1836
1837 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
1838
1839 for (i = 0; i <= limit; i++) {
1840 j = 0;
1841 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1842 goto full;
1843 }
1844 c = &entries[cpuid_i++];
1845 switch (i) {
1846 case 2: {
1847 /* Keep reading function 2 till all the input is received */
1848 int times;
1849
1850 c->function = i;
1851 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1852 times = c->eax & 0xff;
1853 if (times > 1) {
1854 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1855 KVM_CPUID_FLAG_STATE_READ_NEXT;
1856 }
1857
1858 for (j = 1; j < times; ++j) {
1859 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1860 goto full;
1861 }
1862 c = &entries[cpuid_i++];
1863 c->function = i;
1864 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1865 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1866 }
1867 break;
1868 }
1869 case 0x1f:
1870 if (!x86_has_extended_topo(env->avail_cpu_topo)) {
1871 cpuid_i--;
1872 break;
1873 }
1874 /* fallthrough */
1875 case 4:
1876 case 0xb:
1877 case 0xd:
1878 for (j = 0; ; j++) {
1879 c->function = i;
1880 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1881 c->index = j;
1882 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1883
1884 if (i == 4 && c->eax == 0) {
1885 break;
1886 }
1887 if (i == 0xb && !(c->ecx & 0xff00)) {
1888 break;
1889 }
1890 if (i == 0x1f && !(c->ecx & 0xff00)) {
1891 break;
1892 }
1893 if (i == 0xd && c->eax == 0) {
1894 if (j < 63) {
1895 continue;
1896 } else {
1897 cpuid_i--;
1898 break;
1899 }
1900 }
1901 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1902 goto full;
1903 }
1904 c = &entries[cpuid_i++];
1905 }
1906 break;
1907 case 0x12:
1908 for (j = 0; ; j++) {
1909 c->function = i;
1910 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1911 c->index = j;
1912 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1913
1914 if (j > 1 && (c->eax & 0xf) != 1) {
1915 break;
1916 }
1917
1918 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1919 goto full;
1920 }
1921 c = &entries[cpuid_i++];
1922 }
1923 break;
1924 case 0x7:
1925 case 0x14:
1926 case 0x1d:
1927 case 0x1e:
1928 case 0x24: {
1929 uint32_t times;
1930
1931 c->function = i;
1932 c->index = 0;
1933 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1934 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1935 times = c->eax;
1936
1937 for (j = 1; j <= times; ++j) {
1938 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1939 goto full;
1940 }
1941 c = &entries[cpuid_i++];
1942 c->function = i;
1943 c->index = j;
1944 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1945 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1946 }
1947 break;
1948 }
1949 default:
1950 c->function = i;
1951 c->flags = 0;
1952 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1953 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1954 /*
1955 * KVM already returns all zeroes if a CPUID entry is missing,
1956 * so we can omit it and avoid hitting KVM's 80-entry limit.
1957 */
1958 cpuid_i--;
1959 }
1960 break;
1961 }
1962 }
1963
1964 if (limit >= 0x0a) {
1965 uint32_t eax, edx;
1966
1967 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1968
1969 has_architectural_pmu_version = eax & 0xff;
1970 if (has_architectural_pmu_version > 0) {
1971 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
1972
1973 /* Shouldn't be more than 32, since that's the number of bits
1974 * available in EBX to tell us _which_ counters are available.
1975 * Play it safe.
1976 */
1977 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1978 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1979 }
1980
1981 if (has_architectural_pmu_version > 1) {
1982 num_architectural_pmu_fixed_counters = edx & 0x1f;
1983
1984 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1985 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1986 }
1987 }
1988 }
1989 }
1990
1991 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
1992
1993 for (i = 0x80000000; i <= limit; i++) {
1994 j = 0;
1995 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1996 goto full;
1997 }
1998 c = &entries[cpuid_i++];
1999
2000 switch (i) {
2001 case 0x8000001d:
2002 /* Query for all AMD cache information leaves */
2003 for (j = 0; ; j++) {
2004 c->function = i;
2005 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2006 c->index = j;
2007 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
2008
2009 if (c->eax == 0) {
2010 break;
2011 }
2012 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
2013 goto full;
2014 }
2015 c = &entries[cpuid_i++];
2016 }
2017 break;
2018 default:
2019 c->function = i;
2020 c->flags = 0;
2021 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
2022 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
2023 /*
2024 * KVM already returns all zeroes if a CPUID entry is missing,
2025 * so we can omit it and avoid hitting KVM's 80-entry limit.
2026 */
2027 cpuid_i--;
2028 }
2029 break;
2030 }
2031 }
2032
2033 /* Call Centaur's CPUID instructions they are supported. */
2034 if (env->cpuid_xlevel2 > 0) {
2035 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
2036
2037 for (i = 0xC0000000; i <= limit; i++) {
2038 j = 0;
2039 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
2040 goto full;
2041 }
2042 c = &entries[cpuid_i++];
2043
2044 c->function = i;
2045 c->flags = 0;
2046 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
2047 }
2048 }
2049
2050 return cpuid_i;
2051
2052 full:
2053 fprintf(stderr, "cpuid_data is full, no space for "
2054 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
2055 abort();
2056 }
2057
kvm_arch_init_vcpu(CPUState * cs)2058 int kvm_arch_init_vcpu(CPUState *cs)
2059 {
2060 struct {
2061 struct kvm_cpuid2 cpuid;
2062 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
2063 } cpuid_data;
2064 /*
2065 * The kernel defines these structs with padding fields so there
2066 * should be no extra padding in our cpuid_data struct.
2067 */
2068 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
2069 sizeof(struct kvm_cpuid2) +
2070 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
2071
2072 X86CPU *cpu = X86_CPU(cs);
2073 CPUX86State *env = &cpu->env;
2074 uint32_t cpuid_i;
2075 struct kvm_cpuid_entry2 *c;
2076 uint32_t signature[3];
2077 int kvm_base = KVM_CPUID_SIGNATURE;
2078 int max_nested_state_len;
2079 int r;
2080 Error *local_err = NULL;
2081
2082 memset(&cpuid_data, 0, sizeof(cpuid_data));
2083
2084 cpuid_i = 0;
2085
2086 has_xsave2 = kvm_check_extension(cs->kvm_state, KVM_CAP_XSAVE2);
2087
2088 r = kvm_arch_set_tsc_khz(cs);
2089 if (r < 0) {
2090 return r;
2091 }
2092
2093 /* vcpu's TSC frequency is either specified by user, or following
2094 * the value used by KVM if the former is not present. In the
2095 * latter case, we query it from KVM and record in env->tsc_khz,
2096 * so that vcpu's TSC frequency can be migrated later via this field.
2097 */
2098 if (!env->tsc_khz) {
2099 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
2100 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
2101 -ENOTSUP;
2102 if (r > 0) {
2103 env->tsc_khz = r;
2104 }
2105 }
2106
2107 env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY;
2108
2109 /*
2110 * kvm_hyperv_expand_features() is called here for the second time in case
2111 * KVM_CAP_SYS_HYPERV_CPUID is not supported. While we can't possibly handle
2112 * 'query-cpu-model-expansion' in this case as we don't have a KVM vCPU to
2113 * check which Hyper-V enlightenments are supported and which are not, we
2114 * can still proceed and check/expand Hyper-V enlightenments here so legacy
2115 * behavior is preserved.
2116 */
2117 if (!kvm_hyperv_expand_features(cpu, &local_err)) {
2118 error_report_err(local_err);
2119 return -ENOSYS;
2120 }
2121
2122 if (hyperv_enabled(cpu)) {
2123 r = hyperv_init_vcpu(cpu);
2124 if (r) {
2125 return r;
2126 }
2127
2128 cpuid_i = hyperv_fill_cpuids(cs, cpuid_data.entries);
2129 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
2130 has_msr_hv_hypercall = true;
2131 }
2132
2133 if (cs->kvm_state->xen_version) {
2134 #ifdef CONFIG_XEN_EMU
2135 struct kvm_cpuid_entry2 *xen_max_leaf;
2136
2137 memcpy(signature, "XenVMMXenVMM", 12);
2138
2139 xen_max_leaf = c = &cpuid_data.entries[cpuid_i++];
2140 c->function = kvm_base + XEN_CPUID_SIGNATURE;
2141 c->eax = kvm_base + XEN_CPUID_TIME;
2142 c->ebx = signature[0];
2143 c->ecx = signature[1];
2144 c->edx = signature[2];
2145
2146 c = &cpuid_data.entries[cpuid_i++];
2147 c->function = kvm_base + XEN_CPUID_VENDOR;
2148 c->eax = cs->kvm_state->xen_version;
2149 c->ebx = 0;
2150 c->ecx = 0;
2151 c->edx = 0;
2152
2153 c = &cpuid_data.entries[cpuid_i++];
2154 c->function = kvm_base + XEN_CPUID_HVM_MSR;
2155 /* Number of hypercall-transfer pages */
2156 c->eax = 1;
2157 /* Hypercall MSR base address */
2158 if (hyperv_enabled(cpu)) {
2159 c->ebx = XEN_HYPERCALL_MSR_HYPERV;
2160 kvm_xen_init(cs->kvm_state, c->ebx);
2161 } else {
2162 c->ebx = XEN_HYPERCALL_MSR;
2163 }
2164 c->ecx = 0;
2165 c->edx = 0;
2166
2167 c = &cpuid_data.entries[cpuid_i++];
2168 c->function = kvm_base + XEN_CPUID_TIME;
2169 c->eax = ((!!tsc_is_stable_and_known(env) << 1) |
2170 (!!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP) << 2));
2171 /* default=0 (emulate if necessary) */
2172 c->ebx = 0;
2173 /* guest tsc frequency */
2174 c->ecx = env->user_tsc_khz;
2175 /* guest tsc incarnation (migration count) */
2176 c->edx = 0;
2177
2178 c = &cpuid_data.entries[cpuid_i++];
2179 c->function = kvm_base + XEN_CPUID_HVM;
2180 xen_max_leaf->eax = kvm_base + XEN_CPUID_HVM;
2181 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 5)) {
2182 c->function = kvm_base + XEN_CPUID_HVM;
2183
2184 if (cpu->xen_vapic) {
2185 c->eax |= XEN_HVM_CPUID_APIC_ACCESS_VIRT;
2186 c->eax |= XEN_HVM_CPUID_X2APIC_VIRT;
2187 }
2188
2189 c->eax |= XEN_HVM_CPUID_IOMMU_MAPPINGS;
2190
2191 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 6)) {
2192 c->eax |= XEN_HVM_CPUID_VCPU_ID_PRESENT;
2193 c->ebx = cs->cpu_index;
2194 }
2195
2196 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 17)) {
2197 c->eax |= XEN_HVM_CPUID_UPCALL_VECTOR;
2198 }
2199 }
2200
2201 r = kvm_xen_init_vcpu(cs);
2202 if (r) {
2203 return r;
2204 }
2205
2206 kvm_base += 0x100;
2207 #else /* CONFIG_XEN_EMU */
2208 /* This should never happen as kvm_arch_init() would have died first. */
2209 fprintf(stderr, "Cannot enable Xen CPUID without Xen support\n");
2210 abort();
2211 #endif
2212 } else if (cpu->expose_kvm) {
2213 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
2214 c = &cpuid_data.entries[cpuid_i++];
2215 c->function = KVM_CPUID_SIGNATURE | kvm_base;
2216 c->eax = KVM_CPUID_FEATURES | kvm_base;
2217 c->ebx = signature[0];
2218 c->ecx = signature[1];
2219 c->edx = signature[2];
2220
2221 c = &cpuid_data.entries[cpuid_i++];
2222 c->function = KVM_CPUID_FEATURES | kvm_base;
2223 c->eax = env->features[FEAT_KVM];
2224 c->edx = env->features[FEAT_KVM_HINTS];
2225 }
2226
2227 if (cpu->kvm_pv_enforce_cpuid) {
2228 r = kvm_vcpu_enable_cap(cs, KVM_CAP_ENFORCE_PV_FEATURE_CPUID, 0, 1);
2229 if (r < 0) {
2230 fprintf(stderr,
2231 "failed to enable KVM_CAP_ENFORCE_PV_FEATURE_CPUID: %s",
2232 strerror(-r));
2233 abort();
2234 }
2235 }
2236
2237 cpuid_i = kvm_x86_build_cpuid(env, cpuid_data.entries, cpuid_i);
2238 cpuid_data.cpuid.nent = cpuid_i;
2239
2240 if (((env->cpuid_version >> 8)&0xF) >= 6
2241 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2242 (CPUID_MCE | CPUID_MCA)) {
2243 uint64_t mcg_cap, unsupported_caps;
2244 int banks;
2245 int ret;
2246
2247 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
2248 if (ret < 0) {
2249 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
2250 return ret;
2251 }
2252
2253 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
2254 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2255 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
2256 return -ENOTSUP;
2257 }
2258
2259 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
2260 if (unsupported_caps) {
2261 if (unsupported_caps & MCG_LMCE_P) {
2262 error_report("kvm: LMCE not supported");
2263 return -ENOTSUP;
2264 }
2265 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
2266 unsupported_caps);
2267 }
2268
2269 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
2270 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
2271 if (ret < 0) {
2272 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
2273 return ret;
2274 }
2275 }
2276
2277 cpu->vmsentry = qemu_add_vm_change_state_handler(cpu_update_state, env);
2278
2279 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
2280 if (c) {
2281 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
2282 !!(c->ecx & CPUID_EXT_SMX);
2283 }
2284
2285 c = cpuid_find_entry(&cpuid_data.cpuid, 7, 0);
2286 if (c && (c->ebx & CPUID_7_0_EBX_SGX)) {
2287 has_msr_feature_control = true;
2288 }
2289
2290 if (env->mcg_cap & MCG_LMCE_P) {
2291 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
2292 }
2293
2294 if (!env->user_tsc_khz) {
2295 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
2296 invtsc_mig_blocker == NULL) {
2297 error_setg(&invtsc_mig_blocker,
2298 "State blocked by non-migratable CPU device"
2299 " (invtsc flag)");
2300 r = migrate_add_blocker(&invtsc_mig_blocker, &local_err);
2301 if (r < 0) {
2302 error_report_err(local_err);
2303 return r;
2304 }
2305 }
2306 }
2307
2308 if (cpu->vmware_cpuid_freq
2309 /* Guests depend on 0x40000000 to detect this feature, so only expose
2310 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
2311 && cpu->expose_kvm
2312 && kvm_base == KVM_CPUID_SIGNATURE
2313 /* TSC clock must be stable and known for this feature. */
2314 && tsc_is_stable_and_known(env)) {
2315
2316 c = &cpuid_data.entries[cpuid_i++];
2317 c->function = KVM_CPUID_SIGNATURE | 0x10;
2318 c->eax = env->tsc_khz;
2319 c->ebx = env->apic_bus_freq / 1000; /* Hz to KHz */
2320 c->ecx = c->edx = 0;
2321
2322 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
2323 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
2324 }
2325
2326 cpuid_data.cpuid.nent = cpuid_i;
2327
2328 cpuid_data.cpuid.padding = 0;
2329 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
2330 if (r) {
2331 goto fail;
2332 }
2333 kvm_init_xsave(env);
2334
2335 max_nested_state_len = kvm_max_nested_state_length();
2336 if (max_nested_state_len > 0) {
2337 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
2338
2339 if (cpu_has_vmx(env) || cpu_has_svm(env)) {
2340 env->nested_state = g_malloc0(max_nested_state_len);
2341 env->nested_state->size = max_nested_state_len;
2342
2343 kvm_init_nested_state(env);
2344 }
2345 }
2346
2347 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
2348
2349 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
2350 has_msr_tsc_aux = false;
2351 }
2352
2353 kvm_init_msrs(cpu);
2354
2355 return 0;
2356
2357 fail:
2358 migrate_del_blocker(&invtsc_mig_blocker);
2359
2360 return r;
2361 }
2362
kvm_arch_destroy_vcpu(CPUState * cs)2363 int kvm_arch_destroy_vcpu(CPUState *cs)
2364 {
2365 X86CPU *cpu = X86_CPU(cs);
2366 CPUX86State *env = &cpu->env;
2367
2368 g_free(env->xsave_buf);
2369
2370 g_free(cpu->kvm_msr_buf);
2371 cpu->kvm_msr_buf = NULL;
2372
2373 g_free(env->nested_state);
2374 env->nested_state = NULL;
2375
2376 qemu_del_vm_change_state_handler(cpu->vmsentry);
2377
2378 return 0;
2379 }
2380
kvm_arch_reset_vcpu(X86CPU * cpu)2381 void kvm_arch_reset_vcpu(X86CPU *cpu)
2382 {
2383 CPUX86State *env = &cpu->env;
2384
2385 env->xcr0 = 1;
2386 if (kvm_irqchip_in_kernel()) {
2387 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
2388 KVM_MP_STATE_UNINITIALIZED;
2389 } else {
2390 env->mp_state = KVM_MP_STATE_RUNNABLE;
2391 }
2392
2393 /* enabled by default */
2394 env->poll_control_msr = 1;
2395
2396 kvm_init_nested_state(env);
2397
2398 sev_es_set_reset_vector(CPU(cpu));
2399 }
2400
kvm_arch_after_reset_vcpu(X86CPU * cpu)2401 void kvm_arch_after_reset_vcpu(X86CPU *cpu)
2402 {
2403 CPUX86State *env = &cpu->env;
2404 int i;
2405
2406 /*
2407 * Reset SynIC after all other devices have been reset to let them remove
2408 * their SINT routes first.
2409 */
2410 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
2411 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
2412 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
2413 }
2414
2415 hyperv_x86_synic_reset(cpu);
2416 }
2417 }
2418
kvm_arch_reset_parked_vcpu(unsigned long vcpu_id,int kvm_fd)2419 void kvm_arch_reset_parked_vcpu(unsigned long vcpu_id, int kvm_fd)
2420 {
2421 g_autofree struct kvm_msrs *msrs = NULL;
2422
2423 msrs = g_malloc0(sizeof(*msrs) + sizeof(msrs->entries[0]));
2424 msrs->entries[0].index = MSR_IA32_TSC;
2425 msrs->entries[0].data = 1; /* match the value in x86_cpu_reset() */
2426 msrs->nmsrs++;
2427
2428 if (ioctl(kvm_fd, KVM_SET_MSRS, msrs) != 1) {
2429 warn_report("parked vCPU %lu TSC reset failed: %d",
2430 vcpu_id, errno);
2431 }
2432 }
2433
kvm_arch_do_init_vcpu(X86CPU * cpu)2434 void kvm_arch_do_init_vcpu(X86CPU *cpu)
2435 {
2436 CPUX86State *env = &cpu->env;
2437
2438 /* APs get directly into wait-for-SIPI state. */
2439 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
2440 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
2441 }
2442 }
2443
kvm_get_supported_feature_msrs(KVMState * s)2444 static int kvm_get_supported_feature_msrs(KVMState *s)
2445 {
2446 int ret = 0;
2447
2448 if (kvm_feature_msrs != NULL) {
2449 return 0;
2450 }
2451
2452 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
2453 return 0;
2454 }
2455
2456 struct kvm_msr_list msr_list;
2457
2458 msr_list.nmsrs = 0;
2459 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
2460 if (ret < 0 && ret != -E2BIG) {
2461 error_report("Fetch KVM feature MSR list failed: %s",
2462 strerror(-ret));
2463 return ret;
2464 }
2465
2466 assert(msr_list.nmsrs > 0);
2467 kvm_feature_msrs = g_malloc0(sizeof(msr_list) +
2468 msr_list.nmsrs * sizeof(msr_list.indices[0]));
2469
2470 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
2471 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
2472
2473 if (ret < 0) {
2474 error_report("Fetch KVM feature MSR list failed: %s",
2475 strerror(-ret));
2476 g_free(kvm_feature_msrs);
2477 kvm_feature_msrs = NULL;
2478 return ret;
2479 }
2480
2481 return 0;
2482 }
2483
kvm_get_supported_msrs(KVMState * s)2484 static int kvm_get_supported_msrs(KVMState *s)
2485 {
2486 int ret = 0;
2487 struct kvm_msr_list msr_list, *kvm_msr_list;
2488
2489 /*
2490 * Obtain MSR list from KVM. These are the MSRs that we must
2491 * save/restore.
2492 */
2493 msr_list.nmsrs = 0;
2494 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
2495 if (ret < 0 && ret != -E2BIG) {
2496 return ret;
2497 }
2498 /*
2499 * Old kernel modules had a bug and could write beyond the provided
2500 * memory. Allocate at least a safe amount of 1K.
2501 */
2502 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
2503 msr_list.nmsrs *
2504 sizeof(msr_list.indices[0])));
2505
2506 kvm_msr_list->nmsrs = msr_list.nmsrs;
2507 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
2508 if (ret >= 0) {
2509 int i;
2510
2511 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
2512 switch (kvm_msr_list->indices[i]) {
2513 case MSR_STAR:
2514 has_msr_star = true;
2515 break;
2516 case MSR_VM_HSAVE_PA:
2517 has_msr_hsave_pa = true;
2518 break;
2519 case MSR_TSC_AUX:
2520 has_msr_tsc_aux = true;
2521 break;
2522 case MSR_TSC_ADJUST:
2523 has_msr_tsc_adjust = true;
2524 break;
2525 case MSR_IA32_TSCDEADLINE:
2526 has_msr_tsc_deadline = true;
2527 break;
2528 case MSR_IA32_SMBASE:
2529 has_msr_smbase = true;
2530 break;
2531 case MSR_SMI_COUNT:
2532 has_msr_smi_count = true;
2533 break;
2534 case MSR_IA32_MISC_ENABLE:
2535 has_msr_misc_enable = true;
2536 break;
2537 case MSR_IA32_BNDCFGS:
2538 has_msr_bndcfgs = true;
2539 break;
2540 case MSR_IA32_XSS:
2541 has_msr_xss = true;
2542 break;
2543 case MSR_IA32_UMWAIT_CONTROL:
2544 has_msr_umwait = true;
2545 break;
2546 case HV_X64_MSR_CRASH_CTL:
2547 has_msr_hv_crash = true;
2548 break;
2549 case HV_X64_MSR_RESET:
2550 has_msr_hv_reset = true;
2551 break;
2552 case HV_X64_MSR_VP_INDEX:
2553 has_msr_hv_vpindex = true;
2554 break;
2555 case HV_X64_MSR_VP_RUNTIME:
2556 has_msr_hv_runtime = true;
2557 break;
2558 case HV_X64_MSR_SCONTROL:
2559 has_msr_hv_synic = true;
2560 break;
2561 case HV_X64_MSR_STIMER0_CONFIG:
2562 has_msr_hv_stimer = true;
2563 break;
2564 case HV_X64_MSR_TSC_FREQUENCY:
2565 has_msr_hv_frequencies = true;
2566 break;
2567 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2568 has_msr_hv_reenlightenment = true;
2569 break;
2570 case HV_X64_MSR_SYNDBG_OPTIONS:
2571 has_msr_hv_syndbg_options = true;
2572 break;
2573 case MSR_IA32_SPEC_CTRL:
2574 has_msr_spec_ctrl = true;
2575 break;
2576 case MSR_AMD64_TSC_RATIO:
2577 has_tsc_scale_msr = true;
2578 break;
2579 case MSR_IA32_TSX_CTRL:
2580 has_msr_tsx_ctrl = true;
2581 break;
2582 case MSR_VIRT_SSBD:
2583 has_msr_virt_ssbd = true;
2584 break;
2585 case MSR_IA32_ARCH_CAPABILITIES:
2586 has_msr_arch_capabs = true;
2587 break;
2588 case MSR_IA32_CORE_CAPABILITY:
2589 has_msr_core_capabs = true;
2590 break;
2591 case MSR_IA32_PERF_CAPABILITIES:
2592 has_msr_perf_capabs = true;
2593 break;
2594 case MSR_IA32_VMX_VMFUNC:
2595 has_msr_vmx_vmfunc = true;
2596 break;
2597 case MSR_IA32_UCODE_REV:
2598 has_msr_ucode_rev = true;
2599 break;
2600 case MSR_IA32_VMX_PROCBASED_CTLS2:
2601 has_msr_vmx_procbased_ctls2 = true;
2602 break;
2603 case MSR_IA32_PKRS:
2604 has_msr_pkrs = true;
2605 break;
2606 case MSR_K7_HWCR:
2607 has_msr_hwcr = true;
2608 }
2609 }
2610 }
2611
2612 g_free(kvm_msr_list);
2613
2614 return ret;
2615 }
2616
kvm_rdmsr_core_thread_count(X86CPU * cpu,uint32_t msr,uint64_t * val)2617 static bool kvm_rdmsr_core_thread_count(X86CPU *cpu,
2618 uint32_t msr,
2619 uint64_t *val)
2620 {
2621 *val = cpu_x86_get_msr_core_thread_count(cpu);
2622
2623 return true;
2624 }
2625
kvm_rdmsr_rapl_power_unit(X86CPU * cpu,uint32_t msr,uint64_t * val)2626 static bool kvm_rdmsr_rapl_power_unit(X86CPU *cpu,
2627 uint32_t msr,
2628 uint64_t *val)
2629 {
2630
2631 CPUState *cs = CPU(cpu);
2632
2633 *val = cs->kvm_state->msr_energy.msr_unit;
2634
2635 return true;
2636 }
2637
kvm_rdmsr_pkg_power_limit(X86CPU * cpu,uint32_t msr,uint64_t * val)2638 static bool kvm_rdmsr_pkg_power_limit(X86CPU *cpu,
2639 uint32_t msr,
2640 uint64_t *val)
2641 {
2642
2643 CPUState *cs = CPU(cpu);
2644
2645 *val = cs->kvm_state->msr_energy.msr_limit;
2646
2647 return true;
2648 }
2649
kvm_rdmsr_pkg_power_info(X86CPU * cpu,uint32_t msr,uint64_t * val)2650 static bool kvm_rdmsr_pkg_power_info(X86CPU *cpu,
2651 uint32_t msr,
2652 uint64_t *val)
2653 {
2654
2655 CPUState *cs = CPU(cpu);
2656
2657 *val = cs->kvm_state->msr_energy.msr_info;
2658
2659 return true;
2660 }
2661
kvm_rdmsr_pkg_energy_status(X86CPU * cpu,uint32_t msr,uint64_t * val)2662 static bool kvm_rdmsr_pkg_energy_status(X86CPU *cpu,
2663 uint32_t msr,
2664 uint64_t *val)
2665 {
2666
2667 CPUState *cs = CPU(cpu);
2668 *val = cs->kvm_state->msr_energy.msr_value[cs->cpu_index];
2669
2670 return true;
2671 }
2672
2673 static Notifier smram_machine_done;
2674 static KVMMemoryListener smram_listener;
2675 static AddressSpace smram_address_space;
2676 static MemoryRegion smram_as_root;
2677 static MemoryRegion smram_as_mem;
2678
register_smram_listener(Notifier * n,void * unused)2679 static void register_smram_listener(Notifier *n, void *unused)
2680 {
2681 MemoryRegion *smram =
2682 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2683
2684 /* Outer container... */
2685 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
2686 memory_region_set_enabled(&smram_as_root, true);
2687
2688 /* ... with two regions inside: normal system memory with low
2689 * priority, and...
2690 */
2691 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
2692 get_system_memory(), 0, ~0ull);
2693 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
2694 memory_region_set_enabled(&smram_as_mem, true);
2695
2696 if (smram) {
2697 /* ... SMRAM with higher priority */
2698 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
2699 memory_region_set_enabled(smram, true);
2700 }
2701
2702 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
2703 kvm_memory_listener_register(kvm_state, &smram_listener,
2704 &smram_address_space, 1, "kvm-smram");
2705 }
2706
kvm_msr_energy_thread(void * data)2707 static void *kvm_msr_energy_thread(void *data)
2708 {
2709 KVMState *s = data;
2710 struct KVMMsrEnergy *vmsr = &s->msr_energy;
2711
2712 g_autofree vmsr_package_energy_stat *pkg_stat = NULL;
2713 g_autofree vmsr_thread_stat *thd_stat = NULL;
2714 g_autofree CPUState *cpu = NULL;
2715 g_autofree unsigned int *vpkgs_energy_stat = NULL;
2716 unsigned int num_threads = 0;
2717
2718 X86CPUTopoIDs topo_ids;
2719
2720 rcu_register_thread();
2721
2722 /* Allocate memory for each package energy status */
2723 pkg_stat = g_new0(vmsr_package_energy_stat, vmsr->host_topo.maxpkgs);
2724
2725 /* Allocate memory for thread stats */
2726 thd_stat = g_new0(vmsr_thread_stat, 1);
2727
2728 /* Allocate memory for holding virtual package energy counter */
2729 vpkgs_energy_stat = g_new0(unsigned int, vmsr->guest_vsockets);
2730
2731 /* Populate the max tick of each packages */
2732 for (int i = 0; i < vmsr->host_topo.maxpkgs; i++) {
2733 /*
2734 * Max numbers of ticks per package
2735 * Time in second * Number of ticks/second * Number of cores/package
2736 * ex: 100 ticks/second/CPU, 12 CPUs per Package gives 1200 ticks max
2737 */
2738 vmsr->host_topo.maxticks[i] = (MSR_ENERGY_THREAD_SLEEP_US / 1000000)
2739 * sysconf(_SC_CLK_TCK)
2740 * vmsr->host_topo.pkg_cpu_count[i];
2741 }
2742
2743 while (true) {
2744 /* Get all qemu threads id */
2745 g_autofree pid_t *thread_ids
2746 = vmsr_get_thread_ids(vmsr->pid, &num_threads);
2747
2748 if (thread_ids == NULL) {
2749 goto clean;
2750 }
2751
2752 thd_stat = g_renew(vmsr_thread_stat, thd_stat, num_threads);
2753 /* Unlike g_new0, g_renew0 function doesn't exist yet... */
2754 memset(thd_stat, 0, num_threads * sizeof(vmsr_thread_stat));
2755
2756 /* Populate all the thread stats */
2757 for (int i = 0; i < num_threads; i++) {
2758 thd_stat[i].utime = g_new0(unsigned long long, 2);
2759 thd_stat[i].stime = g_new0(unsigned long long, 2);
2760 thd_stat[i].thread_id = thread_ids[i];
2761 vmsr_read_thread_stat(vmsr->pid,
2762 thd_stat[i].thread_id,
2763 &thd_stat[i].utime[0],
2764 &thd_stat[i].stime[0],
2765 &thd_stat[i].cpu_id);
2766 thd_stat[i].pkg_id =
2767 vmsr_get_physical_package_id(thd_stat[i].cpu_id);
2768 }
2769
2770 /* Retrieve all packages power plane energy counter */
2771 for (int i = 0; i < vmsr->host_topo.maxpkgs; i++) {
2772 for (int j = 0; j < num_threads; j++) {
2773 /*
2774 * Use the first thread we found that ran on the CPU
2775 * of the package to read the packages energy counter
2776 */
2777 if (thd_stat[j].pkg_id == i) {
2778 pkg_stat[i].e_start =
2779 vmsr_read_msr(MSR_PKG_ENERGY_STATUS,
2780 thd_stat[j].cpu_id,
2781 thd_stat[j].thread_id,
2782 s->msr_energy.sioc);
2783 break;
2784 }
2785 }
2786 }
2787
2788 /* Sleep a short period while the other threads are working */
2789 usleep(MSR_ENERGY_THREAD_SLEEP_US);
2790
2791 /*
2792 * Retrieve all packages power plane energy counter
2793 * Calculate the delta of all packages
2794 */
2795 for (int i = 0; i < vmsr->host_topo.maxpkgs; i++) {
2796 for (int j = 0; j < num_threads; j++) {
2797 /*
2798 * Use the first thread we found that ran on the CPU
2799 * of the package to read the packages energy counter
2800 */
2801 if (thd_stat[j].pkg_id == i) {
2802 pkg_stat[i].e_end =
2803 vmsr_read_msr(MSR_PKG_ENERGY_STATUS,
2804 thd_stat[j].cpu_id,
2805 thd_stat[j].thread_id,
2806 s->msr_energy.sioc);
2807 /*
2808 * Prevent the case we have migrate the VM
2809 * during the sleep period or any other cases
2810 * were energy counter might be lower after
2811 * the sleep period.
2812 */
2813 if (pkg_stat[i].e_end > pkg_stat[i].e_start) {
2814 pkg_stat[i].e_delta =
2815 pkg_stat[i].e_end - pkg_stat[i].e_start;
2816 } else {
2817 pkg_stat[i].e_delta = 0;
2818 }
2819 break;
2820 }
2821 }
2822 }
2823
2824 /* Delta of ticks spend by each thread between the sample */
2825 for (int i = 0; i < num_threads; i++) {
2826 vmsr_read_thread_stat(vmsr->pid,
2827 thd_stat[i].thread_id,
2828 &thd_stat[i].utime[1],
2829 &thd_stat[i].stime[1],
2830 &thd_stat[i].cpu_id);
2831
2832 if (vmsr->pid < 0) {
2833 /*
2834 * We don't count the dead thread
2835 * i.e threads that existed before the sleep
2836 * and not anymore
2837 */
2838 thd_stat[i].delta_ticks = 0;
2839 } else {
2840 vmsr_delta_ticks(thd_stat, i);
2841 }
2842 }
2843
2844 /*
2845 * Identify the vcpu threads
2846 * Calculate the number of vcpu per package
2847 */
2848 CPU_FOREACH(cpu) {
2849 for (int i = 0; i < num_threads; i++) {
2850 if (cpu->thread_id == thd_stat[i].thread_id) {
2851 thd_stat[i].is_vcpu = true;
2852 thd_stat[i].vcpu_id = cpu->cpu_index;
2853 pkg_stat[thd_stat[i].pkg_id].nb_vcpu++;
2854 thd_stat[i].acpi_id = kvm_arch_vcpu_id(cpu);
2855 break;
2856 }
2857 }
2858 }
2859
2860 /* Retrieve the virtual package number of each vCPU */
2861 for (int i = 0; i < vmsr->guest_cpu_list->len; i++) {
2862 for (int j = 0; j < num_threads; j++) {
2863 if ((thd_stat[j].acpi_id ==
2864 vmsr->guest_cpu_list->cpus[i].arch_id)
2865 && (thd_stat[j].is_vcpu == true)) {
2866 x86_topo_ids_from_apicid(thd_stat[j].acpi_id,
2867 &vmsr->guest_topo_info, &topo_ids);
2868 thd_stat[j].vpkg_id = topo_ids.pkg_id;
2869 }
2870 }
2871 }
2872
2873 /* Calculate the total energy of all non-vCPU thread */
2874 for (int i = 0; i < num_threads; i++) {
2875 if ((thd_stat[i].is_vcpu != true) &&
2876 (thd_stat[i].delta_ticks > 0)) {
2877 double temp;
2878 temp = vmsr_get_ratio(pkg_stat[thd_stat[i].pkg_id].e_delta,
2879 thd_stat[i].delta_ticks,
2880 vmsr->host_topo.maxticks[thd_stat[i].pkg_id]);
2881 pkg_stat[thd_stat[i].pkg_id].e_ratio
2882 += (uint64_t)lround(temp);
2883 }
2884 }
2885
2886 /* Calculate the ratio per non-vCPU thread of each package */
2887 for (int i = 0; i < vmsr->host_topo.maxpkgs; i++) {
2888 if (pkg_stat[i].nb_vcpu > 0) {
2889 pkg_stat[i].e_ratio = pkg_stat[i].e_ratio / pkg_stat[i].nb_vcpu;
2890 }
2891 }
2892
2893 /*
2894 * Calculate the energy for each Package:
2895 * Energy Package = sum of each vCPU energy that belongs to the package
2896 */
2897 for (int i = 0; i < num_threads; i++) {
2898 if ((thd_stat[i].is_vcpu == true) && \
2899 (thd_stat[i].delta_ticks > 0)) {
2900 double temp;
2901 temp = vmsr_get_ratio(pkg_stat[thd_stat[i].pkg_id].e_delta,
2902 thd_stat[i].delta_ticks,
2903 vmsr->host_topo.maxticks[thd_stat[i].pkg_id]);
2904 vpkgs_energy_stat[thd_stat[i].vpkg_id] +=
2905 (uint64_t)lround(temp);
2906 vpkgs_energy_stat[thd_stat[i].vpkg_id] +=
2907 pkg_stat[thd_stat[i].pkg_id].e_ratio;
2908 }
2909 }
2910
2911 /*
2912 * Finally populate the vmsr register of each vCPU with the total
2913 * package value to emulate the real hardware where each CPU return the
2914 * value of the package it belongs.
2915 */
2916 for (int i = 0; i < num_threads; i++) {
2917 if ((thd_stat[i].is_vcpu == true) && \
2918 (thd_stat[i].delta_ticks > 0)) {
2919 vmsr->msr_value[thd_stat[i].vcpu_id] = \
2920 vpkgs_energy_stat[thd_stat[i].vpkg_id];
2921 }
2922 }
2923
2924 /* Freeing memory before zeroing the pointer */
2925 for (int i = 0; i < num_threads; i++) {
2926 g_free(thd_stat[i].utime);
2927 g_free(thd_stat[i].stime);
2928 }
2929 }
2930
2931 clean:
2932 rcu_unregister_thread();
2933 return NULL;
2934 }
2935
kvm_msr_energy_thread_init(KVMState * s,MachineState * ms)2936 static int kvm_msr_energy_thread_init(KVMState *s, MachineState *ms)
2937 {
2938 MachineClass *mc = MACHINE_GET_CLASS(ms);
2939 struct KVMMsrEnergy *r = &s->msr_energy;
2940
2941 /*
2942 * Sanity check
2943 * 1. Host cpu must be Intel cpu
2944 * 2. RAPL must be enabled on the Host
2945 */
2946 if (!is_host_cpu_intel()) {
2947 error_report("The RAPL feature can only be enabled on hosts "
2948 "with Intel CPU models");
2949 return -1;
2950 }
2951
2952 if (!is_rapl_enabled()) {
2953 return -1;
2954 }
2955
2956 /* Retrieve the virtual topology */
2957 vmsr_init_topo_info(&r->guest_topo_info, ms);
2958
2959 /* Retrieve the number of vcpu */
2960 r->guest_vcpus = ms->smp.cpus;
2961
2962 /* Retrieve the number of virtual sockets */
2963 r->guest_vsockets = ms->smp.sockets;
2964
2965 /* Allocate register memory (MSR_PKG_STATUS) for each vcpu */
2966 r->msr_value = g_new0(uint64_t, r->guest_vcpus);
2967
2968 /* Retrieve the CPUArchIDlist */
2969 r->guest_cpu_list = mc->possible_cpu_arch_ids(ms);
2970
2971 /* Max number of cpus on the Host */
2972 r->host_topo.maxcpus = vmsr_get_maxcpus();
2973 if (r->host_topo.maxcpus == 0) {
2974 error_report("host max cpus = 0");
2975 return -1;
2976 }
2977
2978 /* Max number of packages on the host */
2979 r->host_topo.maxpkgs = vmsr_get_max_physical_package(r->host_topo.maxcpus);
2980 if (r->host_topo.maxpkgs == 0) {
2981 error_report("host max pkgs = 0");
2982 return -1;
2983 }
2984
2985 /* Allocate memory for each package on the host */
2986 r->host_topo.pkg_cpu_count = g_new0(unsigned int, r->host_topo.maxpkgs);
2987 r->host_topo.maxticks = g_new0(unsigned int, r->host_topo.maxpkgs);
2988
2989 vmsr_count_cpus_per_package(r->host_topo.pkg_cpu_count,
2990 r->host_topo.maxpkgs);
2991 for (int i = 0; i < r->host_topo.maxpkgs; i++) {
2992 if (r->host_topo.pkg_cpu_count[i] == 0) {
2993 error_report("cpu per packages = 0 on package_%d", i);
2994 return -1;
2995 }
2996 }
2997
2998 /* Get QEMU PID*/
2999 r->pid = getpid();
3000
3001 /* Compute the socket path if necessary */
3002 if (s->msr_energy.socket_path == NULL) {
3003 s->msr_energy.socket_path = vmsr_compute_default_paths();
3004 }
3005
3006 /* Open socket with vmsr helper */
3007 s->msr_energy.sioc = vmsr_open_socket(s->msr_energy.socket_path);
3008
3009 if (s->msr_energy.sioc == NULL) {
3010 error_report("vmsr socket opening failed");
3011 return -1;
3012 }
3013
3014 /* Those MSR values should not change */
3015 r->msr_unit = vmsr_read_msr(MSR_RAPL_POWER_UNIT, 0, r->pid,
3016 s->msr_energy.sioc);
3017 r->msr_limit = vmsr_read_msr(MSR_PKG_POWER_LIMIT, 0, r->pid,
3018 s->msr_energy.sioc);
3019 r->msr_info = vmsr_read_msr(MSR_PKG_POWER_INFO, 0, r->pid,
3020 s->msr_energy.sioc);
3021 if (r->msr_unit == 0 || r->msr_limit == 0 || r->msr_info == 0) {
3022 error_report("can't read any virtual msr");
3023 return -1;
3024 }
3025
3026 qemu_thread_create(&r->msr_thr, "kvm-msr",
3027 kvm_msr_energy_thread,
3028 s, QEMU_THREAD_JOINABLE);
3029 return 0;
3030 }
3031
kvm_arch_get_default_type(MachineState * ms)3032 int kvm_arch_get_default_type(MachineState *ms)
3033 {
3034 return 0;
3035 }
3036
kvm_vm_enable_exception_payload(KVMState * s)3037 static int kvm_vm_enable_exception_payload(KVMState *s)
3038 {
3039 int ret = 0;
3040 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD);
3041 if (has_exception_payload) {
3042 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true);
3043 if (ret < 0) {
3044 error_report("kvm: Failed to enable exception payload cap: %s",
3045 strerror(-ret));
3046 }
3047 }
3048
3049 return ret;
3050 }
3051
kvm_vm_enable_triple_fault_event(KVMState * s)3052 static int kvm_vm_enable_triple_fault_event(KVMState *s)
3053 {
3054 int ret = 0;
3055 has_triple_fault_event = \
3056 kvm_check_extension(s,
3057 KVM_CAP_X86_TRIPLE_FAULT_EVENT);
3058 if (has_triple_fault_event) {
3059 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_TRIPLE_FAULT_EVENT, 0, true);
3060 if (ret < 0) {
3061 error_report("kvm: Failed to enable triple fault event cap: %s",
3062 strerror(-ret));
3063 }
3064 }
3065 return ret;
3066 }
3067
kvm_vm_set_identity_map_addr(KVMState * s,uint64_t identity_base)3068 static int kvm_vm_set_identity_map_addr(KVMState *s, uint64_t identity_base)
3069 {
3070 return kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
3071 }
3072
kvm_vm_set_nr_mmu_pages(KVMState * s)3073 static int kvm_vm_set_nr_mmu_pages(KVMState *s)
3074 {
3075 uint64_t shadow_mem;
3076 int ret = 0;
3077 shadow_mem = object_property_get_int(OBJECT(s),
3078 "kvm-shadow-mem",
3079 &error_abort);
3080 if (shadow_mem != -1) {
3081 shadow_mem /= 4096;
3082 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
3083 }
3084 return ret;
3085 }
3086
kvm_vm_set_tss_addr(KVMState * s,uint64_t tss_base)3087 static int kvm_vm_set_tss_addr(KVMState *s, uint64_t tss_base)
3088 {
3089 return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, tss_base);
3090 }
3091
kvm_vm_enable_disable_exits(KVMState * s)3092 static int kvm_vm_enable_disable_exits(KVMState *s)
3093 {
3094 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
3095
3096 if (disable_exits) {
3097 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
3098 KVM_X86_DISABLE_EXITS_HLT |
3099 KVM_X86_DISABLE_EXITS_PAUSE |
3100 KVM_X86_DISABLE_EXITS_CSTATE);
3101 }
3102
3103 return kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
3104 disable_exits);
3105 }
3106
kvm_vm_enable_bus_lock_exit(KVMState * s)3107 static int kvm_vm_enable_bus_lock_exit(KVMState *s)
3108 {
3109 int ret = 0;
3110 ret = kvm_check_extension(s, KVM_CAP_X86_BUS_LOCK_EXIT);
3111 if (!(ret & KVM_BUS_LOCK_DETECTION_EXIT)) {
3112 error_report("kvm: bus lock detection unsupported");
3113 return -ENOTSUP;
3114 }
3115 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_BUS_LOCK_EXIT, 0,
3116 KVM_BUS_LOCK_DETECTION_EXIT);
3117 if (ret < 0) {
3118 error_report("kvm: Failed to enable bus lock detection cap: %s",
3119 strerror(-ret));
3120 }
3121
3122 return ret;
3123 }
3124
kvm_vm_enable_notify_vmexit(KVMState * s)3125 static int kvm_vm_enable_notify_vmexit(KVMState *s)
3126 {
3127 int ret = 0;
3128 if (s->notify_vmexit != NOTIFY_VMEXIT_OPTION_DISABLE) {
3129 uint64_t notify_window_flags =
3130 ((uint64_t)s->notify_window << 32) |
3131 KVM_X86_NOTIFY_VMEXIT_ENABLED |
3132 KVM_X86_NOTIFY_VMEXIT_USER;
3133 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_NOTIFY_VMEXIT, 0,
3134 notify_window_flags);
3135 if (ret < 0) {
3136 error_report("kvm: Failed to enable notify vmexit cap: %s",
3137 strerror(-ret));
3138 }
3139 }
3140 return ret;
3141 }
3142
kvm_vm_enable_userspace_msr(KVMState * s)3143 static int kvm_vm_enable_userspace_msr(KVMState *s)
3144 {
3145 int ret;
3146
3147 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_USER_SPACE_MSR, 0,
3148 KVM_MSR_EXIT_REASON_FILTER);
3149 if (ret < 0) {
3150 error_report("Could not enable user space MSRs: %s",
3151 strerror(-ret));
3152 exit(1);
3153 }
3154
3155 ret = kvm_filter_msr(s, MSR_CORE_THREAD_COUNT,
3156 kvm_rdmsr_core_thread_count, NULL);
3157 if (ret < 0) {
3158 error_report("Could not install MSR_CORE_THREAD_COUNT handler: %s",
3159 strerror(-ret));
3160 exit(1);
3161 }
3162
3163 return 0;
3164 }
3165
kvm_vm_enable_energy_msrs(KVMState * s)3166 static int kvm_vm_enable_energy_msrs(KVMState *s)
3167 {
3168 int ret;
3169
3170 if (s->msr_energy.enable == true) {
3171 ret = kvm_filter_msr(s, MSR_RAPL_POWER_UNIT,
3172 kvm_rdmsr_rapl_power_unit, NULL);
3173 if (ret < 0) {
3174 error_report("Could not install MSR_RAPL_POWER_UNIT handler: %s",
3175 strerror(-ret));
3176 return ret;
3177 }
3178
3179 ret = kvm_filter_msr(s, MSR_PKG_POWER_LIMIT,
3180 kvm_rdmsr_pkg_power_limit, NULL);
3181 if (ret < 0) {
3182 error_report("Could not install MSR_PKG_POWER_LIMIT handler: %s",
3183 strerror(-ret));
3184 return ret;
3185 }
3186
3187 ret = kvm_filter_msr(s, MSR_PKG_POWER_INFO,
3188 kvm_rdmsr_pkg_power_info, NULL);
3189 if (ret < 0) {
3190 error_report("Could not install MSR_PKG_POWER_INFO handler: %s",
3191 strerror(-ret));
3192 return ret;
3193 }
3194 ret = kvm_filter_msr(s, MSR_PKG_ENERGY_STATUS,
3195 kvm_rdmsr_pkg_energy_status, NULL);
3196 if (ret < 0) {
3197 error_report("Could not install MSR_PKG_ENERGY_STATUS handler: %s",
3198 strerror(-ret));
3199 return ret;
3200 }
3201 }
3202 return 0;
3203 }
3204
kvm_arch_init(MachineState * ms,KVMState * s)3205 int kvm_arch_init(MachineState *ms, KVMState *s)
3206 {
3207 int ret;
3208 struct utsname utsname;
3209 Error *local_err = NULL;
3210
3211 /*
3212 * Initialize SEV context, if required
3213 *
3214 * If no memory encryption is requested (ms->cgs == NULL) this is
3215 * a no-op.
3216 *
3217 * It's also a no-op if a non-SEV confidential guest support
3218 * mechanism is selected. SEV is the only mechanism available to
3219 * select on x86 at present, so this doesn't arise, but if new
3220 * mechanisms are supported in future (e.g. TDX), they'll need
3221 * their own initialization either here or elsewhere.
3222 */
3223 if (ms->cgs) {
3224 ret = confidential_guest_kvm_init(ms->cgs, &local_err);
3225 if (ret < 0) {
3226 error_report_err(local_err);
3227 return ret;
3228 }
3229 }
3230
3231 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
3232 has_sregs2 = kvm_check_extension(s, KVM_CAP_SREGS2) > 0;
3233
3234 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
3235
3236 ret = kvm_vm_enable_exception_payload(s);
3237 if (ret < 0) {
3238 return ret;
3239 }
3240
3241 ret = kvm_vm_enable_triple_fault_event(s);
3242 if (ret < 0) {
3243 return ret;
3244 }
3245
3246 if (s->xen_version) {
3247 #ifdef CONFIG_XEN_EMU
3248 if (!object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE)) {
3249 error_report("kvm: Xen support only available in PC machine");
3250 return -ENOTSUP;
3251 }
3252 /* hyperv_enabled() doesn't work yet. */
3253 uint32_t msr = XEN_HYPERCALL_MSR;
3254 ret = kvm_xen_init(s, msr);
3255 if (ret < 0) {
3256 return ret;
3257 }
3258 #else
3259 error_report("kvm: Xen support not enabled in qemu");
3260 return -ENOTSUP;
3261 #endif
3262 }
3263
3264 ret = kvm_get_supported_msrs(s);
3265 if (ret < 0) {
3266 return ret;
3267 }
3268
3269 ret = kvm_get_supported_feature_msrs(s);
3270 if (ret < 0) {
3271 return ret;
3272 }
3273
3274 uname(&utsname);
3275 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
3276
3277 ret = kvm_vm_set_identity_map_addr(s, KVM_IDENTITY_BASE);
3278 if (ret < 0) {
3279 return ret;
3280 }
3281
3282 /* Set TSS base one page after EPT identity map. */
3283 ret = kvm_vm_set_tss_addr(s, KVM_IDENTITY_BASE + 0x1000);
3284 if (ret < 0) {
3285 return ret;
3286 }
3287
3288 /* Tell fw_cfg to notify the BIOS to reserve the range. */
3289 e820_add_entry(KVM_IDENTITY_BASE, 0x4000, E820_RESERVED);
3290
3291 ret = kvm_vm_set_nr_mmu_pages(s);
3292 if (ret < 0) {
3293 return ret;
3294 }
3295
3296 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
3297 object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE) &&
3298 x86_machine_is_smm_enabled(X86_MACHINE(ms))) {
3299 smram_machine_done.notify = register_smram_listener;
3300 qemu_add_machine_init_done_notifier(&smram_machine_done);
3301 }
3302
3303 if (enable_cpu_pm) {
3304 ret = kvm_vm_enable_disable_exits(s);
3305 if (ret < 0) {
3306 error_report("kvm: guest stopping CPU not supported: %s",
3307 strerror(-ret));
3308 return ret;
3309 }
3310 }
3311
3312 if (object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE)) {
3313 X86MachineState *x86ms = X86_MACHINE(ms);
3314
3315 if (x86ms->bus_lock_ratelimit > 0) {
3316 ret = kvm_vm_enable_bus_lock_exit(s);
3317 if (ret < 0) {
3318 return ret;
3319 }
3320 ratelimit_init(&bus_lock_ratelimit_ctrl);
3321 ratelimit_set_speed(&bus_lock_ratelimit_ctrl,
3322 x86ms->bus_lock_ratelimit, BUS_LOCK_SLICE_TIME);
3323 }
3324 }
3325
3326 if (kvm_check_extension(s, KVM_CAP_X86_NOTIFY_VMEXIT)) {
3327 ret = kvm_vm_enable_notify_vmexit(s);
3328 if (ret < 0) {
3329 return ret;
3330 }
3331 }
3332
3333 if (kvm_vm_check_extension(s, KVM_CAP_X86_USER_SPACE_MSR)) {
3334 ret = kvm_vm_enable_userspace_msr(s);
3335 if (ret < 0) {
3336 return ret;
3337 }
3338
3339 if (s->msr_energy.enable == true) {
3340 ret = kvm_vm_enable_energy_msrs(s);
3341 if (ret < 0) {
3342 return ret;
3343 }
3344
3345 ret = kvm_msr_energy_thread_init(s, ms);
3346 if (ret < 0) {
3347 error_report("kvm : error RAPL feature requirement not met");
3348 return ret;
3349 }
3350 }
3351 }
3352
3353 return 0;
3354 }
3355
set_v8086_seg(struct kvm_segment * lhs,const SegmentCache * rhs)3356 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
3357 {
3358 lhs->selector = rhs->selector;
3359 lhs->base = rhs->base;
3360 lhs->limit = rhs->limit;
3361 lhs->type = 3;
3362 lhs->present = 1;
3363 lhs->dpl = 3;
3364 lhs->db = 0;
3365 lhs->s = 1;
3366 lhs->l = 0;
3367 lhs->g = 0;
3368 lhs->avl = 0;
3369 lhs->unusable = 0;
3370 }
3371
set_seg(struct kvm_segment * lhs,const SegmentCache * rhs)3372 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
3373 {
3374 unsigned flags = rhs->flags;
3375 lhs->selector = rhs->selector;
3376 lhs->base = rhs->base;
3377 lhs->limit = rhs->limit;
3378 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
3379 lhs->present = (flags & DESC_P_MASK) != 0;
3380 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
3381 lhs->db = (flags >> DESC_B_SHIFT) & 1;
3382 lhs->s = (flags & DESC_S_MASK) != 0;
3383 lhs->l = (flags >> DESC_L_SHIFT) & 1;
3384 lhs->g = (flags & DESC_G_MASK) != 0;
3385 lhs->avl = (flags & DESC_AVL_MASK) != 0;
3386 lhs->unusable = !lhs->present;
3387 lhs->padding = 0;
3388 }
3389
get_seg(SegmentCache * lhs,const struct kvm_segment * rhs)3390 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
3391 {
3392 lhs->selector = rhs->selector;
3393 lhs->base = rhs->base;
3394 lhs->limit = rhs->limit;
3395 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
3396 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
3397 (rhs->dpl << DESC_DPL_SHIFT) |
3398 (rhs->db << DESC_B_SHIFT) |
3399 (rhs->s * DESC_S_MASK) |
3400 (rhs->l << DESC_L_SHIFT) |
3401 (rhs->g * DESC_G_MASK) |
3402 (rhs->avl * DESC_AVL_MASK);
3403 }
3404
kvm_getput_reg(__u64 * kvm_reg,target_ulong * qemu_reg,int set)3405 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
3406 {
3407 if (set) {
3408 *kvm_reg = *qemu_reg;
3409 } else {
3410 *qemu_reg = *kvm_reg;
3411 }
3412 }
3413
kvm_getput_regs(X86CPU * cpu,int set)3414 static int kvm_getput_regs(X86CPU *cpu, int set)
3415 {
3416 CPUX86State *env = &cpu->env;
3417 struct kvm_regs regs;
3418 int ret = 0;
3419
3420 if (!set) {
3421 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, ®s);
3422 if (ret < 0) {
3423 return ret;
3424 }
3425 }
3426
3427 kvm_getput_reg(®s.rax, &env->regs[R_EAX], set);
3428 kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set);
3429 kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set);
3430 kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set);
3431 kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set);
3432 kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set);
3433 kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set);
3434 kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set);
3435 #ifdef TARGET_X86_64
3436 kvm_getput_reg(®s.r8, &env->regs[8], set);
3437 kvm_getput_reg(®s.r9, &env->regs[9], set);
3438 kvm_getput_reg(®s.r10, &env->regs[10], set);
3439 kvm_getput_reg(®s.r11, &env->regs[11], set);
3440 kvm_getput_reg(®s.r12, &env->regs[12], set);
3441 kvm_getput_reg(®s.r13, &env->regs[13], set);
3442 kvm_getput_reg(®s.r14, &env->regs[14], set);
3443 kvm_getput_reg(®s.r15, &env->regs[15], set);
3444 #endif
3445
3446 kvm_getput_reg(®s.rflags, &env->eflags, set);
3447 kvm_getput_reg(®s.rip, &env->eip, set);
3448
3449 if (set) {
3450 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, ®s);
3451 }
3452
3453 return ret;
3454 }
3455
kvm_put_xsave(X86CPU * cpu)3456 static int kvm_put_xsave(X86CPU *cpu)
3457 {
3458 CPUX86State *env = &cpu->env;
3459 void *xsave = env->xsave_buf;
3460
3461 x86_cpu_xsave_all_areas(cpu, xsave, env->xsave_buf_len);
3462
3463 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
3464 }
3465
kvm_put_xcrs(X86CPU * cpu)3466 static int kvm_put_xcrs(X86CPU *cpu)
3467 {
3468 CPUX86State *env = &cpu->env;
3469 struct kvm_xcrs xcrs = {};
3470
3471 if (!has_xcrs) {
3472 return 0;
3473 }
3474
3475 xcrs.nr_xcrs = 1;
3476 xcrs.flags = 0;
3477 xcrs.xcrs[0].xcr = 0;
3478 xcrs.xcrs[0].value = env->xcr0;
3479 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
3480 }
3481
kvm_put_sregs(X86CPU * cpu)3482 static int kvm_put_sregs(X86CPU *cpu)
3483 {
3484 CPUX86State *env = &cpu->env;
3485 struct kvm_sregs sregs;
3486
3487 /*
3488 * The interrupt_bitmap is ignored because KVM_SET_SREGS is
3489 * always followed by KVM_SET_VCPU_EVENTS.
3490 */
3491 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
3492
3493 if ((env->eflags & VM_MASK)) {
3494 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
3495 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
3496 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
3497 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
3498 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
3499 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
3500 } else {
3501 set_seg(&sregs.cs, &env->segs[R_CS]);
3502 set_seg(&sregs.ds, &env->segs[R_DS]);
3503 set_seg(&sregs.es, &env->segs[R_ES]);
3504 set_seg(&sregs.fs, &env->segs[R_FS]);
3505 set_seg(&sregs.gs, &env->segs[R_GS]);
3506 set_seg(&sregs.ss, &env->segs[R_SS]);
3507 }
3508
3509 set_seg(&sregs.tr, &env->tr);
3510 set_seg(&sregs.ldt, &env->ldt);
3511
3512 sregs.idt.limit = env->idt.limit;
3513 sregs.idt.base = env->idt.base;
3514 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
3515 sregs.gdt.limit = env->gdt.limit;
3516 sregs.gdt.base = env->gdt.base;
3517 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
3518
3519 sregs.cr0 = env->cr[0];
3520 sregs.cr2 = env->cr[2];
3521 sregs.cr3 = env->cr[3];
3522 sregs.cr4 = env->cr[4];
3523
3524 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
3525 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
3526
3527 sregs.efer = env->efer;
3528
3529 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
3530 }
3531
kvm_put_sregs2(X86CPU * cpu)3532 static int kvm_put_sregs2(X86CPU *cpu)
3533 {
3534 CPUX86State *env = &cpu->env;
3535 struct kvm_sregs2 sregs;
3536 int i;
3537
3538 sregs.flags = 0;
3539
3540 if ((env->eflags & VM_MASK)) {
3541 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
3542 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
3543 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
3544 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
3545 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
3546 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
3547 } else {
3548 set_seg(&sregs.cs, &env->segs[R_CS]);
3549 set_seg(&sregs.ds, &env->segs[R_DS]);
3550 set_seg(&sregs.es, &env->segs[R_ES]);
3551 set_seg(&sregs.fs, &env->segs[R_FS]);
3552 set_seg(&sregs.gs, &env->segs[R_GS]);
3553 set_seg(&sregs.ss, &env->segs[R_SS]);
3554 }
3555
3556 set_seg(&sregs.tr, &env->tr);
3557 set_seg(&sregs.ldt, &env->ldt);
3558
3559 sregs.idt.limit = env->idt.limit;
3560 sregs.idt.base = env->idt.base;
3561 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
3562 sregs.gdt.limit = env->gdt.limit;
3563 sregs.gdt.base = env->gdt.base;
3564 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
3565
3566 sregs.cr0 = env->cr[0];
3567 sregs.cr2 = env->cr[2];
3568 sregs.cr3 = env->cr[3];
3569 sregs.cr4 = env->cr[4];
3570
3571 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
3572 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
3573
3574 sregs.efer = env->efer;
3575
3576 if (env->pdptrs_valid) {
3577 for (i = 0; i < 4; i++) {
3578 sregs.pdptrs[i] = env->pdptrs[i];
3579 }
3580 sregs.flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
3581 }
3582
3583 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS2, &sregs);
3584 }
3585
3586
kvm_msr_buf_reset(X86CPU * cpu)3587 static void kvm_msr_buf_reset(X86CPU *cpu)
3588 {
3589 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
3590 }
3591
kvm_msr_entry_add(X86CPU * cpu,uint32_t index,uint64_t value)3592 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
3593 {
3594 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
3595 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
3596 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
3597
3598 assert((void *)(entry + 1) <= limit);
3599
3600 entry->index = index;
3601 entry->reserved = 0;
3602 entry->data = value;
3603 msrs->nmsrs++;
3604 }
3605
kvm_put_one_msr(X86CPU * cpu,int index,uint64_t value)3606 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
3607 {
3608 kvm_msr_buf_reset(cpu);
3609 kvm_msr_entry_add(cpu, index, value);
3610
3611 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
3612 }
3613
kvm_get_one_msr(X86CPU * cpu,int index,uint64_t * value)3614 static int kvm_get_one_msr(X86CPU *cpu, int index, uint64_t *value)
3615 {
3616 int ret;
3617 struct {
3618 struct kvm_msrs info;
3619 struct kvm_msr_entry entries[1];
3620 } msr_data = {
3621 .info.nmsrs = 1,
3622 .entries[0].index = index,
3623 };
3624
3625 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
3626 if (ret < 0) {
3627 return ret;
3628 }
3629 assert(ret == 1);
3630 *value = msr_data.entries[0].data;
3631 return ret;
3632 }
kvm_put_apicbase(X86CPU * cpu,uint64_t value)3633 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
3634 {
3635 int ret;
3636
3637 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
3638 assert(ret == 1);
3639 }
3640
kvm_put_tscdeadline_msr(X86CPU * cpu)3641 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
3642 {
3643 CPUX86State *env = &cpu->env;
3644 int ret;
3645
3646 if (!has_msr_tsc_deadline) {
3647 return 0;
3648 }
3649
3650 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
3651 if (ret < 0) {
3652 return ret;
3653 }
3654
3655 assert(ret == 1);
3656 return 0;
3657 }
3658
3659 /*
3660 * Provide a separate write service for the feature control MSR in order to
3661 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
3662 * before writing any other state because forcibly leaving nested mode
3663 * invalidates the VCPU state.
3664 */
kvm_put_msr_feature_control(X86CPU * cpu)3665 static int kvm_put_msr_feature_control(X86CPU *cpu)
3666 {
3667 int ret;
3668
3669 if (!has_msr_feature_control) {
3670 return 0;
3671 }
3672
3673 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
3674 cpu->env.msr_ia32_feature_control);
3675 if (ret < 0) {
3676 return ret;
3677 }
3678
3679 assert(ret == 1);
3680 return 0;
3681 }
3682
make_vmx_msr_value(uint32_t index,uint32_t features)3683 static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features)
3684 {
3685 uint32_t default1, can_be_one, can_be_zero;
3686 uint32_t must_be_one;
3687
3688 switch (index) {
3689 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3690 default1 = 0x00000016;
3691 break;
3692 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3693 default1 = 0x0401e172;
3694 break;
3695 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3696 default1 = 0x000011ff;
3697 break;
3698 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3699 default1 = 0x00036dff;
3700 break;
3701 case MSR_IA32_VMX_PROCBASED_CTLS2:
3702 default1 = 0;
3703 break;
3704 default:
3705 abort();
3706 }
3707
3708 /* If a feature bit is set, the control can be either set or clear.
3709 * Otherwise the value is limited to either 0 or 1 by default1.
3710 */
3711 can_be_one = features | default1;
3712 can_be_zero = features | ~default1;
3713 must_be_one = ~can_be_zero;
3714
3715 /*
3716 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one).
3717 * Bit 32:63 -> 1 if the control bit can be one.
3718 */
3719 return must_be_one | (((uint64_t)can_be_one) << 32);
3720 }
3721
kvm_msr_entry_add_vmx(X86CPU * cpu,FeatureWordArray f)3722 static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f)
3723 {
3724 uint64_t kvm_vmx_basic =
3725 kvm_arch_get_supported_msr_feature(kvm_state,
3726 MSR_IA32_VMX_BASIC);
3727
3728 if (!kvm_vmx_basic) {
3729 /* If the kernel doesn't support VMX feature (kvm_intel.nested=0),
3730 * then kvm_vmx_basic will be 0 and KVM_SET_MSR will fail.
3731 */
3732 return;
3733 }
3734
3735 uint64_t kvm_vmx_misc =
3736 kvm_arch_get_supported_msr_feature(kvm_state,
3737 MSR_IA32_VMX_MISC);
3738 uint64_t kvm_vmx_ept_vpid =
3739 kvm_arch_get_supported_msr_feature(kvm_state,
3740 MSR_IA32_VMX_EPT_VPID_CAP);
3741
3742 /*
3743 * If the guest is 64-bit, a value of 1 is allowed for the host address
3744 * space size vmexit control.
3745 */
3746 uint64_t fixed_vmx_exit = f[FEAT_8000_0001_EDX] & CPUID_EXT2_LM
3747 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE << 32 : 0;
3748
3749 /*
3750 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should
3751 * not change them for backwards compatibility.
3752 */
3753 uint64_t fixed_vmx_basic = kvm_vmx_basic &
3754 (MSR_VMX_BASIC_VMCS_REVISION_MASK |
3755 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK |
3756 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK);
3757
3758 /*
3759 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can
3760 * change in the future but are always zero for now, clear them to be
3761 * future proof. Bits 32-63 in theory could change, though KVM does
3762 * not support dual-monitor treatment and probably never will; mask
3763 * them out as well.
3764 */
3765 uint64_t fixed_vmx_misc = kvm_vmx_misc &
3766 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK |
3767 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK);
3768
3769 /*
3770 * EPT memory types should not change either, so we do not bother
3771 * adding features for them.
3772 */
3773 uint64_t fixed_vmx_ept_mask =
3774 (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ?
3775 MSR_VMX_EPT_UC | MSR_VMX_EPT_WB : 0);
3776 uint64_t fixed_vmx_ept_vpid = kvm_vmx_ept_vpid & fixed_vmx_ept_mask;
3777
3778 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
3779 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
3780 f[FEAT_VMX_PROCBASED_CTLS]));
3781 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS,
3782 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS,
3783 f[FEAT_VMX_PINBASED_CTLS]));
3784 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_EXIT_CTLS,
3785 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS,
3786 f[FEAT_VMX_EXIT_CTLS]) | fixed_vmx_exit);
3787 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS,
3788 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS,
3789 f[FEAT_VMX_ENTRY_CTLS]));
3790 kvm_msr_entry_add(cpu, MSR_IA32_VMX_PROCBASED_CTLS2,
3791 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2,
3792 f[FEAT_VMX_SECONDARY_CTLS]));
3793 kvm_msr_entry_add(cpu, MSR_IA32_VMX_EPT_VPID_CAP,
3794 f[FEAT_VMX_EPT_VPID_CAPS] | fixed_vmx_ept_vpid);
3795 kvm_msr_entry_add(cpu, MSR_IA32_VMX_BASIC,
3796 f[FEAT_VMX_BASIC] | fixed_vmx_basic);
3797 kvm_msr_entry_add(cpu, MSR_IA32_VMX_MISC,
3798 f[FEAT_VMX_MISC] | fixed_vmx_misc);
3799 if (has_msr_vmx_vmfunc) {
3800 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMFUNC, f[FEAT_VMX_VMFUNC]);
3801 }
3802
3803 /*
3804 * Just to be safe, write these with constant values. The CRn_FIXED1
3805 * MSRs are generated by KVM based on the vCPU's CPUID.
3806 */
3807 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR0_FIXED0,
3808 CR0_PE_MASK | CR0_PG_MASK | CR0_NE_MASK);
3809 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0,
3810 CR4_VMXE_MASK);
3811
3812 if (f[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) {
3813 /* FRED injected-event data (0x2052). */
3814 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x52);
3815 } else if (f[FEAT_VMX_EXIT_CTLS] &
3816 VMX_VM_EXIT_ACTIVATE_SECONDARY_CONTROLS) {
3817 /* Secondary VM-exit controls (0x2044). */
3818 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x44);
3819 } else if (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_TSC_SCALING) {
3820 /* TSC multiplier (0x2032). */
3821 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x32);
3822 } else {
3823 /* Preemption timer (0x482E). */
3824 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x2E);
3825 }
3826 }
3827
kvm_msr_entry_add_perf(X86CPU * cpu,FeatureWordArray f)3828 static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f)
3829 {
3830 uint64_t kvm_perf_cap =
3831 kvm_arch_get_supported_msr_feature(kvm_state,
3832 MSR_IA32_PERF_CAPABILITIES);
3833
3834 if (kvm_perf_cap) {
3835 kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES,
3836 kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]);
3837 }
3838 }
3839
kvm_buf_set_msrs(X86CPU * cpu)3840 static int kvm_buf_set_msrs(X86CPU *cpu)
3841 {
3842 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
3843 if (ret < 0) {
3844 return ret;
3845 }
3846
3847 if (ret < cpu->kvm_msr_buf->nmsrs) {
3848 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3849 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
3850 (uint32_t)e->index, (uint64_t)e->data);
3851 }
3852
3853 assert(ret == cpu->kvm_msr_buf->nmsrs);
3854 return 0;
3855 }
3856
kvm_init_msrs(X86CPU * cpu)3857 static void kvm_init_msrs(X86CPU *cpu)
3858 {
3859 CPUX86State *env = &cpu->env;
3860
3861 kvm_msr_buf_reset(cpu);
3862 if (has_msr_arch_capabs) {
3863 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
3864 env->features[FEAT_ARCH_CAPABILITIES]);
3865 }
3866
3867 if (has_msr_core_capabs) {
3868 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
3869 env->features[FEAT_CORE_CAPABILITY]);
3870 }
3871
3872 if (has_msr_perf_capabs && cpu->enable_pmu) {
3873 kvm_msr_entry_add_perf(cpu, env->features);
3874 }
3875
3876 if (has_msr_ucode_rev) {
3877 kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev);
3878 }
3879
3880 /*
3881 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
3882 * all kernels with MSR features should have them.
3883 */
3884 if (kvm_feature_msrs && cpu_has_vmx(env)) {
3885 kvm_msr_entry_add_vmx(cpu, env->features);
3886 }
3887
3888 assert(kvm_buf_set_msrs(cpu) == 0);
3889 }
3890
kvm_put_msrs(X86CPU * cpu,int level)3891 static int kvm_put_msrs(X86CPU *cpu, int level)
3892 {
3893 CPUX86State *env = &cpu->env;
3894 int i;
3895
3896 kvm_msr_buf_reset(cpu);
3897
3898 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
3899 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
3900 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
3901 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
3902 if (has_msr_star) {
3903 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
3904 }
3905 if (has_msr_hsave_pa) {
3906 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
3907 }
3908 if (has_msr_tsc_aux) {
3909 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
3910 }
3911 if (has_msr_tsc_adjust) {
3912 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
3913 }
3914 if (has_msr_misc_enable) {
3915 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
3916 env->msr_ia32_misc_enable);
3917 }
3918 if (has_msr_smbase) {
3919 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
3920 }
3921 if (has_msr_smi_count) {
3922 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
3923 }
3924 if (has_msr_pkrs) {
3925 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, env->pkrs);
3926 }
3927 if (has_msr_bndcfgs) {
3928 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
3929 }
3930 if (has_msr_xss) {
3931 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
3932 }
3933 if (has_msr_umwait) {
3934 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait);
3935 }
3936 if (has_msr_spec_ctrl) {
3937 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
3938 }
3939 if (has_tsc_scale_msr) {
3940 kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, env->amd_tsc_scale_msr);
3941 }
3942
3943 if (has_msr_tsx_ctrl) {
3944 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl);
3945 }
3946 if (has_msr_virt_ssbd) {
3947 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
3948 }
3949 if (has_msr_hwcr) {
3950 kvm_msr_entry_add(cpu, MSR_K7_HWCR, env->msr_hwcr);
3951 }
3952
3953 #ifdef TARGET_X86_64
3954 if (lm_capable_kernel) {
3955 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
3956 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
3957 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
3958 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
3959 if (env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) {
3960 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP0, env->fred_rsp0);
3961 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP1, env->fred_rsp1);
3962 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP2, env->fred_rsp2);
3963 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP3, env->fred_rsp3);
3964 kvm_msr_entry_add(cpu, MSR_IA32_FRED_STKLVLS, env->fred_stklvls);
3965 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP1, env->fred_ssp1);
3966 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP2, env->fred_ssp2);
3967 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP3, env->fred_ssp3);
3968 kvm_msr_entry_add(cpu, MSR_IA32_FRED_CONFIG, env->fred_config);
3969 }
3970 }
3971 #endif
3972
3973 /*
3974 * The following MSRs have side effects on the guest or are too heavy
3975 * for normal writeback. Limit them to reset or full state updates.
3976 */
3977 if (level >= KVM_PUT_RESET_STATE) {
3978 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
3979 if (env->features[FEAT_KVM] & (CPUID_KVM_CLOCK | CPUID_KVM_CLOCK2)) {
3980 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
3981 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
3982 }
3983 if (env->features[FEAT_KVM] & CPUID_KVM_ASYNCPF_INT) {
3984 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, env->async_pf_int_msr);
3985 }
3986 if (env->features[FEAT_KVM] & CPUID_KVM_ASYNCPF) {
3987 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
3988 }
3989 if (env->features[FEAT_KVM] & CPUID_KVM_PV_EOI) {
3990 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
3991 }
3992 if (env->features[FEAT_KVM] & CPUID_KVM_STEAL_TIME) {
3993 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
3994 }
3995
3996 if (env->features[FEAT_KVM] & CPUID_KVM_POLL_CONTROL) {
3997 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr);
3998 }
3999
4000 if (has_architectural_pmu_version > 0) {
4001 if (has_architectural_pmu_version > 1) {
4002 /* Stop the counter. */
4003 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
4004 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
4005 }
4006
4007 /* Set the counter values. */
4008 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
4009 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
4010 env->msr_fixed_counters[i]);
4011 }
4012 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
4013 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
4014 env->msr_gp_counters[i]);
4015 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
4016 env->msr_gp_evtsel[i]);
4017 }
4018 if (has_architectural_pmu_version > 1) {
4019 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
4020 env->msr_global_status);
4021 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
4022 env->msr_global_ovf_ctrl);
4023
4024 /* Now start the PMU. */
4025 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
4026 env->msr_fixed_ctr_ctrl);
4027 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
4028 env->msr_global_ctrl);
4029 }
4030 }
4031 /*
4032 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
4033 * only sync them to KVM on the first cpu
4034 */
4035 if (current_cpu == first_cpu) {
4036 if (has_msr_hv_hypercall) {
4037 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
4038 env->msr_hv_guest_os_id);
4039 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
4040 env->msr_hv_hypercall);
4041 }
4042 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
4043 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
4044 env->msr_hv_tsc);
4045 }
4046 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
4047 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
4048 env->msr_hv_reenlightenment_control);
4049 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
4050 env->msr_hv_tsc_emulation_control);
4051 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
4052 env->msr_hv_tsc_emulation_status);
4053 }
4054 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG) &&
4055 has_msr_hv_syndbg_options) {
4056 kvm_msr_entry_add(cpu, HV_X64_MSR_SYNDBG_OPTIONS,
4057 hyperv_syndbg_query_options());
4058 }
4059 }
4060 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
4061 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
4062 env->msr_hv_vapic);
4063 }
4064 if (has_msr_hv_crash) {
4065 int j;
4066
4067 for (j = 0; j < HV_CRASH_PARAMS; j++)
4068 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
4069 env->msr_hv_crash_params[j]);
4070
4071 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
4072 }
4073 if (has_msr_hv_runtime) {
4074 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
4075 }
4076 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
4077 && hv_vpindex_settable) {
4078 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
4079 hyperv_vp_index(CPU(cpu)));
4080 }
4081 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
4082 int j;
4083
4084 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
4085
4086 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
4087 env->msr_hv_synic_control);
4088 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
4089 env->msr_hv_synic_evt_page);
4090 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
4091 env->msr_hv_synic_msg_page);
4092
4093 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
4094 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
4095 env->msr_hv_synic_sint[j]);
4096 }
4097 }
4098 if (has_msr_hv_stimer) {
4099 int j;
4100
4101 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
4102 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
4103 env->msr_hv_stimer_config[j]);
4104 }
4105
4106 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
4107 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
4108 env->msr_hv_stimer_count[j]);
4109 }
4110 }
4111 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
4112 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
4113
4114 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
4115 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
4116 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
4117 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
4118 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
4119 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
4120 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
4121 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
4122 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
4123 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
4124 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
4125 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
4126 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
4127 /* The CPU GPs if we write to a bit above the physical limit of
4128 * the host CPU (and KVM emulates that)
4129 */
4130 uint64_t mask = env->mtrr_var[i].mask;
4131 mask &= phys_mask;
4132
4133 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
4134 env->mtrr_var[i].base);
4135 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
4136 }
4137 }
4138 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
4139 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
4140 0x14, 1, R_EAX) & 0x7;
4141
4142 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
4143 env->msr_rtit_ctrl);
4144 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
4145 env->msr_rtit_status);
4146 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
4147 env->msr_rtit_output_base);
4148 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
4149 env->msr_rtit_output_mask);
4150 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
4151 env->msr_rtit_cr3_match);
4152 for (i = 0; i < addr_num; i++) {
4153 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
4154 env->msr_rtit_addrs[i]);
4155 }
4156 }
4157
4158 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) {
4159 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0,
4160 env->msr_ia32_sgxlepubkeyhash[0]);
4161 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1,
4162 env->msr_ia32_sgxlepubkeyhash[1]);
4163 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2,
4164 env->msr_ia32_sgxlepubkeyhash[2]);
4165 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3,
4166 env->msr_ia32_sgxlepubkeyhash[3]);
4167 }
4168
4169 if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
4170 kvm_msr_entry_add(cpu, MSR_IA32_XFD,
4171 env->msr_xfd);
4172 kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR,
4173 env->msr_xfd_err);
4174 }
4175
4176 if (kvm_enabled() && cpu->enable_pmu &&
4177 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
4178 uint64_t depth;
4179 int ret;
4180
4181 /*
4182 * Only migrate Arch LBR states when the host Arch LBR depth
4183 * equals that of source guest's, this is to avoid mismatch
4184 * of guest/host config for the msr hence avoid unexpected
4185 * misbehavior.
4186 */
4187 ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth);
4188
4189 if (ret == 1 && !!depth && depth == env->msr_lbr_depth) {
4190 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_CTL, env->msr_lbr_ctl);
4191 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_DEPTH, env->msr_lbr_depth);
4192
4193 for (i = 0; i < ARCH_LBR_NR_ENTRIES; i++) {
4194 if (!env->lbr_records[i].from) {
4195 continue;
4196 }
4197 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_FROM_0 + i,
4198 env->lbr_records[i].from);
4199 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_TO_0 + i,
4200 env->lbr_records[i].to);
4201 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_INFO_0 + i,
4202 env->lbr_records[i].info);
4203 }
4204 }
4205 }
4206
4207 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
4208 * kvm_put_msr_feature_control. */
4209 }
4210
4211 if (env->mcg_cap) {
4212 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
4213 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
4214 if (has_msr_mcg_ext_ctl) {
4215 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
4216 }
4217 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
4218 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
4219 }
4220 }
4221
4222 return kvm_buf_set_msrs(cpu);
4223 }
4224
4225
kvm_get_xsave(X86CPU * cpu)4226 static int kvm_get_xsave(X86CPU *cpu)
4227 {
4228 CPUX86State *env = &cpu->env;
4229 void *xsave = env->xsave_buf;
4230 unsigned long type;
4231 int ret;
4232
4233 type = has_xsave2 ? KVM_GET_XSAVE2 : KVM_GET_XSAVE;
4234 ret = kvm_vcpu_ioctl(CPU(cpu), type, xsave);
4235 if (ret < 0) {
4236 return ret;
4237 }
4238 x86_cpu_xrstor_all_areas(cpu, xsave, env->xsave_buf_len);
4239
4240 return 0;
4241 }
4242
kvm_get_xcrs(X86CPU * cpu)4243 static int kvm_get_xcrs(X86CPU *cpu)
4244 {
4245 CPUX86State *env = &cpu->env;
4246 int i, ret;
4247 struct kvm_xcrs xcrs;
4248
4249 if (!has_xcrs) {
4250 return 0;
4251 }
4252
4253 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
4254 if (ret < 0) {
4255 return ret;
4256 }
4257
4258 for (i = 0; i < xcrs.nr_xcrs; i++) {
4259 /* Only support xcr0 now */
4260 if (xcrs.xcrs[i].xcr == 0) {
4261 env->xcr0 = xcrs.xcrs[i].value;
4262 break;
4263 }
4264 }
4265 return 0;
4266 }
4267
kvm_get_sregs(X86CPU * cpu)4268 static int kvm_get_sregs(X86CPU *cpu)
4269 {
4270 CPUX86State *env = &cpu->env;
4271 struct kvm_sregs sregs;
4272 int ret;
4273
4274 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
4275 if (ret < 0) {
4276 return ret;
4277 }
4278
4279 /*
4280 * The interrupt_bitmap is ignored because KVM_GET_SREGS is
4281 * always preceded by KVM_GET_VCPU_EVENTS.
4282 */
4283
4284 get_seg(&env->segs[R_CS], &sregs.cs);
4285 get_seg(&env->segs[R_DS], &sregs.ds);
4286 get_seg(&env->segs[R_ES], &sregs.es);
4287 get_seg(&env->segs[R_FS], &sregs.fs);
4288 get_seg(&env->segs[R_GS], &sregs.gs);
4289 get_seg(&env->segs[R_SS], &sregs.ss);
4290
4291 get_seg(&env->tr, &sregs.tr);
4292 get_seg(&env->ldt, &sregs.ldt);
4293
4294 env->idt.limit = sregs.idt.limit;
4295 env->idt.base = sregs.idt.base;
4296 env->gdt.limit = sregs.gdt.limit;
4297 env->gdt.base = sregs.gdt.base;
4298
4299 env->cr[0] = sregs.cr0;
4300 env->cr[2] = sregs.cr2;
4301 env->cr[3] = sregs.cr3;
4302 env->cr[4] = sregs.cr4;
4303
4304 env->efer = sregs.efer;
4305 if (sev_es_enabled() && env->efer & MSR_EFER_LME &&
4306 env->cr[0] & CR0_PG_MASK) {
4307 env->efer |= MSR_EFER_LMA;
4308 }
4309
4310 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
4311 x86_update_hflags(env);
4312
4313 return 0;
4314 }
4315
kvm_get_sregs2(X86CPU * cpu)4316 static int kvm_get_sregs2(X86CPU *cpu)
4317 {
4318 CPUX86State *env = &cpu->env;
4319 struct kvm_sregs2 sregs;
4320 int i, ret;
4321
4322 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS2, &sregs);
4323 if (ret < 0) {
4324 return ret;
4325 }
4326
4327 get_seg(&env->segs[R_CS], &sregs.cs);
4328 get_seg(&env->segs[R_DS], &sregs.ds);
4329 get_seg(&env->segs[R_ES], &sregs.es);
4330 get_seg(&env->segs[R_FS], &sregs.fs);
4331 get_seg(&env->segs[R_GS], &sregs.gs);
4332 get_seg(&env->segs[R_SS], &sregs.ss);
4333
4334 get_seg(&env->tr, &sregs.tr);
4335 get_seg(&env->ldt, &sregs.ldt);
4336
4337 env->idt.limit = sregs.idt.limit;
4338 env->idt.base = sregs.idt.base;
4339 env->gdt.limit = sregs.gdt.limit;
4340 env->gdt.base = sregs.gdt.base;
4341
4342 env->cr[0] = sregs.cr0;
4343 env->cr[2] = sregs.cr2;
4344 env->cr[3] = sregs.cr3;
4345 env->cr[4] = sregs.cr4;
4346
4347 env->efer = sregs.efer;
4348 if (sev_es_enabled() && env->efer & MSR_EFER_LME &&
4349 env->cr[0] & CR0_PG_MASK) {
4350 env->efer |= MSR_EFER_LMA;
4351 }
4352
4353 env->pdptrs_valid = sregs.flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
4354
4355 if (env->pdptrs_valid) {
4356 for (i = 0; i < 4; i++) {
4357 env->pdptrs[i] = sregs.pdptrs[i];
4358 }
4359 }
4360
4361 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
4362 x86_update_hflags(env);
4363
4364 return 0;
4365 }
4366
kvm_get_msrs(X86CPU * cpu)4367 static int kvm_get_msrs(X86CPU *cpu)
4368 {
4369 CPUX86State *env = &cpu->env;
4370 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
4371 int ret, i;
4372 uint64_t mtrr_top_bits;
4373
4374 kvm_msr_buf_reset(cpu);
4375
4376 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
4377 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
4378 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
4379 kvm_msr_entry_add(cpu, MSR_PAT, 0);
4380 if (has_msr_star) {
4381 kvm_msr_entry_add(cpu, MSR_STAR, 0);
4382 }
4383 if (has_msr_hsave_pa) {
4384 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
4385 }
4386 if (has_msr_tsc_aux) {
4387 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
4388 }
4389 if (has_msr_tsc_adjust) {
4390 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
4391 }
4392 if (has_msr_tsc_deadline) {
4393 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
4394 }
4395 if (has_msr_misc_enable) {
4396 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
4397 }
4398 if (has_msr_smbase) {
4399 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
4400 }
4401 if (has_msr_smi_count) {
4402 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
4403 }
4404 if (has_msr_feature_control) {
4405 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
4406 }
4407 if (has_msr_pkrs) {
4408 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, 0);
4409 }
4410 if (has_msr_bndcfgs) {
4411 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
4412 }
4413 if (has_msr_xss) {
4414 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
4415 }
4416 if (has_msr_umwait) {
4417 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0);
4418 }
4419 if (has_msr_spec_ctrl) {
4420 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
4421 }
4422 if (has_tsc_scale_msr) {
4423 kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, 0);
4424 }
4425
4426 if (has_msr_tsx_ctrl) {
4427 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0);
4428 }
4429 if (has_msr_virt_ssbd) {
4430 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
4431 }
4432 if (!env->tsc_valid) {
4433 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
4434 env->tsc_valid = !runstate_is_running();
4435 }
4436 if (has_msr_hwcr) {
4437 kvm_msr_entry_add(cpu, MSR_K7_HWCR, 0);
4438 }
4439
4440 #ifdef TARGET_X86_64
4441 if (lm_capable_kernel) {
4442 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
4443 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
4444 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
4445 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
4446 if (env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) {
4447 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP0, 0);
4448 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP1, 0);
4449 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP2, 0);
4450 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP3, 0);
4451 kvm_msr_entry_add(cpu, MSR_IA32_FRED_STKLVLS, 0);
4452 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP1, 0);
4453 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP2, 0);
4454 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP3, 0);
4455 kvm_msr_entry_add(cpu, MSR_IA32_FRED_CONFIG, 0);
4456 }
4457 }
4458 #endif
4459 if (env->features[FEAT_KVM] & (CPUID_KVM_CLOCK | CPUID_KVM_CLOCK2)) {
4460 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
4461 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
4462 }
4463 if (env->features[FEAT_KVM] & CPUID_KVM_ASYNCPF_INT) {
4464 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, 0);
4465 }
4466 if (env->features[FEAT_KVM] & CPUID_KVM_ASYNCPF) {
4467 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
4468 }
4469 if (env->features[FEAT_KVM] & CPUID_KVM_PV_EOI) {
4470 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
4471 }
4472 if (env->features[FEAT_KVM] & CPUID_KVM_STEAL_TIME) {
4473 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
4474 }
4475 if (env->features[FEAT_KVM] & CPUID_KVM_POLL_CONTROL) {
4476 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1);
4477 }
4478 if (has_architectural_pmu_version > 0) {
4479 if (has_architectural_pmu_version > 1) {
4480 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
4481 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
4482 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
4483 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
4484 }
4485 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
4486 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
4487 }
4488 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
4489 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
4490 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
4491 }
4492 }
4493
4494 if (env->mcg_cap) {
4495 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
4496 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
4497 if (has_msr_mcg_ext_ctl) {
4498 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
4499 }
4500 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
4501 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
4502 }
4503 }
4504
4505 if (has_msr_hv_hypercall) {
4506 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
4507 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
4508 }
4509 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
4510 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
4511 }
4512 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
4513 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
4514 }
4515 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
4516 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
4517 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
4518 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
4519 }
4520 if (has_msr_hv_syndbg_options) {
4521 kvm_msr_entry_add(cpu, HV_X64_MSR_SYNDBG_OPTIONS, 0);
4522 }
4523 if (has_msr_hv_crash) {
4524 int j;
4525
4526 for (j = 0; j < HV_CRASH_PARAMS; j++) {
4527 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
4528 }
4529 }
4530 if (has_msr_hv_runtime) {
4531 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
4532 }
4533 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
4534 uint32_t msr;
4535
4536 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
4537 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
4538 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
4539 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
4540 kvm_msr_entry_add(cpu, msr, 0);
4541 }
4542 }
4543 if (has_msr_hv_stimer) {
4544 uint32_t msr;
4545
4546 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
4547 msr++) {
4548 kvm_msr_entry_add(cpu, msr, 0);
4549 }
4550 }
4551 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
4552 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
4553 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
4554 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
4555 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
4556 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
4557 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
4558 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
4559 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
4560 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
4561 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
4562 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
4563 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
4564 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
4565 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
4566 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
4567 }
4568 }
4569
4570 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
4571 int addr_num =
4572 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
4573
4574 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
4575 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
4576 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
4577 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
4578 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
4579 for (i = 0; i < addr_num; i++) {
4580 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
4581 }
4582 }
4583
4584 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) {
4585 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0, 0);
4586 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1, 0);
4587 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2, 0);
4588 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 0);
4589 }
4590
4591 if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
4592 kvm_msr_entry_add(cpu, MSR_IA32_XFD, 0);
4593 kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, 0);
4594 }
4595
4596 if (kvm_enabled() && cpu->enable_pmu &&
4597 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
4598 uint64_t depth;
4599
4600 ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth);
4601 if (ret == 1 && depth == ARCH_LBR_NR_ENTRIES) {
4602 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_CTL, 0);
4603 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_DEPTH, 0);
4604
4605 for (i = 0; i < ARCH_LBR_NR_ENTRIES; i++) {
4606 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_FROM_0 + i, 0);
4607 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_TO_0 + i, 0);
4608 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_INFO_0 + i, 0);
4609 }
4610 }
4611 }
4612
4613 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
4614 if (ret < 0) {
4615 return ret;
4616 }
4617
4618 if (ret < cpu->kvm_msr_buf->nmsrs) {
4619 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
4620 error_report("error: failed to get MSR 0x%" PRIx32,
4621 (uint32_t)e->index);
4622 }
4623
4624 assert(ret == cpu->kvm_msr_buf->nmsrs);
4625 /*
4626 * MTRR masks: Each mask consists of 5 parts
4627 * a 10..0: must be zero
4628 * b 11 : valid bit
4629 * c n-1.12: actual mask bits
4630 * d 51..n: reserved must be zero
4631 * e 63.52: reserved must be zero
4632 *
4633 * 'n' is the number of physical bits supported by the CPU and is
4634 * apparently always <= 52. We know our 'n' but don't know what
4635 * the destinations 'n' is; it might be smaller, in which case
4636 * it masks (c) on loading. It might be larger, in which case
4637 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
4638 * we're migrating to.
4639 */
4640
4641 if (cpu->fill_mtrr_mask) {
4642 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
4643 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
4644 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
4645 } else {
4646 mtrr_top_bits = 0;
4647 }
4648
4649 for (i = 0; i < ret; i++) {
4650 uint32_t index = msrs[i].index;
4651 switch (index) {
4652 case MSR_IA32_SYSENTER_CS:
4653 env->sysenter_cs = msrs[i].data;
4654 break;
4655 case MSR_IA32_SYSENTER_ESP:
4656 env->sysenter_esp = msrs[i].data;
4657 break;
4658 case MSR_IA32_SYSENTER_EIP:
4659 env->sysenter_eip = msrs[i].data;
4660 break;
4661 case MSR_PAT:
4662 env->pat = msrs[i].data;
4663 break;
4664 case MSR_STAR:
4665 env->star = msrs[i].data;
4666 break;
4667 #ifdef TARGET_X86_64
4668 case MSR_CSTAR:
4669 env->cstar = msrs[i].data;
4670 break;
4671 case MSR_KERNELGSBASE:
4672 env->kernelgsbase = msrs[i].data;
4673 break;
4674 case MSR_FMASK:
4675 env->fmask = msrs[i].data;
4676 break;
4677 case MSR_LSTAR:
4678 env->lstar = msrs[i].data;
4679 break;
4680 case MSR_IA32_FRED_RSP0:
4681 env->fred_rsp0 = msrs[i].data;
4682 break;
4683 case MSR_IA32_FRED_RSP1:
4684 env->fred_rsp1 = msrs[i].data;
4685 break;
4686 case MSR_IA32_FRED_RSP2:
4687 env->fred_rsp2 = msrs[i].data;
4688 break;
4689 case MSR_IA32_FRED_RSP3:
4690 env->fred_rsp3 = msrs[i].data;
4691 break;
4692 case MSR_IA32_FRED_STKLVLS:
4693 env->fred_stklvls = msrs[i].data;
4694 break;
4695 case MSR_IA32_FRED_SSP1:
4696 env->fred_ssp1 = msrs[i].data;
4697 break;
4698 case MSR_IA32_FRED_SSP2:
4699 env->fred_ssp2 = msrs[i].data;
4700 break;
4701 case MSR_IA32_FRED_SSP3:
4702 env->fred_ssp3 = msrs[i].data;
4703 break;
4704 case MSR_IA32_FRED_CONFIG:
4705 env->fred_config = msrs[i].data;
4706 break;
4707 #endif
4708 case MSR_IA32_TSC:
4709 env->tsc = msrs[i].data;
4710 break;
4711 case MSR_TSC_AUX:
4712 env->tsc_aux = msrs[i].data;
4713 break;
4714 case MSR_TSC_ADJUST:
4715 env->tsc_adjust = msrs[i].data;
4716 break;
4717 case MSR_IA32_TSCDEADLINE:
4718 env->tsc_deadline = msrs[i].data;
4719 break;
4720 case MSR_VM_HSAVE_PA:
4721 env->vm_hsave = msrs[i].data;
4722 break;
4723 case MSR_KVM_SYSTEM_TIME:
4724 env->system_time_msr = msrs[i].data;
4725 break;
4726 case MSR_KVM_WALL_CLOCK:
4727 env->wall_clock_msr = msrs[i].data;
4728 break;
4729 case MSR_MCG_STATUS:
4730 env->mcg_status = msrs[i].data;
4731 break;
4732 case MSR_MCG_CTL:
4733 env->mcg_ctl = msrs[i].data;
4734 break;
4735 case MSR_MCG_EXT_CTL:
4736 env->mcg_ext_ctl = msrs[i].data;
4737 break;
4738 case MSR_IA32_MISC_ENABLE:
4739 env->msr_ia32_misc_enable = msrs[i].data;
4740 break;
4741 case MSR_IA32_SMBASE:
4742 env->smbase = msrs[i].data;
4743 break;
4744 case MSR_SMI_COUNT:
4745 env->msr_smi_count = msrs[i].data;
4746 break;
4747 case MSR_IA32_FEATURE_CONTROL:
4748 env->msr_ia32_feature_control = msrs[i].data;
4749 break;
4750 case MSR_IA32_BNDCFGS:
4751 env->msr_bndcfgs = msrs[i].data;
4752 break;
4753 case MSR_IA32_XSS:
4754 env->xss = msrs[i].data;
4755 break;
4756 case MSR_IA32_UMWAIT_CONTROL:
4757 env->umwait = msrs[i].data;
4758 break;
4759 case MSR_IA32_PKRS:
4760 env->pkrs = msrs[i].data;
4761 break;
4762 default:
4763 if (msrs[i].index >= MSR_MC0_CTL &&
4764 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
4765 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
4766 }
4767 break;
4768 case MSR_KVM_ASYNC_PF_EN:
4769 env->async_pf_en_msr = msrs[i].data;
4770 break;
4771 case MSR_KVM_ASYNC_PF_INT:
4772 env->async_pf_int_msr = msrs[i].data;
4773 break;
4774 case MSR_KVM_PV_EOI_EN:
4775 env->pv_eoi_en_msr = msrs[i].data;
4776 break;
4777 case MSR_KVM_STEAL_TIME:
4778 env->steal_time_msr = msrs[i].data;
4779 break;
4780 case MSR_KVM_POLL_CONTROL: {
4781 env->poll_control_msr = msrs[i].data;
4782 break;
4783 }
4784 case MSR_CORE_PERF_FIXED_CTR_CTRL:
4785 env->msr_fixed_ctr_ctrl = msrs[i].data;
4786 break;
4787 case MSR_CORE_PERF_GLOBAL_CTRL:
4788 env->msr_global_ctrl = msrs[i].data;
4789 break;
4790 case MSR_CORE_PERF_GLOBAL_STATUS:
4791 env->msr_global_status = msrs[i].data;
4792 break;
4793 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
4794 env->msr_global_ovf_ctrl = msrs[i].data;
4795 break;
4796 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
4797 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
4798 break;
4799 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
4800 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
4801 break;
4802 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
4803 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
4804 break;
4805 case HV_X64_MSR_HYPERCALL:
4806 env->msr_hv_hypercall = msrs[i].data;
4807 break;
4808 case HV_X64_MSR_GUEST_OS_ID:
4809 env->msr_hv_guest_os_id = msrs[i].data;
4810 break;
4811 case HV_X64_MSR_APIC_ASSIST_PAGE:
4812 env->msr_hv_vapic = msrs[i].data;
4813 break;
4814 case HV_X64_MSR_REFERENCE_TSC:
4815 env->msr_hv_tsc = msrs[i].data;
4816 break;
4817 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4818 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
4819 break;
4820 case HV_X64_MSR_VP_RUNTIME:
4821 env->msr_hv_runtime = msrs[i].data;
4822 break;
4823 case HV_X64_MSR_SCONTROL:
4824 env->msr_hv_synic_control = msrs[i].data;
4825 break;
4826 case HV_X64_MSR_SIEFP:
4827 env->msr_hv_synic_evt_page = msrs[i].data;
4828 break;
4829 case HV_X64_MSR_SIMP:
4830 env->msr_hv_synic_msg_page = msrs[i].data;
4831 break;
4832 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
4833 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
4834 break;
4835 case HV_X64_MSR_STIMER0_CONFIG:
4836 case HV_X64_MSR_STIMER1_CONFIG:
4837 case HV_X64_MSR_STIMER2_CONFIG:
4838 case HV_X64_MSR_STIMER3_CONFIG:
4839 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
4840 msrs[i].data;
4841 break;
4842 case HV_X64_MSR_STIMER0_COUNT:
4843 case HV_X64_MSR_STIMER1_COUNT:
4844 case HV_X64_MSR_STIMER2_COUNT:
4845 case HV_X64_MSR_STIMER3_COUNT:
4846 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
4847 msrs[i].data;
4848 break;
4849 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4850 env->msr_hv_reenlightenment_control = msrs[i].data;
4851 break;
4852 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4853 env->msr_hv_tsc_emulation_control = msrs[i].data;
4854 break;
4855 case HV_X64_MSR_TSC_EMULATION_STATUS:
4856 env->msr_hv_tsc_emulation_status = msrs[i].data;
4857 break;
4858 case HV_X64_MSR_SYNDBG_OPTIONS:
4859 env->msr_hv_syndbg_options = msrs[i].data;
4860 break;
4861 case MSR_MTRRdefType:
4862 env->mtrr_deftype = msrs[i].data;
4863 break;
4864 case MSR_MTRRfix64K_00000:
4865 env->mtrr_fixed[0] = msrs[i].data;
4866 break;
4867 case MSR_MTRRfix16K_80000:
4868 env->mtrr_fixed[1] = msrs[i].data;
4869 break;
4870 case MSR_MTRRfix16K_A0000:
4871 env->mtrr_fixed[2] = msrs[i].data;
4872 break;
4873 case MSR_MTRRfix4K_C0000:
4874 env->mtrr_fixed[3] = msrs[i].data;
4875 break;
4876 case MSR_MTRRfix4K_C8000:
4877 env->mtrr_fixed[4] = msrs[i].data;
4878 break;
4879 case MSR_MTRRfix4K_D0000:
4880 env->mtrr_fixed[5] = msrs[i].data;
4881 break;
4882 case MSR_MTRRfix4K_D8000:
4883 env->mtrr_fixed[6] = msrs[i].data;
4884 break;
4885 case MSR_MTRRfix4K_E0000:
4886 env->mtrr_fixed[7] = msrs[i].data;
4887 break;
4888 case MSR_MTRRfix4K_E8000:
4889 env->mtrr_fixed[8] = msrs[i].data;
4890 break;
4891 case MSR_MTRRfix4K_F0000:
4892 env->mtrr_fixed[9] = msrs[i].data;
4893 break;
4894 case MSR_MTRRfix4K_F8000:
4895 env->mtrr_fixed[10] = msrs[i].data;
4896 break;
4897 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
4898 if (index & 1) {
4899 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
4900 mtrr_top_bits;
4901 } else {
4902 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
4903 }
4904 break;
4905 case MSR_IA32_SPEC_CTRL:
4906 env->spec_ctrl = msrs[i].data;
4907 break;
4908 case MSR_AMD64_TSC_RATIO:
4909 env->amd_tsc_scale_msr = msrs[i].data;
4910 break;
4911 case MSR_IA32_TSX_CTRL:
4912 env->tsx_ctrl = msrs[i].data;
4913 break;
4914 case MSR_VIRT_SSBD:
4915 env->virt_ssbd = msrs[i].data;
4916 break;
4917 case MSR_IA32_RTIT_CTL:
4918 env->msr_rtit_ctrl = msrs[i].data;
4919 break;
4920 case MSR_IA32_RTIT_STATUS:
4921 env->msr_rtit_status = msrs[i].data;
4922 break;
4923 case MSR_IA32_RTIT_OUTPUT_BASE:
4924 env->msr_rtit_output_base = msrs[i].data;
4925 break;
4926 case MSR_IA32_RTIT_OUTPUT_MASK:
4927 env->msr_rtit_output_mask = msrs[i].data;
4928 break;
4929 case MSR_IA32_RTIT_CR3_MATCH:
4930 env->msr_rtit_cr3_match = msrs[i].data;
4931 break;
4932 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
4933 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
4934 break;
4935 case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
4936 env->msr_ia32_sgxlepubkeyhash[index - MSR_IA32_SGXLEPUBKEYHASH0] =
4937 msrs[i].data;
4938 break;
4939 case MSR_IA32_XFD:
4940 env->msr_xfd = msrs[i].data;
4941 break;
4942 case MSR_IA32_XFD_ERR:
4943 env->msr_xfd_err = msrs[i].data;
4944 break;
4945 case MSR_ARCH_LBR_CTL:
4946 env->msr_lbr_ctl = msrs[i].data;
4947 break;
4948 case MSR_ARCH_LBR_DEPTH:
4949 env->msr_lbr_depth = msrs[i].data;
4950 break;
4951 case MSR_ARCH_LBR_FROM_0 ... MSR_ARCH_LBR_FROM_0 + 31:
4952 env->lbr_records[index - MSR_ARCH_LBR_FROM_0].from = msrs[i].data;
4953 break;
4954 case MSR_ARCH_LBR_TO_0 ... MSR_ARCH_LBR_TO_0 + 31:
4955 env->lbr_records[index - MSR_ARCH_LBR_TO_0].to = msrs[i].data;
4956 break;
4957 case MSR_ARCH_LBR_INFO_0 ... MSR_ARCH_LBR_INFO_0 + 31:
4958 env->lbr_records[index - MSR_ARCH_LBR_INFO_0].info = msrs[i].data;
4959 break;
4960 case MSR_K7_HWCR:
4961 env->msr_hwcr = msrs[i].data;
4962 break;
4963 }
4964 }
4965
4966 return 0;
4967 }
4968
kvm_put_mp_state(X86CPU * cpu)4969 static int kvm_put_mp_state(X86CPU *cpu)
4970 {
4971 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
4972
4973 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
4974 }
4975
kvm_get_mp_state(X86CPU * cpu)4976 static int kvm_get_mp_state(X86CPU *cpu)
4977 {
4978 CPUState *cs = CPU(cpu);
4979 CPUX86State *env = &cpu->env;
4980 struct kvm_mp_state mp_state;
4981 int ret;
4982
4983 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
4984 if (ret < 0) {
4985 return ret;
4986 }
4987 env->mp_state = mp_state.mp_state;
4988 if (kvm_irqchip_in_kernel()) {
4989 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
4990 }
4991 return 0;
4992 }
4993
kvm_get_apic(X86CPU * cpu)4994 static int kvm_get_apic(X86CPU *cpu)
4995 {
4996 DeviceState *apic = cpu->apic_state;
4997 struct kvm_lapic_state kapic;
4998 int ret;
4999
5000 if (apic && kvm_irqchip_in_kernel()) {
5001 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
5002 if (ret < 0) {
5003 return ret;
5004 }
5005
5006 kvm_get_apic_state(apic, &kapic);
5007 }
5008 return 0;
5009 }
5010
kvm_put_vcpu_events(X86CPU * cpu,int level)5011 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
5012 {
5013 CPUState *cs = CPU(cpu);
5014 CPUX86State *env = &cpu->env;
5015 struct kvm_vcpu_events events = {};
5016
5017 events.flags = 0;
5018
5019 if (has_exception_payload) {
5020 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
5021 events.exception.pending = env->exception_pending;
5022 events.exception_has_payload = env->exception_has_payload;
5023 events.exception_payload = env->exception_payload;
5024 }
5025 events.exception.nr = env->exception_nr;
5026 events.exception.injected = env->exception_injected;
5027 events.exception.has_error_code = env->has_error_code;
5028 events.exception.error_code = env->error_code;
5029
5030 events.interrupt.injected = (env->interrupt_injected >= 0);
5031 events.interrupt.nr = env->interrupt_injected;
5032 events.interrupt.soft = env->soft_interrupt;
5033
5034 events.nmi.injected = env->nmi_injected;
5035 events.nmi.pending = env->nmi_pending;
5036 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
5037
5038 events.sipi_vector = env->sipi_vector;
5039
5040 if (has_msr_smbase) {
5041 events.flags |= KVM_VCPUEVENT_VALID_SMM;
5042 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
5043 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
5044 if (kvm_irqchip_in_kernel()) {
5045 /* As soon as these are moved to the kernel, remove them
5046 * from cs->interrupt_request.
5047 */
5048 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
5049 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
5050 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
5051 } else {
5052 /* Keep these in cs->interrupt_request. */
5053 events.smi.pending = 0;
5054 events.smi.latched_init = 0;
5055 }
5056 }
5057
5058 if (level >= KVM_PUT_RESET_STATE) {
5059 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
5060 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
5061 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
5062 }
5063 }
5064
5065 if (has_triple_fault_event) {
5066 events.flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT;
5067 events.triple_fault.pending = env->triple_fault_pending;
5068 }
5069
5070 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
5071 }
5072
kvm_get_vcpu_events(X86CPU * cpu)5073 static int kvm_get_vcpu_events(X86CPU *cpu)
5074 {
5075 CPUX86State *env = &cpu->env;
5076 struct kvm_vcpu_events events;
5077 int ret;
5078
5079 memset(&events, 0, sizeof(events));
5080 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
5081 if (ret < 0) {
5082 return ret;
5083 }
5084
5085 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
5086 env->exception_pending = events.exception.pending;
5087 env->exception_has_payload = events.exception_has_payload;
5088 env->exception_payload = events.exception_payload;
5089 } else {
5090 env->exception_pending = 0;
5091 env->exception_has_payload = false;
5092 }
5093 env->exception_injected = events.exception.injected;
5094 env->exception_nr =
5095 (env->exception_pending || env->exception_injected) ?
5096 events.exception.nr : -1;
5097 env->has_error_code = events.exception.has_error_code;
5098 env->error_code = events.exception.error_code;
5099
5100 env->interrupt_injected =
5101 events.interrupt.injected ? events.interrupt.nr : -1;
5102 env->soft_interrupt = events.interrupt.soft;
5103
5104 env->nmi_injected = events.nmi.injected;
5105 env->nmi_pending = events.nmi.pending;
5106 if (events.nmi.masked) {
5107 env->hflags2 |= HF2_NMI_MASK;
5108 } else {
5109 env->hflags2 &= ~HF2_NMI_MASK;
5110 }
5111
5112 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
5113 if (events.smi.smm) {
5114 env->hflags |= HF_SMM_MASK;
5115 } else {
5116 env->hflags &= ~HF_SMM_MASK;
5117 }
5118 if (events.smi.pending) {
5119 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
5120 } else {
5121 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
5122 }
5123 if (events.smi.smm_inside_nmi) {
5124 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
5125 } else {
5126 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
5127 }
5128 if (events.smi.latched_init) {
5129 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
5130 } else {
5131 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
5132 }
5133 }
5134
5135 if (events.flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) {
5136 env->triple_fault_pending = events.triple_fault.pending;
5137 }
5138
5139 env->sipi_vector = events.sipi_vector;
5140
5141 return 0;
5142 }
5143
kvm_put_debugregs(X86CPU * cpu)5144 static int kvm_put_debugregs(X86CPU *cpu)
5145 {
5146 CPUX86State *env = &cpu->env;
5147 struct kvm_debugregs dbgregs;
5148 int i;
5149
5150 memset(&dbgregs, 0, sizeof(dbgregs));
5151 for (i = 0; i < 4; i++) {
5152 dbgregs.db[i] = env->dr[i];
5153 }
5154 dbgregs.dr6 = env->dr[6];
5155 dbgregs.dr7 = env->dr[7];
5156 dbgregs.flags = 0;
5157
5158 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
5159 }
5160
kvm_get_debugregs(X86CPU * cpu)5161 static int kvm_get_debugregs(X86CPU *cpu)
5162 {
5163 CPUX86State *env = &cpu->env;
5164 struct kvm_debugregs dbgregs;
5165 int i, ret;
5166
5167 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
5168 if (ret < 0) {
5169 return ret;
5170 }
5171 for (i = 0; i < 4; i++) {
5172 env->dr[i] = dbgregs.db[i];
5173 }
5174 env->dr[4] = env->dr[6] = dbgregs.dr6;
5175 env->dr[5] = env->dr[7] = dbgregs.dr7;
5176
5177 return 0;
5178 }
5179
kvm_put_nested_state(X86CPU * cpu)5180 static int kvm_put_nested_state(X86CPU *cpu)
5181 {
5182 CPUX86State *env = &cpu->env;
5183 int max_nested_state_len = kvm_max_nested_state_length();
5184
5185 if (!env->nested_state) {
5186 return 0;
5187 }
5188
5189 /*
5190 * Copy flags that are affected by reset from env->hflags and env->hflags2.
5191 */
5192 if (env->hflags & HF_GUEST_MASK) {
5193 env->nested_state->flags |= KVM_STATE_NESTED_GUEST_MODE;
5194 } else {
5195 env->nested_state->flags &= ~KVM_STATE_NESTED_GUEST_MODE;
5196 }
5197
5198 /* Don't set KVM_STATE_NESTED_GIF_SET on VMX as it is illegal */
5199 if (cpu_has_svm(env) && (env->hflags2 & HF2_GIF_MASK)) {
5200 env->nested_state->flags |= KVM_STATE_NESTED_GIF_SET;
5201 } else {
5202 env->nested_state->flags &= ~KVM_STATE_NESTED_GIF_SET;
5203 }
5204
5205 assert(env->nested_state->size <= max_nested_state_len);
5206 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
5207 }
5208
kvm_get_nested_state(X86CPU * cpu)5209 static int kvm_get_nested_state(X86CPU *cpu)
5210 {
5211 CPUX86State *env = &cpu->env;
5212 int max_nested_state_len = kvm_max_nested_state_length();
5213 int ret;
5214
5215 if (!env->nested_state) {
5216 return 0;
5217 }
5218
5219 /*
5220 * It is possible that migration restored a smaller size into
5221 * nested_state->hdr.size than what our kernel support.
5222 * We preserve migration origin nested_state->hdr.size for
5223 * call to KVM_SET_NESTED_STATE but wish that our next call
5224 * to KVM_GET_NESTED_STATE will use max size our kernel support.
5225 */
5226 env->nested_state->size = max_nested_state_len;
5227
5228 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
5229 if (ret < 0) {
5230 return ret;
5231 }
5232
5233 /*
5234 * Copy flags that are affected by reset to env->hflags and env->hflags2.
5235 */
5236 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
5237 env->hflags |= HF_GUEST_MASK;
5238 } else {
5239 env->hflags &= ~HF_GUEST_MASK;
5240 }
5241
5242 /* Keep HF2_GIF_MASK set on !SVM as x86_cpu_pending_interrupt() needs it */
5243 if (cpu_has_svm(env)) {
5244 if (env->nested_state->flags & KVM_STATE_NESTED_GIF_SET) {
5245 env->hflags2 |= HF2_GIF_MASK;
5246 } else {
5247 env->hflags2 &= ~HF2_GIF_MASK;
5248 }
5249 }
5250
5251 return ret;
5252 }
5253
kvm_arch_put_registers(CPUState * cpu,int level,Error ** errp)5254 int kvm_arch_put_registers(CPUState *cpu, int level, Error **errp)
5255 {
5256 X86CPU *x86_cpu = X86_CPU(cpu);
5257 int ret;
5258
5259 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
5260
5261 /*
5262 * Put MSR_IA32_FEATURE_CONTROL first, this ensures the VM gets out of VMX
5263 * root operation upon vCPU reset. kvm_put_msr_feature_control() should also
5264 * precede kvm_put_nested_state() when 'real' nested state is set.
5265 */
5266 if (level >= KVM_PUT_RESET_STATE) {
5267 ret = kvm_put_msr_feature_control(x86_cpu);
5268 if (ret < 0) {
5269 error_setg_errno(errp, -ret, "Failed to set feature control MSR");
5270 return ret;
5271 }
5272 }
5273
5274 /* must be before kvm_put_nested_state so that EFER.SVME is set */
5275 ret = has_sregs2 ? kvm_put_sregs2(x86_cpu) : kvm_put_sregs(x86_cpu);
5276 if (ret < 0) {
5277 error_setg_errno(errp, -ret, "Failed to set special registers");
5278 return ret;
5279 }
5280
5281 if (level >= KVM_PUT_RESET_STATE) {
5282 ret = kvm_put_nested_state(x86_cpu);
5283 if (ret < 0) {
5284 error_setg_errno(errp, -ret, "Failed to set nested state");
5285 return ret;
5286 }
5287 }
5288
5289 if (level == KVM_PUT_FULL_STATE) {
5290 /* We don't check for kvm_arch_set_tsc_khz() errors here,
5291 * because TSC frequency mismatch shouldn't abort migration,
5292 * unless the user explicitly asked for a more strict TSC
5293 * setting (e.g. using an explicit "tsc-freq" option).
5294 */
5295 kvm_arch_set_tsc_khz(cpu);
5296 }
5297
5298 #ifdef CONFIG_XEN_EMU
5299 if (xen_mode == XEN_EMULATE && level == KVM_PUT_FULL_STATE) {
5300 ret = kvm_put_xen_state(cpu);
5301 if (ret < 0) {
5302 error_setg_errno(errp, -ret, "Failed to set Xen state");
5303 return ret;
5304 }
5305 }
5306 #endif
5307
5308 ret = kvm_getput_regs(x86_cpu, 1);
5309 if (ret < 0) {
5310 error_setg_errno(errp, -ret, "Failed to set general purpose registers");
5311 return ret;
5312 }
5313 ret = kvm_put_xsave(x86_cpu);
5314 if (ret < 0) {
5315 error_setg_errno(errp, -ret, "Failed to set XSAVE");
5316 return ret;
5317 }
5318 ret = kvm_put_xcrs(x86_cpu);
5319 if (ret < 0) {
5320 error_setg_errno(errp, -ret, "Failed to set XCRs");
5321 return ret;
5322 }
5323 ret = kvm_put_msrs(x86_cpu, level);
5324 if (ret < 0) {
5325 error_setg_errno(errp, -ret, "Failed to set MSRs");
5326 return ret;
5327 }
5328 ret = kvm_put_vcpu_events(x86_cpu, level);
5329 if (ret < 0) {
5330 error_setg_errno(errp, -ret, "Failed to set vCPU events");
5331 return ret;
5332 }
5333 if (level >= KVM_PUT_RESET_STATE) {
5334 ret = kvm_put_mp_state(x86_cpu);
5335 if (ret < 0) {
5336 error_setg_errno(errp, -ret, "Failed to set MP state");
5337 return ret;
5338 }
5339 }
5340
5341 ret = kvm_put_tscdeadline_msr(x86_cpu);
5342 if (ret < 0) {
5343 error_setg_errno(errp, -ret, "Failed to set TSC deadline MSR");
5344 return ret;
5345 }
5346 ret = kvm_put_debugregs(x86_cpu);
5347 if (ret < 0) {
5348 error_setg_errno(errp, -ret, "Failed to set debug registers");
5349 return ret;
5350 }
5351 return 0;
5352 }
5353
kvm_arch_get_registers(CPUState * cs,Error ** errp)5354 int kvm_arch_get_registers(CPUState *cs, Error **errp)
5355 {
5356 X86CPU *cpu = X86_CPU(cs);
5357 int ret;
5358
5359 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
5360
5361 ret = kvm_get_vcpu_events(cpu);
5362 if (ret < 0) {
5363 error_setg_errno(errp, -ret, "Failed to get vCPU events");
5364 goto out;
5365 }
5366 /*
5367 * KVM_GET_MPSTATE can modify CS and RIP, call it before
5368 * KVM_GET_REGS and KVM_GET_SREGS.
5369 */
5370 ret = kvm_get_mp_state(cpu);
5371 if (ret < 0) {
5372 error_setg_errno(errp, -ret, "Failed to get MP state");
5373 goto out;
5374 }
5375 ret = kvm_getput_regs(cpu, 0);
5376 if (ret < 0) {
5377 error_setg_errno(errp, -ret, "Failed to get general purpose registers");
5378 goto out;
5379 }
5380 ret = kvm_get_xsave(cpu);
5381 if (ret < 0) {
5382 error_setg_errno(errp, -ret, "Failed to get XSAVE");
5383 goto out;
5384 }
5385 ret = kvm_get_xcrs(cpu);
5386 if (ret < 0) {
5387 error_setg_errno(errp, -ret, "Failed to get XCRs");
5388 goto out;
5389 }
5390 ret = has_sregs2 ? kvm_get_sregs2(cpu) : kvm_get_sregs(cpu);
5391 if (ret < 0) {
5392 error_setg_errno(errp, -ret, "Failed to get special registers");
5393 goto out;
5394 }
5395 ret = kvm_get_msrs(cpu);
5396 if (ret < 0) {
5397 error_setg_errno(errp, -ret, "Failed to get MSRs");
5398 goto out;
5399 }
5400 ret = kvm_get_apic(cpu);
5401 if (ret < 0) {
5402 error_setg_errno(errp, -ret, "Failed to get APIC");
5403 goto out;
5404 }
5405 ret = kvm_get_debugregs(cpu);
5406 if (ret < 0) {
5407 error_setg_errno(errp, -ret, "Failed to get debug registers");
5408 goto out;
5409 }
5410 ret = kvm_get_nested_state(cpu);
5411 if (ret < 0) {
5412 error_setg_errno(errp, -ret, "Failed to get nested state");
5413 goto out;
5414 }
5415 #ifdef CONFIG_XEN_EMU
5416 if (xen_mode == XEN_EMULATE) {
5417 ret = kvm_get_xen_state(cs);
5418 if (ret < 0) {
5419 error_setg_errno(errp, -ret, "Failed to get Xen state");
5420 goto out;
5421 }
5422 }
5423 #endif
5424 ret = 0;
5425 out:
5426 cpu_sync_bndcs_hflags(&cpu->env);
5427 return ret;
5428 }
5429
kvm_arch_pre_run(CPUState * cpu,struct kvm_run * run)5430 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
5431 {
5432 X86CPU *x86_cpu = X86_CPU(cpu);
5433 CPUX86State *env = &x86_cpu->env;
5434 int ret;
5435
5436 /* Inject NMI */
5437 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
5438 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
5439 bql_lock();
5440 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
5441 bql_unlock();
5442 DPRINTF("injected NMI\n");
5443 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
5444 if (ret < 0) {
5445 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
5446 strerror(-ret));
5447 }
5448 }
5449 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
5450 bql_lock();
5451 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
5452 bql_unlock();
5453 DPRINTF("injected SMI\n");
5454 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
5455 if (ret < 0) {
5456 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
5457 strerror(-ret));
5458 }
5459 }
5460 }
5461
5462 if (!kvm_pic_in_kernel()) {
5463 bql_lock();
5464 }
5465
5466 /* Force the VCPU out of its inner loop to process any INIT requests
5467 * or (for userspace APIC, but it is cheap to combine the checks here)
5468 * pending TPR access reports.
5469 */
5470 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
5471 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
5472 !(env->hflags & HF_SMM_MASK)) {
5473 cpu->exit_request = 1;
5474 }
5475 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
5476 cpu->exit_request = 1;
5477 }
5478 }
5479
5480 if (!kvm_pic_in_kernel()) {
5481 /* Try to inject an interrupt if the guest can accept it */
5482 if (run->ready_for_interrupt_injection &&
5483 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
5484 (env->eflags & IF_MASK)) {
5485 int irq;
5486
5487 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
5488 irq = cpu_get_pic_interrupt(env);
5489 if (irq >= 0) {
5490 struct kvm_interrupt intr;
5491
5492 intr.irq = irq;
5493 DPRINTF("injected interrupt %d\n", irq);
5494 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
5495 if (ret < 0) {
5496 fprintf(stderr,
5497 "KVM: injection failed, interrupt lost (%s)\n",
5498 strerror(-ret));
5499 }
5500 }
5501 }
5502
5503 /* If we have an interrupt but the guest is not ready to receive an
5504 * interrupt, request an interrupt window exit. This will
5505 * cause a return to userspace as soon as the guest is ready to
5506 * receive interrupts. */
5507 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
5508 run->request_interrupt_window = 1;
5509 } else {
5510 run->request_interrupt_window = 0;
5511 }
5512
5513 DPRINTF("setting tpr\n");
5514 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
5515
5516 bql_unlock();
5517 }
5518 }
5519
kvm_rate_limit_on_bus_lock(void)5520 static void kvm_rate_limit_on_bus_lock(void)
5521 {
5522 uint64_t delay_ns = ratelimit_calculate_delay(&bus_lock_ratelimit_ctrl, 1);
5523
5524 if (delay_ns) {
5525 g_usleep(delay_ns / SCALE_US);
5526 }
5527 }
5528
kvm_arch_post_run(CPUState * cpu,struct kvm_run * run)5529 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
5530 {
5531 X86CPU *x86_cpu = X86_CPU(cpu);
5532 CPUX86State *env = &x86_cpu->env;
5533
5534 if (run->flags & KVM_RUN_X86_SMM) {
5535 env->hflags |= HF_SMM_MASK;
5536 } else {
5537 env->hflags &= ~HF_SMM_MASK;
5538 }
5539 if (run->if_flag) {
5540 env->eflags |= IF_MASK;
5541 } else {
5542 env->eflags &= ~IF_MASK;
5543 }
5544 if (run->flags & KVM_RUN_X86_BUS_LOCK) {
5545 kvm_rate_limit_on_bus_lock();
5546 }
5547
5548 #ifdef CONFIG_XEN_EMU
5549 /*
5550 * If the callback is asserted as a GSI (or PCI INTx) then check if
5551 * vcpu_info->evtchn_upcall_pending has been cleared, and deassert
5552 * the callback IRQ if so. Ideally we could hook into the PIC/IOAPIC
5553 * EOI and only resample then, exactly how the VFIO eventfd pairs
5554 * are designed to work for level triggered interrupts.
5555 */
5556 if (x86_cpu->env.xen_callback_asserted) {
5557 kvm_xen_maybe_deassert_callback(cpu);
5558 }
5559 #endif
5560
5561 /* We need to protect the apic state against concurrent accesses from
5562 * different threads in case the userspace irqchip is used. */
5563 if (!kvm_irqchip_in_kernel()) {
5564 bql_lock();
5565 }
5566 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
5567 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
5568 if (!kvm_irqchip_in_kernel()) {
5569 bql_unlock();
5570 }
5571 return cpu_get_mem_attrs(env);
5572 }
5573
kvm_arch_process_async_events(CPUState * cs)5574 int kvm_arch_process_async_events(CPUState *cs)
5575 {
5576 X86CPU *cpu = X86_CPU(cs);
5577 CPUX86State *env = &cpu->env;
5578
5579 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
5580 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
5581 assert(env->mcg_cap);
5582
5583 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
5584
5585 kvm_cpu_synchronize_state(cs);
5586
5587 if (env->exception_nr == EXCP08_DBLE) {
5588 /* this means triple fault */
5589 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
5590 cs->exit_request = 1;
5591 return 0;
5592 }
5593 kvm_queue_exception(env, EXCP12_MCHK, 0, 0);
5594 env->has_error_code = 0;
5595
5596 cs->halted = 0;
5597 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
5598 env->mp_state = KVM_MP_STATE_RUNNABLE;
5599 }
5600 }
5601
5602 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
5603 !(env->hflags & HF_SMM_MASK)) {
5604 kvm_cpu_synchronize_state(cs);
5605 do_cpu_init(cpu);
5606 }
5607
5608 if (kvm_irqchip_in_kernel()) {
5609 return 0;
5610 }
5611
5612 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
5613 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
5614 apic_poll_irq(cpu->apic_state);
5615 }
5616 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
5617 (env->eflags & IF_MASK)) ||
5618 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
5619 cs->halted = 0;
5620 }
5621 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
5622 kvm_cpu_synchronize_state(cs);
5623 do_cpu_sipi(cpu);
5624 }
5625 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
5626 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
5627 kvm_cpu_synchronize_state(cs);
5628 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
5629 env->tpr_access_type);
5630 }
5631
5632 return cs->halted;
5633 }
5634
kvm_handle_halt(X86CPU * cpu)5635 static int kvm_handle_halt(X86CPU *cpu)
5636 {
5637 CPUState *cs = CPU(cpu);
5638 CPUX86State *env = &cpu->env;
5639
5640 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
5641 (env->eflags & IF_MASK)) &&
5642 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
5643 cs->halted = 1;
5644 return EXCP_HLT;
5645 }
5646
5647 return 0;
5648 }
5649
kvm_handle_tpr_access(X86CPU * cpu)5650 static int kvm_handle_tpr_access(X86CPU *cpu)
5651 {
5652 CPUState *cs = CPU(cpu);
5653 struct kvm_run *run = cs->kvm_run;
5654
5655 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
5656 run->tpr_access.is_write ? TPR_ACCESS_WRITE
5657 : TPR_ACCESS_READ);
5658 return 1;
5659 }
5660
kvm_arch_insert_sw_breakpoint(CPUState * cs,struct kvm_sw_breakpoint * bp)5661 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
5662 {
5663 static const uint8_t int3 = 0xcc;
5664
5665 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
5666 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
5667 return -EINVAL;
5668 }
5669 return 0;
5670 }
5671
kvm_arch_remove_sw_breakpoint(CPUState * cs,struct kvm_sw_breakpoint * bp)5672 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
5673 {
5674 uint8_t int3;
5675
5676 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0)) {
5677 return -EINVAL;
5678 }
5679 if (int3 != 0xcc) {
5680 return 0;
5681 }
5682 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
5683 return -EINVAL;
5684 }
5685 return 0;
5686 }
5687
5688 static struct {
5689 target_ulong addr;
5690 int len;
5691 int type;
5692 } hw_breakpoint[4];
5693
5694 static int nb_hw_breakpoint;
5695
find_hw_breakpoint(target_ulong addr,int len,int type)5696 static int find_hw_breakpoint(target_ulong addr, int len, int type)
5697 {
5698 int n;
5699
5700 for (n = 0; n < nb_hw_breakpoint; n++) {
5701 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
5702 (hw_breakpoint[n].len == len || len == -1)) {
5703 return n;
5704 }
5705 }
5706 return -1;
5707 }
5708
kvm_arch_insert_hw_breakpoint(vaddr addr,vaddr len,int type)5709 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type)
5710 {
5711 switch (type) {
5712 case GDB_BREAKPOINT_HW:
5713 len = 1;
5714 break;
5715 case GDB_WATCHPOINT_WRITE:
5716 case GDB_WATCHPOINT_ACCESS:
5717 switch (len) {
5718 case 1:
5719 break;
5720 case 2:
5721 case 4:
5722 case 8:
5723 if (addr & (len - 1)) {
5724 return -EINVAL;
5725 }
5726 break;
5727 default:
5728 return -EINVAL;
5729 }
5730 break;
5731 default:
5732 return -ENOSYS;
5733 }
5734
5735 if (nb_hw_breakpoint == 4) {
5736 return -ENOBUFS;
5737 }
5738 if (find_hw_breakpoint(addr, len, type) >= 0) {
5739 return -EEXIST;
5740 }
5741 hw_breakpoint[nb_hw_breakpoint].addr = addr;
5742 hw_breakpoint[nb_hw_breakpoint].len = len;
5743 hw_breakpoint[nb_hw_breakpoint].type = type;
5744 nb_hw_breakpoint++;
5745
5746 return 0;
5747 }
5748
kvm_arch_remove_hw_breakpoint(vaddr addr,vaddr len,int type)5749 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type)
5750 {
5751 int n;
5752
5753 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
5754 if (n < 0) {
5755 return -ENOENT;
5756 }
5757 nb_hw_breakpoint--;
5758 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
5759
5760 return 0;
5761 }
5762
kvm_arch_remove_all_hw_breakpoints(void)5763 void kvm_arch_remove_all_hw_breakpoints(void)
5764 {
5765 nb_hw_breakpoint = 0;
5766 }
5767
5768 static CPUWatchpoint hw_watchpoint;
5769
kvm_handle_debug(X86CPU * cpu,struct kvm_debug_exit_arch * arch_info)5770 static int kvm_handle_debug(X86CPU *cpu,
5771 struct kvm_debug_exit_arch *arch_info)
5772 {
5773 CPUState *cs = CPU(cpu);
5774 CPUX86State *env = &cpu->env;
5775 int ret = 0;
5776 int n;
5777
5778 if (arch_info->exception == EXCP01_DB) {
5779 if (arch_info->dr6 & DR6_BS) {
5780 if (cs->singlestep_enabled) {
5781 ret = EXCP_DEBUG;
5782 }
5783 } else {
5784 for (n = 0; n < 4; n++) {
5785 if (arch_info->dr6 & (1 << n)) {
5786 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
5787 case 0x0:
5788 ret = EXCP_DEBUG;
5789 break;
5790 case 0x1:
5791 ret = EXCP_DEBUG;
5792 cs->watchpoint_hit = &hw_watchpoint;
5793 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
5794 hw_watchpoint.flags = BP_MEM_WRITE;
5795 break;
5796 case 0x3:
5797 ret = EXCP_DEBUG;
5798 cs->watchpoint_hit = &hw_watchpoint;
5799 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
5800 hw_watchpoint.flags = BP_MEM_ACCESS;
5801 break;
5802 }
5803 }
5804 }
5805 }
5806 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
5807 ret = EXCP_DEBUG;
5808 }
5809 if (ret == 0) {
5810 cpu_synchronize_state(cs);
5811 assert(env->exception_nr == -1);
5812
5813 /* pass to guest */
5814 kvm_queue_exception(env, arch_info->exception,
5815 arch_info->exception == EXCP01_DB,
5816 arch_info->dr6);
5817 env->has_error_code = 0;
5818 }
5819
5820 return ret;
5821 }
5822
kvm_arch_update_guest_debug(CPUState * cpu,struct kvm_guest_debug * dbg)5823 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
5824 {
5825 const uint8_t type_code[] = {
5826 [GDB_BREAKPOINT_HW] = 0x0,
5827 [GDB_WATCHPOINT_WRITE] = 0x1,
5828 [GDB_WATCHPOINT_ACCESS] = 0x3
5829 };
5830 const uint8_t len_code[] = {
5831 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
5832 };
5833 int n;
5834
5835 if (kvm_sw_breakpoints_active(cpu)) {
5836 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
5837 }
5838 if (nb_hw_breakpoint > 0) {
5839 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
5840 dbg->arch.debugreg[7] = 0x0600;
5841 for (n = 0; n < nb_hw_breakpoint; n++) {
5842 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
5843 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
5844 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
5845 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
5846 }
5847 }
5848 }
5849
kvm_install_msr_filters(KVMState * s)5850 static int kvm_install_msr_filters(KVMState *s)
5851 {
5852 uint64_t zero = 0;
5853 struct kvm_msr_filter filter = {
5854 .flags = KVM_MSR_FILTER_DEFAULT_ALLOW,
5855 };
5856 int i, j = 0;
5857
5858 QEMU_BUILD_BUG_ON(ARRAY_SIZE(msr_handlers) != ARRAY_SIZE(filter.ranges));
5859 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5860 KVMMSRHandlers *handler = &msr_handlers[i];
5861 if (handler->msr) {
5862 struct kvm_msr_filter_range *range = &filter.ranges[j++];
5863
5864 *range = (struct kvm_msr_filter_range) {
5865 .flags = 0,
5866 .nmsrs = 1,
5867 .base = handler->msr,
5868 .bitmap = (__u8 *)&zero,
5869 };
5870
5871 if (handler->rdmsr) {
5872 range->flags |= KVM_MSR_FILTER_READ;
5873 }
5874
5875 if (handler->wrmsr) {
5876 range->flags |= KVM_MSR_FILTER_WRITE;
5877 }
5878 }
5879 }
5880
5881 return kvm_vm_ioctl(s, KVM_X86_SET_MSR_FILTER, &filter);
5882 }
5883
kvm_filter_msr(KVMState * s,uint32_t msr,QEMURDMSRHandler * rdmsr,QEMUWRMSRHandler * wrmsr)5884 static int kvm_filter_msr(KVMState *s, uint32_t msr, QEMURDMSRHandler *rdmsr,
5885 QEMUWRMSRHandler *wrmsr)
5886 {
5887 int i, ret;
5888
5889 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5890 if (!msr_handlers[i].msr) {
5891 msr_handlers[i] = (KVMMSRHandlers) {
5892 .msr = msr,
5893 .rdmsr = rdmsr,
5894 .wrmsr = wrmsr,
5895 };
5896
5897 ret = kvm_install_msr_filters(s);
5898 if (ret) {
5899 msr_handlers[i] = (KVMMSRHandlers) { };
5900 return ret;
5901 }
5902
5903 return 0;
5904 }
5905 }
5906
5907 return -EINVAL;
5908 }
5909
kvm_handle_rdmsr(X86CPU * cpu,struct kvm_run * run)5910 static int kvm_handle_rdmsr(X86CPU *cpu, struct kvm_run *run)
5911 {
5912 int i;
5913 bool r;
5914
5915 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5916 KVMMSRHandlers *handler = &msr_handlers[i];
5917 if (run->msr.index == handler->msr) {
5918 if (handler->rdmsr) {
5919 r = handler->rdmsr(cpu, handler->msr,
5920 (uint64_t *)&run->msr.data);
5921 run->msr.error = r ? 0 : 1;
5922 return 0;
5923 }
5924 }
5925 }
5926
5927 g_assert_not_reached();
5928 }
5929
kvm_handle_wrmsr(X86CPU * cpu,struct kvm_run * run)5930 static int kvm_handle_wrmsr(X86CPU *cpu, struct kvm_run *run)
5931 {
5932 int i;
5933 bool r;
5934
5935 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5936 KVMMSRHandlers *handler = &msr_handlers[i];
5937 if (run->msr.index == handler->msr) {
5938 if (handler->wrmsr) {
5939 r = handler->wrmsr(cpu, handler->msr, run->msr.data);
5940 run->msr.error = r ? 0 : 1;
5941 return 0;
5942 }
5943 }
5944 }
5945
5946 g_assert_not_reached();
5947 }
5948
5949 static bool has_sgx_provisioning;
5950
__kvm_enable_sgx_provisioning(KVMState * s)5951 static bool __kvm_enable_sgx_provisioning(KVMState *s)
5952 {
5953 int fd, ret;
5954
5955 if (!kvm_vm_check_extension(s, KVM_CAP_SGX_ATTRIBUTE)) {
5956 return false;
5957 }
5958
5959 fd = qemu_open_old("/dev/sgx_provision", O_RDONLY);
5960 if (fd < 0) {
5961 return false;
5962 }
5963
5964 ret = kvm_vm_enable_cap(s, KVM_CAP_SGX_ATTRIBUTE, 0, fd);
5965 if (ret) {
5966 error_report("Could not enable SGX PROVISIONKEY: %s", strerror(-ret));
5967 exit(1);
5968 }
5969 close(fd);
5970 return true;
5971 }
5972
kvm_enable_sgx_provisioning(KVMState * s)5973 bool kvm_enable_sgx_provisioning(KVMState *s)
5974 {
5975 return MEMORIZE(__kvm_enable_sgx_provisioning(s), has_sgx_provisioning);
5976 }
5977
host_supports_vmx(void)5978 static bool host_supports_vmx(void)
5979 {
5980 uint32_t ecx, unused;
5981
5982 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
5983 return ecx & CPUID_EXT_VMX;
5984 }
5985
5986 /*
5987 * Currently the handling here only supports use of KVM_HC_MAP_GPA_RANGE
5988 * to service guest-initiated memory attribute update requests so that
5989 * KVM_SET_MEMORY_ATTRIBUTES can update whether or not a page should be
5990 * backed by the private memory pool provided by guest_memfd, and as such
5991 * is only applicable to guest_memfd-backed guests (e.g. SNP/TDX).
5992 *
5993 * Other other use-cases for KVM_HC_MAP_GPA_RANGE, such as for SEV live
5994 * migration, are not implemented here currently.
5995 *
5996 * For the guest_memfd use-case, these exits will generally be synthesized
5997 * by KVM based on platform-specific hypercalls, like GHCB requests in the
5998 * case of SEV-SNP, and not issued directly within the guest though the
5999 * KVM_HC_MAP_GPA_RANGE hypercall. So in this case, KVM_HC_MAP_GPA_RANGE is
6000 * not actually advertised to guests via the KVM CPUID feature bit, as
6001 * opposed to SEV live migration where it would be. Since it is unlikely the
6002 * SEV live migration use-case would be useful for guest-memfd backed guests,
6003 * because private/shared page tracking is already provided through other
6004 * means, these 2 use-cases should be treated as being mutually-exclusive.
6005 */
kvm_handle_hc_map_gpa_range(struct kvm_run * run)6006 static int kvm_handle_hc_map_gpa_range(struct kvm_run *run)
6007 {
6008 uint64_t gpa, size, attributes;
6009
6010 if (!machine_require_guest_memfd(current_machine))
6011 return -EINVAL;
6012
6013 gpa = run->hypercall.args[0];
6014 size = run->hypercall.args[1] * TARGET_PAGE_SIZE;
6015 attributes = run->hypercall.args[2];
6016
6017 trace_kvm_hc_map_gpa_range(gpa, size, attributes, run->hypercall.flags);
6018
6019 return kvm_convert_memory(gpa, size, attributes & KVM_MAP_GPA_RANGE_ENCRYPTED);
6020 }
6021
kvm_handle_hypercall(struct kvm_run * run)6022 static int kvm_handle_hypercall(struct kvm_run *run)
6023 {
6024 if (run->hypercall.nr == KVM_HC_MAP_GPA_RANGE)
6025 return kvm_handle_hc_map_gpa_range(run);
6026
6027 return -EINVAL;
6028 }
6029
6030 #define VMX_INVALID_GUEST_STATE 0x80000021
6031
kvm_arch_handle_exit(CPUState * cs,struct kvm_run * run)6032 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
6033 {
6034 X86CPU *cpu = X86_CPU(cs);
6035 uint64_t code;
6036 int ret;
6037 bool ctx_invalid;
6038 KVMState *state;
6039
6040 switch (run->exit_reason) {
6041 case KVM_EXIT_HLT:
6042 DPRINTF("handle_hlt\n");
6043 bql_lock();
6044 ret = kvm_handle_halt(cpu);
6045 bql_unlock();
6046 break;
6047 case KVM_EXIT_SET_TPR:
6048 ret = 0;
6049 break;
6050 case KVM_EXIT_TPR_ACCESS:
6051 bql_lock();
6052 ret = kvm_handle_tpr_access(cpu);
6053 bql_unlock();
6054 break;
6055 case KVM_EXIT_FAIL_ENTRY:
6056 code = run->fail_entry.hardware_entry_failure_reason;
6057 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
6058 code);
6059 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
6060 fprintf(stderr,
6061 "\nIf you're running a guest on an Intel machine without "
6062 "unrestricted mode\n"
6063 "support, the failure can be most likely due to the guest "
6064 "entering an invalid\n"
6065 "state for Intel VT. For example, the guest maybe running "
6066 "in big real mode\n"
6067 "which is not supported on less recent Intel processors."
6068 "\n\n");
6069 }
6070 ret = -1;
6071 break;
6072 case KVM_EXIT_EXCEPTION:
6073 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
6074 run->ex.exception, run->ex.error_code);
6075 ret = -1;
6076 break;
6077 case KVM_EXIT_DEBUG:
6078 DPRINTF("kvm_exit_debug\n");
6079 bql_lock();
6080 ret = kvm_handle_debug(cpu, &run->debug.arch);
6081 bql_unlock();
6082 break;
6083 case KVM_EXIT_HYPERV:
6084 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
6085 break;
6086 case KVM_EXIT_IOAPIC_EOI:
6087 ioapic_eoi_broadcast(run->eoi.vector);
6088 ret = 0;
6089 break;
6090 case KVM_EXIT_X86_BUS_LOCK:
6091 /* already handled in kvm_arch_post_run */
6092 ret = 0;
6093 break;
6094 case KVM_EXIT_NOTIFY:
6095 ctx_invalid = !!(run->notify.flags & KVM_NOTIFY_CONTEXT_INVALID);
6096 state = KVM_STATE(current_accel());
6097 if (ctx_invalid ||
6098 state->notify_vmexit == NOTIFY_VMEXIT_OPTION_INTERNAL_ERROR) {
6099 warn_report("KVM internal error: Encountered a notify exit "
6100 "with invalid context in guest.");
6101 ret = -1;
6102 } else {
6103 warn_report_once("KVM: Encountered a notify exit with valid "
6104 "context in guest. "
6105 "The guest could be misbehaving.");
6106 ret = 0;
6107 }
6108 break;
6109 case KVM_EXIT_X86_RDMSR:
6110 /* We only enable MSR filtering, any other exit is bogus */
6111 assert(run->msr.reason == KVM_MSR_EXIT_REASON_FILTER);
6112 ret = kvm_handle_rdmsr(cpu, run);
6113 break;
6114 case KVM_EXIT_X86_WRMSR:
6115 /* We only enable MSR filtering, any other exit is bogus */
6116 assert(run->msr.reason == KVM_MSR_EXIT_REASON_FILTER);
6117 ret = kvm_handle_wrmsr(cpu, run);
6118 break;
6119 #ifdef CONFIG_XEN_EMU
6120 case KVM_EXIT_XEN:
6121 ret = kvm_xen_handle_exit(cpu, &run->xen);
6122 break;
6123 #endif
6124 case KVM_EXIT_HYPERCALL:
6125 ret = kvm_handle_hypercall(run);
6126 break;
6127 default:
6128 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
6129 ret = -1;
6130 break;
6131 }
6132
6133 return ret;
6134 }
6135
kvm_arch_stop_on_emulation_error(CPUState * cs)6136 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
6137 {
6138 X86CPU *cpu = X86_CPU(cs);
6139 CPUX86State *env = &cpu->env;
6140
6141 kvm_cpu_synchronize_state(cs);
6142 return !(env->cr[0] & CR0_PE_MASK) ||
6143 ((env->segs[R_CS].selector & 3) != 3);
6144 }
6145
kvm_arch_init_irq_routing(KVMState * s)6146 void kvm_arch_init_irq_routing(KVMState *s)
6147 {
6148 /* We know at this point that we're using the in-kernel
6149 * irqchip, so we can use irqfds, and on x86 we know
6150 * we can use msi via irqfd and GSI routing.
6151 */
6152 kvm_msi_via_irqfd_allowed = true;
6153 kvm_gsi_routing_allowed = true;
6154
6155 if (kvm_irqchip_is_split()) {
6156 KVMRouteChange c = kvm_irqchip_begin_route_changes(s);
6157 int i;
6158
6159 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
6160 MSI routes for signaling interrupts to the local apics. */
6161 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
6162 if (kvm_irqchip_add_msi_route(&c, 0, NULL) < 0) {
6163 error_report("Could not enable split IRQ mode.");
6164 exit(1);
6165 }
6166 }
6167 kvm_irqchip_commit_route_changes(&c);
6168 }
6169 }
6170
kvm_arch_irqchip_create(KVMState * s)6171 int kvm_arch_irqchip_create(KVMState *s)
6172 {
6173 int ret;
6174 if (kvm_kernel_irqchip_split()) {
6175 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
6176 if (ret) {
6177 error_report("Could not enable split irqchip mode: %s",
6178 strerror(-ret));
6179 exit(1);
6180 } else {
6181 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
6182 kvm_split_irqchip = true;
6183 return 1;
6184 }
6185 } else {
6186 return 0;
6187 }
6188 }
6189
kvm_swizzle_msi_ext_dest_id(uint64_t address)6190 uint64_t kvm_swizzle_msi_ext_dest_id(uint64_t address)
6191 {
6192 CPUX86State *env;
6193 uint64_t ext_id;
6194
6195 if (!first_cpu) {
6196 return address;
6197 }
6198 env = &X86_CPU(first_cpu)->env;
6199 if (!(env->features[FEAT_KVM] & CPUID_KVM_MSI_EXT_DEST_ID)) {
6200 return address;
6201 }
6202
6203 /*
6204 * If the remappable format bit is set, or the upper bits are
6205 * already set in address_hi, or the low extended bits aren't
6206 * there anyway, do nothing.
6207 */
6208 ext_id = address & (0xff << MSI_ADDR_DEST_IDX_SHIFT);
6209 if (!ext_id || (ext_id & (1 << MSI_ADDR_DEST_IDX_SHIFT)) || (address >> 32)) {
6210 return address;
6211 }
6212
6213 address &= ~ext_id;
6214 address |= ext_id << 35;
6215 return address;
6216 }
6217
kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry * route,uint64_t address,uint32_t data,PCIDevice * dev)6218 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
6219 uint64_t address, uint32_t data, PCIDevice *dev)
6220 {
6221 X86IOMMUState *iommu = x86_iommu_get_default();
6222
6223 if (iommu) {
6224 X86IOMMUClass *class = X86_IOMMU_DEVICE_GET_CLASS(iommu);
6225
6226 if (class->int_remap) {
6227 int ret;
6228 MSIMessage src, dst;
6229
6230 src.address = route->u.msi.address_hi;
6231 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
6232 src.address |= route->u.msi.address_lo;
6233 src.data = route->u.msi.data;
6234
6235 ret = class->int_remap(iommu, &src, &dst, dev ? \
6236 pci_requester_id(dev) : \
6237 X86_IOMMU_SID_INVALID);
6238 if (ret) {
6239 trace_kvm_x86_fixup_msi_error(route->gsi);
6240 return 1;
6241 }
6242
6243 /*
6244 * Handled untranslated compatibility format interrupt with
6245 * extended destination ID in the low bits 11-5. */
6246 dst.address = kvm_swizzle_msi_ext_dest_id(dst.address);
6247
6248 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
6249 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
6250 route->u.msi.data = dst.data;
6251 return 0;
6252 }
6253 }
6254
6255 #ifdef CONFIG_XEN_EMU
6256 if (xen_mode == XEN_EMULATE) {
6257 int handled = xen_evtchn_translate_pirq_msi(route, address, data);
6258
6259 /*
6260 * If it was a PIRQ and successfully routed (handled == 0) or it was
6261 * an error (handled < 0), return. If it wasn't a PIRQ, keep going.
6262 */
6263 if (handled <= 0) {
6264 return handled;
6265 }
6266 }
6267 #endif
6268
6269 address = kvm_swizzle_msi_ext_dest_id(address);
6270 route->u.msi.address_hi = address >> VTD_MSI_ADDR_HI_SHIFT;
6271 route->u.msi.address_lo = address & VTD_MSI_ADDR_LO_MASK;
6272 return 0;
6273 }
6274
6275 typedef struct MSIRouteEntry MSIRouteEntry;
6276
6277 struct MSIRouteEntry {
6278 PCIDevice *dev; /* Device pointer */
6279 int vector; /* MSI/MSIX vector index */
6280 int virq; /* Virtual IRQ index */
6281 QLIST_ENTRY(MSIRouteEntry) list;
6282 };
6283
6284 /* List of used GSI routes */
6285 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
6286 QLIST_HEAD_INITIALIZER(msi_route_list);
6287
kvm_update_msi_routes_all(void * private,bool global,uint32_t index,uint32_t mask)6288 void kvm_update_msi_routes_all(void *private, bool global,
6289 uint32_t index, uint32_t mask)
6290 {
6291 int cnt = 0, vector;
6292 MSIRouteEntry *entry;
6293 MSIMessage msg;
6294 PCIDevice *dev;
6295
6296 /* TODO: explicit route update */
6297 QLIST_FOREACH(entry, &msi_route_list, list) {
6298 cnt++;
6299 vector = entry->vector;
6300 dev = entry->dev;
6301 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
6302 msg = msix_get_message(dev, vector);
6303 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
6304 msg = msi_get_message(dev, vector);
6305 } else {
6306 /*
6307 * Either MSI/MSIX is disabled for the device, or the
6308 * specific message was masked out. Skip this one.
6309 */
6310 continue;
6311 }
6312 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
6313 }
6314 kvm_irqchip_commit_routes(kvm_state);
6315 trace_kvm_x86_update_msi_routes(cnt);
6316 }
6317
kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry * route,int vector,PCIDevice * dev)6318 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
6319 int vector, PCIDevice *dev)
6320 {
6321 static bool notify_list_inited = false;
6322 MSIRouteEntry *entry;
6323
6324 if (!dev) {
6325 /* These are (possibly) IOAPIC routes only used for split
6326 * kernel irqchip mode, while what we are housekeeping are
6327 * PCI devices only. */
6328 return 0;
6329 }
6330
6331 entry = g_new0(MSIRouteEntry, 1);
6332 entry->dev = dev;
6333 entry->vector = vector;
6334 entry->virq = route->gsi;
6335 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
6336
6337 trace_kvm_x86_add_msi_route(route->gsi);
6338
6339 if (!notify_list_inited) {
6340 /* For the first time we do add route, add ourselves into
6341 * IOMMU's IEC notify list if needed. */
6342 X86IOMMUState *iommu = x86_iommu_get_default();
6343 if (iommu) {
6344 x86_iommu_iec_register_notifier(iommu,
6345 kvm_update_msi_routes_all,
6346 NULL);
6347 }
6348 notify_list_inited = true;
6349 }
6350 return 0;
6351 }
6352
kvm_arch_release_virq_post(int virq)6353 int kvm_arch_release_virq_post(int virq)
6354 {
6355 MSIRouteEntry *entry, *next;
6356 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
6357 if (entry->virq == virq) {
6358 trace_kvm_x86_remove_msi_route(virq);
6359 QLIST_REMOVE(entry, list);
6360 g_free(entry);
6361 break;
6362 }
6363 }
6364 return 0;
6365 }
6366
kvm_arch_msi_data_to_gsi(uint32_t data)6367 int kvm_arch_msi_data_to_gsi(uint32_t data)
6368 {
6369 abort();
6370 }
6371
kvm_has_waitpkg(void)6372 bool kvm_has_waitpkg(void)
6373 {
6374 return has_msr_umwait;
6375 }
6376
6377 #define ARCH_REQ_XCOMP_GUEST_PERM 0x1025
6378
kvm_request_xsave_components(X86CPU * cpu,uint64_t mask)6379 void kvm_request_xsave_components(X86CPU *cpu, uint64_t mask)
6380 {
6381 KVMState *s = kvm_state;
6382 uint64_t supported;
6383
6384 mask &= XSTATE_DYNAMIC_MASK;
6385 if (!mask) {
6386 return;
6387 }
6388 /*
6389 * Just ignore bits that are not in CPUID[EAX=0xD,ECX=0].
6390 * ARCH_REQ_XCOMP_GUEST_PERM would fail, and QEMU has warned
6391 * about them already because they are not supported features.
6392 */
6393 supported = kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX);
6394 supported |= (uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32;
6395 mask &= supported;
6396
6397 while (mask) {
6398 int bit = ctz64(mask);
6399 int rc = syscall(SYS_arch_prctl, ARCH_REQ_XCOMP_GUEST_PERM, bit);
6400 if (rc) {
6401 /*
6402 * Older kernel version (<5.17) do not support
6403 * ARCH_REQ_XCOMP_GUEST_PERM, but also do not return
6404 * any dynamic feature from kvm_arch_get_supported_cpuid.
6405 */
6406 warn_report("prctl(ARCH_REQ_XCOMP_GUEST_PERM) failure "
6407 "for feature bit %d", bit);
6408 }
6409 mask &= ~BIT_ULL(bit);
6410 }
6411 }
6412
kvm_arch_get_notify_vmexit(Object * obj,Error ** errp)6413 static int kvm_arch_get_notify_vmexit(Object *obj, Error **errp)
6414 {
6415 KVMState *s = KVM_STATE(obj);
6416 return s->notify_vmexit;
6417 }
6418
kvm_arch_set_notify_vmexit(Object * obj,int value,Error ** errp)6419 static void kvm_arch_set_notify_vmexit(Object *obj, int value, Error **errp)
6420 {
6421 KVMState *s = KVM_STATE(obj);
6422
6423 if (s->fd != -1) {
6424 error_setg(errp, "Cannot set properties after the accelerator has been initialized");
6425 return;
6426 }
6427
6428 s->notify_vmexit = value;
6429 }
6430
kvm_arch_get_notify_window(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6431 static void kvm_arch_get_notify_window(Object *obj, Visitor *v,
6432 const char *name, void *opaque,
6433 Error **errp)
6434 {
6435 KVMState *s = KVM_STATE(obj);
6436 uint32_t value = s->notify_window;
6437
6438 visit_type_uint32(v, name, &value, errp);
6439 }
6440
kvm_arch_set_notify_window(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6441 static void kvm_arch_set_notify_window(Object *obj, Visitor *v,
6442 const char *name, void *opaque,
6443 Error **errp)
6444 {
6445 KVMState *s = KVM_STATE(obj);
6446 uint32_t value;
6447
6448 if (s->fd != -1) {
6449 error_setg(errp, "Cannot set properties after the accelerator has been initialized");
6450 return;
6451 }
6452
6453 if (!visit_type_uint32(v, name, &value, errp)) {
6454 return;
6455 }
6456
6457 s->notify_window = value;
6458 }
6459
kvm_arch_get_xen_version(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6460 static void kvm_arch_get_xen_version(Object *obj, Visitor *v,
6461 const char *name, void *opaque,
6462 Error **errp)
6463 {
6464 KVMState *s = KVM_STATE(obj);
6465 uint32_t value = s->xen_version;
6466
6467 visit_type_uint32(v, name, &value, errp);
6468 }
6469
kvm_arch_set_xen_version(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6470 static void kvm_arch_set_xen_version(Object *obj, Visitor *v,
6471 const char *name, void *opaque,
6472 Error **errp)
6473 {
6474 KVMState *s = KVM_STATE(obj);
6475 Error *error = NULL;
6476 uint32_t value;
6477
6478 visit_type_uint32(v, name, &value, &error);
6479 if (error) {
6480 error_propagate(errp, error);
6481 return;
6482 }
6483
6484 s->xen_version = value;
6485 if (value && xen_mode == XEN_DISABLED) {
6486 xen_mode = XEN_EMULATE;
6487 }
6488 }
6489
kvm_arch_get_xen_gnttab_max_frames(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6490 static void kvm_arch_get_xen_gnttab_max_frames(Object *obj, Visitor *v,
6491 const char *name, void *opaque,
6492 Error **errp)
6493 {
6494 KVMState *s = KVM_STATE(obj);
6495 uint16_t value = s->xen_gnttab_max_frames;
6496
6497 visit_type_uint16(v, name, &value, errp);
6498 }
6499
kvm_arch_set_xen_gnttab_max_frames(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6500 static void kvm_arch_set_xen_gnttab_max_frames(Object *obj, Visitor *v,
6501 const char *name, void *opaque,
6502 Error **errp)
6503 {
6504 KVMState *s = KVM_STATE(obj);
6505 Error *error = NULL;
6506 uint16_t value;
6507
6508 visit_type_uint16(v, name, &value, &error);
6509 if (error) {
6510 error_propagate(errp, error);
6511 return;
6512 }
6513
6514 s->xen_gnttab_max_frames = value;
6515 }
6516
kvm_arch_get_xen_evtchn_max_pirq(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6517 static void kvm_arch_get_xen_evtchn_max_pirq(Object *obj, Visitor *v,
6518 const char *name, void *opaque,
6519 Error **errp)
6520 {
6521 KVMState *s = KVM_STATE(obj);
6522 uint16_t value = s->xen_evtchn_max_pirq;
6523
6524 visit_type_uint16(v, name, &value, errp);
6525 }
6526
kvm_arch_set_xen_evtchn_max_pirq(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6527 static void kvm_arch_set_xen_evtchn_max_pirq(Object *obj, Visitor *v,
6528 const char *name, void *opaque,
6529 Error **errp)
6530 {
6531 KVMState *s = KVM_STATE(obj);
6532 Error *error = NULL;
6533 uint16_t value;
6534
6535 visit_type_uint16(v, name, &value, &error);
6536 if (error) {
6537 error_propagate(errp, error);
6538 return;
6539 }
6540
6541 s->xen_evtchn_max_pirq = value;
6542 }
6543
kvm_arch_accel_class_init(ObjectClass * oc)6544 void kvm_arch_accel_class_init(ObjectClass *oc)
6545 {
6546 object_class_property_add_enum(oc, "notify-vmexit", "NotifyVMexitOption",
6547 &NotifyVmexitOption_lookup,
6548 kvm_arch_get_notify_vmexit,
6549 kvm_arch_set_notify_vmexit);
6550 object_class_property_set_description(oc, "notify-vmexit",
6551 "Enable notify VM exit");
6552
6553 object_class_property_add(oc, "notify-window", "uint32",
6554 kvm_arch_get_notify_window,
6555 kvm_arch_set_notify_window,
6556 NULL, NULL);
6557 object_class_property_set_description(oc, "notify-window",
6558 "Clock cycles without an event window "
6559 "after which a notification VM exit occurs");
6560
6561 object_class_property_add(oc, "xen-version", "uint32",
6562 kvm_arch_get_xen_version,
6563 kvm_arch_set_xen_version,
6564 NULL, NULL);
6565 object_class_property_set_description(oc, "xen-version",
6566 "Xen version to be emulated "
6567 "(in XENVER_version form "
6568 "e.g. 0x4000a for 4.10)");
6569
6570 object_class_property_add(oc, "xen-gnttab-max-frames", "uint16",
6571 kvm_arch_get_xen_gnttab_max_frames,
6572 kvm_arch_set_xen_gnttab_max_frames,
6573 NULL, NULL);
6574 object_class_property_set_description(oc, "xen-gnttab-max-frames",
6575 "Maximum number of grant table frames");
6576
6577 object_class_property_add(oc, "xen-evtchn-max-pirq", "uint16",
6578 kvm_arch_get_xen_evtchn_max_pirq,
6579 kvm_arch_set_xen_evtchn_max_pirq,
6580 NULL, NULL);
6581 object_class_property_set_description(oc, "xen-evtchn-max-pirq",
6582 "Maximum number of Xen PIRQs");
6583 }
6584
kvm_set_max_apic_id(uint32_t max_apic_id)6585 void kvm_set_max_apic_id(uint32_t max_apic_id)
6586 {
6587 kvm_vm_enable_cap(kvm_state, KVM_CAP_MAX_VCPU_ID, 0, max_apic_id);
6588 }
6589