1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/acpi.h>
7 #include <linux/time.h>
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/interconnect.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/platform_device.h>
14 #include <linux/phy/phy.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/reset-controller.h>
17 #include <linux/devfreq.h>
18
19 #include <soc/qcom/ice.h>
20
21 #include <ufs/ufshcd.h>
22 #include "ufshcd-pltfrm.h"
23 #include <ufs/unipro.h>
24 #include "ufs-qcom.h"
25 #include <ufs/ufshci.h>
26 #include <ufs/ufs_quirks.h>
27
28 #define MCQ_QCFGPTR_MASK GENMASK(7, 0)
29 #define MCQ_QCFGPTR_UNIT 0x200
30 #define MCQ_SQATTR_OFFSET(c) \
31 ((((c) >> 16) & MCQ_QCFGPTR_MASK) * MCQ_QCFGPTR_UNIT)
32 #define MCQ_QCFG_SIZE 0x40
33
34 enum {
35 TSTBUS_UAWM,
36 TSTBUS_UARM,
37 TSTBUS_TXUC,
38 TSTBUS_RXUC,
39 TSTBUS_DFC,
40 TSTBUS_TRLUT,
41 TSTBUS_TMRLUT,
42 TSTBUS_OCSC,
43 TSTBUS_UTP_HCI,
44 TSTBUS_COMBINED,
45 TSTBUS_WRAPPER,
46 TSTBUS_UNIPRO,
47 TSTBUS_MAX,
48 };
49
50 #define QCOM_UFS_MAX_GEAR 5
51 #define QCOM_UFS_MAX_LANE 2
52
53 enum {
54 MODE_MIN,
55 MODE_PWM,
56 MODE_HS_RA,
57 MODE_HS_RB,
58 MODE_MAX,
59 };
60
61 static const struct __ufs_qcom_bw_table {
62 u32 mem_bw;
63 u32 cfg_bw;
64 } ufs_qcom_bw_table[MODE_MAX + 1][QCOM_UFS_MAX_GEAR + 1][QCOM_UFS_MAX_LANE + 1] = {
65 [MODE_MIN][0][0] = { 0, 0 }, /* Bandwidth values in KB/s */
66 [MODE_PWM][UFS_PWM_G1][UFS_LANE_1] = { 922, 1000 },
67 [MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844, 1000 },
68 [MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688, 1000 },
69 [MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376, 1000 },
70 [MODE_PWM][UFS_PWM_G5][UFS_LANE_1] = { 14752, 1000 },
71 [MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844, 1000 },
72 [MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688, 1000 },
73 [MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376, 1000 },
74 [MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752, 1000 },
75 [MODE_PWM][UFS_PWM_G5][UFS_LANE_2] = { 29504, 1000 },
76 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796, 1000 },
77 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591, 1000 },
78 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 },
79 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 },
80 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 },
81 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591, 1000 },
82 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181, 1000 },
83 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 },
84 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 },
85 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 },
86 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422, 1000 },
87 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189, 1000 },
88 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 },
89 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 },
90 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 },
91 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189, 1000 },
92 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378, 1000 },
93 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 },
94 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 },
95 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 },
96 [MODE_MAX][0][0] = { 7643136, 819200 },
97 };
98
99 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS];
100
101 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
102 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
103 u32 clk_cycles);
104
rcdev_to_ufs_host(struct reset_controller_dev * rcd)105 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
106 {
107 return container_of(rcd, struct ufs_qcom_host, rcdev);
108 }
109
110 #ifdef CONFIG_SCSI_UFS_CRYPTO
111
ufs_qcom_ice_enable(struct ufs_qcom_host * host)112 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host)
113 {
114 if (host->hba->caps & UFSHCD_CAP_CRYPTO)
115 qcom_ice_enable(host->ice);
116 }
117
ufs_qcom_ice_init(struct ufs_qcom_host * host)118 static int ufs_qcom_ice_init(struct ufs_qcom_host *host)
119 {
120 struct ufs_hba *hba = host->hba;
121 struct device *dev = hba->dev;
122 struct qcom_ice *ice;
123
124 ice = of_qcom_ice_get(dev);
125 if (ice == ERR_PTR(-EOPNOTSUPP)) {
126 dev_warn(dev, "Disabling inline encryption support\n");
127 ice = NULL;
128 }
129
130 if (IS_ERR_OR_NULL(ice))
131 return PTR_ERR_OR_ZERO(ice);
132
133 host->ice = ice;
134 hba->caps |= UFSHCD_CAP_CRYPTO;
135
136 return 0;
137 }
138
ufs_qcom_ice_resume(struct ufs_qcom_host * host)139 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
140 {
141 if (host->hba->caps & UFSHCD_CAP_CRYPTO)
142 return qcom_ice_resume(host->ice);
143
144 return 0;
145 }
146
ufs_qcom_ice_suspend(struct ufs_qcom_host * host)147 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host)
148 {
149 if (host->hba->caps & UFSHCD_CAP_CRYPTO)
150 return qcom_ice_suspend(host->ice);
151
152 return 0;
153 }
154
ufs_qcom_ice_program_key(struct ufs_hba * hba,const union ufs_crypto_cfg_entry * cfg,int slot)155 static int ufs_qcom_ice_program_key(struct ufs_hba *hba,
156 const union ufs_crypto_cfg_entry *cfg,
157 int slot)
158 {
159 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
160 union ufs_crypto_cap_entry cap;
161 bool config_enable =
162 cfg->config_enable & UFS_CRYPTO_CONFIGURATION_ENABLE;
163
164 /* Only AES-256-XTS has been tested so far. */
165 cap = hba->crypto_cap_array[cfg->crypto_cap_idx];
166 if (cap.algorithm_id != UFS_CRYPTO_ALG_AES_XTS ||
167 cap.key_size != UFS_CRYPTO_KEY_SIZE_256)
168 return -EOPNOTSUPP;
169
170 if (config_enable)
171 return qcom_ice_program_key(host->ice,
172 QCOM_ICE_CRYPTO_ALG_AES_XTS,
173 QCOM_ICE_CRYPTO_KEY_SIZE_256,
174 cfg->crypto_key,
175 cfg->data_unit_size, slot);
176 else
177 return qcom_ice_evict_key(host->ice, slot);
178 }
179
180 #else
181
182 #define ufs_qcom_ice_program_key NULL
183
ufs_qcom_ice_enable(struct ufs_qcom_host * host)184 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host)
185 {
186 }
187
ufs_qcom_ice_init(struct ufs_qcom_host * host)188 static int ufs_qcom_ice_init(struct ufs_qcom_host *host)
189 {
190 return 0;
191 }
192
ufs_qcom_ice_resume(struct ufs_qcom_host * host)193 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
194 {
195 return 0;
196 }
197
ufs_qcom_ice_suspend(struct ufs_qcom_host * host)198 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host)
199 {
200 return 0;
201 }
202 #endif
203
ufs_qcom_host_clk_get(struct device * dev,const char * name,struct clk ** clk_out,bool optional)204 static int ufs_qcom_host_clk_get(struct device *dev,
205 const char *name, struct clk **clk_out, bool optional)
206 {
207 struct clk *clk;
208 int err = 0;
209
210 clk = devm_clk_get(dev, name);
211 if (!IS_ERR(clk)) {
212 *clk_out = clk;
213 return 0;
214 }
215
216 err = PTR_ERR(clk);
217
218 if (optional && err == -ENOENT) {
219 *clk_out = NULL;
220 return 0;
221 }
222
223 if (err != -EPROBE_DEFER)
224 dev_err(dev, "failed to get %s err %d\n", name, err);
225
226 return err;
227 }
228
ufs_qcom_host_clk_enable(struct device * dev,const char * name,struct clk * clk)229 static int ufs_qcom_host_clk_enable(struct device *dev,
230 const char *name, struct clk *clk)
231 {
232 int err = 0;
233
234 err = clk_prepare_enable(clk);
235 if (err)
236 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err);
237
238 return err;
239 }
240
ufs_qcom_disable_lane_clks(struct ufs_qcom_host * host)241 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
242 {
243 if (!host->is_lane_clks_enabled)
244 return;
245
246 clk_disable_unprepare(host->tx_l1_sync_clk);
247 clk_disable_unprepare(host->tx_l0_sync_clk);
248 clk_disable_unprepare(host->rx_l1_sync_clk);
249 clk_disable_unprepare(host->rx_l0_sync_clk);
250
251 host->is_lane_clks_enabled = false;
252 }
253
ufs_qcom_enable_lane_clks(struct ufs_qcom_host * host)254 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
255 {
256 int err;
257 struct device *dev = host->hba->dev;
258
259 if (host->is_lane_clks_enabled)
260 return 0;
261
262 err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
263 host->rx_l0_sync_clk);
264 if (err)
265 return err;
266
267 err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
268 host->tx_l0_sync_clk);
269 if (err)
270 goto disable_rx_l0;
271
272 err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk",
273 host->rx_l1_sync_clk);
274 if (err)
275 goto disable_tx_l0;
276
277 err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk",
278 host->tx_l1_sync_clk);
279 if (err)
280 goto disable_rx_l1;
281
282 host->is_lane_clks_enabled = true;
283
284 return 0;
285
286 disable_rx_l1:
287 clk_disable_unprepare(host->rx_l1_sync_clk);
288 disable_tx_l0:
289 clk_disable_unprepare(host->tx_l0_sync_clk);
290 disable_rx_l0:
291 clk_disable_unprepare(host->rx_l0_sync_clk);
292
293 return err;
294 }
295
ufs_qcom_init_lane_clks(struct ufs_qcom_host * host)296 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
297 {
298 int err = 0;
299 struct device *dev = host->hba->dev;
300
301 if (has_acpi_companion(dev))
302 return 0;
303
304 err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk",
305 &host->rx_l0_sync_clk, false);
306 if (err)
307 return err;
308
309 err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk",
310 &host->tx_l0_sync_clk, false);
311 if (err)
312 return err;
313
314 /* In case of single lane per direction, don't read lane1 clocks */
315 if (host->hba->lanes_per_direction > 1) {
316 err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
317 &host->rx_l1_sync_clk, false);
318 if (err)
319 return err;
320
321 err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
322 &host->tx_l1_sync_clk, true);
323 }
324
325 return 0;
326 }
327
ufs_qcom_check_hibern8(struct ufs_hba * hba)328 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
329 {
330 int err;
331 u32 tx_fsm_val = 0;
332 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
333
334 do {
335 err = ufshcd_dme_get(hba,
336 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
337 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
338 &tx_fsm_val);
339 if (err || tx_fsm_val == TX_FSM_HIBERN8)
340 break;
341
342 /* sleep for max. 200us */
343 usleep_range(100, 200);
344 } while (time_before(jiffies, timeout));
345
346 /*
347 * we might have scheduled out for long during polling so
348 * check the state again.
349 */
350 if (time_after(jiffies, timeout))
351 err = ufshcd_dme_get(hba,
352 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
353 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
354 &tx_fsm_val);
355
356 if (err) {
357 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
358 __func__, err);
359 } else if (tx_fsm_val != TX_FSM_HIBERN8) {
360 err = tx_fsm_val;
361 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
362 __func__, err);
363 }
364
365 return err;
366 }
367
ufs_qcom_select_unipro_mode(struct ufs_qcom_host * host)368 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
369 {
370 ufshcd_rmwl(host->hba, QUNIPRO_SEL,
371 ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0,
372 REG_UFS_CFG1);
373
374 if (host->hw_ver.major >= 0x05)
375 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0);
376 }
377
378 /*
379 * ufs_qcom_host_reset - reset host controller and PHY
380 */
ufs_qcom_host_reset(struct ufs_hba * hba)381 static int ufs_qcom_host_reset(struct ufs_hba *hba)
382 {
383 int ret = 0;
384 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
385 bool reenable_intr = false;
386
387 if (!host->core_reset) {
388 dev_warn(hba->dev, "%s: reset control not set\n", __func__);
389 return 0;
390 }
391
392 reenable_intr = hba->is_irq_enabled;
393 disable_irq(hba->irq);
394 hba->is_irq_enabled = false;
395
396 ret = reset_control_assert(host->core_reset);
397 if (ret) {
398 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",
399 __func__, ret);
400 return ret;
401 }
402
403 /*
404 * The hardware requirement for delay between assert/deassert
405 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
406 * ~125us (4/32768). To be on the safe side add 200us delay.
407 */
408 usleep_range(200, 210);
409
410 ret = reset_control_deassert(host->core_reset);
411 if (ret)
412 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n",
413 __func__, ret);
414
415 usleep_range(1000, 1100);
416
417 if (reenable_intr) {
418 enable_irq(hba->irq);
419 hba->is_irq_enabled = true;
420 }
421
422 return 0;
423 }
424
ufs_qcom_get_hs_gear(struct ufs_hba * hba)425 static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
426 {
427 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
428
429 if (host->hw_ver.major == 0x1) {
430 /*
431 * HS-G3 operations may not reliably work on legacy QCOM
432 * UFS host controller hardware even though capability
433 * exchange during link startup phase may end up
434 * negotiating maximum supported gear as G3.
435 * Hence downgrade the maximum supported gear to HS-G2.
436 */
437 return UFS_HS_G2;
438 } else if (host->hw_ver.major >= 0x4) {
439 return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0));
440 }
441
442 /* Default is HS-G3 */
443 return UFS_HS_G3;
444 }
445
ufs_qcom_power_up_sequence(struct ufs_hba * hba)446 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
447 {
448 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
449 struct phy *phy = host->generic_phy;
450 int ret;
451
452 /* Reset UFS Host Controller and PHY */
453 ret = ufs_qcom_host_reset(hba);
454 if (ret)
455 dev_warn(hba->dev, "%s: host reset returned %d\n",
456 __func__, ret);
457
458 if (phy->power_count) {
459 phy_power_off(phy);
460 phy_exit(phy);
461 }
462
463 /* phy initialization - calibrate the phy */
464 ret = phy_init(phy);
465 if (ret) {
466 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
467 __func__, ret);
468 return ret;
469 }
470
471 phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->hs_gear);
472
473 /* power on phy - start serdes and phy's power and clocks */
474 ret = phy_power_on(phy);
475 if (ret) {
476 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
477 __func__, ret);
478 goto out_disable_phy;
479 }
480
481 ufs_qcom_select_unipro_mode(host);
482
483 return 0;
484
485 out_disable_phy:
486 phy_exit(phy);
487
488 return ret;
489 }
490
491 /*
492 * The UTP controller has a number of internal clock gating cells (CGCs).
493 * Internal hardware sub-modules within the UTP controller control the CGCs.
494 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
495 * in a specific operation, UTP controller CGCs are by default disabled and
496 * this function enables them (after every UFS link startup) to save some power
497 * leakage.
498 */
ufs_qcom_enable_hw_clk_gating(struct ufs_hba * hba)499 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
500 {
501 ufshcd_writel(hba,
502 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL,
503 REG_UFS_CFG2);
504
505 /* Ensure that HW clock gating is enabled before next operations */
506 ufshcd_readl(hba, REG_UFS_CFG2);
507 }
508
ufs_qcom_hce_enable_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)509 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
510 enum ufs_notify_change_status status)
511 {
512 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
513 int err = 0;
514
515 switch (status) {
516 case PRE_CHANGE:
517 ufs_qcom_power_up_sequence(hba);
518 /*
519 * The PHY PLL output is the source of tx/rx lane symbol
520 * clocks, hence, enable the lane clocks only after PHY
521 * is initialized.
522 */
523 err = ufs_qcom_enable_lane_clks(host);
524 break;
525 case POST_CHANGE:
526 /* check if UFS PHY moved from DISABLED to HIBERN8 */
527 err = ufs_qcom_check_hibern8(hba);
528 ufs_qcom_enable_hw_clk_gating(hba);
529 ufs_qcom_ice_enable(host);
530 break;
531 default:
532 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
533 err = -EINVAL;
534 break;
535 }
536 return err;
537 }
538
539 /*
540 * Return: zero for success and non-zero in case of a failure.
541 */
ufs_qcom_cfg_timers(struct ufs_hba * hba,u32 gear,u32 hs,u32 rate,bool update_link_startup_timer)542 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
543 u32 hs, u32 rate, bool update_link_startup_timer)
544 {
545 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
546 struct ufs_clk_info *clki;
547 u32 core_clk_period_in_ns;
548 u32 tx_clk_cycles_per_us = 0;
549 unsigned long core_clk_rate = 0;
550 u32 core_clk_cycles_per_us = 0;
551
552 static u32 pwm_fr_table[][2] = {
553 {UFS_PWM_G1, 0x1},
554 {UFS_PWM_G2, 0x1},
555 {UFS_PWM_G3, 0x1},
556 {UFS_PWM_G4, 0x1},
557 };
558
559 static u32 hs_fr_table_rA[][2] = {
560 {UFS_HS_G1, 0x1F},
561 {UFS_HS_G2, 0x3e},
562 {UFS_HS_G3, 0x7D},
563 };
564
565 static u32 hs_fr_table_rB[][2] = {
566 {UFS_HS_G1, 0x24},
567 {UFS_HS_G2, 0x49},
568 {UFS_HS_G3, 0x92},
569 };
570
571 /*
572 * The Qunipro controller does not use following registers:
573 * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG &
574 * UFS_REG_PA_LINK_STARTUP_TIMER
575 * But UTP controller uses SYS1CLK_1US_REG register for Interrupt
576 * Aggregation logic.
577 */
578 if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
579 return 0;
580
581 if (gear == 0) {
582 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
583 return -EINVAL;
584 }
585
586 list_for_each_entry(clki, &hba->clk_list_head, list) {
587 if (!strcmp(clki->name, "core_clk"))
588 core_clk_rate = clk_get_rate(clki->clk);
589 }
590
591 /* If frequency is smaller than 1MHz, set to 1MHz */
592 if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
593 core_clk_rate = DEFAULT_CLK_RATE_HZ;
594
595 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
596 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
597 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
598 /*
599 * make sure above write gets applied before we return from
600 * this function.
601 */
602 ufshcd_readl(hba, REG_UFS_SYS1CLK_1US);
603 }
604
605 if (ufs_qcom_cap_qunipro(host))
606 return 0;
607
608 core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
609 core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
610 core_clk_period_in_ns &= MASK_CLK_NS_REG;
611
612 switch (hs) {
613 case FASTAUTO_MODE:
614 case FAST_MODE:
615 if (rate == PA_HS_MODE_A) {
616 if (gear > ARRAY_SIZE(hs_fr_table_rA)) {
617 dev_err(hba->dev,
618 "%s: index %d exceeds table size %zu\n",
619 __func__, gear,
620 ARRAY_SIZE(hs_fr_table_rA));
621 return -EINVAL;
622 }
623 tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
624 } else if (rate == PA_HS_MODE_B) {
625 if (gear > ARRAY_SIZE(hs_fr_table_rB)) {
626 dev_err(hba->dev,
627 "%s: index %d exceeds table size %zu\n",
628 __func__, gear,
629 ARRAY_SIZE(hs_fr_table_rB));
630 return -EINVAL;
631 }
632 tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
633 } else {
634 dev_err(hba->dev, "%s: invalid rate = %d\n",
635 __func__, rate);
636 return -EINVAL;
637 }
638 break;
639 case SLOWAUTO_MODE:
640 case SLOW_MODE:
641 if (gear > ARRAY_SIZE(pwm_fr_table)) {
642 dev_err(hba->dev,
643 "%s: index %d exceeds table size %zu\n",
644 __func__, gear,
645 ARRAY_SIZE(pwm_fr_table));
646 return -EINVAL;
647 }
648 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
649 break;
650 case UNCHANGED:
651 default:
652 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
653 return -EINVAL;
654 }
655
656 if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=
657 (core_clk_period_in_ns | tx_clk_cycles_per_us)) {
658 /* this register 2 fields shall be written at once */
659 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us,
660 REG_UFS_TX_SYMBOL_CLK_NS_US);
661 /*
662 * make sure above write gets applied before we return from
663 * this function.
664 */
665 mb();
666 }
667
668 if (update_link_startup_timer && host->hw_ver.major != 0x5) {
669 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100),
670 REG_UFS_CFG0);
671 /*
672 * make sure that this configuration is applied before
673 * we return
674 */
675 mb();
676 }
677
678 return 0;
679 }
680
ufs_qcom_link_startup_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)681 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
682 enum ufs_notify_change_status status)
683 {
684 int err = 0;
685 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
686
687 switch (status) {
688 case PRE_CHANGE:
689 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
690 0, true)) {
691 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
692 __func__);
693 return -EINVAL;
694 }
695
696 if (ufs_qcom_cap_qunipro(host))
697 /*
698 * set unipro core clock cycles to 150 & clear clock
699 * divider
700 */
701 err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba,
702 150);
703
704 /*
705 * Some UFS devices (and may be host) have issues if LCC is
706 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
707 * before link startup which will make sure that both host
708 * and device TX LCC are disabled once link startup is
709 * completed.
710 */
711 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41)
712 err = ufshcd_disable_host_tx_lcc(hba);
713
714 break;
715 default:
716 break;
717 }
718
719 return err;
720 }
721
ufs_qcom_device_reset_ctrl(struct ufs_hba * hba,bool asserted)722 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted)
723 {
724 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
725
726 /* reset gpio is optional */
727 if (!host->device_reset)
728 return;
729
730 gpiod_set_value_cansleep(host->device_reset, asserted);
731 }
732
ufs_qcom_suspend(struct ufs_hba * hba,enum ufs_pm_op pm_op,enum ufs_notify_change_status status)733 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
734 enum ufs_notify_change_status status)
735 {
736 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
737 struct phy *phy = host->generic_phy;
738
739 if (status == PRE_CHANGE)
740 return 0;
741
742 if (ufs_qcom_is_link_off(hba)) {
743 /*
744 * Disable the tx/rx lane symbol clocks before PHY is
745 * powered down as the PLL source should be disabled
746 * after downstream clocks are disabled.
747 */
748 ufs_qcom_disable_lane_clks(host);
749 phy_power_off(phy);
750
751 /* reset the connected UFS device during power down */
752 ufs_qcom_device_reset_ctrl(hba, true);
753
754 } else if (!ufs_qcom_is_link_active(hba)) {
755 ufs_qcom_disable_lane_clks(host);
756 }
757
758 return ufs_qcom_ice_suspend(host);
759 }
760
ufs_qcom_resume(struct ufs_hba * hba,enum ufs_pm_op pm_op)761 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
762 {
763 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
764 struct phy *phy = host->generic_phy;
765 int err;
766
767 if (ufs_qcom_is_link_off(hba)) {
768 err = phy_power_on(phy);
769 if (err) {
770 dev_err(hba->dev, "%s: failed PHY power on: %d\n",
771 __func__, err);
772 return err;
773 }
774
775 err = ufs_qcom_enable_lane_clks(host);
776 if (err)
777 return err;
778
779 } else if (!ufs_qcom_is_link_active(hba)) {
780 err = ufs_qcom_enable_lane_clks(host);
781 if (err)
782 return err;
783 }
784
785 return ufs_qcom_ice_resume(host);
786 }
787
ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host * host,bool enable)788 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
789 {
790 if (host->dev_ref_clk_ctrl_mmio &&
791 (enable ^ host->is_dev_ref_clk_enabled)) {
792 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
793
794 if (enable)
795 temp |= host->dev_ref_clk_en_mask;
796 else
797 temp &= ~host->dev_ref_clk_en_mask;
798
799 /*
800 * If we are here to disable this clock it might be immediately
801 * after entering into hibern8 in which case we need to make
802 * sure that device ref_clk is active for specific time after
803 * hibern8 enter.
804 */
805 if (!enable) {
806 unsigned long gating_wait;
807
808 gating_wait = host->hba->dev_info.clk_gating_wait_us;
809 if (!gating_wait) {
810 udelay(1);
811 } else {
812 /*
813 * bRefClkGatingWaitTime defines the minimum
814 * time for which the reference clock is
815 * required by device during transition from
816 * HS-MODE to LS-MODE or HIBERN8 state. Give it
817 * more delay to be on the safe side.
818 */
819 gating_wait += 10;
820 usleep_range(gating_wait, gating_wait + 10);
821 }
822 }
823
824 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
825
826 /*
827 * Make sure the write to ref_clk reaches the destination and
828 * not stored in a Write Buffer (WB).
829 */
830 readl(host->dev_ref_clk_ctrl_mmio);
831
832 /*
833 * If we call hibern8 exit after this, we need to make sure that
834 * device ref_clk is stable for at least 1us before the hibern8
835 * exit command.
836 */
837 if (enable)
838 udelay(1);
839
840 host->is_dev_ref_clk_enabled = enable;
841 }
842 }
843
ufs_qcom_icc_set_bw(struct ufs_qcom_host * host,u32 mem_bw,u32 cfg_bw)844 static int ufs_qcom_icc_set_bw(struct ufs_qcom_host *host, u32 mem_bw, u32 cfg_bw)
845 {
846 struct device *dev = host->hba->dev;
847 int ret;
848
849 ret = icc_set_bw(host->icc_ddr, 0, mem_bw);
850 if (ret < 0) {
851 dev_err(dev, "failed to set bandwidth request: %d\n", ret);
852 return ret;
853 }
854
855 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw);
856 if (ret < 0) {
857 dev_err(dev, "failed to set bandwidth request: %d\n", ret);
858 return ret;
859 }
860
861 return 0;
862 }
863
ufs_qcom_get_bw_table(struct ufs_qcom_host * host)864 static struct __ufs_qcom_bw_table ufs_qcom_get_bw_table(struct ufs_qcom_host *host)
865 {
866 struct ufs_pa_layer_attr *p = &host->dev_req_params;
867 int gear = max_t(u32, p->gear_rx, p->gear_tx);
868 int lane = max_t(u32, p->lane_rx, p->lane_tx);
869
870 if (ufshcd_is_hs_mode(p)) {
871 if (p->hs_rate == PA_HS_MODE_B)
872 return ufs_qcom_bw_table[MODE_HS_RB][gear][lane];
873 else
874 return ufs_qcom_bw_table[MODE_HS_RA][gear][lane];
875 } else {
876 return ufs_qcom_bw_table[MODE_PWM][gear][lane];
877 }
878 }
879
ufs_qcom_icc_update_bw(struct ufs_qcom_host * host)880 static int ufs_qcom_icc_update_bw(struct ufs_qcom_host *host)
881 {
882 struct __ufs_qcom_bw_table bw_table;
883
884 bw_table = ufs_qcom_get_bw_table(host);
885
886 return ufs_qcom_icc_set_bw(host, bw_table.mem_bw, bw_table.cfg_bw);
887 }
888
ufs_qcom_pwr_change_notify(struct ufs_hba * hba,enum ufs_notify_change_status status,struct ufs_pa_layer_attr * dev_max_params,struct ufs_pa_layer_attr * dev_req_params)889 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
890 enum ufs_notify_change_status status,
891 struct ufs_pa_layer_attr *dev_max_params,
892 struct ufs_pa_layer_attr *dev_req_params)
893 {
894 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
895 struct ufs_dev_params ufs_qcom_cap;
896 int ret = 0;
897
898 if (!dev_req_params) {
899 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
900 return -EINVAL;
901 }
902
903 switch (status) {
904 case PRE_CHANGE:
905 ufshcd_init_pwr_dev_param(&ufs_qcom_cap);
906 ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
907
908 /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
909 ufs_qcom_cap.hs_tx_gear = ufs_qcom_cap.hs_rx_gear = ufs_qcom_get_hs_gear(hba);
910
911 ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap,
912 dev_max_params,
913 dev_req_params);
914 if (ret) {
915 dev_err(hba->dev, "%s: failed to determine capabilities\n",
916 __func__);
917 return ret;
918 }
919
920 /*
921 * Update hs_gear only when the gears are scaled to a higher value. This is because,
922 * the PHY gear settings are backwards compatible and we only need to change the PHY
923 * settings while scaling to higher gears.
924 */
925 if (dev_req_params->gear_tx > host->hs_gear)
926 host->hs_gear = dev_req_params->gear_tx;
927
928 /* enable the device ref clock before changing to HS mode */
929 if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
930 ufshcd_is_hs_mode(dev_req_params))
931 ufs_qcom_dev_ref_clk_ctrl(host, true);
932
933 if (host->hw_ver.major >= 0x4) {
934 ufshcd_dme_configure_adapt(hba,
935 dev_req_params->gear_tx,
936 PA_INITIAL_ADAPT);
937 }
938 break;
939 case POST_CHANGE:
940 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
941 dev_req_params->pwr_rx,
942 dev_req_params->hs_rate, false)) {
943 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
944 __func__);
945 /*
946 * we return error code at the end of the routine,
947 * but continue to configure UFS_PHY_TX_LANE_ENABLE
948 * and bus voting as usual
949 */
950 ret = -EINVAL;
951 }
952
953 /* cache the power mode parameters to use internally */
954 memcpy(&host->dev_req_params,
955 dev_req_params, sizeof(*dev_req_params));
956
957 ufs_qcom_icc_update_bw(host);
958
959 /* disable the device ref clock if entered PWM mode */
960 if (ufshcd_is_hs_mode(&hba->pwr_info) &&
961 !ufshcd_is_hs_mode(dev_req_params))
962 ufs_qcom_dev_ref_clk_ctrl(host, false);
963 break;
964 default:
965 ret = -EINVAL;
966 break;
967 }
968
969 return ret;
970 }
971
ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba * hba)972 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
973 {
974 int err;
975 u32 pa_vs_config_reg1;
976
977 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
978 &pa_vs_config_reg1);
979 if (err)
980 return err;
981
982 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
983 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
984 (pa_vs_config_reg1 | (1 << 12)));
985 }
986
ufs_qcom_apply_dev_quirks(struct ufs_hba * hba)987 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
988 {
989 int err = 0;
990
991 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
992 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
993
994 if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC)
995 hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE;
996
997 return err;
998 }
999
ufs_qcom_get_ufs_hci_version(struct ufs_hba * hba)1000 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
1001 {
1002 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1003
1004 if (host->hw_ver.major == 0x1)
1005 return ufshci_version(1, 1);
1006 else
1007 return ufshci_version(2, 0);
1008 }
1009
1010 /**
1011 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
1012 * @hba: host controller instance
1013 *
1014 * QCOM UFS host controller might have some non standard behaviours (quirks)
1015 * than what is specified by UFSHCI specification. Advertise all such
1016 * quirks to standard UFS host controller driver so standard takes them into
1017 * account.
1018 */
ufs_qcom_advertise_quirks(struct ufs_hba * hba)1019 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
1020 {
1021 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1022
1023 if (host->hw_ver.major == 0x01) {
1024 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
1025 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
1026 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE;
1027
1028 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001)
1029 hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR;
1030
1031 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
1032 }
1033
1034 if (host->hw_ver.major == 0x2) {
1035 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
1036
1037 if (!ufs_qcom_cap_qunipro(host))
1038 /* Legacy UniPro mode still need following quirks */
1039 hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
1040 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
1041 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP);
1042 }
1043
1044 if (host->hw_ver.major > 0x3)
1045 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
1046 }
1047
ufs_qcom_set_caps(struct ufs_hba * hba)1048 static void ufs_qcom_set_caps(struct ufs_hba *hba)
1049 {
1050 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1051
1052 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1053 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING;
1054 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
1055 hba->caps |= UFSHCD_CAP_WB_EN;
1056 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE;
1057 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
1058
1059 if (host->hw_ver.major >= 0x2) {
1060 host->caps = UFS_QCOM_CAP_QUNIPRO |
1061 UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE;
1062 }
1063 }
1064
1065 /**
1066 * ufs_qcom_setup_clocks - enables/disable clocks
1067 * @hba: host controller instance
1068 * @on: If true, enable clocks else disable them.
1069 * @status: PRE_CHANGE or POST_CHANGE notify
1070 *
1071 * Return: 0 on success, non-zero on failure.
1072 */
ufs_qcom_setup_clocks(struct ufs_hba * hba,bool on,enum ufs_notify_change_status status)1073 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
1074 enum ufs_notify_change_status status)
1075 {
1076 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1077
1078 /*
1079 * In case ufs_qcom_init() is not yet done, simply ignore.
1080 * This ufs_qcom_setup_clocks() shall be called from
1081 * ufs_qcom_init() after init is done.
1082 */
1083 if (!host)
1084 return 0;
1085
1086 switch (status) {
1087 case PRE_CHANGE:
1088 if (on) {
1089 ufs_qcom_icc_update_bw(host);
1090 } else {
1091 if (!ufs_qcom_is_link_active(hba)) {
1092 /* disable device ref_clk */
1093 ufs_qcom_dev_ref_clk_ctrl(host, false);
1094 }
1095 }
1096 break;
1097 case POST_CHANGE:
1098 if (on) {
1099 /* enable the device ref clock for HS mode*/
1100 if (ufshcd_is_hs_mode(&hba->pwr_info))
1101 ufs_qcom_dev_ref_clk_ctrl(host, true);
1102 } else {
1103 ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw,
1104 ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw);
1105 }
1106 break;
1107 }
1108
1109 return 0;
1110 }
1111
1112 static int
ufs_qcom_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)1113 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
1114 {
1115 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
1116
1117 ufs_qcom_assert_reset(host->hba);
1118 /* provide 1ms delay to let the reset pulse propagate. */
1119 usleep_range(1000, 1100);
1120 return 0;
1121 }
1122
1123 static int
ufs_qcom_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)1124 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
1125 {
1126 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
1127
1128 ufs_qcom_deassert_reset(host->hba);
1129
1130 /*
1131 * after reset deassertion, phy will need all ref clocks,
1132 * voltage, current to settle down before starting serdes.
1133 */
1134 usleep_range(1000, 1100);
1135 return 0;
1136 }
1137
1138 static const struct reset_control_ops ufs_qcom_reset_ops = {
1139 .assert = ufs_qcom_reset_assert,
1140 .deassert = ufs_qcom_reset_deassert,
1141 };
1142
ufs_qcom_icc_init(struct ufs_qcom_host * host)1143 static int ufs_qcom_icc_init(struct ufs_qcom_host *host)
1144 {
1145 struct device *dev = host->hba->dev;
1146 int ret;
1147
1148 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr");
1149 if (IS_ERR(host->icc_ddr))
1150 return dev_err_probe(dev, PTR_ERR(host->icc_ddr),
1151 "failed to acquire interconnect path\n");
1152
1153 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs");
1154 if (IS_ERR(host->icc_cpu))
1155 return dev_err_probe(dev, PTR_ERR(host->icc_cpu),
1156 "failed to acquire interconnect path\n");
1157
1158 /*
1159 * Set Maximum bandwidth vote before initializing the UFS controller and
1160 * device. Ideally, a minimal interconnect vote would suffice for the
1161 * initialization, but a max vote would allow faster initialization.
1162 */
1163 ret = ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MAX][0][0].mem_bw,
1164 ufs_qcom_bw_table[MODE_MAX][0][0].cfg_bw);
1165 if (ret < 0)
1166 return dev_err_probe(dev, ret, "failed to set bandwidth request\n");
1167
1168 return 0;
1169 }
1170
1171 /**
1172 * ufs_qcom_init - bind phy with controller
1173 * @hba: host controller instance
1174 *
1175 * Binds PHY with controller and powers up PHY enabling clocks
1176 * and regulators.
1177 *
1178 * Return: -EPROBE_DEFER if binding fails, returns negative error
1179 * on phy power up failure and returns zero on success.
1180 */
ufs_qcom_init(struct ufs_hba * hba)1181 static int ufs_qcom_init(struct ufs_hba *hba)
1182 {
1183 int err;
1184 struct device *dev = hba->dev;
1185 struct platform_device *pdev = to_platform_device(dev);
1186 struct ufs_qcom_host *host;
1187 struct resource *res;
1188 struct ufs_clk_info *clki;
1189
1190 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
1191 if (!host) {
1192 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
1193 return -ENOMEM;
1194 }
1195
1196 /* Make a two way bind between the qcom host and the hba */
1197 host->hba = hba;
1198 ufshcd_set_variant(hba, host);
1199
1200 /* Setup the optional reset control of HCI */
1201 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst");
1202 if (IS_ERR(host->core_reset)) {
1203 err = dev_err_probe(dev, PTR_ERR(host->core_reset),
1204 "Failed to get reset control\n");
1205 goto out_variant_clear;
1206 }
1207
1208 /* Fire up the reset controller. Failure here is non-fatal. */
1209 host->rcdev.of_node = dev->of_node;
1210 host->rcdev.ops = &ufs_qcom_reset_ops;
1211 host->rcdev.owner = dev->driver->owner;
1212 host->rcdev.nr_resets = 1;
1213 err = devm_reset_controller_register(dev, &host->rcdev);
1214 if (err)
1215 dev_warn(dev, "Failed to register reset controller\n");
1216
1217 if (!has_acpi_companion(dev)) {
1218 host->generic_phy = devm_phy_get(dev, "ufsphy");
1219 if (IS_ERR(host->generic_phy)) {
1220 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n");
1221 goto out_variant_clear;
1222 }
1223 }
1224
1225 err = ufs_qcom_icc_init(host);
1226 if (err)
1227 goto out_variant_clear;
1228
1229 host->device_reset = devm_gpiod_get_optional(dev, "reset",
1230 GPIOD_OUT_HIGH);
1231 if (IS_ERR(host->device_reset)) {
1232 err = PTR_ERR(host->device_reset);
1233 if (err != -EPROBE_DEFER)
1234 dev_err(dev, "failed to acquire reset gpio: %d\n", err);
1235 goto out_variant_clear;
1236 }
1237
1238 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1239 &host->hw_ver.minor, &host->hw_ver.step);
1240
1241 /*
1242 * for newer controllers, device reference clock control bit has
1243 * moved inside UFS controller register address space itself.
1244 */
1245 if (host->hw_ver.major >= 0x02) {
1246 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1247 host->dev_ref_clk_en_mask = BIT(26);
1248 } else {
1249 /* "dev_ref_clk_ctrl_mem" is optional resource */
1250 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1251 "dev_ref_clk_ctrl_mem");
1252 if (res) {
1253 host->dev_ref_clk_ctrl_mmio =
1254 devm_ioremap_resource(dev, res);
1255 if (IS_ERR(host->dev_ref_clk_ctrl_mmio))
1256 host->dev_ref_clk_ctrl_mmio = NULL;
1257 host->dev_ref_clk_en_mask = BIT(5);
1258 }
1259 }
1260
1261 list_for_each_entry(clki, &hba->clk_list_head, list) {
1262 if (!strcmp(clki->name, "core_clk_unipro"))
1263 clki->keep_link_active = true;
1264 }
1265
1266 err = ufs_qcom_init_lane_clks(host);
1267 if (err)
1268 goto out_variant_clear;
1269
1270 ufs_qcom_set_caps(hba);
1271 ufs_qcom_advertise_quirks(hba);
1272
1273 err = ufs_qcom_ice_init(host);
1274 if (err)
1275 goto out_variant_clear;
1276
1277 ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1278
1279 if (hba->dev->id < MAX_UFS_QCOM_HOSTS)
1280 ufs_qcom_hosts[hba->dev->id] = host;
1281
1282 ufs_qcom_get_default_testbus_cfg(host);
1283 err = ufs_qcom_testbus_config(host);
1284 if (err)
1285 /* Failure is non-fatal */
1286 dev_warn(dev, "%s: failed to configure the testbus %d\n",
1287 __func__, err);
1288
1289 /*
1290 * Power up the PHY using the minimum supported gear (UFS_HS_G2).
1291 * Switching to max gear will be performed during reinit if supported.
1292 */
1293 host->hs_gear = UFS_HS_G2;
1294
1295 return 0;
1296
1297 out_variant_clear:
1298 ufshcd_set_variant(hba, NULL);
1299
1300 return err;
1301 }
1302
ufs_qcom_exit(struct ufs_hba * hba)1303 static void ufs_qcom_exit(struct ufs_hba *hba)
1304 {
1305 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1306
1307 ufs_qcom_disable_lane_clks(host);
1308 phy_power_off(host->generic_phy);
1309 phy_exit(host->generic_phy);
1310 }
1311
ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba * hba,u32 clk_cycles)1312 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
1313 u32 clk_cycles)
1314 {
1315 int err;
1316 u32 core_clk_ctrl_reg;
1317
1318 if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK)
1319 return -EINVAL;
1320
1321 err = ufshcd_dme_get(hba,
1322 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1323 &core_clk_ctrl_reg);
1324 if (err)
1325 return err;
1326
1327 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
1328 core_clk_ctrl_reg |= clk_cycles;
1329
1330 /* Clear CORE_CLK_DIV_EN */
1331 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1332
1333 return ufshcd_dme_set(hba,
1334 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1335 core_clk_ctrl_reg);
1336 }
1337
ufs_qcom_clk_scale_up_pre_change(struct ufs_hba * hba)1338 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
1339 {
1340 /* nothing to do as of now */
1341 return 0;
1342 }
1343
ufs_qcom_clk_scale_up_post_change(struct ufs_hba * hba)1344 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1345 {
1346 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1347
1348 if (!ufs_qcom_cap_qunipro(host))
1349 return 0;
1350
1351 /* set unipro core clock cycles to 150 and clear clock divider */
1352 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150);
1353 }
1354
ufs_qcom_clk_scale_down_pre_change(struct ufs_hba * hba)1355 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1356 {
1357 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1358 int err;
1359 u32 core_clk_ctrl_reg;
1360
1361 if (!ufs_qcom_cap_qunipro(host))
1362 return 0;
1363
1364 err = ufshcd_dme_get(hba,
1365 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1366 &core_clk_ctrl_reg);
1367
1368 /* make sure CORE_CLK_DIV_EN is cleared */
1369 if (!err &&
1370 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1371 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1372 err = ufshcd_dme_set(hba,
1373 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1374 core_clk_ctrl_reg);
1375 }
1376
1377 return err;
1378 }
1379
ufs_qcom_clk_scale_down_post_change(struct ufs_hba * hba)1380 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
1381 {
1382 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1383
1384 if (!ufs_qcom_cap_qunipro(host))
1385 return 0;
1386
1387 /* set unipro core clock cycles to 75 and clear clock divider */
1388 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75);
1389 }
1390
ufs_qcom_clk_scale_notify(struct ufs_hba * hba,bool scale_up,enum ufs_notify_change_status status)1391 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
1392 bool scale_up, enum ufs_notify_change_status status)
1393 {
1394 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1395 struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
1396 int err = 0;
1397
1398 /* check the host controller state before sending hibern8 cmd */
1399 if (!ufshcd_is_hba_active(hba))
1400 return 0;
1401
1402 if (status == PRE_CHANGE) {
1403 err = ufshcd_uic_hibern8_enter(hba);
1404 if (err)
1405 return err;
1406 if (scale_up)
1407 err = ufs_qcom_clk_scale_up_pre_change(hba);
1408 else
1409 err = ufs_qcom_clk_scale_down_pre_change(hba);
1410
1411 if (err) {
1412 ufshcd_uic_hibern8_exit(hba);
1413 return err;
1414 }
1415 } else {
1416 if (scale_up)
1417 err = ufs_qcom_clk_scale_up_post_change(hba);
1418 else
1419 err = ufs_qcom_clk_scale_down_post_change(hba);
1420
1421
1422 if (err) {
1423 ufshcd_uic_hibern8_exit(hba);
1424 return err;
1425 }
1426
1427 ufs_qcom_cfg_timers(hba,
1428 dev_req_params->gear_rx,
1429 dev_req_params->pwr_rx,
1430 dev_req_params->hs_rate,
1431 false);
1432 ufs_qcom_icc_update_bw(host);
1433 ufshcd_uic_hibern8_exit(hba);
1434 }
1435
1436 return 0;
1437 }
1438
ufs_qcom_enable_test_bus(struct ufs_qcom_host * host)1439 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1440 {
1441 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1442 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1443 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1444 }
1445
ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host * host)1446 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1447 {
1448 /* provide a legal default configuration */
1449 host->testbus.select_major = TSTBUS_UNIPRO;
1450 host->testbus.select_minor = 37;
1451 }
1452
ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host * host)1453 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1454 {
1455 if (host->testbus.select_major >= TSTBUS_MAX) {
1456 dev_err(host->hba->dev,
1457 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1458 __func__, host->testbus.select_major);
1459 return false;
1460 }
1461
1462 return true;
1463 }
1464
ufs_qcom_testbus_config(struct ufs_qcom_host * host)1465 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1466 {
1467 int reg;
1468 int offset;
1469 u32 mask = TEST_BUS_SUB_SEL_MASK;
1470
1471 if (!host)
1472 return -EINVAL;
1473
1474 if (!ufs_qcom_testbus_cfg_is_ok(host))
1475 return -EPERM;
1476
1477 switch (host->testbus.select_major) {
1478 case TSTBUS_UAWM:
1479 reg = UFS_TEST_BUS_CTRL_0;
1480 offset = 24;
1481 break;
1482 case TSTBUS_UARM:
1483 reg = UFS_TEST_BUS_CTRL_0;
1484 offset = 16;
1485 break;
1486 case TSTBUS_TXUC:
1487 reg = UFS_TEST_BUS_CTRL_0;
1488 offset = 8;
1489 break;
1490 case TSTBUS_RXUC:
1491 reg = UFS_TEST_BUS_CTRL_0;
1492 offset = 0;
1493 break;
1494 case TSTBUS_DFC:
1495 reg = UFS_TEST_BUS_CTRL_1;
1496 offset = 24;
1497 break;
1498 case TSTBUS_TRLUT:
1499 reg = UFS_TEST_BUS_CTRL_1;
1500 offset = 16;
1501 break;
1502 case TSTBUS_TMRLUT:
1503 reg = UFS_TEST_BUS_CTRL_1;
1504 offset = 8;
1505 break;
1506 case TSTBUS_OCSC:
1507 reg = UFS_TEST_BUS_CTRL_1;
1508 offset = 0;
1509 break;
1510 case TSTBUS_WRAPPER:
1511 reg = UFS_TEST_BUS_CTRL_2;
1512 offset = 16;
1513 break;
1514 case TSTBUS_COMBINED:
1515 reg = UFS_TEST_BUS_CTRL_2;
1516 offset = 8;
1517 break;
1518 case TSTBUS_UTP_HCI:
1519 reg = UFS_TEST_BUS_CTRL_2;
1520 offset = 0;
1521 break;
1522 case TSTBUS_UNIPRO:
1523 reg = UFS_UNIPRO_CFG;
1524 offset = 20;
1525 mask = 0xFFF;
1526 break;
1527 /*
1528 * No need for a default case, since
1529 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1530 * is legal
1531 */
1532 }
1533 mask <<= offset;
1534 ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1535 (u32)host->testbus.select_major << 19,
1536 REG_UFS_CFG1);
1537 ufshcd_rmwl(host->hba, mask,
1538 (u32)host->testbus.select_minor << offset,
1539 reg);
1540 ufs_qcom_enable_test_bus(host);
1541 /*
1542 * Make sure the test bus configuration is
1543 * committed before returning.
1544 */
1545 mb();
1546
1547 return 0;
1548 }
1549
ufs_qcom_dump_dbg_regs(struct ufs_hba * hba)1550 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1551 {
1552 u32 reg;
1553 struct ufs_qcom_host *host;
1554
1555 host = ufshcd_get_variant(hba);
1556
1557 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1558 "HCI Vendor Specific Registers ");
1559
1560 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1561 ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC ");
1562
1563 reg = ufshcd_readl(hba, REG_UFS_CFG1);
1564 reg |= UTP_DBG_RAMS_EN;
1565 ufshcd_writel(hba, reg, REG_UFS_CFG1);
1566
1567 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1568 ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM ");
1569
1570 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1571 ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM ");
1572
1573 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1574 ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM ");
1575
1576 /* clear bit 17 - UTP_DBG_RAMS_EN */
1577 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1578
1579 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1580 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM ");
1581
1582 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1583 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM ");
1584
1585 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1586 ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC ");
1587
1588 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1589 ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC ");
1590
1591 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1592 ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC ");
1593
1594 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1595 ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT ");
1596
1597 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1598 ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT ");
1599 }
1600
1601 /**
1602 * ufs_qcom_device_reset() - toggle the (optional) device reset line
1603 * @hba: per-adapter instance
1604 *
1605 * Toggles the (optional) reset line to reset the attached device.
1606 */
ufs_qcom_device_reset(struct ufs_hba * hba)1607 static int ufs_qcom_device_reset(struct ufs_hba *hba)
1608 {
1609 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1610
1611 /* reset gpio is optional */
1612 if (!host->device_reset)
1613 return -EOPNOTSUPP;
1614
1615 /*
1616 * The UFS device shall detect reset pulses of 1us, sleep for 10us to
1617 * be on the safe side.
1618 */
1619 ufs_qcom_device_reset_ctrl(hba, true);
1620 usleep_range(10, 15);
1621
1622 ufs_qcom_device_reset_ctrl(hba, false);
1623 usleep_range(10, 15);
1624
1625 return 0;
1626 }
1627
1628 #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND)
ufs_qcom_config_scaling_param(struct ufs_hba * hba,struct devfreq_dev_profile * p,struct devfreq_simple_ondemand_data * d)1629 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1630 struct devfreq_dev_profile *p,
1631 struct devfreq_simple_ondemand_data *d)
1632 {
1633 p->polling_ms = 60;
1634 p->timer = DEVFREQ_TIMER_DELAYED;
1635 d->upthreshold = 70;
1636 d->downdifferential = 5;
1637 }
1638 #else
ufs_qcom_config_scaling_param(struct ufs_hba * hba,struct devfreq_dev_profile * p,struct devfreq_simple_ondemand_data * data)1639 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1640 struct devfreq_dev_profile *p,
1641 struct devfreq_simple_ondemand_data *data)
1642 {
1643 }
1644 #endif
1645
1646 /* Resources */
1647 static const struct ufshcd_res_info ufs_res_info[RES_MAX] = {
1648 {.name = "ufs_mem",},
1649 {.name = "mcq",},
1650 /* Submission Queue DAO */
1651 {.name = "mcq_sqd",},
1652 /* Submission Queue Interrupt Status */
1653 {.name = "mcq_sqis",},
1654 /* Completion Queue DAO */
1655 {.name = "mcq_cqd",},
1656 /* Completion Queue Interrupt Status */
1657 {.name = "mcq_cqis",},
1658 /* MCQ vendor specific */
1659 {.name = "mcq_vs",},
1660 };
1661
ufs_qcom_mcq_config_resource(struct ufs_hba * hba)1662 static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba)
1663 {
1664 struct platform_device *pdev = to_platform_device(hba->dev);
1665 struct ufshcd_res_info *res;
1666 struct resource *res_mem, *res_mcq;
1667 int i, ret = 0;
1668
1669 memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info));
1670
1671 for (i = 0; i < RES_MAX; i++) {
1672 res = &hba->res[i];
1673 res->resource = platform_get_resource_byname(pdev,
1674 IORESOURCE_MEM,
1675 res->name);
1676 if (!res->resource) {
1677 dev_info(hba->dev, "Resource %s not provided\n", res->name);
1678 if (i == RES_UFS)
1679 return -ENODEV;
1680 continue;
1681 } else if (i == RES_UFS) {
1682 res_mem = res->resource;
1683 res->base = hba->mmio_base;
1684 continue;
1685 }
1686
1687 res->base = devm_ioremap_resource(hba->dev, res->resource);
1688 if (IS_ERR(res->base)) {
1689 dev_err(hba->dev, "Failed to map res %s, err=%d\n",
1690 res->name, (int)PTR_ERR(res->base));
1691 ret = PTR_ERR(res->base);
1692 res->base = NULL;
1693 return ret;
1694 }
1695 }
1696
1697 /* MCQ resource provided in DT */
1698 res = &hba->res[RES_MCQ];
1699 /* Bail if MCQ resource is provided */
1700 if (res->base)
1701 goto out;
1702
1703 /* Explicitly allocate MCQ resource from ufs_mem */
1704 res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL);
1705 if (!res_mcq)
1706 return -ENOMEM;
1707
1708 res_mcq->start = res_mem->start +
1709 MCQ_SQATTR_OFFSET(hba->mcq_capabilities);
1710 res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1;
1711 res_mcq->flags = res_mem->flags;
1712 res_mcq->name = "mcq";
1713
1714 ret = insert_resource(&iomem_resource, res_mcq);
1715 if (ret) {
1716 dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n",
1717 ret);
1718 return ret;
1719 }
1720
1721 res->base = devm_ioremap_resource(hba->dev, res_mcq);
1722 if (IS_ERR(res->base)) {
1723 dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n",
1724 (int)PTR_ERR(res->base));
1725 ret = PTR_ERR(res->base);
1726 goto ioremap_err;
1727 }
1728
1729 out:
1730 hba->mcq_base = res->base;
1731 return 0;
1732 ioremap_err:
1733 res->base = NULL;
1734 remove_resource(res_mcq);
1735 return ret;
1736 }
1737
ufs_qcom_op_runtime_config(struct ufs_hba * hba)1738 static int ufs_qcom_op_runtime_config(struct ufs_hba *hba)
1739 {
1740 struct ufshcd_res_info *mem_res, *sqdao_res;
1741 struct ufshcd_mcq_opr_info_t *opr;
1742 int i;
1743
1744 mem_res = &hba->res[RES_UFS];
1745 sqdao_res = &hba->res[RES_MCQ_SQD];
1746
1747 if (!mem_res->base || !sqdao_res->base)
1748 return -EINVAL;
1749
1750 for (i = 0; i < OPR_MAX; i++) {
1751 opr = &hba->mcq_opr[i];
1752 opr->offset = sqdao_res->resource->start -
1753 mem_res->resource->start + 0x40 * i;
1754 opr->stride = 0x100;
1755 opr->base = sqdao_res->base + 0x40 * i;
1756 }
1757
1758 return 0;
1759 }
1760
ufs_qcom_get_hba_mac(struct ufs_hba * hba)1761 static int ufs_qcom_get_hba_mac(struct ufs_hba *hba)
1762 {
1763 /* Qualcomm HC supports up to 64 */
1764 return MAX_SUPP_MAC;
1765 }
1766
ufs_qcom_get_outstanding_cqs(struct ufs_hba * hba,unsigned long * ocqs)1767 static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba,
1768 unsigned long *ocqs)
1769 {
1770 struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS];
1771
1772 if (!mcq_vs_res->base)
1773 return -EINVAL;
1774
1775 *ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS);
1776
1777 return 0;
1778 }
1779
ufs_qcom_write_msi_msg(struct msi_desc * desc,struct msi_msg * msg)1780 static void ufs_qcom_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
1781 {
1782 struct device *dev = msi_desc_to_dev(desc);
1783 struct ufs_hba *hba = dev_get_drvdata(dev);
1784
1785 ufshcd_mcq_config_esi(hba, msg);
1786 }
1787
ufs_qcom_mcq_esi_handler(int irq,void * data)1788 static irqreturn_t ufs_qcom_mcq_esi_handler(int irq, void *data)
1789 {
1790 struct msi_desc *desc = data;
1791 struct device *dev = msi_desc_to_dev(desc);
1792 struct ufs_hba *hba = dev_get_drvdata(dev);
1793 u32 id = desc->msi_index;
1794 struct ufs_hw_queue *hwq = &hba->uhq[id];
1795
1796 ufshcd_mcq_write_cqis(hba, 0x1, id);
1797 ufshcd_mcq_poll_cqe_lock(hba, hwq);
1798
1799 return IRQ_HANDLED;
1800 }
1801
ufs_qcom_config_esi(struct ufs_hba * hba)1802 static int ufs_qcom_config_esi(struct ufs_hba *hba)
1803 {
1804 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1805 struct msi_desc *desc;
1806 struct msi_desc *failed_desc = NULL;
1807 int nr_irqs, ret;
1808
1809 if (host->esi_enabled)
1810 return 0;
1811
1812 /*
1813 * 1. We only handle CQs as of now.
1814 * 2. Poll queues do not need ESI.
1815 */
1816 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL];
1817 ret = platform_msi_domain_alloc_irqs(hba->dev, nr_irqs,
1818 ufs_qcom_write_msi_msg);
1819 if (ret) {
1820 dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret);
1821 goto out;
1822 }
1823
1824 msi_lock_descs(hba->dev);
1825 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) {
1826 ret = devm_request_irq(hba->dev, desc->irq,
1827 ufs_qcom_mcq_esi_handler,
1828 IRQF_SHARED, "qcom-mcq-esi", desc);
1829 if (ret) {
1830 dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n",
1831 __func__, desc->irq, ret);
1832 failed_desc = desc;
1833 break;
1834 }
1835 }
1836 msi_unlock_descs(hba->dev);
1837
1838 if (ret) {
1839 /* Rewind */
1840 msi_lock_descs(hba->dev);
1841 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) {
1842 if (desc == failed_desc)
1843 break;
1844 devm_free_irq(hba->dev, desc->irq, hba);
1845 }
1846 msi_unlock_descs(hba->dev);
1847 platform_msi_domain_free_irqs(hba->dev);
1848 } else {
1849 if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 &&
1850 host->hw_ver.step == 0) {
1851 ufshcd_writel(hba,
1852 ufshcd_readl(hba, REG_UFS_CFG3) | 0x1F000,
1853 REG_UFS_CFG3);
1854 }
1855 ufshcd_mcq_enable_esi(hba);
1856 }
1857
1858 out:
1859 if (!ret)
1860 host->esi_enabled = true;
1861
1862 return ret;
1863 }
1864
1865 /*
1866 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1867 *
1868 * The variant operations configure the necessary controller and PHY
1869 * handshake during initialization.
1870 */
1871 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1872 .name = "qcom",
1873 .init = ufs_qcom_init,
1874 .exit = ufs_qcom_exit,
1875 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version,
1876 .clk_scale_notify = ufs_qcom_clk_scale_notify,
1877 .setup_clocks = ufs_qcom_setup_clocks,
1878 .hce_enable_notify = ufs_qcom_hce_enable_notify,
1879 .link_startup_notify = ufs_qcom_link_startup_notify,
1880 .pwr_change_notify = ufs_qcom_pwr_change_notify,
1881 .apply_dev_quirks = ufs_qcom_apply_dev_quirks,
1882 .suspend = ufs_qcom_suspend,
1883 .resume = ufs_qcom_resume,
1884 .dbg_register_dump = ufs_qcom_dump_dbg_regs,
1885 .device_reset = ufs_qcom_device_reset,
1886 .config_scaling_param = ufs_qcom_config_scaling_param,
1887 .program_key = ufs_qcom_ice_program_key,
1888 .mcq_config_resource = ufs_qcom_mcq_config_resource,
1889 .get_hba_mac = ufs_qcom_get_hba_mac,
1890 .op_runtime_config = ufs_qcom_op_runtime_config,
1891 .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs,
1892 .config_esi = ufs_qcom_config_esi,
1893 };
1894
1895 /**
1896 * ufs_qcom_probe - probe routine of the driver
1897 * @pdev: pointer to Platform device handle
1898 *
1899 * Return: zero for success and non-zero for failure.
1900 */
ufs_qcom_probe(struct platform_device * pdev)1901 static int ufs_qcom_probe(struct platform_device *pdev)
1902 {
1903 int err;
1904 struct device *dev = &pdev->dev;
1905
1906 /* Perform generic probe */
1907 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1908 if (err)
1909 return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n");
1910
1911 return 0;
1912 }
1913
1914 /**
1915 * ufs_qcom_remove - set driver_data of the device to NULL
1916 * @pdev: pointer to platform device handle
1917 *
1918 * Always returns 0
1919 */
ufs_qcom_remove(struct platform_device * pdev)1920 static int ufs_qcom_remove(struct platform_device *pdev)
1921 {
1922 struct ufs_hba *hba = platform_get_drvdata(pdev);
1923
1924 pm_runtime_get_sync(&(pdev)->dev);
1925 ufshcd_remove(hba);
1926 platform_msi_domain_free_irqs(hba->dev);
1927 return 0;
1928 }
1929
1930 static const struct of_device_id ufs_qcom_of_match[] __maybe_unused = {
1931 { .compatible = "qcom,ufshc"},
1932 {},
1933 };
1934 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
1935
1936 #ifdef CONFIG_ACPI
1937 static const struct acpi_device_id ufs_qcom_acpi_match[] = {
1938 { "QCOM24A5" },
1939 { },
1940 };
1941 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match);
1942 #endif
1943
1944 static const struct dev_pm_ops ufs_qcom_pm_ops = {
1945 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
1946 .prepare = ufshcd_suspend_prepare,
1947 .complete = ufshcd_resume_complete,
1948 #ifdef CONFIG_PM_SLEEP
1949 .suspend = ufshcd_system_suspend,
1950 .resume = ufshcd_system_resume,
1951 .freeze = ufshcd_system_freeze,
1952 .restore = ufshcd_system_restore,
1953 .thaw = ufshcd_system_thaw,
1954 #endif
1955 };
1956
1957 static struct platform_driver ufs_qcom_pltform = {
1958 .probe = ufs_qcom_probe,
1959 .remove = ufs_qcom_remove,
1960 .driver = {
1961 .name = "ufshcd-qcom",
1962 .pm = &ufs_qcom_pm_ops,
1963 .of_match_table = of_match_ptr(ufs_qcom_of_match),
1964 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match),
1965 },
1966 };
1967 module_platform_driver(ufs_qcom_pltform);
1968
1969 MODULE_LICENSE("GPL v2");
1970