1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #include <linux/dma-mapping.h>
5 #include <linux/etherdevice.h>
6 #include <linux/interrupt.h>
7 #ifdef CONFIG_RFS_ACCEL
8 #include <linux/cpu_rmap.h>
9 #endif
10 #include <linux/if_vlan.h>
11 #include <linux/irq.h>
12 #include <linux/ip.h>
13 #include <linux/ipv6.h>
14 #include <linux/module.h>
15 #include <linux/pci.h>
16 #include <linux/skbuff.h>
17 #include <linux/sctp.h>
18 #include <net/gre.h>
19 #include <net/gro.h>
20 #include <net/ip6_checksum.h>
21 #include <net/page_pool/helpers.h>
22 #include <net/pkt_cls.h>
23 #include <net/pkt_sched.h>
24 #include <net/tcp.h>
25 #include <net/vxlan.h>
26 #include <net/geneve.h>
27
28 #include "hnae3.h"
29 #include "hns3_enet.h"
30 /* All hns3 tracepoints are defined by the include below, which
31 * must be included exactly once across the whole kernel with
32 * CREATE_TRACE_POINTS defined
33 */
34 #define CREATE_TRACE_POINTS
35 #include "hns3_trace.h"
36
37 #define hns3_set_field(origin, shift, val) ((origin) |= (val) << (shift))
38 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
39
40 #define hns3_rl_err(fmt, ...) \
41 do { \
42 if (net_ratelimit()) \
43 netdev_err(fmt, ##__VA_ARGS__); \
44 } while (0)
45
46 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
47
48 static const char hns3_driver_name[] = "hns3";
49 static const char hns3_driver_string[] =
50 "Hisilicon Ethernet Network Driver for Hip08 Family";
51 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
52 static struct hnae3_client client;
53
54 static int debug = -1;
55 module_param(debug, int, 0);
56 MODULE_PARM_DESC(debug, " Network interface message level setting");
57
58 static unsigned int tx_sgl = 1;
59 module_param(tx_sgl, uint, 0600);
60 MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to optimize the IOMMU mapping");
61
62 static bool page_pool_enabled = true;
63 module_param(page_pool_enabled, bool, 0400);
64
65 #define HNS3_SGL_SIZE(nfrag) (sizeof(struct scatterlist) * (nfrag) + \
66 sizeof(struct sg_table))
67 #define HNS3_MAX_SGL_SIZE ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM), \
68 dma_get_cache_alignment())
69
70 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
71 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
72
73 #define HNS3_INNER_VLAN_TAG 1
74 #define HNS3_OUTER_VLAN_TAG 2
75
76 #define HNS3_MIN_TX_LEN 33U
77 #define HNS3_MIN_TUN_PKT_LEN 65U
78
79 /* hns3_pci_tbl - PCI Device ID Table
80 *
81 * Last entry must be all 0s
82 *
83 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
84 * Class, Class Mask, private data (not used) }
85 */
86 static const struct pci_device_id hns3_pci_tbl[] = {
87 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
88 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
89 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
90 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
91 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
92 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
93 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
94 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
95 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
96 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
97 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
98 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
99 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA),
100 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
101 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
102 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
103 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
104 /* required last entry */
105 {0,}
106 };
107 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
108
109 #define HNS3_RX_PTYPE_ENTRY(ptype, l, s, t, h) \
110 { ptype, \
111 l, \
112 CHECKSUM_##s, \
113 HNS3_L3_TYPE_##t, \
114 1, \
115 h}
116
117 #define HNS3_RX_PTYPE_UNUSED_ENTRY(ptype) \
118 { ptype, 0, CHECKSUM_NONE, HNS3_L3_TYPE_PARSE_FAIL, 0, \
119 PKT_HASH_TYPE_NONE }
120
121 static const struct hns3_rx_ptype hns3_rx_ptype_tbl[] = {
122 HNS3_RX_PTYPE_UNUSED_ENTRY(0),
123 HNS3_RX_PTYPE_ENTRY(1, 0, COMPLETE, ARP, PKT_HASH_TYPE_NONE),
124 HNS3_RX_PTYPE_ENTRY(2, 0, COMPLETE, RARP, PKT_HASH_TYPE_NONE),
125 HNS3_RX_PTYPE_ENTRY(3, 0, COMPLETE, LLDP, PKT_HASH_TYPE_NONE),
126 HNS3_RX_PTYPE_ENTRY(4, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
127 HNS3_RX_PTYPE_ENTRY(5, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
128 HNS3_RX_PTYPE_ENTRY(6, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
129 HNS3_RX_PTYPE_ENTRY(7, 0, COMPLETE, CNM, PKT_HASH_TYPE_NONE),
130 HNS3_RX_PTYPE_ENTRY(8, 0, NONE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
131 HNS3_RX_PTYPE_UNUSED_ENTRY(9),
132 HNS3_RX_PTYPE_UNUSED_ENTRY(10),
133 HNS3_RX_PTYPE_UNUSED_ENTRY(11),
134 HNS3_RX_PTYPE_UNUSED_ENTRY(12),
135 HNS3_RX_PTYPE_UNUSED_ENTRY(13),
136 HNS3_RX_PTYPE_UNUSED_ENTRY(14),
137 HNS3_RX_PTYPE_UNUSED_ENTRY(15),
138 HNS3_RX_PTYPE_ENTRY(16, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
139 HNS3_RX_PTYPE_ENTRY(17, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE),
140 HNS3_RX_PTYPE_ENTRY(18, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE),
141 HNS3_RX_PTYPE_ENTRY(19, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
142 HNS3_RX_PTYPE_ENTRY(20, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
143 HNS3_RX_PTYPE_ENTRY(21, 0, NONE, IPV4, PKT_HASH_TYPE_NONE),
144 HNS3_RX_PTYPE_ENTRY(22, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
145 HNS3_RX_PTYPE_ENTRY(23, 0, NONE, IPV4, PKT_HASH_TYPE_L3),
146 HNS3_RX_PTYPE_ENTRY(24, 0, NONE, IPV4, PKT_HASH_TYPE_L3),
147 HNS3_RX_PTYPE_ENTRY(25, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
148 HNS3_RX_PTYPE_UNUSED_ENTRY(26),
149 HNS3_RX_PTYPE_UNUSED_ENTRY(27),
150 HNS3_RX_PTYPE_UNUSED_ENTRY(28),
151 HNS3_RX_PTYPE_ENTRY(29, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
152 HNS3_RX_PTYPE_ENTRY(30, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
153 HNS3_RX_PTYPE_ENTRY(31, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
154 HNS3_RX_PTYPE_ENTRY(32, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
155 HNS3_RX_PTYPE_ENTRY(33, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
156 HNS3_RX_PTYPE_ENTRY(34, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
157 HNS3_RX_PTYPE_ENTRY(35, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
158 HNS3_RX_PTYPE_ENTRY(36, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
159 HNS3_RX_PTYPE_ENTRY(37, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
160 HNS3_RX_PTYPE_UNUSED_ENTRY(38),
161 HNS3_RX_PTYPE_ENTRY(39, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
162 HNS3_RX_PTYPE_ENTRY(40, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
163 HNS3_RX_PTYPE_ENTRY(41, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
164 HNS3_RX_PTYPE_ENTRY(42, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
165 HNS3_RX_PTYPE_ENTRY(43, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
166 HNS3_RX_PTYPE_ENTRY(44, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
167 HNS3_RX_PTYPE_ENTRY(45, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
168 HNS3_RX_PTYPE_UNUSED_ENTRY(46),
169 HNS3_RX_PTYPE_UNUSED_ENTRY(47),
170 HNS3_RX_PTYPE_UNUSED_ENTRY(48),
171 HNS3_RX_PTYPE_UNUSED_ENTRY(49),
172 HNS3_RX_PTYPE_UNUSED_ENTRY(50),
173 HNS3_RX_PTYPE_UNUSED_ENTRY(51),
174 HNS3_RX_PTYPE_UNUSED_ENTRY(52),
175 HNS3_RX_PTYPE_UNUSED_ENTRY(53),
176 HNS3_RX_PTYPE_UNUSED_ENTRY(54),
177 HNS3_RX_PTYPE_UNUSED_ENTRY(55),
178 HNS3_RX_PTYPE_UNUSED_ENTRY(56),
179 HNS3_RX_PTYPE_UNUSED_ENTRY(57),
180 HNS3_RX_PTYPE_UNUSED_ENTRY(58),
181 HNS3_RX_PTYPE_UNUSED_ENTRY(59),
182 HNS3_RX_PTYPE_UNUSED_ENTRY(60),
183 HNS3_RX_PTYPE_UNUSED_ENTRY(61),
184 HNS3_RX_PTYPE_UNUSED_ENTRY(62),
185 HNS3_RX_PTYPE_UNUSED_ENTRY(63),
186 HNS3_RX_PTYPE_UNUSED_ENTRY(64),
187 HNS3_RX_PTYPE_UNUSED_ENTRY(65),
188 HNS3_RX_PTYPE_UNUSED_ENTRY(66),
189 HNS3_RX_PTYPE_UNUSED_ENTRY(67),
190 HNS3_RX_PTYPE_UNUSED_ENTRY(68),
191 HNS3_RX_PTYPE_UNUSED_ENTRY(69),
192 HNS3_RX_PTYPE_UNUSED_ENTRY(70),
193 HNS3_RX_PTYPE_UNUSED_ENTRY(71),
194 HNS3_RX_PTYPE_UNUSED_ENTRY(72),
195 HNS3_RX_PTYPE_UNUSED_ENTRY(73),
196 HNS3_RX_PTYPE_UNUSED_ENTRY(74),
197 HNS3_RX_PTYPE_UNUSED_ENTRY(75),
198 HNS3_RX_PTYPE_UNUSED_ENTRY(76),
199 HNS3_RX_PTYPE_UNUSED_ENTRY(77),
200 HNS3_RX_PTYPE_UNUSED_ENTRY(78),
201 HNS3_RX_PTYPE_UNUSED_ENTRY(79),
202 HNS3_RX_PTYPE_UNUSED_ENTRY(80),
203 HNS3_RX_PTYPE_UNUSED_ENTRY(81),
204 HNS3_RX_PTYPE_UNUSED_ENTRY(82),
205 HNS3_RX_PTYPE_UNUSED_ENTRY(83),
206 HNS3_RX_PTYPE_UNUSED_ENTRY(84),
207 HNS3_RX_PTYPE_UNUSED_ENTRY(85),
208 HNS3_RX_PTYPE_UNUSED_ENTRY(86),
209 HNS3_RX_PTYPE_UNUSED_ENTRY(87),
210 HNS3_RX_PTYPE_UNUSED_ENTRY(88),
211 HNS3_RX_PTYPE_UNUSED_ENTRY(89),
212 HNS3_RX_PTYPE_UNUSED_ENTRY(90),
213 HNS3_RX_PTYPE_UNUSED_ENTRY(91),
214 HNS3_RX_PTYPE_UNUSED_ENTRY(92),
215 HNS3_RX_PTYPE_UNUSED_ENTRY(93),
216 HNS3_RX_PTYPE_UNUSED_ENTRY(94),
217 HNS3_RX_PTYPE_UNUSED_ENTRY(95),
218 HNS3_RX_PTYPE_UNUSED_ENTRY(96),
219 HNS3_RX_PTYPE_UNUSED_ENTRY(97),
220 HNS3_RX_PTYPE_UNUSED_ENTRY(98),
221 HNS3_RX_PTYPE_UNUSED_ENTRY(99),
222 HNS3_RX_PTYPE_UNUSED_ENTRY(100),
223 HNS3_RX_PTYPE_UNUSED_ENTRY(101),
224 HNS3_RX_PTYPE_UNUSED_ENTRY(102),
225 HNS3_RX_PTYPE_UNUSED_ENTRY(103),
226 HNS3_RX_PTYPE_UNUSED_ENTRY(104),
227 HNS3_RX_PTYPE_UNUSED_ENTRY(105),
228 HNS3_RX_PTYPE_UNUSED_ENTRY(106),
229 HNS3_RX_PTYPE_UNUSED_ENTRY(107),
230 HNS3_RX_PTYPE_UNUSED_ENTRY(108),
231 HNS3_RX_PTYPE_UNUSED_ENTRY(109),
232 HNS3_RX_PTYPE_UNUSED_ENTRY(110),
233 HNS3_RX_PTYPE_ENTRY(111, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
234 HNS3_RX_PTYPE_ENTRY(112, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
235 HNS3_RX_PTYPE_ENTRY(113, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
236 HNS3_RX_PTYPE_ENTRY(114, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
237 HNS3_RX_PTYPE_ENTRY(115, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
238 HNS3_RX_PTYPE_ENTRY(116, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
239 HNS3_RX_PTYPE_ENTRY(117, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
240 HNS3_RX_PTYPE_ENTRY(118, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
241 HNS3_RX_PTYPE_ENTRY(119, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
242 HNS3_RX_PTYPE_UNUSED_ENTRY(120),
243 HNS3_RX_PTYPE_UNUSED_ENTRY(121),
244 HNS3_RX_PTYPE_UNUSED_ENTRY(122),
245 HNS3_RX_PTYPE_ENTRY(123, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
246 HNS3_RX_PTYPE_ENTRY(124, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
247 HNS3_RX_PTYPE_ENTRY(125, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
248 HNS3_RX_PTYPE_ENTRY(126, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
249 HNS3_RX_PTYPE_ENTRY(127, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
250 HNS3_RX_PTYPE_ENTRY(128, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
251 HNS3_RX_PTYPE_ENTRY(129, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
252 HNS3_RX_PTYPE_ENTRY(130, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
253 HNS3_RX_PTYPE_ENTRY(131, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
254 HNS3_RX_PTYPE_UNUSED_ENTRY(132),
255 HNS3_RX_PTYPE_ENTRY(133, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
256 HNS3_RX_PTYPE_ENTRY(134, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
257 HNS3_RX_PTYPE_ENTRY(135, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
258 HNS3_RX_PTYPE_ENTRY(136, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
259 HNS3_RX_PTYPE_ENTRY(137, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
260 HNS3_RX_PTYPE_ENTRY(138, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
261 HNS3_RX_PTYPE_ENTRY(139, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
262 HNS3_RX_PTYPE_UNUSED_ENTRY(140),
263 HNS3_RX_PTYPE_UNUSED_ENTRY(141),
264 HNS3_RX_PTYPE_UNUSED_ENTRY(142),
265 HNS3_RX_PTYPE_UNUSED_ENTRY(143),
266 HNS3_RX_PTYPE_UNUSED_ENTRY(144),
267 HNS3_RX_PTYPE_UNUSED_ENTRY(145),
268 HNS3_RX_PTYPE_UNUSED_ENTRY(146),
269 HNS3_RX_PTYPE_UNUSED_ENTRY(147),
270 HNS3_RX_PTYPE_UNUSED_ENTRY(148),
271 HNS3_RX_PTYPE_UNUSED_ENTRY(149),
272 HNS3_RX_PTYPE_UNUSED_ENTRY(150),
273 HNS3_RX_PTYPE_UNUSED_ENTRY(151),
274 HNS3_RX_PTYPE_UNUSED_ENTRY(152),
275 HNS3_RX_PTYPE_UNUSED_ENTRY(153),
276 HNS3_RX_PTYPE_UNUSED_ENTRY(154),
277 HNS3_RX_PTYPE_UNUSED_ENTRY(155),
278 HNS3_RX_PTYPE_UNUSED_ENTRY(156),
279 HNS3_RX_PTYPE_UNUSED_ENTRY(157),
280 HNS3_RX_PTYPE_UNUSED_ENTRY(158),
281 HNS3_RX_PTYPE_UNUSED_ENTRY(159),
282 HNS3_RX_PTYPE_UNUSED_ENTRY(160),
283 HNS3_RX_PTYPE_UNUSED_ENTRY(161),
284 HNS3_RX_PTYPE_UNUSED_ENTRY(162),
285 HNS3_RX_PTYPE_UNUSED_ENTRY(163),
286 HNS3_RX_PTYPE_UNUSED_ENTRY(164),
287 HNS3_RX_PTYPE_UNUSED_ENTRY(165),
288 HNS3_RX_PTYPE_UNUSED_ENTRY(166),
289 HNS3_RX_PTYPE_UNUSED_ENTRY(167),
290 HNS3_RX_PTYPE_UNUSED_ENTRY(168),
291 HNS3_RX_PTYPE_UNUSED_ENTRY(169),
292 HNS3_RX_PTYPE_UNUSED_ENTRY(170),
293 HNS3_RX_PTYPE_UNUSED_ENTRY(171),
294 HNS3_RX_PTYPE_UNUSED_ENTRY(172),
295 HNS3_RX_PTYPE_UNUSED_ENTRY(173),
296 HNS3_RX_PTYPE_UNUSED_ENTRY(174),
297 HNS3_RX_PTYPE_UNUSED_ENTRY(175),
298 HNS3_RX_PTYPE_UNUSED_ENTRY(176),
299 HNS3_RX_PTYPE_UNUSED_ENTRY(177),
300 HNS3_RX_PTYPE_UNUSED_ENTRY(178),
301 HNS3_RX_PTYPE_UNUSED_ENTRY(179),
302 HNS3_RX_PTYPE_UNUSED_ENTRY(180),
303 HNS3_RX_PTYPE_UNUSED_ENTRY(181),
304 HNS3_RX_PTYPE_UNUSED_ENTRY(182),
305 HNS3_RX_PTYPE_UNUSED_ENTRY(183),
306 HNS3_RX_PTYPE_UNUSED_ENTRY(184),
307 HNS3_RX_PTYPE_UNUSED_ENTRY(185),
308 HNS3_RX_PTYPE_UNUSED_ENTRY(186),
309 HNS3_RX_PTYPE_UNUSED_ENTRY(187),
310 HNS3_RX_PTYPE_UNUSED_ENTRY(188),
311 HNS3_RX_PTYPE_UNUSED_ENTRY(189),
312 HNS3_RX_PTYPE_UNUSED_ENTRY(190),
313 HNS3_RX_PTYPE_UNUSED_ENTRY(191),
314 HNS3_RX_PTYPE_UNUSED_ENTRY(192),
315 HNS3_RX_PTYPE_UNUSED_ENTRY(193),
316 HNS3_RX_PTYPE_UNUSED_ENTRY(194),
317 HNS3_RX_PTYPE_UNUSED_ENTRY(195),
318 HNS3_RX_PTYPE_UNUSED_ENTRY(196),
319 HNS3_RX_PTYPE_UNUSED_ENTRY(197),
320 HNS3_RX_PTYPE_UNUSED_ENTRY(198),
321 HNS3_RX_PTYPE_UNUSED_ENTRY(199),
322 HNS3_RX_PTYPE_UNUSED_ENTRY(200),
323 HNS3_RX_PTYPE_UNUSED_ENTRY(201),
324 HNS3_RX_PTYPE_UNUSED_ENTRY(202),
325 HNS3_RX_PTYPE_UNUSED_ENTRY(203),
326 HNS3_RX_PTYPE_UNUSED_ENTRY(204),
327 HNS3_RX_PTYPE_UNUSED_ENTRY(205),
328 HNS3_RX_PTYPE_UNUSED_ENTRY(206),
329 HNS3_RX_PTYPE_UNUSED_ENTRY(207),
330 HNS3_RX_PTYPE_UNUSED_ENTRY(208),
331 HNS3_RX_PTYPE_UNUSED_ENTRY(209),
332 HNS3_RX_PTYPE_UNUSED_ENTRY(210),
333 HNS3_RX_PTYPE_UNUSED_ENTRY(211),
334 HNS3_RX_PTYPE_UNUSED_ENTRY(212),
335 HNS3_RX_PTYPE_UNUSED_ENTRY(213),
336 HNS3_RX_PTYPE_UNUSED_ENTRY(214),
337 HNS3_RX_PTYPE_UNUSED_ENTRY(215),
338 HNS3_RX_PTYPE_UNUSED_ENTRY(216),
339 HNS3_RX_PTYPE_UNUSED_ENTRY(217),
340 HNS3_RX_PTYPE_UNUSED_ENTRY(218),
341 HNS3_RX_PTYPE_UNUSED_ENTRY(219),
342 HNS3_RX_PTYPE_UNUSED_ENTRY(220),
343 HNS3_RX_PTYPE_UNUSED_ENTRY(221),
344 HNS3_RX_PTYPE_UNUSED_ENTRY(222),
345 HNS3_RX_PTYPE_UNUSED_ENTRY(223),
346 HNS3_RX_PTYPE_UNUSED_ENTRY(224),
347 HNS3_RX_PTYPE_UNUSED_ENTRY(225),
348 HNS3_RX_PTYPE_UNUSED_ENTRY(226),
349 HNS3_RX_PTYPE_UNUSED_ENTRY(227),
350 HNS3_RX_PTYPE_UNUSED_ENTRY(228),
351 HNS3_RX_PTYPE_UNUSED_ENTRY(229),
352 HNS3_RX_PTYPE_UNUSED_ENTRY(230),
353 HNS3_RX_PTYPE_UNUSED_ENTRY(231),
354 HNS3_RX_PTYPE_UNUSED_ENTRY(232),
355 HNS3_RX_PTYPE_UNUSED_ENTRY(233),
356 HNS3_RX_PTYPE_UNUSED_ENTRY(234),
357 HNS3_RX_PTYPE_UNUSED_ENTRY(235),
358 HNS3_RX_PTYPE_UNUSED_ENTRY(236),
359 HNS3_RX_PTYPE_UNUSED_ENTRY(237),
360 HNS3_RX_PTYPE_UNUSED_ENTRY(238),
361 HNS3_RX_PTYPE_UNUSED_ENTRY(239),
362 HNS3_RX_PTYPE_UNUSED_ENTRY(240),
363 HNS3_RX_PTYPE_UNUSED_ENTRY(241),
364 HNS3_RX_PTYPE_UNUSED_ENTRY(242),
365 HNS3_RX_PTYPE_UNUSED_ENTRY(243),
366 HNS3_RX_PTYPE_UNUSED_ENTRY(244),
367 HNS3_RX_PTYPE_UNUSED_ENTRY(245),
368 HNS3_RX_PTYPE_UNUSED_ENTRY(246),
369 HNS3_RX_PTYPE_UNUSED_ENTRY(247),
370 HNS3_RX_PTYPE_UNUSED_ENTRY(248),
371 HNS3_RX_PTYPE_UNUSED_ENTRY(249),
372 HNS3_RX_PTYPE_UNUSED_ENTRY(250),
373 HNS3_RX_PTYPE_UNUSED_ENTRY(251),
374 HNS3_RX_PTYPE_UNUSED_ENTRY(252),
375 HNS3_RX_PTYPE_UNUSED_ENTRY(253),
376 HNS3_RX_PTYPE_UNUSED_ENTRY(254),
377 HNS3_RX_PTYPE_UNUSED_ENTRY(255),
378 };
379
380 #define HNS3_INVALID_PTYPE \
381 ARRAY_SIZE(hns3_rx_ptype_tbl)
382
hns3_irq_handle(int irq,void * vector)383 static irqreturn_t hns3_irq_handle(int irq, void *vector)
384 {
385 struct hns3_enet_tqp_vector *tqp_vector = vector;
386
387 napi_schedule_irqoff(&tqp_vector->napi);
388 tqp_vector->event_cnt++;
389
390 return IRQ_HANDLED;
391 }
392
hns3_nic_uninit_irq(struct hns3_nic_priv * priv)393 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
394 {
395 struct hns3_enet_tqp_vector *tqp_vectors;
396 unsigned int i;
397
398 for (i = 0; i < priv->vector_num; i++) {
399 tqp_vectors = &priv->tqp_vector[i];
400
401 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
402 continue;
403
404 /* clear the affinity mask */
405 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
406
407 /* release the irq resource */
408 free_irq(tqp_vectors->vector_irq, tqp_vectors);
409 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
410 }
411 }
412
hns3_nic_init_irq(struct hns3_nic_priv * priv)413 static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
414 {
415 struct hns3_enet_tqp_vector *tqp_vectors;
416 int txrx_int_idx = 0;
417 int rx_int_idx = 0;
418 int tx_int_idx = 0;
419 unsigned int i;
420 int ret;
421
422 for (i = 0; i < priv->vector_num; i++) {
423 tqp_vectors = &priv->tqp_vector[i];
424
425 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
426 continue;
427
428 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
429 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
430 "%s-%s-%s-%d", hns3_driver_name,
431 pci_name(priv->ae_handle->pdev),
432 "TxRx", txrx_int_idx++);
433 txrx_int_idx++;
434 } else if (tqp_vectors->rx_group.ring) {
435 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
436 "%s-%s-%s-%d", hns3_driver_name,
437 pci_name(priv->ae_handle->pdev),
438 "Rx", rx_int_idx++);
439 } else if (tqp_vectors->tx_group.ring) {
440 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
441 "%s-%s-%s-%d", hns3_driver_name,
442 pci_name(priv->ae_handle->pdev),
443 "Tx", tx_int_idx++);
444 } else {
445 /* Skip this unused q_vector */
446 continue;
447 }
448
449 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
450
451 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN);
452 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
453 tqp_vectors->name, tqp_vectors);
454 if (ret) {
455 netdev_err(priv->netdev, "request irq(%d) fail\n",
456 tqp_vectors->vector_irq);
457 hns3_nic_uninit_irq(priv);
458 return ret;
459 }
460
461 irq_set_affinity_hint(tqp_vectors->vector_irq,
462 &tqp_vectors->affinity_mask);
463
464 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
465 }
466
467 return 0;
468 }
469
hns3_mask_vector_irq(struct hns3_enet_tqp_vector * tqp_vector,u32 mask_en)470 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
471 u32 mask_en)
472 {
473 writel(mask_en, tqp_vector->mask_addr);
474 }
475
hns3_irq_enable(struct hns3_enet_tqp_vector * tqp_vector)476 static void hns3_irq_enable(struct hns3_enet_tqp_vector *tqp_vector)
477 {
478 napi_enable(&tqp_vector->napi);
479 enable_irq(tqp_vector->vector_irq);
480 }
481
hns3_irq_disable(struct hns3_enet_tqp_vector * tqp_vector)482 static void hns3_irq_disable(struct hns3_enet_tqp_vector *tqp_vector)
483 {
484 disable_irq(tqp_vector->vector_irq);
485 napi_disable(&tqp_vector->napi);
486 cancel_work_sync(&tqp_vector->rx_group.dim.work);
487 cancel_work_sync(&tqp_vector->tx_group.dim.work);
488 }
489
hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector * tqp_vector,u32 rl_value)490 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
491 u32 rl_value)
492 {
493 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
494
495 /* this defines the configuration for RL (Interrupt Rate Limiter).
496 * Rl defines rate of interrupts i.e. number of interrupts-per-second
497 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
498 */
499 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable &&
500 !tqp_vector->rx_group.coal.adapt_enable)
501 /* According to the hardware, the range of rl_reg is
502 * 0-59 and the unit is 4.
503 */
504 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
505
506 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
507 }
508
hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector * tqp_vector,u32 gl_value)509 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
510 u32 gl_value)
511 {
512 u32 new_val;
513
514 if (tqp_vector->rx_group.coal.unit_1us)
515 new_val = gl_value | HNS3_INT_GL_1US;
516 else
517 new_val = hns3_gl_usec_to_reg(gl_value);
518
519 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
520 }
521
hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector * tqp_vector,u32 gl_value)522 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
523 u32 gl_value)
524 {
525 u32 new_val;
526
527 if (tqp_vector->tx_group.coal.unit_1us)
528 new_val = gl_value | HNS3_INT_GL_1US;
529 else
530 new_val = hns3_gl_usec_to_reg(gl_value);
531
532 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
533 }
534
hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector * tqp_vector,u32 ql_value)535 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
536 u32 ql_value)
537 {
538 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET);
539 }
540
hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector * tqp_vector,u32 ql_value)541 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector,
542 u32 ql_value)
543 {
544 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET);
545 }
546
hns3_vector_coalesce_init(struct hns3_enet_tqp_vector * tqp_vector,struct hns3_nic_priv * priv)547 static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector,
548 struct hns3_nic_priv *priv)
549 {
550 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
551 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
552 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
553 struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal;
554 struct hns3_enet_coalesce *prx_coal = &priv->rx_coal;
555
556 tx_coal->adapt_enable = ptx_coal->adapt_enable;
557 rx_coal->adapt_enable = prx_coal->adapt_enable;
558
559 tx_coal->int_gl = ptx_coal->int_gl;
560 rx_coal->int_gl = prx_coal->int_gl;
561
562 rx_coal->flow_level = prx_coal->flow_level;
563 tx_coal->flow_level = ptx_coal->flow_level;
564
565 /* device version above V3(include V3), GL can configure 1us
566 * unit, so uses 1us unit.
567 */
568 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
569 tx_coal->unit_1us = 1;
570 rx_coal->unit_1us = 1;
571 }
572
573 if (ae_dev->dev_specs.int_ql_max) {
574 tx_coal->ql_enable = 1;
575 rx_coal->ql_enable = 1;
576 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
577 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
578 tx_coal->int_ql = ptx_coal->int_ql;
579 rx_coal->int_ql = prx_coal->int_ql;
580 }
581 }
582
583 static void
hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector * tqp_vector,struct hns3_nic_priv * priv)584 hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
585 struct hns3_nic_priv *priv)
586 {
587 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
588 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
589 struct hnae3_handle *h = priv->ae_handle;
590
591 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl);
592 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl);
593 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
594
595 if (tx_coal->ql_enable)
596 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql);
597
598 if (rx_coal->ql_enable)
599 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql);
600 }
601
hns3_nic_set_real_num_queue(struct net_device * netdev)602 static int hns3_nic_set_real_num_queue(struct net_device *netdev)
603 {
604 struct hnae3_handle *h = hns3_get_handle(netdev);
605 struct hnae3_knic_private_info *kinfo = &h->kinfo;
606 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
607 unsigned int queue_size = kinfo->num_tqps;
608 int i, ret;
609
610 if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) {
611 netdev_reset_tc(netdev);
612 } else {
613 ret = netdev_set_num_tc(netdev, tc_info->num_tc);
614 if (ret) {
615 netdev_err(netdev,
616 "netdev_set_num_tc fail, ret=%d!\n", ret);
617 return ret;
618 }
619
620 for (i = 0; i < tc_info->num_tc; i++)
621 netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i],
622 tc_info->tqp_offset[i]);
623 }
624
625 ret = netif_set_real_num_tx_queues(netdev, queue_size);
626 if (ret) {
627 netdev_err(netdev,
628 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
629 return ret;
630 }
631
632 ret = netif_set_real_num_rx_queues(netdev, queue_size);
633 if (ret) {
634 netdev_err(netdev,
635 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
636 return ret;
637 }
638
639 return 0;
640 }
641
hns3_get_max_available_channels(struct hnae3_handle * h)642 u16 hns3_get_max_available_channels(struct hnae3_handle *h)
643 {
644 u16 alloc_tqps, max_rss_size, rss_size;
645
646 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
647 rss_size = alloc_tqps / h->kinfo.tc_info.num_tc;
648
649 return min_t(u16, rss_size, max_rss_size);
650 }
651
hns3_tqp_enable(struct hnae3_queue * tqp)652 static void hns3_tqp_enable(struct hnae3_queue *tqp)
653 {
654 u32 rcb_reg;
655
656 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
657 rcb_reg |= BIT(HNS3_RING_EN_B);
658 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
659 }
660
hns3_tqp_disable(struct hnae3_queue * tqp)661 static void hns3_tqp_disable(struct hnae3_queue *tqp)
662 {
663 u32 rcb_reg;
664
665 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
666 rcb_reg &= ~BIT(HNS3_RING_EN_B);
667 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
668 }
669
hns3_free_rx_cpu_rmap(struct net_device * netdev)670 static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
671 {
672 #ifdef CONFIG_RFS_ACCEL
673 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
674 netdev->rx_cpu_rmap = NULL;
675 #endif
676 }
677
hns3_set_rx_cpu_rmap(struct net_device * netdev)678 static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
679 {
680 #ifdef CONFIG_RFS_ACCEL
681 struct hns3_nic_priv *priv = netdev_priv(netdev);
682 struct hns3_enet_tqp_vector *tqp_vector;
683 int i, ret;
684
685 if (!netdev->rx_cpu_rmap) {
686 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
687 if (!netdev->rx_cpu_rmap)
688 return -ENOMEM;
689 }
690
691 for (i = 0; i < priv->vector_num; i++) {
692 tqp_vector = &priv->tqp_vector[i];
693 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
694 tqp_vector->vector_irq);
695 if (ret) {
696 hns3_free_rx_cpu_rmap(netdev);
697 return ret;
698 }
699 }
700 #endif
701 return 0;
702 }
703
hns3_enable_irqs_and_tqps(struct net_device * netdev)704 static void hns3_enable_irqs_and_tqps(struct net_device *netdev)
705 {
706 struct hns3_nic_priv *priv = netdev_priv(netdev);
707 struct hnae3_handle *h = priv->ae_handle;
708 u16 i;
709
710 for (i = 0; i < priv->vector_num; i++)
711 hns3_irq_enable(&priv->tqp_vector[i]);
712
713 for (i = 0; i < priv->vector_num; i++)
714 hns3_mask_vector_irq(&priv->tqp_vector[i], 1);
715
716 for (i = 0; i < h->kinfo.num_tqps; i++)
717 hns3_tqp_enable(h->kinfo.tqp[i]);
718 }
719
hns3_disable_irqs_and_tqps(struct net_device * netdev)720 static void hns3_disable_irqs_and_tqps(struct net_device *netdev)
721 {
722 struct hns3_nic_priv *priv = netdev_priv(netdev);
723 struct hnae3_handle *h = priv->ae_handle;
724 u16 i;
725
726 for (i = 0; i < h->kinfo.num_tqps; i++)
727 hns3_tqp_disable(h->kinfo.tqp[i]);
728
729 for (i = 0; i < priv->vector_num; i++)
730 hns3_mask_vector_irq(&priv->tqp_vector[i], 0);
731
732 for (i = 0; i < priv->vector_num; i++)
733 hns3_irq_disable(&priv->tqp_vector[i]);
734 }
735
hns3_nic_net_up(struct net_device * netdev)736 static int hns3_nic_net_up(struct net_device *netdev)
737 {
738 struct hns3_nic_priv *priv = netdev_priv(netdev);
739 struct hnae3_handle *h = priv->ae_handle;
740 int ret;
741
742 ret = hns3_nic_reset_all_ring(h);
743 if (ret)
744 return ret;
745
746 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
747
748 hns3_enable_irqs_and_tqps(netdev);
749
750 /* start the ae_dev */
751 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
752 if (ret) {
753 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
754 hns3_disable_irqs_and_tqps(netdev);
755 }
756
757 return ret;
758 }
759
hns3_config_xps(struct hns3_nic_priv * priv)760 static void hns3_config_xps(struct hns3_nic_priv *priv)
761 {
762 int i;
763
764 for (i = 0; i < priv->vector_num; i++) {
765 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
766 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
767
768 while (ring) {
769 int ret;
770
771 ret = netif_set_xps_queue(priv->netdev,
772 &tqp_vector->affinity_mask,
773 ring->tqp->tqp_index);
774 if (ret)
775 netdev_warn(priv->netdev,
776 "set xps queue failed: %d", ret);
777
778 ring = ring->next;
779 }
780 }
781 }
782
hns3_nic_net_open(struct net_device * netdev)783 static int hns3_nic_net_open(struct net_device *netdev)
784 {
785 struct hns3_nic_priv *priv = netdev_priv(netdev);
786 struct hnae3_handle *h = hns3_get_handle(netdev);
787 struct hnae3_knic_private_info *kinfo;
788 int i, ret;
789
790 if (hns3_nic_resetting(netdev))
791 return -EBUSY;
792
793 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
794 netdev_warn(netdev, "net open repeatedly!\n");
795 return 0;
796 }
797
798 netif_carrier_off(netdev);
799
800 ret = hns3_nic_set_real_num_queue(netdev);
801 if (ret)
802 return ret;
803
804 ret = hns3_nic_net_up(netdev);
805 if (ret) {
806 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
807 return ret;
808 }
809
810 kinfo = &h->kinfo;
811 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
812 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]);
813
814 if (h->ae_algo->ops->set_timer_task)
815 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
816
817 hns3_config_xps(priv);
818
819 netif_dbg(h, drv, netdev, "net open\n");
820
821 return 0;
822 }
823
hns3_reset_tx_queue(struct hnae3_handle * h)824 static void hns3_reset_tx_queue(struct hnae3_handle *h)
825 {
826 struct net_device *ndev = h->kinfo.netdev;
827 struct hns3_nic_priv *priv = netdev_priv(ndev);
828 struct netdev_queue *dev_queue;
829 u32 i;
830
831 for (i = 0; i < h->kinfo.num_tqps; i++) {
832 dev_queue = netdev_get_tx_queue(ndev,
833 priv->ring[i].queue_index);
834 netdev_tx_reset_queue(dev_queue);
835 }
836 }
837
hns3_nic_net_down(struct net_device * netdev)838 static void hns3_nic_net_down(struct net_device *netdev)
839 {
840 struct hns3_nic_priv *priv = netdev_priv(netdev);
841 const struct hnae3_ae_ops *ops;
842
843 hns3_disable_irqs_and_tqps(netdev);
844
845 /* stop ae_dev */
846 ops = priv->ae_handle->ae_algo->ops;
847 if (ops->stop)
848 ops->stop(priv->ae_handle);
849
850 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
851 * during reset process, because driver may not be able
852 * to disable the ring through firmware when downing the netdev.
853 */
854 if (!hns3_nic_resetting(netdev))
855 hns3_clear_all_ring(priv->ae_handle, false);
856
857 hns3_reset_tx_queue(priv->ae_handle);
858 }
859
hns3_nic_net_stop(struct net_device * netdev)860 static int hns3_nic_net_stop(struct net_device *netdev)
861 {
862 struct hns3_nic_priv *priv = netdev_priv(netdev);
863 struct hnae3_handle *h = hns3_get_handle(netdev);
864
865 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
866 return 0;
867
868 netif_dbg(h, drv, netdev, "net stop\n");
869
870 if (h->ae_algo->ops->set_timer_task)
871 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
872
873 netif_carrier_off(netdev);
874 netif_tx_disable(netdev);
875
876 hns3_nic_net_down(netdev);
877
878 return 0;
879 }
880
hns3_nic_uc_sync(struct net_device * netdev,const unsigned char * addr)881 static int hns3_nic_uc_sync(struct net_device *netdev,
882 const unsigned char *addr)
883 {
884 struct hnae3_handle *h = hns3_get_handle(netdev);
885
886 if (h->ae_algo->ops->add_uc_addr)
887 return h->ae_algo->ops->add_uc_addr(h, addr);
888
889 return 0;
890 }
891
hns3_nic_uc_unsync(struct net_device * netdev,const unsigned char * addr)892 static int hns3_nic_uc_unsync(struct net_device *netdev,
893 const unsigned char *addr)
894 {
895 struct hnae3_handle *h = hns3_get_handle(netdev);
896
897 /* need ignore the request of removing device address, because
898 * we store the device address and other addresses of uc list
899 * in the function's mac filter list.
900 */
901 if (ether_addr_equal(addr, netdev->dev_addr))
902 return 0;
903
904 if (h->ae_algo->ops->rm_uc_addr)
905 return h->ae_algo->ops->rm_uc_addr(h, addr);
906
907 return 0;
908 }
909
hns3_nic_mc_sync(struct net_device * netdev,const unsigned char * addr)910 static int hns3_nic_mc_sync(struct net_device *netdev,
911 const unsigned char *addr)
912 {
913 struct hnae3_handle *h = hns3_get_handle(netdev);
914
915 if (h->ae_algo->ops->add_mc_addr)
916 return h->ae_algo->ops->add_mc_addr(h, addr);
917
918 return 0;
919 }
920
hns3_nic_mc_unsync(struct net_device * netdev,const unsigned char * addr)921 static int hns3_nic_mc_unsync(struct net_device *netdev,
922 const unsigned char *addr)
923 {
924 struct hnae3_handle *h = hns3_get_handle(netdev);
925
926 if (h->ae_algo->ops->rm_mc_addr)
927 return h->ae_algo->ops->rm_mc_addr(h, addr);
928
929 return 0;
930 }
931
hns3_get_netdev_flags(struct net_device * netdev)932 static u8 hns3_get_netdev_flags(struct net_device *netdev)
933 {
934 u8 flags = 0;
935
936 if (netdev->flags & IFF_PROMISC)
937 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
938 else if (netdev->flags & IFF_ALLMULTI)
939 flags = HNAE3_USER_MPE;
940
941 return flags;
942 }
943
hns3_nic_set_rx_mode(struct net_device * netdev)944 static void hns3_nic_set_rx_mode(struct net_device *netdev)
945 {
946 struct hnae3_handle *h = hns3_get_handle(netdev);
947 u8 new_flags;
948
949 new_flags = hns3_get_netdev_flags(netdev);
950
951 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
952 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync);
953
954 /* User mode Promisc mode enable and vlan filtering is disabled to
955 * let all packets in.
956 */
957 h->netdev_flags = new_flags;
958 hns3_request_update_promisc_mode(h);
959 }
960
hns3_request_update_promisc_mode(struct hnae3_handle * handle)961 void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
962 {
963 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
964
965 if (ops->request_update_promisc_mode)
966 ops->request_update_promisc_mode(handle);
967 }
968
hns3_tx_spare_space(struct hns3_enet_ring * ring)969 static u32 hns3_tx_spare_space(struct hns3_enet_ring *ring)
970 {
971 struct hns3_tx_spare *tx_spare = ring->tx_spare;
972 u32 ntc, ntu;
973
974 /* This smp_load_acquire() pairs with smp_store_release() in
975 * hns3_tx_spare_update() called in tx desc cleaning process.
976 */
977 ntc = smp_load_acquire(&tx_spare->last_to_clean);
978 ntu = tx_spare->next_to_use;
979
980 if (ntc > ntu)
981 return ntc - ntu - 1;
982
983 /* The free tx buffer is divided into two part, so pick the
984 * larger one.
985 */
986 return max(ntc, tx_spare->len - ntu) - 1;
987 }
988
hns3_tx_spare_update(struct hns3_enet_ring * ring)989 static void hns3_tx_spare_update(struct hns3_enet_ring *ring)
990 {
991 struct hns3_tx_spare *tx_spare = ring->tx_spare;
992
993 if (!tx_spare ||
994 tx_spare->last_to_clean == tx_spare->next_to_clean)
995 return;
996
997 /* This smp_store_release() pairs with smp_load_acquire() in
998 * hns3_tx_spare_space() called in xmit process.
999 */
1000 smp_store_release(&tx_spare->last_to_clean,
1001 tx_spare->next_to_clean);
1002 }
1003
hns3_can_use_tx_bounce(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 space)1004 static bool hns3_can_use_tx_bounce(struct hns3_enet_ring *ring,
1005 struct sk_buff *skb,
1006 u32 space)
1007 {
1008 u32 len = skb->len <= ring->tx_copybreak ? skb->len :
1009 skb_headlen(skb);
1010
1011 if (len > ring->tx_copybreak)
1012 return false;
1013
1014 if (ALIGN(len, dma_get_cache_alignment()) > space) {
1015 hns3_ring_stats_update(ring, tx_spare_full);
1016 return false;
1017 }
1018
1019 return true;
1020 }
1021
hns3_can_use_tx_sgl(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 space)1022 static bool hns3_can_use_tx_sgl(struct hns3_enet_ring *ring,
1023 struct sk_buff *skb,
1024 u32 space)
1025 {
1026 if (skb->len <= ring->tx_copybreak || !tx_sgl ||
1027 (!skb_has_frag_list(skb) &&
1028 skb_shinfo(skb)->nr_frags < tx_sgl))
1029 return false;
1030
1031 if (space < HNS3_MAX_SGL_SIZE) {
1032 hns3_ring_stats_update(ring, tx_spare_full);
1033 return false;
1034 }
1035
1036 return true;
1037 }
1038
hns3_init_tx_spare_buffer(struct hns3_enet_ring * ring)1039 static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring)
1040 {
1041 u32 alloc_size = ring->tqp->handle->kinfo.tx_spare_buf_size;
1042 struct hns3_tx_spare *tx_spare;
1043 struct page *page;
1044 dma_addr_t dma;
1045 int order;
1046
1047 if (!alloc_size)
1048 return;
1049
1050 order = get_order(alloc_size);
1051 if (order > MAX_ORDER) {
1052 if (net_ratelimit())
1053 dev_warn(ring_to_dev(ring), "failed to allocate tx spare buffer, exceed to max order\n");
1054 return;
1055 }
1056
1057 tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare),
1058 GFP_KERNEL);
1059 if (!tx_spare) {
1060 /* The driver still work without the tx spare buffer */
1061 dev_warn(ring_to_dev(ring), "failed to allocate hns3_tx_spare\n");
1062 goto devm_kzalloc_error;
1063 }
1064
1065 page = alloc_pages_node(dev_to_node(ring_to_dev(ring)),
1066 GFP_KERNEL, order);
1067 if (!page) {
1068 dev_warn(ring_to_dev(ring), "failed to allocate tx spare pages\n");
1069 goto alloc_pages_error;
1070 }
1071
1072 dma = dma_map_page(ring_to_dev(ring), page, 0,
1073 PAGE_SIZE << order, DMA_TO_DEVICE);
1074 if (dma_mapping_error(ring_to_dev(ring), dma)) {
1075 dev_warn(ring_to_dev(ring), "failed to map pages for tx spare\n");
1076 goto dma_mapping_error;
1077 }
1078
1079 tx_spare->dma = dma;
1080 tx_spare->buf = page_address(page);
1081 tx_spare->len = PAGE_SIZE << order;
1082 ring->tx_spare = tx_spare;
1083 return;
1084
1085 dma_mapping_error:
1086 put_page(page);
1087 alloc_pages_error:
1088 devm_kfree(ring_to_dev(ring), tx_spare);
1089 devm_kzalloc_error:
1090 ring->tqp->handle->kinfo.tx_spare_buf_size = 0;
1091 }
1092
1093 /* Use hns3_tx_spare_space() to make sure there is enough buffer
1094 * before calling below function to allocate tx buffer.
1095 */
hns3_tx_spare_alloc(struct hns3_enet_ring * ring,unsigned int size,dma_addr_t * dma,u32 * cb_len)1096 static void *hns3_tx_spare_alloc(struct hns3_enet_ring *ring,
1097 unsigned int size, dma_addr_t *dma,
1098 u32 *cb_len)
1099 {
1100 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1101 u32 ntu = tx_spare->next_to_use;
1102
1103 size = ALIGN(size, dma_get_cache_alignment());
1104 *cb_len = size;
1105
1106 /* Tx spare buffer wraps back here because the end of
1107 * freed tx buffer is not enough.
1108 */
1109 if (ntu + size > tx_spare->len) {
1110 *cb_len += (tx_spare->len - ntu);
1111 ntu = 0;
1112 }
1113
1114 tx_spare->next_to_use = ntu + size;
1115 if (tx_spare->next_to_use == tx_spare->len)
1116 tx_spare->next_to_use = 0;
1117
1118 *dma = tx_spare->dma + ntu;
1119
1120 return tx_spare->buf + ntu;
1121 }
1122
hns3_tx_spare_rollback(struct hns3_enet_ring * ring,u32 len)1123 static void hns3_tx_spare_rollback(struct hns3_enet_ring *ring, u32 len)
1124 {
1125 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1126
1127 if (len > tx_spare->next_to_use) {
1128 len -= tx_spare->next_to_use;
1129 tx_spare->next_to_use = tx_spare->len - len;
1130 } else {
1131 tx_spare->next_to_use -= len;
1132 }
1133 }
1134
hns3_tx_spare_reclaim_cb(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)1135 static void hns3_tx_spare_reclaim_cb(struct hns3_enet_ring *ring,
1136 struct hns3_desc_cb *cb)
1137 {
1138 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1139 u32 ntc = tx_spare->next_to_clean;
1140 u32 len = cb->length;
1141
1142 tx_spare->next_to_clean += len;
1143
1144 if (tx_spare->next_to_clean >= tx_spare->len) {
1145 tx_spare->next_to_clean -= tx_spare->len;
1146
1147 if (tx_spare->next_to_clean) {
1148 ntc = 0;
1149 len = tx_spare->next_to_clean;
1150 }
1151 }
1152
1153 /* This tx spare buffer is only really reclaimed after calling
1154 * hns3_tx_spare_update(), so it is still safe to use the info in
1155 * the tx buffer to do the dma sync or sg unmapping after
1156 * tx_spare->next_to_clean is moved forword.
1157 */
1158 if (cb->type & (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) {
1159 dma_addr_t dma = tx_spare->dma + ntc;
1160
1161 dma_sync_single_for_cpu(ring_to_dev(ring), dma, len,
1162 DMA_TO_DEVICE);
1163 } else {
1164 struct sg_table *sgt = tx_spare->buf + ntc;
1165
1166 dma_unmap_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
1167 DMA_TO_DEVICE);
1168 }
1169 }
1170
hns3_set_tso(struct sk_buff * skb,u32 * paylen_fdop_ol4cs,u16 * mss,u32 * type_cs_vlan_tso,u32 * send_bytes)1171 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs,
1172 u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes)
1173 {
1174 u32 l4_offset, hdr_len;
1175 union l3_hdr_info l3;
1176 union l4_hdr_info l4;
1177 u32 l4_paylen;
1178 int ret;
1179
1180 if (!skb_is_gso(skb))
1181 return 0;
1182
1183 ret = skb_cow_head(skb, 0);
1184 if (unlikely(ret < 0))
1185 return ret;
1186
1187 l3.hdr = skb_network_header(skb);
1188 l4.hdr = skb_transport_header(skb);
1189
1190 /* Software should clear the IPv4's checksum field when tso is
1191 * needed.
1192 */
1193 if (l3.v4->version == 4)
1194 l3.v4->check = 0;
1195
1196 /* tunnel packet */
1197 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
1198 SKB_GSO_GRE_CSUM |
1199 SKB_GSO_UDP_TUNNEL |
1200 SKB_GSO_UDP_TUNNEL_CSUM)) {
1201 /* reset l3&l4 pointers from outer to inner headers */
1202 l3.hdr = skb_inner_network_header(skb);
1203 l4.hdr = skb_inner_transport_header(skb);
1204
1205 /* Software should clear the IPv4's checksum field when
1206 * tso is needed.
1207 */
1208 if (l3.v4->version == 4)
1209 l3.v4->check = 0;
1210 }
1211
1212 /* normal or tunnel packet */
1213 l4_offset = l4.hdr - skb->data;
1214
1215 /* remove payload length from inner pseudo checksum when tso */
1216 l4_paylen = skb->len - l4_offset;
1217
1218 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
1219 hdr_len = sizeof(*l4.udp) + l4_offset;
1220 csum_replace_by_diff(&l4.udp->check,
1221 (__force __wsum)htonl(l4_paylen));
1222 } else {
1223 hdr_len = (l4.tcp->doff << 2) + l4_offset;
1224 csum_replace_by_diff(&l4.tcp->check,
1225 (__force __wsum)htonl(l4_paylen));
1226 }
1227
1228 *send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len;
1229
1230 /* find the txbd field values */
1231 *paylen_fdop_ol4cs = skb->len - hdr_len;
1232 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
1233
1234 /* offload outer UDP header checksum */
1235 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)
1236 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1);
1237
1238 /* get MSS for TSO */
1239 *mss = skb_shinfo(skb)->gso_size;
1240
1241 trace_hns3_tso(skb);
1242
1243 return 0;
1244 }
1245
hns3_get_l4_protocol(struct sk_buff * skb,u8 * ol4_proto,u8 * il4_proto)1246 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
1247 u8 *il4_proto)
1248 {
1249 union l3_hdr_info l3;
1250 unsigned char *l4_hdr;
1251 unsigned char *exthdr;
1252 u8 l4_proto_tmp;
1253 __be16 frag_off;
1254
1255 /* find outer header point */
1256 l3.hdr = skb_network_header(skb);
1257 l4_hdr = skb_transport_header(skb);
1258
1259 if (skb->protocol == htons(ETH_P_IPV6)) {
1260 exthdr = l3.hdr + sizeof(*l3.v6);
1261 l4_proto_tmp = l3.v6->nexthdr;
1262 if (l4_hdr != exthdr)
1263 ipv6_skip_exthdr(skb, exthdr - skb->data,
1264 &l4_proto_tmp, &frag_off);
1265 } else if (skb->protocol == htons(ETH_P_IP)) {
1266 l4_proto_tmp = l3.v4->protocol;
1267 } else {
1268 return -EINVAL;
1269 }
1270
1271 *ol4_proto = l4_proto_tmp;
1272
1273 /* tunnel packet */
1274 if (!skb->encapsulation) {
1275 *il4_proto = 0;
1276 return 0;
1277 }
1278
1279 /* find inner header point */
1280 l3.hdr = skb_inner_network_header(skb);
1281 l4_hdr = skb_inner_transport_header(skb);
1282
1283 if (l3.v6->version == 6) {
1284 exthdr = l3.hdr + sizeof(*l3.v6);
1285 l4_proto_tmp = l3.v6->nexthdr;
1286 if (l4_hdr != exthdr)
1287 ipv6_skip_exthdr(skb, exthdr - skb->data,
1288 &l4_proto_tmp, &frag_off);
1289 } else if (l3.v4->version == 4) {
1290 l4_proto_tmp = l3.v4->protocol;
1291 }
1292
1293 *il4_proto = l4_proto_tmp;
1294
1295 return 0;
1296 }
1297
1298 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
1299 * and it is udp packet, which has a dest port as the IANA assigned.
1300 * the hardware is expected to do the checksum offload, but the
1301 * hardware will not do the checksum offload when udp dest port is
1302 * 4789, 4790 or 6081.
1303 */
hns3_tunnel_csum_bug(struct sk_buff * skb)1304 static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
1305 {
1306 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1307 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
1308 union l4_hdr_info l4;
1309
1310 /* device version above V3(include V3), the hardware can
1311 * do this checksum offload.
1312 */
1313 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
1314 return false;
1315
1316 l4.hdr = skb_transport_header(skb);
1317
1318 if (!(!skb->encapsulation &&
1319 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) ||
1320 l4.udp->dest == htons(GENEVE_UDP_PORT) ||
1321 l4.udp->dest == htons(IANA_VXLAN_GPE_UDP_PORT))))
1322 return false;
1323
1324 return true;
1325 }
1326
hns3_set_outer_l2l3l4(struct sk_buff * skb,u8 ol4_proto,u32 * ol_type_vlan_len_msec)1327 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1328 u32 *ol_type_vlan_len_msec)
1329 {
1330 u32 l2_len, l3_len, l4_len;
1331 unsigned char *il2_hdr;
1332 union l3_hdr_info l3;
1333 union l4_hdr_info l4;
1334
1335 l3.hdr = skb_network_header(skb);
1336 l4.hdr = skb_transport_header(skb);
1337
1338 /* compute OL2 header size, defined in 2 Bytes */
1339 l2_len = l3.hdr - skb->data;
1340 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
1341
1342 /* compute OL3 header size, defined in 4 Bytes */
1343 l3_len = l4.hdr - l3.hdr;
1344 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
1345
1346 il2_hdr = skb_inner_mac_header(skb);
1347 /* compute OL4 header size, defined in 4 Bytes */
1348 l4_len = il2_hdr - l4.hdr;
1349 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
1350
1351 /* define outer network header type */
1352 if (skb->protocol == htons(ETH_P_IP)) {
1353 if (skb_is_gso(skb))
1354 hns3_set_field(*ol_type_vlan_len_msec,
1355 HNS3_TXD_OL3T_S,
1356 HNS3_OL3T_IPV4_CSUM);
1357 else
1358 hns3_set_field(*ol_type_vlan_len_msec,
1359 HNS3_TXD_OL3T_S,
1360 HNS3_OL3T_IPV4_NO_CSUM);
1361 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1362 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
1363 HNS3_OL3T_IPV6);
1364 }
1365
1366 if (ol4_proto == IPPROTO_UDP)
1367 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1368 HNS3_TUN_MAC_IN_UDP);
1369 else if (ol4_proto == IPPROTO_GRE)
1370 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1371 HNS3_TUN_NVGRE);
1372 }
1373
hns3_set_l3_type(struct sk_buff * skb,union l3_hdr_info l3,u32 * type_cs_vlan_tso)1374 static void hns3_set_l3_type(struct sk_buff *skb, union l3_hdr_info l3,
1375 u32 *type_cs_vlan_tso)
1376 {
1377 if (l3.v4->version == 4) {
1378 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1379 HNS3_L3T_IPV4);
1380
1381 /* the stack computes the IP header already, the only time we
1382 * need the hardware to recompute it is in the case of TSO.
1383 */
1384 if (skb_is_gso(skb))
1385 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
1386 } else if (l3.v6->version == 6) {
1387 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1388 HNS3_L3T_IPV6);
1389 }
1390 }
1391
hns3_set_l4_csum_length(struct sk_buff * skb,union l4_hdr_info l4,u32 l4_proto,u32 * type_cs_vlan_tso)1392 static int hns3_set_l4_csum_length(struct sk_buff *skb, union l4_hdr_info l4,
1393 u32 l4_proto, u32 *type_cs_vlan_tso)
1394 {
1395 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
1396 switch (l4_proto) {
1397 case IPPROTO_TCP:
1398 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1399 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1400 HNS3_L4T_TCP);
1401 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1402 l4.tcp->doff);
1403 break;
1404 case IPPROTO_UDP:
1405 if (hns3_tunnel_csum_bug(skb)) {
1406 int ret = skb_put_padto(skb, HNS3_MIN_TUN_PKT_LEN);
1407
1408 return ret ? ret : skb_checksum_help(skb);
1409 }
1410
1411 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1412 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1413 HNS3_L4T_UDP);
1414 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1415 (sizeof(struct udphdr) >> 2));
1416 break;
1417 case IPPROTO_SCTP:
1418 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1419 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1420 HNS3_L4T_SCTP);
1421 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1422 (sizeof(struct sctphdr) >> 2));
1423 break;
1424 default:
1425 /* drop the skb tunnel packet if hardware don't support,
1426 * because hardware can't calculate csum when TSO.
1427 */
1428 if (skb_is_gso(skb))
1429 return -EDOM;
1430
1431 /* the stack computes the IP header already,
1432 * driver calculate l4 checksum when not TSO.
1433 */
1434 return skb_checksum_help(skb);
1435 }
1436
1437 return 0;
1438 }
1439
hns3_set_l2l3l4(struct sk_buff * skb,u8 ol4_proto,u8 il4_proto,u32 * type_cs_vlan_tso,u32 * ol_type_vlan_len_msec)1440 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1441 u8 il4_proto, u32 *type_cs_vlan_tso,
1442 u32 *ol_type_vlan_len_msec)
1443 {
1444 unsigned char *l2_hdr = skb->data;
1445 u32 l4_proto = ol4_proto;
1446 union l4_hdr_info l4;
1447 union l3_hdr_info l3;
1448 u32 l2_len, l3_len;
1449
1450 l4.hdr = skb_transport_header(skb);
1451 l3.hdr = skb_network_header(skb);
1452
1453 /* handle encapsulation skb */
1454 if (skb->encapsulation) {
1455 /* If this is a not UDP/GRE encapsulation skb */
1456 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
1457 /* drop the skb tunnel packet if hardware don't support,
1458 * because hardware can't calculate csum when TSO.
1459 */
1460 if (skb_is_gso(skb))
1461 return -EDOM;
1462
1463 /* the stack computes the IP header already,
1464 * driver calculate l4 checksum when not TSO.
1465 */
1466 return skb_checksum_help(skb);
1467 }
1468
1469 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
1470
1471 /* switch to inner header */
1472 l2_hdr = skb_inner_mac_header(skb);
1473 l3.hdr = skb_inner_network_header(skb);
1474 l4.hdr = skb_inner_transport_header(skb);
1475 l4_proto = il4_proto;
1476 }
1477
1478 hns3_set_l3_type(skb, l3, type_cs_vlan_tso);
1479
1480 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
1481 l2_len = l3.hdr - l2_hdr;
1482 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
1483
1484 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
1485 l3_len = l4.hdr - l3.hdr;
1486 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
1487
1488 return hns3_set_l4_csum_length(skb, l4, l4_proto, type_cs_vlan_tso);
1489 }
1490
hns3_handle_vtags(struct hns3_enet_ring * tx_ring,struct sk_buff * skb)1491 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
1492 struct sk_buff *skb)
1493 {
1494 struct hnae3_handle *handle = tx_ring->tqp->handle;
1495 struct hnae3_ae_dev *ae_dev;
1496 struct vlan_ethhdr *vhdr;
1497 int rc;
1498
1499 if (!(skb->protocol == htons(ETH_P_8021Q) ||
1500 skb_vlan_tag_present(skb)))
1501 return 0;
1502
1503 /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert
1504 * VLAN enabled, only one VLAN header is allowed in skb, otherwise it
1505 * will cause RAS error.
1506 */
1507 ae_dev = pci_get_drvdata(handle->pdev);
1508 if (unlikely(skb_vlan_tagged_multi(skb) &&
1509 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 &&
1510 handle->port_base_vlan_state ==
1511 HNAE3_PORT_BASE_VLAN_ENABLE))
1512 return -EINVAL;
1513
1514 if (skb->protocol == htons(ETH_P_8021Q) &&
1515 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1516 /* When HW VLAN acceleration is turned off, and the stack
1517 * sets the protocol to 802.1q, the driver just need to
1518 * set the protocol to the encapsulated ethertype.
1519 */
1520 skb->protocol = vlan_get_protocol(skb);
1521 return 0;
1522 }
1523
1524 if (skb_vlan_tag_present(skb)) {
1525 /* Based on hw strategy, use out_vtag in two layer tag case,
1526 * and use inner_vtag in one tag case.
1527 */
1528 if (skb->protocol == htons(ETH_P_8021Q) &&
1529 handle->port_base_vlan_state ==
1530 HNAE3_PORT_BASE_VLAN_DISABLE)
1531 rc = HNS3_OUTER_VLAN_TAG;
1532 else
1533 rc = HNS3_INNER_VLAN_TAG;
1534
1535 skb->protocol = vlan_get_protocol(skb);
1536 return rc;
1537 }
1538
1539 rc = skb_cow_head(skb, 0);
1540 if (unlikely(rc < 0))
1541 return rc;
1542
1543 vhdr = skb_vlan_eth_hdr(skb);
1544 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1545 & VLAN_PRIO_MASK);
1546
1547 skb->protocol = vlan_get_protocol(skb);
1548 return 0;
1549 }
1550
1551 /* check if the hardware is capable of checksum offloading */
hns3_check_hw_tx_csum(struct sk_buff * skb)1552 static bool hns3_check_hw_tx_csum(struct sk_buff *skb)
1553 {
1554 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1555
1556 /* Kindly note, due to backward compatibility of the TX descriptor,
1557 * HW checksum of the non-IP packets and GSO packets is handled at
1558 * different place in the following code
1559 */
1560 if (skb_csum_is_sctp(skb) || skb_is_gso(skb) ||
1561 !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state))
1562 return false;
1563
1564 return true;
1565 }
1566
1567 struct hns3_desc_param {
1568 u32 paylen_ol4cs;
1569 u32 ol_type_vlan_len_msec;
1570 u32 type_cs_vlan_tso;
1571 u16 mss_hw_csum;
1572 u16 inner_vtag;
1573 u16 out_vtag;
1574 };
1575
hns3_init_desc_data(struct sk_buff * skb,struct hns3_desc_param * pa)1576 static void hns3_init_desc_data(struct sk_buff *skb, struct hns3_desc_param *pa)
1577 {
1578 pa->paylen_ol4cs = skb->len;
1579 pa->ol_type_vlan_len_msec = 0;
1580 pa->type_cs_vlan_tso = 0;
1581 pa->mss_hw_csum = 0;
1582 pa->inner_vtag = 0;
1583 pa->out_vtag = 0;
1584 }
1585
hns3_handle_vlan_info(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_param * param)1586 static int hns3_handle_vlan_info(struct hns3_enet_ring *ring,
1587 struct sk_buff *skb,
1588 struct hns3_desc_param *param)
1589 {
1590 int ret;
1591
1592 ret = hns3_handle_vtags(ring, skb);
1593 if (unlikely(ret < 0)) {
1594 hns3_ring_stats_update(ring, tx_vlan_err);
1595 return ret;
1596 } else if (ret == HNS3_INNER_VLAN_TAG) {
1597 param->inner_vtag = skb_vlan_tag_get(skb);
1598 param->inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1599 VLAN_PRIO_MASK;
1600 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1601 } else if (ret == HNS3_OUTER_VLAN_TAG) {
1602 param->out_vtag = skb_vlan_tag_get(skb);
1603 param->out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1604 VLAN_PRIO_MASK;
1605 hns3_set_field(param->ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1606 1);
1607 }
1608 return 0;
1609 }
1610
hns3_handle_csum_partial(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_cb * desc_cb,struct hns3_desc_param * param)1611 static int hns3_handle_csum_partial(struct hns3_enet_ring *ring,
1612 struct sk_buff *skb,
1613 struct hns3_desc_cb *desc_cb,
1614 struct hns3_desc_param *param)
1615 {
1616 u8 ol4_proto, il4_proto;
1617 int ret;
1618
1619 if (hns3_check_hw_tx_csum(skb)) {
1620 /* set checksum start and offset, defined in 2 Bytes */
1621 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_CSUM_START_S,
1622 skb_checksum_start_offset(skb) >> 1);
1623 hns3_set_field(param->ol_type_vlan_len_msec,
1624 HNS3_TXD_CSUM_OFFSET_S,
1625 skb->csum_offset >> 1);
1626 param->mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B);
1627 return 0;
1628 }
1629
1630 skb_reset_mac_len(skb);
1631
1632 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1633 if (unlikely(ret < 0)) {
1634 hns3_ring_stats_update(ring, tx_l4_proto_err);
1635 return ret;
1636 }
1637
1638 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1639 ¶m->type_cs_vlan_tso,
1640 ¶m->ol_type_vlan_len_msec);
1641 if (unlikely(ret < 0)) {
1642 hns3_ring_stats_update(ring, tx_l2l3l4_err);
1643 return ret;
1644 }
1645
1646 ret = hns3_set_tso(skb, ¶m->paylen_ol4cs, ¶m->mss_hw_csum,
1647 ¶m->type_cs_vlan_tso, &desc_cb->send_bytes);
1648 if (unlikely(ret < 0)) {
1649 hns3_ring_stats_update(ring, tx_tso_err);
1650 return ret;
1651 }
1652 return 0;
1653 }
1654
hns3_fill_skb_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc * desc,struct hns3_desc_cb * desc_cb)1655 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
1656 struct sk_buff *skb, struct hns3_desc *desc,
1657 struct hns3_desc_cb *desc_cb)
1658 {
1659 struct hns3_desc_param param;
1660 int ret;
1661
1662 hns3_init_desc_data(skb, ¶m);
1663 ret = hns3_handle_vlan_info(ring, skb, ¶m);
1664 if (unlikely(ret < 0))
1665 return ret;
1666
1667 desc_cb->send_bytes = skb->len;
1668
1669 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1670 ret = hns3_handle_csum_partial(ring, skb, desc_cb, ¶m);
1671 if (ret)
1672 return ret;
1673 }
1674
1675 /* Set txbd */
1676 desc->tx.ol_type_vlan_len_msec =
1677 cpu_to_le32(param.ol_type_vlan_len_msec);
1678 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(param.type_cs_vlan_tso);
1679 desc->tx.paylen_ol4cs = cpu_to_le32(param.paylen_ol4cs);
1680 desc->tx.mss_hw_csum = cpu_to_le16(param.mss_hw_csum);
1681 desc->tx.vlan_tag = cpu_to_le16(param.inner_vtag);
1682 desc->tx.outer_vlan_tag = cpu_to_le16(param.out_vtag);
1683
1684 return 0;
1685 }
1686
hns3_fill_desc(struct hns3_enet_ring * ring,dma_addr_t dma,unsigned int size)1687 static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma,
1688 unsigned int size)
1689 {
1690 #define HNS3_LIKELY_BD_NUM 1
1691
1692 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1693 unsigned int frag_buf_num;
1694 int k, sizeoflast;
1695
1696 if (likely(size <= HNS3_MAX_BD_SIZE)) {
1697 desc->addr = cpu_to_le64(dma);
1698 desc->tx.send_size = cpu_to_le16(size);
1699 desc->tx.bdtp_fe_sc_vld_ra_ri =
1700 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1701
1702 trace_hns3_tx_desc(ring, ring->next_to_use);
1703 ring_ptr_move_fw(ring, next_to_use);
1704 return HNS3_LIKELY_BD_NUM;
1705 }
1706
1707 frag_buf_num = hns3_tx_bd_count(size);
1708 sizeoflast = size % HNS3_MAX_BD_SIZE;
1709 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1710
1711 /* When frag size is bigger than hardware limit, split this frag */
1712 for (k = 0; k < frag_buf_num; k++) {
1713 /* now, fill the descriptor */
1714 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
1715 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1716 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1717 desc->tx.bdtp_fe_sc_vld_ra_ri =
1718 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1719
1720 trace_hns3_tx_desc(ring, ring->next_to_use);
1721 /* move ring pointer to next */
1722 ring_ptr_move_fw(ring, next_to_use);
1723
1724 desc = &ring->desc[ring->next_to_use];
1725 }
1726
1727 return frag_buf_num;
1728 }
1729
hns3_map_and_fill_desc(struct hns3_enet_ring * ring,void * priv,unsigned int type)1730 static int hns3_map_and_fill_desc(struct hns3_enet_ring *ring, void *priv,
1731 unsigned int type)
1732 {
1733 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1734 struct device *dev = ring_to_dev(ring);
1735 unsigned int size;
1736 dma_addr_t dma;
1737
1738 if (type & (DESC_TYPE_FRAGLIST_SKB | DESC_TYPE_SKB)) {
1739 struct sk_buff *skb = (struct sk_buff *)priv;
1740
1741 size = skb_headlen(skb);
1742 if (!size)
1743 return 0;
1744
1745 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1746 } else if (type & DESC_TYPE_BOUNCE_HEAD) {
1747 /* Head data has been filled in hns3_handle_tx_bounce(),
1748 * just return 0 here.
1749 */
1750 return 0;
1751 } else {
1752 skb_frag_t *frag = (skb_frag_t *)priv;
1753
1754 size = skb_frag_size(frag);
1755 if (!size)
1756 return 0;
1757
1758 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1759 }
1760
1761 if (unlikely(dma_mapping_error(dev, dma))) {
1762 hns3_ring_stats_update(ring, sw_err_cnt);
1763 return -ENOMEM;
1764 }
1765
1766 desc_cb->priv = priv;
1767 desc_cb->length = size;
1768 desc_cb->dma = dma;
1769 desc_cb->type = type;
1770
1771 return hns3_fill_desc(ring, dma, size);
1772 }
1773
hns3_skb_bd_num(struct sk_buff * skb,unsigned int * bd_size,unsigned int bd_num)1774 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1775 unsigned int bd_num)
1776 {
1777 unsigned int size;
1778 int i;
1779
1780 size = skb_headlen(skb);
1781 while (size > HNS3_MAX_BD_SIZE) {
1782 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1783 size -= HNS3_MAX_BD_SIZE;
1784
1785 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1786 return bd_num;
1787 }
1788
1789 if (size) {
1790 bd_size[bd_num++] = size;
1791 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1792 return bd_num;
1793 }
1794
1795 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1796 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1797 size = skb_frag_size(frag);
1798 if (!size)
1799 continue;
1800
1801 while (size > HNS3_MAX_BD_SIZE) {
1802 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1803 size -= HNS3_MAX_BD_SIZE;
1804
1805 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1806 return bd_num;
1807 }
1808
1809 bd_size[bd_num++] = size;
1810 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1811 return bd_num;
1812 }
1813
1814 return bd_num;
1815 }
1816
hns3_tx_bd_num(struct sk_buff * skb,unsigned int * bd_size,u8 max_non_tso_bd_num,unsigned int bd_num,unsigned int recursion_level)1817 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1818 u8 max_non_tso_bd_num, unsigned int bd_num,
1819 unsigned int recursion_level)
1820 {
1821 #define HNS3_MAX_RECURSION_LEVEL 24
1822
1823 struct sk_buff *frag_skb;
1824
1825 /* If the total len is within the max bd limit */
1826 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !recursion_level &&
1827 !skb_has_frag_list(skb) &&
1828 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num))
1829 return skb_shinfo(skb)->nr_frags + 1U;
1830
1831 if (unlikely(recursion_level >= HNS3_MAX_RECURSION_LEVEL))
1832 return UINT_MAX;
1833
1834 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
1835 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1836 return bd_num;
1837
1838 skb_walk_frags(skb, frag_skb) {
1839 bd_num = hns3_tx_bd_num(frag_skb, bd_size, max_non_tso_bd_num,
1840 bd_num, recursion_level + 1);
1841 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1842 return bd_num;
1843 }
1844
1845 return bd_num;
1846 }
1847
hns3_gso_hdr_len(struct sk_buff * skb)1848 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1849 {
1850 if (!skb->encapsulation)
1851 return skb_tcp_all_headers(skb);
1852
1853 return skb_inner_tcp_all_headers(skb);
1854 }
1855
1856 /* HW need every continuous max_non_tso_bd_num buffer data to be larger
1857 * than MSS, we simplify it by ensuring skb_headlen + the first continuous
1858 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss,
1859 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger
1860 * than MSS except the last max_non_tso_bd_num - 1 frags.
1861 */
hns3_skb_need_linearized(struct sk_buff * skb,unsigned int * bd_size,unsigned int bd_num,u8 max_non_tso_bd_num)1862 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
1863 unsigned int bd_num, u8 max_non_tso_bd_num)
1864 {
1865 unsigned int tot_len = 0;
1866 int i;
1867
1868 for (i = 0; i < max_non_tso_bd_num - 1U; i++)
1869 tot_len += bd_size[i];
1870
1871 /* ensure the first max_non_tso_bd_num frags is greater than
1872 * mss + header
1873 */
1874 if (tot_len + bd_size[max_non_tso_bd_num - 1U] <
1875 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
1876 return true;
1877
1878 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater
1879 * than mss except the last one.
1880 */
1881 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) {
1882 tot_len -= bd_size[i];
1883 tot_len += bd_size[i + max_non_tso_bd_num - 1U];
1884
1885 if (tot_len < skb_shinfo(skb)->gso_size)
1886 return true;
1887 }
1888
1889 return false;
1890 }
1891
hns3_shinfo_pack(struct skb_shared_info * shinfo,__u32 * size)1892 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1893 {
1894 int i;
1895
1896 for (i = 0; i < MAX_SKB_FRAGS; i++)
1897 size[i] = skb_frag_size(&shinfo->frags[i]);
1898 }
1899
hns3_skb_linearize(struct hns3_enet_ring * ring,struct sk_buff * skb,unsigned int bd_num)1900 static int hns3_skb_linearize(struct hns3_enet_ring *ring,
1901 struct sk_buff *skb,
1902 unsigned int bd_num)
1903 {
1904 /* 'bd_num == UINT_MAX' means the skb' fraglist has a
1905 * recursion level of over HNS3_MAX_RECURSION_LEVEL.
1906 */
1907 if (bd_num == UINT_MAX) {
1908 hns3_ring_stats_update(ring, over_max_recursion);
1909 return -ENOMEM;
1910 }
1911
1912 /* The skb->len has exceeded the hw limitation, linearization
1913 * will not help.
1914 */
1915 if (skb->len > HNS3_MAX_TSO_SIZE ||
1916 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)) {
1917 hns3_ring_stats_update(ring, hw_limitation);
1918 return -ENOMEM;
1919 }
1920
1921 if (__skb_linearize(skb)) {
1922 hns3_ring_stats_update(ring, sw_err_cnt);
1923 return -ENOMEM;
1924 }
1925
1926 return 0;
1927 }
1928
hns3_nic_maybe_stop_tx(struct hns3_enet_ring * ring,struct net_device * netdev,struct sk_buff * skb)1929 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
1930 struct net_device *netdev,
1931 struct sk_buff *skb)
1932 {
1933 struct hns3_nic_priv *priv = netdev_priv(netdev);
1934 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num;
1935 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
1936 unsigned int bd_num;
1937
1938 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num, 0, 0);
1939 if (unlikely(bd_num > max_non_tso_bd_num)) {
1940 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
1941 !hns3_skb_need_linearized(skb, bd_size, bd_num,
1942 max_non_tso_bd_num)) {
1943 trace_hns3_over_max_bd(skb);
1944 goto out;
1945 }
1946
1947 if (hns3_skb_linearize(ring, skb, bd_num))
1948 return -ENOMEM;
1949
1950 bd_num = hns3_tx_bd_count(skb->len);
1951
1952 hns3_ring_stats_update(ring, tx_copy);
1953 }
1954
1955 out:
1956 if (likely(ring_space(ring) >= bd_num))
1957 return bd_num;
1958
1959 netif_stop_subqueue(netdev, ring->queue_index);
1960 smp_mb(); /* Memory barrier before checking ring_space */
1961
1962 /* Start queue in case hns3_clean_tx_ring has just made room
1963 * available and has not seen the queue stopped state performed
1964 * by netif_stop_subqueue above.
1965 */
1966 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) &&
1967 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1968 netif_start_subqueue(netdev, ring->queue_index);
1969 return bd_num;
1970 }
1971
1972 hns3_ring_stats_update(ring, tx_busy);
1973
1974 return -EBUSY;
1975 }
1976
hns3_clear_desc(struct hns3_enet_ring * ring,int next_to_use_orig)1977 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
1978 {
1979 struct device *dev = ring_to_dev(ring);
1980 unsigned int i;
1981
1982 for (i = 0; i < ring->desc_num; i++) {
1983 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1984 struct hns3_desc_cb *desc_cb;
1985
1986 memset(desc, 0, sizeof(*desc));
1987
1988 /* check if this is where we started */
1989 if (ring->next_to_use == next_to_use_orig)
1990 break;
1991
1992 /* rollback one */
1993 ring_ptr_move_bw(ring, next_to_use);
1994
1995 desc_cb = &ring->desc_cb[ring->next_to_use];
1996
1997 if (!desc_cb->dma)
1998 continue;
1999
2000 /* unmap the descriptor dma address */
2001 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
2002 dma_unmap_single(dev, desc_cb->dma, desc_cb->length,
2003 DMA_TO_DEVICE);
2004 else if (desc_cb->type &
2005 (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL))
2006 hns3_tx_spare_rollback(ring, desc_cb->length);
2007 else if (desc_cb->length)
2008 dma_unmap_page(dev, desc_cb->dma, desc_cb->length,
2009 DMA_TO_DEVICE);
2010
2011 desc_cb->length = 0;
2012 desc_cb->dma = 0;
2013 desc_cb->type = DESC_TYPE_UNKNOWN;
2014 }
2015 }
2016
hns3_fill_skb_to_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,unsigned int type)2017 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
2018 struct sk_buff *skb, unsigned int type)
2019 {
2020 struct sk_buff *frag_skb;
2021 int i, ret, bd_num = 0;
2022
2023 ret = hns3_map_and_fill_desc(ring, skb, type);
2024 if (unlikely(ret < 0))
2025 return ret;
2026
2027 bd_num += ret;
2028
2029 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2030 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2031
2032 ret = hns3_map_and_fill_desc(ring, frag, DESC_TYPE_PAGE);
2033 if (unlikely(ret < 0))
2034 return ret;
2035
2036 bd_num += ret;
2037 }
2038
2039 skb_walk_frags(skb, frag_skb) {
2040 ret = hns3_fill_skb_to_desc(ring, frag_skb,
2041 DESC_TYPE_FRAGLIST_SKB);
2042 if (unlikely(ret < 0))
2043 return ret;
2044
2045 bd_num += ret;
2046 }
2047
2048 return bd_num;
2049 }
2050
hns3_tx_push_bd(struct hns3_enet_ring * ring,int num)2051 static void hns3_tx_push_bd(struct hns3_enet_ring *ring, int num)
2052 {
2053 #define HNS3_BYTES_PER_64BIT 8
2054
2055 struct hns3_desc desc[HNS3_MAX_PUSH_BD_NUM] = {};
2056 int offset = 0;
2057
2058 /* make sure everything is visible to device before
2059 * excuting tx push or updating doorbell
2060 */
2061 dma_wmb();
2062
2063 do {
2064 int idx = (ring->next_to_use - num + ring->desc_num) %
2065 ring->desc_num;
2066
2067 u64_stats_update_begin(&ring->syncp);
2068 ring->stats.tx_push++;
2069 u64_stats_update_end(&ring->syncp);
2070 memcpy(&desc[offset], &ring->desc[idx],
2071 sizeof(struct hns3_desc));
2072 offset++;
2073 } while (--num);
2074
2075 __iowrite64_copy(ring->tqp->mem_base, desc,
2076 (sizeof(struct hns3_desc) * HNS3_MAX_PUSH_BD_NUM) /
2077 HNS3_BYTES_PER_64BIT);
2078
2079 io_stop_wc();
2080 }
2081
hns3_tx_mem_doorbell(struct hns3_enet_ring * ring)2082 static void hns3_tx_mem_doorbell(struct hns3_enet_ring *ring)
2083 {
2084 #define HNS3_MEM_DOORBELL_OFFSET 64
2085
2086 __le64 bd_num = cpu_to_le64((u64)ring->pending_buf);
2087
2088 /* make sure everything is visible to device before
2089 * excuting tx push or updating doorbell
2090 */
2091 dma_wmb();
2092
2093 __iowrite64_copy(ring->tqp->mem_base + HNS3_MEM_DOORBELL_OFFSET,
2094 &bd_num, 1);
2095 u64_stats_update_begin(&ring->syncp);
2096 ring->stats.tx_mem_doorbell += ring->pending_buf;
2097 u64_stats_update_end(&ring->syncp);
2098
2099 io_stop_wc();
2100 }
2101
hns3_tx_doorbell(struct hns3_enet_ring * ring,int num,bool doorbell)2102 static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num,
2103 bool doorbell)
2104 {
2105 struct net_device *netdev = ring_to_netdev(ring);
2106 struct hns3_nic_priv *priv = netdev_priv(netdev);
2107
2108 /* when tx push is enabled, the packet whose number of BD below
2109 * HNS3_MAX_PUSH_BD_NUM can be pushed directly.
2110 */
2111 if (test_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state) && num &&
2112 !ring->pending_buf && num <= HNS3_MAX_PUSH_BD_NUM && doorbell) {
2113 /* This smp_store_release() pairs with smp_load_aquire() in
2114 * hns3_nic_reclaim_desc(). Ensure that the BD valid bit
2115 * is updated.
2116 */
2117 smp_store_release(&ring->last_to_use, ring->next_to_use);
2118 hns3_tx_push_bd(ring, num);
2119 return;
2120 }
2121
2122 ring->pending_buf += num;
2123
2124 if (!doorbell) {
2125 hns3_ring_stats_update(ring, tx_more);
2126 return;
2127 }
2128
2129 /* This smp_store_release() pairs with smp_load_aquire() in
2130 * hns3_nic_reclaim_desc(). Ensure that the BD valid bit is updated.
2131 */
2132 smp_store_release(&ring->last_to_use, ring->next_to_use);
2133
2134 if (ring->tqp->mem_base)
2135 hns3_tx_mem_doorbell(ring);
2136 else
2137 writel(ring->pending_buf,
2138 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG);
2139
2140 ring->pending_buf = 0;
2141 }
2142
hns3_tsyn(struct net_device * netdev,struct sk_buff * skb,struct hns3_desc * desc)2143 static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb,
2144 struct hns3_desc *desc)
2145 {
2146 struct hnae3_handle *h = hns3_get_handle(netdev);
2147
2148 if (!(h->ae_algo->ops->set_tx_hwts_info &&
2149 h->ae_algo->ops->set_tx_hwts_info(h, skb)))
2150 return;
2151
2152 desc->tx.bdtp_fe_sc_vld_ra_ri |= cpu_to_le16(BIT(HNS3_TXD_TSYN_B));
2153 }
2154
hns3_handle_tx_bounce(struct hns3_enet_ring * ring,struct sk_buff * skb)2155 static int hns3_handle_tx_bounce(struct hns3_enet_ring *ring,
2156 struct sk_buff *skb)
2157 {
2158 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2159 unsigned int type = DESC_TYPE_BOUNCE_HEAD;
2160 unsigned int size = skb_headlen(skb);
2161 dma_addr_t dma;
2162 int bd_num = 0;
2163 u32 cb_len;
2164 void *buf;
2165 int ret;
2166
2167 if (skb->len <= ring->tx_copybreak) {
2168 size = skb->len;
2169 type = DESC_TYPE_BOUNCE_ALL;
2170 }
2171
2172 /* hns3_can_use_tx_bounce() is called to ensure the below
2173 * function can always return the tx buffer.
2174 */
2175 buf = hns3_tx_spare_alloc(ring, size, &dma, &cb_len);
2176
2177 ret = skb_copy_bits(skb, 0, buf, size);
2178 if (unlikely(ret < 0)) {
2179 hns3_tx_spare_rollback(ring, cb_len);
2180 hns3_ring_stats_update(ring, copy_bits_err);
2181 return ret;
2182 }
2183
2184 desc_cb->priv = skb;
2185 desc_cb->length = cb_len;
2186 desc_cb->dma = dma;
2187 desc_cb->type = type;
2188
2189 bd_num += hns3_fill_desc(ring, dma, size);
2190
2191 if (type == DESC_TYPE_BOUNCE_HEAD) {
2192 ret = hns3_fill_skb_to_desc(ring, skb,
2193 DESC_TYPE_BOUNCE_HEAD);
2194 if (unlikely(ret < 0))
2195 return ret;
2196
2197 bd_num += ret;
2198 }
2199
2200 dma_sync_single_for_device(ring_to_dev(ring), dma, size,
2201 DMA_TO_DEVICE);
2202
2203 hns3_ring_stats_update(ring, tx_bounce);
2204
2205 return bd_num;
2206 }
2207
hns3_handle_tx_sgl(struct hns3_enet_ring * ring,struct sk_buff * skb)2208 static int hns3_handle_tx_sgl(struct hns3_enet_ring *ring,
2209 struct sk_buff *skb)
2210 {
2211 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2212 u32 nfrag = skb_shinfo(skb)->nr_frags + 1;
2213 struct sg_table *sgt;
2214 int i, bd_num = 0;
2215 dma_addr_t dma;
2216 u32 cb_len;
2217 int nents;
2218
2219 if (skb_has_frag_list(skb))
2220 nfrag = HNS3_MAX_TSO_BD_NUM;
2221
2222 /* hns3_can_use_tx_sgl() is called to ensure the below
2223 * function can always return the tx buffer.
2224 */
2225 sgt = hns3_tx_spare_alloc(ring, HNS3_SGL_SIZE(nfrag),
2226 &dma, &cb_len);
2227
2228 /* scatterlist follows by the sg table */
2229 sgt->sgl = (struct scatterlist *)(sgt + 1);
2230 sg_init_table(sgt->sgl, nfrag);
2231 nents = skb_to_sgvec(skb, sgt->sgl, 0, skb->len);
2232 if (unlikely(nents < 0)) {
2233 hns3_tx_spare_rollback(ring, cb_len);
2234 hns3_ring_stats_update(ring, skb2sgl_err);
2235 return -ENOMEM;
2236 }
2237
2238 sgt->orig_nents = nents;
2239 sgt->nents = dma_map_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
2240 DMA_TO_DEVICE);
2241 if (unlikely(!sgt->nents)) {
2242 hns3_tx_spare_rollback(ring, cb_len);
2243 hns3_ring_stats_update(ring, map_sg_err);
2244 return -ENOMEM;
2245 }
2246
2247 desc_cb->priv = skb;
2248 desc_cb->length = cb_len;
2249 desc_cb->dma = dma;
2250 desc_cb->type = DESC_TYPE_SGL_SKB;
2251
2252 for (i = 0; i < sgt->nents; i++)
2253 bd_num += hns3_fill_desc(ring, sg_dma_address(sgt->sgl + i),
2254 sg_dma_len(sgt->sgl + i));
2255 hns3_ring_stats_update(ring, tx_sgl);
2256
2257 return bd_num;
2258 }
2259
hns3_handle_desc_filling(struct hns3_enet_ring * ring,struct sk_buff * skb)2260 static int hns3_handle_desc_filling(struct hns3_enet_ring *ring,
2261 struct sk_buff *skb)
2262 {
2263 u32 space;
2264
2265 if (!ring->tx_spare)
2266 goto out;
2267
2268 space = hns3_tx_spare_space(ring);
2269
2270 if (hns3_can_use_tx_sgl(ring, skb, space))
2271 return hns3_handle_tx_sgl(ring, skb);
2272
2273 if (hns3_can_use_tx_bounce(ring, skb, space))
2274 return hns3_handle_tx_bounce(ring, skb);
2275
2276 out:
2277 return hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
2278 }
2279
hns3_handle_skb_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_cb * desc_cb,int next_to_use_head)2280 static int hns3_handle_skb_desc(struct hns3_enet_ring *ring,
2281 struct sk_buff *skb,
2282 struct hns3_desc_cb *desc_cb,
2283 int next_to_use_head)
2284 {
2285 int ret;
2286
2287 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use],
2288 desc_cb);
2289 if (unlikely(ret < 0))
2290 goto fill_err;
2291
2292 /* 'ret < 0' means filling error, 'ret == 0' means skb->len is
2293 * zero, which is unlikely, and 'ret > 0' means how many tx desc
2294 * need to be notified to the hw.
2295 */
2296 ret = hns3_handle_desc_filling(ring, skb);
2297 if (likely(ret > 0))
2298 return ret;
2299
2300 fill_err:
2301 hns3_clear_desc(ring, next_to_use_head);
2302 return ret;
2303 }
2304
hns3_nic_net_xmit(struct sk_buff * skb,struct net_device * netdev)2305 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
2306 {
2307 struct hns3_nic_priv *priv = netdev_priv(netdev);
2308 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
2309 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2310 struct netdev_queue *dev_queue;
2311 int pre_ntu, ret;
2312 bool doorbell;
2313
2314 /* Hardware can only handle short frames above 32 bytes */
2315 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) {
2316 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
2317
2318 hns3_ring_stats_update(ring, sw_err_cnt);
2319
2320 return NETDEV_TX_OK;
2321 }
2322
2323 /* Prefetch the data used later */
2324 prefetch(skb->data);
2325
2326 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb);
2327 if (unlikely(ret <= 0)) {
2328 if (ret == -EBUSY) {
2329 hns3_tx_doorbell(ring, 0, true);
2330 return NETDEV_TX_BUSY;
2331 }
2332
2333 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
2334 goto out_err_tx_ok;
2335 }
2336
2337 ret = hns3_handle_skb_desc(ring, skb, desc_cb, ring->next_to_use);
2338 if (unlikely(ret <= 0))
2339 goto out_err_tx_ok;
2340
2341 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
2342 (ring->desc_num - 1);
2343
2344 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
2345 hns3_tsyn(netdev, skb, &ring->desc[pre_ntu]);
2346
2347 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
2348 cpu_to_le16(BIT(HNS3_TXD_FE_B));
2349 trace_hns3_tx_desc(ring, pre_ntu);
2350
2351 skb_tx_timestamp(skb);
2352
2353 /* Complete translate all packets */
2354 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
2355 doorbell = __netdev_tx_sent_queue(dev_queue, desc_cb->send_bytes,
2356 netdev_xmit_more());
2357 hns3_tx_doorbell(ring, ret, doorbell);
2358
2359 return NETDEV_TX_OK;
2360
2361 out_err_tx_ok:
2362 dev_kfree_skb_any(skb);
2363 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
2364 return NETDEV_TX_OK;
2365 }
2366
hns3_nic_net_set_mac_address(struct net_device * netdev,void * p)2367 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
2368 {
2369 char format_mac_addr_perm[HNAE3_FORMAT_MAC_ADDR_LEN];
2370 char format_mac_addr_sa[HNAE3_FORMAT_MAC_ADDR_LEN];
2371 struct hnae3_handle *h = hns3_get_handle(netdev);
2372 struct sockaddr *mac_addr = p;
2373 int ret;
2374
2375 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
2376 return -EADDRNOTAVAIL;
2377
2378 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
2379 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data);
2380 netdev_info(netdev, "already using mac address %s\n",
2381 format_mac_addr_sa);
2382 return 0;
2383 }
2384
2385 /* For VF device, if there is a perm_addr, then the user will not
2386 * be allowed to change the address.
2387 */
2388 if (!hns3_is_phys_func(h->pdev) &&
2389 !is_zero_ether_addr(netdev->perm_addr)) {
2390 hnae3_format_mac_addr(format_mac_addr_perm, netdev->perm_addr);
2391 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data);
2392 netdev_err(netdev, "has permanent MAC %s, user MAC %s not allow\n",
2393 format_mac_addr_perm, format_mac_addr_sa);
2394 return -EPERM;
2395 }
2396
2397 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
2398 if (ret) {
2399 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
2400 return ret;
2401 }
2402
2403 eth_hw_addr_set(netdev, mac_addr->sa_data);
2404
2405 return 0;
2406 }
2407
hns3_nic_do_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)2408 static int hns3_nic_do_ioctl(struct net_device *netdev,
2409 struct ifreq *ifr, int cmd)
2410 {
2411 struct hnae3_handle *h = hns3_get_handle(netdev);
2412
2413 if (!netif_running(netdev))
2414 return -EINVAL;
2415
2416 if (!h->ae_algo->ops->do_ioctl)
2417 return -EOPNOTSUPP;
2418
2419 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
2420 }
2421
hns3_nic_set_features(struct net_device * netdev,netdev_features_t features)2422 static int hns3_nic_set_features(struct net_device *netdev,
2423 netdev_features_t features)
2424 {
2425 netdev_features_t changed = netdev->features ^ features;
2426 struct hns3_nic_priv *priv = netdev_priv(netdev);
2427 struct hnae3_handle *h = priv->ae_handle;
2428 bool enable;
2429 int ret;
2430
2431 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
2432 enable = !!(features & NETIF_F_GRO_HW);
2433 ret = h->ae_algo->ops->set_gro_en(h, enable);
2434 if (ret)
2435 return ret;
2436 }
2437
2438 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
2439 h->ae_algo->ops->enable_hw_strip_rxvtag) {
2440 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
2441 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
2442 if (ret)
2443 return ret;
2444 }
2445
2446 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
2447 enable = !!(features & NETIF_F_NTUPLE);
2448 h->ae_algo->ops->enable_fd(h, enable);
2449 }
2450
2451 if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) &&
2452 h->ae_algo->ops->cls_flower_active(h)) {
2453 netdev_err(netdev,
2454 "there are offloaded TC filters active, cannot disable HW TC offload");
2455 return -EINVAL;
2456 }
2457
2458 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
2459 h->ae_algo->ops->enable_vlan_filter) {
2460 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
2461 ret = h->ae_algo->ops->enable_vlan_filter(h, enable);
2462 if (ret)
2463 return ret;
2464 }
2465
2466 netdev->features = features;
2467 return 0;
2468 }
2469
hns3_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)2470 static netdev_features_t hns3_features_check(struct sk_buff *skb,
2471 struct net_device *dev,
2472 netdev_features_t features)
2473 {
2474 #define HNS3_MAX_HDR_LEN 480U
2475 #define HNS3_MAX_L4_HDR_LEN 60U
2476
2477 size_t len;
2478
2479 if (skb->ip_summed != CHECKSUM_PARTIAL)
2480 return features;
2481
2482 if (skb->encapsulation)
2483 len = skb_inner_transport_header(skb) - skb->data;
2484 else
2485 len = skb_transport_header(skb) - skb->data;
2486
2487 /* Assume L4 is 60 byte as TCP is the only protocol with a
2488 * a flexible value, and it's max len is 60 bytes.
2489 */
2490 len += HNS3_MAX_L4_HDR_LEN;
2491
2492 /* Hardware only supports checksum on the skb with a max header
2493 * len of 480 bytes.
2494 */
2495 if (len > HNS3_MAX_HDR_LEN)
2496 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2497
2498 return features;
2499 }
2500
hns3_fetch_stats(struct rtnl_link_stats64 * stats,struct hns3_enet_ring * ring,bool is_tx)2501 static void hns3_fetch_stats(struct rtnl_link_stats64 *stats,
2502 struct hns3_enet_ring *ring, bool is_tx)
2503 {
2504 unsigned int start;
2505
2506 do {
2507 start = u64_stats_fetch_begin(&ring->syncp);
2508 if (is_tx) {
2509 stats->tx_bytes += ring->stats.tx_bytes;
2510 stats->tx_packets += ring->stats.tx_pkts;
2511 stats->tx_dropped += ring->stats.sw_err_cnt;
2512 stats->tx_dropped += ring->stats.tx_vlan_err;
2513 stats->tx_dropped += ring->stats.tx_l4_proto_err;
2514 stats->tx_dropped += ring->stats.tx_l2l3l4_err;
2515 stats->tx_dropped += ring->stats.tx_tso_err;
2516 stats->tx_dropped += ring->stats.over_max_recursion;
2517 stats->tx_dropped += ring->stats.hw_limitation;
2518 stats->tx_dropped += ring->stats.copy_bits_err;
2519 stats->tx_dropped += ring->stats.skb2sgl_err;
2520 stats->tx_dropped += ring->stats.map_sg_err;
2521 stats->tx_errors += ring->stats.sw_err_cnt;
2522 stats->tx_errors += ring->stats.tx_vlan_err;
2523 stats->tx_errors += ring->stats.tx_l4_proto_err;
2524 stats->tx_errors += ring->stats.tx_l2l3l4_err;
2525 stats->tx_errors += ring->stats.tx_tso_err;
2526 stats->tx_errors += ring->stats.over_max_recursion;
2527 stats->tx_errors += ring->stats.hw_limitation;
2528 stats->tx_errors += ring->stats.copy_bits_err;
2529 stats->tx_errors += ring->stats.skb2sgl_err;
2530 stats->tx_errors += ring->stats.map_sg_err;
2531 } else {
2532 stats->rx_bytes += ring->stats.rx_bytes;
2533 stats->rx_packets += ring->stats.rx_pkts;
2534 stats->rx_dropped += ring->stats.l2_err;
2535 stats->rx_errors += ring->stats.l2_err;
2536 stats->rx_errors += ring->stats.l3l4_csum_err;
2537 stats->rx_crc_errors += ring->stats.l2_err;
2538 stats->multicast += ring->stats.rx_multicast;
2539 stats->rx_length_errors += ring->stats.err_pkt_len;
2540 }
2541 } while (u64_stats_fetch_retry(&ring->syncp, start));
2542 }
2543
hns3_nic_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)2544 static void hns3_nic_get_stats64(struct net_device *netdev,
2545 struct rtnl_link_stats64 *stats)
2546 {
2547 struct hns3_nic_priv *priv = netdev_priv(netdev);
2548 int queue_num = priv->ae_handle->kinfo.num_tqps;
2549 struct hnae3_handle *handle = priv->ae_handle;
2550 struct rtnl_link_stats64 ring_total_stats;
2551 struct hns3_enet_ring *ring;
2552 unsigned int idx;
2553
2554 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
2555 return;
2556
2557 handle->ae_algo->ops->update_stats(handle);
2558
2559 memset(&ring_total_stats, 0, sizeof(ring_total_stats));
2560 for (idx = 0; idx < queue_num; idx++) {
2561 /* fetch the tx stats */
2562 ring = &priv->ring[idx];
2563 hns3_fetch_stats(&ring_total_stats, ring, true);
2564
2565 /* fetch the rx stats */
2566 ring = &priv->ring[idx + queue_num];
2567 hns3_fetch_stats(&ring_total_stats, ring, false);
2568 }
2569
2570 stats->tx_bytes = ring_total_stats.tx_bytes;
2571 stats->tx_packets = ring_total_stats.tx_packets;
2572 stats->rx_bytes = ring_total_stats.rx_bytes;
2573 stats->rx_packets = ring_total_stats.rx_packets;
2574
2575 stats->rx_errors = ring_total_stats.rx_errors;
2576 stats->multicast = ring_total_stats.multicast;
2577 stats->rx_length_errors = ring_total_stats.rx_length_errors;
2578 stats->rx_crc_errors = ring_total_stats.rx_crc_errors;
2579 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
2580
2581 stats->tx_errors = ring_total_stats.tx_errors;
2582 stats->rx_dropped = ring_total_stats.rx_dropped;
2583 stats->tx_dropped = ring_total_stats.tx_dropped;
2584 stats->collisions = netdev->stats.collisions;
2585 stats->rx_over_errors = netdev->stats.rx_over_errors;
2586 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
2587 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
2588 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
2589 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
2590 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
2591 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
2592 stats->tx_window_errors = netdev->stats.tx_window_errors;
2593 stats->rx_compressed = netdev->stats.rx_compressed;
2594 stats->tx_compressed = netdev->stats.tx_compressed;
2595 }
2596
hns3_setup_tc(struct net_device * netdev,void * type_data)2597 static int hns3_setup_tc(struct net_device *netdev, void *type_data)
2598 {
2599 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
2600 struct hnae3_knic_private_info *kinfo;
2601 u8 tc = mqprio_qopt->qopt.num_tc;
2602 u16 mode = mqprio_qopt->mode;
2603 u8 hw = mqprio_qopt->qopt.hw;
2604 struct hnae3_handle *h;
2605
2606 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
2607 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
2608 return -EOPNOTSUPP;
2609
2610 if (tc > HNAE3_MAX_TC)
2611 return -EINVAL;
2612
2613 if (!netdev)
2614 return -EINVAL;
2615
2616 h = hns3_get_handle(netdev);
2617 kinfo = &h->kinfo;
2618
2619 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
2620
2621 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
2622 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP;
2623 }
2624
hns3_setup_tc_cls_flower(struct hns3_nic_priv * priv,struct flow_cls_offload * flow)2625 static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv,
2626 struct flow_cls_offload *flow)
2627 {
2628 int tc = tc_classid_to_hwtc(priv->netdev, flow->classid);
2629 struct hnae3_handle *h = hns3_get_handle(priv->netdev);
2630
2631 switch (flow->command) {
2632 case FLOW_CLS_REPLACE:
2633 if (h->ae_algo->ops->add_cls_flower)
2634 return h->ae_algo->ops->add_cls_flower(h, flow, tc);
2635 break;
2636 case FLOW_CLS_DESTROY:
2637 if (h->ae_algo->ops->del_cls_flower)
2638 return h->ae_algo->ops->del_cls_flower(h, flow);
2639 break;
2640 default:
2641 break;
2642 }
2643
2644 return -EOPNOTSUPP;
2645 }
2646
hns3_setup_tc_block_cb(enum tc_setup_type type,void * type_data,void * cb_priv)2647 static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2648 void *cb_priv)
2649 {
2650 struct hns3_nic_priv *priv = cb_priv;
2651
2652 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
2653 return -EOPNOTSUPP;
2654
2655 switch (type) {
2656 case TC_SETUP_CLSFLOWER:
2657 return hns3_setup_tc_cls_flower(priv, type_data);
2658 default:
2659 return -EOPNOTSUPP;
2660 }
2661 }
2662
2663 static LIST_HEAD(hns3_block_cb_list);
2664
hns3_nic_setup_tc(struct net_device * dev,enum tc_setup_type type,void * type_data)2665 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
2666 void *type_data)
2667 {
2668 struct hns3_nic_priv *priv = netdev_priv(dev);
2669 int ret;
2670
2671 switch (type) {
2672 case TC_SETUP_QDISC_MQPRIO:
2673 ret = hns3_setup_tc(dev, type_data);
2674 break;
2675 case TC_SETUP_BLOCK:
2676 ret = flow_block_cb_setup_simple(type_data,
2677 &hns3_block_cb_list,
2678 hns3_setup_tc_block_cb,
2679 priv, priv, true);
2680 break;
2681 default:
2682 return -EOPNOTSUPP;
2683 }
2684
2685 return ret;
2686 }
2687
hns3_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)2688 static int hns3_vlan_rx_add_vid(struct net_device *netdev,
2689 __be16 proto, u16 vid)
2690 {
2691 struct hnae3_handle *h = hns3_get_handle(netdev);
2692 int ret = -EIO;
2693
2694 if (h->ae_algo->ops->set_vlan_filter)
2695 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
2696
2697 return ret;
2698 }
2699
hns3_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)2700 static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
2701 __be16 proto, u16 vid)
2702 {
2703 struct hnae3_handle *h = hns3_get_handle(netdev);
2704 int ret = -EIO;
2705
2706 if (h->ae_algo->ops->set_vlan_filter)
2707 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
2708
2709 return ret;
2710 }
2711
hns3_ndo_set_vf_vlan(struct net_device * netdev,int vf,u16 vlan,u8 qos,__be16 vlan_proto)2712 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
2713 u8 qos, __be16 vlan_proto)
2714 {
2715 struct hnae3_handle *h = hns3_get_handle(netdev);
2716 int ret = -EIO;
2717
2718 netif_dbg(h, drv, netdev,
2719 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
2720 vf, vlan, qos, ntohs(vlan_proto));
2721
2722 if (h->ae_algo->ops->set_vf_vlan_filter)
2723 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
2724 qos, vlan_proto);
2725
2726 return ret;
2727 }
2728
hns3_set_vf_spoofchk(struct net_device * netdev,int vf,bool enable)2729 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
2730 {
2731 struct hnae3_handle *handle = hns3_get_handle(netdev);
2732
2733 if (hns3_nic_resetting(netdev))
2734 return -EBUSY;
2735
2736 if (!handle->ae_algo->ops->set_vf_spoofchk)
2737 return -EOPNOTSUPP;
2738
2739 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
2740 }
2741
hns3_set_vf_trust(struct net_device * netdev,int vf,bool enable)2742 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
2743 {
2744 struct hnae3_handle *handle = hns3_get_handle(netdev);
2745
2746 if (!handle->ae_algo->ops->set_vf_trust)
2747 return -EOPNOTSUPP;
2748
2749 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
2750 }
2751
hns3_nic_change_mtu(struct net_device * netdev,int new_mtu)2752 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
2753 {
2754 struct hnae3_handle *h = hns3_get_handle(netdev);
2755 int ret;
2756
2757 if (hns3_nic_resetting(netdev))
2758 return -EBUSY;
2759
2760 if (!h->ae_algo->ops->set_mtu)
2761 return -EOPNOTSUPP;
2762
2763 netif_dbg(h, drv, netdev,
2764 "change mtu from %u to %d\n", netdev->mtu, new_mtu);
2765
2766 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
2767 if (ret)
2768 netdev_err(netdev, "failed to change MTU in hardware %d\n",
2769 ret);
2770 else
2771 netdev->mtu = new_mtu;
2772
2773 return ret;
2774 }
2775
hns3_get_timeout_queue(struct net_device * ndev)2776 static int hns3_get_timeout_queue(struct net_device *ndev)
2777 {
2778 int i;
2779
2780 /* Find the stopped queue the same way the stack does */
2781 for (i = 0; i < ndev->num_tx_queues; i++) {
2782 struct netdev_queue *q;
2783 unsigned long trans_start;
2784
2785 q = netdev_get_tx_queue(ndev, i);
2786 trans_start = READ_ONCE(q->trans_start);
2787 if (netif_xmit_stopped(q) &&
2788 time_after(jiffies,
2789 (trans_start + ndev->watchdog_timeo))) {
2790 #ifdef CONFIG_BQL
2791 struct dql *dql = &q->dql;
2792
2793 netdev_info(ndev, "DQL info last_cnt: %u, queued: %u, adj_limit: %u, completed: %u\n",
2794 dql->last_obj_cnt, dql->num_queued,
2795 dql->adj_limit, dql->num_completed);
2796 #endif
2797 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
2798 q->state,
2799 jiffies_to_msecs(jiffies - trans_start));
2800 break;
2801 }
2802 }
2803
2804 return i;
2805 }
2806
hns3_dump_queue_stats(struct net_device * ndev,struct hns3_enet_ring * tx_ring,int timeout_queue)2807 static void hns3_dump_queue_stats(struct net_device *ndev,
2808 struct hns3_enet_ring *tx_ring,
2809 int timeout_queue)
2810 {
2811 struct napi_struct *napi = &tx_ring->tqp_vector->napi;
2812 struct hns3_nic_priv *priv = netdev_priv(ndev);
2813
2814 netdev_info(ndev,
2815 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
2816 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
2817 tx_ring->next_to_clean, napi->state);
2818
2819 netdev_info(ndev,
2820 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n",
2821 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
2822 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf);
2823
2824 netdev_info(ndev,
2825 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n",
2826 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more,
2827 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
2828
2829 netdev_info(ndev, "tx_push: %llu, tx_mem_doorbell: %llu\n",
2830 tx_ring->stats.tx_push, tx_ring->stats.tx_mem_doorbell);
2831 }
2832
hns3_dump_queue_reg(struct net_device * ndev,struct hns3_enet_ring * tx_ring)2833 static void hns3_dump_queue_reg(struct net_device *ndev,
2834 struct hns3_enet_ring *tx_ring)
2835 {
2836 netdev_info(ndev,
2837 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
2838 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_NUM_REG),
2839 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_HEAD_REG),
2840 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TAIL_REG),
2841 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_ERR_REG),
2842 readl(tx_ring->tqp_vector->mask_addr));
2843 netdev_info(ndev,
2844 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
2845 hns3_tqp_read_reg(tx_ring, HNS3_RING_EN_REG),
2846 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TC_REG),
2847 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_FBDNUM_REG),
2848 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_OFFSET_REG),
2849 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_EBDNUM_REG),
2850 hns3_tqp_read_reg(tx_ring,
2851 HNS3_RING_TX_RING_EBD_OFFSET_REG));
2852 }
2853
hns3_get_tx_timeo_queue_info(struct net_device * ndev)2854 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
2855 {
2856 struct hns3_nic_priv *priv = netdev_priv(ndev);
2857 struct hnae3_handle *h = hns3_get_handle(ndev);
2858 struct hns3_enet_ring *tx_ring;
2859 int timeout_queue;
2860
2861 timeout_queue = hns3_get_timeout_queue(ndev);
2862 if (timeout_queue >= ndev->num_tx_queues) {
2863 netdev_info(ndev,
2864 "no netdev TX timeout queue found, timeout count: %llu\n",
2865 priv->tx_timeout_count);
2866 return false;
2867 }
2868
2869 priv->tx_timeout_count++;
2870
2871 tx_ring = &priv->ring[timeout_queue];
2872 hns3_dump_queue_stats(ndev, tx_ring, timeout_queue);
2873
2874 /* When mac received many pause frames continuous, it's unable to send
2875 * packets, which may cause tx timeout
2876 */
2877 if (h->ae_algo->ops->get_mac_stats) {
2878 struct hns3_mac_stats mac_stats;
2879
2880 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
2881 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
2882 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
2883 }
2884
2885 hns3_dump_queue_reg(ndev, tx_ring);
2886
2887 return true;
2888 }
2889
hns3_nic_net_timeout(struct net_device * ndev,unsigned int txqueue)2890 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue)
2891 {
2892 struct hns3_nic_priv *priv = netdev_priv(ndev);
2893 struct hnae3_handle *h = priv->ae_handle;
2894
2895 if (!hns3_get_tx_timeo_queue_info(ndev))
2896 return;
2897
2898 /* request the reset, and let the hclge to determine
2899 * which reset level should be done
2900 */
2901 if (h->ae_algo->ops->reset_event)
2902 h->ae_algo->ops->reset_event(h->pdev, h);
2903 }
2904
2905 #ifdef CONFIG_RFS_ACCEL
hns3_rx_flow_steer(struct net_device * dev,const struct sk_buff * skb,u16 rxq_index,u32 flow_id)2906 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
2907 u16 rxq_index, u32 flow_id)
2908 {
2909 struct hnae3_handle *h = hns3_get_handle(dev);
2910 struct flow_keys fkeys;
2911
2912 if (!h->ae_algo->ops->add_arfs_entry)
2913 return -EOPNOTSUPP;
2914
2915 if (skb->encapsulation)
2916 return -EPROTONOSUPPORT;
2917
2918 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
2919 return -EPROTONOSUPPORT;
2920
2921 if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
2922 fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
2923 (fkeys.basic.ip_proto != IPPROTO_TCP &&
2924 fkeys.basic.ip_proto != IPPROTO_UDP))
2925 return -EPROTONOSUPPORT;
2926
2927 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
2928 }
2929 #endif
2930
hns3_nic_get_vf_config(struct net_device * ndev,int vf,struct ifla_vf_info * ivf)2931 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
2932 struct ifla_vf_info *ivf)
2933 {
2934 struct hnae3_handle *h = hns3_get_handle(ndev);
2935
2936 if (!h->ae_algo->ops->get_vf_config)
2937 return -EOPNOTSUPP;
2938
2939 return h->ae_algo->ops->get_vf_config(h, vf, ivf);
2940 }
2941
hns3_nic_set_vf_link_state(struct net_device * ndev,int vf,int link_state)2942 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
2943 int link_state)
2944 {
2945 struct hnae3_handle *h = hns3_get_handle(ndev);
2946
2947 if (!h->ae_algo->ops->set_vf_link_state)
2948 return -EOPNOTSUPP;
2949
2950 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
2951 }
2952
hns3_nic_set_vf_rate(struct net_device * ndev,int vf,int min_tx_rate,int max_tx_rate)2953 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
2954 int min_tx_rate, int max_tx_rate)
2955 {
2956 struct hnae3_handle *h = hns3_get_handle(ndev);
2957
2958 if (!h->ae_algo->ops->set_vf_rate)
2959 return -EOPNOTSUPP;
2960
2961 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
2962 false);
2963 }
2964
hns3_nic_set_vf_mac(struct net_device * netdev,int vf_id,u8 * mac)2965 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
2966 {
2967 struct hnae3_handle *h = hns3_get_handle(netdev);
2968 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
2969
2970 if (!h->ae_algo->ops->set_vf_mac)
2971 return -EOPNOTSUPP;
2972
2973 if (is_multicast_ether_addr(mac)) {
2974 hnae3_format_mac_addr(format_mac_addr, mac);
2975 netdev_err(netdev,
2976 "Invalid MAC:%s specified. Could not set MAC\n",
2977 format_mac_addr);
2978 return -EINVAL;
2979 }
2980
2981 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
2982 }
2983
2984 #define HNS3_INVALID_DSCP 0xff
2985 #define HNS3_DSCP_SHIFT 2
2986
hns3_get_skb_dscp(struct sk_buff * skb)2987 static u8 hns3_get_skb_dscp(struct sk_buff *skb)
2988 {
2989 __be16 protocol = skb->protocol;
2990 u8 dscp = HNS3_INVALID_DSCP;
2991
2992 if (protocol == htons(ETH_P_8021Q))
2993 protocol = vlan_get_protocol(skb);
2994
2995 if (protocol == htons(ETH_P_IP))
2996 dscp = ipv4_get_dsfield(ip_hdr(skb)) >> HNS3_DSCP_SHIFT;
2997 else if (protocol == htons(ETH_P_IPV6))
2998 dscp = ipv6_get_dsfield(ipv6_hdr(skb)) >> HNS3_DSCP_SHIFT;
2999
3000 return dscp;
3001 }
3002
hns3_nic_select_queue(struct net_device * netdev,struct sk_buff * skb,struct net_device * sb_dev)3003 static u16 hns3_nic_select_queue(struct net_device *netdev,
3004 struct sk_buff *skb,
3005 struct net_device *sb_dev)
3006 {
3007 struct hnae3_handle *h = hns3_get_handle(netdev);
3008 u8 dscp;
3009
3010 if (h->kinfo.tc_map_mode != HNAE3_TC_MAP_MODE_DSCP ||
3011 !h->ae_algo->ops->get_dscp_prio)
3012 goto out;
3013
3014 dscp = hns3_get_skb_dscp(skb);
3015 if (unlikely(dscp >= HNAE3_MAX_DSCP))
3016 goto out;
3017
3018 skb->priority = h->kinfo.dscp_prio[dscp];
3019 if (skb->priority == HNAE3_PRIO_ID_INVALID)
3020 skb->priority = 0;
3021
3022 out:
3023 return netdev_pick_tx(netdev, skb, sb_dev);
3024 }
3025
3026 static const struct net_device_ops hns3_nic_netdev_ops = {
3027 .ndo_open = hns3_nic_net_open,
3028 .ndo_stop = hns3_nic_net_stop,
3029 .ndo_start_xmit = hns3_nic_net_xmit,
3030 .ndo_tx_timeout = hns3_nic_net_timeout,
3031 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
3032 .ndo_eth_ioctl = hns3_nic_do_ioctl,
3033 .ndo_change_mtu = hns3_nic_change_mtu,
3034 .ndo_set_features = hns3_nic_set_features,
3035 .ndo_features_check = hns3_features_check,
3036 .ndo_get_stats64 = hns3_nic_get_stats64,
3037 .ndo_setup_tc = hns3_nic_setup_tc,
3038 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
3039 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
3040 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
3041 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
3042 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk,
3043 .ndo_set_vf_trust = hns3_set_vf_trust,
3044 #ifdef CONFIG_RFS_ACCEL
3045 .ndo_rx_flow_steer = hns3_rx_flow_steer,
3046 #endif
3047 .ndo_get_vf_config = hns3_nic_get_vf_config,
3048 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state,
3049 .ndo_set_vf_rate = hns3_nic_set_vf_rate,
3050 .ndo_set_vf_mac = hns3_nic_set_vf_mac,
3051 .ndo_select_queue = hns3_nic_select_queue,
3052 };
3053
hns3_is_phys_func(struct pci_dev * pdev)3054 bool hns3_is_phys_func(struct pci_dev *pdev)
3055 {
3056 u32 dev_id = pdev->device;
3057
3058 switch (dev_id) {
3059 case HNAE3_DEV_ID_GE:
3060 case HNAE3_DEV_ID_25GE:
3061 case HNAE3_DEV_ID_25GE_RDMA:
3062 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
3063 case HNAE3_DEV_ID_50GE_RDMA:
3064 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
3065 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
3066 case HNAE3_DEV_ID_200G_RDMA:
3067 return true;
3068 case HNAE3_DEV_ID_VF:
3069 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF:
3070 return false;
3071 default:
3072 dev_warn(&pdev->dev, "un-recognized pci device-id %u",
3073 dev_id);
3074 }
3075
3076 return false;
3077 }
3078
hns3_disable_sriov(struct pci_dev * pdev)3079 static void hns3_disable_sriov(struct pci_dev *pdev)
3080 {
3081 /* If our VFs are assigned we cannot shut down SR-IOV
3082 * without causing issues, so just leave the hardware
3083 * available but disabled
3084 */
3085 if (pci_vfs_assigned(pdev)) {
3086 dev_warn(&pdev->dev,
3087 "disabling driver while VFs are assigned\n");
3088 return;
3089 }
3090
3091 pci_disable_sriov(pdev);
3092 }
3093
3094 /* hns3_probe - Device initialization routine
3095 * @pdev: PCI device information struct
3096 * @ent: entry in hns3_pci_tbl
3097 *
3098 * hns3_probe initializes a PF identified by a pci_dev structure.
3099 * The OS initialization, configuring of the PF private structure,
3100 * and a hardware reset occur.
3101 *
3102 * Returns 0 on success, negative on failure
3103 */
hns3_probe(struct pci_dev * pdev,const struct pci_device_id * ent)3104 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3105 {
3106 struct hnae3_ae_dev *ae_dev;
3107 int ret;
3108
3109 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
3110 if (!ae_dev)
3111 return -ENOMEM;
3112
3113 ae_dev->pdev = pdev;
3114 ae_dev->flag = ent->driver_data;
3115 pci_set_drvdata(pdev, ae_dev);
3116
3117 ret = hnae3_register_ae_dev(ae_dev);
3118 if (ret)
3119 pci_set_drvdata(pdev, NULL);
3120
3121 return ret;
3122 }
3123
3124 /**
3125 * hns3_clean_vf_config
3126 * @pdev: pointer to a pci_dev structure
3127 * @num_vfs: number of VFs allocated
3128 *
3129 * Clean residual vf config after disable sriov
3130 **/
hns3_clean_vf_config(struct pci_dev * pdev,int num_vfs)3131 static void hns3_clean_vf_config(struct pci_dev *pdev, int num_vfs)
3132 {
3133 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3134
3135 if (ae_dev->ops->clean_vf_config)
3136 ae_dev->ops->clean_vf_config(ae_dev, num_vfs);
3137 }
3138
3139 /* hns3_remove - Device removal routine
3140 * @pdev: PCI device information struct
3141 */
hns3_remove(struct pci_dev * pdev)3142 static void hns3_remove(struct pci_dev *pdev)
3143 {
3144 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3145
3146 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
3147 hns3_disable_sriov(pdev);
3148
3149 hnae3_unregister_ae_dev(ae_dev);
3150 pci_set_drvdata(pdev, NULL);
3151 }
3152
3153 /**
3154 * hns3_pci_sriov_configure
3155 * @pdev: pointer to a pci_dev structure
3156 * @num_vfs: number of VFs to allocate
3157 *
3158 * Enable or change the number of VFs. Called when the user updates the number
3159 * of VFs in sysfs.
3160 **/
hns3_pci_sriov_configure(struct pci_dev * pdev,int num_vfs)3161 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
3162 {
3163 int ret;
3164
3165 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
3166 dev_warn(&pdev->dev, "Can not config SRIOV\n");
3167 return -EINVAL;
3168 }
3169
3170 if (num_vfs) {
3171 ret = pci_enable_sriov(pdev, num_vfs);
3172 if (ret)
3173 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
3174 else
3175 return num_vfs;
3176 } else if (!pci_vfs_assigned(pdev)) {
3177 int num_vfs_pre = pci_num_vf(pdev);
3178
3179 pci_disable_sriov(pdev);
3180 hns3_clean_vf_config(pdev, num_vfs_pre);
3181 } else {
3182 dev_warn(&pdev->dev,
3183 "Unable to free VFs because some are assigned to VMs.\n");
3184 }
3185
3186 return 0;
3187 }
3188
hns3_shutdown(struct pci_dev * pdev)3189 static void hns3_shutdown(struct pci_dev *pdev)
3190 {
3191 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3192
3193 hnae3_unregister_ae_dev(ae_dev);
3194 pci_set_drvdata(pdev, NULL);
3195
3196 if (system_state == SYSTEM_POWER_OFF)
3197 pci_set_power_state(pdev, PCI_D3hot);
3198 }
3199
hns3_suspend(struct device * dev)3200 static int __maybe_unused hns3_suspend(struct device *dev)
3201 {
3202 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3203
3204 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
3205 dev_info(dev, "Begin to suspend.\n");
3206 if (ae_dev->ops && ae_dev->ops->reset_prepare)
3207 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET);
3208 }
3209
3210 return 0;
3211 }
3212
hns3_resume(struct device * dev)3213 static int __maybe_unused hns3_resume(struct device *dev)
3214 {
3215 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3216
3217 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
3218 dev_info(dev, "Begin to resume.\n");
3219 if (ae_dev->ops && ae_dev->ops->reset_done)
3220 ae_dev->ops->reset_done(ae_dev);
3221 }
3222
3223 return 0;
3224 }
3225
hns3_error_detected(struct pci_dev * pdev,pci_channel_state_t state)3226 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
3227 pci_channel_state_t state)
3228 {
3229 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3230 pci_ers_result_t ret;
3231
3232 dev_info(&pdev->dev, "PCI error detected, state(=%u)!!\n", state);
3233
3234 if (state == pci_channel_io_perm_failure)
3235 return PCI_ERS_RESULT_DISCONNECT;
3236
3237 if (!ae_dev || !ae_dev->ops) {
3238 dev_err(&pdev->dev,
3239 "Can't recover - error happened before device initialized\n");
3240 return PCI_ERS_RESULT_NONE;
3241 }
3242
3243 if (ae_dev->ops->handle_hw_ras_error)
3244 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
3245 else
3246 return PCI_ERS_RESULT_NONE;
3247
3248 return ret;
3249 }
3250
hns3_slot_reset(struct pci_dev * pdev)3251 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
3252 {
3253 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3254 const struct hnae3_ae_ops *ops;
3255 enum hnae3_reset_type reset_type;
3256 struct device *dev = &pdev->dev;
3257
3258 if (!ae_dev || !ae_dev->ops)
3259 return PCI_ERS_RESULT_NONE;
3260
3261 ops = ae_dev->ops;
3262 /* request the reset */
3263 if (ops->reset_event && ops->get_reset_level &&
3264 ops->set_default_reset_request) {
3265 if (ae_dev->hw_err_reset_req) {
3266 reset_type = ops->get_reset_level(ae_dev,
3267 &ae_dev->hw_err_reset_req);
3268 ops->set_default_reset_request(ae_dev, reset_type);
3269 dev_info(dev, "requesting reset due to PCI error\n");
3270 ops->reset_event(pdev, NULL);
3271 }
3272
3273 return PCI_ERS_RESULT_RECOVERED;
3274 }
3275
3276 return PCI_ERS_RESULT_DISCONNECT;
3277 }
3278
hns3_reset_prepare(struct pci_dev * pdev)3279 static void hns3_reset_prepare(struct pci_dev *pdev)
3280 {
3281 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3282
3283 dev_info(&pdev->dev, "FLR prepare\n");
3284 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare)
3285 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET);
3286 }
3287
hns3_reset_done(struct pci_dev * pdev)3288 static void hns3_reset_done(struct pci_dev *pdev)
3289 {
3290 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3291
3292 dev_info(&pdev->dev, "FLR done\n");
3293 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done)
3294 ae_dev->ops->reset_done(ae_dev);
3295 }
3296
3297 static const struct pci_error_handlers hns3_err_handler = {
3298 .error_detected = hns3_error_detected,
3299 .slot_reset = hns3_slot_reset,
3300 .reset_prepare = hns3_reset_prepare,
3301 .reset_done = hns3_reset_done,
3302 };
3303
3304 static SIMPLE_DEV_PM_OPS(hns3_pm_ops, hns3_suspend, hns3_resume);
3305
3306 static struct pci_driver hns3_driver = {
3307 .name = hns3_driver_name,
3308 .id_table = hns3_pci_tbl,
3309 .probe = hns3_probe,
3310 .remove = hns3_remove,
3311 .shutdown = hns3_shutdown,
3312 .driver.pm = &hns3_pm_ops,
3313 .sriov_configure = hns3_pci_sriov_configure,
3314 .err_handler = &hns3_err_handler,
3315 };
3316
3317 /* set default feature to hns3 */
hns3_set_default_feature(struct net_device * netdev)3318 static void hns3_set_default_feature(struct net_device *netdev)
3319 {
3320 struct hnae3_handle *h = hns3_get_handle(netdev);
3321 struct pci_dev *pdev = h->pdev;
3322 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3323
3324 netdev->priv_flags |= IFF_UNICAST_FLT;
3325
3326 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
3327 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
3328 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
3329 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
3330 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
3331 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST;
3332
3333 if (hnae3_ae_dev_gro_supported(ae_dev))
3334 netdev->features |= NETIF_F_GRO_HW;
3335
3336 if (hnae3_ae_dev_fd_supported(ae_dev))
3337 netdev->features |= NETIF_F_NTUPLE;
3338
3339 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps))
3340 netdev->features |= NETIF_F_GSO_UDP_L4;
3341
3342 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
3343 netdev->features |= NETIF_F_HW_CSUM;
3344 else
3345 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
3346
3347 if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps))
3348 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
3349
3350 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps))
3351 netdev->features |= NETIF_F_HW_TC;
3352
3353 netdev->hw_features |= netdev->features;
3354 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
3355 netdev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
3356
3357 netdev->vlan_features |= netdev->features &
3358 ~(NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX |
3359 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_GRO_HW | NETIF_F_NTUPLE |
3360 NETIF_F_HW_TC);
3361
3362 netdev->hw_enc_features |= netdev->vlan_features | NETIF_F_TSO_MANGLEID;
3363
3364 /* The device_version V3 hardware can't offload the checksum for IP in
3365 * GRE packets, but can do it for NvGRE. So default to disable the
3366 * checksum and GSO offload for GRE.
3367 */
3368 if (ae_dev->dev_version > HNAE3_DEVICE_VERSION_V2) {
3369 netdev->features &= ~NETIF_F_GSO_GRE;
3370 netdev->features &= ~NETIF_F_GSO_GRE_CSUM;
3371 }
3372 }
3373
hns3_alloc_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3374 static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
3375 struct hns3_desc_cb *cb)
3376 {
3377 unsigned int order = hns3_page_order(ring);
3378 struct page *p;
3379
3380 if (ring->page_pool) {
3381 p = page_pool_dev_alloc_frag(ring->page_pool,
3382 &cb->page_offset,
3383 hns3_buf_size(ring));
3384 if (unlikely(!p))
3385 return -ENOMEM;
3386
3387 cb->priv = p;
3388 cb->buf = page_address(p);
3389 cb->dma = page_pool_get_dma_addr(p);
3390 cb->type = DESC_TYPE_PP_FRAG;
3391 cb->reuse_flag = 0;
3392 return 0;
3393 }
3394
3395 p = dev_alloc_pages(order);
3396 if (!p)
3397 return -ENOMEM;
3398
3399 cb->priv = p;
3400 cb->page_offset = 0;
3401 cb->reuse_flag = 0;
3402 cb->buf = page_address(p);
3403 cb->length = hns3_page_size(ring);
3404 cb->type = DESC_TYPE_PAGE;
3405 page_ref_add(p, USHRT_MAX - 1);
3406 cb->pagecnt_bias = USHRT_MAX;
3407
3408 return 0;
3409 }
3410
hns3_free_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb,int budget)3411 static void hns3_free_buffer(struct hns3_enet_ring *ring,
3412 struct hns3_desc_cb *cb, int budget)
3413 {
3414 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_HEAD |
3415 DESC_TYPE_BOUNCE_ALL | DESC_TYPE_SGL_SKB))
3416 napi_consume_skb(cb->priv, budget);
3417 else if (!HNAE3_IS_TX_RING(ring)) {
3418 if (cb->type & DESC_TYPE_PAGE && cb->pagecnt_bias)
3419 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias);
3420 else if (cb->type & DESC_TYPE_PP_FRAG)
3421 page_pool_put_full_page(ring->page_pool, cb->priv,
3422 false);
3423 }
3424 memset(cb, 0, sizeof(*cb));
3425 }
3426
hns3_map_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3427 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
3428 {
3429 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
3430 cb->length, ring_to_dma_dir(ring));
3431
3432 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
3433 return -EIO;
3434
3435 return 0;
3436 }
3437
hns3_unmap_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3438 static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
3439 struct hns3_desc_cb *cb)
3440 {
3441 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
3442 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
3443 ring_to_dma_dir(ring));
3444 else if ((cb->type & DESC_TYPE_PAGE) && cb->length)
3445 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
3446 ring_to_dma_dir(ring));
3447 else if (cb->type & (DESC_TYPE_BOUNCE_ALL | DESC_TYPE_BOUNCE_HEAD |
3448 DESC_TYPE_SGL_SKB))
3449 hns3_tx_spare_reclaim_cb(ring, cb);
3450 }
3451
hns3_buffer_detach(struct hns3_enet_ring * ring,int i)3452 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
3453 {
3454 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3455 ring->desc[i].addr = 0;
3456 ring->desc_cb[i].refill = 0;
3457 }
3458
hns3_free_buffer_detach(struct hns3_enet_ring * ring,int i,int budget)3459 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i,
3460 int budget)
3461 {
3462 struct hns3_desc_cb *cb = &ring->desc_cb[i];
3463
3464 if (!ring->desc_cb[i].dma)
3465 return;
3466
3467 hns3_buffer_detach(ring, i);
3468 hns3_free_buffer(ring, cb, budget);
3469 }
3470
hns3_free_buffers(struct hns3_enet_ring * ring)3471 static void hns3_free_buffers(struct hns3_enet_ring *ring)
3472 {
3473 int i;
3474
3475 for (i = 0; i < ring->desc_num; i++)
3476 hns3_free_buffer_detach(ring, i, 0);
3477 }
3478
3479 /* free desc along with its attached buffer */
hns3_free_desc(struct hns3_enet_ring * ring)3480 static void hns3_free_desc(struct hns3_enet_ring *ring)
3481 {
3482 int size = ring->desc_num * sizeof(ring->desc[0]);
3483
3484 hns3_free_buffers(ring);
3485
3486 if (ring->desc) {
3487 dma_free_coherent(ring_to_dev(ring), size,
3488 ring->desc, ring->desc_dma_addr);
3489 ring->desc = NULL;
3490 }
3491 }
3492
hns3_alloc_desc(struct hns3_enet_ring * ring)3493 static int hns3_alloc_desc(struct hns3_enet_ring *ring)
3494 {
3495 int size = ring->desc_num * sizeof(ring->desc[0]);
3496
3497 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
3498 &ring->desc_dma_addr, GFP_KERNEL);
3499 if (!ring->desc)
3500 return -ENOMEM;
3501
3502 return 0;
3503 }
3504
hns3_alloc_and_map_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3505 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring,
3506 struct hns3_desc_cb *cb)
3507 {
3508 int ret;
3509
3510 ret = hns3_alloc_buffer(ring, cb);
3511 if (ret || ring->page_pool)
3512 goto out;
3513
3514 ret = hns3_map_buffer(ring, cb);
3515 if (ret)
3516 goto out_with_buf;
3517
3518 return 0;
3519
3520 out_with_buf:
3521 hns3_free_buffer(ring, cb, 0);
3522 out:
3523 return ret;
3524 }
3525
hns3_alloc_and_attach_buffer(struct hns3_enet_ring * ring,int i)3526 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i)
3527 {
3528 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]);
3529
3530 if (ret)
3531 return ret;
3532
3533 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3534 ring->desc_cb[i].page_offset);
3535 ring->desc_cb[i].refill = 1;
3536
3537 return 0;
3538 }
3539
3540 /* Allocate memory for raw pkg, and map with dma */
hns3_alloc_ring_buffers(struct hns3_enet_ring * ring)3541 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
3542 {
3543 int i, j, ret;
3544
3545 for (i = 0; i < ring->desc_num; i++) {
3546 ret = hns3_alloc_and_attach_buffer(ring, i);
3547 if (ret)
3548 goto out_buffer_fail;
3549
3550 if (!(i % HNS3_RESCHED_BD_NUM))
3551 cond_resched();
3552 }
3553
3554 return 0;
3555
3556 out_buffer_fail:
3557 for (j = i - 1; j >= 0; j--)
3558 hns3_free_buffer_detach(ring, j, 0);
3559 return ret;
3560 }
3561
3562 /* detach a in-used buffer and replace with a reserved one */
hns3_replace_buffer(struct hns3_enet_ring * ring,int i,struct hns3_desc_cb * res_cb)3563 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
3564 struct hns3_desc_cb *res_cb)
3565 {
3566 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3567 ring->desc_cb[i] = *res_cb;
3568 ring->desc_cb[i].refill = 1;
3569 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3570 ring->desc_cb[i].page_offset);
3571 ring->desc[i].rx.bd_base_info = 0;
3572 }
3573
hns3_reuse_buffer(struct hns3_enet_ring * ring,int i)3574 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
3575 {
3576 ring->desc_cb[i].reuse_flag = 0;
3577 ring->desc_cb[i].refill = 1;
3578 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3579 ring->desc_cb[i].page_offset);
3580 ring->desc[i].rx.bd_base_info = 0;
3581
3582 dma_sync_single_for_device(ring_to_dev(ring),
3583 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset,
3584 hns3_buf_size(ring),
3585 DMA_FROM_DEVICE);
3586 }
3587
hns3_nic_reclaim_desc(struct hns3_enet_ring * ring,int * bytes,int * pkts,int budget)3588 static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring,
3589 int *bytes, int *pkts, int budget)
3590 {
3591 /* This smp_load_acquire() pairs with smp_store_release() in
3592 * hns3_tx_doorbell().
3593 */
3594 int ltu = smp_load_acquire(&ring->last_to_use);
3595 int ntc = ring->next_to_clean;
3596 struct hns3_desc_cb *desc_cb;
3597 bool reclaimed = false;
3598 struct hns3_desc *desc;
3599
3600 while (ltu != ntc) {
3601 desc = &ring->desc[ntc];
3602
3603 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) &
3604 BIT(HNS3_TXD_VLD_B))
3605 break;
3606
3607 desc_cb = &ring->desc_cb[ntc];
3608
3609 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_ALL |
3610 DESC_TYPE_BOUNCE_HEAD |
3611 DESC_TYPE_SGL_SKB)) {
3612 (*pkts)++;
3613 (*bytes) += desc_cb->send_bytes;
3614 }
3615
3616 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
3617 hns3_free_buffer_detach(ring, ntc, budget);
3618
3619 if (++ntc == ring->desc_num)
3620 ntc = 0;
3621
3622 /* Issue prefetch for next Tx descriptor */
3623 prefetch(&ring->desc_cb[ntc]);
3624 reclaimed = true;
3625 }
3626
3627 if (unlikely(!reclaimed))
3628 return false;
3629
3630 /* This smp_store_release() pairs with smp_load_acquire() in
3631 * ring_space called by hns3_nic_net_xmit.
3632 */
3633 smp_store_release(&ring->next_to_clean, ntc);
3634
3635 hns3_tx_spare_update(ring);
3636
3637 return true;
3638 }
3639
hns3_clean_tx_ring(struct hns3_enet_ring * ring,int budget)3640 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget)
3641 {
3642 struct net_device *netdev = ring_to_netdev(ring);
3643 struct hns3_nic_priv *priv = netdev_priv(netdev);
3644 struct netdev_queue *dev_queue;
3645 int bytes, pkts;
3646
3647 bytes = 0;
3648 pkts = 0;
3649
3650 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget)))
3651 return;
3652
3653 ring->tqp_vector->tx_group.total_bytes += bytes;
3654 ring->tqp_vector->tx_group.total_packets += pkts;
3655
3656 u64_stats_update_begin(&ring->syncp);
3657 ring->stats.tx_bytes += bytes;
3658 ring->stats.tx_pkts += pkts;
3659 u64_stats_update_end(&ring->syncp);
3660
3661 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
3662 netdev_tx_completed_queue(dev_queue, pkts, bytes);
3663
3664 if (unlikely(netif_carrier_ok(netdev) &&
3665 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
3666 /* Make sure that anybody stopping the queue after this
3667 * sees the new next_to_clean.
3668 */
3669 smp_mb();
3670 if (netif_tx_queue_stopped(dev_queue) &&
3671 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
3672 netif_tx_wake_queue(dev_queue);
3673 ring->stats.restart_queue++;
3674 }
3675 }
3676 }
3677
hns3_desc_unused(struct hns3_enet_ring * ring)3678 static int hns3_desc_unused(struct hns3_enet_ring *ring)
3679 {
3680 int ntc = ring->next_to_clean;
3681 int ntu = ring->next_to_use;
3682
3683 if (unlikely(ntc == ntu && !ring->desc_cb[ntc].refill))
3684 return ring->desc_num;
3685
3686 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
3687 }
3688
3689 /* Return true if there is any allocation failure */
hns3_nic_alloc_rx_buffers(struct hns3_enet_ring * ring,int cleand_count)3690 static bool hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
3691 int cleand_count)
3692 {
3693 struct hns3_desc_cb *desc_cb;
3694 struct hns3_desc_cb res_cbs;
3695 int i, ret;
3696
3697 for (i = 0; i < cleand_count; i++) {
3698 desc_cb = &ring->desc_cb[ring->next_to_use];
3699 if (desc_cb->reuse_flag) {
3700 hns3_ring_stats_update(ring, reuse_pg_cnt);
3701
3702 hns3_reuse_buffer(ring, ring->next_to_use);
3703 } else {
3704 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
3705 if (ret) {
3706 hns3_ring_stats_update(ring, sw_err_cnt);
3707
3708 hns3_rl_err(ring_to_netdev(ring),
3709 "alloc rx buffer failed: %d\n",
3710 ret);
3711
3712 writel(i, ring->tqp->io_base +
3713 HNS3_RING_RX_RING_HEAD_REG);
3714 return true;
3715 }
3716 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
3717
3718 hns3_ring_stats_update(ring, non_reuse_pg);
3719 }
3720
3721 ring_ptr_move_fw(ring, next_to_use);
3722 }
3723
3724 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
3725 return false;
3726 }
3727
hns3_can_reuse_page(struct hns3_desc_cb * cb)3728 static bool hns3_can_reuse_page(struct hns3_desc_cb *cb)
3729 {
3730 return page_count(cb->priv) == cb->pagecnt_bias;
3731 }
3732
hns3_handle_rx_copybreak(struct sk_buff * skb,int i,struct hns3_enet_ring * ring,int pull_len,struct hns3_desc_cb * desc_cb)3733 static int hns3_handle_rx_copybreak(struct sk_buff *skb, int i,
3734 struct hns3_enet_ring *ring,
3735 int pull_len,
3736 struct hns3_desc_cb *desc_cb)
3737 {
3738 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
3739 u32 frag_offset = desc_cb->page_offset + pull_len;
3740 int size = le16_to_cpu(desc->rx.size);
3741 u32 frag_size = size - pull_len;
3742 void *frag = napi_alloc_frag(frag_size);
3743
3744 if (unlikely(!frag)) {
3745 hns3_ring_stats_update(ring, frag_alloc_err);
3746
3747 hns3_rl_err(ring_to_netdev(ring),
3748 "failed to allocate rx frag\n");
3749 return -ENOMEM;
3750 }
3751
3752 desc_cb->reuse_flag = 1;
3753 memcpy(frag, desc_cb->buf + frag_offset, frag_size);
3754 skb_add_rx_frag(skb, i, virt_to_page(frag),
3755 offset_in_page(frag), frag_size, frag_size);
3756
3757 hns3_ring_stats_update(ring, frag_alloc);
3758 return 0;
3759 }
3760
hns3_nic_reuse_page(struct sk_buff * skb,int i,struct hns3_enet_ring * ring,int pull_len,struct hns3_desc_cb * desc_cb)3761 static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
3762 struct hns3_enet_ring *ring, int pull_len,
3763 struct hns3_desc_cb *desc_cb)
3764 {
3765 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
3766 u32 frag_offset = desc_cb->page_offset + pull_len;
3767 int size = le16_to_cpu(desc->rx.size);
3768 u32 truesize = hns3_buf_size(ring);
3769 u32 frag_size = size - pull_len;
3770 int ret = 0;
3771 bool reused;
3772
3773 if (ring->page_pool) {
3774 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3775 frag_size, truesize);
3776 return;
3777 }
3778
3779 /* Avoid re-using remote or pfmem page */
3780 if (unlikely(!dev_page_is_reusable(desc_cb->priv)))
3781 goto out;
3782
3783 reused = hns3_can_reuse_page(desc_cb);
3784
3785 /* Rx page can be reused when:
3786 * 1. Rx page is only owned by the driver when page_offset
3787 * is zero, which means 0 @ truesize will be used by
3788 * stack after skb_add_rx_frag() is called, and the rest
3789 * of rx page can be reused by driver.
3790 * Or
3791 * 2. Rx page is only owned by the driver when page_offset
3792 * is non-zero, which means page_offset @ truesize will
3793 * be used by stack after skb_add_rx_frag() is called,
3794 * and 0 @ truesize can be reused by driver.
3795 */
3796 if ((!desc_cb->page_offset && reused) ||
3797 ((desc_cb->page_offset + truesize + truesize) <=
3798 hns3_page_size(ring) && desc_cb->page_offset)) {
3799 desc_cb->page_offset += truesize;
3800 desc_cb->reuse_flag = 1;
3801 } else if (desc_cb->page_offset && reused) {
3802 desc_cb->page_offset = 0;
3803 desc_cb->reuse_flag = 1;
3804 } else if (frag_size <= ring->rx_copybreak) {
3805 ret = hns3_handle_rx_copybreak(skb, i, ring, pull_len, desc_cb);
3806 if (!ret)
3807 return;
3808 }
3809
3810 out:
3811 desc_cb->pagecnt_bias--;
3812
3813 if (unlikely(!desc_cb->pagecnt_bias)) {
3814 page_ref_add(desc_cb->priv, USHRT_MAX);
3815 desc_cb->pagecnt_bias = USHRT_MAX;
3816 }
3817
3818 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3819 frag_size, truesize);
3820
3821 if (unlikely(!desc_cb->reuse_flag))
3822 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias);
3823 }
3824
hns3_gro_complete(struct sk_buff * skb,u32 l234info)3825 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
3826 {
3827 __be16 type = skb->protocol;
3828 struct tcphdr *th;
3829 int depth = 0;
3830
3831 while (eth_type_vlan(type)) {
3832 struct vlan_hdr *vh;
3833
3834 if ((depth + VLAN_HLEN) > skb_headlen(skb))
3835 return -EFAULT;
3836
3837 vh = (struct vlan_hdr *)(skb->data + depth);
3838 type = vh->h_vlan_encapsulated_proto;
3839 depth += VLAN_HLEN;
3840 }
3841
3842 skb_set_network_header(skb, depth);
3843
3844 if (type == htons(ETH_P_IP)) {
3845 const struct iphdr *iph = ip_hdr(skb);
3846
3847 depth += sizeof(struct iphdr);
3848 skb_set_transport_header(skb, depth);
3849 th = tcp_hdr(skb);
3850 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
3851 iph->daddr, 0);
3852 } else if (type == htons(ETH_P_IPV6)) {
3853 const struct ipv6hdr *iph = ipv6_hdr(skb);
3854
3855 depth += sizeof(struct ipv6hdr);
3856 skb_set_transport_header(skb, depth);
3857 th = tcp_hdr(skb);
3858 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
3859 &iph->daddr, 0);
3860 } else {
3861 hns3_rl_err(skb->dev,
3862 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
3863 be16_to_cpu(type), depth);
3864 return -EFAULT;
3865 }
3866
3867 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
3868 if (th->cwr)
3869 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
3870
3871 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
3872 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
3873
3874 skb->csum_start = (unsigned char *)th - skb->head;
3875 skb->csum_offset = offsetof(struct tcphdr, check);
3876 skb->ip_summed = CHECKSUM_PARTIAL;
3877
3878 trace_hns3_gro(skb);
3879
3880 return 0;
3881 }
3882
hns3_checksum_complete(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 ptype,u16 csum)3883 static void hns3_checksum_complete(struct hns3_enet_ring *ring,
3884 struct sk_buff *skb, u32 ptype, u16 csum)
3885 {
3886 if (ptype == HNS3_INVALID_PTYPE ||
3887 hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE)
3888 return;
3889
3890 hns3_ring_stats_update(ring, csum_complete);
3891 skb->ip_summed = CHECKSUM_COMPLETE;
3892 skb->csum = csum_unfold((__force __sum16)csum);
3893 }
3894
hns3_rx_handle_csum(struct sk_buff * skb,u32 l234info,u32 ol_info,u32 ptype)3895 static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info,
3896 u32 ol_info, u32 ptype)
3897 {
3898 int l3_type, l4_type;
3899 int ol4_type;
3900
3901 if (ptype != HNS3_INVALID_PTYPE) {
3902 skb->csum_level = hns3_rx_ptype_tbl[ptype].csum_level;
3903 skb->ip_summed = hns3_rx_ptype_tbl[ptype].ip_summed;
3904
3905 return;
3906 }
3907
3908 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
3909 HNS3_RXD_OL4ID_S);
3910 switch (ol4_type) {
3911 case HNS3_OL4_TYPE_MAC_IN_UDP:
3912 case HNS3_OL4_TYPE_NVGRE:
3913 skb->csum_level = 1;
3914 fallthrough;
3915 case HNS3_OL4_TYPE_NO_TUN:
3916 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
3917 HNS3_RXD_L3ID_S);
3918 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
3919 HNS3_RXD_L4ID_S);
3920 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
3921 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
3922 l3_type == HNS3_L3_TYPE_IPV6) &&
3923 (l4_type == HNS3_L4_TYPE_UDP ||
3924 l4_type == HNS3_L4_TYPE_TCP ||
3925 l4_type == HNS3_L4_TYPE_SCTP))
3926 skb->ip_summed = CHECKSUM_UNNECESSARY;
3927 break;
3928 default:
3929 break;
3930 }
3931 }
3932
hns3_rx_checksum(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 l234info,u32 bd_base_info,u32 ol_info,u16 csum)3933 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
3934 u32 l234info, u32 bd_base_info, u32 ol_info,
3935 u16 csum)
3936 {
3937 struct net_device *netdev = ring_to_netdev(ring);
3938 struct hns3_nic_priv *priv = netdev_priv(netdev);
3939 u32 ptype = HNS3_INVALID_PTYPE;
3940
3941 skb->ip_summed = CHECKSUM_NONE;
3942
3943 skb_checksum_none_assert(skb);
3944
3945 if (!(netdev->features & NETIF_F_RXCSUM))
3946 return;
3947
3948 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state))
3949 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
3950 HNS3_RXD_PTYPE_S);
3951
3952 hns3_checksum_complete(ring, skb, ptype, csum);
3953
3954 /* check if hardware has done checksum */
3955 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
3956 return;
3957
3958 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
3959 BIT(HNS3_RXD_OL3E_B) |
3960 BIT(HNS3_RXD_OL4E_B)))) {
3961 skb->ip_summed = CHECKSUM_NONE;
3962 hns3_ring_stats_update(ring, l3l4_csum_err);
3963
3964 return;
3965 }
3966
3967 hns3_rx_handle_csum(skb, l234info, ol_info, ptype);
3968 }
3969
hns3_rx_skb(struct hns3_enet_ring * ring,struct sk_buff * skb)3970 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
3971 {
3972 if (skb_has_frag_list(skb))
3973 napi_gro_flush(&ring->tqp_vector->napi, false);
3974
3975 napi_gro_receive(&ring->tqp_vector->napi, skb);
3976 }
3977
hns3_parse_vlan_tag(struct hns3_enet_ring * ring,struct hns3_desc * desc,u32 l234info,u16 * vlan_tag)3978 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
3979 struct hns3_desc *desc, u32 l234info,
3980 u16 *vlan_tag)
3981 {
3982 struct hnae3_handle *handle = ring->tqp->handle;
3983 struct pci_dev *pdev = ring->tqp->handle->pdev;
3984 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3985
3986 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) {
3987 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3988 if (!(*vlan_tag & VLAN_VID_MASK))
3989 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
3990
3991 return (*vlan_tag != 0);
3992 }
3993
3994 #define HNS3_STRP_OUTER_VLAN 0x1
3995 #define HNS3_STRP_INNER_VLAN 0x2
3996 #define HNS3_STRP_BOTH 0x3
3997
3998 /* Hardware always insert VLAN tag into RX descriptor when
3999 * remove the tag from packet, driver needs to determine
4000 * reporting which tag to stack.
4001 */
4002 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
4003 HNS3_RXD_STRP_TAGP_S)) {
4004 case HNS3_STRP_OUTER_VLAN:
4005 if (handle->port_base_vlan_state !=
4006 HNAE3_PORT_BASE_VLAN_DISABLE)
4007 return false;
4008
4009 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
4010 return true;
4011 case HNS3_STRP_INNER_VLAN:
4012 if (handle->port_base_vlan_state !=
4013 HNAE3_PORT_BASE_VLAN_DISABLE)
4014 return false;
4015
4016 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
4017 return true;
4018 case HNS3_STRP_BOTH:
4019 if (handle->port_base_vlan_state ==
4020 HNAE3_PORT_BASE_VLAN_DISABLE)
4021 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
4022 else
4023 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
4024
4025 return true;
4026 default:
4027 return false;
4028 }
4029 }
4030
hns3_rx_ring_move_fw(struct hns3_enet_ring * ring)4031 static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring)
4032 {
4033 ring->desc[ring->next_to_clean].rx.bd_base_info &=
4034 cpu_to_le32(~BIT(HNS3_RXD_VLD_B));
4035 ring->desc_cb[ring->next_to_clean].refill = 0;
4036 ring->next_to_clean += 1;
4037
4038 if (unlikely(ring->next_to_clean == ring->desc_num))
4039 ring->next_to_clean = 0;
4040 }
4041
hns3_alloc_skb(struct hns3_enet_ring * ring,unsigned int length,unsigned char * va)4042 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
4043 unsigned char *va)
4044 {
4045 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
4046 struct net_device *netdev = ring_to_netdev(ring);
4047 struct sk_buff *skb;
4048
4049 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
4050 skb = ring->skb;
4051 if (unlikely(!skb)) {
4052 hns3_rl_err(netdev, "alloc rx skb fail\n");
4053 hns3_ring_stats_update(ring, sw_err_cnt);
4054
4055 return -ENOMEM;
4056 }
4057
4058 trace_hns3_rx_desc(ring);
4059 prefetchw(skb->data);
4060
4061 ring->pending_buf = 1;
4062 ring->frag_num = 0;
4063 ring->tail_skb = NULL;
4064 if (length <= HNS3_RX_HEAD_SIZE) {
4065 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
4066
4067 /* We can reuse buffer as-is, just make sure it is reusable */
4068 if (dev_page_is_reusable(desc_cb->priv))
4069 desc_cb->reuse_flag = 1;
4070 else if (desc_cb->type & DESC_TYPE_PP_FRAG)
4071 page_pool_put_full_page(ring->page_pool, desc_cb->priv,
4072 false);
4073 else /* This page cannot be reused so discard it */
4074 __page_frag_cache_drain(desc_cb->priv,
4075 desc_cb->pagecnt_bias);
4076
4077 hns3_rx_ring_move_fw(ring);
4078 return 0;
4079 }
4080
4081 if (ring->page_pool)
4082 skb_mark_for_recycle(skb);
4083
4084 hns3_ring_stats_update(ring, seg_pkt_cnt);
4085
4086 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
4087 __skb_put(skb, ring->pull_len);
4088 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
4089 desc_cb);
4090 hns3_rx_ring_move_fw(ring);
4091
4092 return 0;
4093 }
4094
hns3_add_frag(struct hns3_enet_ring * ring)4095 static int hns3_add_frag(struct hns3_enet_ring *ring)
4096 {
4097 struct sk_buff *skb = ring->skb;
4098 struct sk_buff *head_skb = skb;
4099 struct sk_buff *new_skb;
4100 struct hns3_desc_cb *desc_cb;
4101 struct hns3_desc *desc;
4102 u32 bd_base_info;
4103
4104 do {
4105 desc = &ring->desc[ring->next_to_clean];
4106 desc_cb = &ring->desc_cb[ring->next_to_clean];
4107 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4108 /* make sure HW write desc complete */
4109 dma_rmb();
4110 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
4111 return -ENXIO;
4112
4113 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
4114 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
4115 if (unlikely(!new_skb)) {
4116 hns3_rl_err(ring_to_netdev(ring),
4117 "alloc rx fraglist skb fail\n");
4118 return -ENXIO;
4119 }
4120
4121 if (ring->page_pool)
4122 skb_mark_for_recycle(new_skb);
4123
4124 ring->frag_num = 0;
4125
4126 if (ring->tail_skb) {
4127 ring->tail_skb->next = new_skb;
4128 ring->tail_skb = new_skb;
4129 } else {
4130 skb_shinfo(skb)->frag_list = new_skb;
4131 ring->tail_skb = new_skb;
4132 }
4133 }
4134
4135 if (ring->tail_skb) {
4136 head_skb->truesize += hns3_buf_size(ring);
4137 head_skb->data_len += le16_to_cpu(desc->rx.size);
4138 head_skb->len += le16_to_cpu(desc->rx.size);
4139 skb = ring->tail_skb;
4140 }
4141
4142 dma_sync_single_for_cpu(ring_to_dev(ring),
4143 desc_cb->dma + desc_cb->page_offset,
4144 hns3_buf_size(ring),
4145 DMA_FROM_DEVICE);
4146
4147 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
4148 trace_hns3_rx_desc(ring);
4149 hns3_rx_ring_move_fw(ring);
4150 ring->pending_buf++;
4151 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B)));
4152
4153 return 0;
4154 }
4155
hns3_set_gro_and_checksum(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 l234info,u32 bd_base_info,u32 ol_info,u16 csum)4156 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
4157 struct sk_buff *skb, u32 l234info,
4158 u32 bd_base_info, u32 ol_info, u16 csum)
4159 {
4160 struct net_device *netdev = ring_to_netdev(ring);
4161 struct hns3_nic_priv *priv = netdev_priv(netdev);
4162 u32 l3_type;
4163
4164 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
4165 HNS3_RXD_GRO_SIZE_M,
4166 HNS3_RXD_GRO_SIZE_S);
4167 /* if there is no HW GRO, do not set gro params */
4168 if (!skb_shinfo(skb)->gso_size) {
4169 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info,
4170 csum);
4171 return 0;
4172 }
4173
4174 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
4175 HNS3_RXD_GRO_COUNT_M,
4176 HNS3_RXD_GRO_COUNT_S);
4177
4178 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
4179 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
4180 HNS3_RXD_PTYPE_S);
4181
4182 l3_type = hns3_rx_ptype_tbl[ptype].l3_type;
4183 } else {
4184 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
4185 HNS3_RXD_L3ID_S);
4186 }
4187
4188 if (l3_type == HNS3_L3_TYPE_IPV4)
4189 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
4190 else if (l3_type == HNS3_L3_TYPE_IPV6)
4191 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
4192 else
4193 return -EFAULT;
4194
4195 return hns3_gro_complete(skb, l234info);
4196 }
4197
hns3_set_rx_skb_rss_type(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 rss_hash,u32 l234info,u32 ol_info)4198 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
4199 struct sk_buff *skb, u32 rss_hash,
4200 u32 l234info, u32 ol_info)
4201 {
4202 enum pkt_hash_types rss_type = PKT_HASH_TYPE_NONE;
4203 struct net_device *netdev = ring_to_netdev(ring);
4204 struct hns3_nic_priv *priv = netdev_priv(netdev);
4205
4206 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
4207 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
4208 HNS3_RXD_PTYPE_S);
4209
4210 rss_type = hns3_rx_ptype_tbl[ptype].hash_type;
4211 } else {
4212 int l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
4213 HNS3_RXD_L3ID_S);
4214 int l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
4215 HNS3_RXD_L4ID_S);
4216
4217 if (l3_type == HNS3_L3_TYPE_IPV4 ||
4218 l3_type == HNS3_L3_TYPE_IPV6) {
4219 if (l4_type == HNS3_L4_TYPE_UDP ||
4220 l4_type == HNS3_L4_TYPE_TCP ||
4221 l4_type == HNS3_L4_TYPE_SCTP)
4222 rss_type = PKT_HASH_TYPE_L4;
4223 else if (l4_type == HNS3_L4_TYPE_IGMP ||
4224 l4_type == HNS3_L4_TYPE_ICMP)
4225 rss_type = PKT_HASH_TYPE_L3;
4226 }
4227 }
4228
4229 skb_set_hash(skb, rss_hash, rss_type);
4230 }
4231
hns3_handle_rx_ts_info(struct net_device * netdev,struct hns3_desc * desc,struct sk_buff * skb,u32 bd_base_info)4232 static void hns3_handle_rx_ts_info(struct net_device *netdev,
4233 struct hns3_desc *desc, struct sk_buff *skb,
4234 u32 bd_base_info)
4235 {
4236 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) {
4237 struct hnae3_handle *h = hns3_get_handle(netdev);
4238 u32 nsec = le32_to_cpu(desc->ts_nsec);
4239 u32 sec = le32_to_cpu(desc->ts_sec);
4240
4241 if (h->ae_algo->ops->get_rx_hwts)
4242 h->ae_algo->ops->get_rx_hwts(h, skb, nsec, sec);
4243 }
4244 }
4245
hns3_handle_rx_vlan_tag(struct hns3_enet_ring * ring,struct hns3_desc * desc,struct sk_buff * skb,u32 l234info)4246 static void hns3_handle_rx_vlan_tag(struct hns3_enet_ring *ring,
4247 struct hns3_desc *desc, struct sk_buff *skb,
4248 u32 l234info)
4249 {
4250 struct net_device *netdev = ring_to_netdev(ring);
4251
4252 /* Based on hw strategy, the tag offloaded will be stored at
4253 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
4254 * in one layer tag case.
4255 */
4256 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
4257 u16 vlan_tag;
4258
4259 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
4260 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
4261 vlan_tag);
4262 }
4263 }
4264
hns3_handle_bdinfo(struct hns3_enet_ring * ring,struct sk_buff * skb)4265 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
4266 {
4267 struct net_device *netdev = ring_to_netdev(ring);
4268 enum hns3_pkt_l2t_type l2_frame_type;
4269 u32 bd_base_info, l234info, ol_info;
4270 struct hns3_desc *desc;
4271 unsigned int len;
4272 int pre_ntc, ret;
4273 u16 csum;
4274
4275 /* bdinfo handled below is only valid on the last BD of the
4276 * current packet, and ring->next_to_clean indicates the first
4277 * descriptor of next packet, so need - 1 below.
4278 */
4279 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
4280 (ring->desc_num - 1);
4281 desc = &ring->desc[pre_ntc];
4282 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4283 l234info = le32_to_cpu(desc->rx.l234_info);
4284 ol_info = le32_to_cpu(desc->rx.ol_info);
4285 csum = le16_to_cpu(desc->csum);
4286
4287 hns3_handle_rx_ts_info(netdev, desc, skb, bd_base_info);
4288
4289 hns3_handle_rx_vlan_tag(ring, desc, skb, l234info);
4290
4291 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
4292 BIT(HNS3_RXD_L2E_B))))) {
4293 u64_stats_update_begin(&ring->syncp);
4294 if (l234info & BIT(HNS3_RXD_L2E_B))
4295 ring->stats.l2_err++;
4296 else
4297 ring->stats.err_pkt_len++;
4298 u64_stats_update_end(&ring->syncp);
4299
4300 return -EFAULT;
4301 }
4302
4303 len = skb->len;
4304
4305 /* Do update ip stack process */
4306 skb->protocol = eth_type_trans(skb, netdev);
4307
4308 /* This is needed in order to enable forwarding support */
4309 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
4310 bd_base_info, ol_info, csum);
4311 if (unlikely(ret)) {
4312 hns3_ring_stats_update(ring, rx_err_cnt);
4313 return ret;
4314 }
4315
4316 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
4317 HNS3_RXD_DMAC_S);
4318
4319 u64_stats_update_begin(&ring->syncp);
4320 ring->stats.rx_pkts++;
4321 ring->stats.rx_bytes += len;
4322
4323 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
4324 ring->stats.rx_multicast++;
4325
4326 u64_stats_update_end(&ring->syncp);
4327
4328 ring->tqp_vector->rx_group.total_bytes += len;
4329
4330 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash),
4331 l234info, ol_info);
4332 return 0;
4333 }
4334
hns3_handle_rx_bd(struct hns3_enet_ring * ring)4335 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
4336 {
4337 struct sk_buff *skb = ring->skb;
4338 struct hns3_desc_cb *desc_cb;
4339 struct hns3_desc *desc;
4340 unsigned int length;
4341 u32 bd_base_info;
4342 int ret;
4343
4344 desc = &ring->desc[ring->next_to_clean];
4345 desc_cb = &ring->desc_cb[ring->next_to_clean];
4346
4347 prefetch(desc);
4348
4349 if (!skb) {
4350 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4351 /* Check valid BD */
4352 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
4353 return -ENXIO;
4354
4355 dma_rmb();
4356 length = le16_to_cpu(desc->rx.size);
4357
4358 ring->va = desc_cb->buf + desc_cb->page_offset;
4359
4360 dma_sync_single_for_cpu(ring_to_dev(ring),
4361 desc_cb->dma + desc_cb->page_offset,
4362 hns3_buf_size(ring),
4363 DMA_FROM_DEVICE);
4364
4365 /* Prefetch first cache line of first page.
4366 * Idea is to cache few bytes of the header of the packet.
4367 * Our L1 Cache line size is 64B so need to prefetch twice to make
4368 * it 128B. But in actual we can have greater size of caches with
4369 * 128B Level 1 cache lines. In such a case, single fetch would
4370 * suffice to cache in the relevant part of the header.
4371 */
4372 net_prefetch(ring->va);
4373
4374 ret = hns3_alloc_skb(ring, length, ring->va);
4375 skb = ring->skb;
4376
4377 if (ret < 0) /* alloc buffer fail */
4378 return ret;
4379 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */
4380 ret = hns3_add_frag(ring);
4381 if (ret)
4382 return ret;
4383 }
4384 } else {
4385 ret = hns3_add_frag(ring);
4386 if (ret)
4387 return ret;
4388 }
4389
4390 /* As the head data may be changed when GRO enable, copy
4391 * the head data in after other data rx completed
4392 */
4393 if (skb->len > HNS3_RX_HEAD_SIZE)
4394 memcpy(skb->data, ring->va,
4395 ALIGN(ring->pull_len, sizeof(long)));
4396
4397 ret = hns3_handle_bdinfo(ring, skb);
4398 if (unlikely(ret)) {
4399 dev_kfree_skb_any(skb);
4400 return ret;
4401 }
4402
4403 skb_record_rx_queue(skb, ring->tqp->tqp_index);
4404 return 0;
4405 }
4406
hns3_clean_rx_ring(struct hns3_enet_ring * ring,int budget,void (* rx_fn)(struct hns3_enet_ring *,struct sk_buff *))4407 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
4408 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
4409 {
4410 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
4411 int unused_count = hns3_desc_unused(ring);
4412 bool failure = false;
4413 int recv_pkts = 0;
4414 int err;
4415
4416 unused_count -= ring->pending_buf;
4417
4418 while (recv_pkts < budget) {
4419 /* Reuse or realloc buffers */
4420 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
4421 failure = failure ||
4422 hns3_nic_alloc_rx_buffers(ring, unused_count);
4423 unused_count = 0;
4424 }
4425
4426 /* Poll one pkt */
4427 err = hns3_handle_rx_bd(ring);
4428 /* Do not get FE for the packet or failed to alloc skb */
4429 if (unlikely(!ring->skb || err == -ENXIO)) {
4430 goto out;
4431 } else if (likely(!err)) {
4432 rx_fn(ring, ring->skb);
4433 recv_pkts++;
4434 }
4435
4436 unused_count += ring->pending_buf;
4437 ring->skb = NULL;
4438 ring->pending_buf = 0;
4439 }
4440
4441 out:
4442 /* sync head pointer before exiting, since hardware will calculate
4443 * FBD number with head pointer
4444 */
4445 if (unused_count > 0)
4446 failure = failure ||
4447 hns3_nic_alloc_rx_buffers(ring, unused_count);
4448
4449 return failure ? budget : recv_pkts;
4450 }
4451
hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector * tqp_vector)4452 static void hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
4453 {
4454 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
4455 struct dim_sample sample = {};
4456
4457 if (!rx_group->coal.adapt_enable)
4458 return;
4459
4460 dim_update_sample(tqp_vector->event_cnt, rx_group->total_packets,
4461 rx_group->total_bytes, &sample);
4462 net_dim(&rx_group->dim, sample);
4463 }
4464
hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector * tqp_vector)4465 static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
4466 {
4467 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
4468 struct dim_sample sample = {};
4469
4470 if (!tx_group->coal.adapt_enable)
4471 return;
4472
4473 dim_update_sample(tqp_vector->event_cnt, tx_group->total_packets,
4474 tx_group->total_bytes, &sample);
4475 net_dim(&tx_group->dim, sample);
4476 }
4477
hns3_nic_common_poll(struct napi_struct * napi,int budget)4478 static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
4479 {
4480 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
4481 struct hns3_enet_ring *ring;
4482 int rx_pkt_total = 0;
4483
4484 struct hns3_enet_tqp_vector *tqp_vector =
4485 container_of(napi, struct hns3_enet_tqp_vector, napi);
4486 bool clean_complete = true;
4487 int rx_budget = budget;
4488
4489 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4490 napi_complete(napi);
4491 return 0;
4492 }
4493
4494 /* Since the actual Tx work is minimal, we can give the Tx a larger
4495 * budget and be more aggressive about cleaning up the Tx descriptors.
4496 */
4497 hns3_for_each_ring(ring, tqp_vector->tx_group)
4498 hns3_clean_tx_ring(ring, budget);
4499
4500 /* make sure rx ring budget not smaller than 1 */
4501 if (tqp_vector->num_tqps > 1)
4502 rx_budget = max(budget / tqp_vector->num_tqps, 1);
4503
4504 hns3_for_each_ring(ring, tqp_vector->rx_group) {
4505 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
4506 hns3_rx_skb);
4507 if (rx_cleaned >= rx_budget)
4508 clean_complete = false;
4509
4510 rx_pkt_total += rx_cleaned;
4511 }
4512
4513 tqp_vector->rx_group.total_packets += rx_pkt_total;
4514
4515 if (!clean_complete)
4516 return budget;
4517
4518 if (napi_complete(napi) &&
4519 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4520 hns3_update_rx_int_coalesce(tqp_vector);
4521 hns3_update_tx_int_coalesce(tqp_vector);
4522
4523 hns3_mask_vector_irq(tqp_vector, 1);
4524 }
4525
4526 return rx_pkt_total;
4527 }
4528
hns3_create_ring_chain(struct hns3_enet_tqp_vector * tqp_vector,struct hnae3_ring_chain_node ** head,bool is_tx)4529 static int hns3_create_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4530 struct hnae3_ring_chain_node **head,
4531 bool is_tx)
4532 {
4533 u32 bit_value = is_tx ? HNAE3_RING_TYPE_TX : HNAE3_RING_TYPE_RX;
4534 u32 field_value = is_tx ? HNAE3_RING_GL_TX : HNAE3_RING_GL_RX;
4535 struct hnae3_ring_chain_node *cur_chain = *head;
4536 struct pci_dev *pdev = tqp_vector->handle->pdev;
4537 struct hnae3_ring_chain_node *chain;
4538 struct hns3_enet_ring *ring;
4539
4540 ring = is_tx ? tqp_vector->tx_group.ring : tqp_vector->rx_group.ring;
4541
4542 if (cur_chain) {
4543 while (cur_chain->next)
4544 cur_chain = cur_chain->next;
4545 }
4546
4547 while (ring) {
4548 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
4549 if (!chain)
4550 return -ENOMEM;
4551 if (cur_chain)
4552 cur_chain->next = chain;
4553 else
4554 *head = chain;
4555 chain->tqp_index = ring->tqp->tqp_index;
4556 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
4557 bit_value);
4558 hnae3_set_field(chain->int_gl_idx,
4559 HNAE3_RING_GL_IDX_M,
4560 HNAE3_RING_GL_IDX_S, field_value);
4561
4562 cur_chain = chain;
4563
4564 ring = ring->next;
4565 }
4566
4567 return 0;
4568 }
4569
4570 static struct hnae3_ring_chain_node *
hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector * tqp_vector)4571 hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector)
4572 {
4573 struct pci_dev *pdev = tqp_vector->handle->pdev;
4574 struct hnae3_ring_chain_node *cur_chain = NULL;
4575 struct hnae3_ring_chain_node *chain;
4576
4577 if (hns3_create_ring_chain(tqp_vector, &cur_chain, true))
4578 goto err_free_chain;
4579
4580 if (hns3_create_ring_chain(tqp_vector, &cur_chain, false))
4581 goto err_free_chain;
4582
4583 return cur_chain;
4584
4585 err_free_chain:
4586 while (cur_chain) {
4587 chain = cur_chain->next;
4588 devm_kfree(&pdev->dev, cur_chain);
4589 cur_chain = chain;
4590 }
4591
4592 return NULL;
4593 }
4594
hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector * tqp_vector,struct hnae3_ring_chain_node * head)4595 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4596 struct hnae3_ring_chain_node *head)
4597 {
4598 struct pci_dev *pdev = tqp_vector->handle->pdev;
4599 struct hnae3_ring_chain_node *chain_tmp, *chain;
4600
4601 chain = head;
4602
4603 while (chain) {
4604 chain_tmp = chain->next;
4605 devm_kfree(&pdev->dev, chain);
4606 chain = chain_tmp;
4607 }
4608 }
4609
hns3_add_ring_to_group(struct hns3_enet_ring_group * group,struct hns3_enet_ring * ring)4610 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
4611 struct hns3_enet_ring *ring)
4612 {
4613 ring->next = group->ring;
4614 group->ring = ring;
4615
4616 group->count++;
4617 }
4618
hns3_nic_set_cpumask(struct hns3_nic_priv * priv)4619 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
4620 {
4621 struct pci_dev *pdev = priv->ae_handle->pdev;
4622 struct hns3_enet_tqp_vector *tqp_vector;
4623 int num_vectors = priv->vector_num;
4624 int numa_node;
4625 int vector_i;
4626
4627 numa_node = dev_to_node(&pdev->dev);
4628
4629 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
4630 tqp_vector = &priv->tqp_vector[vector_i];
4631 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
4632 &tqp_vector->affinity_mask);
4633 }
4634 }
4635
hns3_rx_dim_work(struct work_struct * work)4636 static void hns3_rx_dim_work(struct work_struct *work)
4637 {
4638 struct dim *dim = container_of(work, struct dim, work);
4639 struct hns3_enet_ring_group *group = container_of(dim,
4640 struct hns3_enet_ring_group, dim);
4641 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4642 struct dim_cq_moder cur_moder =
4643 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
4644
4645 hns3_set_vector_coalesce_rx_gl(group->ring->tqp_vector, cur_moder.usec);
4646 tqp_vector->rx_group.coal.int_gl = cur_moder.usec;
4647
4648 if (cur_moder.pkts < tqp_vector->rx_group.coal.int_ql_max) {
4649 hns3_set_vector_coalesce_rx_ql(tqp_vector, cur_moder.pkts);
4650 tqp_vector->rx_group.coal.int_ql = cur_moder.pkts;
4651 }
4652
4653 dim->state = DIM_START_MEASURE;
4654 }
4655
hns3_tx_dim_work(struct work_struct * work)4656 static void hns3_tx_dim_work(struct work_struct *work)
4657 {
4658 struct dim *dim = container_of(work, struct dim, work);
4659 struct hns3_enet_ring_group *group = container_of(dim,
4660 struct hns3_enet_ring_group, dim);
4661 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4662 struct dim_cq_moder cur_moder =
4663 net_dim_get_tx_moderation(dim->mode, dim->profile_ix);
4664
4665 hns3_set_vector_coalesce_tx_gl(tqp_vector, cur_moder.usec);
4666 tqp_vector->tx_group.coal.int_gl = cur_moder.usec;
4667
4668 if (cur_moder.pkts < tqp_vector->tx_group.coal.int_ql_max) {
4669 hns3_set_vector_coalesce_tx_ql(tqp_vector, cur_moder.pkts);
4670 tqp_vector->tx_group.coal.int_ql = cur_moder.pkts;
4671 }
4672
4673 dim->state = DIM_START_MEASURE;
4674 }
4675
hns3_nic_init_dim(struct hns3_enet_tqp_vector * tqp_vector)4676 static void hns3_nic_init_dim(struct hns3_enet_tqp_vector *tqp_vector)
4677 {
4678 INIT_WORK(&tqp_vector->rx_group.dim.work, hns3_rx_dim_work);
4679 INIT_WORK(&tqp_vector->tx_group.dim.work, hns3_tx_dim_work);
4680 }
4681
hns3_nic_init_vector_data(struct hns3_nic_priv * priv)4682 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
4683 {
4684 struct hnae3_handle *h = priv->ae_handle;
4685 struct hns3_enet_tqp_vector *tqp_vector;
4686 int ret;
4687 int i;
4688
4689 hns3_nic_set_cpumask(priv);
4690
4691 for (i = 0; i < priv->vector_num; i++) {
4692 tqp_vector = &priv->tqp_vector[i];
4693 hns3_vector_coalesce_init_hw(tqp_vector, priv);
4694 tqp_vector->num_tqps = 0;
4695 hns3_nic_init_dim(tqp_vector);
4696 }
4697
4698 for (i = 0; i < h->kinfo.num_tqps; i++) {
4699 u16 vector_i = i % priv->vector_num;
4700 u16 tqp_num = h->kinfo.num_tqps;
4701
4702 tqp_vector = &priv->tqp_vector[vector_i];
4703
4704 hns3_add_ring_to_group(&tqp_vector->tx_group,
4705 &priv->ring[i]);
4706
4707 hns3_add_ring_to_group(&tqp_vector->rx_group,
4708 &priv->ring[i + tqp_num]);
4709
4710 priv->ring[i].tqp_vector = tqp_vector;
4711 priv->ring[i + tqp_num].tqp_vector = tqp_vector;
4712 tqp_vector->num_tqps++;
4713 }
4714
4715 for (i = 0; i < priv->vector_num; i++) {
4716 struct hnae3_ring_chain_node *vector_ring_chain;
4717
4718 tqp_vector = &priv->tqp_vector[i];
4719
4720 tqp_vector->rx_group.total_bytes = 0;
4721 tqp_vector->rx_group.total_packets = 0;
4722 tqp_vector->tx_group.total_bytes = 0;
4723 tqp_vector->tx_group.total_packets = 0;
4724 tqp_vector->handle = h;
4725
4726 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector);
4727 if (!vector_ring_chain) {
4728 ret = -ENOMEM;
4729 goto map_ring_fail;
4730 }
4731
4732 ret = h->ae_algo->ops->map_ring_to_vector(h,
4733 tqp_vector->vector_irq, vector_ring_chain);
4734
4735 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain);
4736
4737 if (ret)
4738 goto map_ring_fail;
4739
4740 netif_napi_add(priv->netdev, &tqp_vector->napi,
4741 hns3_nic_common_poll);
4742 }
4743
4744 return 0;
4745
4746 map_ring_fail:
4747 while (i--)
4748 netif_napi_del(&priv->tqp_vector[i].napi);
4749
4750 return ret;
4751 }
4752
hns3_nic_init_coal_cfg(struct hns3_nic_priv * priv)4753 static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv)
4754 {
4755 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
4756 struct hns3_enet_coalesce *tx_coal = &priv->tx_coal;
4757 struct hns3_enet_coalesce *rx_coal = &priv->rx_coal;
4758
4759 /* initialize the configuration for interrupt coalescing.
4760 * 1. GL (Interrupt Gap Limiter)
4761 * 2. RL (Interrupt Rate Limiter)
4762 * 3. QL (Interrupt Quantity Limiter)
4763 *
4764 * Default: enable interrupt coalescing self-adaptive and GL
4765 */
4766 tx_coal->adapt_enable = 1;
4767 rx_coal->adapt_enable = 1;
4768
4769 tx_coal->int_gl = HNS3_INT_GL_50K;
4770 rx_coal->int_gl = HNS3_INT_GL_50K;
4771
4772 rx_coal->flow_level = HNS3_FLOW_LOW;
4773 tx_coal->flow_level = HNS3_FLOW_LOW;
4774
4775 if (ae_dev->dev_specs.int_ql_max) {
4776 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4777 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4778 }
4779 }
4780
hns3_nic_alloc_vector_data(struct hns3_nic_priv * priv)4781 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
4782 {
4783 struct hnae3_handle *h = priv->ae_handle;
4784 struct hns3_enet_tqp_vector *tqp_vector;
4785 struct hnae3_vector_info *vector;
4786 struct pci_dev *pdev = h->pdev;
4787 u16 tqp_num = h->kinfo.num_tqps;
4788 u16 vector_num;
4789 int ret = 0;
4790 u16 i;
4791
4792 /* RSS size, cpu online and vector_num should be the same */
4793 /* Should consider 2p/4p later */
4794 vector_num = min_t(u16, num_online_cpus(), tqp_num);
4795
4796 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
4797 GFP_KERNEL);
4798 if (!vector)
4799 return -ENOMEM;
4800
4801 /* save the actual available vector number */
4802 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
4803
4804 priv->vector_num = vector_num;
4805 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
4806 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
4807 GFP_KERNEL);
4808 if (!priv->tqp_vector) {
4809 ret = -ENOMEM;
4810 goto out;
4811 }
4812
4813 for (i = 0; i < priv->vector_num; i++) {
4814 tqp_vector = &priv->tqp_vector[i];
4815 tqp_vector->idx = i;
4816 tqp_vector->mask_addr = vector[i].io_addr;
4817 tqp_vector->vector_irq = vector[i].vector;
4818 hns3_vector_coalesce_init(tqp_vector, priv);
4819 }
4820
4821 out:
4822 devm_kfree(&pdev->dev, vector);
4823 return ret;
4824 }
4825
hns3_clear_ring_group(struct hns3_enet_ring_group * group)4826 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
4827 {
4828 group->ring = NULL;
4829 group->count = 0;
4830 }
4831
hns3_nic_uninit_vector_data(struct hns3_nic_priv * priv)4832 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
4833 {
4834 struct hnae3_ring_chain_node *vector_ring_chain;
4835 struct hnae3_handle *h = priv->ae_handle;
4836 struct hns3_enet_tqp_vector *tqp_vector;
4837 int i;
4838
4839 for (i = 0; i < priv->vector_num; i++) {
4840 tqp_vector = &priv->tqp_vector[i];
4841
4842 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
4843 continue;
4844
4845 /* Since the mapping can be overwritten, when fail to get the
4846 * chain between vector and ring, we should go on to deal with
4847 * the remaining options.
4848 */
4849 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector);
4850 if (!vector_ring_chain)
4851 dev_warn(priv->dev, "failed to get ring chain\n");
4852
4853 h->ae_algo->ops->unmap_ring_from_vector(h,
4854 tqp_vector->vector_irq, vector_ring_chain);
4855
4856 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain);
4857
4858 hns3_clear_ring_group(&tqp_vector->rx_group);
4859 hns3_clear_ring_group(&tqp_vector->tx_group);
4860 netif_napi_del(&priv->tqp_vector[i].napi);
4861 }
4862 }
4863
hns3_nic_dealloc_vector_data(struct hns3_nic_priv * priv)4864 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
4865 {
4866 struct hnae3_handle *h = priv->ae_handle;
4867 struct pci_dev *pdev = h->pdev;
4868 int i, ret;
4869
4870 for (i = 0; i < priv->vector_num; i++) {
4871 struct hns3_enet_tqp_vector *tqp_vector;
4872
4873 tqp_vector = &priv->tqp_vector[i];
4874 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
4875 if (ret)
4876 return;
4877 }
4878
4879 devm_kfree(&pdev->dev, priv->tqp_vector);
4880 }
4881
hns3_ring_get_cfg(struct hnae3_queue * q,struct hns3_nic_priv * priv,unsigned int ring_type)4882 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
4883 unsigned int ring_type)
4884 {
4885 int queue_num = priv->ae_handle->kinfo.num_tqps;
4886 struct hns3_enet_ring *ring;
4887 int desc_num;
4888
4889 if (ring_type == HNAE3_RING_TYPE_TX) {
4890 ring = &priv->ring[q->tqp_index];
4891 desc_num = priv->ae_handle->kinfo.num_tx_desc;
4892 ring->queue_index = q->tqp_index;
4893 ring->tx_copybreak = priv->tx_copybreak;
4894 ring->last_to_use = 0;
4895 } else {
4896 ring = &priv->ring[q->tqp_index + queue_num];
4897 desc_num = priv->ae_handle->kinfo.num_rx_desc;
4898 ring->queue_index = q->tqp_index;
4899 ring->rx_copybreak = priv->rx_copybreak;
4900 }
4901
4902 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
4903
4904 ring->tqp = q;
4905 ring->desc = NULL;
4906 ring->desc_cb = NULL;
4907 ring->dev = priv->dev;
4908 ring->desc_dma_addr = 0;
4909 ring->buf_size = q->buf_size;
4910 ring->desc_num = desc_num;
4911 ring->next_to_use = 0;
4912 ring->next_to_clean = 0;
4913 }
4914
hns3_queue_to_ring(struct hnae3_queue * tqp,struct hns3_nic_priv * priv)4915 static void hns3_queue_to_ring(struct hnae3_queue *tqp,
4916 struct hns3_nic_priv *priv)
4917 {
4918 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
4919 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
4920 }
4921
hns3_get_ring_config(struct hns3_nic_priv * priv)4922 static int hns3_get_ring_config(struct hns3_nic_priv *priv)
4923 {
4924 struct hnae3_handle *h = priv->ae_handle;
4925 struct pci_dev *pdev = h->pdev;
4926 int i;
4927
4928 priv->ring = devm_kzalloc(&pdev->dev,
4929 array3_size(h->kinfo.num_tqps,
4930 sizeof(*priv->ring), 2),
4931 GFP_KERNEL);
4932 if (!priv->ring)
4933 return -ENOMEM;
4934
4935 for (i = 0; i < h->kinfo.num_tqps; i++)
4936 hns3_queue_to_ring(h->kinfo.tqp[i], priv);
4937
4938 return 0;
4939 }
4940
hns3_put_ring_config(struct hns3_nic_priv * priv)4941 static void hns3_put_ring_config(struct hns3_nic_priv *priv)
4942 {
4943 if (!priv->ring)
4944 return;
4945
4946 devm_kfree(priv->dev, priv->ring);
4947 priv->ring = NULL;
4948 }
4949
hns3_alloc_page_pool(struct hns3_enet_ring * ring)4950 static void hns3_alloc_page_pool(struct hns3_enet_ring *ring)
4951 {
4952 struct page_pool_params pp_params = {
4953 .flags = PP_FLAG_DMA_MAP | PP_FLAG_PAGE_FRAG |
4954 PP_FLAG_DMA_SYNC_DEV,
4955 .order = hns3_page_order(ring),
4956 .pool_size = ring->desc_num * hns3_buf_size(ring) /
4957 (PAGE_SIZE << hns3_page_order(ring)),
4958 .nid = dev_to_node(ring_to_dev(ring)),
4959 .dev = ring_to_dev(ring),
4960 .dma_dir = DMA_FROM_DEVICE,
4961 .offset = 0,
4962 .max_len = PAGE_SIZE << hns3_page_order(ring),
4963 };
4964
4965 ring->page_pool = page_pool_create(&pp_params);
4966 if (IS_ERR(ring->page_pool)) {
4967 dev_warn(ring_to_dev(ring), "page pool creation failed: %ld\n",
4968 PTR_ERR(ring->page_pool));
4969 ring->page_pool = NULL;
4970 }
4971 }
4972
hns3_alloc_ring_memory(struct hns3_enet_ring * ring)4973 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
4974 {
4975 int ret;
4976
4977 if (ring->desc_num <= 0 || ring->buf_size <= 0)
4978 return -EINVAL;
4979
4980 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
4981 sizeof(ring->desc_cb[0]), GFP_KERNEL);
4982 if (!ring->desc_cb) {
4983 ret = -ENOMEM;
4984 goto out;
4985 }
4986
4987 ret = hns3_alloc_desc(ring);
4988 if (ret)
4989 goto out_with_desc_cb;
4990
4991 if (!HNAE3_IS_TX_RING(ring)) {
4992 if (page_pool_enabled)
4993 hns3_alloc_page_pool(ring);
4994
4995 ret = hns3_alloc_ring_buffers(ring);
4996 if (ret)
4997 goto out_with_desc;
4998 } else {
4999 hns3_init_tx_spare_buffer(ring);
5000 }
5001
5002 return 0;
5003
5004 out_with_desc:
5005 hns3_free_desc(ring);
5006 out_with_desc_cb:
5007 devm_kfree(ring_to_dev(ring), ring->desc_cb);
5008 ring->desc_cb = NULL;
5009 out:
5010 return ret;
5011 }
5012
hns3_fini_ring(struct hns3_enet_ring * ring)5013 void hns3_fini_ring(struct hns3_enet_ring *ring)
5014 {
5015 hns3_free_desc(ring);
5016 devm_kfree(ring_to_dev(ring), ring->desc_cb);
5017 ring->desc_cb = NULL;
5018 ring->next_to_clean = 0;
5019 ring->next_to_use = 0;
5020 ring->last_to_use = 0;
5021 ring->pending_buf = 0;
5022 if (!HNAE3_IS_TX_RING(ring) && ring->skb) {
5023 dev_kfree_skb_any(ring->skb);
5024 ring->skb = NULL;
5025 } else if (HNAE3_IS_TX_RING(ring) && ring->tx_spare) {
5026 struct hns3_tx_spare *tx_spare = ring->tx_spare;
5027
5028 dma_unmap_page(ring_to_dev(ring), tx_spare->dma, tx_spare->len,
5029 DMA_TO_DEVICE);
5030 free_pages((unsigned long)tx_spare->buf,
5031 get_order(tx_spare->len));
5032 devm_kfree(ring_to_dev(ring), tx_spare);
5033 ring->tx_spare = NULL;
5034 }
5035
5036 if (!HNAE3_IS_TX_RING(ring) && ring->page_pool) {
5037 page_pool_destroy(ring->page_pool);
5038 ring->page_pool = NULL;
5039 }
5040 }
5041
hns3_buf_size2type(u32 buf_size)5042 static int hns3_buf_size2type(u32 buf_size)
5043 {
5044 int bd_size_type;
5045
5046 switch (buf_size) {
5047 case 512:
5048 bd_size_type = HNS3_BD_SIZE_512_TYPE;
5049 break;
5050 case 1024:
5051 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
5052 break;
5053 case 2048:
5054 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
5055 break;
5056 case 4096:
5057 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
5058 break;
5059 default:
5060 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
5061 }
5062
5063 return bd_size_type;
5064 }
5065
hns3_init_ring_hw(struct hns3_enet_ring * ring)5066 static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
5067 {
5068 dma_addr_t dma = ring->desc_dma_addr;
5069 struct hnae3_queue *q = ring->tqp;
5070
5071 if (!HNAE3_IS_TX_RING(ring)) {
5072 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
5073 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
5074 (u32)((dma >> 31) >> 1));
5075
5076 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
5077 hns3_buf_size2type(ring->buf_size));
5078 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
5079 ring->desc_num / 8 - 1);
5080 } else {
5081 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
5082 (u32)dma);
5083 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
5084 (u32)((dma >> 31) >> 1));
5085
5086 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
5087 ring->desc_num / 8 - 1);
5088 }
5089 }
5090
hns3_init_tx_ring_tc(struct hns3_nic_priv * priv)5091 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
5092 {
5093 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
5094 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
5095 int i;
5096
5097 for (i = 0; i < tc_info->num_tc; i++) {
5098 int j;
5099
5100 for (j = 0; j < tc_info->tqp_count[i]; j++) {
5101 struct hnae3_queue *q;
5102
5103 q = priv->ring[tc_info->tqp_offset[i] + j].tqp;
5104 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i);
5105 }
5106 }
5107 }
5108
hns3_init_all_ring(struct hns3_nic_priv * priv)5109 int hns3_init_all_ring(struct hns3_nic_priv *priv)
5110 {
5111 struct hnae3_handle *h = priv->ae_handle;
5112 int ring_num = h->kinfo.num_tqps * 2;
5113 int i, j;
5114 int ret;
5115
5116 for (i = 0; i < ring_num; i++) {
5117 ret = hns3_alloc_ring_memory(&priv->ring[i]);
5118 if (ret) {
5119 dev_err(priv->dev,
5120 "Alloc ring memory fail! ret=%d\n", ret);
5121 goto out_when_alloc_ring_memory;
5122 }
5123
5124 u64_stats_init(&priv->ring[i].syncp);
5125 cond_resched();
5126 }
5127
5128 return 0;
5129
5130 out_when_alloc_ring_memory:
5131 for (j = i - 1; j >= 0; j--)
5132 hns3_fini_ring(&priv->ring[j]);
5133
5134 return -ENOMEM;
5135 }
5136
hns3_uninit_all_ring(struct hns3_nic_priv * priv)5137 static void hns3_uninit_all_ring(struct hns3_nic_priv *priv)
5138 {
5139 struct hnae3_handle *h = priv->ae_handle;
5140 int i;
5141
5142 for (i = 0; i < h->kinfo.num_tqps; i++) {
5143 hns3_fini_ring(&priv->ring[i]);
5144 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
5145 }
5146 }
5147
5148 /* Set mac addr if it is configured. or leave it to the AE driver */
hns3_init_mac_addr(struct net_device * netdev)5149 static int hns3_init_mac_addr(struct net_device *netdev)
5150 {
5151 struct hns3_nic_priv *priv = netdev_priv(netdev);
5152 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
5153 struct hnae3_handle *h = priv->ae_handle;
5154 u8 mac_addr_temp[ETH_ALEN] = {0};
5155 int ret = 0;
5156
5157 if (h->ae_algo->ops->get_mac_addr)
5158 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
5159
5160 /* Check if the MAC address is valid, if not get a random one */
5161 if (!is_valid_ether_addr(mac_addr_temp)) {
5162 eth_hw_addr_random(netdev);
5163 hnae3_format_mac_addr(format_mac_addr, netdev->dev_addr);
5164 dev_warn(priv->dev, "using random MAC address %s\n",
5165 format_mac_addr);
5166 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) {
5167 eth_hw_addr_set(netdev, mac_addr_temp);
5168 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
5169 } else {
5170 return 0;
5171 }
5172
5173 if (h->ae_algo->ops->set_mac_addr)
5174 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
5175
5176 return ret;
5177 }
5178
hns3_init_phy(struct net_device * netdev)5179 static int hns3_init_phy(struct net_device *netdev)
5180 {
5181 struct hnae3_handle *h = hns3_get_handle(netdev);
5182 int ret = 0;
5183
5184 if (h->ae_algo->ops->mac_connect_phy)
5185 ret = h->ae_algo->ops->mac_connect_phy(h);
5186
5187 return ret;
5188 }
5189
hns3_uninit_phy(struct net_device * netdev)5190 static void hns3_uninit_phy(struct net_device *netdev)
5191 {
5192 struct hnae3_handle *h = hns3_get_handle(netdev);
5193
5194 if (h->ae_algo->ops->mac_disconnect_phy)
5195 h->ae_algo->ops->mac_disconnect_phy(h);
5196 }
5197
hns3_client_start(struct hnae3_handle * handle)5198 static int hns3_client_start(struct hnae3_handle *handle)
5199 {
5200 if (!handle->ae_algo->ops->client_start)
5201 return 0;
5202
5203 return handle->ae_algo->ops->client_start(handle);
5204 }
5205
hns3_client_stop(struct hnae3_handle * handle)5206 static void hns3_client_stop(struct hnae3_handle *handle)
5207 {
5208 if (!handle->ae_algo->ops->client_stop)
5209 return;
5210
5211 handle->ae_algo->ops->client_stop(handle);
5212 }
5213
hns3_info_show(struct hns3_nic_priv * priv)5214 static void hns3_info_show(struct hns3_nic_priv *priv)
5215 {
5216 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
5217 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
5218
5219 hnae3_format_mac_addr(format_mac_addr, priv->netdev->dev_addr);
5220 dev_info(priv->dev, "MAC address: %s\n", format_mac_addr);
5221 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
5222 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
5223 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
5224 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
5225 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
5226 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
5227 dev_info(priv->dev, "Total number of enabled TCs: %u\n",
5228 kinfo->tc_info.num_tc);
5229 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
5230 }
5231
hns3_set_cq_period_mode(struct hns3_nic_priv * priv,enum dim_cq_period_mode mode,bool is_tx)5232 static void hns3_set_cq_period_mode(struct hns3_nic_priv *priv,
5233 enum dim_cq_period_mode mode, bool is_tx)
5234 {
5235 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
5236 struct hnae3_handle *handle = priv->ae_handle;
5237 int i;
5238
5239 if (is_tx) {
5240 priv->tx_cqe_mode = mode;
5241
5242 for (i = 0; i < priv->vector_num; i++)
5243 priv->tqp_vector[i].tx_group.dim.mode = mode;
5244 } else {
5245 priv->rx_cqe_mode = mode;
5246
5247 for (i = 0; i < priv->vector_num; i++)
5248 priv->tqp_vector[i].rx_group.dim.mode = mode;
5249 }
5250
5251 if (hnae3_ae_dev_cq_supported(ae_dev)) {
5252 u32 new_mode;
5253 u64 reg;
5254
5255 new_mode = (mode == DIM_CQ_PERIOD_MODE_START_FROM_CQE) ?
5256 HNS3_CQ_MODE_CQE : HNS3_CQ_MODE_EQE;
5257 reg = is_tx ? HNS3_GL1_CQ_MODE_REG : HNS3_GL0_CQ_MODE_REG;
5258
5259 writel(new_mode, handle->kinfo.io_base + reg);
5260 }
5261 }
5262
hns3_cq_period_mode_init(struct hns3_nic_priv * priv,enum dim_cq_period_mode tx_mode,enum dim_cq_period_mode rx_mode)5263 void hns3_cq_period_mode_init(struct hns3_nic_priv *priv,
5264 enum dim_cq_period_mode tx_mode,
5265 enum dim_cq_period_mode rx_mode)
5266 {
5267 hns3_set_cq_period_mode(priv, tx_mode, true);
5268 hns3_set_cq_period_mode(priv, rx_mode, false);
5269 }
5270
hns3_state_init(struct hnae3_handle * handle)5271 static void hns3_state_init(struct hnae3_handle *handle)
5272 {
5273 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
5274 struct net_device *netdev = handle->kinfo.netdev;
5275 struct hns3_nic_priv *priv = netdev_priv(netdev);
5276
5277 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5278
5279 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps))
5280 set_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state);
5281
5282 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
5283 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags);
5284
5285 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
5286 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state);
5287
5288 if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev))
5289 set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state);
5290 }
5291
hns3_state_uninit(struct hnae3_handle * handle)5292 static void hns3_state_uninit(struct hnae3_handle *handle)
5293 {
5294 struct hns3_nic_priv *priv = handle->priv;
5295
5296 clear_bit(HNS3_NIC_STATE_INITED, &priv->state);
5297 }
5298
hns3_client_init(struct hnae3_handle * handle)5299 static int hns3_client_init(struct hnae3_handle *handle)
5300 {
5301 struct pci_dev *pdev = handle->pdev;
5302 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
5303 u16 alloc_tqps, max_rss_size;
5304 struct hns3_nic_priv *priv;
5305 struct net_device *netdev;
5306 int ret;
5307
5308 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
5309 &max_rss_size);
5310 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
5311 if (!netdev)
5312 return -ENOMEM;
5313
5314 priv = netdev_priv(netdev);
5315 priv->dev = &pdev->dev;
5316 priv->netdev = netdev;
5317 priv->ae_handle = handle;
5318 priv->tx_timeout_count = 0;
5319 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num;
5320 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
5321
5322 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
5323
5324 handle->kinfo.netdev = netdev;
5325 handle->priv = (void *)priv;
5326
5327 hns3_init_mac_addr(netdev);
5328
5329 hns3_set_default_feature(netdev);
5330
5331 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
5332 netdev->priv_flags |= IFF_UNICAST_FLT;
5333 netdev->netdev_ops = &hns3_nic_netdev_ops;
5334 SET_NETDEV_DEV(netdev, &pdev->dev);
5335 hns3_ethtool_set_ops(netdev);
5336
5337 /* Carrier off reporting is important to ethtool even BEFORE open */
5338 netif_carrier_off(netdev);
5339
5340 ret = hns3_get_ring_config(priv);
5341 if (ret) {
5342 ret = -ENOMEM;
5343 goto out_get_ring_cfg;
5344 }
5345
5346 hns3_nic_init_coal_cfg(priv);
5347
5348 ret = hns3_nic_alloc_vector_data(priv);
5349 if (ret) {
5350 ret = -ENOMEM;
5351 goto out_alloc_vector_data;
5352 }
5353
5354 ret = hns3_nic_init_vector_data(priv);
5355 if (ret) {
5356 ret = -ENOMEM;
5357 goto out_init_vector_data;
5358 }
5359
5360 ret = hns3_init_all_ring(priv);
5361 if (ret) {
5362 ret = -ENOMEM;
5363 goto out_init_ring;
5364 }
5365
5366 hns3_cq_period_mode_init(priv, DIM_CQ_PERIOD_MODE_START_FROM_EQE,
5367 DIM_CQ_PERIOD_MODE_START_FROM_EQE);
5368
5369 ret = hns3_init_phy(netdev);
5370 if (ret)
5371 goto out_init_phy;
5372
5373 /* the device can work without cpu rmap, only aRFS needs it */
5374 ret = hns3_set_rx_cpu_rmap(netdev);
5375 if (ret)
5376 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5377
5378 ret = hns3_nic_init_irq(priv);
5379 if (ret) {
5380 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5381 hns3_free_rx_cpu_rmap(netdev);
5382 goto out_init_irq_fail;
5383 }
5384
5385 ret = hns3_client_start(handle);
5386 if (ret) {
5387 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
5388 goto out_client_start;
5389 }
5390
5391 hns3_dcbnl_setup(handle);
5392
5393 ret = hns3_dbg_init(handle);
5394 if (ret) {
5395 dev_err(priv->dev, "failed to init debugfs, ret = %d\n",
5396 ret);
5397 goto out_client_start;
5398 }
5399
5400 netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size);
5401
5402 hns3_state_init(handle);
5403
5404 ret = register_netdev(netdev);
5405 if (ret) {
5406 dev_err(priv->dev, "probe register netdev fail!\n");
5407 goto out_reg_netdev_fail;
5408 }
5409
5410 if (netif_msg_drv(handle))
5411 hns3_info_show(priv);
5412
5413 return ret;
5414
5415 out_reg_netdev_fail:
5416 hns3_state_uninit(handle);
5417 hns3_dbg_uninit(handle);
5418 hns3_client_stop(handle);
5419 out_client_start:
5420 hns3_free_rx_cpu_rmap(netdev);
5421 hns3_nic_uninit_irq(priv);
5422 out_init_irq_fail:
5423 hns3_uninit_phy(netdev);
5424 out_init_phy:
5425 hns3_uninit_all_ring(priv);
5426 out_init_ring:
5427 hns3_nic_uninit_vector_data(priv);
5428 out_init_vector_data:
5429 hns3_nic_dealloc_vector_data(priv);
5430 out_alloc_vector_data:
5431 priv->ring = NULL;
5432 out_get_ring_cfg:
5433 priv->ae_handle = NULL;
5434 free_netdev(netdev);
5435 return ret;
5436 }
5437
hns3_client_uninit(struct hnae3_handle * handle,bool reset)5438 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
5439 {
5440 struct net_device *netdev = handle->kinfo.netdev;
5441 struct hns3_nic_priv *priv = netdev_priv(netdev);
5442
5443 if (netdev->reg_state != NETREG_UNINITIALIZED)
5444 unregister_netdev(netdev);
5445
5446 hns3_client_stop(handle);
5447
5448 hns3_uninit_phy(netdev);
5449
5450 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5451 netdev_warn(netdev, "already uninitialized\n");
5452 goto out_netdev_free;
5453 }
5454
5455 hns3_free_rx_cpu_rmap(netdev);
5456
5457 hns3_nic_uninit_irq(priv);
5458
5459 hns3_clear_all_ring(handle, true);
5460
5461 hns3_nic_uninit_vector_data(priv);
5462
5463 hns3_nic_dealloc_vector_data(priv);
5464
5465 hns3_uninit_all_ring(priv);
5466
5467 hns3_put_ring_config(priv);
5468
5469 out_netdev_free:
5470 hns3_dbg_uninit(handle);
5471 free_netdev(netdev);
5472 }
5473
hns3_link_status_change(struct hnae3_handle * handle,bool linkup)5474 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
5475 {
5476 struct net_device *netdev = handle->kinfo.netdev;
5477
5478 if (!netdev)
5479 return;
5480
5481 if (linkup) {
5482 netif_tx_wake_all_queues(netdev);
5483 netif_carrier_on(netdev);
5484 if (netif_msg_link(handle))
5485 netdev_info(netdev, "link up\n");
5486 } else {
5487 netif_carrier_off(netdev);
5488 netif_tx_stop_all_queues(netdev);
5489 if (netif_msg_link(handle))
5490 netdev_info(netdev, "link down\n");
5491 }
5492 }
5493
hns3_clear_tx_ring(struct hns3_enet_ring * ring)5494 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
5495 {
5496 while (ring->next_to_clean != ring->next_to_use) {
5497 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
5498 hns3_free_buffer_detach(ring, ring->next_to_clean, 0);
5499 ring_ptr_move_fw(ring, next_to_clean);
5500 }
5501
5502 ring->pending_buf = 0;
5503 }
5504
hns3_clear_rx_ring(struct hns3_enet_ring * ring)5505 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
5506 {
5507 struct hns3_desc_cb res_cbs;
5508 int ret;
5509
5510 while (ring->next_to_use != ring->next_to_clean) {
5511 /* When a buffer is not reused, it's memory has been
5512 * freed in hns3_handle_rx_bd or will be freed by
5513 * stack, so we need to replace the buffer here.
5514 */
5515 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5516 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
5517 if (ret) {
5518 hns3_ring_stats_update(ring, sw_err_cnt);
5519 /* if alloc new buffer fail, exit directly
5520 * and reclear in up flow.
5521 */
5522 netdev_warn(ring_to_netdev(ring),
5523 "reserve buffer map failed, ret = %d\n",
5524 ret);
5525 return ret;
5526 }
5527 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
5528 }
5529 ring_ptr_move_fw(ring, next_to_use);
5530 }
5531
5532 /* Free the pending skb in rx ring */
5533 if (ring->skb) {
5534 dev_kfree_skb_any(ring->skb);
5535 ring->skb = NULL;
5536 ring->pending_buf = 0;
5537 }
5538
5539 return 0;
5540 }
5541
hns3_force_clear_rx_ring(struct hns3_enet_ring * ring)5542 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
5543 {
5544 while (ring->next_to_use != ring->next_to_clean) {
5545 /* When a buffer is not reused, it's memory has been
5546 * freed in hns3_handle_rx_bd or will be freed by
5547 * stack, so only need to unmap the buffer here.
5548 */
5549 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5550 hns3_unmap_buffer(ring,
5551 &ring->desc_cb[ring->next_to_use]);
5552 ring->desc_cb[ring->next_to_use].dma = 0;
5553 }
5554
5555 ring_ptr_move_fw(ring, next_to_use);
5556 }
5557 }
5558
hns3_clear_all_ring(struct hnae3_handle * h,bool force)5559 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
5560 {
5561 struct net_device *ndev = h->kinfo.netdev;
5562 struct hns3_nic_priv *priv = netdev_priv(ndev);
5563 u32 i;
5564
5565 for (i = 0; i < h->kinfo.num_tqps; i++) {
5566 struct hns3_enet_ring *ring;
5567
5568 ring = &priv->ring[i];
5569 hns3_clear_tx_ring(ring);
5570
5571 ring = &priv->ring[i + h->kinfo.num_tqps];
5572 /* Continue to clear other rings even if clearing some
5573 * rings failed.
5574 */
5575 if (force)
5576 hns3_force_clear_rx_ring(ring);
5577 else
5578 hns3_clear_rx_ring(ring);
5579 }
5580 }
5581
hns3_nic_reset_all_ring(struct hnae3_handle * h)5582 int hns3_nic_reset_all_ring(struct hnae3_handle *h)
5583 {
5584 struct net_device *ndev = h->kinfo.netdev;
5585 struct hns3_nic_priv *priv = netdev_priv(ndev);
5586 struct hns3_enet_ring *rx_ring;
5587 int i, j;
5588 int ret;
5589
5590 ret = h->ae_algo->ops->reset_queue(h);
5591 if (ret)
5592 return ret;
5593
5594 for (i = 0; i < h->kinfo.num_tqps; i++) {
5595 hns3_init_ring_hw(&priv->ring[i]);
5596
5597 /* We need to clear tx ring here because self test will
5598 * use the ring and will not run down before up
5599 */
5600 hns3_clear_tx_ring(&priv->ring[i]);
5601 priv->ring[i].next_to_clean = 0;
5602 priv->ring[i].next_to_use = 0;
5603 priv->ring[i].last_to_use = 0;
5604
5605 rx_ring = &priv->ring[i + h->kinfo.num_tqps];
5606 hns3_init_ring_hw(rx_ring);
5607 ret = hns3_clear_rx_ring(rx_ring);
5608 if (ret)
5609 return ret;
5610
5611 /* We can not know the hardware head and tail when this
5612 * function is called in reset flow, so we reuse all desc.
5613 */
5614 for (j = 0; j < rx_ring->desc_num; j++)
5615 hns3_reuse_buffer(rx_ring, j);
5616
5617 rx_ring->next_to_clean = 0;
5618 rx_ring->next_to_use = 0;
5619 }
5620
5621 hns3_init_tx_ring_tc(priv);
5622
5623 return 0;
5624 }
5625
hns3_reset_notify_down_enet(struct hnae3_handle * handle)5626 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
5627 {
5628 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5629 struct net_device *ndev = kinfo->netdev;
5630 struct hns3_nic_priv *priv = netdev_priv(ndev);
5631
5632 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
5633 return 0;
5634
5635 if (!netif_running(ndev))
5636 return 0;
5637
5638 return hns3_nic_net_stop(ndev);
5639 }
5640
hns3_reset_notify_up_enet(struct hnae3_handle * handle)5641 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
5642 {
5643 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5644 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
5645 int ret = 0;
5646
5647 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5648 netdev_err(kinfo->netdev, "device is not initialized yet\n");
5649 return -EFAULT;
5650 }
5651
5652 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5653
5654 if (netif_running(kinfo->netdev)) {
5655 ret = hns3_nic_net_open(kinfo->netdev);
5656 if (ret) {
5657 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5658 netdev_err(kinfo->netdev,
5659 "net up fail, ret=%d!\n", ret);
5660 return ret;
5661 }
5662 }
5663
5664 return ret;
5665 }
5666
hns3_reset_notify_init_enet(struct hnae3_handle * handle)5667 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
5668 {
5669 struct net_device *netdev = handle->kinfo.netdev;
5670 struct hns3_nic_priv *priv = netdev_priv(netdev);
5671 int ret;
5672
5673 /* Carrier off reporting is important to ethtool even BEFORE open */
5674 netif_carrier_off(netdev);
5675
5676 ret = hns3_get_ring_config(priv);
5677 if (ret)
5678 return ret;
5679
5680 ret = hns3_nic_alloc_vector_data(priv);
5681 if (ret)
5682 goto err_put_ring;
5683
5684 ret = hns3_nic_init_vector_data(priv);
5685 if (ret)
5686 goto err_dealloc_vector;
5687
5688 ret = hns3_init_all_ring(priv);
5689 if (ret)
5690 goto err_uninit_vector;
5691
5692 hns3_cq_period_mode_init(priv, priv->tx_cqe_mode, priv->rx_cqe_mode);
5693
5694 /* the device can work without cpu rmap, only aRFS needs it */
5695 ret = hns3_set_rx_cpu_rmap(netdev);
5696 if (ret)
5697 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5698
5699 ret = hns3_nic_init_irq(priv);
5700 if (ret) {
5701 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5702 hns3_free_rx_cpu_rmap(netdev);
5703 goto err_init_irq_fail;
5704 }
5705
5706 if (!hns3_is_phys_func(handle->pdev))
5707 hns3_init_mac_addr(netdev);
5708
5709 ret = hns3_client_start(handle);
5710 if (ret) {
5711 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
5712 goto err_client_start_fail;
5713 }
5714
5715 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5716
5717 return ret;
5718
5719 err_client_start_fail:
5720 hns3_free_rx_cpu_rmap(netdev);
5721 hns3_nic_uninit_irq(priv);
5722 err_init_irq_fail:
5723 hns3_uninit_all_ring(priv);
5724 err_uninit_vector:
5725 hns3_nic_uninit_vector_data(priv);
5726 err_dealloc_vector:
5727 hns3_nic_dealloc_vector_data(priv);
5728 err_put_ring:
5729 hns3_put_ring_config(priv);
5730
5731 return ret;
5732 }
5733
hns3_reset_notify_uninit_enet(struct hnae3_handle * handle)5734 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
5735 {
5736 struct net_device *netdev = handle->kinfo.netdev;
5737 struct hns3_nic_priv *priv = netdev_priv(netdev);
5738
5739 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5740 hns3_nic_net_stop(netdev);
5741
5742 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5743 netdev_warn(netdev, "already uninitialized\n");
5744 return 0;
5745 }
5746
5747 hns3_free_rx_cpu_rmap(netdev);
5748 hns3_nic_uninit_irq(priv);
5749 hns3_clear_all_ring(handle, true);
5750 hns3_reset_tx_queue(priv->ae_handle);
5751
5752 hns3_nic_uninit_vector_data(priv);
5753
5754 hns3_nic_dealloc_vector_data(priv);
5755
5756 hns3_uninit_all_ring(priv);
5757
5758 hns3_put_ring_config(priv);
5759
5760 return 0;
5761 }
5762
hns3_reset_notify(struct hnae3_handle * handle,enum hnae3_reset_notify_type type)5763 int hns3_reset_notify(struct hnae3_handle *handle,
5764 enum hnae3_reset_notify_type type)
5765 {
5766 int ret = 0;
5767
5768 switch (type) {
5769 case HNAE3_UP_CLIENT:
5770 ret = hns3_reset_notify_up_enet(handle);
5771 break;
5772 case HNAE3_DOWN_CLIENT:
5773 ret = hns3_reset_notify_down_enet(handle);
5774 break;
5775 case HNAE3_INIT_CLIENT:
5776 ret = hns3_reset_notify_init_enet(handle);
5777 break;
5778 case HNAE3_UNINIT_CLIENT:
5779 ret = hns3_reset_notify_uninit_enet(handle);
5780 break;
5781 default:
5782 break;
5783 }
5784
5785 return ret;
5786 }
5787
hns3_change_channels(struct hnae3_handle * handle,u32 new_tqp_num,bool rxfh_configured)5788 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
5789 bool rxfh_configured)
5790 {
5791 int ret;
5792
5793 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
5794 rxfh_configured);
5795 if (ret) {
5796 dev_err(&handle->pdev->dev,
5797 "Change tqp num(%u) fail.\n", new_tqp_num);
5798 return ret;
5799 }
5800
5801 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
5802 if (ret)
5803 return ret;
5804
5805 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT);
5806 if (ret)
5807 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
5808
5809 return ret;
5810 }
5811
hns3_set_channels(struct net_device * netdev,struct ethtool_channels * ch)5812 int hns3_set_channels(struct net_device *netdev,
5813 struct ethtool_channels *ch)
5814 {
5815 struct hnae3_handle *h = hns3_get_handle(netdev);
5816 struct hnae3_knic_private_info *kinfo = &h->kinfo;
5817 bool rxfh_configured = netif_is_rxfh_configured(netdev);
5818 u32 new_tqp_num = ch->combined_count;
5819 u16 org_tqp_num;
5820 int ret;
5821
5822 if (hns3_nic_resetting(netdev))
5823 return -EBUSY;
5824
5825 if (ch->rx_count || ch->tx_count)
5826 return -EINVAL;
5827
5828 if (kinfo->tc_info.mqprio_active) {
5829 dev_err(&netdev->dev,
5830 "it's not allowed to set channels via ethtool when MQPRIO mode is on\n");
5831 return -EINVAL;
5832 }
5833
5834 if (new_tqp_num > hns3_get_max_available_channels(h) ||
5835 new_tqp_num < 1) {
5836 dev_err(&netdev->dev,
5837 "Change tqps fail, the tqp range is from 1 to %u",
5838 hns3_get_max_available_channels(h));
5839 return -EINVAL;
5840 }
5841
5842 if (kinfo->rss_size == new_tqp_num)
5843 return 0;
5844
5845 netif_dbg(h, drv, netdev,
5846 "set channels: tqp_num=%u, rxfh=%d\n",
5847 new_tqp_num, rxfh_configured);
5848
5849 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
5850 if (ret)
5851 return ret;
5852
5853 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
5854 if (ret)
5855 return ret;
5856
5857 org_tqp_num = h->kinfo.num_tqps;
5858 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
5859 if (ret) {
5860 int ret1;
5861
5862 netdev_warn(netdev,
5863 "Change channels fail, revert to old value\n");
5864 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
5865 if (ret1) {
5866 netdev_err(netdev,
5867 "revert to old channel fail\n");
5868 return ret1;
5869 }
5870
5871 return ret;
5872 }
5873
5874 return 0;
5875 }
5876
hns3_external_lb_prepare(struct net_device * ndev,bool if_running)5877 void hns3_external_lb_prepare(struct net_device *ndev, bool if_running)
5878 {
5879 struct hns3_nic_priv *priv = netdev_priv(ndev);
5880
5881 if (!if_running)
5882 return;
5883
5884 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5885 return;
5886
5887 netif_carrier_off(ndev);
5888 netif_tx_disable(ndev);
5889
5890 hns3_disable_irqs_and_tqps(ndev);
5891
5892 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
5893 * during reset process, because driver may not be able
5894 * to disable the ring through firmware when downing the netdev.
5895 */
5896 if (!hns3_nic_resetting(ndev))
5897 hns3_nic_reset_all_ring(priv->ae_handle);
5898
5899 hns3_reset_tx_queue(priv->ae_handle);
5900 }
5901
hns3_external_lb_restore(struct net_device * ndev,bool if_running)5902 void hns3_external_lb_restore(struct net_device *ndev, bool if_running)
5903 {
5904 struct hns3_nic_priv *priv = netdev_priv(ndev);
5905 struct hnae3_handle *h = priv->ae_handle;
5906
5907 if (!if_running)
5908 return;
5909
5910 if (hns3_nic_resetting(ndev))
5911 return;
5912
5913 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5914 return;
5915
5916 if (hns3_nic_reset_all_ring(priv->ae_handle))
5917 return;
5918
5919 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
5920
5921 hns3_enable_irqs_and_tqps(ndev);
5922
5923 netif_tx_wake_all_queues(ndev);
5924
5925 if (h->ae_algo->ops->get_status(h))
5926 netif_carrier_on(ndev);
5927 }
5928
5929 static const struct hns3_hw_error_info hns3_hw_err[] = {
5930 { .type = HNAE3_PPU_POISON_ERROR,
5931 .msg = "PPU poison" },
5932 { .type = HNAE3_CMDQ_ECC_ERROR,
5933 .msg = "IMP CMDQ error" },
5934 { .type = HNAE3_IMP_RD_POISON_ERROR,
5935 .msg = "IMP RD poison" },
5936 { .type = HNAE3_ROCEE_AXI_RESP_ERROR,
5937 .msg = "ROCEE AXI RESP error" },
5938 };
5939
hns3_process_hw_error(struct hnae3_handle * handle,enum hnae3_hw_error_type type)5940 static void hns3_process_hw_error(struct hnae3_handle *handle,
5941 enum hnae3_hw_error_type type)
5942 {
5943 int i;
5944
5945 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
5946 if (hns3_hw_err[i].type == type) {
5947 dev_err(&handle->pdev->dev, "Detected %s!\n",
5948 hns3_hw_err[i].msg);
5949 break;
5950 }
5951 }
5952 }
5953
5954 static const struct hnae3_client_ops client_ops = {
5955 .init_instance = hns3_client_init,
5956 .uninit_instance = hns3_client_uninit,
5957 .link_status_change = hns3_link_status_change,
5958 .reset_notify = hns3_reset_notify,
5959 .process_hw_error = hns3_process_hw_error,
5960 };
5961
5962 /* hns3_init_module - Driver registration routine
5963 * hns3_init_module is the first routine called when the driver is
5964 * loaded. All it does is register with the PCI subsystem.
5965 */
hns3_init_module(void)5966 static int __init hns3_init_module(void)
5967 {
5968 int ret;
5969
5970 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
5971 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
5972
5973 client.type = HNAE3_CLIENT_KNIC;
5974 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s",
5975 hns3_driver_name);
5976
5977 client.ops = &client_ops;
5978
5979 INIT_LIST_HEAD(&client.node);
5980
5981 hns3_dbg_register_debugfs(hns3_driver_name);
5982
5983 ret = hnae3_register_client(&client);
5984 if (ret)
5985 goto err_reg_client;
5986
5987 ret = pci_register_driver(&hns3_driver);
5988 if (ret)
5989 goto err_reg_driver;
5990
5991 return ret;
5992
5993 err_reg_driver:
5994 hnae3_unregister_client(&client);
5995 err_reg_client:
5996 hns3_dbg_unregister_debugfs();
5997 return ret;
5998 }
5999 module_init(hns3_init_module);
6000
6001 /* hns3_exit_module - Driver exit cleanup routine
6002 * hns3_exit_module is called just before the driver is removed
6003 * from memory.
6004 */
hns3_exit_module(void)6005 static void __exit hns3_exit_module(void)
6006 {
6007 hnae3_acquire_unload_lock();
6008 pci_unregister_driver(&hns3_driver);
6009 hnae3_unregister_client(&client);
6010 hns3_dbg_unregister_debugfs();
6011 hnae3_release_unload_lock();
6012 }
6013 module_exit(hns3_exit_module);
6014
6015 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
6016 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6017 MODULE_LICENSE("GPL");
6018 MODULE_ALIAS("pci:hns-nic");
6019