1 /*
2 * RISC-V APLIC (Advanced Platform Level Interrupt Controller)
3 *
4 * Copyright (c) 2021 Western Digital Corporation or its affiliates.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include "qemu/osdep.h"
20 #include "qapi/error.h"
21 #include "qemu/log.h"
22 #include "qemu/module.h"
23 #include "qemu/error-report.h"
24 #include "qemu/bswap.h"
25 #include "exec/address-spaces.h"
26 #include "hw/sysbus.h"
27 #include "hw/pci/msi.h"
28 #include "hw/boards.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/intc/riscv_aplic.h"
31 #include "hw/irq.h"
32 #include "target/riscv/cpu.h"
33 #include "sysemu/sysemu.h"
34 #include "sysemu/kvm.h"
35 #include "kvm/kvm_riscv.h"
36 #include "migration/vmstate.h"
37
38 #define APLIC_MAX_IDC (1UL << 14)
39 #define APLIC_MAX_SOURCE 1024
40 #define APLIC_MIN_IPRIO_BITS 1
41 #define APLIC_MAX_IPRIO_BITS 8
42 #define APLIC_MAX_CHILDREN 1024
43
44 #define APLIC_DOMAINCFG 0x0000
45 #define APLIC_DOMAINCFG_RDONLY 0x80000000
46 #define APLIC_DOMAINCFG_IE (1 << 8)
47 #define APLIC_DOMAINCFG_DM (1 << 2)
48 #define APLIC_DOMAINCFG_BE (1 << 0)
49
50 #define APLIC_SOURCECFG_BASE 0x0004
51 #define APLIC_SOURCECFG_D (1 << 10)
52 #define APLIC_SOURCECFG_CHILDIDX_MASK 0x000003ff
53 #define APLIC_SOURCECFG_SM_MASK 0x00000007
54 #define APLIC_SOURCECFG_SM_INACTIVE 0x0
55 #define APLIC_SOURCECFG_SM_DETACH 0x1
56 #define APLIC_SOURCECFG_SM_EDGE_RISE 0x4
57 #define APLIC_SOURCECFG_SM_EDGE_FALL 0x5
58 #define APLIC_SOURCECFG_SM_LEVEL_HIGH 0x6
59 #define APLIC_SOURCECFG_SM_LEVEL_LOW 0x7
60
61 #define APLIC_MMSICFGADDR 0x1bc0
62 #define APLIC_MMSICFGADDRH 0x1bc4
63 #define APLIC_SMSICFGADDR 0x1bc8
64 #define APLIC_SMSICFGADDRH 0x1bcc
65
66 #define APLIC_xMSICFGADDRH_L (1UL << 31)
67 #define APLIC_xMSICFGADDRH_HHXS_MASK 0x1f
68 #define APLIC_xMSICFGADDRH_HHXS_SHIFT 24
69 #define APLIC_xMSICFGADDRH_LHXS_MASK 0x7
70 #define APLIC_xMSICFGADDRH_LHXS_SHIFT 20
71 #define APLIC_xMSICFGADDRH_HHXW_MASK 0x7
72 #define APLIC_xMSICFGADDRH_HHXW_SHIFT 16
73 #define APLIC_xMSICFGADDRH_LHXW_MASK 0xf
74 #define APLIC_xMSICFGADDRH_LHXW_SHIFT 12
75 #define APLIC_xMSICFGADDRH_BAPPN_MASK 0xfff
76
77 #define APLIC_xMSICFGADDR_PPN_SHIFT 12
78
79 #define APLIC_xMSICFGADDR_PPN_HART(__lhxs) \
80 ((1UL << (__lhxs)) - 1)
81
82 #define APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) \
83 ((1UL << (__lhxw)) - 1)
84 #define APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs) \
85 ((__lhxs))
86 #define APLIC_xMSICFGADDR_PPN_LHX(__lhxw, __lhxs) \
87 (APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) << \
88 APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs))
89
90 #define APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) \
91 ((1UL << (__hhxw)) - 1)
92 #define APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs) \
93 ((__hhxs) + APLIC_xMSICFGADDR_PPN_SHIFT)
94 #define APLIC_xMSICFGADDR_PPN_HHX(__hhxw, __hhxs) \
95 (APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) << \
96 APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs))
97
98 #define APLIC_xMSICFGADDRH_VALID_MASK \
99 (APLIC_xMSICFGADDRH_L | \
100 (APLIC_xMSICFGADDRH_HHXS_MASK << APLIC_xMSICFGADDRH_HHXS_SHIFT) | \
101 (APLIC_xMSICFGADDRH_LHXS_MASK << APLIC_xMSICFGADDRH_LHXS_SHIFT) | \
102 (APLIC_xMSICFGADDRH_HHXW_MASK << APLIC_xMSICFGADDRH_HHXW_SHIFT) | \
103 (APLIC_xMSICFGADDRH_LHXW_MASK << APLIC_xMSICFGADDRH_LHXW_SHIFT) | \
104 APLIC_xMSICFGADDRH_BAPPN_MASK)
105
106 #define APLIC_SETIP_BASE 0x1c00
107 #define APLIC_SETIPNUM 0x1cdc
108
109 #define APLIC_CLRIP_BASE 0x1d00
110 #define APLIC_CLRIPNUM 0x1ddc
111
112 #define APLIC_SETIE_BASE 0x1e00
113 #define APLIC_SETIENUM 0x1edc
114
115 #define APLIC_CLRIE_BASE 0x1f00
116 #define APLIC_CLRIENUM 0x1fdc
117
118 #define APLIC_SETIPNUM_LE 0x2000
119 #define APLIC_SETIPNUM_BE 0x2004
120
121 #define APLIC_ISTATE_PENDING (1U << 0)
122 #define APLIC_ISTATE_ENABLED (1U << 1)
123 #define APLIC_ISTATE_ENPEND (APLIC_ISTATE_ENABLED | \
124 APLIC_ISTATE_PENDING)
125 #define APLIC_ISTATE_INPUT (1U << 8)
126
127 #define APLIC_GENMSI 0x3000
128
129 #define APLIC_TARGET_BASE 0x3004
130 #define APLIC_TARGET_HART_IDX_SHIFT 18
131 #define APLIC_TARGET_HART_IDX_MASK 0x3fff
132 #define APLIC_TARGET_GUEST_IDX_SHIFT 12
133 #define APLIC_TARGET_GUEST_IDX_MASK 0x3f
134 #define APLIC_TARGET_IPRIO_MASK 0xff
135 #define APLIC_TARGET_EIID_MASK 0x7ff
136
137 #define APLIC_IDC_BASE 0x4000
138 #define APLIC_IDC_SIZE 32
139
140 #define APLIC_IDC_IDELIVERY 0x00
141
142 #define APLIC_IDC_IFORCE 0x04
143
144 #define APLIC_IDC_ITHRESHOLD 0x08
145
146 #define APLIC_IDC_TOPI 0x18
147 #define APLIC_IDC_TOPI_ID_SHIFT 16
148 #define APLIC_IDC_TOPI_ID_MASK 0x3ff
149 #define APLIC_IDC_TOPI_PRIO_MASK 0xff
150
151 #define APLIC_IDC_CLAIMI 0x1c
152
153 /*
154 * KVM AIA only supports APLIC MSI, fallback to QEMU emulation if we want to use
155 * APLIC Wired.
156 */
is_kvm_aia(bool msimode)157 static bool is_kvm_aia(bool msimode)
158 {
159 return kvm_irqchip_in_kernel() && msimode;
160 }
161
riscv_aplic_irq_rectified_val(RISCVAPLICState * aplic,uint32_t irq)162 static bool riscv_aplic_irq_rectified_val(RISCVAPLICState *aplic,
163 uint32_t irq)
164 {
165 uint32_t sourcecfg, sm, raw_input, irq_inverted;
166
167 if (!irq || aplic->num_irqs <= irq) {
168 return false;
169 }
170
171 sourcecfg = aplic->sourcecfg[irq];
172 if (sourcecfg & APLIC_SOURCECFG_D) {
173 return false;
174 }
175
176 sm = sourcecfg & APLIC_SOURCECFG_SM_MASK;
177 if (sm == APLIC_SOURCECFG_SM_INACTIVE) {
178 return false;
179 }
180
181 raw_input = (aplic->state[irq] & APLIC_ISTATE_INPUT) ? 1 : 0;
182 irq_inverted = (sm == APLIC_SOURCECFG_SM_LEVEL_LOW ||
183 sm == APLIC_SOURCECFG_SM_EDGE_FALL) ? 1 : 0;
184
185 return !!(raw_input ^ irq_inverted);
186 }
187
riscv_aplic_read_input_word(RISCVAPLICState * aplic,uint32_t word)188 static uint32_t riscv_aplic_read_input_word(RISCVAPLICState *aplic,
189 uint32_t word)
190 {
191 uint32_t i, irq, rectified_val, ret = 0;
192
193 for (i = 0; i < 32; i++) {
194 irq = word * 32 + i;
195
196 rectified_val = riscv_aplic_irq_rectified_val(aplic, irq);
197 ret |= rectified_val << i;
198 }
199
200 return ret;
201 }
202
riscv_aplic_read_pending_word(RISCVAPLICState * aplic,uint32_t word)203 static uint32_t riscv_aplic_read_pending_word(RISCVAPLICState *aplic,
204 uint32_t word)
205 {
206 uint32_t i, irq, ret = 0;
207
208 for (i = 0; i < 32; i++) {
209 irq = word * 32 + i;
210 if (!irq || aplic->num_irqs <= irq) {
211 continue;
212 }
213
214 ret |= ((aplic->state[irq] & APLIC_ISTATE_PENDING) ? 1 : 0) << i;
215 }
216
217 return ret;
218 }
219
riscv_aplic_set_pending_raw(RISCVAPLICState * aplic,uint32_t irq,bool pending)220 static void riscv_aplic_set_pending_raw(RISCVAPLICState *aplic,
221 uint32_t irq, bool pending)
222 {
223 if (pending) {
224 aplic->state[irq] |= APLIC_ISTATE_PENDING;
225 } else {
226 aplic->state[irq] &= ~APLIC_ISTATE_PENDING;
227 }
228 }
229
riscv_aplic_set_pending(RISCVAPLICState * aplic,uint32_t irq,bool pending)230 static void riscv_aplic_set_pending(RISCVAPLICState *aplic,
231 uint32_t irq, bool pending)
232 {
233 uint32_t sourcecfg, sm;
234
235 if ((irq <= 0) || (aplic->num_irqs <= irq)) {
236 return;
237 }
238
239 sourcecfg = aplic->sourcecfg[irq];
240 if (sourcecfg & APLIC_SOURCECFG_D) {
241 return;
242 }
243
244 sm = sourcecfg & APLIC_SOURCECFG_SM_MASK;
245 if (sm == APLIC_SOURCECFG_SM_INACTIVE) {
246 return;
247 }
248
249 if ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) ||
250 (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) {
251 if (!aplic->msimode) {
252 return;
253 }
254 if (aplic->msimode && !pending) {
255 goto noskip_write_pending;
256 }
257 if ((aplic->state[irq] & APLIC_ISTATE_INPUT) &&
258 (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) {
259 return;
260 }
261 if (!(aplic->state[irq] & APLIC_ISTATE_INPUT) &&
262 (sm == APLIC_SOURCECFG_SM_LEVEL_HIGH)) {
263 return;
264 }
265 }
266
267 noskip_write_pending:
268 riscv_aplic_set_pending_raw(aplic, irq, pending);
269 }
270
riscv_aplic_set_pending_word(RISCVAPLICState * aplic,uint32_t word,uint32_t value,bool pending)271 static void riscv_aplic_set_pending_word(RISCVAPLICState *aplic,
272 uint32_t word, uint32_t value,
273 bool pending)
274 {
275 uint32_t i, irq;
276
277 for (i = 0; i < 32; i++) {
278 irq = word * 32 + i;
279 if (!irq || aplic->num_irqs <= irq) {
280 continue;
281 }
282
283 if (value & (1U << i)) {
284 riscv_aplic_set_pending(aplic, irq, pending);
285 }
286 }
287 }
288
riscv_aplic_read_enabled_word(RISCVAPLICState * aplic,int word)289 static uint32_t riscv_aplic_read_enabled_word(RISCVAPLICState *aplic,
290 int word)
291 {
292 uint32_t i, irq, ret = 0;
293
294 for (i = 0; i < 32; i++) {
295 irq = word * 32 + i;
296 if (!irq || aplic->num_irqs <= irq) {
297 continue;
298 }
299
300 ret |= ((aplic->state[irq] & APLIC_ISTATE_ENABLED) ? 1 : 0) << i;
301 }
302
303 return ret;
304 }
305
riscv_aplic_set_enabled_raw(RISCVAPLICState * aplic,uint32_t irq,bool enabled)306 static void riscv_aplic_set_enabled_raw(RISCVAPLICState *aplic,
307 uint32_t irq, bool enabled)
308 {
309 if (enabled) {
310 aplic->state[irq] |= APLIC_ISTATE_ENABLED;
311 } else {
312 aplic->state[irq] &= ~APLIC_ISTATE_ENABLED;
313 }
314 }
315
riscv_aplic_set_enabled(RISCVAPLICState * aplic,uint32_t irq,bool enabled)316 static void riscv_aplic_set_enabled(RISCVAPLICState *aplic,
317 uint32_t irq, bool enabled)
318 {
319 uint32_t sourcecfg, sm;
320
321 if ((irq <= 0) || (aplic->num_irqs <= irq)) {
322 return;
323 }
324
325 sourcecfg = aplic->sourcecfg[irq];
326 if (sourcecfg & APLIC_SOURCECFG_D) {
327 return;
328 }
329
330 sm = sourcecfg & APLIC_SOURCECFG_SM_MASK;
331 if (sm == APLIC_SOURCECFG_SM_INACTIVE) {
332 return;
333 }
334
335 riscv_aplic_set_enabled_raw(aplic, irq, enabled);
336 }
337
riscv_aplic_set_enabled_word(RISCVAPLICState * aplic,uint32_t word,uint32_t value,bool enabled)338 static void riscv_aplic_set_enabled_word(RISCVAPLICState *aplic,
339 uint32_t word, uint32_t value,
340 bool enabled)
341 {
342 uint32_t i, irq;
343
344 for (i = 0; i < 32; i++) {
345 irq = word * 32 + i;
346 if (!irq || aplic->num_irqs <= irq) {
347 continue;
348 }
349
350 if (value & (1U << i)) {
351 riscv_aplic_set_enabled(aplic, irq, enabled);
352 }
353 }
354 }
355
riscv_aplic_msi_send(RISCVAPLICState * aplic,uint32_t hart_idx,uint32_t guest_idx,uint32_t eiid)356 static void riscv_aplic_msi_send(RISCVAPLICState *aplic,
357 uint32_t hart_idx, uint32_t guest_idx,
358 uint32_t eiid)
359 {
360 uint64_t addr;
361 MemTxResult result;
362 RISCVAPLICState *aplic_m;
363 uint32_t lhxs, lhxw, hhxs, hhxw, group_idx, msicfgaddr, msicfgaddrH;
364
365 aplic_m = aplic;
366 while (aplic_m && !aplic_m->mmode) {
367 aplic_m = aplic_m->parent;
368 }
369 if (!aplic_m) {
370 qemu_log_mask(LOG_GUEST_ERROR, "%s: m-level APLIC not found\n",
371 __func__);
372 return;
373 }
374
375 if (aplic->mmode) {
376 msicfgaddr = aplic_m->mmsicfgaddr;
377 msicfgaddrH = aplic_m->mmsicfgaddrH;
378 } else {
379 msicfgaddr = aplic_m->smsicfgaddr;
380 msicfgaddrH = aplic_m->smsicfgaddrH;
381 }
382
383 lhxs = (msicfgaddrH >> APLIC_xMSICFGADDRH_LHXS_SHIFT) &
384 APLIC_xMSICFGADDRH_LHXS_MASK;
385 lhxw = (msicfgaddrH >> APLIC_xMSICFGADDRH_LHXW_SHIFT) &
386 APLIC_xMSICFGADDRH_LHXW_MASK;
387 hhxs = (msicfgaddrH >> APLIC_xMSICFGADDRH_HHXS_SHIFT) &
388 APLIC_xMSICFGADDRH_HHXS_MASK;
389 hhxw = (msicfgaddrH >> APLIC_xMSICFGADDRH_HHXW_SHIFT) &
390 APLIC_xMSICFGADDRH_HHXW_MASK;
391
392 group_idx = hart_idx >> lhxw;
393 hart_idx &= APLIC_xMSICFGADDR_PPN_LHX_MASK(lhxw);
394
395 addr = msicfgaddr;
396 addr |= ((uint64_t)(msicfgaddrH & APLIC_xMSICFGADDRH_BAPPN_MASK)) << 32;
397 addr |= ((uint64_t)(group_idx & APLIC_xMSICFGADDR_PPN_HHX_MASK(hhxw))) <<
398 APLIC_xMSICFGADDR_PPN_HHX_SHIFT(hhxs);
399 addr |= ((uint64_t)(hart_idx & APLIC_xMSICFGADDR_PPN_LHX_MASK(lhxw))) <<
400 APLIC_xMSICFGADDR_PPN_LHX_SHIFT(lhxs);
401 addr |= (uint64_t)(guest_idx & APLIC_xMSICFGADDR_PPN_HART(lhxs));
402 addr <<= APLIC_xMSICFGADDR_PPN_SHIFT;
403
404 address_space_stl_le(&address_space_memory, addr,
405 eiid, MEMTXATTRS_UNSPECIFIED, &result);
406 if (result != MEMTX_OK) {
407 qemu_log_mask(LOG_GUEST_ERROR, "%s: MSI write failed for "
408 "hart_index=%d guest_index=%d eiid=%d\n",
409 __func__, hart_idx, guest_idx, eiid);
410 }
411 }
412
riscv_aplic_msi_irq_update(RISCVAPLICState * aplic,uint32_t irq)413 static void riscv_aplic_msi_irq_update(RISCVAPLICState *aplic, uint32_t irq)
414 {
415 uint32_t hart_idx, guest_idx, eiid;
416
417 if (!aplic->msimode || (aplic->num_irqs <= irq) ||
418 !(aplic->domaincfg & APLIC_DOMAINCFG_IE)) {
419 return;
420 }
421
422 if ((aplic->state[irq] & APLIC_ISTATE_ENPEND) != APLIC_ISTATE_ENPEND) {
423 return;
424 }
425
426 riscv_aplic_set_pending_raw(aplic, irq, false);
427
428 hart_idx = aplic->target[irq] >> APLIC_TARGET_HART_IDX_SHIFT;
429 hart_idx &= APLIC_TARGET_HART_IDX_MASK;
430 if (aplic->mmode) {
431 /* M-level APLIC ignores guest_index */
432 guest_idx = 0;
433 } else {
434 guest_idx = aplic->target[irq] >> APLIC_TARGET_GUEST_IDX_SHIFT;
435 guest_idx &= APLIC_TARGET_GUEST_IDX_MASK;
436 }
437 eiid = aplic->target[irq] & APLIC_TARGET_EIID_MASK;
438 riscv_aplic_msi_send(aplic, hart_idx, guest_idx, eiid);
439 }
440
riscv_aplic_idc_topi(RISCVAPLICState * aplic,uint32_t idc)441 static uint32_t riscv_aplic_idc_topi(RISCVAPLICState *aplic, uint32_t idc)
442 {
443 uint32_t best_irq, best_iprio;
444 uint32_t irq, iprio, ihartidx, ithres;
445
446 if (aplic->num_harts <= idc) {
447 return 0;
448 }
449
450 ithres = aplic->ithreshold[idc];
451 best_irq = best_iprio = UINT32_MAX;
452 for (irq = 1; irq < aplic->num_irqs; irq++) {
453 if ((aplic->state[irq] & APLIC_ISTATE_ENPEND) !=
454 APLIC_ISTATE_ENPEND) {
455 continue;
456 }
457
458 ihartidx = aplic->target[irq] >> APLIC_TARGET_HART_IDX_SHIFT;
459 ihartidx &= APLIC_TARGET_HART_IDX_MASK;
460 if (ihartidx != idc) {
461 continue;
462 }
463
464 iprio = aplic->target[irq] & aplic->iprio_mask;
465 if (ithres && iprio >= ithres) {
466 continue;
467 }
468
469 if (iprio < best_iprio) {
470 best_irq = irq;
471 best_iprio = iprio;
472 }
473 }
474
475 if (best_irq < aplic->num_irqs && best_iprio <= aplic->iprio_mask) {
476 return (best_irq << APLIC_IDC_TOPI_ID_SHIFT) | best_iprio;
477 }
478
479 return 0;
480 }
481
riscv_aplic_idc_update(RISCVAPLICState * aplic,uint32_t idc)482 static void riscv_aplic_idc_update(RISCVAPLICState *aplic, uint32_t idc)
483 {
484 uint32_t topi;
485
486 if (aplic->msimode || aplic->num_harts <= idc) {
487 return;
488 }
489
490 topi = riscv_aplic_idc_topi(aplic, idc);
491 if ((aplic->domaincfg & APLIC_DOMAINCFG_IE) &&
492 aplic->idelivery[idc] &&
493 (aplic->iforce[idc] || topi)) {
494 qemu_irq_raise(aplic->external_irqs[idc]);
495 } else {
496 qemu_irq_lower(aplic->external_irqs[idc]);
497 }
498 }
499
riscv_aplic_idc_claimi(RISCVAPLICState * aplic,uint32_t idc)500 static uint32_t riscv_aplic_idc_claimi(RISCVAPLICState *aplic, uint32_t idc)
501 {
502 uint32_t irq, state, sm, topi = riscv_aplic_idc_topi(aplic, idc);
503
504 if (!topi) {
505 aplic->iforce[idc] = 0;
506 riscv_aplic_idc_update(aplic, idc);
507 return 0;
508 }
509
510 irq = (topi >> APLIC_IDC_TOPI_ID_SHIFT) & APLIC_IDC_TOPI_ID_MASK;
511 sm = aplic->sourcecfg[irq] & APLIC_SOURCECFG_SM_MASK;
512 state = aplic->state[irq];
513 riscv_aplic_set_pending_raw(aplic, irq, false);
514 if ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) &&
515 (state & APLIC_ISTATE_INPUT)) {
516 riscv_aplic_set_pending_raw(aplic, irq, true);
517 } else if ((sm == APLIC_SOURCECFG_SM_LEVEL_LOW) &&
518 !(state & APLIC_ISTATE_INPUT)) {
519 riscv_aplic_set_pending_raw(aplic, irq, true);
520 }
521 riscv_aplic_idc_update(aplic, idc);
522
523 return topi;
524 }
525
riscv_aplic_request(void * opaque,int irq,int level)526 static void riscv_aplic_request(void *opaque, int irq, int level)
527 {
528 bool update = false;
529 RISCVAPLICState *aplic = opaque;
530 uint32_t sourcecfg, childidx, state, idc;
531
532 assert((0 < irq) && (irq < aplic->num_irqs));
533
534 sourcecfg = aplic->sourcecfg[irq];
535 if (sourcecfg & APLIC_SOURCECFG_D) {
536 childidx = sourcecfg & APLIC_SOURCECFG_CHILDIDX_MASK;
537 if (childidx < aplic->num_children) {
538 riscv_aplic_request(aplic->children[childidx], irq, level);
539 }
540 return;
541 }
542
543 state = aplic->state[irq];
544 switch (sourcecfg & APLIC_SOURCECFG_SM_MASK) {
545 case APLIC_SOURCECFG_SM_EDGE_RISE:
546 if ((level > 0) && !(state & APLIC_ISTATE_INPUT) &&
547 !(state & APLIC_ISTATE_PENDING)) {
548 riscv_aplic_set_pending_raw(aplic, irq, true);
549 update = true;
550 }
551 break;
552 case APLIC_SOURCECFG_SM_EDGE_FALL:
553 if ((level <= 0) && (state & APLIC_ISTATE_INPUT) &&
554 !(state & APLIC_ISTATE_PENDING)) {
555 riscv_aplic_set_pending_raw(aplic, irq, true);
556 update = true;
557 }
558 break;
559 case APLIC_SOURCECFG_SM_LEVEL_HIGH:
560 if ((level > 0) && !(state & APLIC_ISTATE_PENDING)) {
561 riscv_aplic_set_pending_raw(aplic, irq, true);
562 update = true;
563 }
564 break;
565 case APLIC_SOURCECFG_SM_LEVEL_LOW:
566 if ((level <= 0) && !(state & APLIC_ISTATE_PENDING)) {
567 riscv_aplic_set_pending_raw(aplic, irq, true);
568 update = true;
569 }
570 break;
571 default:
572 break;
573 }
574
575 if (level <= 0) {
576 aplic->state[irq] &= ~APLIC_ISTATE_INPUT;
577 } else {
578 aplic->state[irq] |= APLIC_ISTATE_INPUT;
579 }
580
581 if (update) {
582 if (aplic->msimode) {
583 riscv_aplic_msi_irq_update(aplic, irq);
584 } else {
585 idc = aplic->target[irq] >> APLIC_TARGET_HART_IDX_SHIFT;
586 idc &= APLIC_TARGET_HART_IDX_MASK;
587 riscv_aplic_idc_update(aplic, idc);
588 }
589 }
590 }
591
riscv_aplic_read(void * opaque,hwaddr addr,unsigned size)592 static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size)
593 {
594 uint32_t irq, word, idc;
595 RISCVAPLICState *aplic = opaque;
596
597 /* Reads must be 4 byte words */
598 if ((addr & 0x3) != 0) {
599 goto err;
600 }
601
602 if (addr == APLIC_DOMAINCFG) {
603 return APLIC_DOMAINCFG_RDONLY | aplic->domaincfg |
604 (aplic->msimode ? APLIC_DOMAINCFG_DM : 0);
605 } else if ((APLIC_SOURCECFG_BASE <= addr) &&
606 (addr < (APLIC_SOURCECFG_BASE + (aplic->num_irqs - 1) * 4))) {
607 irq = ((addr - APLIC_SOURCECFG_BASE) >> 2) + 1;
608 return aplic->sourcecfg[irq];
609 } else if (aplic->mmode && aplic->msimode &&
610 (addr == APLIC_MMSICFGADDR)) {
611 return aplic->mmsicfgaddr;
612 } else if (aplic->mmode && aplic->msimode &&
613 (addr == APLIC_MMSICFGADDRH)) {
614 return aplic->mmsicfgaddrH;
615 } else if (aplic->mmode && aplic->msimode &&
616 (addr == APLIC_SMSICFGADDR)) {
617 /*
618 * Registers SMSICFGADDR and SMSICFGADDRH are implemented only if:
619 * (a) the interrupt domain is at machine level
620 * (b) the domain's harts implement supervisor mode
621 * (c) the domain has one or more child supervisor-level domains
622 * that support MSI delivery mode (domaincfg.DM is not read-
623 * only zero in at least one of the supervisor-level child
624 * domains).
625 */
626 return (aplic->num_children) ? aplic->smsicfgaddr : 0;
627 } else if (aplic->mmode && aplic->msimode &&
628 (addr == APLIC_SMSICFGADDRH)) {
629 return (aplic->num_children) ? aplic->smsicfgaddrH : 0;
630 } else if ((APLIC_SETIP_BASE <= addr) &&
631 (addr < (APLIC_SETIP_BASE + aplic->bitfield_words * 4))) {
632 word = (addr - APLIC_SETIP_BASE) >> 2;
633 return riscv_aplic_read_pending_word(aplic, word);
634 } else if (addr == APLIC_SETIPNUM) {
635 return 0;
636 } else if ((APLIC_CLRIP_BASE <= addr) &&
637 (addr < (APLIC_CLRIP_BASE + aplic->bitfield_words * 4))) {
638 word = (addr - APLIC_CLRIP_BASE) >> 2;
639 return riscv_aplic_read_input_word(aplic, word);
640 } else if (addr == APLIC_CLRIPNUM) {
641 return 0;
642 } else if ((APLIC_SETIE_BASE <= addr) &&
643 (addr < (APLIC_SETIE_BASE + aplic->bitfield_words * 4))) {
644 word = (addr - APLIC_SETIE_BASE) >> 2;
645 return riscv_aplic_read_enabled_word(aplic, word);
646 } else if (addr == APLIC_SETIENUM) {
647 return 0;
648 } else if ((APLIC_CLRIE_BASE <= addr) &&
649 (addr < (APLIC_CLRIE_BASE + aplic->bitfield_words * 4))) {
650 return 0;
651 } else if (addr == APLIC_CLRIENUM) {
652 return 0;
653 } else if (addr == APLIC_SETIPNUM_LE) {
654 return 0;
655 } else if (addr == APLIC_SETIPNUM_BE) {
656 return 0;
657 } else if (addr == APLIC_GENMSI) {
658 return (aplic->msimode) ? aplic->genmsi : 0;
659 } else if ((APLIC_TARGET_BASE <= addr) &&
660 (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) {
661 irq = ((addr - APLIC_TARGET_BASE) >> 2) + 1;
662 return aplic->target[irq];
663 } else if (!aplic->msimode && (APLIC_IDC_BASE <= addr) &&
664 (addr < (APLIC_IDC_BASE + aplic->num_harts * APLIC_IDC_SIZE))) {
665 idc = (addr - APLIC_IDC_BASE) / APLIC_IDC_SIZE;
666 switch (addr - (APLIC_IDC_BASE + idc * APLIC_IDC_SIZE)) {
667 case APLIC_IDC_IDELIVERY:
668 return aplic->idelivery[idc];
669 case APLIC_IDC_IFORCE:
670 return aplic->iforce[idc];
671 case APLIC_IDC_ITHRESHOLD:
672 return aplic->ithreshold[idc];
673 case APLIC_IDC_TOPI:
674 return riscv_aplic_idc_topi(aplic, idc);
675 case APLIC_IDC_CLAIMI:
676 return riscv_aplic_idc_claimi(aplic, idc);
677 default:
678 goto err;
679 };
680 }
681
682 err:
683 qemu_log_mask(LOG_GUEST_ERROR,
684 "%s: Invalid register read 0x%" HWADDR_PRIx "\n",
685 __func__, addr);
686 return 0;
687 }
688
riscv_aplic_write(void * opaque,hwaddr addr,uint64_t value,unsigned size)689 static void riscv_aplic_write(void *opaque, hwaddr addr, uint64_t value,
690 unsigned size)
691 {
692 RISCVAPLICState *aplic = opaque;
693 uint32_t irq, word, idc = UINT32_MAX;
694
695 /* Writes must be 4 byte words */
696 if ((addr & 0x3) != 0) {
697 goto err;
698 }
699
700 if (addr == APLIC_DOMAINCFG) {
701 /* Only IE bit writable at the moment */
702 value &= APLIC_DOMAINCFG_IE;
703 aplic->domaincfg = value;
704 } else if ((APLIC_SOURCECFG_BASE <= addr) &&
705 (addr < (APLIC_SOURCECFG_BASE + (aplic->num_irqs - 1) * 4))) {
706 irq = ((addr - APLIC_SOURCECFG_BASE) >> 2) + 1;
707 if (!aplic->num_children && (value & APLIC_SOURCECFG_D)) {
708 value = 0;
709 }
710 if (value & APLIC_SOURCECFG_D) {
711 value &= (APLIC_SOURCECFG_D | APLIC_SOURCECFG_CHILDIDX_MASK);
712 } else {
713 value &= (APLIC_SOURCECFG_D | APLIC_SOURCECFG_SM_MASK);
714 }
715 aplic->sourcecfg[irq] = value;
716 if ((aplic->sourcecfg[irq] & APLIC_SOURCECFG_D) ||
717 (aplic->sourcecfg[irq] == 0)) {
718 riscv_aplic_set_pending_raw(aplic, irq, false);
719 riscv_aplic_set_enabled_raw(aplic, irq, false);
720 } else {
721 if (riscv_aplic_irq_rectified_val(aplic, irq)) {
722 riscv_aplic_set_pending_raw(aplic, irq, true);
723 }
724 }
725 } else if (aplic->mmode && aplic->msimode &&
726 (addr == APLIC_MMSICFGADDR)) {
727 if (!(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
728 aplic->mmsicfgaddr = value;
729 }
730 } else if (aplic->mmode && aplic->msimode &&
731 (addr == APLIC_MMSICFGADDRH)) {
732 if (!(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
733 aplic->mmsicfgaddrH = value & APLIC_xMSICFGADDRH_VALID_MASK;
734 }
735 } else if (aplic->mmode && aplic->msimode &&
736 (addr == APLIC_SMSICFGADDR)) {
737 /*
738 * Registers SMSICFGADDR and SMSICFGADDRH are implemented only if:
739 * (a) the interrupt domain is at machine level
740 * (b) the domain's harts implement supervisor mode
741 * (c) the domain has one or more child supervisor-level domains
742 * that support MSI delivery mode (domaincfg.DM is not read-
743 * only zero in at least one of the supervisor-level child
744 * domains).
745 */
746 if (aplic->num_children &&
747 !(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
748 aplic->smsicfgaddr = value;
749 }
750 } else if (aplic->mmode && aplic->msimode &&
751 (addr == APLIC_SMSICFGADDRH)) {
752 if (aplic->num_children &&
753 !(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
754 aplic->smsicfgaddrH = value & APLIC_xMSICFGADDRH_VALID_MASK;
755 }
756 } else if ((APLIC_SETIP_BASE <= addr) &&
757 (addr < (APLIC_SETIP_BASE + aplic->bitfield_words * 4))) {
758 word = (addr - APLIC_SETIP_BASE) >> 2;
759 riscv_aplic_set_pending_word(aplic, word, value, true);
760 } else if (addr == APLIC_SETIPNUM) {
761 riscv_aplic_set_pending(aplic, value, true);
762 } else if ((APLIC_CLRIP_BASE <= addr) &&
763 (addr < (APLIC_CLRIP_BASE + aplic->bitfield_words * 4))) {
764 word = (addr - APLIC_CLRIP_BASE) >> 2;
765 riscv_aplic_set_pending_word(aplic, word, value, false);
766 } else if (addr == APLIC_CLRIPNUM) {
767 riscv_aplic_set_pending(aplic, value, false);
768 } else if ((APLIC_SETIE_BASE <= addr) &&
769 (addr < (APLIC_SETIE_BASE + aplic->bitfield_words * 4))) {
770 word = (addr - APLIC_SETIE_BASE) >> 2;
771 riscv_aplic_set_enabled_word(aplic, word, value, true);
772 } else if (addr == APLIC_SETIENUM) {
773 riscv_aplic_set_enabled(aplic, value, true);
774 } else if ((APLIC_CLRIE_BASE <= addr) &&
775 (addr < (APLIC_CLRIE_BASE + aplic->bitfield_words * 4))) {
776 word = (addr - APLIC_CLRIE_BASE) >> 2;
777 riscv_aplic_set_enabled_word(aplic, word, value, false);
778 } else if (addr == APLIC_CLRIENUM) {
779 riscv_aplic_set_enabled(aplic, value, false);
780 } else if (addr == APLIC_SETIPNUM_LE) {
781 riscv_aplic_set_pending(aplic, value, true);
782 } else if (addr == APLIC_SETIPNUM_BE) {
783 riscv_aplic_set_pending(aplic, bswap32(value), true);
784 } else if (addr == APLIC_GENMSI) {
785 if (aplic->msimode) {
786 aplic->genmsi = value & ~(APLIC_TARGET_GUEST_IDX_MASK <<
787 APLIC_TARGET_GUEST_IDX_SHIFT);
788 riscv_aplic_msi_send(aplic,
789 value >> APLIC_TARGET_HART_IDX_SHIFT,
790 0,
791 value & APLIC_TARGET_EIID_MASK);
792 }
793 } else if ((APLIC_TARGET_BASE <= addr) &&
794 (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) {
795 irq = ((addr - APLIC_TARGET_BASE) >> 2) + 1;
796 if (aplic->msimode) {
797 aplic->target[irq] = value;
798 } else {
799 aplic->target[irq] = (value & ~APLIC_TARGET_IPRIO_MASK) |
800 ((value & aplic->iprio_mask) ?
801 (value & aplic->iprio_mask) : 1);
802 }
803 } else if (!aplic->msimode && (APLIC_IDC_BASE <= addr) &&
804 (addr < (APLIC_IDC_BASE + aplic->num_harts * APLIC_IDC_SIZE))) {
805 idc = (addr - APLIC_IDC_BASE) / APLIC_IDC_SIZE;
806 switch (addr - (APLIC_IDC_BASE + idc * APLIC_IDC_SIZE)) {
807 case APLIC_IDC_IDELIVERY:
808 aplic->idelivery[idc] = value & 0x1;
809 break;
810 case APLIC_IDC_IFORCE:
811 aplic->iforce[idc] = value & 0x1;
812 break;
813 case APLIC_IDC_ITHRESHOLD:
814 aplic->ithreshold[idc] = value & aplic->iprio_mask;
815 break;
816 default:
817 goto err;
818 };
819 } else {
820 goto err;
821 }
822
823 if (aplic->msimode) {
824 for (irq = 1; irq < aplic->num_irqs; irq++) {
825 riscv_aplic_msi_irq_update(aplic, irq);
826 }
827 } else {
828 if (idc == UINT32_MAX) {
829 for (idc = 0; idc < aplic->num_harts; idc++) {
830 riscv_aplic_idc_update(aplic, idc);
831 }
832 } else {
833 riscv_aplic_idc_update(aplic, idc);
834 }
835 }
836
837 return;
838
839 err:
840 qemu_log_mask(LOG_GUEST_ERROR,
841 "%s: Invalid register write 0x%" HWADDR_PRIx "\n",
842 __func__, addr);
843 }
844
845 static const MemoryRegionOps riscv_aplic_ops = {
846 .read = riscv_aplic_read,
847 .write = riscv_aplic_write,
848 .endianness = DEVICE_LITTLE_ENDIAN,
849 .valid = {
850 .min_access_size = 4,
851 .max_access_size = 4
852 }
853 };
854
riscv_aplic_realize(DeviceState * dev,Error ** errp)855 static void riscv_aplic_realize(DeviceState *dev, Error **errp)
856 {
857 uint32_t i;
858 RISCVAPLICState *aplic = RISCV_APLIC(dev);
859
860 if (!is_kvm_aia(aplic->msimode)) {
861 aplic->bitfield_words = (aplic->num_irqs + 31) >> 5;
862 aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs);
863 aplic->state = g_new0(uint32_t, aplic->num_irqs);
864 aplic->target = g_new0(uint32_t, aplic->num_irqs);
865 if (!aplic->msimode) {
866 for (i = 0; i < aplic->num_irqs; i++) {
867 aplic->target[i] = 1;
868 }
869 }
870 aplic->idelivery = g_new0(uint32_t, aplic->num_harts);
871 aplic->iforce = g_new0(uint32_t, aplic->num_harts);
872 aplic->ithreshold = g_new0(uint32_t, aplic->num_harts);
873
874 memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops,
875 aplic, TYPE_RISCV_APLIC, aplic->aperture_size);
876 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio);
877 }
878
879 /*
880 * Only root APLICs have hardware IRQ lines. All non-root APLICs
881 * have IRQ lines delegated by their parent APLIC.
882 */
883 if (!aplic->parent) {
884 if (kvm_enabled() && is_kvm_aia(aplic->msimode)) {
885 qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irqs);
886 } else {
887 qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs);
888 }
889 }
890
891 /* Create output IRQ lines for non-MSI mode */
892 if (!aplic->msimode) {
893 aplic->external_irqs = g_malloc(sizeof(qemu_irq) * aplic->num_harts);
894 qdev_init_gpio_out(dev, aplic->external_irqs, aplic->num_harts);
895
896 /* Claim the CPU interrupt to be triggered by this APLIC */
897 for (i = 0; i < aplic->num_harts; i++) {
898 RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(aplic->hartid_base + i));
899 if (riscv_cpu_claim_interrupts(cpu,
900 (aplic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {
901 error_report("%s already claimed",
902 (aplic->mmode) ? "MEIP" : "SEIP");
903 exit(1);
904 }
905 }
906 }
907
908 msi_nonbroken = true;
909 }
910
911 static Property riscv_aplic_properties[] = {
912 DEFINE_PROP_UINT32("aperture-size", RISCVAPLICState, aperture_size, 0),
913 DEFINE_PROP_UINT32("hartid-base", RISCVAPLICState, hartid_base, 0),
914 DEFINE_PROP_UINT32("num-harts", RISCVAPLICState, num_harts, 0),
915 DEFINE_PROP_UINT32("iprio-mask", RISCVAPLICState, iprio_mask, 0),
916 DEFINE_PROP_UINT32("num-irqs", RISCVAPLICState, num_irqs, 0),
917 DEFINE_PROP_BOOL("msimode", RISCVAPLICState, msimode, 0),
918 DEFINE_PROP_BOOL("mmode", RISCVAPLICState, mmode, 0),
919 DEFINE_PROP_END_OF_LIST(),
920 };
921
922 static const VMStateDescription vmstate_riscv_aplic = {
923 .name = "riscv_aplic",
924 .version_id = 1,
925 .minimum_version_id = 1,
926 .fields = (const VMStateField[]) {
927 VMSTATE_UINT32(domaincfg, RISCVAPLICState),
928 VMSTATE_UINT32(mmsicfgaddr, RISCVAPLICState),
929 VMSTATE_UINT32(mmsicfgaddrH, RISCVAPLICState),
930 VMSTATE_UINT32(smsicfgaddr, RISCVAPLICState),
931 VMSTATE_UINT32(smsicfgaddrH, RISCVAPLICState),
932 VMSTATE_UINT32(genmsi, RISCVAPLICState),
933 VMSTATE_VARRAY_UINT32(sourcecfg, RISCVAPLICState,
934 num_irqs, 0,
935 vmstate_info_uint32, uint32_t),
936 VMSTATE_VARRAY_UINT32(state, RISCVAPLICState,
937 num_irqs, 0,
938 vmstate_info_uint32, uint32_t),
939 VMSTATE_VARRAY_UINT32(target, RISCVAPLICState,
940 num_irqs, 0,
941 vmstate_info_uint32, uint32_t),
942 VMSTATE_VARRAY_UINT32(idelivery, RISCVAPLICState,
943 num_harts, 0,
944 vmstate_info_uint32, uint32_t),
945 VMSTATE_VARRAY_UINT32(iforce, RISCVAPLICState,
946 num_harts, 0,
947 vmstate_info_uint32, uint32_t),
948 VMSTATE_VARRAY_UINT32(ithreshold, RISCVAPLICState,
949 num_harts, 0,
950 vmstate_info_uint32, uint32_t),
951 VMSTATE_END_OF_LIST()
952 }
953 };
954
riscv_aplic_class_init(ObjectClass * klass,void * data)955 static void riscv_aplic_class_init(ObjectClass *klass, void *data)
956 {
957 DeviceClass *dc = DEVICE_CLASS(klass);
958
959 device_class_set_props(dc, riscv_aplic_properties);
960 dc->realize = riscv_aplic_realize;
961 dc->vmsd = &vmstate_riscv_aplic;
962 }
963
964 static const TypeInfo riscv_aplic_info = {
965 .name = TYPE_RISCV_APLIC,
966 .parent = TYPE_SYS_BUS_DEVICE,
967 .instance_size = sizeof(RISCVAPLICState),
968 .class_init = riscv_aplic_class_init,
969 };
970
riscv_aplic_register_types(void)971 static void riscv_aplic_register_types(void)
972 {
973 type_register_static(&riscv_aplic_info);
974 }
975
type_init(riscv_aplic_register_types)976 type_init(riscv_aplic_register_types)
977
978 /*
979 * Add a APLIC device to another APLIC device as child for
980 * interrupt delegation.
981 */
982 void riscv_aplic_add_child(DeviceState *parent, DeviceState *child)
983 {
984 RISCVAPLICState *caplic, *paplic;
985
986 assert(parent && child);
987 caplic = RISCV_APLIC(child);
988 paplic = RISCV_APLIC(parent);
989
990 assert(paplic->num_irqs == caplic->num_irqs);
991 assert(paplic->num_children <= QEMU_APLIC_MAX_CHILDREN);
992
993 caplic->parent = paplic;
994 paplic->children[paplic->num_children] = caplic;
995 paplic->num_children++;
996 }
997
998 /*
999 * Create APLIC device.
1000 */
riscv_aplic_create(hwaddr addr,hwaddr size,uint32_t hartid_base,uint32_t num_harts,uint32_t num_sources,uint32_t iprio_bits,bool msimode,bool mmode,DeviceState * parent)1001 DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
1002 uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
1003 uint32_t iprio_bits, bool msimode, bool mmode, DeviceState *parent)
1004 {
1005 DeviceState *dev = qdev_new(TYPE_RISCV_APLIC);
1006 uint32_t i;
1007
1008 assert(num_harts < APLIC_MAX_IDC);
1009 assert((APLIC_IDC_BASE + (num_harts * APLIC_IDC_SIZE)) <= size);
1010 assert(num_sources < APLIC_MAX_SOURCE);
1011 assert(APLIC_MIN_IPRIO_BITS <= iprio_bits);
1012 assert(iprio_bits <= APLIC_MAX_IPRIO_BITS);
1013
1014 qdev_prop_set_uint32(dev, "aperture-size", size);
1015 qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
1016 qdev_prop_set_uint32(dev, "num-harts", num_harts);
1017 qdev_prop_set_uint32(dev, "iprio-mask", ((1U << iprio_bits) - 1));
1018 qdev_prop_set_uint32(dev, "num-irqs", num_sources + 1);
1019 qdev_prop_set_bit(dev, "msimode", msimode);
1020 qdev_prop_set_bit(dev, "mmode", mmode);
1021
1022 if (parent) {
1023 riscv_aplic_add_child(parent, dev);
1024 }
1025
1026 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1027
1028 if (!is_kvm_aia(msimode)) {
1029 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
1030 }
1031
1032 if (!msimode) {
1033 for (i = 0; i < num_harts; i++) {
1034 CPUState *cpu = cpu_by_arch_id(hartid_base + i);
1035
1036 qdev_connect_gpio_out_named(dev, NULL, i,
1037 qdev_get_gpio_in(DEVICE(cpu),
1038 (mmode) ? IRQ_M_EXT : IRQ_S_EXT));
1039 }
1040 }
1041
1042 return dev;
1043 }
1044