1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/slab.h>
26 #include <linux/module.h>
27
28 #include "amdgpu.h"
29 #include "amdgpu_ucode.h"
30
31 static const struct kicker_device kicker_device_list[] = {
32 {0x744B, 0x00},
33 };
34
amdgpu_ucode_print_common_hdr(const struct common_firmware_header * hdr)35 static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
36 {
37 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
38 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
39 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
40 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
41 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
42 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
43 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
44 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
45 DRM_DEBUG("ucode_array_offset_bytes: %u\n",
46 le32_to_cpu(hdr->ucode_array_offset_bytes));
47 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
48 }
49
amdgpu_ucode_print_mc_hdr(const struct common_firmware_header * hdr)50 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
51 {
52 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
53 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
54
55 DRM_DEBUG("MC\n");
56 amdgpu_ucode_print_common_hdr(hdr);
57
58 if (version_major == 1) {
59 const struct mc_firmware_header_v1_0 *mc_hdr =
60 container_of(hdr, struct mc_firmware_header_v1_0, header);
61
62 DRM_DEBUG("io_debug_size_bytes: %u\n",
63 le32_to_cpu(mc_hdr->io_debug_size_bytes));
64 DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
65 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
66 } else {
67 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
68 }
69 }
70
amdgpu_ucode_print_smc_hdr(const struct common_firmware_header * hdr)71 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
72 {
73 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
74 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
75 const struct smc_firmware_header_v1_0 *v1_0_hdr;
76 const struct smc_firmware_header_v2_0 *v2_0_hdr;
77 const struct smc_firmware_header_v2_1 *v2_1_hdr;
78
79 DRM_DEBUG("SMC\n");
80 amdgpu_ucode_print_common_hdr(hdr);
81
82 if (version_major == 1) {
83 v1_0_hdr = container_of(hdr, struct smc_firmware_header_v1_0, header);
84 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(v1_0_hdr->ucode_start_addr));
85 } else if (version_major == 2) {
86 switch (version_minor) {
87 case 0:
88 v2_0_hdr = container_of(hdr, struct smc_firmware_header_v2_0, v1_0.header);
89 DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_offset_bytes));
90 DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_size_bytes));
91 break;
92 case 1:
93 v2_1_hdr = container_of(hdr, struct smc_firmware_header_v2_1, v1_0.header);
94 DRM_DEBUG("pptable_count: %u\n", le32_to_cpu(v2_1_hdr->pptable_count));
95 DRM_DEBUG("pptable_entry_offset: %u\n", le32_to_cpu(v2_1_hdr->pptable_entry_offset));
96 break;
97 default:
98 break;
99 }
100
101 } else {
102 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
103 }
104 }
105
amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header * hdr)106 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
107 {
108 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
109 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
110
111 DRM_DEBUG("GFX\n");
112 amdgpu_ucode_print_common_hdr(hdr);
113
114 if (version_major == 1) {
115 const struct gfx_firmware_header_v1_0 *gfx_hdr =
116 container_of(hdr, struct gfx_firmware_header_v1_0, header);
117
118 DRM_DEBUG("ucode_feature_version: %u\n",
119 le32_to_cpu(gfx_hdr->ucode_feature_version));
120 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
121 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
122 } else if (version_major == 2) {
123 const struct gfx_firmware_header_v2_0 *gfx_hdr =
124 container_of(hdr, struct gfx_firmware_header_v2_0, header);
125
126 DRM_DEBUG("ucode_feature_version: %u\n",
127 le32_to_cpu(gfx_hdr->ucode_feature_version));
128 } else {
129 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
130 }
131 }
132
amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header * hdr)133 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
134 {
135 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
136 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
137
138 DRM_DEBUG("RLC\n");
139 amdgpu_ucode_print_common_hdr(hdr);
140
141 if (version_major == 1) {
142 const struct rlc_firmware_header_v1_0 *rlc_hdr =
143 container_of(hdr, struct rlc_firmware_header_v1_0, header);
144
145 DRM_DEBUG("ucode_feature_version: %u\n",
146 le32_to_cpu(rlc_hdr->ucode_feature_version));
147 DRM_DEBUG("save_and_restore_offset: %u\n",
148 le32_to_cpu(rlc_hdr->save_and_restore_offset));
149 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
150 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
151 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
152 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
153 DRM_DEBUG("master_pkt_description_offset: %u\n",
154 le32_to_cpu(rlc_hdr->master_pkt_description_offset));
155 } else if (version_major == 2) {
156 const struct rlc_firmware_header_v2_0 *rlc_hdr =
157 container_of(hdr, struct rlc_firmware_header_v2_0, header);
158 const struct rlc_firmware_header_v2_1 *rlc_hdr_v2_1 =
159 container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0);
160 const struct rlc_firmware_header_v2_2 *rlc_hdr_v2_2 =
161 container_of(rlc_hdr_v2_1, struct rlc_firmware_header_v2_2, v2_1);
162 const struct rlc_firmware_header_v2_3 *rlc_hdr_v2_3 =
163 container_of(rlc_hdr_v2_2, struct rlc_firmware_header_v2_3, v2_2);
164 const struct rlc_firmware_header_v2_4 *rlc_hdr_v2_4 =
165 container_of(rlc_hdr_v2_3, struct rlc_firmware_header_v2_4, v2_3);
166
167 switch (version_minor) {
168 case 0:
169 /* rlc_hdr v2_0 */
170 DRM_DEBUG("ucode_feature_version: %u\n",
171 le32_to_cpu(rlc_hdr->ucode_feature_version));
172 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
173 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
174 DRM_DEBUG("save_and_restore_offset: %u\n",
175 le32_to_cpu(rlc_hdr->save_and_restore_offset));
176 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
177 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
178 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
179 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
180 DRM_DEBUG("reg_restore_list_size: %u\n",
181 le32_to_cpu(rlc_hdr->reg_restore_list_size));
182 DRM_DEBUG("reg_list_format_start: %u\n",
183 le32_to_cpu(rlc_hdr->reg_list_format_start));
184 DRM_DEBUG("reg_list_format_separate_start: %u\n",
185 le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
186 DRM_DEBUG("starting_offsets_start: %u\n",
187 le32_to_cpu(rlc_hdr->starting_offsets_start));
188 DRM_DEBUG("reg_list_format_size_bytes: %u\n",
189 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
190 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
191 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
192 DRM_DEBUG("reg_list_size_bytes: %u\n",
193 le32_to_cpu(rlc_hdr->reg_list_size_bytes));
194 DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
195 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
196 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
197 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
198 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
199 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
200 DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
201 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
202 DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n",
203 le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes));
204 break;
205 case 1:
206 /* rlc_hdr v2_1 */
207 DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n",
208 le32_to_cpu(rlc_hdr_v2_1->reg_list_format_direct_reg_list_length));
209 DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n",
210 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_ucode_ver));
211 DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n",
212 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_feature_ver));
213 DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n",
214 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_size_bytes));
215 DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n",
216 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_offset_bytes));
217 DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n",
218 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_ucode_ver));
219 DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n",
220 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_feature_ver));
221 DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n",
222 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_size_bytes));
223 DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n",
224 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_offset_bytes));
225 DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n",
226 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_ucode_ver));
227 DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n",
228 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_feature_ver));
229 DRM_DEBUG("save_restore_list_srm_size_bytes %u\n",
230 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_size_bytes));
231 DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n",
232 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_offset_bytes));
233 break;
234 case 2:
235 /* rlc_hdr v2_2 */
236 DRM_DEBUG("rlc_iram_ucode_size_bytes: %u\n",
237 le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_size_bytes));
238 DRM_DEBUG("rlc_iram_ucode_offset_bytes: %u\n",
239 le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_offset_bytes));
240 DRM_DEBUG("rlc_dram_ucode_size_bytes: %u\n",
241 le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_size_bytes));
242 DRM_DEBUG("rlc_dram_ucode_offset_bytes: %u\n",
243 le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_offset_bytes));
244 break;
245 case 3:
246 /* rlc_hdr v2_3 */
247 DRM_DEBUG("rlcp_ucode_version: %u\n",
248 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_version));
249 DRM_DEBUG("rlcp_ucode_feature_version: %u\n",
250 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_feature_version));
251 DRM_DEBUG("rlcp_ucode_size_bytes: %u\n",
252 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_size_bytes));
253 DRM_DEBUG("rlcp_ucode_offset_bytes: %u\n",
254 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_offset_bytes));
255 DRM_DEBUG("rlcv_ucode_version: %u\n",
256 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_version));
257 DRM_DEBUG("rlcv_ucode_feature_version: %u\n",
258 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_feature_version));
259 DRM_DEBUG("rlcv_ucode_size_bytes: %u\n",
260 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_size_bytes));
261 DRM_DEBUG("rlcv_ucode_offset_bytes: %u\n",
262 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_offset_bytes));
263 break;
264 case 4:
265 /* rlc_hdr v2_4 */
266 DRM_DEBUG("global_tap_delays_ucode_size_bytes :%u\n",
267 le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_size_bytes));
268 DRM_DEBUG("global_tap_delays_ucode_offset_bytes: %u\n",
269 le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_offset_bytes));
270 DRM_DEBUG("se0_tap_delays_ucode_size_bytes :%u\n",
271 le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_size_bytes));
272 DRM_DEBUG("se0_tap_delays_ucode_offset_bytes: %u\n",
273 le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_offset_bytes));
274 DRM_DEBUG("se1_tap_delays_ucode_size_bytes :%u\n",
275 le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_size_bytes));
276 DRM_DEBUG("se1_tap_delays_ucode_offset_bytes: %u\n",
277 le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_offset_bytes));
278 DRM_DEBUG("se2_tap_delays_ucode_size_bytes :%u\n",
279 le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_size_bytes));
280 DRM_DEBUG("se2_tap_delays_ucode_offset_bytes: %u\n",
281 le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_offset_bytes));
282 DRM_DEBUG("se3_tap_delays_ucode_size_bytes :%u\n",
283 le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_size_bytes));
284 DRM_DEBUG("se3_tap_delays_ucode_offset_bytes: %u\n",
285 le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_offset_bytes));
286 break;
287 default:
288 DRM_ERROR("Unknown RLC v2 ucode: v2.%u\n", version_minor);
289 break;
290 }
291 } else {
292 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
293 }
294 }
295
amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header * hdr)296 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
297 {
298 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
299 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
300
301 DRM_DEBUG("SDMA\n");
302 amdgpu_ucode_print_common_hdr(hdr);
303
304 if (version_major == 1) {
305 const struct sdma_firmware_header_v1_0 *sdma_hdr =
306 container_of(hdr, struct sdma_firmware_header_v1_0, header);
307
308 DRM_DEBUG("ucode_feature_version: %u\n",
309 le32_to_cpu(sdma_hdr->ucode_feature_version));
310 DRM_DEBUG("ucode_change_version: %u\n",
311 le32_to_cpu(sdma_hdr->ucode_change_version));
312 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
313 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
314 if (version_minor >= 1) {
315 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr =
316 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);
317 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));
318 }
319 } else if (version_major == 2) {
320 const struct sdma_firmware_header_v2_0 *sdma_hdr =
321 container_of(hdr, struct sdma_firmware_header_v2_0, header);
322
323 DRM_DEBUG("ucode_feature_version: %u\n",
324 le32_to_cpu(sdma_hdr->ucode_feature_version));
325 DRM_DEBUG("ctx_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_offset));
326 DRM_DEBUG("ctx_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_size));
327 DRM_DEBUG("ctl_ucode_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_ucode_offset));
328 DRM_DEBUG("ctl_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_offset));
329 DRM_DEBUG("ctl_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_size));
330 } else {
331 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
332 version_major, version_minor);
333 }
334 }
335
amdgpu_ucode_print_psp_hdr(const struct common_firmware_header * hdr)336 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr)
337 {
338 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
339 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
340 uint32_t fw_index;
341 const struct psp_fw_bin_desc *desc;
342
343 DRM_DEBUG("PSP\n");
344 amdgpu_ucode_print_common_hdr(hdr);
345
346 if (version_major == 1) {
347 const struct psp_firmware_header_v1_0 *psp_hdr =
348 container_of(hdr, struct psp_firmware_header_v1_0, header);
349
350 DRM_DEBUG("ucode_feature_version: %u\n",
351 le32_to_cpu(psp_hdr->sos.fw_version));
352 DRM_DEBUG("sos_offset_bytes: %u\n",
353 le32_to_cpu(psp_hdr->sos.offset_bytes));
354 DRM_DEBUG("sos_size_bytes: %u\n",
355 le32_to_cpu(psp_hdr->sos.size_bytes));
356 if (version_minor == 1) {
357 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
358 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
359 DRM_DEBUG("toc_header_version: %u\n",
360 le32_to_cpu(psp_hdr_v1_1->toc.fw_version));
361 DRM_DEBUG("toc_offset_bytes: %u\n",
362 le32_to_cpu(psp_hdr_v1_1->toc.offset_bytes));
363 DRM_DEBUG("toc_size_bytes: %u\n",
364 le32_to_cpu(psp_hdr_v1_1->toc.size_bytes));
365 DRM_DEBUG("kdb_header_version: %u\n",
366 le32_to_cpu(psp_hdr_v1_1->kdb.fw_version));
367 DRM_DEBUG("kdb_offset_bytes: %u\n",
368 le32_to_cpu(psp_hdr_v1_1->kdb.offset_bytes));
369 DRM_DEBUG("kdb_size_bytes: %u\n",
370 le32_to_cpu(psp_hdr_v1_1->kdb.size_bytes));
371 }
372 if (version_minor == 2) {
373 const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 =
374 container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0);
375 DRM_DEBUG("kdb_header_version: %u\n",
376 le32_to_cpu(psp_hdr_v1_2->kdb.fw_version));
377 DRM_DEBUG("kdb_offset_bytes: %u\n",
378 le32_to_cpu(psp_hdr_v1_2->kdb.offset_bytes));
379 DRM_DEBUG("kdb_size_bytes: %u\n",
380 le32_to_cpu(psp_hdr_v1_2->kdb.size_bytes));
381 }
382 if (version_minor == 3) {
383 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
384 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
385 const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 =
386 container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1);
387 DRM_DEBUG("toc_header_version: %u\n",
388 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.fw_version));
389 DRM_DEBUG("toc_offset_bytes: %u\n",
390 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.offset_bytes));
391 DRM_DEBUG("toc_size_bytes: %u\n",
392 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.size_bytes));
393 DRM_DEBUG("kdb_header_version: %u\n",
394 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.fw_version));
395 DRM_DEBUG("kdb_offset_bytes: %u\n",
396 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.offset_bytes));
397 DRM_DEBUG("kdb_size_bytes: %u\n",
398 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.size_bytes));
399 DRM_DEBUG("spl_header_version: %u\n",
400 le32_to_cpu(psp_hdr_v1_3->spl.fw_version));
401 DRM_DEBUG("spl_offset_bytes: %u\n",
402 le32_to_cpu(psp_hdr_v1_3->spl.offset_bytes));
403 DRM_DEBUG("spl_size_bytes: %u\n",
404 le32_to_cpu(psp_hdr_v1_3->spl.size_bytes));
405 }
406 } else if (version_major == 2) {
407 const struct psp_firmware_header_v2_0 *psp_hdr_v2_0 =
408 container_of(hdr, struct psp_firmware_header_v2_0, header);
409 for (fw_index = 0; fw_index < le32_to_cpu(psp_hdr_v2_0->psp_fw_bin_count); fw_index++) {
410 desc = &(psp_hdr_v2_0->psp_fw_bin[fw_index]);
411 switch (desc->fw_type) {
412 case PSP_FW_TYPE_PSP_SOS:
413 DRM_DEBUG("psp_sos_version: %u\n",
414 le32_to_cpu(desc->fw_version));
415 DRM_DEBUG("psp_sos_size_bytes: %u\n",
416 le32_to_cpu(desc->size_bytes));
417 break;
418 case PSP_FW_TYPE_PSP_SYS_DRV:
419 DRM_DEBUG("psp_sys_drv_version: %u\n",
420 le32_to_cpu(desc->fw_version));
421 DRM_DEBUG("psp_sys_drv_size_bytes: %u\n",
422 le32_to_cpu(desc->size_bytes));
423 break;
424 case PSP_FW_TYPE_PSP_KDB:
425 DRM_DEBUG("psp_kdb_version: %u\n",
426 le32_to_cpu(desc->fw_version));
427 DRM_DEBUG("psp_kdb_size_bytes: %u\n",
428 le32_to_cpu(desc->size_bytes));
429 break;
430 case PSP_FW_TYPE_PSP_TOC:
431 DRM_DEBUG("psp_toc_version: %u\n",
432 le32_to_cpu(desc->fw_version));
433 DRM_DEBUG("psp_toc_size_bytes: %u\n",
434 le32_to_cpu(desc->size_bytes));
435 break;
436 case PSP_FW_TYPE_PSP_SPL:
437 DRM_DEBUG("psp_spl_version: %u\n",
438 le32_to_cpu(desc->fw_version));
439 DRM_DEBUG("psp_spl_size_bytes: %u\n",
440 le32_to_cpu(desc->size_bytes));
441 break;
442 case PSP_FW_TYPE_PSP_RL:
443 DRM_DEBUG("psp_rl_version: %u\n",
444 le32_to_cpu(desc->fw_version));
445 DRM_DEBUG("psp_rl_size_bytes: %u\n",
446 le32_to_cpu(desc->size_bytes));
447 break;
448 case PSP_FW_TYPE_PSP_SOC_DRV:
449 DRM_DEBUG("psp_soc_drv_version: %u\n",
450 le32_to_cpu(desc->fw_version));
451 DRM_DEBUG("psp_soc_drv_size_bytes: %u\n",
452 le32_to_cpu(desc->size_bytes));
453 break;
454 case PSP_FW_TYPE_PSP_INTF_DRV:
455 DRM_DEBUG("psp_intf_drv_version: %u\n",
456 le32_to_cpu(desc->fw_version));
457 DRM_DEBUG("psp_intf_drv_size_bytes: %u\n",
458 le32_to_cpu(desc->size_bytes));
459 break;
460 case PSP_FW_TYPE_PSP_DBG_DRV:
461 DRM_DEBUG("psp_dbg_drv_version: %u\n",
462 le32_to_cpu(desc->fw_version));
463 DRM_DEBUG("psp_dbg_drv_size_bytes: %u\n",
464 le32_to_cpu(desc->size_bytes));
465 break;
466 case PSP_FW_TYPE_PSP_RAS_DRV:
467 DRM_DEBUG("psp_ras_drv_version: %u\n",
468 le32_to_cpu(desc->fw_version));
469 DRM_DEBUG("psp_ras_drv_size_bytes: %u\n",
470 le32_to_cpu(desc->size_bytes));
471 break;
472 default:
473 DRM_DEBUG("Unsupported PSP fw type: %d\n", desc->fw_type);
474 break;
475 }
476 }
477 } else {
478 DRM_ERROR("Unknown PSP ucode version: %u.%u\n",
479 version_major, version_minor);
480 }
481 }
482
amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header * hdr)483 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr)
484 {
485 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
486 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
487
488 DRM_DEBUG("GPU_INFO\n");
489 amdgpu_ucode_print_common_hdr(hdr);
490
491 if (version_major == 1) {
492 const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr =
493 container_of(hdr, struct gpu_info_firmware_header_v1_0, header);
494
495 DRM_DEBUG("version_major: %u\n",
496 le16_to_cpu(gpu_info_hdr->version_major));
497 DRM_DEBUG("version_minor: %u\n",
498 le16_to_cpu(gpu_info_hdr->version_minor));
499 } else {
500 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor);
501 }
502 }
503
amdgpu_ucode_validate(const struct firmware * fw)504 static int amdgpu_ucode_validate(const struct firmware *fw)
505 {
506 const struct common_firmware_header *hdr =
507 (const struct common_firmware_header *)fw->data;
508
509 if (fw->size == le32_to_cpu(hdr->size_bytes))
510 return 0;
511
512 return -EINVAL;
513 }
514
amdgpu_ucode_hdr_version(union amdgpu_firmware_header * hdr,uint16_t hdr_major,uint16_t hdr_minor)515 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
516 uint16_t hdr_major, uint16_t hdr_minor)
517 {
518 if ((hdr->common.header_version_major == hdr_major) &&
519 (hdr->common.header_version_minor == hdr_minor))
520 return true;
521 return false;
522 }
523
524 enum amdgpu_firmware_load_type
amdgpu_ucode_get_load_type(struct amdgpu_device * adev,int load_type)525 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
526 {
527 switch (adev->asic_type) {
528 #ifdef CONFIG_DRM_AMDGPU_SI
529 case CHIP_TAHITI:
530 case CHIP_PITCAIRN:
531 case CHIP_VERDE:
532 case CHIP_OLAND:
533 case CHIP_HAINAN:
534 return AMDGPU_FW_LOAD_DIRECT;
535 #endif
536 #ifdef CONFIG_DRM_AMDGPU_CIK
537 case CHIP_BONAIRE:
538 case CHIP_KAVERI:
539 case CHIP_KABINI:
540 case CHIP_HAWAII:
541 case CHIP_MULLINS:
542 return AMDGPU_FW_LOAD_DIRECT;
543 #endif
544 case CHIP_TOPAZ:
545 case CHIP_TONGA:
546 case CHIP_FIJI:
547 case CHIP_CARRIZO:
548 case CHIP_STONEY:
549 case CHIP_POLARIS10:
550 case CHIP_POLARIS11:
551 case CHIP_POLARIS12:
552 case CHIP_VEGAM:
553 return AMDGPU_FW_LOAD_SMU;
554 case CHIP_CYAN_SKILLFISH:
555 if (!(load_type &&
556 adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2))
557 return AMDGPU_FW_LOAD_DIRECT;
558 else
559 return AMDGPU_FW_LOAD_PSP;
560 default:
561 if (!load_type)
562 return AMDGPU_FW_LOAD_DIRECT;
563 else
564 return AMDGPU_FW_LOAD_PSP;
565 }
566 }
567
amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id)568 const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id)
569 {
570 switch (ucode_id) {
571 case AMDGPU_UCODE_ID_SDMA0:
572 return "SDMA0";
573 case AMDGPU_UCODE_ID_SDMA1:
574 return "SDMA1";
575 case AMDGPU_UCODE_ID_SDMA2:
576 return "SDMA2";
577 case AMDGPU_UCODE_ID_SDMA3:
578 return "SDMA3";
579 case AMDGPU_UCODE_ID_SDMA4:
580 return "SDMA4";
581 case AMDGPU_UCODE_ID_SDMA5:
582 return "SDMA5";
583 case AMDGPU_UCODE_ID_SDMA6:
584 return "SDMA6";
585 case AMDGPU_UCODE_ID_SDMA7:
586 return "SDMA7";
587 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
588 return "SDMA_CTX";
589 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
590 return "SDMA_CTL";
591 case AMDGPU_UCODE_ID_CP_CE:
592 return "CP_CE";
593 case AMDGPU_UCODE_ID_CP_PFP:
594 return "CP_PFP";
595 case AMDGPU_UCODE_ID_CP_ME:
596 return "CP_ME";
597 case AMDGPU_UCODE_ID_CP_MEC1:
598 return "CP_MEC1";
599 case AMDGPU_UCODE_ID_CP_MEC1_JT:
600 return "CP_MEC1_JT";
601 case AMDGPU_UCODE_ID_CP_MEC2:
602 return "CP_MEC2";
603 case AMDGPU_UCODE_ID_CP_MEC2_JT:
604 return "CP_MEC2_JT";
605 case AMDGPU_UCODE_ID_CP_MES:
606 return "CP_MES";
607 case AMDGPU_UCODE_ID_CP_MES_DATA:
608 return "CP_MES_DATA";
609 case AMDGPU_UCODE_ID_CP_MES1:
610 return "CP_MES_KIQ";
611 case AMDGPU_UCODE_ID_CP_MES1_DATA:
612 return "CP_MES_KIQ_DATA";
613 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
614 return "RLC_RESTORE_LIST_CNTL";
615 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
616 return "RLC_RESTORE_LIST_GPM_MEM";
617 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
618 return "RLC_RESTORE_LIST_SRM_MEM";
619 case AMDGPU_UCODE_ID_RLC_IRAM:
620 return "RLC_IRAM";
621 case AMDGPU_UCODE_ID_RLC_DRAM:
622 return "RLC_DRAM";
623 case AMDGPU_UCODE_ID_RLC_G:
624 return "RLC_G";
625 case AMDGPU_UCODE_ID_RLC_P:
626 return "RLC_P";
627 case AMDGPU_UCODE_ID_RLC_V:
628 return "RLC_V";
629 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
630 return "GLOBAL_TAP_DELAYS";
631 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
632 return "SE0_TAP_DELAYS";
633 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
634 return "SE1_TAP_DELAYS";
635 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
636 return "SE2_TAP_DELAYS";
637 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
638 return "SE3_TAP_DELAYS";
639 case AMDGPU_UCODE_ID_IMU_I:
640 return "IMU_I";
641 case AMDGPU_UCODE_ID_IMU_D:
642 return "IMU_D";
643 case AMDGPU_UCODE_ID_STORAGE:
644 return "STORAGE";
645 case AMDGPU_UCODE_ID_SMC:
646 return "SMC";
647 case AMDGPU_UCODE_ID_PPTABLE:
648 return "PPTABLE";
649 case AMDGPU_UCODE_ID_UVD:
650 return "UVD";
651 case AMDGPU_UCODE_ID_UVD1:
652 return "UVD1";
653 case AMDGPU_UCODE_ID_VCE:
654 return "VCE";
655 case AMDGPU_UCODE_ID_VCN:
656 return "VCN";
657 case AMDGPU_UCODE_ID_VCN1:
658 return "VCN1";
659 case AMDGPU_UCODE_ID_DMCU_ERAM:
660 return "DMCU_ERAM";
661 case AMDGPU_UCODE_ID_DMCU_INTV:
662 return "DMCU_INTV";
663 case AMDGPU_UCODE_ID_VCN0_RAM:
664 return "VCN0_RAM";
665 case AMDGPU_UCODE_ID_VCN1_RAM:
666 return "VCN1_RAM";
667 case AMDGPU_UCODE_ID_DMCUB:
668 return "DMCUB";
669 case AMDGPU_UCODE_ID_CAP:
670 return "CAP";
671 default:
672 return "UNKNOWN UCODE";
673 }
674 }
675
676 #define FW_VERSION_ATTR(name, mode, field) \
677 static ssize_t show_##name(struct device *dev, \
678 struct device_attribute *attr, \
679 char *buf) \
680 { \
681 struct drm_device *ddev = dev_get_drvdata(dev); \
682 struct amdgpu_device *adev = drm_to_adev(ddev); \
683 \
684 return sysfs_emit(buf, "0x%08x\n", adev->field); \
685 } \
686 static DEVICE_ATTR(name, mode, show_##name, NULL)
687
688 FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version);
689 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version);
690 FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version);
691 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
692 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
693 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
694 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
695 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
696 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
697 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
698 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
699 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
700 FW_VERSION_ATTR(imu_fw_version, 0444, gfx.imu_fw_version);
701 FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos.fw_version);
702 FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_context.bin_desc.fw_version);
703 FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ras_context.context.bin_desc.fw_version);
704 FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.xgmi_context.context.bin_desc.fw_version);
705 FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version);
706 FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version);
707 FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version);
708 FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version);
709 FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version);
710 FW_VERSION_ATTR(mes_fw_version, 0444, mes.sched_version & AMDGPU_MES_VERSION_MASK);
711 FW_VERSION_ATTR(mes_kiq_fw_version, 0444, mes.kiq_version & AMDGPU_MES_VERSION_MASK);
712
713 static struct attribute *fw_attrs[] = {
714 &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr,
715 &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr,
716 &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr,
717 &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr,
718 &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr,
719 &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr,
720 &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr,
721 &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr,
722 &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr,
723 &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr,
724 &dev_attr_dmcu_fw_version.attr, &dev_attr_imu_fw_version.attr,
725 &dev_attr_mes_fw_version.attr, &dev_attr_mes_kiq_fw_version.attr,
726 NULL
727 };
728
729 static const struct attribute_group fw_attr_group = {
730 .name = "fw_version",
731 .attrs = fw_attrs
732 };
733
amdgpu_ucode_sysfs_init(struct amdgpu_device * adev)734 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev)
735 {
736 return sysfs_create_group(&adev->dev->kobj, &fw_attr_group);
737 }
738
amdgpu_ucode_sysfs_fini(struct amdgpu_device * adev)739 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev)
740 {
741 sysfs_remove_group(&adev->dev->kobj, &fw_attr_group);
742 }
743
amdgpu_ucode_init_single_fw(struct amdgpu_device * adev,struct amdgpu_firmware_info * ucode,uint64_t mc_addr,void * kptr)744 static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
745 struct amdgpu_firmware_info *ucode,
746 uint64_t mc_addr, void *kptr)
747 {
748 const struct common_firmware_header *header = NULL;
749 const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
750 const struct gfx_firmware_header_v2_0 *cpv2_hdr = NULL;
751 const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL;
752 const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL;
753 const struct mes_firmware_header_v1_0 *mes_hdr = NULL;
754 const struct sdma_firmware_header_v2_0 *sdma_hdr = NULL;
755 const struct imu_firmware_header_v1_0 *imu_hdr = NULL;
756 u8 *ucode_addr;
757
758 if (!ucode->fw)
759 return 0;
760
761 ucode->mc_addr = mc_addr;
762 ucode->kaddr = kptr;
763
764 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE)
765 return 0;
766
767 header = (const struct common_firmware_header *)ucode->fw->data;
768 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
769 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)ucode->fw->data;
770 dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data;
771 dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data;
772 mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data;
773 sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode->fw->data;
774 imu_hdr = (const struct imu_firmware_header_v1_0 *)ucode->fw->data;
775
776 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
777 switch (ucode->ucode_id) {
778 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
779 ucode->ucode_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes);
780 ucode_addr = (u8 *)ucode->fw->data +
781 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes);
782 break;
783 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
784 ucode->ucode_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes);
785 ucode_addr = (u8 *)ucode->fw->data +
786 le32_to_cpu(sdma_hdr->ctl_ucode_offset);
787 break;
788 case AMDGPU_UCODE_ID_CP_MEC1:
789 case AMDGPU_UCODE_ID_CP_MEC2:
790 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
791 le32_to_cpu(cp_hdr->jt_size) * 4;
792 ucode_addr = (u8 *)ucode->fw->data +
793 le32_to_cpu(header->ucode_array_offset_bytes);
794 break;
795 case AMDGPU_UCODE_ID_CP_MEC1_JT:
796 case AMDGPU_UCODE_ID_CP_MEC2_JT:
797 ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;
798 ucode_addr = (u8 *)ucode->fw->data +
799 le32_to_cpu(header->ucode_array_offset_bytes) +
800 le32_to_cpu(cp_hdr->jt_offset) * 4;
801 break;
802 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
803 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
804 ucode_addr = adev->gfx.rlc.save_restore_list_cntl;
805 break;
806 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
807 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes;
808 ucode_addr = adev->gfx.rlc.save_restore_list_gpm;
809 break;
810 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
811 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
812 ucode_addr = adev->gfx.rlc.save_restore_list_srm;
813 break;
814 case AMDGPU_UCODE_ID_RLC_IRAM:
815 ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes;
816 ucode_addr = adev->gfx.rlc.rlc_iram_ucode;
817 break;
818 case AMDGPU_UCODE_ID_RLC_DRAM:
819 ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes;
820 ucode_addr = adev->gfx.rlc.rlc_dram_ucode;
821 break;
822 case AMDGPU_UCODE_ID_RLC_P:
823 ucode->ucode_size = adev->gfx.rlc.rlcp_ucode_size_bytes;
824 ucode_addr = adev->gfx.rlc.rlcp_ucode;
825 break;
826 case AMDGPU_UCODE_ID_RLC_V:
827 ucode->ucode_size = adev->gfx.rlc.rlcv_ucode_size_bytes;
828 ucode_addr = adev->gfx.rlc.rlcv_ucode;
829 break;
830 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
831 ucode->ucode_size = adev->gfx.rlc.global_tap_delays_ucode_size_bytes;
832 ucode_addr = adev->gfx.rlc.global_tap_delays_ucode;
833 break;
834 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
835 ucode->ucode_size = adev->gfx.rlc.se0_tap_delays_ucode_size_bytes;
836 ucode_addr = adev->gfx.rlc.se0_tap_delays_ucode;
837 break;
838 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
839 ucode->ucode_size = adev->gfx.rlc.se1_tap_delays_ucode_size_bytes;
840 ucode_addr = adev->gfx.rlc.se1_tap_delays_ucode;
841 break;
842 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
843 ucode->ucode_size = adev->gfx.rlc.se2_tap_delays_ucode_size_bytes;
844 ucode_addr = adev->gfx.rlc.se2_tap_delays_ucode;
845 break;
846 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
847 ucode->ucode_size = adev->gfx.rlc.se3_tap_delays_ucode_size_bytes;
848 ucode_addr = adev->gfx.rlc.se3_tap_delays_ucode;
849 break;
850 case AMDGPU_UCODE_ID_CP_MES:
851 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
852 ucode_addr = (u8 *)ucode->fw->data +
853 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes);
854 break;
855 case AMDGPU_UCODE_ID_CP_MES_DATA:
856 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
857 ucode_addr = (u8 *)ucode->fw->data +
858 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes);
859 break;
860 case AMDGPU_UCODE_ID_CP_MES1:
861 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
862 ucode_addr = (u8 *)ucode->fw->data +
863 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes);
864 break;
865 case AMDGPU_UCODE_ID_CP_MES1_DATA:
866 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
867 ucode_addr = (u8 *)ucode->fw->data +
868 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes);
869 break;
870 case AMDGPU_UCODE_ID_DMCU_ERAM:
871 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
872 le32_to_cpu(dmcu_hdr->intv_size_bytes);
873 ucode_addr = (u8 *)ucode->fw->data +
874 le32_to_cpu(header->ucode_array_offset_bytes);
875 break;
876 case AMDGPU_UCODE_ID_DMCU_INTV:
877 ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes);
878 ucode_addr = (u8 *)ucode->fw->data +
879 le32_to_cpu(header->ucode_array_offset_bytes) +
880 le32_to_cpu(dmcu_hdr->intv_offset_bytes);
881 break;
882 case AMDGPU_UCODE_ID_DMCUB:
883 ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes);
884 ucode_addr = (u8 *)ucode->fw->data +
885 le32_to_cpu(header->ucode_array_offset_bytes);
886 break;
887 case AMDGPU_UCODE_ID_PPTABLE:
888 ucode->ucode_size = ucode->fw->size;
889 ucode_addr = (u8 *)ucode->fw->data;
890 break;
891 case AMDGPU_UCODE_ID_IMU_I:
892 ucode->ucode_size = le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes);
893 ucode_addr = (u8 *)ucode->fw->data +
894 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes);
895 break;
896 case AMDGPU_UCODE_ID_IMU_D:
897 ucode->ucode_size = le32_to_cpu(imu_hdr->imu_dram_ucode_size_bytes);
898 ucode_addr = (u8 *)ucode->fw->data +
899 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes) +
900 le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes);
901 break;
902 case AMDGPU_UCODE_ID_CP_RS64_PFP:
903 ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
904 ucode_addr = (u8 *)ucode->fw->data +
905 le32_to_cpu(header->ucode_array_offset_bytes);
906 break;
907 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
908 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
909 ucode_addr = (u8 *)ucode->fw->data +
910 le32_to_cpu(cpv2_hdr->data_offset_bytes);
911 break;
912 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
913 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
914 ucode_addr = (u8 *)ucode->fw->data +
915 le32_to_cpu(cpv2_hdr->data_offset_bytes);
916 break;
917 case AMDGPU_UCODE_ID_CP_RS64_ME:
918 ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
919 ucode_addr = (u8 *)ucode->fw->data +
920 le32_to_cpu(header->ucode_array_offset_bytes);
921 break;
922 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
923 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
924 ucode_addr = (u8 *)ucode->fw->data +
925 le32_to_cpu(cpv2_hdr->data_offset_bytes);
926 break;
927 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
928 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
929 ucode_addr = (u8 *)ucode->fw->data +
930 le32_to_cpu(cpv2_hdr->data_offset_bytes);
931 break;
932 case AMDGPU_UCODE_ID_CP_RS64_MEC:
933 ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
934 ucode_addr = (u8 *)ucode->fw->data +
935 le32_to_cpu(header->ucode_array_offset_bytes);
936 break;
937 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
938 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
939 ucode_addr = (u8 *)ucode->fw->data +
940 le32_to_cpu(cpv2_hdr->data_offset_bytes);
941 break;
942 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
943 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
944 ucode_addr = (u8 *)ucode->fw->data +
945 le32_to_cpu(cpv2_hdr->data_offset_bytes);
946 break;
947 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
948 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
949 ucode_addr = (u8 *)ucode->fw->data +
950 le32_to_cpu(cpv2_hdr->data_offset_bytes);
951 break;
952 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
953 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
954 ucode_addr = (u8 *)ucode->fw->data +
955 le32_to_cpu(cpv2_hdr->data_offset_bytes);
956 break;
957 default:
958 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
959 ucode_addr = (u8 *)ucode->fw->data +
960 le32_to_cpu(header->ucode_array_offset_bytes);
961 break;
962 }
963 } else {
964 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
965 ucode_addr = (u8 *)ucode->fw->data +
966 le32_to_cpu(header->ucode_array_offset_bytes);
967 }
968
969 memcpy(ucode->kaddr, ucode_addr, ucode->ucode_size);
970
971 return 0;
972 }
973
amdgpu_ucode_patch_jt(struct amdgpu_firmware_info * ucode,uint64_t mc_addr,void * kptr)974 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
975 uint64_t mc_addr, void *kptr)
976 {
977 const struct gfx_firmware_header_v1_0 *header = NULL;
978 const struct common_firmware_header *comm_hdr = NULL;
979 uint8_t *src_addr = NULL;
980 uint8_t *dst_addr = NULL;
981
982 if (!ucode->fw)
983 return 0;
984
985 comm_hdr = (const struct common_firmware_header *)ucode->fw->data;
986 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
987 dst_addr = ucode->kaddr +
988 ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes),
989 PAGE_SIZE);
990 src_addr = (uint8_t *)ucode->fw->data +
991 le32_to_cpu(comm_hdr->ucode_array_offset_bytes) +
992 (le32_to_cpu(header->jt_offset) * 4);
993 memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
994
995 return 0;
996 }
997
amdgpu_ucode_create_bo(struct amdgpu_device * adev)998 int amdgpu_ucode_create_bo(struct amdgpu_device *adev)
999 {
1000 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {
1001 amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
1002 amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
1003 &adev->firmware.fw_buf,
1004 &adev->firmware.fw_buf_mc,
1005 &adev->firmware.fw_buf_ptr);
1006 if (!adev->firmware.fw_buf) {
1007 dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n");
1008 return -ENOMEM;
1009 } else if (amdgpu_sriov_vf(adev)) {
1010 memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
1011 }
1012 }
1013 return 0;
1014 }
1015
amdgpu_ucode_free_bo(struct amdgpu_device * adev)1016 void amdgpu_ucode_free_bo(struct amdgpu_device *adev)
1017 {
1018 amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
1019 &adev->firmware.fw_buf_mc,
1020 &adev->firmware.fw_buf_ptr);
1021 }
1022
amdgpu_ucode_init_bo(struct amdgpu_device * adev)1023 int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
1024 {
1025 uint64_t fw_offset = 0;
1026 int i;
1027 struct amdgpu_firmware_info *ucode = NULL;
1028
1029 /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */
1030 if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend))
1031 return 0;
1032 /*
1033 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
1034 * ucode info here
1035 */
1036 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1037 if (amdgpu_sriov_vf(adev))
1038 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3;
1039 else
1040 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4;
1041 } else {
1042 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM;
1043 }
1044
1045 for (i = 0; i < adev->firmware.max_ucodes; i++) {
1046 ucode = &adev->firmware.ucode[i];
1047 if (ucode->fw) {
1048 amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
1049 adev->firmware.fw_buf_ptr + fw_offset);
1050 if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
1051 adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1052 const struct gfx_firmware_header_v1_0 *cp_hdr;
1053
1054 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
1055 amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset,
1056 adev->firmware.fw_buf_ptr + fw_offset);
1057 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
1058 }
1059 fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
1060 }
1061 }
1062 return 0;
1063 }
1064
amdgpu_ucode_legacy_naming(struct amdgpu_device * adev,int block_type)1065 static const char *amdgpu_ucode_legacy_naming(struct amdgpu_device *adev, int block_type)
1066 {
1067 if (block_type == MP0_HWIP) {
1068 switch (adev->ip_versions[MP0_HWIP][0]) {
1069 case IP_VERSION(9, 0, 0):
1070 switch (adev->asic_type) {
1071 case CHIP_VEGA10:
1072 return "vega10";
1073 case CHIP_VEGA12:
1074 return "vega12";
1075 default:
1076 return NULL;
1077 }
1078 case IP_VERSION(10, 0, 0):
1079 case IP_VERSION(10, 0, 1):
1080 if (adev->asic_type == CHIP_RAVEN) {
1081 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1082 return "raven2";
1083 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1084 return "picasso";
1085 return "raven";
1086 }
1087 break;
1088 case IP_VERSION(11, 0, 0):
1089 return "navi10";
1090 case IP_VERSION(11, 0, 2):
1091 return "vega20";
1092 case IP_VERSION(11, 0, 3):
1093 return "renoir";
1094 case IP_VERSION(11, 0, 4):
1095 return "arcturus";
1096 case IP_VERSION(11, 0, 5):
1097 return "navi14";
1098 case IP_VERSION(11, 0, 7):
1099 return "sienna_cichlid";
1100 case IP_VERSION(11, 0, 9):
1101 return "navi12";
1102 case IP_VERSION(11, 0, 11):
1103 return "navy_flounder";
1104 case IP_VERSION(11, 0, 12):
1105 return "dimgrey_cavefish";
1106 case IP_VERSION(11, 0, 13):
1107 return "beige_goby";
1108 case IP_VERSION(11, 5, 0):
1109 return "vangogh";
1110 case IP_VERSION(12, 0, 1):
1111 return "green_sardine";
1112 case IP_VERSION(13, 0, 2):
1113 return "aldebaran";
1114 case IP_VERSION(13, 0, 1):
1115 case IP_VERSION(13, 0, 3):
1116 return "yellow_carp";
1117 }
1118 } else if (block_type == MP1_HWIP) {
1119 switch (adev->ip_versions[MP1_HWIP][0]) {
1120 case IP_VERSION(9, 0, 0):
1121 case IP_VERSION(10, 0, 0):
1122 case IP_VERSION(10, 0, 1):
1123 case IP_VERSION(11, 0, 2):
1124 if (adev->asic_type == CHIP_ARCTURUS)
1125 return "arcturus_smc";
1126 return NULL;
1127 case IP_VERSION(11, 0, 0):
1128 return "navi10_smc";
1129 case IP_VERSION(11, 0, 5):
1130 return "navi14_smc";
1131 case IP_VERSION(11, 0, 9):
1132 return "navi12_smc";
1133 case IP_VERSION(11, 0, 7):
1134 return "sienna_cichlid_smc";
1135 case IP_VERSION(11, 0, 11):
1136 return "navy_flounder_smc";
1137 case IP_VERSION(11, 0, 12):
1138 return "dimgrey_cavefish_smc";
1139 case IP_VERSION(11, 0, 13):
1140 return "beige_goby_smc";
1141 case IP_VERSION(13, 0, 2):
1142 return "aldebaran_smc";
1143 }
1144 } else if (block_type == SDMA0_HWIP) {
1145 switch (adev->ip_versions[SDMA0_HWIP][0]) {
1146 case IP_VERSION(4, 0, 0):
1147 return "vega10_sdma";
1148 case IP_VERSION(4, 0, 1):
1149 return "vega12_sdma";
1150 case IP_VERSION(4, 1, 0):
1151 case IP_VERSION(4, 1, 1):
1152 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1153 return "raven2_sdma";
1154 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1155 return "picasso_sdma";
1156 return "raven_sdma";
1157 case IP_VERSION(4, 1, 2):
1158 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1159 return "renoir_sdma";
1160 return "green_sardine_sdma";
1161 case IP_VERSION(4, 2, 0):
1162 return "vega20_sdma";
1163 case IP_VERSION(4, 2, 2):
1164 return "arcturus_sdma";
1165 case IP_VERSION(4, 4, 0):
1166 return "aldebaran_sdma";
1167 case IP_VERSION(5, 0, 0):
1168 return "navi10_sdma";
1169 case IP_VERSION(5, 0, 1):
1170 return "cyan_skillfish2_sdma";
1171 case IP_VERSION(5, 0, 2):
1172 return "navi14_sdma";
1173 case IP_VERSION(5, 0, 5):
1174 return "navi12_sdma";
1175 case IP_VERSION(5, 2, 0):
1176 return "sienna_cichlid_sdma";
1177 case IP_VERSION(5, 2, 2):
1178 return "navy_flounder_sdma";
1179 case IP_VERSION(5, 2, 4):
1180 return "dimgrey_cavefish_sdma";
1181 case IP_VERSION(5, 2, 5):
1182 return "beige_goby_sdma";
1183 case IP_VERSION(5, 2, 3):
1184 return "yellow_carp_sdma";
1185 case IP_VERSION(5, 2, 1):
1186 return "vangogh_sdma";
1187 }
1188 } else if (block_type == UVD_HWIP) {
1189 switch (adev->ip_versions[UVD_HWIP][0]) {
1190 case IP_VERSION(1, 0, 0):
1191 case IP_VERSION(1, 0, 1):
1192 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1193 return "raven2_vcn";
1194 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1195 return "picasso_vcn";
1196 return "raven_vcn";
1197 case IP_VERSION(2, 5, 0):
1198 return "arcturus_vcn";
1199 case IP_VERSION(2, 2, 0):
1200 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1201 return "renoir_vcn";
1202 return "green_sardine_vcn";
1203 case IP_VERSION(2, 6, 0):
1204 return "aldebaran_vcn";
1205 case IP_VERSION(2, 0, 0):
1206 return "navi10_vcn";
1207 case IP_VERSION(2, 0, 2):
1208 if (adev->asic_type == CHIP_NAVI12)
1209 return "navi12_vcn";
1210 return "navi14_vcn";
1211 case IP_VERSION(3, 0, 0):
1212 case IP_VERSION(3, 0, 64):
1213 case IP_VERSION(3, 0, 192):
1214 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
1215 return "sienna_cichlid_vcn";
1216 return "navy_flounder_vcn";
1217 case IP_VERSION(3, 0, 2):
1218 return "vangogh_vcn";
1219 case IP_VERSION(3, 0, 16):
1220 return "dimgrey_cavefish_vcn";
1221 case IP_VERSION(3, 0, 33):
1222 return "beige_goby_vcn";
1223 case IP_VERSION(3, 1, 1):
1224 return "yellow_carp_vcn";
1225 }
1226 } else if (block_type == GC_HWIP) {
1227 switch (adev->ip_versions[GC_HWIP][0]) {
1228 case IP_VERSION(9, 0, 1):
1229 return "vega10";
1230 case IP_VERSION(9, 2, 1):
1231 return "vega12";
1232 case IP_VERSION(9, 4, 0):
1233 return "vega20";
1234 case IP_VERSION(9, 2, 2):
1235 case IP_VERSION(9, 1, 0):
1236 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1237 return "raven2";
1238 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1239 return "picasso";
1240 return "raven";
1241 case IP_VERSION(9, 4, 1):
1242 return "arcturus";
1243 case IP_VERSION(9, 3, 0):
1244 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1245 return "renoir";
1246 return "green_sardine";
1247 case IP_VERSION(9, 4, 2):
1248 return "aldebaran";
1249 case IP_VERSION(10, 1, 10):
1250 return "navi10";
1251 case IP_VERSION(10, 1, 1):
1252 return "navi14";
1253 case IP_VERSION(10, 1, 2):
1254 return "navi12";
1255 case IP_VERSION(10, 3, 0):
1256 return "sienna_cichlid";
1257 case IP_VERSION(10, 3, 2):
1258 return "navy_flounder";
1259 case IP_VERSION(10, 3, 1):
1260 return "vangogh";
1261 case IP_VERSION(10, 3, 4):
1262 return "dimgrey_cavefish";
1263 case IP_VERSION(10, 3, 5):
1264 return "beige_goby";
1265 case IP_VERSION(10, 3, 3):
1266 return "yellow_carp";
1267 case IP_VERSION(10, 1, 3):
1268 case IP_VERSION(10, 1, 4):
1269 return "cyan_skillfish2";
1270 }
1271 }
1272 return NULL;
1273 }
1274
amdgpu_is_kicker_fw(struct amdgpu_device * adev)1275 bool amdgpu_is_kicker_fw(struct amdgpu_device *adev)
1276 {
1277 int i;
1278
1279 for (i = 0; i < ARRAY_SIZE(kicker_device_list); i++) {
1280 if (adev->pdev->device == kicker_device_list[i].device &&
1281 adev->pdev->revision == kicker_device_list[i].revision)
1282 return true;
1283 }
1284
1285 return false;
1286 }
1287
amdgpu_ucode_ip_version_decode(struct amdgpu_device * adev,int block_type,char * ucode_prefix,int len)1288 void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len)
1289 {
1290 int maj, min, rev;
1291 char *ip_name;
1292 const char *legacy;
1293 uint32_t version = adev->ip_versions[block_type][0];
1294
1295 legacy = amdgpu_ucode_legacy_naming(adev, block_type);
1296 if (legacy) {
1297 snprintf(ucode_prefix, len, "%s", legacy);
1298 return;
1299 }
1300
1301 switch (block_type) {
1302 case GC_HWIP:
1303 ip_name = "gc";
1304 break;
1305 case SDMA0_HWIP:
1306 ip_name = "sdma";
1307 break;
1308 case MP0_HWIP:
1309 ip_name = "psp";
1310 break;
1311 case MP1_HWIP:
1312 ip_name = "smu";
1313 break;
1314 case UVD_HWIP:
1315 ip_name = "vcn";
1316 break;
1317 default:
1318 BUG();
1319 }
1320
1321 maj = IP_VERSION_MAJ(version);
1322 min = IP_VERSION_MIN(version);
1323 rev = IP_VERSION_REV(version);
1324
1325 snprintf(ucode_prefix, len, "%s_%d_%d_%d", ip_name, maj, min, rev);
1326 }
1327
1328 /*
1329 * amdgpu_ucode_request - Fetch and validate amdgpu microcode
1330 *
1331 * @adev: amdgpu device
1332 * @fw: pointer to load firmware to
1333 * @fw_name: firmware to load
1334 *
1335 * This is a helper that will use request_firmware and amdgpu_ucode_validate
1336 * to load and run basic validation on firmware. If the load fails, remap
1337 * the error code to -ENODEV, so that early_init functions will fail to load.
1338 */
amdgpu_ucode_request(struct amdgpu_device * adev,const struct firmware ** fw,const char * fw_name)1339 int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw,
1340 const char *fw_name)
1341 {
1342 int err = request_firmware(fw, fw_name, adev->dev);
1343
1344 if (err)
1345 return -ENODEV;
1346
1347 err = amdgpu_ucode_validate(*fw);
1348 if (err) {
1349 dev_dbg(adev->dev, "\"%s\" failed to validate\n", fw_name);
1350 release_firmware(*fw);
1351 *fw = NULL;
1352 }
1353
1354 return err;
1355 }
1356
1357 /*
1358 * amdgpu_ucode_release - Release firmware microcode
1359 *
1360 * @fw: pointer to firmware to release
1361 */
amdgpu_ucode_release(const struct firmware ** fw)1362 void amdgpu_ucode_release(const struct firmware **fw)
1363 {
1364 release_firmware(*fw);
1365 *fw = NULL;
1366 }
1367