1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #include <linux/etherdevice.h>
5 #include <linux/iopoll.h>
6 #include <net/rtnetlink.h>
7 #include "hclgevf_cmd.h"
8 #include "hclgevf_main.h"
9 #include "hclgevf_regs.h"
10 #include "hclge_mbx.h"
11 #include "hnae3.h"
12 #include "hclgevf_devlink.h"
13 #include "hclge_comm_rss.h"
14
15 #define HCLGEVF_NAME "hclgevf"
16
17 #define HCLGEVF_RESET_MAX_FAIL_CNT 5
18
19 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev);
20 static void hclgevf_task_schedule(struct hclgevf_dev *hdev,
21 unsigned long delay);
22
23 static struct hnae3_ae_algo ae_algovf;
24
25 static struct workqueue_struct *hclgevf_wq;
26
27 static const struct pci_device_id ae_algovf_pci_tbl[] = {
28 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
29 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
30 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
31 /* required last entry */
32 {0, }
33 };
34
35 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl);
36
37 /* hclgevf_cmd_send - send command to command queue
38 * @hw: pointer to the hw struct
39 * @desc: prefilled descriptor for describing the command
40 * @num : the number of descriptors to be sent
41 *
42 * This is the main send command for command queue, it
43 * sends the queue, cleans the queue, etc
44 */
hclgevf_cmd_send(struct hclgevf_hw * hw,struct hclge_desc * desc,int num)45 int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num)
46 {
47 return hclge_comm_cmd_send(&hw->hw, desc, num);
48 }
49
hclgevf_arq_init(struct hclgevf_dev * hdev)50 void hclgevf_arq_init(struct hclgevf_dev *hdev)
51 {
52 struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq;
53
54 spin_lock(&cmdq->crq.lock);
55 /* initialize the pointers of async rx queue of mailbox */
56 hdev->arq.hdev = hdev;
57 hdev->arq.head = 0;
58 hdev->arq.tail = 0;
59 atomic_set(&hdev->arq.count, 0);
60 spin_unlock(&cmdq->crq.lock);
61 }
62
hclgevf_ae_get_hdev(struct hnae3_handle * handle)63 struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle)
64 {
65 if (!handle->client)
66 return container_of(handle, struct hclgevf_dev, nic);
67 else if (handle->client->type == HNAE3_CLIENT_ROCE)
68 return container_of(handle, struct hclgevf_dev, roce);
69 else
70 return container_of(handle, struct hclgevf_dev, nic);
71 }
72
hclgevf_update_stats(struct hnae3_handle * handle)73 static void hclgevf_update_stats(struct hnae3_handle *handle)
74 {
75 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
76 int status;
77
78 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw);
79 if (status)
80 dev_err(&hdev->pdev->dev,
81 "VF update of TQPS stats fail, status = %d.\n",
82 status);
83 }
84
hclgevf_get_sset_count(struct hnae3_handle * handle,int strset)85 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset)
86 {
87 if (strset == ETH_SS_TEST)
88 return -EOPNOTSUPP;
89 else if (strset == ETH_SS_STATS)
90 return hclge_comm_tqps_get_sset_count(handle);
91
92 return 0;
93 }
94
hclgevf_get_strings(struct hnae3_handle * handle,u32 strset,u8 * data)95 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset,
96 u8 *data)
97 {
98 u8 *p = (char *)data;
99
100 if (strset == ETH_SS_STATS)
101 p = hclge_comm_tqps_get_strings(handle, p);
102 }
103
hclgevf_get_stats(struct hnae3_handle * handle,u64 * data)104 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data)
105 {
106 hclge_comm_tqps_get_stats(handle, data);
107 }
108
hclgevf_build_send_msg(struct hclge_vf_to_pf_msg * msg,u8 code,u8 subcode)109 static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code,
110 u8 subcode)
111 {
112 if (msg) {
113 memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg));
114 msg->code = code;
115 msg->subcode = subcode;
116 }
117 }
118
hclgevf_get_basic_info(struct hclgevf_dev * hdev)119 static int hclgevf_get_basic_info(struct hclgevf_dev *hdev)
120 {
121 struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
122 u8 resp_msg[HCLGE_MBX_MAX_RESP_DATA_SIZE];
123 struct hclge_basic_info *basic_info;
124 struct hclge_vf_to_pf_msg send_msg;
125 unsigned long caps;
126 int status;
127
128 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_BASIC_INFO, 0);
129 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
130 sizeof(resp_msg));
131 if (status) {
132 dev_err(&hdev->pdev->dev,
133 "failed to get basic info from pf, ret = %d", status);
134 return status;
135 }
136
137 basic_info = (struct hclge_basic_info *)resp_msg;
138
139 hdev->hw_tc_map = basic_info->hw_tc_map;
140 hdev->mbx_api_version = le16_to_cpu(basic_info->mbx_api_version);
141 caps = le32_to_cpu(basic_info->pf_caps);
142 if (test_bit(HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B, &caps))
143 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps);
144
145 return 0;
146 }
147
hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev * hdev)148 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev)
149 {
150 struct hnae3_handle *nic = &hdev->nic;
151 struct hclge_vf_to_pf_msg send_msg;
152 u8 resp_msg;
153 int ret;
154
155 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
156 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE);
157 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg,
158 sizeof(u8));
159 if (ret) {
160 dev_err(&hdev->pdev->dev,
161 "VF request to get port based vlan state failed %d",
162 ret);
163 return ret;
164 }
165
166 nic->port_base_vlan_state = resp_msg;
167
168 return 0;
169 }
170
hclgevf_get_queue_info(struct hclgevf_dev * hdev)171 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev)
172 {
173 #define HCLGEVF_TQPS_RSS_INFO_LEN 6
174
175 struct hclge_mbx_vf_queue_info *queue_info;
176 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN];
177 struct hclge_vf_to_pf_msg send_msg;
178 int status;
179
180 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0);
181 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
182 HCLGEVF_TQPS_RSS_INFO_LEN);
183 if (status) {
184 dev_err(&hdev->pdev->dev,
185 "VF request to get tqp info from PF failed %d",
186 status);
187 return status;
188 }
189
190 queue_info = (struct hclge_mbx_vf_queue_info *)resp_msg;
191 hdev->num_tqps = le16_to_cpu(queue_info->num_tqps);
192 hdev->rss_size_max = le16_to_cpu(queue_info->rss_size);
193 hdev->rx_buf_len = le16_to_cpu(queue_info->rx_buf_len);
194
195 return 0;
196 }
197
hclgevf_get_queue_depth(struct hclgevf_dev * hdev)198 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev)
199 {
200 #define HCLGEVF_TQPS_DEPTH_INFO_LEN 4
201
202 struct hclge_mbx_vf_queue_depth *queue_depth;
203 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN];
204 struct hclge_vf_to_pf_msg send_msg;
205 int ret;
206
207 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0);
208 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
209 HCLGEVF_TQPS_DEPTH_INFO_LEN);
210 if (ret) {
211 dev_err(&hdev->pdev->dev,
212 "VF request to get tqp depth info from PF failed %d",
213 ret);
214 return ret;
215 }
216
217 queue_depth = (struct hclge_mbx_vf_queue_depth *)resp_msg;
218 hdev->num_tx_desc = le16_to_cpu(queue_depth->num_tx_desc);
219 hdev->num_rx_desc = le16_to_cpu(queue_depth->num_rx_desc);
220
221 return 0;
222 }
223
hclgevf_get_qid_global(struct hnae3_handle * handle,u16 queue_id)224 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id)
225 {
226 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
227 struct hclge_vf_to_pf_msg send_msg;
228 u16 qid_in_pf = 0;
229 u8 resp_data[2];
230 int ret;
231
232 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0);
233 *(__le16 *)send_msg.data = cpu_to_le16(queue_id);
234 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data,
235 sizeof(resp_data));
236 if (!ret)
237 qid_in_pf = le16_to_cpu(*(__le16 *)resp_data);
238
239 return qid_in_pf;
240 }
241
hclgevf_get_pf_media_type(struct hclgevf_dev * hdev)242 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev)
243 {
244 struct hclge_vf_to_pf_msg send_msg;
245 u8 resp_msg[2];
246 int ret;
247
248 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0);
249 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
250 sizeof(resp_msg));
251 if (ret) {
252 dev_err(&hdev->pdev->dev,
253 "VF request to get the pf port media type failed %d",
254 ret);
255 return ret;
256 }
257
258 hdev->hw.mac.media_type = resp_msg[0];
259 hdev->hw.mac.module_type = resp_msg[1];
260
261 return 0;
262 }
263
hclgevf_alloc_tqps(struct hclgevf_dev * hdev)264 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev)
265 {
266 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
267 struct hclge_comm_tqp *tqp;
268 int i;
269
270 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
271 sizeof(struct hclge_comm_tqp), GFP_KERNEL);
272 if (!hdev->htqp)
273 return -ENOMEM;
274
275 tqp = hdev->htqp;
276
277 for (i = 0; i < hdev->num_tqps; i++) {
278 tqp->dev = &hdev->pdev->dev;
279 tqp->index = i;
280
281 tqp->q.ae_algo = &ae_algovf;
282 tqp->q.buf_size = hdev->rx_buf_len;
283 tqp->q.tx_desc_num = hdev->num_tx_desc;
284 tqp->q.rx_desc_num = hdev->num_rx_desc;
285
286 /* need an extended offset to configure queues >=
287 * HCLGEVF_TQP_MAX_SIZE_DEV_V2.
288 */
289 if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2)
290 tqp->q.io_base = hdev->hw.hw.io_base +
291 HCLGEVF_TQP_REG_OFFSET +
292 i * HCLGEVF_TQP_REG_SIZE;
293 else
294 tqp->q.io_base = hdev->hw.hw.io_base +
295 HCLGEVF_TQP_REG_OFFSET +
296 HCLGEVF_TQP_EXT_REG_OFFSET +
297 (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) *
298 HCLGEVF_TQP_REG_SIZE;
299
300 /* when device supports tx push and has device memory,
301 * the queue can execute push mode or doorbell mode on
302 * device memory.
303 */
304 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps))
305 tqp->q.mem_base = hdev->hw.hw.mem_base +
306 HCLGEVF_TQP_MEM_OFFSET(hdev, i);
307
308 tqp++;
309 }
310
311 return 0;
312 }
313
hclgevf_knic_setup(struct hclgevf_dev * hdev)314 static int hclgevf_knic_setup(struct hclgevf_dev *hdev)
315 {
316 struct hnae3_handle *nic = &hdev->nic;
317 struct hnae3_knic_private_info *kinfo;
318 u16 new_tqps = hdev->num_tqps;
319 unsigned int i;
320 u8 num_tc = 0;
321
322 kinfo = &nic->kinfo;
323 kinfo->num_tx_desc = hdev->num_tx_desc;
324 kinfo->num_rx_desc = hdev->num_rx_desc;
325 kinfo->rx_buf_len = hdev->rx_buf_len;
326 for (i = 0; i < HCLGE_COMM_MAX_TC_NUM; i++)
327 if (hdev->hw_tc_map & BIT(i))
328 num_tc++;
329
330 num_tc = num_tc ? num_tc : 1;
331 kinfo->tc_info.num_tc = num_tc;
332 kinfo->rss_size = min_t(u16, hdev->rss_size_max, new_tqps / num_tc);
333 new_tqps = kinfo->rss_size * num_tc;
334 kinfo->num_tqps = min(new_tqps, hdev->num_tqps);
335
336 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
337 sizeof(struct hnae3_queue *), GFP_KERNEL);
338 if (!kinfo->tqp)
339 return -ENOMEM;
340
341 for (i = 0; i < kinfo->num_tqps; i++) {
342 hdev->htqp[i].q.handle = &hdev->nic;
343 hdev->htqp[i].q.tqp_index = i;
344 kinfo->tqp[i] = &hdev->htqp[i].q;
345 }
346
347 /* after init the max rss_size and tqps, adjust the default tqp numbers
348 * and rss size with the actual vector numbers
349 */
350 kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps);
351 kinfo->rss_size = min_t(u16, kinfo->num_tqps / num_tc,
352 kinfo->rss_size);
353
354 return 0;
355 }
356
hclgevf_request_link_info(struct hclgevf_dev * hdev)357 static void hclgevf_request_link_info(struct hclgevf_dev *hdev)
358 {
359 struct hclge_vf_to_pf_msg send_msg;
360 int status;
361
362 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0);
363 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
364 if (status)
365 dev_err(&hdev->pdev->dev,
366 "VF failed to fetch link status(%d) from PF", status);
367 }
368
hclgevf_update_link_status(struct hclgevf_dev * hdev,int link_state)369 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state)
370 {
371 struct hnae3_handle *rhandle = &hdev->roce;
372 struct hnae3_handle *handle = &hdev->nic;
373 struct hnae3_client *rclient;
374 struct hnae3_client *client;
375
376 if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state))
377 return;
378
379 client = handle->client;
380 rclient = hdev->roce_client;
381
382 link_state =
383 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state;
384 if (link_state != hdev->hw.mac.link) {
385 hdev->hw.mac.link = link_state;
386 client->ops->link_status_change(handle, !!link_state);
387 if (rclient && rclient->ops->link_status_change)
388 rclient->ops->link_status_change(rhandle, !!link_state);
389 }
390
391 clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state);
392 }
393
hclgevf_update_link_mode(struct hclgevf_dev * hdev)394 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev)
395 {
396 #define HCLGEVF_ADVERTISING 0
397 #define HCLGEVF_SUPPORTED 1
398
399 struct hclge_vf_to_pf_msg send_msg;
400
401 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0);
402 send_msg.data[0] = HCLGEVF_ADVERTISING;
403 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
404 send_msg.data[0] = HCLGEVF_SUPPORTED;
405 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
406 }
407
hclgevf_set_handle_info(struct hclgevf_dev * hdev)408 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev)
409 {
410 struct hnae3_handle *nic = &hdev->nic;
411 int ret;
412
413 nic->ae_algo = &ae_algovf;
414 nic->pdev = hdev->pdev;
415 bitmap_copy(nic->numa_node_mask.bits, hdev->numa_node_mask.bits,
416 MAX_NUMNODES);
417 nic->flags |= HNAE3_SUPPORT_VF;
418 nic->kinfo.io_base = hdev->hw.hw.io_base;
419
420 ret = hclgevf_knic_setup(hdev);
421 if (ret)
422 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n",
423 ret);
424 return ret;
425 }
426
hclgevf_free_vector(struct hclgevf_dev * hdev,int vector_id)427 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id)
428 {
429 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) {
430 dev_warn(&hdev->pdev->dev,
431 "vector(vector_id %d) has been freed.\n", vector_id);
432 return;
433 }
434
435 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT;
436 hdev->num_msi_left += 1;
437 hdev->num_msi_used -= 1;
438 }
439
hclgevf_get_vector(struct hnae3_handle * handle,u16 vector_num,struct hnae3_vector_info * vector_info)440 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num,
441 struct hnae3_vector_info *vector_info)
442 {
443 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
444 struct hnae3_vector_info *vector = vector_info;
445 int alloc = 0;
446 int i, j;
447
448 vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num);
449 vector_num = min(hdev->num_msi_left, vector_num);
450
451 for (j = 0; j < vector_num; j++) {
452 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) {
453 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) {
454 vector->vector = pci_irq_vector(hdev->pdev, i);
455 vector->io_addr = hdev->hw.hw.io_base +
456 HCLGEVF_VECTOR_REG_BASE +
457 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET;
458 hdev->vector_status[i] = 0;
459 hdev->vector_irq[i] = vector->vector;
460
461 vector++;
462 alloc++;
463
464 break;
465 }
466 }
467 }
468 hdev->num_msi_left -= alloc;
469 hdev->num_msi_used += alloc;
470
471 return alloc;
472 }
473
hclgevf_get_vector_index(struct hclgevf_dev * hdev,int vector)474 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector)
475 {
476 int i;
477
478 for (i = 0; i < hdev->num_msi; i++)
479 if (vector == hdev->vector_irq[i])
480 return i;
481
482 return -EINVAL;
483 }
484
485 /* for revision 0x20, vf shared the same rss config with pf */
hclgevf_get_rss_hash_key(struct hclgevf_dev * hdev)486 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev)
487 {
488 #define HCLGEVF_RSS_MBX_RESP_LEN 8
489 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg;
490 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN];
491 struct hclge_vf_to_pf_msg send_msg;
492 u16 msg_num, hash_key_index;
493 u8 index;
494 int ret;
495
496 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0);
497 msg_num = (HCLGE_COMM_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) /
498 HCLGEVF_RSS_MBX_RESP_LEN;
499 for (index = 0; index < msg_num; index++) {
500 send_msg.data[0] = index;
501 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
502 HCLGEVF_RSS_MBX_RESP_LEN);
503 if (ret) {
504 dev_err(&hdev->pdev->dev,
505 "VF get rss hash key from PF failed, ret=%d",
506 ret);
507 return ret;
508 }
509
510 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index;
511 if (index == msg_num - 1)
512 memcpy(&rss_cfg->rss_hash_key[hash_key_index],
513 &resp_msg[0],
514 HCLGE_COMM_RSS_KEY_SIZE - hash_key_index);
515 else
516 memcpy(&rss_cfg->rss_hash_key[hash_key_index],
517 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN);
518 }
519
520 return 0;
521 }
522
hclgevf_get_rss(struct hnae3_handle * handle,u32 * indir,u8 * key,u8 * hfunc)523 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key,
524 u8 *hfunc)
525 {
526 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
527 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg;
528 int ret;
529
530 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
531 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc);
532 } else {
533 if (hfunc)
534 *hfunc = ETH_RSS_HASH_TOP;
535 if (key) {
536 ret = hclgevf_get_rss_hash_key(hdev);
537 if (ret)
538 return ret;
539 memcpy(key, rss_cfg->rss_hash_key,
540 HCLGE_COMM_RSS_KEY_SIZE);
541 }
542 }
543
544 hclge_comm_get_rss_indir_tbl(rss_cfg, indir,
545 hdev->ae_dev->dev_specs.rss_ind_tbl_size);
546
547 return 0;
548 }
549
hclgevf_set_rss(struct hnae3_handle * handle,const u32 * indir,const u8 * key,const u8 hfunc)550 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir,
551 const u8 *key, const u8 hfunc)
552 {
553 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
554 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg;
555 int ret, i;
556
557 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
558 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key,
559 hfunc);
560 if (ret)
561 return ret;
562 }
563
564 /* update the shadow RSS table with user specified qids */
565 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++)
566 rss_cfg->rss_indirection_tbl[i] = indir[i];
567
568 /* update the hardware */
569 return hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw,
570 rss_cfg->rss_indirection_tbl);
571 }
572
hclgevf_set_rss_tuple(struct hnae3_handle * handle,struct ethtool_rxnfc * nfc)573 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle,
574 struct ethtool_rxnfc *nfc)
575 {
576 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
577 int ret;
578
579 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
580 return -EOPNOTSUPP;
581
582 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw,
583 &hdev->rss_cfg, nfc);
584 if (ret)
585 dev_err(&hdev->pdev->dev,
586 "failed to set rss tuple, ret = %d.\n", ret);
587
588 return ret;
589 }
590
hclgevf_get_rss_tuple(struct hnae3_handle * handle,struct ethtool_rxnfc * nfc)591 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle,
592 struct ethtool_rxnfc *nfc)
593 {
594 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
595 u8 tuple_sets;
596 int ret;
597
598 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
599 return -EOPNOTSUPP;
600
601 nfc->data = 0;
602
603 ret = hclge_comm_get_rss_tuple(&hdev->rss_cfg, nfc->flow_type,
604 &tuple_sets);
605 if (ret || !tuple_sets)
606 return ret;
607
608 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets);
609
610 return 0;
611 }
612
hclgevf_get_tc_size(struct hnae3_handle * handle)613 static int hclgevf_get_tc_size(struct hnae3_handle *handle)
614 {
615 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
616 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg;
617
618 return rss_cfg->rss_size;
619 }
620
hclgevf_bind_ring_to_vector(struct hnae3_handle * handle,bool en,int vector_id,struct hnae3_ring_chain_node * ring_chain)621 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en,
622 int vector_id,
623 struct hnae3_ring_chain_node *ring_chain)
624 {
625 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
626 struct hclge_vf_to_pf_msg send_msg;
627 struct hnae3_ring_chain_node *node;
628 int status;
629 int i = 0;
630
631 memset(&send_msg, 0, sizeof(send_msg));
632 send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR :
633 HCLGE_MBX_UNMAP_RING_TO_VECTOR;
634 send_msg.vector_id = vector_id;
635
636 for (node = ring_chain; node; node = node->next) {
637 send_msg.param[i].ring_type =
638 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B);
639
640 send_msg.param[i].tqp_index = node->tqp_index;
641 send_msg.param[i].int_gl_index =
642 hnae3_get_field(node->int_gl_idx,
643 HNAE3_RING_GL_IDX_M,
644 HNAE3_RING_GL_IDX_S);
645
646 i++;
647 if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) {
648 send_msg.ring_num = i;
649
650 status = hclgevf_send_mbx_msg(hdev, &send_msg, false,
651 NULL, 0);
652 if (status) {
653 dev_err(&hdev->pdev->dev,
654 "Map TQP fail, status is %d.\n",
655 status);
656 return status;
657 }
658 i = 0;
659 }
660 }
661
662 return 0;
663 }
664
hclgevf_map_ring_to_vector(struct hnae3_handle * handle,int vector,struct hnae3_ring_chain_node * ring_chain)665 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector,
666 struct hnae3_ring_chain_node *ring_chain)
667 {
668 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
669 int vector_id;
670
671 vector_id = hclgevf_get_vector_index(hdev, vector);
672 if (vector_id < 0) {
673 dev_err(&handle->pdev->dev,
674 "Get vector index fail. ret =%d\n", vector_id);
675 return vector_id;
676 }
677
678 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain);
679 }
680
hclgevf_unmap_ring_from_vector(struct hnae3_handle * handle,int vector,struct hnae3_ring_chain_node * ring_chain)681 static int hclgevf_unmap_ring_from_vector(
682 struct hnae3_handle *handle,
683 int vector,
684 struct hnae3_ring_chain_node *ring_chain)
685 {
686 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
687 int ret, vector_id;
688
689 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
690 return 0;
691
692 vector_id = hclgevf_get_vector_index(hdev, vector);
693 if (vector_id < 0) {
694 dev_err(&handle->pdev->dev,
695 "Get vector index fail. ret =%d\n", vector_id);
696 return vector_id;
697 }
698
699 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain);
700 if (ret)
701 dev_err(&handle->pdev->dev,
702 "Unmap ring from vector fail. vector=%d, ret =%d\n",
703 vector_id,
704 ret);
705
706 return ret;
707 }
708
hclgevf_put_vector(struct hnae3_handle * handle,int vector)709 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector)
710 {
711 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
712 int vector_id;
713
714 vector_id = hclgevf_get_vector_index(hdev, vector);
715 if (vector_id < 0) {
716 dev_err(&handle->pdev->dev,
717 "hclgevf_put_vector get vector index fail. ret =%d\n",
718 vector_id);
719 return vector_id;
720 }
721
722 hclgevf_free_vector(hdev, vector_id);
723
724 return 0;
725 }
726
hclgevf_cmd_set_promisc_mode(struct hclgevf_dev * hdev,bool en_uc_pmc,bool en_mc_pmc,bool en_bc_pmc)727 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev,
728 bool en_uc_pmc, bool en_mc_pmc,
729 bool en_bc_pmc)
730 {
731 struct hnae3_handle *handle = &hdev->nic;
732 struct hclge_vf_to_pf_msg send_msg;
733 int ret;
734
735 memset(&send_msg, 0, sizeof(send_msg));
736 send_msg.code = HCLGE_MBX_SET_PROMISC_MODE;
737 send_msg.en_bc = en_bc_pmc ? 1 : 0;
738 send_msg.en_uc = en_uc_pmc ? 1 : 0;
739 send_msg.en_mc = en_mc_pmc ? 1 : 0;
740 send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC,
741 &handle->priv_flags) ? 1 : 0;
742
743 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
744 if (ret)
745 dev_err(&hdev->pdev->dev,
746 "Set promisc mode fail, status is %d.\n", ret);
747
748 return ret;
749 }
750
hclgevf_set_promisc_mode(struct hnae3_handle * handle,bool en_uc_pmc,bool en_mc_pmc)751 static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
752 bool en_mc_pmc)
753 {
754 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
755 bool en_bc_pmc;
756
757 en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2;
758
759 return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc,
760 en_bc_pmc);
761 }
762
hclgevf_request_update_promisc_mode(struct hnae3_handle * handle)763 static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle)
764 {
765 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
766
767 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
768 hclgevf_task_schedule(hdev, 0);
769 }
770
hclgevf_sync_promisc_mode(struct hclgevf_dev * hdev)771 static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev)
772 {
773 struct hnae3_handle *handle = &hdev->nic;
774 bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE;
775 bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE;
776 int ret;
777
778 if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) {
779 ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc);
780 if (!ret)
781 clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
782 }
783 }
784
hclgevf_tqp_enable_cmd_send(struct hclgevf_dev * hdev,u16 tqp_id,u16 stream_id,bool enable)785 static int hclgevf_tqp_enable_cmd_send(struct hclgevf_dev *hdev, u16 tqp_id,
786 u16 stream_id, bool enable)
787 {
788 struct hclgevf_cfg_com_tqp_queue_cmd *req;
789 struct hclge_desc desc;
790
791 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data;
792
793 hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
794 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK);
795 req->stream_id = cpu_to_le16(stream_id);
796 if (enable)
797 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B;
798
799 return hclgevf_cmd_send(&hdev->hw, &desc, 1);
800 }
801
hclgevf_tqp_enable(struct hnae3_handle * handle,bool enable)802 static int hclgevf_tqp_enable(struct hnae3_handle *handle, bool enable)
803 {
804 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
805 int ret;
806 u16 i;
807
808 for (i = 0; i < handle->kinfo.num_tqps; i++) {
809 ret = hclgevf_tqp_enable_cmd_send(hdev, i, 0, enable);
810 if (ret)
811 return ret;
812 }
813
814 return 0;
815 }
816
hclgevf_get_host_mac_addr(struct hclgevf_dev * hdev,u8 * p)817 static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p)
818 {
819 struct hclge_vf_to_pf_msg send_msg;
820 u8 host_mac[ETH_ALEN];
821 int status;
822
823 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0);
824 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac,
825 ETH_ALEN);
826 if (status) {
827 dev_err(&hdev->pdev->dev,
828 "fail to get VF MAC from host %d", status);
829 return status;
830 }
831
832 ether_addr_copy(p, host_mac);
833
834 return 0;
835 }
836
hclgevf_get_mac_addr(struct hnae3_handle * handle,u8 * p)837 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p)
838 {
839 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
840 u8 host_mac_addr[ETH_ALEN];
841
842 if (hclgevf_get_host_mac_addr(hdev, host_mac_addr))
843 return;
844
845 hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr);
846 if (hdev->has_pf_mac)
847 ether_addr_copy(p, host_mac_addr);
848 else
849 ether_addr_copy(p, hdev->hw.mac.mac_addr);
850 }
851
hclgevf_set_mac_addr(struct hnae3_handle * handle,const void * p,bool is_first)852 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, const void *p,
853 bool is_first)
854 {
855 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
856 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr;
857 struct hclge_vf_to_pf_msg send_msg;
858 u8 *new_mac_addr = (u8 *)p;
859 int status;
860
861 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0);
862 send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY;
863 ether_addr_copy(send_msg.data, new_mac_addr);
864 if (is_first && !hdev->has_pf_mac)
865 eth_zero_addr(&send_msg.data[ETH_ALEN]);
866 else
867 ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr);
868 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
869 if (!status)
870 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr);
871
872 return status;
873 }
874
875 static struct hclgevf_mac_addr_node *
hclgevf_find_mac_node(struct list_head * list,const u8 * mac_addr)876 hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr)
877 {
878 struct hclgevf_mac_addr_node *mac_node, *tmp;
879
880 list_for_each_entry_safe(mac_node, tmp, list, node)
881 if (ether_addr_equal(mac_addr, mac_node->mac_addr))
882 return mac_node;
883
884 return NULL;
885 }
886
hclgevf_update_mac_node(struct hclgevf_mac_addr_node * mac_node,enum HCLGEVF_MAC_NODE_STATE state)887 static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node,
888 enum HCLGEVF_MAC_NODE_STATE state)
889 {
890 switch (state) {
891 /* from set_rx_mode or tmp_add_list */
892 case HCLGEVF_MAC_TO_ADD:
893 if (mac_node->state == HCLGEVF_MAC_TO_DEL)
894 mac_node->state = HCLGEVF_MAC_ACTIVE;
895 break;
896 /* only from set_rx_mode */
897 case HCLGEVF_MAC_TO_DEL:
898 if (mac_node->state == HCLGEVF_MAC_TO_ADD) {
899 list_del(&mac_node->node);
900 kfree(mac_node);
901 } else {
902 mac_node->state = HCLGEVF_MAC_TO_DEL;
903 }
904 break;
905 /* only from tmp_add_list, the mac_node->state won't be
906 * HCLGEVF_MAC_ACTIVE
907 */
908 case HCLGEVF_MAC_ACTIVE:
909 if (mac_node->state == HCLGEVF_MAC_TO_ADD)
910 mac_node->state = HCLGEVF_MAC_ACTIVE;
911 break;
912 }
913 }
914
hclgevf_update_mac_list(struct hnae3_handle * handle,enum HCLGEVF_MAC_NODE_STATE state,enum HCLGEVF_MAC_ADDR_TYPE mac_type,const unsigned char * addr)915 static int hclgevf_update_mac_list(struct hnae3_handle *handle,
916 enum HCLGEVF_MAC_NODE_STATE state,
917 enum HCLGEVF_MAC_ADDR_TYPE mac_type,
918 const unsigned char *addr)
919 {
920 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
921 struct hclgevf_mac_addr_node *mac_node;
922 struct list_head *list;
923
924 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ?
925 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list;
926
927 spin_lock_bh(&hdev->mac_table.mac_list_lock);
928
929 /* if the mac addr is already in the mac list, no need to add a new
930 * one into it, just check the mac addr state, convert it to a new
931 * state, or just remove it, or do nothing.
932 */
933 mac_node = hclgevf_find_mac_node(list, addr);
934 if (mac_node) {
935 hclgevf_update_mac_node(mac_node, state);
936 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
937 return 0;
938 }
939 /* if this address is never added, unnecessary to delete */
940 if (state == HCLGEVF_MAC_TO_DEL) {
941 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
942 return -ENOENT;
943 }
944
945 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC);
946 if (!mac_node) {
947 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
948 return -ENOMEM;
949 }
950
951 mac_node->state = state;
952 ether_addr_copy(mac_node->mac_addr, addr);
953 list_add_tail(&mac_node->node, list);
954
955 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
956 return 0;
957 }
958
hclgevf_add_uc_addr(struct hnae3_handle * handle,const unsigned char * addr)959 static int hclgevf_add_uc_addr(struct hnae3_handle *handle,
960 const unsigned char *addr)
961 {
962 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD,
963 HCLGEVF_MAC_ADDR_UC, addr);
964 }
965
hclgevf_rm_uc_addr(struct hnae3_handle * handle,const unsigned char * addr)966 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle,
967 const unsigned char *addr)
968 {
969 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL,
970 HCLGEVF_MAC_ADDR_UC, addr);
971 }
972
hclgevf_add_mc_addr(struct hnae3_handle * handle,const unsigned char * addr)973 static int hclgevf_add_mc_addr(struct hnae3_handle *handle,
974 const unsigned char *addr)
975 {
976 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD,
977 HCLGEVF_MAC_ADDR_MC, addr);
978 }
979
hclgevf_rm_mc_addr(struct hnae3_handle * handle,const unsigned char * addr)980 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle,
981 const unsigned char *addr)
982 {
983 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL,
984 HCLGEVF_MAC_ADDR_MC, addr);
985 }
986
hclgevf_add_del_mac_addr(struct hclgevf_dev * hdev,struct hclgevf_mac_addr_node * mac_node,enum HCLGEVF_MAC_ADDR_TYPE mac_type)987 static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev,
988 struct hclgevf_mac_addr_node *mac_node,
989 enum HCLGEVF_MAC_ADDR_TYPE mac_type)
990 {
991 struct hclge_vf_to_pf_msg send_msg;
992 u8 code, subcode;
993
994 if (mac_type == HCLGEVF_MAC_ADDR_UC) {
995 code = HCLGE_MBX_SET_UNICAST;
996 if (mac_node->state == HCLGEVF_MAC_TO_ADD)
997 subcode = HCLGE_MBX_MAC_VLAN_UC_ADD;
998 else
999 subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE;
1000 } else {
1001 code = HCLGE_MBX_SET_MULTICAST;
1002 if (mac_node->state == HCLGEVF_MAC_TO_ADD)
1003 subcode = HCLGE_MBX_MAC_VLAN_MC_ADD;
1004 else
1005 subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE;
1006 }
1007
1008 hclgevf_build_send_msg(&send_msg, code, subcode);
1009 ether_addr_copy(send_msg.data, mac_node->mac_addr);
1010 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
1011 }
1012
hclgevf_config_mac_list(struct hclgevf_dev * hdev,struct list_head * list,enum HCLGEVF_MAC_ADDR_TYPE mac_type)1013 static void hclgevf_config_mac_list(struct hclgevf_dev *hdev,
1014 struct list_head *list,
1015 enum HCLGEVF_MAC_ADDR_TYPE mac_type)
1016 {
1017 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
1018 struct hclgevf_mac_addr_node *mac_node, *tmp;
1019 int ret;
1020
1021 list_for_each_entry_safe(mac_node, tmp, list, node) {
1022 ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type);
1023 if (ret) {
1024 hnae3_format_mac_addr(format_mac_addr,
1025 mac_node->mac_addr);
1026 dev_err(&hdev->pdev->dev,
1027 "failed to configure mac %s, state = %d, ret = %d\n",
1028 format_mac_addr, mac_node->state, ret);
1029 return;
1030 }
1031 if (mac_node->state == HCLGEVF_MAC_TO_ADD) {
1032 mac_node->state = HCLGEVF_MAC_ACTIVE;
1033 } else {
1034 list_del(&mac_node->node);
1035 kfree(mac_node);
1036 }
1037 }
1038 }
1039
hclgevf_sync_from_add_list(struct list_head * add_list,struct list_head * mac_list)1040 static void hclgevf_sync_from_add_list(struct list_head *add_list,
1041 struct list_head *mac_list)
1042 {
1043 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;
1044
1045 list_for_each_entry_safe(mac_node, tmp, add_list, node) {
1046 /* if the mac address from tmp_add_list is not in the
1047 * uc/mc_mac_list, it means have received a TO_DEL request
1048 * during the time window of sending mac config request to PF
1049 * If mac_node state is ACTIVE, then change its state to TO_DEL,
1050 * then it will be removed at next time. If is TO_ADD, it means
1051 * send TO_ADD request failed, so just remove the mac node.
1052 */
1053 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr);
1054 if (new_node) {
1055 hclgevf_update_mac_node(new_node, mac_node->state);
1056 list_del(&mac_node->node);
1057 kfree(mac_node);
1058 } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) {
1059 mac_node->state = HCLGEVF_MAC_TO_DEL;
1060 list_move_tail(&mac_node->node, mac_list);
1061 } else {
1062 list_del(&mac_node->node);
1063 kfree(mac_node);
1064 }
1065 }
1066 }
1067
hclgevf_sync_from_del_list(struct list_head * del_list,struct list_head * mac_list)1068 static void hclgevf_sync_from_del_list(struct list_head *del_list,
1069 struct list_head *mac_list)
1070 {
1071 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;
1072
1073 list_for_each_entry_safe(mac_node, tmp, del_list, node) {
1074 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr);
1075 if (new_node) {
1076 /* If the mac addr is exist in the mac list, it means
1077 * received a new request TO_ADD during the time window
1078 * of sending mac addr configurrequest to PF, so just
1079 * change the mac state to ACTIVE.
1080 */
1081 new_node->state = HCLGEVF_MAC_ACTIVE;
1082 list_del(&mac_node->node);
1083 kfree(mac_node);
1084 } else {
1085 list_move_tail(&mac_node->node, mac_list);
1086 }
1087 }
1088 }
1089
hclgevf_clear_list(struct list_head * list)1090 static void hclgevf_clear_list(struct list_head *list)
1091 {
1092 struct hclgevf_mac_addr_node *mac_node, *tmp;
1093
1094 list_for_each_entry_safe(mac_node, tmp, list, node) {
1095 list_del(&mac_node->node);
1096 kfree(mac_node);
1097 }
1098 }
1099
hclgevf_sync_mac_list(struct hclgevf_dev * hdev,enum HCLGEVF_MAC_ADDR_TYPE mac_type)1100 static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev,
1101 enum HCLGEVF_MAC_ADDR_TYPE mac_type)
1102 {
1103 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;
1104 struct list_head tmp_add_list, tmp_del_list;
1105 struct list_head *list;
1106
1107 INIT_LIST_HEAD(&tmp_add_list);
1108 INIT_LIST_HEAD(&tmp_del_list);
1109
1110 /* move the mac addr to the tmp_add_list and tmp_del_list, then
1111 * we can add/delete these mac addr outside the spin lock
1112 */
1113 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ?
1114 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list;
1115
1116 spin_lock_bh(&hdev->mac_table.mac_list_lock);
1117
1118 list_for_each_entry_safe(mac_node, tmp, list, node) {
1119 switch (mac_node->state) {
1120 case HCLGEVF_MAC_TO_DEL:
1121 list_move_tail(&mac_node->node, &tmp_del_list);
1122 break;
1123 case HCLGEVF_MAC_TO_ADD:
1124 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC);
1125 if (!new_node)
1126 goto stop_traverse;
1127
1128 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr);
1129 new_node->state = mac_node->state;
1130 list_add_tail(&new_node->node, &tmp_add_list);
1131 break;
1132 default:
1133 break;
1134 }
1135 }
1136
1137 stop_traverse:
1138 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1139
1140 /* delete first, in order to get max mac table space for adding */
1141 hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type);
1142 hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type);
1143
1144 /* if some mac addresses were added/deleted fail, move back to the
1145 * mac_list, and retry at next time.
1146 */
1147 spin_lock_bh(&hdev->mac_table.mac_list_lock);
1148
1149 hclgevf_sync_from_del_list(&tmp_del_list, list);
1150 hclgevf_sync_from_add_list(&tmp_add_list, list);
1151
1152 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1153 }
1154
hclgevf_sync_mac_table(struct hclgevf_dev * hdev)1155 static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev)
1156 {
1157 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC);
1158 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC);
1159 }
1160
hclgevf_uninit_mac_list(struct hclgevf_dev * hdev)1161 static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev)
1162 {
1163 spin_lock_bh(&hdev->mac_table.mac_list_lock);
1164
1165 hclgevf_clear_list(&hdev->mac_table.uc_mac_list);
1166 hclgevf_clear_list(&hdev->mac_table.mc_mac_list);
1167
1168 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1169 }
1170
hclgevf_enable_vlan_filter(struct hnae3_handle * handle,bool enable)1171 static int hclgevf_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
1172 {
1173 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1174 struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
1175 struct hclge_vf_to_pf_msg send_msg;
1176
1177 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
1178 return -EOPNOTSUPP;
1179
1180 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
1181 HCLGE_MBX_ENABLE_VLAN_FILTER);
1182 send_msg.data[0] = enable ? 1 : 0;
1183
1184 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1185 }
1186
hclgevf_set_vlan_filter(struct hnae3_handle * handle,__be16 proto,u16 vlan_id,bool is_kill)1187 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle,
1188 __be16 proto, u16 vlan_id,
1189 bool is_kill)
1190 {
1191 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1192 struct hclge_mbx_vlan_filter *vlan_filter;
1193 struct hclge_vf_to_pf_msg send_msg;
1194 int ret;
1195
1196 if (vlan_id > HCLGEVF_MAX_VLAN_ID)
1197 return -EINVAL;
1198
1199 if (proto != htons(ETH_P_8021Q))
1200 return -EPROTONOSUPPORT;
1201
1202 /* When device is resetting or reset failed, firmware is unable to
1203 * handle mailbox. Just record the vlan id, and remove it after
1204 * reset finished.
1205 */
1206 if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||
1207 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) {
1208 set_bit(vlan_id, hdev->vlan_del_fail_bmap);
1209 return -EBUSY;
1210 } else if (!is_kill && test_bit(vlan_id, hdev->vlan_del_fail_bmap)) {
1211 clear_bit(vlan_id, hdev->vlan_del_fail_bmap);
1212 }
1213
1214 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
1215 HCLGE_MBX_VLAN_FILTER);
1216 vlan_filter = (struct hclge_mbx_vlan_filter *)send_msg.data;
1217 vlan_filter->is_kill = is_kill;
1218 vlan_filter->vlan_id = cpu_to_le16(vlan_id);
1219 vlan_filter->proto = cpu_to_le16(be16_to_cpu(proto));
1220
1221 /* when remove hw vlan filter failed, record the vlan id,
1222 * and try to remove it from hw later, to be consistence
1223 * with stack.
1224 */
1225 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1226 if (is_kill && ret)
1227 set_bit(vlan_id, hdev->vlan_del_fail_bmap);
1228
1229 return ret;
1230 }
1231
hclgevf_sync_vlan_filter(struct hclgevf_dev * hdev)1232 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev)
1233 {
1234 #define HCLGEVF_MAX_SYNC_COUNT 60
1235 struct hnae3_handle *handle = &hdev->nic;
1236 int ret, sync_cnt = 0;
1237 u16 vlan_id;
1238
1239 if (bitmap_empty(hdev->vlan_del_fail_bmap, VLAN_N_VID))
1240 return;
1241
1242 rtnl_lock();
1243 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID);
1244 while (vlan_id != VLAN_N_VID) {
1245 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q),
1246 vlan_id, true);
1247 if (ret)
1248 break;
1249
1250 clear_bit(vlan_id, hdev->vlan_del_fail_bmap);
1251 sync_cnt++;
1252 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT)
1253 break;
1254
1255 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID);
1256 }
1257 rtnl_unlock();
1258 }
1259
hclgevf_en_hw_strip_rxvtag_cmd(struct hclgevf_dev * hdev,bool enable)1260 static int hclgevf_en_hw_strip_rxvtag_cmd(struct hclgevf_dev *hdev, bool enable)
1261 {
1262 struct hclge_vf_to_pf_msg send_msg;
1263
1264 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
1265 HCLGE_MBX_VLAN_RX_OFF_CFG);
1266 send_msg.data[0] = enable ? 1 : 0;
1267 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
1268 }
1269
hclgevf_en_hw_strip_rxvtag(struct hnae3_handle * handle,bool enable)1270 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
1271 {
1272 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1273 int ret;
1274
1275 ret = hclgevf_en_hw_strip_rxvtag_cmd(hdev, enable);
1276 if (ret)
1277 return ret;
1278
1279 hdev->rxvtag_strip_en = enable;
1280 return 0;
1281 }
1282
hclgevf_reset_tqp(struct hnae3_handle * handle)1283 static int hclgevf_reset_tqp(struct hnae3_handle *handle)
1284 {
1285 #define HCLGEVF_RESET_ALL_QUEUE_DONE 1U
1286 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1287 struct hclge_vf_to_pf_msg send_msg;
1288 u8 return_status = 0;
1289 int ret;
1290 u16 i;
1291
1292 /* disable vf queue before send queue reset msg to PF */
1293 ret = hclgevf_tqp_enable(handle, false);
1294 if (ret) {
1295 dev_err(&hdev->pdev->dev, "failed to disable tqp, ret = %d\n",
1296 ret);
1297 return ret;
1298 }
1299
1300 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0);
1301
1302 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &return_status,
1303 sizeof(return_status));
1304 if (ret || return_status == HCLGEVF_RESET_ALL_QUEUE_DONE)
1305 return ret;
1306
1307 for (i = 1; i < handle->kinfo.num_tqps; i++) {
1308 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0);
1309 *(__le16 *)send_msg.data = cpu_to_le16(i);
1310 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1311 if (ret)
1312 return ret;
1313 }
1314
1315 return 0;
1316 }
1317
hclgevf_set_mtu(struct hnae3_handle * handle,int new_mtu)1318 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu)
1319 {
1320 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1321 struct hclge_mbx_mtu_info *mtu_info;
1322 struct hclge_vf_to_pf_msg send_msg;
1323
1324 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0);
1325 mtu_info = (struct hclge_mbx_mtu_info *)send_msg.data;
1326 mtu_info->mtu = cpu_to_le32(new_mtu);
1327
1328 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1329 }
1330
hclgevf_notify_client(struct hclgevf_dev * hdev,enum hnae3_reset_notify_type type)1331 static int hclgevf_notify_client(struct hclgevf_dev *hdev,
1332 enum hnae3_reset_notify_type type)
1333 {
1334 struct hnae3_client *client = hdev->nic_client;
1335 struct hnae3_handle *handle = &hdev->nic;
1336 int ret;
1337
1338 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) ||
1339 !client)
1340 return 0;
1341
1342 if (!client->ops->reset_notify)
1343 return -EOPNOTSUPP;
1344
1345 ret = client->ops->reset_notify(handle, type);
1346 if (ret)
1347 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n",
1348 type, ret);
1349
1350 return ret;
1351 }
1352
hclgevf_notify_roce_client(struct hclgevf_dev * hdev,enum hnae3_reset_notify_type type)1353 static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev,
1354 enum hnae3_reset_notify_type type)
1355 {
1356 struct hnae3_client *client = hdev->roce_client;
1357 struct hnae3_handle *handle = &hdev->roce;
1358 int ret;
1359
1360 if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client)
1361 return 0;
1362
1363 if (!client->ops->reset_notify)
1364 return -EOPNOTSUPP;
1365
1366 ret = client->ops->reset_notify(handle, type);
1367 if (ret)
1368 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)",
1369 type, ret);
1370 return ret;
1371 }
1372
hclgevf_reset_wait(struct hclgevf_dev * hdev)1373 static int hclgevf_reset_wait(struct hclgevf_dev *hdev)
1374 {
1375 #define HCLGEVF_RESET_WAIT_US 20000
1376 #define HCLGEVF_RESET_WAIT_CNT 2000
1377 #define HCLGEVF_RESET_WAIT_TIMEOUT_US \
1378 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT)
1379
1380 u32 val;
1381 int ret;
1382
1383 if (hdev->reset_type == HNAE3_VF_RESET)
1384 ret = readl_poll_timeout(hdev->hw.hw.io_base +
1385 HCLGEVF_VF_RST_ING, val,
1386 !(val & HCLGEVF_VF_RST_ING_BIT),
1387 HCLGEVF_RESET_WAIT_US,
1388 HCLGEVF_RESET_WAIT_TIMEOUT_US);
1389 else
1390 ret = readl_poll_timeout(hdev->hw.hw.io_base +
1391 HCLGEVF_RST_ING, val,
1392 !(val & HCLGEVF_RST_ING_BITS),
1393 HCLGEVF_RESET_WAIT_US,
1394 HCLGEVF_RESET_WAIT_TIMEOUT_US);
1395
1396 /* hardware completion status should be available by this time */
1397 if (ret) {
1398 dev_err(&hdev->pdev->dev,
1399 "couldn't get reset done status from h/w, timeout!\n");
1400 return ret;
1401 }
1402
1403 /* we will wait a bit more to let reset of the stack to complete. This
1404 * might happen in case reset assertion was made by PF. Yes, this also
1405 * means we might end up waiting bit more even for VF reset.
1406 */
1407 if (hdev->reset_type == HNAE3_VF_FULL_RESET)
1408 msleep(5000);
1409 else
1410 msleep(500);
1411
1412 return 0;
1413 }
1414
hclgevf_reset_handshake(struct hclgevf_dev * hdev,bool enable)1415 static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable)
1416 {
1417 u32 reg_val;
1418
1419 reg_val = hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG);
1420 if (enable)
1421 reg_val |= HCLGEVF_NIC_SW_RST_RDY;
1422 else
1423 reg_val &= ~HCLGEVF_NIC_SW_RST_RDY;
1424
1425 hclgevf_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG,
1426 reg_val);
1427 }
1428
hclgevf_reset_stack(struct hclgevf_dev * hdev)1429 static int hclgevf_reset_stack(struct hclgevf_dev *hdev)
1430 {
1431 int ret;
1432
1433 /* uninitialize the nic client */
1434 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT);
1435 if (ret)
1436 return ret;
1437
1438 /* re-initialize the hclge device */
1439 ret = hclgevf_reset_hdev(hdev);
1440 if (ret) {
1441 dev_err(&hdev->pdev->dev,
1442 "hclge device re-init failed, VF is disabled!\n");
1443 return ret;
1444 }
1445
1446 /* bring up the nic client again */
1447 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT);
1448 if (ret)
1449 return ret;
1450
1451 /* clear handshake status with IMP */
1452 hclgevf_reset_handshake(hdev, false);
1453
1454 /* bring up the nic to enable TX/RX again */
1455 return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
1456 }
1457
hclgevf_reset_prepare_wait(struct hclgevf_dev * hdev)1458 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev)
1459 {
1460 #define HCLGEVF_RESET_SYNC_TIME 100
1461
1462 if (hdev->reset_type == HNAE3_VF_FUNC_RESET) {
1463 struct hclge_vf_to_pf_msg send_msg;
1464 int ret;
1465
1466 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0);
1467 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1468 if (ret) {
1469 dev_err(&hdev->pdev->dev,
1470 "failed to assert VF reset, ret = %d\n", ret);
1471 return ret;
1472 }
1473 hdev->rst_stats.vf_func_rst_cnt++;
1474 }
1475
1476 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
1477 /* inform hardware that preparatory work is done */
1478 msleep(HCLGEVF_RESET_SYNC_TIME);
1479 hclgevf_reset_handshake(hdev, true);
1480 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n",
1481 hdev->reset_type);
1482
1483 return 0;
1484 }
1485
hclgevf_dump_rst_info(struct hclgevf_dev * hdev)1486 static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev)
1487 {
1488 dev_info(&hdev->pdev->dev, "VF function reset count: %u\n",
1489 hdev->rst_stats.vf_func_rst_cnt);
1490 dev_info(&hdev->pdev->dev, "FLR reset count: %u\n",
1491 hdev->rst_stats.flr_rst_cnt);
1492 dev_info(&hdev->pdev->dev, "VF reset count: %u\n",
1493 hdev->rst_stats.vf_rst_cnt);
1494 dev_info(&hdev->pdev->dev, "reset done count: %u\n",
1495 hdev->rst_stats.rst_done_cnt);
1496 dev_info(&hdev->pdev->dev, "HW reset done count: %u\n",
1497 hdev->rst_stats.hw_rst_done_cnt);
1498 dev_info(&hdev->pdev->dev, "reset count: %u\n",
1499 hdev->rst_stats.rst_cnt);
1500 dev_info(&hdev->pdev->dev, "reset fail count: %u\n",
1501 hdev->rst_stats.rst_fail_cnt);
1502 dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n",
1503 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE));
1504 dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n",
1505 hclgevf_read_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_STATE_REG));
1506 dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n",
1507 hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG));
1508 dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n",
1509 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING));
1510 dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state);
1511 }
1512
hclgevf_reset_err_handle(struct hclgevf_dev * hdev)1513 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev)
1514 {
1515 /* recover handshake status with IMP when reset fail */
1516 hclgevf_reset_handshake(hdev, true);
1517 hdev->rst_stats.rst_fail_cnt++;
1518 dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n",
1519 hdev->rst_stats.rst_fail_cnt);
1520
1521 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT)
1522 set_bit(hdev->reset_type, &hdev->reset_pending);
1523
1524 if (hclgevf_is_reset_pending(hdev)) {
1525 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1526 hclgevf_reset_task_schedule(hdev);
1527 } else {
1528 set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
1529 hclgevf_dump_rst_info(hdev);
1530 }
1531 }
1532
hclgevf_reset_prepare(struct hclgevf_dev * hdev)1533 static int hclgevf_reset_prepare(struct hclgevf_dev *hdev)
1534 {
1535 int ret;
1536
1537 hdev->rst_stats.rst_cnt++;
1538
1539 /* perform reset of the stack & ae device for a client */
1540 ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT);
1541 if (ret)
1542 return ret;
1543
1544 rtnl_lock();
1545 /* bring down the nic to stop any ongoing TX/RX */
1546 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
1547 rtnl_unlock();
1548 if (ret)
1549 return ret;
1550
1551 return hclgevf_reset_prepare_wait(hdev);
1552 }
1553
hclgevf_reset_rebuild(struct hclgevf_dev * hdev)1554 static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev)
1555 {
1556 int ret;
1557
1558 hdev->rst_stats.hw_rst_done_cnt++;
1559 ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT);
1560 if (ret)
1561 return ret;
1562
1563 rtnl_lock();
1564 /* now, re-initialize the nic client and ae device */
1565 ret = hclgevf_reset_stack(hdev);
1566 rtnl_unlock();
1567 if (ret) {
1568 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n");
1569 return ret;
1570 }
1571
1572 ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT);
1573 /* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 1
1574 * times
1575 */
1576 if (ret &&
1577 hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1)
1578 return ret;
1579
1580 ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT);
1581 if (ret)
1582 return ret;
1583
1584 hdev->last_reset_time = jiffies;
1585 hdev->rst_stats.rst_done_cnt++;
1586 hdev->rst_stats.rst_fail_cnt = 0;
1587 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
1588
1589 return 0;
1590 }
1591
hclgevf_reset(struct hclgevf_dev * hdev)1592 static void hclgevf_reset(struct hclgevf_dev *hdev)
1593 {
1594 if (hclgevf_reset_prepare(hdev))
1595 goto err_reset;
1596
1597 /* check if VF could successfully fetch the hardware reset completion
1598 * status from the hardware
1599 */
1600 if (hclgevf_reset_wait(hdev)) {
1601 /* can't do much in this situation, will disable VF */
1602 dev_err(&hdev->pdev->dev,
1603 "failed to fetch H/W reset completion status\n");
1604 goto err_reset;
1605 }
1606
1607 if (hclgevf_reset_rebuild(hdev))
1608 goto err_reset;
1609
1610 return;
1611
1612 err_reset:
1613 hclgevf_reset_err_handle(hdev);
1614 }
1615
hclgevf_get_reset_level(unsigned long * addr)1616 static enum hnae3_reset_type hclgevf_get_reset_level(unsigned long *addr)
1617 {
1618 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
1619
1620 /* return the highest priority reset level amongst all */
1621 if (test_bit(HNAE3_VF_RESET, addr)) {
1622 rst_level = HNAE3_VF_RESET;
1623 clear_bit(HNAE3_VF_RESET, addr);
1624 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr);
1625 clear_bit(HNAE3_VF_FUNC_RESET, addr);
1626 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) {
1627 rst_level = HNAE3_VF_FULL_RESET;
1628 clear_bit(HNAE3_VF_FULL_RESET, addr);
1629 clear_bit(HNAE3_VF_FUNC_RESET, addr);
1630 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) {
1631 rst_level = HNAE3_VF_PF_FUNC_RESET;
1632 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr);
1633 clear_bit(HNAE3_VF_FUNC_RESET, addr);
1634 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) {
1635 rst_level = HNAE3_VF_FUNC_RESET;
1636 clear_bit(HNAE3_VF_FUNC_RESET, addr);
1637 } else if (test_bit(HNAE3_FLR_RESET, addr)) {
1638 rst_level = HNAE3_FLR_RESET;
1639 clear_bit(HNAE3_FLR_RESET, addr);
1640 }
1641
1642 return rst_level;
1643 }
1644
hclgevf_reset_event(struct pci_dev * pdev,struct hnae3_handle * handle)1645 static void hclgevf_reset_event(struct pci_dev *pdev,
1646 struct hnae3_handle *handle)
1647 {
1648 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1649 struct hclgevf_dev *hdev = ae_dev->priv;
1650
1651 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n");
1652
1653 if (hdev->default_reset_request)
1654 hdev->reset_level =
1655 hclgevf_get_reset_level(&hdev->default_reset_request);
1656 else
1657 hdev->reset_level = HNAE3_VF_FUNC_RESET;
1658
1659 /* reset of this VF requested */
1660 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state);
1661 hclgevf_reset_task_schedule(hdev);
1662
1663 hdev->last_reset_time = jiffies;
1664 }
1665
hclgevf_set_def_reset_request(struct hnae3_ae_dev * ae_dev,enum hnae3_reset_type rst_type)1666 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
1667 enum hnae3_reset_type rst_type)
1668 {
1669 struct hclgevf_dev *hdev = ae_dev->priv;
1670
1671 set_bit(rst_type, &hdev->default_reset_request);
1672 }
1673
hclgevf_enable_vector(struct hclgevf_misc_vector * vector,bool en)1674 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en)
1675 {
1676 writel(en ? 1 : 0, vector->addr);
1677 }
1678
hclgevf_reset_prepare_general(struct hnae3_ae_dev * ae_dev,enum hnae3_reset_type rst_type)1679 static void hclgevf_reset_prepare_general(struct hnae3_ae_dev *ae_dev,
1680 enum hnae3_reset_type rst_type)
1681 {
1682 #define HCLGEVF_RESET_RETRY_WAIT_MS 500
1683 #define HCLGEVF_RESET_RETRY_CNT 5
1684
1685 struct hclgevf_dev *hdev = ae_dev->priv;
1686 int retry_cnt = 0;
1687 int ret;
1688
1689 while (retry_cnt++ < HCLGEVF_RESET_RETRY_CNT) {
1690 down(&hdev->reset_sem);
1691 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
1692 hdev->reset_type = rst_type;
1693 ret = hclgevf_reset_prepare(hdev);
1694 if (!ret && !hdev->reset_pending)
1695 break;
1696
1697 dev_err(&hdev->pdev->dev,
1698 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n",
1699 ret, hdev->reset_pending, retry_cnt);
1700 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
1701 up(&hdev->reset_sem);
1702 msleep(HCLGEVF_RESET_RETRY_WAIT_MS);
1703 }
1704
1705 /* disable misc vector before reset done */
1706 hclgevf_enable_vector(&hdev->misc_vector, false);
1707
1708 if (hdev->reset_type == HNAE3_FLR_RESET)
1709 hdev->rst_stats.flr_rst_cnt++;
1710 }
1711
hclgevf_reset_done(struct hnae3_ae_dev * ae_dev)1712 static void hclgevf_reset_done(struct hnae3_ae_dev *ae_dev)
1713 {
1714 struct hclgevf_dev *hdev = ae_dev->priv;
1715 int ret;
1716
1717 hclgevf_enable_vector(&hdev->misc_vector, true);
1718
1719 ret = hclgevf_reset_rebuild(hdev);
1720 if (ret)
1721 dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n",
1722 ret);
1723
1724 hdev->reset_type = HNAE3_NONE_RESET;
1725 if (test_and_clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
1726 up(&hdev->reset_sem);
1727 }
1728
hclgevf_get_fw_version(struct hnae3_handle * handle)1729 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle)
1730 {
1731 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1732
1733 return hdev->fw_version;
1734 }
1735
hclgevf_get_misc_vector(struct hclgevf_dev * hdev)1736 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev)
1737 {
1738 struct hclgevf_misc_vector *vector = &hdev->misc_vector;
1739
1740 vector->vector_irq = pci_irq_vector(hdev->pdev,
1741 HCLGEVF_MISC_VECTOR_NUM);
1742 vector->addr = hdev->hw.hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE;
1743 /* vector status always valid for Vector 0 */
1744 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0;
1745 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq;
1746
1747 hdev->num_msi_left -= 1;
1748 hdev->num_msi_used += 1;
1749 }
1750
hclgevf_reset_task_schedule(struct hclgevf_dev * hdev)1751 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev)
1752 {
1753 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&
1754 test_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state) &&
1755 !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED,
1756 &hdev->state))
1757 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0);
1758 }
1759
hclgevf_mbx_task_schedule(struct hclgevf_dev * hdev)1760 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev)
1761 {
1762 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&
1763 !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED,
1764 &hdev->state))
1765 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0);
1766 }
1767
hclgevf_task_schedule(struct hclgevf_dev * hdev,unsigned long delay)1768 static void hclgevf_task_schedule(struct hclgevf_dev *hdev,
1769 unsigned long delay)
1770 {
1771 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&
1772 !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state))
1773 mod_delayed_work(hclgevf_wq, &hdev->service_task, delay);
1774 }
1775
hclgevf_reset_service_task(struct hclgevf_dev * hdev)1776 static void hclgevf_reset_service_task(struct hclgevf_dev *hdev)
1777 {
1778 #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3
1779
1780 if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state))
1781 return;
1782
1783 down(&hdev->reset_sem);
1784 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
1785
1786 if (test_and_clear_bit(HCLGEVF_RESET_PENDING,
1787 &hdev->reset_state)) {
1788 /* PF has intimated that it is about to reset the hardware.
1789 * We now have to poll & check if hardware has actually
1790 * completed the reset sequence. On hardware reset completion,
1791 * VF needs to reset the client and ae device.
1792 */
1793 hdev->reset_attempts = 0;
1794
1795 hdev->last_reset_time = jiffies;
1796 hdev->reset_type =
1797 hclgevf_get_reset_level(&hdev->reset_pending);
1798 if (hdev->reset_type != HNAE3_NONE_RESET)
1799 hclgevf_reset(hdev);
1800 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED,
1801 &hdev->reset_state)) {
1802 /* we could be here when either of below happens:
1803 * 1. reset was initiated due to watchdog timeout caused by
1804 * a. IMP was earlier reset and our TX got choked down and
1805 * which resulted in watchdog reacting and inducing VF
1806 * reset. This also means our cmdq would be unreliable.
1807 * b. problem in TX due to other lower layer(example link
1808 * layer not functioning properly etc.)
1809 * 2. VF reset might have been initiated due to some config
1810 * change.
1811 *
1812 * NOTE: Theres no clear way to detect above cases than to react
1813 * to the response of PF for this reset request. PF will ack the
1814 * 1b and 2. cases but we will not get any intimation about 1a
1815 * from PF as cmdq would be in unreliable state i.e. mailbox
1816 * communication between PF and VF would be broken.
1817 *
1818 * if we are never geting into pending state it means either:
1819 * 1. PF is not receiving our request which could be due to IMP
1820 * reset
1821 * 2. PF is screwed
1822 * We cannot do much for 2. but to check first we can try reset
1823 * our PCIe + stack and see if it alleviates the problem.
1824 */
1825 if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) {
1826 /* prepare for full reset of stack + pcie interface */
1827 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending);
1828
1829 /* "defer" schedule the reset task again */
1830 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1831 } else {
1832 hdev->reset_attempts++;
1833
1834 set_bit(hdev->reset_level, &hdev->reset_pending);
1835 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1836 }
1837 hclgevf_reset_task_schedule(hdev);
1838 }
1839
1840 hdev->reset_type = HNAE3_NONE_RESET;
1841 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
1842 up(&hdev->reset_sem);
1843 }
1844
hclgevf_mailbox_service_task(struct hclgevf_dev * hdev)1845 static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev)
1846 {
1847 if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state))
1848 return;
1849
1850 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state))
1851 return;
1852
1853 hclgevf_mbx_async_handler(hdev);
1854
1855 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
1856 }
1857
hclgevf_keep_alive(struct hclgevf_dev * hdev)1858 static void hclgevf_keep_alive(struct hclgevf_dev *hdev)
1859 {
1860 struct hclge_vf_to_pf_msg send_msg;
1861 int ret;
1862
1863 if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state))
1864 return;
1865
1866 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0);
1867 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
1868 if (ret)
1869 dev_err(&hdev->pdev->dev,
1870 "VF sends keep alive cmd failed(=%d)\n", ret);
1871 }
1872
hclgevf_periodic_service_task(struct hclgevf_dev * hdev)1873 static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev)
1874 {
1875 unsigned long delta = round_jiffies_relative(HZ);
1876 struct hnae3_handle *handle = &hdev->nic;
1877
1878 if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state) ||
1879 test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state))
1880 return;
1881
1882 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) {
1883 delta = jiffies - hdev->last_serv_processed;
1884
1885 if (delta < round_jiffies_relative(HZ)) {
1886 delta = round_jiffies_relative(HZ) - delta;
1887 goto out;
1888 }
1889 }
1890
1891 hdev->serv_processed_cnt++;
1892 if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL))
1893 hclgevf_keep_alive(hdev);
1894
1895 if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) {
1896 hdev->last_serv_processed = jiffies;
1897 goto out;
1898 }
1899
1900 if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL))
1901 hclge_comm_tqps_update_stats(handle, &hdev->hw.hw);
1902
1903 /* VF does not need to request link status when this bit is set, because
1904 * PF will push its link status to VFs when link status changed.
1905 */
1906 if (!test_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state))
1907 hclgevf_request_link_info(hdev);
1908
1909 hclgevf_update_link_mode(hdev);
1910
1911 hclgevf_sync_vlan_filter(hdev);
1912
1913 hclgevf_sync_mac_table(hdev);
1914
1915 hclgevf_sync_promisc_mode(hdev);
1916
1917 hdev->last_serv_processed = jiffies;
1918
1919 out:
1920 hclgevf_task_schedule(hdev, delta);
1921 }
1922
hclgevf_service_task(struct work_struct * work)1923 static void hclgevf_service_task(struct work_struct *work)
1924 {
1925 struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev,
1926 service_task.work);
1927
1928 hclgevf_reset_service_task(hdev);
1929 hclgevf_mailbox_service_task(hdev);
1930 hclgevf_periodic_service_task(hdev);
1931
1932 /* Handle reset and mbx again in case periodical task delays the
1933 * handling by calling hclgevf_task_schedule() in
1934 * hclgevf_periodic_service_task()
1935 */
1936 hclgevf_reset_service_task(hdev);
1937 hclgevf_mailbox_service_task(hdev);
1938 }
1939
hclgevf_clear_event_cause(struct hclgevf_dev * hdev,u32 regclr)1940 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr)
1941 {
1942 hclgevf_write_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, regclr);
1943 }
1944
hclgevf_check_evt_cause(struct hclgevf_dev * hdev,u32 * clearval)1945 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
1946 u32 *clearval)
1947 {
1948 u32 val, cmdq_stat_reg, rst_ing_reg;
1949
1950 /* fetch the events from their corresponding regs */
1951 cmdq_stat_reg = hclgevf_read_dev(&hdev->hw,
1952 HCLGE_COMM_VECTOR0_CMDQ_STATE_REG);
1953 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1954 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
1955 dev_info(&hdev->pdev->dev,
1956 "receive reset interrupt 0x%x!\n", rst_ing_reg);
1957 set_bit(HNAE3_VF_RESET, &hdev->reset_pending);
1958 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1959 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
1960 *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B);
1961 hdev->rst_stats.vf_rst_cnt++;
1962 /* set up VF hardware reset status, its PF will clear
1963 * this status when PF has initialized done.
1964 */
1965 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING);
1966 hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING,
1967 val | HCLGEVF_VF_RST_ING_BIT);
1968 return HCLGEVF_VECTOR0_EVENT_RST;
1969 }
1970
1971 /* check for vector0 mailbox(=CMDQ RX) event source */
1972 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1973 /* for revision 0x21, clearing interrupt is writing bit 0
1974 * to the clear register, writing bit 1 means to keep the
1975 * old value.
1976 * for revision 0x20, the clear register is a read & write
1977 * register, so we should just write 0 to the bit we are
1978 * handling, and keep other bits as cmdq_stat_reg.
1979 */
1980 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
1981 *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
1982 else
1983 *clearval = cmdq_stat_reg &
1984 ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
1985
1986 return HCLGEVF_VECTOR0_EVENT_MBX;
1987 }
1988
1989 /* print other vector0 event source */
1990 dev_info(&hdev->pdev->dev,
1991 "vector 0 interrupt from unknown source, cmdq_src = %#x\n",
1992 cmdq_stat_reg);
1993
1994 return HCLGEVF_VECTOR0_EVENT_OTHER;
1995 }
1996
hclgevf_reset_timer(struct timer_list * t)1997 static void hclgevf_reset_timer(struct timer_list *t)
1998 {
1999 struct hclgevf_dev *hdev = from_timer(hdev, t, reset_timer);
2000
2001 hclgevf_clear_event_cause(hdev, HCLGEVF_VECTOR0_EVENT_RST);
2002 hclgevf_reset_task_schedule(hdev);
2003 }
2004
hclgevf_misc_irq_handle(int irq,void * data)2005 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data)
2006 {
2007 #define HCLGEVF_RESET_DELAY 5
2008
2009 enum hclgevf_evt_cause event_cause;
2010 struct hclgevf_dev *hdev = data;
2011 u32 clearval;
2012
2013 hclgevf_enable_vector(&hdev->misc_vector, false);
2014 event_cause = hclgevf_check_evt_cause(hdev, &clearval);
2015 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER)
2016 hclgevf_clear_event_cause(hdev, clearval);
2017
2018 switch (event_cause) {
2019 case HCLGEVF_VECTOR0_EVENT_RST:
2020 mod_timer(&hdev->reset_timer,
2021 jiffies + msecs_to_jiffies(HCLGEVF_RESET_DELAY));
2022 break;
2023 case HCLGEVF_VECTOR0_EVENT_MBX:
2024 hclgevf_mbx_handler(hdev);
2025 break;
2026 default:
2027 break;
2028 }
2029
2030 hclgevf_enable_vector(&hdev->misc_vector, true);
2031
2032 return IRQ_HANDLED;
2033 }
2034
hclgevf_configure(struct hclgevf_dev * hdev)2035 static int hclgevf_configure(struct hclgevf_dev *hdev)
2036 {
2037 int ret;
2038
2039 hdev->gro_en = true;
2040
2041 ret = hclgevf_get_basic_info(hdev);
2042 if (ret)
2043 return ret;
2044
2045 /* get current port based vlan state from PF */
2046 ret = hclgevf_get_port_base_vlan_filter_state(hdev);
2047 if (ret)
2048 return ret;
2049
2050 /* get queue configuration from PF */
2051 ret = hclgevf_get_queue_info(hdev);
2052 if (ret)
2053 return ret;
2054
2055 /* get queue depth info from PF */
2056 ret = hclgevf_get_queue_depth(hdev);
2057 if (ret)
2058 return ret;
2059
2060 return hclgevf_get_pf_media_type(hdev);
2061 }
2062
hclgevf_alloc_hdev(struct hnae3_ae_dev * ae_dev)2063 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev)
2064 {
2065 struct pci_dev *pdev = ae_dev->pdev;
2066 struct hclgevf_dev *hdev;
2067
2068 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
2069 if (!hdev)
2070 return -ENOMEM;
2071
2072 hdev->pdev = pdev;
2073 hdev->ae_dev = ae_dev;
2074 ae_dev->priv = hdev;
2075
2076 return 0;
2077 }
2078
hclgevf_init_roce_base_info(struct hclgevf_dev * hdev)2079 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev)
2080 {
2081 struct hnae3_handle *roce = &hdev->roce;
2082 struct hnae3_handle *nic = &hdev->nic;
2083
2084 roce->rinfo.num_vectors = hdev->num_roce_msix;
2085
2086 if (hdev->num_msi_left < roce->rinfo.num_vectors ||
2087 hdev->num_msi_left == 0)
2088 return -EINVAL;
2089
2090 roce->rinfo.base_vector = hdev->roce_base_msix_offset;
2091
2092 roce->rinfo.netdev = nic->kinfo.netdev;
2093 roce->rinfo.roce_io_base = hdev->hw.hw.io_base;
2094 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base;
2095
2096 roce->pdev = nic->pdev;
2097 roce->ae_algo = nic->ae_algo;
2098 bitmap_copy(roce->numa_node_mask.bits, nic->numa_node_mask.bits,
2099 MAX_NUMNODES);
2100 return 0;
2101 }
2102
hclgevf_config_gro(struct hclgevf_dev * hdev)2103 static int hclgevf_config_gro(struct hclgevf_dev *hdev)
2104 {
2105 struct hclgevf_cfg_gro_status_cmd *req;
2106 struct hclge_desc desc;
2107 int ret;
2108
2109 if (!hnae3_ae_dev_gro_supported(hdev->ae_dev))
2110 return 0;
2111
2112 hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG,
2113 false);
2114 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data;
2115
2116 req->gro_en = hdev->gro_en ? 1 : 0;
2117
2118 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
2119 if (ret)
2120 dev_err(&hdev->pdev->dev,
2121 "VF GRO hardware config cmd failed, ret = %d.\n", ret);
2122
2123 return ret;
2124 }
2125
hclgevf_rss_init_hw(struct hclgevf_dev * hdev)2126 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev)
2127 {
2128 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg;
2129 u16 tc_offset[HCLGE_COMM_MAX_TC_NUM];
2130 u16 tc_valid[HCLGE_COMM_MAX_TC_NUM];
2131 u16 tc_size[HCLGE_COMM_MAX_TC_NUM];
2132 int ret;
2133
2134 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
2135 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw,
2136 rss_cfg->rss_algo,
2137 rss_cfg->rss_hash_key);
2138 if (ret)
2139 return ret;
2140
2141 ret = hclge_comm_set_rss_input_tuple(&hdev->hw.hw, rss_cfg);
2142 if (ret)
2143 return ret;
2144 }
2145
2146 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw,
2147 rss_cfg->rss_indirection_tbl);
2148 if (ret)
2149 return ret;
2150
2151 hclge_comm_get_rss_tc_info(rss_cfg->rss_size, hdev->hw_tc_map,
2152 tc_offset, tc_valid, tc_size);
2153
2154 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset,
2155 tc_valid, tc_size);
2156 }
2157
hclgevf_init_vlan_config(struct hclgevf_dev * hdev,bool rxvtag_strip_en)2158 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev,
2159 bool rxvtag_strip_en)
2160 {
2161 struct hnae3_handle *nic = &hdev->nic;
2162 int ret;
2163
2164 ret = hclgevf_en_hw_strip_rxvtag(nic, rxvtag_strip_en);
2165 if (ret) {
2166 dev_err(&hdev->pdev->dev,
2167 "failed to enable rx vlan offload, ret = %d\n", ret);
2168 return ret;
2169 }
2170
2171 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0,
2172 false);
2173 }
2174
hclgevf_flush_link_update(struct hclgevf_dev * hdev)2175 static void hclgevf_flush_link_update(struct hclgevf_dev *hdev)
2176 {
2177 #define HCLGEVF_FLUSH_LINK_TIMEOUT 100000
2178
2179 unsigned long last = hdev->serv_processed_cnt;
2180 int i = 0;
2181
2182 while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) &&
2183 i++ < HCLGEVF_FLUSH_LINK_TIMEOUT &&
2184 last == hdev->serv_processed_cnt)
2185 usleep_range(1, 1);
2186 }
2187
hclgevf_set_timer_task(struct hnae3_handle * handle,bool enable)2188 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable)
2189 {
2190 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2191
2192 if (enable) {
2193 hclgevf_task_schedule(hdev, 0);
2194 } else {
2195 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2196
2197 smp_mb__after_atomic(); /* flush memory to make sure DOWN is seen by service task */
2198 hclgevf_flush_link_update(hdev);
2199 }
2200 }
2201
hclgevf_ae_start(struct hnae3_handle * handle)2202 static int hclgevf_ae_start(struct hnae3_handle *handle)
2203 {
2204 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2205
2206 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2207 clear_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state);
2208
2209 hclge_comm_reset_tqp_stats(handle);
2210
2211 hclgevf_request_link_info(hdev);
2212
2213 hclgevf_update_link_mode(hdev);
2214
2215 return 0;
2216 }
2217
hclgevf_ae_stop(struct hnae3_handle * handle)2218 static void hclgevf_ae_stop(struct hnae3_handle *handle)
2219 {
2220 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2221
2222 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2223
2224 if (hdev->reset_type != HNAE3_VF_RESET)
2225 hclgevf_reset_tqp(handle);
2226
2227 hclge_comm_reset_tqp_stats(handle);
2228 hclgevf_update_link_status(hdev, 0);
2229 }
2230
hclgevf_set_alive(struct hnae3_handle * handle,bool alive)2231 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive)
2232 {
2233 #define HCLGEVF_STATE_ALIVE 1
2234 #define HCLGEVF_STATE_NOT_ALIVE 0
2235
2236 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2237 struct hclge_vf_to_pf_msg send_msg;
2238
2239 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0);
2240 send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE :
2241 HCLGEVF_STATE_NOT_ALIVE;
2242 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
2243 }
2244
hclgevf_client_start(struct hnae3_handle * handle)2245 static int hclgevf_client_start(struct hnae3_handle *handle)
2246 {
2247 return hclgevf_set_alive(handle, true);
2248 }
2249
hclgevf_client_stop(struct hnae3_handle * handle)2250 static void hclgevf_client_stop(struct hnae3_handle *handle)
2251 {
2252 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2253 int ret;
2254
2255 ret = hclgevf_set_alive(handle, false);
2256 if (ret)
2257 dev_warn(&hdev->pdev->dev,
2258 "%s failed %d\n", __func__, ret);
2259 }
2260
hclgevf_state_init(struct hclgevf_dev * hdev)2261 static void hclgevf_state_init(struct hclgevf_dev *hdev)
2262 {
2263 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
2264 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
2265 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
2266
2267 INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task);
2268
2269 mutex_init(&hdev->mbx_resp.mbx_mutex);
2270 sema_init(&hdev->reset_sem, 1);
2271
2272 spin_lock_init(&hdev->mac_table.mac_list_lock);
2273 INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list);
2274 INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list);
2275
2276 /* bring the device down */
2277 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2278 }
2279
hclgevf_state_uninit(struct hclgevf_dev * hdev)2280 static void hclgevf_state_uninit(struct hclgevf_dev *hdev)
2281 {
2282 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2283 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state);
2284
2285 if (hdev->service_task.work.func)
2286 cancel_delayed_work_sync(&hdev->service_task);
2287
2288 mutex_destroy(&hdev->mbx_resp.mbx_mutex);
2289 }
2290
hclgevf_init_msi(struct hclgevf_dev * hdev)2291 static int hclgevf_init_msi(struct hclgevf_dev *hdev)
2292 {
2293 struct pci_dev *pdev = hdev->pdev;
2294 int vectors;
2295 int i;
2296
2297 if (hnae3_dev_roce_supported(hdev))
2298 vectors = pci_alloc_irq_vectors(pdev,
2299 hdev->roce_base_msix_offset + 1,
2300 hdev->num_msi,
2301 PCI_IRQ_MSIX);
2302 else
2303 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM,
2304 hdev->num_msi,
2305 PCI_IRQ_MSI | PCI_IRQ_MSIX);
2306
2307 if (vectors < 0) {
2308 dev_err(&pdev->dev,
2309 "failed(%d) to allocate MSI/MSI-X vectors\n",
2310 vectors);
2311 return vectors;
2312 }
2313 if (vectors < hdev->num_msi)
2314 dev_warn(&hdev->pdev->dev,
2315 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2316 hdev->num_msi, vectors);
2317
2318 hdev->num_msi = vectors;
2319 hdev->num_msi_left = vectors;
2320
2321 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2322 sizeof(u16), GFP_KERNEL);
2323 if (!hdev->vector_status) {
2324 pci_free_irq_vectors(pdev);
2325 return -ENOMEM;
2326 }
2327
2328 for (i = 0; i < hdev->num_msi; i++)
2329 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT;
2330
2331 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2332 sizeof(int), GFP_KERNEL);
2333 if (!hdev->vector_irq) {
2334 devm_kfree(&pdev->dev, hdev->vector_status);
2335 pci_free_irq_vectors(pdev);
2336 return -ENOMEM;
2337 }
2338
2339 return 0;
2340 }
2341
hclgevf_uninit_msi(struct hclgevf_dev * hdev)2342 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev)
2343 {
2344 struct pci_dev *pdev = hdev->pdev;
2345
2346 devm_kfree(&pdev->dev, hdev->vector_status);
2347 devm_kfree(&pdev->dev, hdev->vector_irq);
2348 pci_free_irq_vectors(pdev);
2349 }
2350
hclgevf_misc_irq_init(struct hclgevf_dev * hdev)2351 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev)
2352 {
2353 int ret;
2354
2355 hclgevf_get_misc_vector(hdev);
2356
2357 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s",
2358 HCLGEVF_NAME, pci_name(hdev->pdev));
2359 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle,
2360 0, hdev->misc_vector.name, hdev);
2361 if (ret) {
2362 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n",
2363 hdev->misc_vector.vector_irq);
2364 return ret;
2365 }
2366
2367 hclgevf_clear_event_cause(hdev, 0);
2368
2369 /* enable misc. vector(vector 0) */
2370 hclgevf_enable_vector(&hdev->misc_vector, true);
2371
2372 return ret;
2373 }
2374
hclgevf_misc_irq_uninit(struct hclgevf_dev * hdev)2375 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev)
2376 {
2377 /* disable misc vector(vector 0) */
2378 hclgevf_enable_vector(&hdev->misc_vector, false);
2379 synchronize_irq(hdev->misc_vector.vector_irq);
2380 free_irq(hdev->misc_vector.vector_irq, hdev);
2381 hclgevf_free_vector(hdev, 0);
2382 }
2383
hclgevf_info_show(struct hclgevf_dev * hdev)2384 static void hclgevf_info_show(struct hclgevf_dev *hdev)
2385 {
2386 struct device *dev = &hdev->pdev->dev;
2387
2388 dev_info(dev, "VF info begin:\n");
2389
2390 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps);
2391 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc);
2392 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc);
2393 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport);
2394 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map);
2395 dev_info(dev, "PF media type of this VF: %u\n",
2396 hdev->hw.mac.media_type);
2397
2398 dev_info(dev, "VF info end.\n");
2399 }
2400
hclgevf_init_nic_client_instance(struct hnae3_ae_dev * ae_dev,struct hnae3_client * client)2401 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev,
2402 struct hnae3_client *client)
2403 {
2404 struct hclgevf_dev *hdev = ae_dev->priv;
2405 int rst_cnt = hdev->rst_stats.rst_cnt;
2406 int ret;
2407
2408 ret = client->ops->init_instance(&hdev->nic);
2409 if (ret)
2410 return ret;
2411
2412 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
2413 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||
2414 rst_cnt != hdev->rst_stats.rst_cnt) {
2415 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
2416
2417 client->ops->uninit_instance(&hdev->nic, 0);
2418 return -EBUSY;
2419 }
2420
2421 hnae3_set_client_init_flag(client, ae_dev, 1);
2422
2423 if (netif_msg_drv(&hdev->nic))
2424 hclgevf_info_show(hdev);
2425
2426 return 0;
2427 }
2428
hclgevf_init_roce_client_instance(struct hnae3_ae_dev * ae_dev,struct hnae3_client * client)2429 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev,
2430 struct hnae3_client *client)
2431 {
2432 struct hclgevf_dev *hdev = ae_dev->priv;
2433 int ret;
2434
2435 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client ||
2436 !hdev->nic_client)
2437 return 0;
2438
2439 ret = hclgevf_init_roce_base_info(hdev);
2440 if (ret)
2441 return ret;
2442
2443 ret = client->ops->init_instance(&hdev->roce);
2444 if (ret)
2445 return ret;
2446
2447 set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state);
2448 hnae3_set_client_init_flag(client, ae_dev, 1);
2449
2450 return 0;
2451 }
2452
hclgevf_init_client_instance(struct hnae3_client * client,struct hnae3_ae_dev * ae_dev)2453 static int hclgevf_init_client_instance(struct hnae3_client *client,
2454 struct hnae3_ae_dev *ae_dev)
2455 {
2456 struct hclgevf_dev *hdev = ae_dev->priv;
2457 int ret;
2458
2459 switch (client->type) {
2460 case HNAE3_CLIENT_KNIC:
2461 hdev->nic_client = client;
2462 hdev->nic.client = client;
2463
2464 ret = hclgevf_init_nic_client_instance(ae_dev, client);
2465 if (ret)
2466 goto clear_nic;
2467
2468 ret = hclgevf_init_roce_client_instance(ae_dev,
2469 hdev->roce_client);
2470 if (ret)
2471 goto clear_roce;
2472
2473 break;
2474 case HNAE3_CLIENT_ROCE:
2475 if (hnae3_dev_roce_supported(hdev)) {
2476 hdev->roce_client = client;
2477 hdev->roce.client = client;
2478 }
2479
2480 ret = hclgevf_init_roce_client_instance(ae_dev, client);
2481 if (ret)
2482 goto clear_roce;
2483
2484 break;
2485 default:
2486 return -EINVAL;
2487 }
2488
2489 return 0;
2490
2491 clear_nic:
2492 hdev->nic_client = NULL;
2493 hdev->nic.client = NULL;
2494 return ret;
2495 clear_roce:
2496 hdev->roce_client = NULL;
2497 hdev->roce.client = NULL;
2498 return ret;
2499 }
2500
hclgevf_uninit_client_instance(struct hnae3_client * client,struct hnae3_ae_dev * ae_dev)2501 static void hclgevf_uninit_client_instance(struct hnae3_client *client,
2502 struct hnae3_ae_dev *ae_dev)
2503 {
2504 struct hclgevf_dev *hdev = ae_dev->priv;
2505
2506 /* un-init roce, if it exists */
2507 if (hdev->roce_client) {
2508 while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
2509 msleep(HCLGEVF_WAIT_RESET_DONE);
2510 clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state);
2511
2512 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0);
2513 hdev->roce_client = NULL;
2514 hdev->roce.client = NULL;
2515 }
2516
2517 /* un-init nic/unic, if this was not called by roce client */
2518 if (client->ops->uninit_instance && hdev->nic_client &&
2519 client->type != HNAE3_CLIENT_ROCE) {
2520 while (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
2521 msleep(HCLGEVF_WAIT_RESET_DONE);
2522 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
2523
2524 client->ops->uninit_instance(&hdev->nic, 0);
2525 hdev->nic_client = NULL;
2526 hdev->nic.client = NULL;
2527 }
2528 }
2529
hclgevf_dev_mem_map(struct hclgevf_dev * hdev)2530 static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev)
2531 {
2532 struct pci_dev *pdev = hdev->pdev;
2533 struct hclgevf_hw *hw = &hdev->hw;
2534
2535 /* for device does not have device memory, return directly */
2536 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR)))
2537 return 0;
2538
2539 hw->hw.mem_base =
2540 devm_ioremap_wc(&pdev->dev,
2541 pci_resource_start(pdev, HCLGEVF_MEM_BAR),
2542 pci_resource_len(pdev, HCLGEVF_MEM_BAR));
2543 if (!hw->hw.mem_base) {
2544 dev_err(&pdev->dev, "failed to map device memory\n");
2545 return -EFAULT;
2546 }
2547
2548 return 0;
2549 }
2550
hclgevf_pci_init(struct hclgevf_dev * hdev)2551 static int hclgevf_pci_init(struct hclgevf_dev *hdev)
2552 {
2553 struct pci_dev *pdev = hdev->pdev;
2554 struct hclgevf_hw *hw;
2555 int ret;
2556
2557 ret = pci_enable_device(pdev);
2558 if (ret) {
2559 dev_err(&pdev->dev, "failed to enable PCI device\n");
2560 return ret;
2561 }
2562
2563 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2564 if (ret) {
2565 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting");
2566 goto err_disable_device;
2567 }
2568
2569 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME);
2570 if (ret) {
2571 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
2572 goto err_disable_device;
2573 }
2574
2575 pci_set_master(pdev);
2576 hw = &hdev->hw;
2577 hw->hw.io_base = pci_iomap(pdev, 2, 0);
2578 if (!hw->hw.io_base) {
2579 dev_err(&pdev->dev, "can't map configuration register space\n");
2580 ret = -ENOMEM;
2581 goto err_release_regions;
2582 }
2583
2584 ret = hclgevf_dev_mem_map(hdev);
2585 if (ret)
2586 goto err_unmap_io_base;
2587
2588 return 0;
2589
2590 err_unmap_io_base:
2591 pci_iounmap(pdev, hdev->hw.hw.io_base);
2592 err_release_regions:
2593 pci_release_regions(pdev);
2594 err_disable_device:
2595 pci_disable_device(pdev);
2596
2597 return ret;
2598 }
2599
hclgevf_pci_uninit(struct hclgevf_dev * hdev)2600 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev)
2601 {
2602 struct pci_dev *pdev = hdev->pdev;
2603
2604 if (hdev->hw.hw.mem_base)
2605 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base);
2606
2607 pci_iounmap(pdev, hdev->hw.hw.io_base);
2608 pci_release_regions(pdev);
2609 pci_disable_device(pdev);
2610 }
2611
hclgevf_query_vf_resource(struct hclgevf_dev * hdev)2612 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev)
2613 {
2614 struct hclgevf_query_res_cmd *req;
2615 struct hclge_desc desc;
2616 int ret;
2617
2618 hclgevf_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RSRC, true);
2619 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
2620 if (ret) {
2621 dev_err(&hdev->pdev->dev,
2622 "query vf resource failed, ret = %d.\n", ret);
2623 return ret;
2624 }
2625
2626 req = (struct hclgevf_query_res_cmd *)desc.data;
2627
2628 if (hnae3_dev_roce_supported(hdev)) {
2629 hdev->roce_base_msix_offset =
2630 hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee),
2631 HCLGEVF_MSIX_OFT_ROCEE_M,
2632 HCLGEVF_MSIX_OFT_ROCEE_S);
2633 hdev->num_roce_msix =
2634 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number),
2635 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
2636
2637 /* nic's msix numbers is always equals to the roce's. */
2638 hdev->num_nic_msix = hdev->num_roce_msix;
2639
2640 /* VF should have NIC vectors and Roce vectors, NIC vectors
2641 * are queued before Roce vectors. The offset is fixed to 64.
2642 */
2643 hdev->num_msi = hdev->num_roce_msix +
2644 hdev->roce_base_msix_offset;
2645 } else {
2646 hdev->num_msi =
2647 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number),
2648 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
2649
2650 hdev->num_nic_msix = hdev->num_msi;
2651 }
2652
2653 if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) {
2654 dev_err(&hdev->pdev->dev,
2655 "Just %u msi resources, not enough for vf(min:2).\n",
2656 hdev->num_nic_msix);
2657 return -EINVAL;
2658 }
2659
2660 return 0;
2661 }
2662
hclgevf_set_default_dev_specs(struct hclgevf_dev * hdev)2663 static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev)
2664 {
2665 #define HCLGEVF_MAX_NON_TSO_BD_NUM 8U
2666
2667 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
2668
2669 ae_dev->dev_specs.max_non_tso_bd_num =
2670 HCLGEVF_MAX_NON_TSO_BD_NUM;
2671 ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE;
2672 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE;
2673 ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL;
2674 ae_dev->dev_specs.max_frm_size = HCLGEVF_MAC_MAX_FRAME;
2675 }
2676
hclgevf_parse_dev_specs(struct hclgevf_dev * hdev,struct hclge_desc * desc)2677 static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev,
2678 struct hclge_desc *desc)
2679 {
2680 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
2681 struct hclgevf_dev_specs_0_cmd *req0;
2682 struct hclgevf_dev_specs_1_cmd *req1;
2683
2684 req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data;
2685 req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data;
2686
2687 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num;
2688 ae_dev->dev_specs.rss_ind_tbl_size =
2689 le16_to_cpu(req0->rss_ind_tbl_size);
2690 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max);
2691 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size);
2692 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl);
2693 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size);
2694 }
2695
hclgevf_check_dev_specs(struct hclgevf_dev * hdev)2696 static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev)
2697 {
2698 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs;
2699
2700 if (!dev_specs->max_non_tso_bd_num)
2701 dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM;
2702 if (!dev_specs->rss_ind_tbl_size)
2703 dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE;
2704 if (!dev_specs->rss_key_size)
2705 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE;
2706 if (!dev_specs->max_int_gl)
2707 dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL;
2708 if (!dev_specs->max_frm_size)
2709 dev_specs->max_frm_size = HCLGEVF_MAC_MAX_FRAME;
2710 }
2711
hclgevf_query_dev_specs(struct hclgevf_dev * hdev)2712 static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev)
2713 {
2714 struct hclge_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM];
2715 int ret;
2716 int i;
2717
2718 /* set default specifications as devices lower than version V3 do not
2719 * support querying specifications from firmware.
2720 */
2721 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) {
2722 hclgevf_set_default_dev_specs(hdev);
2723 return 0;
2724 }
2725
2726 for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
2727 hclgevf_cmd_setup_basic_desc(&desc[i],
2728 HCLGE_OPC_QUERY_DEV_SPECS, true);
2729 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2730 }
2731 hclgevf_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true);
2732
2733 ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM);
2734 if (ret)
2735 return ret;
2736
2737 hclgevf_parse_dev_specs(hdev, desc);
2738 hclgevf_check_dev_specs(hdev);
2739
2740 return 0;
2741 }
2742
hclgevf_pci_reset(struct hclgevf_dev * hdev)2743 static int hclgevf_pci_reset(struct hclgevf_dev *hdev)
2744 {
2745 struct pci_dev *pdev = hdev->pdev;
2746 int ret = 0;
2747
2748 if ((hdev->reset_type == HNAE3_VF_FULL_RESET ||
2749 hdev->reset_type == HNAE3_FLR_RESET) &&
2750 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
2751 hclgevf_misc_irq_uninit(hdev);
2752 hclgevf_uninit_msi(hdev);
2753 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
2754 }
2755
2756 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
2757 pci_set_master(pdev);
2758 ret = hclgevf_init_msi(hdev);
2759 if (ret) {
2760 dev_err(&pdev->dev,
2761 "failed(%d) to init MSI/MSI-X\n", ret);
2762 return ret;
2763 }
2764
2765 ret = hclgevf_misc_irq_init(hdev);
2766 if (ret) {
2767 hclgevf_uninit_msi(hdev);
2768 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n",
2769 ret);
2770 return ret;
2771 }
2772
2773 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
2774 }
2775
2776 return ret;
2777 }
2778
hclgevf_clear_vport_list(struct hclgevf_dev * hdev)2779 static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev)
2780 {
2781 struct hclge_vf_to_pf_msg send_msg;
2782
2783 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL,
2784 HCLGE_MBX_VPORT_LIST_CLEAR);
2785 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
2786 }
2787
hclgevf_init_rxd_adv_layout(struct hclgevf_dev * hdev)2788 static void hclgevf_init_rxd_adv_layout(struct hclgevf_dev *hdev)
2789 {
2790 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev))
2791 hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 1);
2792 }
2793
hclgevf_uninit_rxd_adv_layout(struct hclgevf_dev * hdev)2794 static void hclgevf_uninit_rxd_adv_layout(struct hclgevf_dev *hdev)
2795 {
2796 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev))
2797 hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 0);
2798 }
2799
hclgevf_reset_hdev(struct hclgevf_dev * hdev)2800 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev)
2801 {
2802 struct pci_dev *pdev = hdev->pdev;
2803 int ret;
2804
2805 ret = hclgevf_pci_reset(hdev);
2806 if (ret) {
2807 dev_err(&pdev->dev, "pci reset failed %d\n", ret);
2808 return ret;
2809 }
2810
2811 hclgevf_arq_init(hdev);
2812 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw,
2813 &hdev->fw_version, false,
2814 hdev->reset_pending);
2815 if (ret) {
2816 dev_err(&pdev->dev, "cmd failed %d\n", ret);
2817 return ret;
2818 }
2819
2820 ret = hclgevf_rss_init_hw(hdev);
2821 if (ret) {
2822 dev_err(&hdev->pdev->dev,
2823 "failed(%d) to initialize RSS\n", ret);
2824 return ret;
2825 }
2826
2827 ret = hclgevf_config_gro(hdev);
2828 if (ret)
2829 return ret;
2830
2831 ret = hclgevf_init_vlan_config(hdev, hdev->rxvtag_strip_en);
2832 if (ret) {
2833 dev_err(&hdev->pdev->dev,
2834 "failed(%d) to initialize VLAN config\n", ret);
2835 return ret;
2836 }
2837
2838 /* get current port based vlan state from PF */
2839 ret = hclgevf_get_port_base_vlan_filter_state(hdev);
2840 if (ret)
2841 return ret;
2842
2843 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
2844
2845 hclgevf_init_rxd_adv_layout(hdev);
2846
2847 dev_info(&hdev->pdev->dev, "Reset done\n");
2848
2849 return 0;
2850 }
2851
hclgevf_init_hdev(struct hclgevf_dev * hdev)2852 static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
2853 {
2854 struct pci_dev *pdev = hdev->pdev;
2855 int ret;
2856
2857 ret = hclgevf_pci_init(hdev);
2858 if (ret)
2859 return ret;
2860
2861 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw);
2862 if (ret)
2863 goto err_cmd_queue_init;
2864
2865 hclgevf_arq_init(hdev);
2866 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw,
2867 &hdev->fw_version, false,
2868 hdev->reset_pending);
2869 if (ret)
2870 goto err_cmd_init;
2871
2872 /* Get vf resource */
2873 ret = hclgevf_query_vf_resource(hdev);
2874 if (ret)
2875 goto err_cmd_init;
2876
2877 ret = hclgevf_query_dev_specs(hdev);
2878 if (ret) {
2879 dev_err(&pdev->dev,
2880 "failed to query dev specifications, ret = %d\n", ret);
2881 goto err_cmd_init;
2882 }
2883
2884 ret = hclgevf_init_msi(hdev);
2885 if (ret) {
2886 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret);
2887 goto err_cmd_init;
2888 }
2889
2890 hclgevf_state_init(hdev);
2891 hdev->reset_level = HNAE3_VF_FUNC_RESET;
2892 hdev->reset_type = HNAE3_NONE_RESET;
2893
2894 ret = hclgevf_misc_irq_init(hdev);
2895 if (ret)
2896 goto err_misc_irq_init;
2897
2898 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
2899
2900 ret = hclgevf_configure(hdev);
2901 if (ret) {
2902 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret);
2903 goto err_config;
2904 }
2905
2906 ret = hclgevf_alloc_tqps(hdev);
2907 if (ret) {
2908 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret);
2909 goto err_config;
2910 }
2911
2912 ret = hclgevf_set_handle_info(hdev);
2913 if (ret)
2914 goto err_config;
2915
2916 ret = hclgevf_config_gro(hdev);
2917 if (ret)
2918 goto err_config;
2919
2920 /* Initialize RSS for this VF */
2921 ret = hclge_comm_rss_init_cfg(&hdev->nic, hdev->ae_dev,
2922 &hdev->rss_cfg);
2923 if (ret) {
2924 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret);
2925 goto err_config;
2926 }
2927
2928 ret = hclgevf_rss_init_hw(hdev);
2929 if (ret) {
2930 dev_err(&hdev->pdev->dev,
2931 "failed(%d) to initialize RSS\n", ret);
2932 goto err_config;
2933 }
2934
2935 /* ensure vf tbl list as empty before init */
2936 ret = hclgevf_clear_vport_list(hdev);
2937 if (ret) {
2938 dev_err(&pdev->dev,
2939 "failed to clear tbl list configuration, ret = %d.\n",
2940 ret);
2941 goto err_config;
2942 }
2943
2944 ret = hclgevf_init_vlan_config(hdev, true);
2945 if (ret) {
2946 dev_err(&hdev->pdev->dev,
2947 "failed(%d) to initialize VLAN config\n", ret);
2948 goto err_config;
2949 }
2950
2951 hclgevf_init_rxd_adv_layout(hdev);
2952
2953 ret = hclgevf_devlink_init(hdev);
2954 if (ret)
2955 goto err_config;
2956
2957 set_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state);
2958
2959 hdev->last_reset_time = jiffies;
2960 dev_info(&hdev->pdev->dev, "finished initializing %s driver\n",
2961 HCLGEVF_DRIVER_NAME);
2962
2963 hclgevf_task_schedule(hdev, round_jiffies_relative(HZ));
2964 timer_setup(&hdev->reset_timer, hclgevf_reset_timer, 0);
2965
2966 return 0;
2967
2968 err_config:
2969 hclgevf_misc_irq_uninit(hdev);
2970 err_misc_irq_init:
2971 hclgevf_state_uninit(hdev);
2972 hclgevf_uninit_msi(hdev);
2973 err_cmd_init:
2974 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw);
2975 err_cmd_queue_init:
2976 hclgevf_pci_uninit(hdev);
2977 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
2978 return ret;
2979 }
2980
hclgevf_uninit_hdev(struct hclgevf_dev * hdev)2981 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev)
2982 {
2983 struct hclge_vf_to_pf_msg send_msg;
2984
2985 hclgevf_state_uninit(hdev);
2986 hclgevf_uninit_rxd_adv_layout(hdev);
2987
2988 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0);
2989 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
2990
2991 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
2992 hclgevf_misc_irq_uninit(hdev);
2993 hclgevf_uninit_msi(hdev);
2994 }
2995
2996 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw);
2997 hclgevf_devlink_uninit(hdev);
2998 hclgevf_pci_uninit(hdev);
2999 hclgevf_uninit_mac_list(hdev);
3000 }
3001
hclgevf_init_ae_dev(struct hnae3_ae_dev * ae_dev)3002 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev)
3003 {
3004 struct pci_dev *pdev = ae_dev->pdev;
3005 int ret;
3006
3007 ret = hclgevf_alloc_hdev(ae_dev);
3008 if (ret) {
3009 dev_err(&pdev->dev, "hclge device allocation failed\n");
3010 return ret;
3011 }
3012
3013 ret = hclgevf_init_hdev(ae_dev->priv);
3014 if (ret) {
3015 dev_err(&pdev->dev, "hclge device initialization failed\n");
3016 return ret;
3017 }
3018
3019 return 0;
3020 }
3021
hclgevf_uninit_ae_dev(struct hnae3_ae_dev * ae_dev)3022 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
3023 {
3024 struct hclgevf_dev *hdev = ae_dev->priv;
3025
3026 hclgevf_uninit_hdev(hdev);
3027 ae_dev->priv = NULL;
3028 }
3029
hclgevf_get_max_channels(struct hclgevf_dev * hdev)3030 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev)
3031 {
3032 struct hnae3_handle *nic = &hdev->nic;
3033 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
3034
3035 return min_t(u32, hdev->rss_size_max,
3036 hdev->num_tqps / kinfo->tc_info.num_tc);
3037 }
3038
3039 /**
3040 * hclgevf_get_channels - Get the current channels enabled and max supported.
3041 * @handle: hardware information for network interface
3042 * @ch: ethtool channels structure
3043 *
3044 * We don't support separate tx and rx queues as channels. The other count
3045 * represents how many queues are being used for control. max_combined counts
3046 * how many queue pairs we can support. They may not be mapped 1 to 1 with
3047 * q_vectors since we support a lot more queue pairs than q_vectors.
3048 **/
hclgevf_get_channels(struct hnae3_handle * handle,struct ethtool_channels * ch)3049 static void hclgevf_get_channels(struct hnae3_handle *handle,
3050 struct ethtool_channels *ch)
3051 {
3052 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3053
3054 ch->max_combined = hclgevf_get_max_channels(hdev);
3055 ch->other_count = 0;
3056 ch->max_other = 0;
3057 ch->combined_count = handle->kinfo.rss_size;
3058 }
3059
hclgevf_get_tqps_and_rss_info(struct hnae3_handle * handle,u16 * alloc_tqps,u16 * max_rss_size)3060 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle,
3061 u16 *alloc_tqps, u16 *max_rss_size)
3062 {
3063 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3064
3065 *alloc_tqps = hdev->num_tqps;
3066 *max_rss_size = hdev->rss_size_max;
3067 }
3068
hclgevf_update_rss_size(struct hnae3_handle * handle,u32 new_tqps_num)3069 static void hclgevf_update_rss_size(struct hnae3_handle *handle,
3070 u32 new_tqps_num)
3071 {
3072 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3073 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3074 u16 max_rss_size;
3075
3076 kinfo->req_rss_size = new_tqps_num;
3077
3078 max_rss_size = min_t(u16, hdev->rss_size_max,
3079 hdev->num_tqps / kinfo->tc_info.num_tc);
3080
3081 /* Use the user's configuration when it is not larger than
3082 * max_rss_size, otherwise, use the maximum specification value.
3083 */
3084 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size &&
3085 kinfo->req_rss_size <= max_rss_size)
3086 kinfo->rss_size = kinfo->req_rss_size;
3087 else if (kinfo->rss_size > max_rss_size ||
3088 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size))
3089 kinfo->rss_size = max_rss_size;
3090
3091 kinfo->num_tqps = kinfo->tc_info.num_tc * kinfo->rss_size;
3092 }
3093
hclgevf_set_channels(struct hnae3_handle * handle,u32 new_tqps_num,bool rxfh_configured)3094 static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num,
3095 bool rxfh_configured)
3096 {
3097 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3098 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3099 u16 tc_offset[HCLGE_COMM_MAX_TC_NUM];
3100 u16 tc_valid[HCLGE_COMM_MAX_TC_NUM];
3101 u16 tc_size[HCLGE_COMM_MAX_TC_NUM];
3102 u16 cur_rss_size = kinfo->rss_size;
3103 u16 cur_tqps = kinfo->num_tqps;
3104 u32 *rss_indir;
3105 unsigned int i;
3106 int ret;
3107
3108 hclgevf_update_rss_size(handle, new_tqps_num);
3109
3110 hclge_comm_get_rss_tc_info(kinfo->rss_size, hdev->hw_tc_map,
3111 tc_offset, tc_valid, tc_size);
3112 ret = hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset,
3113 tc_valid, tc_size);
3114 if (ret)
3115 return ret;
3116
3117 /* RSS indirection table has been configured by user */
3118 if (rxfh_configured)
3119 goto out;
3120
3121 /* Reinitializes the rss indirect table according to the new RSS size */
3122 rss_indir = kcalloc(hdev->ae_dev->dev_specs.rss_ind_tbl_size,
3123 sizeof(u32), GFP_KERNEL);
3124 if (!rss_indir)
3125 return -ENOMEM;
3126
3127 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++)
3128 rss_indir[i] = i % kinfo->rss_size;
3129
3130 hdev->rss_cfg.rss_size = kinfo->rss_size;
3131
3132 ret = hclgevf_set_rss(handle, rss_indir, NULL, 0);
3133 if (ret)
3134 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
3135 ret);
3136
3137 kfree(rss_indir);
3138
3139 out:
3140 if (!ret)
3141 dev_info(&hdev->pdev->dev,
3142 "Channels changed, rss_size from %u to %u, tqps from %u to %u",
3143 cur_rss_size, kinfo->rss_size,
3144 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc);
3145
3146 return ret;
3147 }
3148
hclgevf_get_status(struct hnae3_handle * handle)3149 static int hclgevf_get_status(struct hnae3_handle *handle)
3150 {
3151 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3152
3153 return hdev->hw.mac.link;
3154 }
3155
hclgevf_get_ksettings_an_result(struct hnae3_handle * handle,u8 * auto_neg,u32 * speed,u8 * duplex,u32 * lane_num)3156 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle,
3157 u8 *auto_neg, u32 *speed,
3158 u8 *duplex, u32 *lane_num)
3159 {
3160 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3161
3162 if (speed)
3163 *speed = hdev->hw.mac.speed;
3164 if (duplex)
3165 *duplex = hdev->hw.mac.duplex;
3166 if (auto_neg)
3167 *auto_neg = AUTONEG_DISABLE;
3168 }
3169
hclgevf_update_speed_duplex(struct hclgevf_dev * hdev,u32 speed,u8 duplex)3170 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
3171 u8 duplex)
3172 {
3173 hdev->hw.mac.speed = speed;
3174 hdev->hw.mac.duplex = duplex;
3175 }
3176
hclgevf_gro_en(struct hnae3_handle * handle,bool enable)3177 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable)
3178 {
3179 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3180 bool gro_en_old = hdev->gro_en;
3181 int ret;
3182
3183 hdev->gro_en = enable;
3184 ret = hclgevf_config_gro(hdev);
3185 if (ret)
3186 hdev->gro_en = gro_en_old;
3187
3188 return ret;
3189 }
3190
hclgevf_get_media_type(struct hnae3_handle * handle,u8 * media_type,u8 * module_type)3191 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type,
3192 u8 *module_type)
3193 {
3194 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3195
3196 if (media_type)
3197 *media_type = hdev->hw.mac.media_type;
3198
3199 if (module_type)
3200 *module_type = hdev->hw.mac.module_type;
3201 }
3202
hclgevf_get_hw_reset_stat(struct hnae3_handle * handle)3203 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle)
3204 {
3205 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3206
3207 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
3208 }
3209
hclgevf_get_cmdq_stat(struct hnae3_handle * handle)3210 static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle)
3211 {
3212 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3213
3214 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
3215 }
3216
hclgevf_ae_dev_resetting(struct hnae3_handle * handle)3217 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle)
3218 {
3219 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3220
3221 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
3222 }
3223
hclgevf_ae_dev_reset_cnt(struct hnae3_handle * handle)3224 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle)
3225 {
3226 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3227
3228 return hdev->rst_stats.hw_rst_done_cnt;
3229 }
3230
hclgevf_get_link_mode(struct hnae3_handle * handle,unsigned long * supported,unsigned long * advertising)3231 static void hclgevf_get_link_mode(struct hnae3_handle *handle,
3232 unsigned long *supported,
3233 unsigned long *advertising)
3234 {
3235 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3236
3237 *supported = hdev->hw.mac.supported;
3238 *advertising = hdev->hw.mac.advertising;
3239 }
3240
hclgevf_update_port_base_vlan_info(struct hclgevf_dev * hdev,u16 state,struct hclge_mbx_port_base_vlan * port_base_vlan)3241 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state,
3242 struct hclge_mbx_port_base_vlan *port_base_vlan)
3243 {
3244 struct hnae3_handle *nic = &hdev->nic;
3245 struct hclge_vf_to_pf_msg send_msg;
3246 int ret;
3247
3248 rtnl_lock();
3249
3250 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||
3251 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) {
3252 dev_warn(&hdev->pdev->dev,
3253 "is resetting when updating port based vlan info\n");
3254 rtnl_unlock();
3255 return;
3256 }
3257
3258 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
3259 if (ret) {
3260 rtnl_unlock();
3261 return;
3262 }
3263
3264 /* send msg to PF and wait update port based vlan info */
3265 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
3266 HCLGE_MBX_PORT_BASE_VLAN_CFG);
3267 memcpy(send_msg.data, port_base_vlan, sizeof(*port_base_vlan));
3268 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
3269 if (!ret) {
3270 if (state == HNAE3_PORT_BASE_VLAN_DISABLE)
3271 nic->port_base_vlan_state = state;
3272 else
3273 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE;
3274 }
3275
3276 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
3277 rtnl_unlock();
3278 }
3279
3280 static const struct hnae3_ae_ops hclgevf_ops = {
3281 .init_ae_dev = hclgevf_init_ae_dev,
3282 .uninit_ae_dev = hclgevf_uninit_ae_dev,
3283 .reset_prepare = hclgevf_reset_prepare_general,
3284 .reset_done = hclgevf_reset_done,
3285 .init_client_instance = hclgevf_init_client_instance,
3286 .uninit_client_instance = hclgevf_uninit_client_instance,
3287 .start = hclgevf_ae_start,
3288 .stop = hclgevf_ae_stop,
3289 .client_start = hclgevf_client_start,
3290 .client_stop = hclgevf_client_stop,
3291 .map_ring_to_vector = hclgevf_map_ring_to_vector,
3292 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector,
3293 .get_vector = hclgevf_get_vector,
3294 .put_vector = hclgevf_put_vector,
3295 .reset_queue = hclgevf_reset_tqp,
3296 .get_mac_addr = hclgevf_get_mac_addr,
3297 .set_mac_addr = hclgevf_set_mac_addr,
3298 .add_uc_addr = hclgevf_add_uc_addr,
3299 .rm_uc_addr = hclgevf_rm_uc_addr,
3300 .add_mc_addr = hclgevf_add_mc_addr,
3301 .rm_mc_addr = hclgevf_rm_mc_addr,
3302 .get_stats = hclgevf_get_stats,
3303 .update_stats = hclgevf_update_stats,
3304 .get_strings = hclgevf_get_strings,
3305 .get_sset_count = hclgevf_get_sset_count,
3306 .get_rss_key_size = hclge_comm_get_rss_key_size,
3307 .get_rss = hclgevf_get_rss,
3308 .set_rss = hclgevf_set_rss,
3309 .get_rss_tuple = hclgevf_get_rss_tuple,
3310 .set_rss_tuple = hclgevf_set_rss_tuple,
3311 .get_tc_size = hclgevf_get_tc_size,
3312 .get_fw_version = hclgevf_get_fw_version,
3313 .set_vlan_filter = hclgevf_set_vlan_filter,
3314 .enable_vlan_filter = hclgevf_enable_vlan_filter,
3315 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag,
3316 .reset_event = hclgevf_reset_event,
3317 .set_default_reset_request = hclgevf_set_def_reset_request,
3318 .set_channels = hclgevf_set_channels,
3319 .get_channels = hclgevf_get_channels,
3320 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info,
3321 .get_regs_len = hclgevf_get_regs_len,
3322 .get_regs = hclgevf_get_regs,
3323 .get_status = hclgevf_get_status,
3324 .get_ksettings_an_result = hclgevf_get_ksettings_an_result,
3325 .get_media_type = hclgevf_get_media_type,
3326 .get_hw_reset_stat = hclgevf_get_hw_reset_stat,
3327 .ae_dev_resetting = hclgevf_ae_dev_resetting,
3328 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt,
3329 .set_gro_en = hclgevf_gro_en,
3330 .set_mtu = hclgevf_set_mtu,
3331 .get_global_queue_id = hclgevf_get_qid_global,
3332 .set_timer_task = hclgevf_set_timer_task,
3333 .get_link_mode = hclgevf_get_link_mode,
3334 .set_promisc_mode = hclgevf_set_promisc_mode,
3335 .request_update_promisc_mode = hclgevf_request_update_promisc_mode,
3336 .get_cmdq_stat = hclgevf_get_cmdq_stat,
3337 };
3338
3339 static struct hnae3_ae_algo ae_algovf = {
3340 .ops = &hclgevf_ops,
3341 .pdev_id_table = ae_algovf_pci_tbl,
3342 };
3343
hclgevf_init(void)3344 static int __init hclgevf_init(void)
3345 {
3346 pr_info("%s is initializing\n", HCLGEVF_NAME);
3347
3348 hclgevf_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGEVF_NAME);
3349 if (!hclgevf_wq) {
3350 pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME);
3351 return -ENOMEM;
3352 }
3353
3354 hnae3_register_ae_algo(&ae_algovf);
3355
3356 return 0;
3357 }
3358
hclgevf_exit(void)3359 static void __exit hclgevf_exit(void)
3360 {
3361 hnae3_acquire_unload_lock();
3362 hnae3_unregister_ae_algo(&ae_algovf);
3363 destroy_workqueue(hclgevf_wq);
3364 hnae3_release_unload_lock();
3365 }
3366 module_init(hclgevf_init);
3367 module_exit(hclgevf_exit);
3368
3369 MODULE_LICENSE("GPL");
3370 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
3371 MODULE_DESCRIPTION("HCLGEVF Driver");
3372 MODULE_VERSION(HCLGEVF_MOD_VERSION);
3373